1 /*
2 * Copyright (c) 2024, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_TDM_H__
35 #define NRF_TDM_H__
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 #if defined(HALTIUM_XXAA)
44 #define NRF_TDM_CLOCKPIN_SCK_NEEDED 1
45 #define NRF_TDM_CLOCKPIN_FSYNC_NEEDED 1
46 #define NRF_TDM_CLOCKPIN_MCK_NEEDED 1
47 #endif
48
49 /**
50 * @defgroup nrf_tdm_hal TDM HAL
51 * @{
52 * @ingroup nrf_tdm
53 * @brief Hardware access layer for managing the Time Division Multiplexed Audio Interface
54 * (TDM) peripheral.
55 */
56
57 /**
58 * @brief This value can be provided as a parameter for the @ref nrf_tdm_pins_set
59 * function call to specify that the given TDM signal (SDOUT, SDIN, or MCK)
60 * shall not be connected to a physical pin.
61 */
62 #define NRF_TDM_PIN_NOT_CONNECTED 0xFFFFFFFF
63
64 /** @brief TDM tasks. */
65 typedef enum
66 {
67 NRF_TDM_TASK_START = offsetof(NRF_TDM_Type, TASKS_START), ///< Starts continuous TDM transfer. Also starts the MCK generator if this is enabled.
68 NRF_TDM_TASK_STOP = offsetof(NRF_TDM_Type, TASKS_STOP), ///< Stops TDM transfer after completion of MAXCNT words.
69 NRF_TDM_TASK_ABORT = offsetof(NRF_TDM_Type, TASKS_ABORT) ///< Aborts TDM transfer without completing MAXCNT words.
70 } nrf_tdm_task_t;
71
72 /** @brief TDM events. */
73 typedef enum
74 {
75 NRF_TDM_EVENT_RXPTRUPD = offsetof(NRF_TDM_Type, EVENTS_RXPTRUPD), ///< The RXD.PTR register has been copied to internal double buffers.
76 NRF_TDM_EVENT_STOPPED = offsetof(NRF_TDM_Type, EVENTS_STOPPED), ///< TDM transfer stopped.
77 NRF_TDM_EVENT_ABORTED = offsetof(NRF_TDM_Type, EVENTS_ABORTED), ///< TDM transfer aborted.
78 NRF_TDM_EVENT_TXPTRUPD = offsetof(NRF_TDM_Type, EVENTS_TXPTRUPD), ///< The TXD.PTR register has been copied to internal double buffers.
79 NRF_TDM_EVENT_MAXCNT = offsetof(NRF_TDM_Type, EVENTS_MAXCNT), ///< MAXCNT block event, generated on the active edge of FSYNC of every MAXCNT block.
80 } nrf_tdm_event_t;
81
82 /** @brief TDM interrupts. */
83 typedef enum
84 {
85 NRF_TDM_INT_RXPTRUPD_MASK_MASK = TDM_INTENSET_RXPTRUPD_Msk, ///< Interrupt on RXPTRUPD event.
86 NRF_TDM_INT_STOPPED_MASK_MASK = TDM_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event.
87 NRF_TDM_INT_ABORTED_MASK = TDM_INTENSET_ABORTED_Msk, ///< Interrupt on EVENTS_ABORTED event.
88 NRF_TDM_INT_TXPTRUPD_MASK_MASK = TDM_INTENSET_TXPTRUPD_Msk, ///< Interrupt on TXPTRUPD event.
89 NRF_TDM_INT_MAXCNT_MASK = TDM_INTENSET_MAXCNT_Msk, ///< Interrupt on EVENTS_MAXCNT event.
90 } nrf_tdm_int_mask_t;
91
92 /** @brief TDM modes of operation. */
93 typedef enum
94 {
95 NRF_TDM_MODE_MASTER = TDM_CONFIG_MODE_MODE_Master, ///< Master mode.
96 NRF_TDM_MODE_SLAVE = TDM_CONFIG_MODE_MODE_Slave ///< Slave mode.
97 } nrf_tdm_mode_t;
98
99 /** @brief TDM Reception and transmission settings. */
100 typedef enum
101 {
102 NRF_TDM_RXTXEN_DUPLEX = TDM_CONFIG_RXTXEN_RXTXEN_Duplex, ///< Enable reception and transmission.
103 NRF_TDM_RXTXEN_RX = TDM_CONFIG_RXTXEN_RXTXEN_Rx, ///< Enable reception, disable transmission.
104 NRF_TDM_RXTXEN_TX = TDM_CONFIG_RXTXEN_RXTXEN_Tx ///< Enable transmission, disable reception.
105 } nrf_tdm_rxtxen_t;
106
107 /** @brief TDM master clock divider settings. */
108 typedef enum
109 {
110 NRF_TDM_MCK_DIV_2 = TDM_CONFIG_MCK_DIV_DIV_CKDIV2, ///< MCK divided by 2.
111 NRF_TDM_MCK_DIV_3 = TDM_CONFIG_MCK_DIV_DIV_CKDIV3, ///< MCK divided by 3.
112 NRF_TDM_MCK_DIV_4 = TDM_CONFIG_MCK_DIV_DIV_CKDIV4, ///< MCK divided by 4.
113 NRF_TDM_MCK_DIV_5 = TDM_CONFIG_MCK_DIV_DIV_CKDIV5, ///< MCK divided by 5.
114 NRF_TDM_MCK_DIV_6 = TDM_CONFIG_MCK_DIV_DIV_CKDIV6, ///< MCK divided by 6.
115 NRF_TDM_MCK_DIV_8 = TDM_CONFIG_MCK_DIV_DIV_CKDIV8, ///< MCK divided by 8.
116 NRF_TDM_MCK_DIV_10 = TDM_CONFIG_MCK_DIV_DIV_CKDIV10, ///< MCK divided by 10.
117 NRF_TDM_MCK_DIV_11 = TDM_CONFIG_MCK_DIV_DIV_CKDIV11, ///< MCK divided by 11.
118 NRF_TDM_MCK_DIV_15 = TDM_CONFIG_MCK_DIV_DIV_CKDIV15, ///< MCK divided by 15.
119 NRF_TDM_MCK_DIV_16 = TDM_CONFIG_MCK_DIV_DIV_CKDIV16, ///< MCK divided by 16.
120 NRF_TDM_MCK_DIV_21 = TDM_CONFIG_MCK_DIV_DIV_CKDIV21, ///< MCK divided by 21.
121 NRF_TDM_MCK_DIV_23 = TDM_CONFIG_MCK_DIV_DIV_CKDIV23, ///< MCK divided by 23.
122 NRF_TDM_MCK_DIV_30 = TDM_CONFIG_MCK_DIV_DIV_CKDIV30, ///< MCK divided by 30.
123 NRF_TDM_MCK_DIV_31 = TDM_CONFIG_MCK_DIV_DIV_CKDIV31, ///< MCK divided by 31.
124 NRF_TDM_MCK_DIV_32 = TDM_CONFIG_MCK_DIV_DIV_CKDIV32, ///< MCK divided by 32.
125 NRF_TDM_MCK_DIV_42 = TDM_CONFIG_MCK_DIV_DIV_CKDIV42, ///< MCK divided by 42.
126 NRF_TDM_MCK_DIV_63 = TDM_CONFIG_MCK_DIV_DIV_CKDIV63, ///< MCK divided by 63.
127 NRF_TDM_MCK_DIV_125 = TDM_CONFIG_MCK_DIV_DIV_CKDIV125 ///< MCK divided by 125.
128 } nrf_tdm_mck_div_t;
129
130 /** @brief TDM serial clock divider settings. */
131 typedef enum
132 {
133 NRF_TDM_SCK_DIV_2 = TDM_CONFIG_SCK_DIV_SCKDIV_CKDIV2, ///< SCK divided by 2.
134 NRF_TDM_SCK_DIV_3 = TDM_CONFIG_SCK_DIV_SCKDIV_CKDIV3, ///< SCK divided by 3.
135 NRF_TDM_SCK_DIV_4 = TDM_CONFIG_SCK_DIV_SCKDIV_CKDIV4, ///< SCK divided by 4.
136 NRF_TDM_SCK_DIV_5 = TDM_CONFIG_SCK_DIV_SCKDIV_CKDIV5, ///< SCK divided by 5.
137 NRF_TDM_SCK_DIV_6 = TDM_CONFIG_SCK_DIV_SCKDIV_CKDIV6, ///< SCK divided by 6.
138 NRF_TDM_SCK_DIV_8 = TDM_CONFIG_SCK_DIV_SCKDIV_CKDIV8, ///< SCK divided by 8.
139 NRF_TDM_SCK_DIV_10 = TDM_CONFIG_SCK_DIV_SCKDIV_CKDIV10, ///< SCK divided by 10.
140 NRF_TDM_SCK_DIV_11 = TDM_CONFIG_SCK_DIV_SCKDIV_CKDIV11, ///< SCK divided by 11.
141 NRF_TDM_SCK_DIV_15 = TDM_CONFIG_SCK_DIV_SCKDIV_CKDIV15, ///< SCK divided by 15.
142 NRF_TDM_SCK_DIV_16 = TDM_CONFIG_SCK_DIV_SCKDIV_CKDIV16, ///< SCK divided by 16.
143 NRF_TDM_SCK_DIV_21 = TDM_CONFIG_SCK_DIV_SCKDIV_CKDIV21, ///< SCK divided by 21.
144 NRF_TDM_SCK_DIV_23 = TDM_CONFIG_SCK_DIV_SCKDIV_CKDIV23, ///< SCK divided by 23.
145 NRF_TDM_SCK_DIV_30 = TDM_CONFIG_SCK_DIV_SCKDIV_CKDIV30, ///< SCK divided by 30.
146 NRF_TDM_SCK_DIV_31 = TDM_CONFIG_SCK_DIV_SCKDIV_CKDIV31, ///< SCK divided by 31.
147 NRF_TDM_SCK_DIV_32 = TDM_CONFIG_SCK_DIV_SCKDIV_CKDIV32, ///< SCK divided by 32.
148 NRF_TDM_SCK_DIV_42 = TDM_CONFIG_SCK_DIV_SCKDIV_CKDIV42, ///< SCK divided by 42.
149 NRF_TDM_SCK_DIV_63 = TDM_CONFIG_SCK_DIV_SCKDIV_CKDIV63, ///< SCK divided by 63.
150 NRF_TDM_SCK_DIV_125 = TDM_CONFIG_SCK_DIV_SCKDIV_CKDIV125 ///< SCK divided by 125.
151 } nrf_tdm_sck_div_t;
152
153 /** @brief TDM clock source selection. */
154 typedef enum
155 {
156 NRF_TDM_SRC_PCLK32M = TDM_CONFIG_SCK_SRC_CLKSRC_PCLK32M, ///< 32MHz peripheral clock.
157 NRF_TDM_SRC_ACLK = TDM_CONFIG_SCK_SRC_CLKSRC_ACLK ///< Audio PLL clock.
158 } nrf_tdm_src_t;
159
160 /** @brief TDM sample widths. */
161 typedef enum
162 {
163 NRF_TDM_SWIDTH_8BIT = TDM_CONFIG_SWIDTH_SWIDTH_8Bit, ///< 8 bit.
164 NRF_TDM_SWIDTH_16BIT = TDM_CONFIG_SWIDTH_SWIDTH_16Bit, ///< 16 bit.
165 NRF_TDM_SWIDTH_24BIT = TDM_CONFIG_SWIDTH_SWIDTH_24Bit, ///< 24 bit.
166 NRF_TDM_SWIDTH_32BIT = TDM_CONFIG_SWIDTH_SWIDTH_32Bit, ///< 32 bit.
167 NRF_TDM_SWIDTH_8BIT_IN16BIT = TDM_CONFIG_SWIDTH_SWIDTH_8BitIn16, ///< 8 bit sample in a 16-bit half-frame.
168 NRF_TDM_SWIDTH_8BIT_IN32BIT = TDM_CONFIG_SWIDTH_SWIDTH_8BitIn32, ///< 8 bit sample in a 32-bit half-frame.
169 NRF_TDM_SWIDTH_16BIT_IN32BIT = TDM_CONFIG_SWIDTH_SWIDTH_16BitIn32, ///< 16 bit sample in a 32-bit half-frame.
170 NRF_TDM_SWIDTH_24BIT_IN32BIT = TDM_CONFIG_SWIDTH_SWIDTH_24BitIn32, ///< 24 bit sample in a 32-bit half-frame.
171 } nrf_tdm_swidth_t;
172
173 /** @brief TDM alignments of sample within a frame. */
174 typedef enum
175 {
176 NRF_TDM_ALIGN_LEFT = TDM_CONFIG_ALIGN_ALIGN_Left, ///< Left-aligned.
177 NRF_TDM_ALIGN_RIGHT = TDM_CONFIG_ALIGN_ALIGN_Right ///< Right-aligned.
178 } nrf_tdm_align_t;
179
180 /** @brief TDM channel mask. */
181 typedef enum
182 {
183 NRF_TDM_CHANNEL_RX0_MASK = TDM_CONFIG_CHANNEL_MASK_Rx0Enable_Msk, ///< Enable RX channel 0 data.
184 NRF_TDM_CHANNEL_RX1_MASK = TDM_CONFIG_CHANNEL_MASK_Rx1Enable_Msk, ///< Enable RX channel 1 data.
185 NRF_TDM_CHANNEL_RX2_MASK = TDM_CONFIG_CHANNEL_MASK_Rx2Enable_Msk, ///< Enable RX channel 2 data.
186 NRF_TDM_CHANNEL_RX3_MASK = TDM_CONFIG_CHANNEL_MASK_Rx3Enable_Msk, ///< Enable RX channel 3 data.
187 NRF_TDM_CHANNEL_RX4_MASK = TDM_CONFIG_CHANNEL_MASK_Rx4Enable_Msk, ///< Enable RX channel 4 data.
188 NRF_TDM_CHANNEL_RX5_MASK = TDM_CONFIG_CHANNEL_MASK_Rx5Enable_Msk, ///< Enable RX channel 5 data.
189 NRF_TDM_CHANNEL_RX6_MASK = TDM_CONFIG_CHANNEL_MASK_Rx6Enable_Msk, ///< Enable RX channel 6 data.
190 NRF_TDM_CHANNEL_RX7_MASK = TDM_CONFIG_CHANNEL_MASK_Rx7Enable_Msk, ///< Enable RX channel 7 data.
191 NRF_TDM_CHANNEL_TX0_MASK = TDM_CONFIG_CHANNEL_MASK_Tx0Enable_Msk, ///< Enable TX channel 0 data.
192 NRF_TDM_CHANNEL_TX1_MASK = TDM_CONFIG_CHANNEL_MASK_Tx1Enable_Msk, ///< Enable TX channel 1 data.
193 NRF_TDM_CHANNEL_TX2_MASK = TDM_CONFIG_CHANNEL_MASK_Tx2Enable_Msk, ///< Enable TX channel 2 data.
194 NRF_TDM_CHANNEL_TX3_MASK = TDM_CONFIG_CHANNEL_MASK_Tx3Enable_Msk, ///< Enable TX channel 3 data.
195 NRF_TDM_CHANNEL_TX4_MASK = TDM_CONFIG_CHANNEL_MASK_Tx4Enable_Msk, ///< Enable TX channel 4 data.
196 NRF_TDM_CHANNEL_TX5_MASK = TDM_CONFIG_CHANNEL_MASK_Tx5Enable_Msk, ///< Enable TX channel 5 data.
197 NRF_TDM_CHANNEL_TX6_MASK = TDM_CONFIG_CHANNEL_MASK_Tx6Enable_Msk, ///< Enable TX channel 6 data.
198 NRF_TDM_CHANNEL_TX7_MASK = TDM_CONFIG_CHANNEL_MASK_Tx7Enable_Msk, ///< Enable TX channel 7 data.
199 } nrf_tdm_channel_mask_t;
200
201 /** @brief TDM number of channels. */
202 typedef enum
203 {
204 NRF_TDM_CHANNELS_COUNT_1 = TDM_CONFIG_CHANNEL_NUM_NUM_Tdm1Ch, ///< 1 channel audio (mono).
205 NRF_TDM_CHANNELS_COUNT_2 = TDM_CONFIG_CHANNEL_NUM_NUM_Tdm2Ch, ///< 2 channels audio (stereo).
206 NRF_TDM_CHANNELS_COUNT_3 = TDM_CONFIG_CHANNEL_NUM_NUM_Tdm3Ch, ///< 3 channels audio.
207 NRF_TDM_CHANNELS_COUNT_4 = TDM_CONFIG_CHANNEL_NUM_NUM_Tdm4Ch, ///< 4 channels audio.
208 NRF_TDM_CHANNELS_COUNT_5 = TDM_CONFIG_CHANNEL_NUM_NUM_Tdm5Ch, ///< 5 channels audio.
209 NRF_TDM_CHANNELS_COUNT_6 = TDM_CONFIG_CHANNEL_NUM_NUM_Tdm6Ch, ///< 6 channels audio.
210 NRF_TDM_CHANNELS_COUNT_7 = TDM_CONFIG_CHANNEL_NUM_NUM_Tdm7Ch, ///< 7 channels audio.
211 NRF_TDM_CHANNELS_COUNT_8 = TDM_CONFIG_CHANNEL_NUM_NUM_Tdm8Ch, ///< 8 channels audio.
212 } nrf_tdm_channels_count_t;
213
214 /** @brief TDM channel delay. */
215 typedef enum
216 {
217 NRF_TDM_CHANNEL_DELAY_NONE = TDM_CONFIG_CHANNEL_DELAY_DELAY_Delay0Ck, ///< No delay. Use with DSP/Aligned format.
218 NRF_TDM_CHANNEL_DELAY_1CK = TDM_CONFIG_CHANNEL_DELAY_DELAY_Delay1Ck, ///< 1 clock pulse delay. Used with original TDM format.
219 NRF_TDM_CHANNEL_DELAY_2CK = TDM_CONFIG_CHANNEL_DELAY_DELAY_Delay2Ck, ///< 2 clock pulses delay.
220 } nrf_tdm_channel_delay_t;
221
222 /** @brief TDM signal polarity. */
223 typedef enum
224 {
225 NRF_TDM_POLARITY_POSEDGE, ///< Synchronization at rising edge of the reference signal.
226 NRF_TDM_POLARITY_NEGEDGE, ///< Synchronization at falling edge of the reference signal.
227 } nrf_tdm_polarity_t;
228
229 /** @brief TDM frame synchronization pulse duration. */
230 typedef enum
231 {
232 NRF_TDM_FSYNC_DURATION_SCK = TDM_CONFIG_FSYNC_DURATION_DURATION_Sck, ///< FSYNC is active for the duration of one SCK pulse.
233 NRF_TDM_FSYNC_DURATION_CHANNEL = TDM_CONFIG_FSYNC_DURATION_DURATION_Channel ///< FSYNC is active for the duration of channel transmission.
234 } nrf_tdm_fsync_duration_t;
235
236 /** @brief TDM configuration. */
237 typedef struct
238 {
239 nrf_tdm_mode_t mode; /**< Mode of operation (master or slave). */
240 nrf_tdm_align_t alignment; /**< Alignment of sample within a frame. */
241 nrf_tdm_swidth_t sample_width; /**< Sample width. */
242 nrf_tdm_channel_mask_t channels; /**< Enabled channels. */
243 nrf_tdm_channels_count_t num_of_channels; /**< Nnumber of channels within a frame. */
244 nrf_tdm_channel_delay_t channel_delay; /**< Channel delay settings. */
245 nrf_tdm_mck_div_t mck_setup; /**< Master clock divider setup. */
246 nrf_tdm_sck_div_t sck_setup; /**< Serial clock divider setup. */
247 nrf_tdm_polarity_t sck_polarity; /**< Serial clock polarity. */
248 nrf_tdm_polarity_t fsync_polarity; /**< Frame Synchronization pulse polarity. */
249 nrf_tdm_fsync_duration_t fsync_duration; /**< Frame Synchronization pulse duration. */
250 } nrf_tdm_config_t;
251
252 /** @brief TDM pins. */
253 typedef struct
254 {
255 uint32_t sck_pin; ///< SCK pin number.
256 uint32_t fsync_pin; ///< FSYNC pin number.
257 uint32_t mck_pin; ///< MCK pin number.
258 /**< Optional. Use @ref NRF_TDM_PIN_NOT_CONNECTED
259 * if this signal is not needed. */
260 uint32_t sdout_pin; ///< SDOUT pin number.
261 /**< Optional. Use @ref NRF_TDM_PIN_NOT_CONNECTED
262 * if this signal is not needed. */
263 uint32_t sdin_pin; ///< SDIN pin number.
264 /**< Optional. Use @ref NRF_TDM_PIN_NOT_CONNECTED
265 * if this signal is not needed. */
266 } nrf_tdm_pins_t;
267
268 /**
269 * @brief Function for activating the specified TDM task.
270 *
271 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
272 * @param[in] task Task to be activated.
273 */
274 NRF_STATIC_INLINE void nrf_tdm_task_trigger(NRF_TDM_Type * p_reg,
275 nrf_tdm_task_t task);
276
277 /**
278 * @brief Function for getting the address of the specified TDM task register.
279 *
280 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
281 * @param[in] task Specified task.
282 *
283 * @return Address of the specified task register.
284 */
285 NRF_STATIC_INLINE uint32_t nrf_tdm_task_address_get(NRF_TDM_Type const * p_reg,
286 nrf_tdm_task_t task);
287
288 /**
289 * @brief Function for clearing the specified TDM event.
290 *
291 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
292 * @param[in] event Event to clear.
293 */
294 NRF_STATIC_INLINE void nrf_tdm_event_clear(NRF_TDM_Type * p_reg,
295 nrf_tdm_event_t event);
296
297 /**
298 * @brief Function for retrieving the state of the TDM event.
299 *
300 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
301 * @param[in] event Event to be checked.
302 *
303 * @retval true The event has been generated.
304 * @retval false The event has not been generated.
305 */
306 NRF_STATIC_INLINE bool nrf_tdm_event_check(NRF_TDM_Type const * p_reg,
307 nrf_tdm_event_t event);
308
309 /**
310 * @brief Function for getting the address of the specified TDM event register.
311 *
312 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
313 * @param[in] event Specified event.
314 *
315 * @return Address of the specified event register.
316 */
317 NRF_STATIC_INLINE uint32_t nrf_tdm_event_address_get(NRF_TDM_Type const * p_reg,
318 nrf_tdm_event_t event);
319
320 /**
321 * @brief Function for enabling specified interrupts.
322 *
323 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
324 * @param[in] mask Mask of interrupts to be enabled.
325 * Use @ref nrf_tdm_int_mask_t values for bit masking.
326 */
327 NRF_STATIC_INLINE void nrf_tdm_int_enable(NRF_TDM_Type * p_reg, uint32_t mask);
328
329 /**
330 * @brief Function for disabling specified interrupts.
331 *
332 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
333 * @param[in] mask Mask of interrupts to be disabled.
334 * Use @ref nrf_tdm_int_mask_t values for bit masking.
335 */
336 NRF_STATIC_INLINE void nrf_tdm_int_disable(NRF_TDM_Type * p_reg, uint32_t mask);
337
338 /**
339 * @brief Function for checking if the specified interrupts are enabled.
340 *
341 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
342 * @param[in] mask Mask of interrupts to be checked.
343 * Use @ref nrf_tdm_int_mask_t values for bit masking.
344 *
345 * @return Mask of enabled interrupts.
346 */
347 NRF_STATIC_INLINE uint32_t nrf_tdm_int_enable_check(NRF_TDM_Type const * p_reg, uint32_t mask);
348
349 /**
350 * @brief Function for enabling the TDM peripheral.
351 *
352 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
353 */
354 NRF_STATIC_INLINE void nrf_tdm_enable(NRF_TDM_Type * p_reg);
355
356 /**
357 * @brief Function for disabling the TDM peripheral.
358 *
359 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
360 */
361 NRF_STATIC_INLINE void nrf_tdm_disable(NRF_TDM_Type * p_reg);
362
363 /**
364 * @brief Function for checking if the TDM peripheral is enabled.
365 *
366 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
367 *
368 * @retval true The TDM is enabled.
369 * @retval false The TDM is not enabled.
370 */
371 NRF_STATIC_INLINE bool nrf_tdm_enable_check(NRF_TDM_Type * p_reg);
372
373 #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
374 /**
375 * @brief Function for setting the subscribe configuration for a given
376 * TDM task.
377 *
378 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
379 * @param[in] task Task for which to set the configuration.
380 * @param[in] channel Channel through which to subscribe events.
381 */
382 NRF_STATIC_INLINE void nrf_tdm_subscribe_set(NRF_TDM_Type * p_reg,
383 nrf_tdm_task_t task,
384 uint8_t channel);
385
386 /**
387 * @brief Function for clearing the subscribe configuration for a given
388 * TDM task.
389 *
390 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
391 * @param[in] task Task for which to clear the configuration.
392 */
393 NRF_STATIC_INLINE void nrf_tdm_subscribe_clear(NRF_TDM_Type * p_reg,
394 nrf_tdm_task_t task);
395
396 /**
397 * @brief Function for setting the publish configuration for a given
398 * TDM event.
399 *
400 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
401 * @param[in] event Event for which to set the configuration.
402 * @param[in] channel Channel through which to publish the event.
403 */
404 NRF_STATIC_INLINE void nrf_tdm_publish_set(NRF_TDM_Type * p_reg,
405 nrf_tdm_event_t event,
406 uint8_t channel);
407
408 /**
409 * @brief Function for clearing the publish configuration for a given
410 * TDM event.
411 *
412 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
413 * @param[in] event Event for which to clear the configuration.
414 */
415 NRF_STATIC_INLINE void nrf_tdm_publish_clear(NRF_TDM_Type * p_reg,
416 nrf_tdm_event_t event);
417 #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
418
419 /**
420 * @brief Function for configuring TDM pins.
421 *
422 * Usage of the SDOUT, SDIN, and MCK signals is optional.
423 * If a given signal is not needed, pass the @ref NRF_TDM_PIN_NOT_CONNECTED
424 * value instead of its pin number.
425 *
426 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
427 * @param[in] p_pins Pointer to the structure with pins selection.
428 */
429 NRF_STATIC_INLINE void nrf_tdm_pins_set(NRF_TDM_Type * p_reg, nrf_tdm_pins_t const * p_pins);
430
431 /**
432 * @brief Function for getting the SCK pin selection.
433 *
434 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
435 *
436 * @return SCK pin selection.
437 */
438 NRF_STATIC_INLINE uint32_t nrf_tdm_sck_pin_get(NRF_TDM_Type const * p_reg);
439
440 /**
441 * @brief Function for getting the FSYNC pin selection.
442 *
443 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
444 *
445 * @return FSYNC pin selection.
446 */
447 NRF_STATIC_INLINE uint32_t nrf_tdm_fsync_pin_get(NRF_TDM_Type const * p_reg);
448
449 /**
450 * @brief Function for getting the MCK pin selection.
451 *
452 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
453 *
454 * @return MCK pin selection.
455 */
456 NRF_STATIC_INLINE uint32_t nrf_tdm_mck_pin_get(NRF_TDM_Type const * p_reg);
457
458 /**
459 * @brief Function for getting the SDOUT pin selection.
460 *
461 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
462 *
463 * @return SDOUT pin selection.
464 */
465 NRF_STATIC_INLINE uint32_t nrf_tdm_sdout_pin_get(NRF_TDM_Type const * p_reg);
466
467 /**
468 * @brief Function for getting the SDIN pin selection.
469 *
470 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
471 *
472 * @return SDIN pin selection.
473 */
474 NRF_STATIC_INLINE uint32_t nrf_tdm_sdin_pin_get(NRF_TDM_Type const * p_reg);
475
476 /**
477 * @brief Function for setting the TDM peripheral configuration.
478 *
479 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
480 * @param[in] p_config Pointer to the structure with configuration.
481 */
482 NRF_STATIC_INLINE void nrf_tdm_configure(NRF_TDM_Type * p_reg, nrf_tdm_config_t const * p_config);
483
484 /**
485 * @brief Function for setting the master clock generator.
486 *
487 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
488 * @param[in] enable True if the master clock generator is to be enabled, false otherwise.
489 */
490 NRF_STATIC_INLINE void nrf_tdm_mck_set(NRF_TDM_Type * p_reg, bool enable);
491
492 /**
493 * @brief Function for setting up the TDM RX transfer length.
494 *
495 * @note This function sets up the RX buffer size. At least one of
496 * @ref nrf_tdm_rx_count_set or @ref nrf_tdm_tx_count_set functions must be called
497 * before starting the transmission. Also @ref nrf_tdm_transfer_direction_set and
498 * @ref nrf_tdm_rx_buffer_set should be called before starting the transmission.
499 *
500 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
501 * @param[in] size Size of the buffer (in 32-bit words).
502 */
503 NRF_STATIC_INLINE void nrf_tdm_rx_count_set(NRF_TDM_Type * p_reg,
504 uint16_t size);
505
506 /**
507 * @brief Function for setting up the TDM TX transfer length.
508 *
509 * @note This function sets up the RX buffer size. At least one of
510 * @ref nrf_tdm_rx_count_set or @ref nrf_tdm_tx_count_set functions must be called
511 * before starting the transmission. Also @ref nrf_tdm_transfer_direction_set and
512 * @ref nrf_tdm_tx_buffer_set should be called before starting the transmission.
513 *
514 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
515 * @param[in] size Size of the buffer (in 32-bit words).
516 */
517 NRF_STATIC_INLINE void nrf_tdm_tx_count_set(NRF_TDM_Type * p_reg,
518 uint16_t size);
519
520 /**
521 * @brief Function for setting up the direction of the TDM transfer.
522 *
523 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
524 * @param[in] dir Transmission direction.
525 */
526 NRF_STATIC_INLINE void nrf_tdm_transfer_direction_set(NRF_TDM_Type * p_reg,
527 nrf_tdm_rxtxen_t dir);
528
529 /**
530 * @brief Function for setting the pointer to the receive buffer.
531 *
532 * @note The size of the buffer can be set only by calling
533 * @ref nrf_tdm_rx_count_set.
534 *
535 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
536 * @param[in] p_buffer Pointer to the receive buffer.
537 */
538 NRF_STATIC_INLINE void nrf_tdm_rx_buffer_set(NRF_TDM_Type * p_reg,
539 uint32_t * p_buffer);
540
541 /**
542 * @brief Function for getting the pointer to the receive buffer.
543 *
544 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
545 *
546 * @return Pointer to the receive buffer.
547 */
548 NRF_STATIC_INLINE uint32_t * nrf_tdm_rx_buffer_get(NRF_TDM_Type const * p_reg);
549
550 /**
551 * @brief Function for setting the pointer to the transmit buffer.
552 *
553 * @note The size of the buffer can be set only by calling
554 * @ref nrf_tdm_tx_count_set.
555 *
556 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
557 * @param[in] p_buffer Pointer to the transmit buffer.
558 */
559 NRF_STATIC_INLINE void nrf_tdm_tx_buffer_set(NRF_TDM_Type * p_reg,
560 uint32_t const * p_buffer);
561
562 /**
563 * @brief Function for getting the number of bytes transferred in the current transaction.
564 *
565 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
566 *
567 * @return Number of bytes transferred.
568 */
569 NRF_STATIC_INLINE uint32_t nrf_tdm_current_tx_transfer_amount_get(NRF_TDM_Type const * p_reg);
570
571 /**
572 * @brief Function for getting the number of bytes transferred in the last transaction.
573 * The value has been updated after the END event.
574 *
575 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
576 *
577 * @return Number of bytes transferred.
578 */
579 NRF_STATIC_INLINE uint32_t nrf_tdm_last_tx_transfer_amount_get(NRF_TDM_Type const * p_reg);
580
581 /**
582 * @brief Function for getting the number of bytes received in the current transaction.
583 *
584 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
585 *
586 * @return Number of bytes received.
587 */
588 NRF_STATIC_INLINE uint32_t nrf_tdm_current_rx_transfer_amount_get(NRF_TDM_Type const * p_reg);
589
590 /**
591 * @brief Function for getting the number of bytes received in the last transaction.
592 * The value has been updated after the END event.
593 *
594 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
595 *
596 * @return Number of bytes received.
597 */
598 NRF_STATIC_INLINE uint32_t nrf_tdm_last_rx_transfer_amount_get(NRF_TDM_Type const * p_reg);
599
600 /**
601 * @brief Function for getting the pointer to the transmit buffer.
602 *
603 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
604 *
605 * @return Pointer to the transmit buffer.
606 */
607 NRF_STATIC_INLINE uint32_t * nrf_tdm_tx_buffer_get(NRF_TDM_Type const * p_reg);
608
609 /**
610 * @brief Function for configuring TDM master Clock.
611 *
612 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
613 * @param[in] clksrc TDM master clock source selection.
614 * @param[in] enable_bypass Bypass clock generator. MCK will be equal to source input.
615 * If bypass is enabled the MCK.DIV setting has no effect.
616 */
617 NRF_STATIC_INLINE void nrf_tdm_mck_configure(NRF_TDM_Type * p_reg,
618 nrf_tdm_src_t clksrc,
619 bool enable_bypass);
620
621 /**
622 * @brief Function for configuring TDM serial Clock.
623 *
624 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
625 * @param[in] clksrc TDM serial clock source selection.
626 * @param[in] enable_bypass Bypass clock generator. SCK will be equal to source input.
627 * If bypass is enabled the SCK.DIV setting has no effect.
628 */
629 NRF_STATIC_INLINE void nrf_tdm_sck_configure(NRF_TDM_Type * p_reg,
630 nrf_tdm_src_t clksrc,
631 bool enable_bypass);
632
633 #ifndef NRF_DECLARE_ONLY
634
nrf_tdm_task_trigger(NRF_TDM_Type * p_reg,nrf_tdm_task_t task)635 NRF_STATIC_INLINE void nrf_tdm_task_trigger(NRF_TDM_Type * p_reg,
636 nrf_tdm_task_t task)
637 {
638 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
639 }
640
nrf_tdm_task_address_get(NRF_TDM_Type const * p_reg,nrf_tdm_task_t task)641 NRF_STATIC_INLINE uint32_t nrf_tdm_task_address_get(NRF_TDM_Type const * p_reg,
642 nrf_tdm_task_t task)
643 {
644 return nrf_task_event_address_get(p_reg, task);
645 }
646
nrf_tdm_event_clear(NRF_TDM_Type * p_reg,nrf_tdm_event_t event)647 NRF_STATIC_INLINE void nrf_tdm_event_clear(NRF_TDM_Type * p_reg,
648 nrf_tdm_event_t event)
649 {
650 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
651 nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
652 }
653
nrf_tdm_event_check(NRF_TDM_Type const * p_reg,nrf_tdm_event_t event)654 NRF_STATIC_INLINE bool nrf_tdm_event_check(NRF_TDM_Type const * p_reg,
655 nrf_tdm_event_t event)
656 {
657 return nrf_event_check(p_reg, event);
658 }
659
nrf_tdm_event_address_get(NRF_TDM_Type const * p_reg,nrf_tdm_event_t event)660 NRF_STATIC_INLINE uint32_t nrf_tdm_event_address_get(NRF_TDM_Type const * p_reg,
661 nrf_tdm_event_t event)
662 {
663 return nrf_task_event_address_get(p_reg, event);
664 }
665
nrf_tdm_int_enable(NRF_TDM_Type * p_reg,uint32_t mask)666 NRF_STATIC_INLINE void nrf_tdm_int_enable(NRF_TDM_Type * p_reg, uint32_t mask)
667 {
668 p_reg->INTENSET = mask;
669 }
670
nrf_tdm_int_disable(NRF_TDM_Type * p_reg,uint32_t mask)671 NRF_STATIC_INLINE void nrf_tdm_int_disable(NRF_TDM_Type * p_reg, uint32_t mask)
672 {
673 p_reg->INTENCLR = mask;
674 }
675
nrf_tdm_int_enable_check(NRF_TDM_Type const * p_reg,uint32_t mask)676 NRF_STATIC_INLINE uint32_t nrf_tdm_int_enable_check(NRF_TDM_Type const * p_reg, uint32_t mask)
677 {
678 return p_reg->INTENSET & mask;
679 }
680
nrf_tdm_enable(NRF_TDM_Type * p_reg)681 NRF_STATIC_INLINE void nrf_tdm_enable(NRF_TDM_Type * p_reg)
682 {
683 p_reg->ENABLE = (TDM_ENABLE_ENABLE_Enabled << TDM_ENABLE_ENABLE_Pos);
684 }
685
nrf_tdm_disable(NRF_TDM_Type * p_reg)686 NRF_STATIC_INLINE void nrf_tdm_disable(NRF_TDM_Type * p_reg)
687 {
688 p_reg->ENABLE = (TDM_ENABLE_ENABLE_Disabled << TDM_ENABLE_ENABLE_Pos);
689 }
690
nrf_tdm_enable_check(NRF_TDM_Type * p_reg)691 NRF_STATIC_INLINE bool nrf_tdm_enable_check(NRF_TDM_Type * p_reg)
692 {
693 return p_reg->ENABLE == (TDM_ENABLE_ENABLE_Enabled << TDM_ENABLE_ENABLE_Pos);
694 }
695
696 #if defined(DPPI_PRESENT)
nrf_tdm_subscribe_set(NRF_TDM_Type * p_reg,nrf_tdm_task_t task,uint8_t channel)697 NRF_STATIC_INLINE void nrf_tdm_subscribe_set(NRF_TDM_Type * p_reg,
698 nrf_tdm_task_t task,
699 uint8_t channel)
700 {
701 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
702 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
703 }
704
nrf_tdm_subscribe_clear(NRF_TDM_Type * p_reg,nrf_tdm_task_t task)705 NRF_STATIC_INLINE void nrf_tdm_subscribe_clear(NRF_TDM_Type * p_reg,
706 nrf_tdm_task_t task)
707 {
708 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
709 }
710
nrf_tdm_publish_set(NRF_TDM_Type * p_reg,nrf_tdm_event_t event,uint8_t channel)711 NRF_STATIC_INLINE void nrf_tdm_publish_set(NRF_TDM_Type * p_reg,
712 nrf_tdm_event_t event,
713 uint8_t channel)
714 {
715 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
716 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
717 }
718
nrf_tdm_publish_clear(NRF_TDM_Type * p_reg,nrf_tdm_event_t event)719 NRF_STATIC_INLINE void nrf_tdm_publish_clear(NRF_TDM_Type * p_reg,
720 nrf_tdm_event_t event)
721 {
722 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
723 }
724 #endif // defined(DPPI_PRESENT)
725
nrf_tdm_pins_set(NRF_TDM_Type * p_reg,nrf_tdm_pins_t const * p_pins)726 NRF_STATIC_INLINE void nrf_tdm_pins_set(NRF_TDM_Type * p_reg, nrf_tdm_pins_t const * p_pins)
727 {
728 p_reg->PSEL.SCK = p_pins->sck_pin;
729 p_reg->PSEL.FSYNC = p_pins->fsync_pin;
730 p_reg->PSEL.MCK = p_pins->mck_pin;
731 p_reg->PSEL.SDOUT = p_pins->sdout_pin;
732 p_reg->PSEL.SDIN = p_pins->sdin_pin;
733 }
734
nrf_tdm_sck_pin_get(NRF_TDM_Type const * p_reg)735 NRF_STATIC_INLINE uint32_t nrf_tdm_sck_pin_get(NRF_TDM_Type const * p_reg)
736 {
737 return p_reg->PSEL.SCK;
738 }
739
nrf_tdm_fsync_pin_get(NRF_TDM_Type const * p_reg)740 NRF_STATIC_INLINE uint32_t nrf_tdm_fsync_pin_get(NRF_TDM_Type const * p_reg)
741 {
742 return p_reg->PSEL.FSYNC;
743 }
744
nrf_tdm_mck_pin_get(NRF_TDM_Type const * p_reg)745 NRF_STATIC_INLINE uint32_t nrf_tdm_mck_pin_get(NRF_TDM_Type const * p_reg)
746 {
747 return p_reg->PSEL.MCK;
748 }
749
nrf_tdm_sdout_pin_get(NRF_TDM_Type const * p_reg)750 NRF_STATIC_INLINE uint32_t nrf_tdm_sdout_pin_get(NRF_TDM_Type const * p_reg)
751 {
752 return p_reg->PSEL.SDOUT;
753 }
754
nrf_tdm_sdin_pin_get(NRF_TDM_Type const * p_reg)755 NRF_STATIC_INLINE uint32_t nrf_tdm_sdin_pin_get(NRF_TDM_Type const * p_reg)
756 {
757 return p_reg->PSEL.SDIN;
758 }
759
nrf_tdm_configure(NRF_TDM_Type * p_reg,nrf_tdm_config_t const * p_config)760 NRF_STATIC_INLINE void nrf_tdm_configure(NRF_TDM_Type * p_reg, nrf_tdm_config_t const * p_config)
761 {
762 p_reg->CONFIG.MODE = p_config->mode;
763 p_reg->CONFIG.ALIGN = p_config->alignment;
764 p_reg->CONFIG.SWIDTH = p_config->sample_width;
765 p_reg->CONFIG.CHANNEL.MASK = p_config->channels;
766 p_reg->CONFIG.CHANNEL.NUM = p_config->num_of_channels;
767 p_reg->CONFIG.CHANNEL.DELAY = p_config->channel_delay;
768 p_reg->CONFIG.SCK.DIV = p_config->sck_setup;
769 p_reg->CONFIG.FSYNC.DURATION = p_config->fsync_duration;
770 p_reg->CONFIG.MCK.DIV = p_config->mck_setup;
771 p_reg->CONFIG.SCK.POLARITY = (p_config->sck_polarity == NRF_TDM_POLARITY_POSEDGE) ?
772 (TDM_CONFIG_SCK_POLARITY_SCKPOLARITY_PosEdge) :
773 (TDM_CONFIG_SCK_POLARITY_SCKPOLARITY_NegEdge);
774 p_reg->CONFIG.FSYNC.POLARITY = (p_config->fsync_polarity == NRF_TDM_POLARITY_POSEDGE) ?
775 (TDM_CONFIG_FSYNC_POLARITY_POLARITY_PosEdge) :
776 (TDM_CONFIG_FSYNC_POLARITY_POLARITY_NegEdge);
777 }
778
nrf_tdm_mck_set(NRF_TDM_Type * p_reg,bool enable)779 NRF_STATIC_INLINE void nrf_tdm_mck_set(NRF_TDM_Type * p_reg, bool enable)
780 {
781 p_reg->CONFIG.MCK.EN = ((p_reg->CONFIG.MCK.EN & ~TDM_CONFIG_MCK_EN_MCKEN_Msk) |
782 ((enable ? TDM_CONFIG_MCK_EN_MCKEN_Enabled :
783 TDM_CONFIG_MCK_EN_MCKEN_Disabled) << TDM_CONFIG_MCK_EN_MCKEN_Pos));
784 }
785
nrf_tdm_rx_count_set(NRF_TDM_Type * p_reg,uint16_t size)786 NRF_STATIC_INLINE void nrf_tdm_rx_count_set(NRF_TDM_Type * p_reg,
787 uint16_t size)
788 {
789 #if defined(DMA_BUFFER_UNIFIED_BYTE_ACCESS)
790 p_reg->RXD.MAXCNT = size * sizeof(uint32_t);
791 #else
792 p_reg->RXD.MAXCNT = (uint32_t)size;
793 #endif
794 }
795
nrf_tdm_tx_count_set(NRF_TDM_Type * p_reg,uint16_t size)796 NRF_STATIC_INLINE void nrf_tdm_tx_count_set(NRF_TDM_Type * p_reg,
797 uint16_t size)
798 {
799 #if defined(DMA_BUFFER_UNIFIED_BYTE_ACCESS)
800 p_reg->TXD.MAXCNT = size * sizeof(uint32_t);
801 #else
802 p_reg->TXD.MAXCNT = (uint32_t)size;
803 #endif
804 }
805
nrf_tdm_transfer_direction_set(NRF_TDM_Type * p_reg,nrf_tdm_rxtxen_t dir)806 NRF_STATIC_INLINE void nrf_tdm_transfer_direction_set(NRF_TDM_Type * p_reg,
807 nrf_tdm_rxtxen_t dir)
808 {
809 p_reg->CONFIG.RXTXEN = (dir << TDM_CONFIG_RXTXEN_RXTXEN_Pos);
810 }
811
nrf_tdm_rx_buffer_set(NRF_TDM_Type * p_reg,uint32_t * p_buffer)812 NRF_STATIC_INLINE void nrf_tdm_rx_buffer_set(NRF_TDM_Type * p_reg,
813 uint32_t * p_buffer)
814 {
815 p_reg->RXD.PTR = (uint32_t)p_buffer;
816 }
817
nrf_tdm_rx_buffer_get(NRF_TDM_Type const * p_reg)818 NRF_STATIC_INLINE uint32_t * nrf_tdm_rx_buffer_get(NRF_TDM_Type const * p_reg)
819 {
820 return (uint32_t *)(p_reg->RXD.PTR);
821 }
822
nrf_tdm_tx_buffer_set(NRF_TDM_Type * p_reg,uint32_t const * p_buffer)823 NRF_STATIC_INLINE void nrf_tdm_tx_buffer_set(NRF_TDM_Type * p_reg,
824 uint32_t const * p_buffer)
825 {
826 p_reg->TXD.PTR = (uint32_t)p_buffer;
827 }
828
nrf_tdm_current_tx_transfer_amount_get(NRF_TDM_Type const * p_reg)829 NRF_STATIC_INLINE uint32_t nrf_tdm_current_tx_transfer_amount_get(NRF_TDM_Type const * p_reg)
830 {
831 return p_reg->TXD.CURRENTAMOUNT;
832 }
833
nrf_tdm_last_tx_transfer_amount_get(NRF_TDM_Type const * p_reg)834 NRF_STATIC_INLINE uint32_t nrf_tdm_last_tx_transfer_amount_get(NRF_TDM_Type const * p_reg)
835 {
836 return p_reg->TXD.AMOUNT;
837 }
838
nrf_tdm_current_rx_transfer_amount_get(NRF_TDM_Type const * p_reg)839 NRF_STATIC_INLINE uint32_t nrf_tdm_current_rx_transfer_amount_get(NRF_TDM_Type const * p_reg)
840 {
841 return p_reg->RXD.CURRENTAMOUNT;
842 }
843
nrf_tdm_last_rx_transfer_amount_get(NRF_TDM_Type const * p_reg)844 NRF_STATIC_INLINE uint32_t nrf_tdm_last_rx_transfer_amount_get(NRF_TDM_Type const * p_reg)
845 {
846 return p_reg->RXD.AMOUNT;
847 }
848
nrf_tdm_tx_buffer_get(NRF_TDM_Type const * p_reg)849 NRF_STATIC_INLINE uint32_t * nrf_tdm_tx_buffer_get(NRF_TDM_Type const * p_reg)
850 {
851 return (uint32_t *)(p_reg->TXD.PTR);
852 }
853
nrf_tdm_mck_configure(NRF_TDM_Type * p_reg,nrf_tdm_src_t clksrc,bool enable_bypass)854 NRF_STATIC_INLINE void nrf_tdm_mck_configure(NRF_TDM_Type * p_reg,
855 nrf_tdm_src_t clksrc,
856 bool enable_bypass)
857 {
858 p_reg->CONFIG.MCK.SRC = (((uint32_t) clksrc << TDM_CONFIG_MCK_SRC_CLKSRC_Pos) &
859 TDM_CONFIG_MCK_SRC_CLKSRC_Msk) |
860 (((uint32_t) enable_bypass << TDM_CONFIG_MCK_SRC_BYPASS_Pos) &
861 TDM_CONFIG_MCK_SRC_BYPASS_Msk);
862 }
863
nrf_tdm_sck_configure(NRF_TDM_Type * p_reg,nrf_tdm_src_t clksrc,bool enable_bypass)864 NRF_STATIC_INLINE void nrf_tdm_sck_configure(NRF_TDM_Type * p_reg,
865 nrf_tdm_src_t clksrc,
866 bool enable_bypass)
867 {
868 p_reg->CONFIG.SCK.SRC = ((uint32_t) clksrc << TDM_CONFIG_SCK_SRC_CLKSRC_Pos) |
869 ((uint32_t) enable_bypass << TDM_CONFIG_SCK_SRC_BYPASS_Pos);
870 }
871
872 #endif // NRF_DECLARE_ONLY
873
874 /** @} */
875
876 #ifdef __cplusplus
877 }
878 #endif
879
880 #endif // NRF_TDM_H__
881
