1 /*
2 * Copyright (c) 2023 - 2024, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_TAMPC_H_
35 #define NRF_TAMPC_H_
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /**
44 * @defgroup nrf_tampc_hal TAMPC HAL
45 * @{
46 * @ingroup nrf_tampc
47 * @brief Hardware access layer for managing the Tamper Controller (TAMPC)
48 * peripheral.
49 */
50
51 #if defined(TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_KEY_Msk) || defined(__NRFX_DOXYGEN__)
52 /** @brief Protect register write key mask. */
53 #define NRF_TAMPC_KEY_MASK (TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_KEY_KEY \
54 << TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_KEY_Pos)
55 #else
56 #define NRF_TAMPC_KEY_MASK 0
57 #endif
58
59 #if defined(TAMPC_EVENTS_WRITEERROR_EVENTS_WRITEERROR_Msk) || defined(__NRFX_DOXYGEN__)
60 /** @brief Symbol indicating whether TAMPC write error event is present. */
61 #define NRF_TAMPC_HAS_EVENT_WRITE_ERROR 1
62 #else
63 #define NRF_TAMPC_HAS_EVENT_WRITE_ERROR 0
64 #endif
65
66 #if defined(TAMPC_ACTIVESHIELD_CHEN_CH0_Msk) || defined(__NRFX_DOXYGEN__)
67 /** @brief Symbol indicating whether TAMPC active shield channels are present. */
68 #define NRF_TAMPC_HAS_ACTIVE_SHIELD_CHANNELS 1
69 #else
70 #define NRF_TAMPC_HAS_ACTIVE_SHIELD_CHANNELS 0
71 #endif
72
73 #if defined(TAMPC_PROTECT_ACTIVESHIELD_CTRL_VALUE_Msk) || defined(__NRFX_DOXYGEN__)
74 /** @brief Symbol indicating whether TAMPC extended protection is present. */
75 #define NRF_TAMPC_HAS_EXTENDED_PROTECTORS 1
76 #else
77 #define NRF_TAMPC_HAS_EXTENDED_PROTECTORS 0
78 #endif
79
80 #if defined(TAMPC_PROTECT_ERASEPROTECT_CTRL_VALUE_Msk) || defined(__NRFX_DOXYGEN__)
81 /** @brief Symbol indicating whether TAMPC erase protector is present. */
82 #define NRF_TAMPC_HAS_ERASE_PROTECTOR 1
83 #else
84 #define NRF_TAMPC_HAS_ERASE_PROTECTOR 0
85 #endif
86
87 #if defined(TAMPC_PROTECT_TAMPERSWITCH_CTRL_VALUE_Msk) || defined(__NRFX_DOXYGEN__)
88 /** @brief Symbol indicating whether TAMPC external tamper switch protector is present. */
89 #define NRF_TAMPC_HAS_EXTERNAL_TAMPERSWITCH_PROTECTOR 1
90 #else
91 #define NRF_TAMPC_HAS_EXTERNAL_TAMPERSWITCH_PROTECTOR 0
92 #endif
93
94 #if defined(TAMPC_PROTECT_AP_SPIDEN_CTRL_VALUE_Msk) || defined(__NRFX_DOXYGEN__)
95 /** @brief Symbol indicating whether AP secure priviliged invasive debug detector is present. */
96 #define NRF_TAMPC_HAS_AP_SPIDEN_PROTECTOR 1
97 #else
98 #define NRF_TAMPC_HAS_AP_SPIDEN_PROTECTOR 0
99 #endif
100
101 #if defined(TAMPC_ENABLE_ACTIVESHIELD_Msk) || defined(__NRFX_DOXYGEN__)
102 /** @brief Symbol indicating whether the availability to enable the TAMPC detectors feature is present. */
103 #define NRF_TAMPC_HAS_DETECTORS_ENABLE 1
104 #else
105 #define NRF_TAMPC_HAS_DETECTORS_ENABLE 0
106 #endif
107
108 #if defined(TAMPC_PROTECT_CORESIGHT_DEVICEEN_CTRL_VALUE_High) || defined(__NRFX_DOXYGEN__)
109 /** @brief Symbol indicating whether the configuration of Coresight debugger signals protection is present. */
110 #define NRF_TAMPC_HAS_CORESIGHT 1
111 #else
112 #define NRF_TAMPC_HAS_CORESIGHT 0
113 #endif
114
115 #if defined(TAMPC_PROTECT_WARMBOOT_SYSTEMOFF_CTRL_VALUE_Msk) || defined(__NRFX_DOXYGEN__)
116 /** @brief Symbol indicating whether the configuration of warm boot protection is present. */
117 #define NRF_TAMPC_HAS_WARMBOOT 1
118 #else
119 #define NRF_TAMPC_HAS_WARMBOOT 0
120 #endif
121
122 #if defined(TAMPC_STATUS_TAMPERSWITCH_Msk) || defined(__NRFX_DOXYGEN__)
123 /** @brief Symbol indicating whether TAMPC external tamper switch detector is present. */
124 #define NRF_TAMPC_HAS_EXTERNAL_TAMPERSWITCH_DETECTOR 1
125 #else
126 #define NRF_TAMPC_HAS_EXTERNAL_TAMPERSWITCH_DETECTOR 0
127 #endif
128
129 /** @brief TAMPC events. */
130 typedef enum
131 {
132 NRF_TAMPC_EVENT_TAMPER = offsetof(NRF_TAMPC_Type, EVENTS_TAMPER), ///< TAMPC detected an error.
133 #if NRF_TAMPC_HAS_EVENT_WRITE_ERROR
134 NRF_TAMPC_EVENT_WRITE_ERROR = offsetof(NRF_TAMPC_Type, EVENTS_WRITEERROR) ///< Attempted to write a VALUE in PROTECT registers without clearing the WRITEPROTECT.
135 #endif
136 } nrf_tampc_event_t;
137
138 /** @brief TAMPC interrupts. */
139 typedef enum
140 {
141 NRF_TAMPC_INT_TAMPER_MASK = TAMPC_INTENSET_TAMPER_Msk, ///< Interrupt on TAMPER event.
142 #if NRF_TAMPC_HAS_EVENT_WRITE_ERROR
143 NRF_TAMPC_INT_WRITE_ERROR_MASK = TAMPC_INTENSET_WRITEERROR_Msk, ///< Interrupt on WRITEERROR event.
144 #endif
145 NRF_TAMPC_ALL_INTS_MASK = NRF_TAMPC_INT_TAMPER_MASK
146 #if NRF_TAMPC_HAS_EVENT_WRITE_ERROR
147 | NRF_TAMPC_INT_WRITE_ERROR_MASK ///< All TAMPC interrupts.
148 #endif
149 } nrf_tapmc_int_mask_t;
150
151 #if NRF_TAMPC_HAS_ACTIVE_SHIELD_CHANNELS
152 /** @brief Active shield channel mask. */
153 typedef enum
154 {
155 NRF_TAMPC_ACTIVESHIELD_CHANNEL_0_MASK = TAMPC_ACTIVESHIELD_CHEN_CH0_Msk, ///< Enable active shield channel 0.
156 NRF_TAMPC_ACTIVESHIELD_CHANNEL_1_MASK = TAMPC_ACTIVESHIELD_CHEN_CH1_Msk, ///< Enable active shield channel 1.
157 NRF_TAMPC_ACTIVESHIELD_CHANNEL_2_MASK = TAMPC_ACTIVESHIELD_CHEN_CH2_Msk, ///< Enable active shield channel 2.
158 NRF_TAMPC_ACTIVESHIELD_CHANNEL_3_MASK = TAMPC_ACTIVESHIELD_CHEN_CH3_Msk, ///< Enable active shield channel 3.
159 NRF_TAMPC_ALL_ACTIVESHIELD_CHANNELS_MASK = NRF_TAMPC_ACTIVESHIELD_CHANNEL_0_MASK
160 | NRF_TAMPC_ACTIVESHIELD_CHANNEL_1_MASK
161 | NRF_TAMPC_ACTIVESHIELD_CHANNEL_2_MASK
162 | NRF_TAMPC_ACTIVESHIELD_CHANNEL_3_MASK ///< All TAMPC active shield channels.
163 } nrf_tampc_activeshield_mask_t;
164 #endif
165
166 /** @brief TAMPC error detectors. */
167 typedef enum
168 {
169 NRF_TAMPC_DETECTOR_ACTIVE_SHIELD = TAMPC_STATUS_ACTIVESHIELD_Msk, ///< Active shield error detector.
170 #if NRF_TAMPC_HAS_EXTERNAL_TAMPERSWITCH_DETECTOR
171 NRF_TAMPC_DETECTOR_TAMPER_SWITCH = TAMPC_STATUS_TAMPERSWITCH_Msk, ///< External tamper switch error detector.
172 #endif
173 NRF_TAMPC_DETECTOR_PROTECTED_SIGNAL = TAMPC_STATUS_PROTECT_Msk, ///< Protected signals error detector.
174 NRF_TAMPC_DETECTOR_CRACEN = TAMPC_STATUS_CRACENTAMP_Msk, ///< CRACEN error detector.
175 NRF_TAMPC_DETECTOR_GLITCH_DOMAIN_SLOW = TAMPC_STATUS_GLITCHSLOWDOMAIN0_Msk, ///< Slow domain glitch error detector.
176 NRF_TAMPC_DETECTOR_GLITCH_DOMAIN_FAST = TAMPC_STATUS_GLITCHFASTDOMAIN0_Msk | ///< Fast domain glitch error detector.
177 TAMPC_STATUS_GLITCHFASTDOMAIN1_Msk |
178 TAMPC_STATUS_GLITCHFASTDOMAIN2_Msk |
179 TAMPC_STATUS_GLITCHFASTDOMAIN3_Msk
180 } nrf_tampc_detector_t;
181
182 #if NRF_TAMPC_HAS_EXTENDED_PROTECTORS
183 /** @brief Signal protector registers. */
184 typedef enum
185 {
186 NRF_TAMPC_PROTECT_ACTIVE_SHIELD = offsetof(NRF_TAMPC_Type, PROTECT.ACTIVESHIELD), ///< Control register for active shield detector enable signal.
187 #if NRF_TAMPC_HAS_EXTERNAL_TAMPERSWITCH_PROTECTOR
188 NRF_TAMPC_PROTECT_TAMPER_SWITCH = offsetof(NRF_TAMPC_Type, PROTECT.TAMPERSWITCH), ///< Control register for external tamper switch enable signal.
189 #endif
190 NRF_TAMPC_PROTECT_CRACEN = offsetof(NRF_TAMPC_Type, PROTECT.CRACENTAMP), ///< Control register for CRACEN tamper detector enable signal.
191 NRF_TAMPC_PROTECT_GLITCH_DOMAIN_SLOW = offsetof(NRF_TAMPC_Type, PROTECT.GLITCHSLOWDOMAIN), ///< Control register for slow domain glitch detectors enable signal.
192 NRF_TAMPC_PROTECT_GLITCH_DOMAIN_FAST = offsetof(NRF_TAMPC_Type, PROTECT.GLITCHFASTDOMAIN), ///< Control register for fast domain glitch detectors enable signal.
193 NRF_TAMPC_PROTECT_RESETEN_EXT = offsetof(NRF_TAMPC_Type, PROTECT.EXTRESETEN), ///< Control register for external tamper reset enable signal.
194 NRF_TAMPC_PROTECT_RESETEN_INT = offsetof(NRF_TAMPC_Type, PROTECT.INTRESETEN), ///< Control register for internal tamper reset enable signal.
195 #if NRF_TAMPC_HAS_ERASE_PROTECTOR
196 NRF_TAMPC_PROTECT_ERASE_PROTECT = offsetof(NRF_TAMPC_Type, PROTECT.ERASEPROTECT), ///< Control register for erase protection.
197 #endif
198 } nrf_tampc_protect_t;
199 #endif
200
201 /** @brief Control register debug types. */
202 typedef enum
203 {
204 NRF_TAMPC_DEBUG_TYPE_DBGEN, ///< Invasive (halting) debug.
205 NRF_TAMPC_DEBUG_TYPE_NIDEN, ///< Non-invasive debug.
206 NRF_TAMPC_DEBUG_TYPE_SPIDEN, ///< Secure privileged invasive (halting) debug.
207 NRF_TAMPC_DEBUG_TYPE_SPNIDEN, ///< Secure privileged non-invasive debug.
208 NRF_TAMPC_DEBUG_TYPE_DEVICEEN, ///< Domain circuitry.
209 } nrf_tampc_debug_type_t;
210
211 /** @brief Warm boot control register mode types. */
212 typedef enum
213 {
214 NRF_TAMPC_WARMBOOT_MODE_UNRET_IDLE, ///< Unretained idle mode.
215 NRF_TAMPC_WARMBOOT_MODE_SYSTEMOFF, ///< System off mode.
216 } nrf_tampc_warmboot_mode_t;
217
218 /**
219 * @brief Function for clearing the specified TAMPC event.
220 *
221 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
222 * @param[in] event Event to be cleared.
223 */
224 NRF_STATIC_INLINE void nrf_tampc_event_clear(NRF_TAMPC_Type * p_reg, nrf_tampc_event_t event);
225
226 /**
227 * @brief Function for retrieving the state of the TAMPC event.
228 *
229 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
230 * @param[in] event Event to be checked.
231 *
232 * @retval true The event has been generated.
233 * @retval false The event has not been generated.
234 */
235 NRF_STATIC_INLINE bool nrf_tampc_event_check(NRF_TAMPC_Type const * p_reg, nrf_tampc_event_t event);
236
237 /**
238 * @brief Function for getting the address of the specified TAMPC event register.
239 *
240 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
241 * @param[in] event The specified event.
242 *
243 * @return Address of the specified event register.
244 */
245 NRF_STATIC_INLINE uint32_t nrf_tampc_event_address_get(NRF_TAMPC_Type const * p_reg,
246 nrf_tampc_event_t event);
247
248 /**
249 * @brief Function for enabling the specified interrupts.
250 *
251 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
252 * @param[in] mask Mask of interrupts to be enabled.
253 * Use @ref nrf_tapmc_int_mask_t values for bit masking.
254 */
255 NRF_STATIC_INLINE void nrf_tampc_int_enable(NRF_TAMPC_Type * p_reg, uint32_t mask);
256
257 /**
258 * @brief Function for disabling the specified interrupts.
259 *
260 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
261 * @param[in] mask Mask of interrupts to be disabled.
262 * Use @ref nrf_tapmc_int_mask_t values for bit masking.
263 */
264 NRF_STATIC_INLINE void nrf_tampc_int_disable(NRF_TAMPC_Type * p_reg, uint32_t mask);
265
266 /**
267 * @brief Function for checking if the specified interrupts are enabled.
268 *
269 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
270 * @param[in] mask Mask of interrupts to be checked.
271 * Use @ref nrf_tapmc_int_mask_t values for bit masking.
272 *
273 * @return Mask of enabled interrupts.
274 */
275 NRF_STATIC_INLINE uint32_t nrf_tampc_int_enable_check(NRF_TAMPC_Type const * p_reg, uint32_t mask);
276
277 /**
278 * @brief Function for retrieving the state of pending interrupts.
279 *
280 * @note States of pending interrupt are saved as a bitmask.
281 * One set at particular position means that interrupt for event is pending.
282 *
283 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
284 *
285 * @return Bitmask with information about pending interrupts.
286 * Use @ref nrf_tapmc_int_mask_t values for bit masking.
287 */
288 NRF_STATIC_INLINE uint32_t nrf_tampc_int_pending_get(NRF_TAMPC_Type const * p_reg);
289
290 /**
291 * @brief Function for getting the error detection status for given error detector.
292 *
293 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
294 * @param[in] detector Error detector for which the error status is to be retrieved.
295 *
296 * @retval true Error detected.
297 * @retval false No error detected.
298 */
299 NRF_STATIC_INLINE bool nrf_tampc_detector_status_check(NRF_TAMPC_Type const * p_reg,
300 nrf_tampc_detector_t detector);
301
302 /**
303 * @brief Function for clearing the error detection status for given error detector.
304 *
305 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
306 * @param[in] detector Error detector for which the error status is to be cleared.
307 */
308 NRF_STATIC_INLINE void nrf_tampc_detector_status_clear(NRF_TAMPC_Type * p_reg,
309 nrf_tampc_detector_t detector);
310
311 #if NRF_TAMPC_HAS_ACTIVE_SHIELD_CHANNELS
312 /**
313 * @brief Function for enabling the specified active shield detector channels.
314 *
315 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
316 * @param[in] mask Mask of active shield detector channels to be enabled,
317 * constructed from @ref nrf_tampc_activeshield_mask_t enumerator values.
318 */
319 NRF_STATIC_INLINE void nrf_tampc_activeshield_channel_enable(NRF_TAMPC_Type * p_reg, uint32_t mask);
320
321 /**
322 * @brief Function for disabling the specified active shield detector channels.
323 *
324 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
325 * @param[in] mask Mask of active shield detector channels to be disabled,
326 * constructed from @ref nrf_tampc_activeshield_mask_t enumerator values.
327 */
328 NRF_STATIC_INLINE void nrf_tampc_activeshield_channel_disable(NRF_TAMPC_Type * p_reg,
329 uint32_t mask);
330
331 /**
332 * @brief Function for checking if the specified active shield detector channels are enabled.
333 *
334 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
335 * @param[in] mask Mask of active shield detector channels to be checked,
336 * constructed from @ref nrf_tampc_activeshield_mask_t enumerator values.
337 *
338 * @return Mask of enabled active shield detector channels.
339 */
340 NRF_STATIC_INLINE uint32_t nrf_tampc_activeshield_channel_enable_check(NRF_TAMPC_Type const * p_reg,
341 uint32_t mask);
342 #endif
343
344 /**
345 * @brief Function for setting signal value of the domain control register for
346 * given debug type and domain.
347 *
348 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
349 * @param[in] type Debug type to be modified.
350 * @param[in] domain Domain for which the value is to be modified.
351 * @param[in] enable True if signal is to be logic 1, false if logic 0.
352 */
353 NRF_STATIC_INLINE void nrf_tampc_domain_ctrl_value_set(NRF_TAMPC_Type * p_reg,
354 nrf_tampc_debug_type_t type,
355 nrf_domain_t domain,
356 bool enable);
357
358 /**
359 * @brief Function for getting the signal value of the domain control register for
360 * given debug type and domain.
361 *
362 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
363 * @param[in] type Debug type to be retrieved.
364 * @param[in] domain Domain for which the value is to be retrieved.
365 *
366 * @retval true Signal is logic 1.
367 * @retval false Signal is logic 0.
368 */
369 NRF_STATIC_INLINE bool nrf_tampc_domain_ctrl_value_get(NRF_TAMPC_Type const * p_reg,
370 nrf_tampc_debug_type_t type,
371 nrf_domain_t domain);
372
373 /**
374 * @brief Function for setting lock value of the domain control register for
375 * given debug type and domain.
376 *
377 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
378 * @param[in] type Debug type to be modified.
379 * @param[in] domain Domain for which the value is to be modified.
380 * @param[in] enable True if register is to be locked, false otherwise.
381 */
382 NRF_STATIC_INLINE void nrf_tampc_domain_ctrl_lock_set(NRF_TAMPC_Type * p_reg,
383 nrf_tampc_debug_type_t type,
384 nrf_domain_t domain,
385 bool enable);
386
387 /**
388 * @brief Function for getting the lock value of the domain control register for
389 * given debug type and domain.
390 *
391 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
392 * @param[in] type Debug type to be retrieved.
393 * @param[in] domain Domain for which the value is to be retrieved.
394 *
395 * @retval true Register is locked.
396 * @retval false Register is unlocked.
397 */
398 NRF_STATIC_INLINE bool nrf_tampc_domain_ctrl_lock_get(NRF_TAMPC_Type const * p_reg,
399 nrf_tampc_debug_type_t type,
400 nrf_domain_t domain);
401
402 /**
403 * @brief Function for setting signal value of the access port control register for
404 * given debug type and domain.
405 *
406 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
407 * @param[in] type Debug type to be modified.
408 * @param[in] domain Domain for which the value is to be modified.
409 * @param[in] enable True if signal is to be logic 1, false if logic 0.
410 */
411 NRF_STATIC_INLINE void nrf_tampc_ap_ctrl_value_set(NRF_TAMPC_Type * p_reg,
412 nrf_tampc_debug_type_t type,
413 nrf_domain_t domain,
414 bool enable);
415
416 /**
417 * @brief Function for getting the signal value of the access port control register for
418 * given debug type and domain.
419 *
420 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
421 * @param[in] type Debug type to be retrieved.
422 * @param[in] domain Domain for which the value is to be retrieved.
423 *
424 * @retval true Signal is logic 1.
425 * @retval false Signal is logic 0.
426 */
427 NRF_STATIC_INLINE bool nrf_tampc_ap_ctrl_value_get(NRF_TAMPC_Type const * p_reg,
428 nrf_tampc_debug_type_t type,
429 nrf_domain_t domain);
430
431 /**
432 * @brief Function for setting lock value of the access port control register for
433 * given debug type and domain.
434 *
435 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
436 * @param[in] type Debug type to be modified.
437 * @param[in] domain Domain for which the value is to be modified.
438 * @param[in] enable True if register is to be locked, false otherwise.
439 */
440 NRF_STATIC_INLINE void nrf_tampc_ap_ctrl_lock_set(NRF_TAMPC_Type * p_reg,
441 nrf_tampc_debug_type_t type,
442 nrf_domain_t domain,
443 bool enable);
444
445 /**
446 * @brief Function for getting the lock value of the access port control register for
447 * given debug type and domain.
448 *
449 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
450 * @param[in] type Debug type to be retrieved.
451 * @param[in] domain Domain for which the value is to be retrieved.
452 *
453 * @retval true Register is locked.
454 * @retval false Register is unlocked.
455 */
456 NRF_STATIC_INLINE bool nrf_tampc_ap_ctrl_lock_get(NRF_TAMPC_Type const * p_reg,
457 nrf_tampc_debug_type_t type,
458 nrf_domain_t domain);
459
460 #if NRF_TAMPC_HAS_CORESIGHT
461 /**
462 * @brief Function for setting signal value of the Coresight register for given debug type.
463 *
464 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
465 * @param[in] type Debug type to be modified.
466 * @param[in] enable True if signal is to be logic 1, false if logic 0.
467 */
468 NRF_STATIC_INLINE void nrf_tampc_coresight_ctrl_value_set(NRF_TAMPC_Type * p_reg,
469 nrf_tampc_debug_type_t type,
470 bool enable);
471
472 /**
473 * @brief Function for getting the signal value of the Coresight register for given debug type.
474 *
475 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
476 * @param[in] type Debug type to be retrieved.
477 *
478 * @retval true Signal is logic 1.
479 * @retval false Signal is logic 0.
480 */
481 NRF_STATIC_INLINE bool nrf_tampc_coresight_ctrl_value_get(NRF_TAMPC_Type const * p_reg,
482 nrf_tampc_debug_type_t type);
483
484 /**
485 * @brief Function for setting lock value of the Coresight register for given debug type.
486 *
487 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
488 * @param[in] type Debug type to be modified.
489 * @param[in] enable True if register is to be locked, false otherwise.
490 */
491 NRF_STATIC_INLINE void nrf_tampc_coresight_ctrl_lock_set(NRF_TAMPC_Type * p_reg,
492 nrf_tampc_debug_type_t type,
493 bool enable);
494
495 /**
496 * @brief Function for getting the lock value of the Coresight register for given debug type.
497 *
498 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
499 * @param[in] type Debug type to be retrieved.
500 *
501 * @retval true Register is locked.
502 * @retval false Register is unlocked.
503 */
504 NRF_STATIC_INLINE bool nrf_tampc_coresight_ctrl_lock_get(NRF_TAMPC_Type const * p_reg,
505 nrf_tampc_debug_type_t type);
506
507 /**
508 * @brief Function for setting fault injection of the Coresight register for given debug type.
509 *
510 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
511 * @param[in] type Debug type to be modified.
512 * @param[in] enable True if fault is to be injected, false otherwise.
513 */
514 NRF_STATIC_INLINE void nrf_tampc_coresight_ctrl_fault_set(NRF_TAMPC_Type * p_reg,
515 nrf_tampc_debug_type_t type,
516 bool enable);
517
518 /**
519 * @brief Function for getting the fault injection of the Coresight register for given debug type.
520 *
521 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
522 * @param[in] type Debug type to be retrieved.
523 *
524 * @retval true Fault is to be injected.
525 * @retval false No operation.
526 */
527 NRF_STATIC_INLINE bool nrf_tampc_coresight_ctrl_fault_get(NRF_TAMPC_Type const * p_reg,
528 nrf_tampc_debug_type_t type);
529 #endif // NRF_TAMPC_HAS_CORESIGHT
530
531 #if NRF_TAMPC_HAS_WARMBOOT
532 /**
533 * @brief Function for setting signal value of the warm boot register for given warm boot mode.
534 *
535 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
536 * @param[in] mode Warm boot mode to be modified.
537 * @param[in] enable True if signal is to be logic 1, false if logic 0.
538 */
539 NRF_STATIC_INLINE void nrf_tampc_warmboot_ctrl_value_set(NRF_TAMPC_Type * p_reg,
540 nrf_tampc_warmboot_mode_t mode,
541 bool enable);
542
543 /**
544 * @brief Function for getting the signal value of the warm boot register for given warm boot mode.
545 *
546 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
547 * @param[in] mode Warm boot mode to be retrieved.
548 *
549 * @retval true Signal is logic 1.
550 * @retval false Signal is logic 0.
551 */
552 NRF_STATIC_INLINE bool nrf_tampc_warmboot_ctrl_value_get(NRF_TAMPC_Type const * p_reg,
553 nrf_tampc_warmboot_mode_t mode);
554
555 /**
556 * @brief Function for setting lock value of the warm boot register for given warm boot mode.
557 *
558 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
559 * @param[in] mode Warm boot mode to be modified.
560 * @param[in] enable True if register is to be locked, false otherwise.
561 */
562 NRF_STATIC_INLINE void nrf_tampc_warmboot_ctrl_lock_set(NRF_TAMPC_Type * p_reg,
563 nrf_tampc_warmboot_mode_t mode,
564 bool enable);
565
566 /**
567 * @brief Function for getting the lock value of the warm boot register for given warm boot mode.
568 *
569 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
570 * @param[in] mode Warm boot mode to be retrieved.
571 *
572 * @retval true Register is locked.
573 * @retval false Register is unlocked.
574 */
575 NRF_STATIC_INLINE bool nrf_tampc_warmboot_ctrl_lock_get(NRF_TAMPC_Type const * p_reg,
576 nrf_tampc_warmboot_mode_t mode);
577
578 /**
579 * @brief Function for setting fault injection of the warm boot register for given warm boot mode.
580 *
581 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
582 * @param[in] mode Warm boot mode to be modified.
583 * @param[in] enable True if fault is to be injected, false otherwise.
584 */
585 NRF_STATIC_INLINE void nrf_tampc_warmboot_ctrl_fault_set(NRF_TAMPC_Type * p_reg,
586 nrf_tampc_warmboot_mode_t mode,
587 bool enable);
588
589 /**
590 * @brief Function for getting the fault injection of the warm boot register for given warm boot mode.
591 *
592 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
593 * @param[in] mode Warm boot mode to be retrieved.
594 *
595 * @retval true Fault is to be injected.
596 * @retval false No operation.
597 */
598 NRF_STATIC_INLINE bool nrf_tampc_warmboot_ctrl_fault_get(NRF_TAMPC_Type const * p_reg,
599 nrf_tampc_warmboot_mode_t mode);
600
601 /**
602 * @brief Function for checking the error detection status for given warm boot mode.
603 *
604 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
605 * @param[in] mode Warm boot mode for which to retrieve the error status.
606 *
607 * @retval true Error detected.
608 * @retval false No error detected.
609 */
610 NRF_STATIC_INLINE bool nrf_tampc_warmboot_status_check(NRF_TAMPC_Type const * p_reg,
611 nrf_tampc_warmboot_mode_t mode);
612
613 /**
614 * @brief Function for clearing the error detection status for given warm boot mode.
615 *
616 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
617 * @param[in] mode Warm boot mode for which the error status is to be cleared.
618 */
619 NRF_STATIC_INLINE void nrf_tampc_warmboot_status_clear(NRF_TAMPC_Type * p_reg,
620 nrf_tampc_warmboot_mode_t mode);
621 #endif // NRF_TAMPC_HAS_WARMBOOT
622
623 #if NRF_TAMPC_HAS_EXTENDED_PROTECTORS
624 /**
625 * @brief Function for setting signal value of the given signal protector register.
626 *
627 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
628 * @param[in] ctrl Signal protector control register to be modified.
629 * @param[in] enable True if signal is to be logic 1, false if logic 0.
630 */
631 NRF_STATIC_INLINE void nrf_tampc_protector_ctrl_value_set(NRF_TAMPC_Type * p_reg,
632 nrf_tampc_protect_t ctrl,
633 bool enable);
634
635 /**
636 * @brief Function for getting the signal value of the given signal protector register.
637 *
638 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
639 * @param[in] ctrl Signal protector control register to be retrieved.
640 *
641 * @retval true Signal is logic 1.
642 * @retval false Signal is logic 0.
643 */
644 NRF_STATIC_INLINE bool nrf_tampc_protector_ctrl_value_get(NRF_TAMPC_Type const * p_reg,
645 nrf_tampc_protect_t ctrl);
646
647 /**
648 * @brief Function for setting lock value of the given signal protector register.
649 *
650 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
651 * @param[in] ctrl Signal protector control register to be modified.
652 * @param[in] enable True if register is to be locked, false otherwise.
653 */
654 NRF_STATIC_INLINE void nrf_tampc_protector_ctrl_lock_set(NRF_TAMPC_Type * p_reg,
655 nrf_tampc_protect_t ctrl,
656 bool enable);
657
658 /**
659 * @brief Function for getting the lock value of the given signal protector register.
660 *
661 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
662 * @param[in] ctrl Signal protector control register to be retrieved.
663 *
664 * @retval true Register is locked.
665 * @retval false Register is unlocked.
666 */
667 NRF_STATIC_INLINE bool nrf_tampc_protector_ctrl_lock_get(NRF_TAMPC_Type const * p_reg,
668 nrf_tampc_protect_t ctrl);
669
670 /**
671 * @brief Function for checking the error detection status for given signal protector status register.
672 *
673 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
674 * @param[in] status Signal protector status register for which to retrieve the error status.
675 *
676 * @retval true Error detected.
677 * @retval false No error detected.
678 */
679 NRF_STATIC_INLINE bool nrf_tampc_protector_status_check(NRF_TAMPC_Type const * p_reg,
680 nrf_tampc_protect_t status);
681
682 /**
683 * @brief Function for clearing the error detection status for given signal protector status register.
684 *
685 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
686 * @param[in] status Signal protector status register for which the error status is to be cleared.
687 */
688 NRF_STATIC_INLINE void nrf_tampc_protector_status_clear(NRF_TAMPC_Type * p_reg,
689 nrf_tampc_protect_t status);
690 #endif // NRF_TAMPC_HAS_EXTENDED_PROTECTORS
691
692 #ifndef NRF_DECLARE_ONLY
693
nrf_tampc_event_clear(NRF_TAMPC_Type * p_reg,nrf_tampc_event_t event)694 NRF_STATIC_INLINE void nrf_tampc_event_clear(NRF_TAMPC_Type * p_reg, nrf_tampc_event_t event)
695 {
696 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
697 nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
698 }
699
nrf_tampc_event_check(NRF_TAMPC_Type const * p_reg,nrf_tampc_event_t event)700 NRF_STATIC_INLINE bool nrf_tampc_event_check(NRF_TAMPC_Type const * p_reg, nrf_tampc_event_t event)
701 {
702 return nrf_event_check(p_reg, event);
703 }
704
nrf_tampc_event_address_get(NRF_TAMPC_Type const * p_reg,nrf_tampc_event_t event)705 NRF_STATIC_INLINE uint32_t nrf_tampc_event_address_get(NRF_TAMPC_Type const * p_reg,
706 nrf_tampc_event_t event)
707 {
708 return nrf_task_event_address_get(p_reg, event);
709 }
710
nrf_tampc_int_enable(NRF_TAMPC_Type * p_reg,uint32_t mask)711 NRF_STATIC_INLINE void nrf_tampc_int_enable(NRF_TAMPC_Type * p_reg, uint32_t mask)
712 {
713 p_reg->INTENSET = mask;
714 }
715
nrf_tampc_int_disable(NRF_TAMPC_Type * p_reg,uint32_t mask)716 NRF_STATIC_INLINE void nrf_tampc_int_disable(NRF_TAMPC_Type * p_reg, uint32_t mask)
717 {
718 p_reg->INTENCLR = mask;
719 }
720
nrf_tampc_int_enable_check(NRF_TAMPC_Type const * p_reg,uint32_t mask)721 NRF_STATIC_INLINE uint32_t nrf_tampc_int_enable_check(NRF_TAMPC_Type const * p_reg, uint32_t mask)
722 {
723 return p_reg->INTENSET & mask;
724 }
725
nrf_tampc_int_pending_get(NRF_TAMPC_Type const * p_reg)726 NRF_STATIC_INLINE uint32_t nrf_tampc_int_pending_get(NRF_TAMPC_Type const * p_reg)
727 {
728 return p_reg->INTPEND;
729 }
730
nrf_tampc_detector_status_check(NRF_TAMPC_Type const * p_reg,nrf_tampc_detector_t detector)731 NRF_STATIC_INLINE bool nrf_tampc_detector_status_check(NRF_TAMPC_Type const * p_reg,
732 nrf_tampc_detector_t detector)
733 {
734 return ((p_reg->STATUS & detector) != 0);
735 }
736
nrf_tampc_detector_status_clear(NRF_TAMPC_Type * p_reg,nrf_tampc_detector_t detector)737 NRF_STATIC_INLINE void nrf_tampc_detector_status_clear(NRF_TAMPC_Type * p_reg,
738 nrf_tampc_detector_t detector)
739 {
740 #if NRF_TAMPC_HAS_EXTENDED_PROTECTORS
741 switch (detector)
742 {
743 case NRF_TAMPC_DETECTOR_GLITCH_DOMAIN_SLOW:
744 nrf_tampc_protector_ctrl_value_set(p_reg, NRF_TAMPC_PROTECT_GLITCH_DOMAIN_SLOW, false);
745 break;
746 case NRF_TAMPC_DETECTOR_GLITCH_DOMAIN_FAST:
747 nrf_tampc_protector_ctrl_value_set(p_reg, NRF_TAMPC_PROTECT_GLITCH_DOMAIN_FAST, false);
748 break;
749 default:
750 break;
751 }
752 #endif
753
754 #if NRF_TAMPC_HAS_DETECTORS_ENABLE
755 switch (detector)
756 {
757 case NRF_TAMPC_DETECTOR_GLITCH_DOMAIN_SLOW:
758 p_reg->ENABLE = ((p_reg->ENABLE & ~TAMPC_ENABLE_GLITCHSLOWDOMAIN_Msk) |
759 (TAMPC_ENABLE_GLITCHSLOWDOMAIN_Disabled << TAMPC_ENABLE_GLITCHSLOWDOMAIN_Pos));
760 break;
761 case NRF_TAMPC_DETECTOR_GLITCH_DOMAIN_FAST:
762 p_reg->ENABLE = ((p_reg->ENABLE & ~TAMPC_ENABLE_GLITCHFASTDOMAIN_Msk) |
763 (TAMPC_ENABLE_GLITCHFASTDOMAIN_Disabled << TAMPC_ENABLE_GLITCHFASTDOMAIN_Pos));
764 break;
765 default:
766 break;
767 }
768 #endif
769
770 p_reg->STATUS = detector;
771
772 #if NRF_TAMPC_HAS_DETECTORS_ENABLE
773 switch (detector)
774 {
775 case NRF_TAMPC_DETECTOR_GLITCH_DOMAIN_SLOW:
776 p_reg->ENABLE = ((p_reg->ENABLE & ~TAMPC_ENABLE_GLITCHSLOWDOMAIN_Msk) |
777 (TAMPC_ENABLE_GLITCHSLOWDOMAIN_Enabled << TAMPC_ENABLE_GLITCHSLOWDOMAIN_Pos));
778 break;
779 case NRF_TAMPC_DETECTOR_GLITCH_DOMAIN_FAST:
780 p_reg->ENABLE = ((p_reg->ENABLE & ~TAMPC_ENABLE_GLITCHFASTDOMAIN_Msk) |
781 (TAMPC_ENABLE_GLITCHFASTDOMAIN_Enabled << TAMPC_ENABLE_GLITCHFASTDOMAIN_Pos));
782 break;
783 default:
784 break;
785 }
786 #endif
787
788 #if NRF_TAMPC_HAS_EXTENDED_PROTECTORS
789 switch (detector)
790 {
791 case NRF_TAMPC_DETECTOR_GLITCH_DOMAIN_SLOW:
792 nrf_tampc_protector_ctrl_value_set(p_reg, NRF_TAMPC_PROTECT_GLITCH_DOMAIN_SLOW, true);
793 break;
794 case NRF_TAMPC_DETECTOR_GLITCH_DOMAIN_FAST:
795 nrf_tampc_protector_ctrl_value_set(p_reg, NRF_TAMPC_PROTECT_GLITCH_DOMAIN_FAST, true);
796 break;
797 default:
798 break;
799 }
800 #endif
801 }
802
803 #if NRF_TAMPC_HAS_ACTIVE_SHIELD_CHANNELS
nrf_tampc_activeshield_channel_enable(NRF_TAMPC_Type * p_reg,uint32_t mask)804 NRF_STATIC_INLINE void nrf_tampc_activeshield_channel_enable(NRF_TAMPC_Type * p_reg, uint32_t mask)
805 {
806 p_reg->ACTIVESHIELD.CHEN |= mask;
807 }
808
nrf_tampc_activeshield_channel_disable(NRF_TAMPC_Type * p_reg,uint32_t mask)809 NRF_STATIC_INLINE void nrf_tampc_activeshield_channel_disable(NRF_TAMPC_Type * p_reg,
810 uint32_t mask)
811 {
812 p_reg->ACTIVESHIELD.CHEN &= ~mask;
813 }
814
nrf_tampc_activeshield_channel_enable_check(NRF_TAMPC_Type const * p_reg,uint32_t mask)815 NRF_STATIC_INLINE uint32_t nrf_tampc_activeshield_channel_enable_check(NRF_TAMPC_Type const * p_reg,
816 uint32_t mask)
817 {
818 return p_reg->ACTIVESHIELD.CHEN & mask;
819 }
820 #endif
821
nrf_tampc_domain_ctrl_value_set(NRF_TAMPC_Type * p_reg,nrf_tampc_debug_type_t type,nrf_domain_t domain,bool enable)822 NRF_STATIC_INLINE void nrf_tampc_domain_ctrl_value_set(NRF_TAMPC_Type * p_reg,
823 nrf_tampc_debug_type_t type,
824 nrf_domain_t domain,
825 bool enable)
826 {
827 NRFX_ASSERT(domain > 0);
828 NRFX_ASSERT(domain < NRF_DOMAIN_COUNT);
829
830 switch (type)
831 {
832 case NRF_TAMPC_DEBUG_TYPE_DBGEN:
833 #if NRF_TAMPC_KEY_MASK
834 p_reg->PROTECT.DOMAIN[domain].DBGEN.CTRL =
835 (TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_WRITEPROTECTION_Clear
836 << TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_WRITEPROTECTION_Pos) | NRF_TAMPC_KEY_MASK;
837 #endif
838 p_reg->PROTECT.DOMAIN[domain].DBGEN.CTRL =
839 ((p_reg->PROTECT.DOMAIN[domain].DBGEN.CTRL &
840 ~TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_VALUE_Msk) |
841 ((enable ? TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_VALUE_High
842 : TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_VALUE_Low)
843 << TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_VALUE_Pos))
844 | NRF_TAMPC_KEY_MASK;
845 break;
846 case NRF_TAMPC_DEBUG_TYPE_NIDEN:
847 #if NRF_TAMPC_KEY_MASK
848 p_reg->PROTECT.DOMAIN[domain].NIDEN.CTRL =
849 (TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_WRITEPROTECTION_Clear
850 << TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_WRITEPROTECTION_Pos) | NRF_TAMPC_KEY_MASK;
851 #endif
852 p_reg->PROTECT.DOMAIN[domain].NIDEN.CTRL =
853 ((p_reg->PROTECT.DOMAIN[domain].NIDEN.CTRL &
854 ~TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_VALUE_Msk) |
855 ((enable ? TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_VALUE_High
856 : TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_VALUE_Low)
857 << TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_VALUE_Pos))
858 | NRF_TAMPC_KEY_MASK;
859 break;
860 case NRF_TAMPC_DEBUG_TYPE_SPIDEN:
861 #if NRF_TAMPC_KEY_MASK
862 p_reg->PROTECT.DOMAIN[domain].SPIDEN.CTRL =
863 (TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_WRITEPROTECTION_Clear
864 << TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_WRITEPROTECTION_Pos) | NRF_TAMPC_KEY_MASK;
865 #endif
866 p_reg->PROTECT.DOMAIN[domain].SPIDEN.CTRL =
867 ((p_reg->PROTECT.DOMAIN[domain].SPIDEN.CTRL &
868 ~TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_VALUE_Msk) |
869 ((enable ? TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_VALUE_High
870 : TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_VALUE_Low)
871 << TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_VALUE_Pos))
872 | NRF_TAMPC_KEY_MASK;
873 break;
874 case NRF_TAMPC_DEBUG_TYPE_SPNIDEN:
875 #if NRF_TAMPC_KEY_MASK
876 p_reg->PROTECT.DOMAIN[domain].SPNIDEN.CTRL =
877 (TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_WRITEPROTECTION_Clear
878 << TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_WRITEPROTECTION_Pos) | NRF_TAMPC_KEY_MASK;
879 #endif
880 p_reg->PROTECT.DOMAIN[domain].SPNIDEN.CTRL =
881 ((p_reg->PROTECT.DOMAIN[domain].SPNIDEN.CTRL &
882 ~TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_VALUE_Msk) |
883 ((enable ? TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_VALUE_High
884 : TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_VALUE_Low)
885 << TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_VALUE_Pos))
886 | NRF_TAMPC_KEY_MASK;
887 break;
888 default:
889 NRFX_ASSERT(0);
890 }
891 }
892
nrf_tampc_domain_ctrl_value_get(NRF_TAMPC_Type const * p_reg,nrf_tampc_debug_type_t type,nrf_domain_t domain)893 NRF_STATIC_INLINE bool nrf_tampc_domain_ctrl_value_get(NRF_TAMPC_Type const * p_reg,
894 nrf_tampc_debug_type_t type,
895 nrf_domain_t domain)
896 {
897 NRFX_ASSERT(domain > 0);
898 NRFX_ASSERT(domain < NRF_DOMAIN_COUNT);
899
900 switch (type)
901 {
902 case NRF_TAMPC_DEBUG_TYPE_DBGEN:
903 return ((p_reg->PROTECT.DOMAIN[domain].DBGEN.CTRL
904 & TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_VALUE_Msk)
905 >> TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_VALUE_Pos);
906 case NRF_TAMPC_DEBUG_TYPE_NIDEN:
907 return ((p_reg->PROTECT.DOMAIN[domain].NIDEN.CTRL
908 & TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_VALUE_Msk)
909 >> TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_VALUE_Pos);
910 case NRF_TAMPC_DEBUG_TYPE_SPIDEN:
911 return ((p_reg->PROTECT.DOMAIN[domain].SPIDEN.CTRL
912 & TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_VALUE_Msk)
913 >> TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_VALUE_Pos);
914 case NRF_TAMPC_DEBUG_TYPE_SPNIDEN:
915 return ((p_reg->PROTECT.DOMAIN[domain].SPNIDEN.CTRL
916 & TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_VALUE_Msk)
917 >> TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_VALUE_Pos);
918 default:
919 NRFX_ASSERT(0);
920 return false;
921 }
922 }
923
nrf_tampc_domain_ctrl_lock_set(NRF_TAMPC_Type * p_reg,nrf_tampc_debug_type_t type,nrf_domain_t domain,bool enable)924 NRF_STATIC_INLINE void nrf_tampc_domain_ctrl_lock_set(NRF_TAMPC_Type * p_reg,
925 nrf_tampc_debug_type_t type,
926 nrf_domain_t domain,
927 bool enable)
928 {
929 NRFX_ASSERT(domain > 0);
930 NRFX_ASSERT(domain < NRF_DOMAIN_COUNT);
931
932 switch (type)
933 {
934 case NRF_TAMPC_DEBUG_TYPE_DBGEN:
935 #if NRF_TAMPC_KEY_MASK
936 p_reg->PROTECT.DOMAIN[domain].DBGEN.CTRL =
937 (TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_WRITEPROTECTION_Clear
938 << TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_WRITEPROTECTION_Pos) | NRF_TAMPC_KEY_MASK;
939 #endif
940 p_reg->PROTECT.DOMAIN[domain].DBGEN.CTRL =
941 ((p_reg->PROTECT.DOMAIN[domain].DBGEN.CTRL &
942 ~TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_LOCK_Msk) |
943 ((enable ? TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_LOCK_Enabled
944 : TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_LOCK_Disabled)
945 << TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_LOCK_Pos))
946 | NRF_TAMPC_KEY_MASK;
947 break;
948 case NRF_TAMPC_DEBUG_TYPE_NIDEN:
949 #if NRF_TAMPC_KEY_MASK
950 p_reg->PROTECT.DOMAIN[domain].NIDEN.CTRL =
951 (TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_WRITEPROTECTION_Clear
952 << TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_WRITEPROTECTION_Pos) | NRF_TAMPC_KEY_MASK;
953 #endif
954 p_reg->PROTECT.DOMAIN[domain].NIDEN.CTRL =
955 ((p_reg->PROTECT.DOMAIN[domain].NIDEN.CTRL &
956 ~TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_LOCK_Msk) |
957 ((enable ? TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_LOCK_Enabled
958 : TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_LOCK_Disabled)
959 << TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_LOCK_Pos))
960 | NRF_TAMPC_KEY_MASK;
961 break;
962 case NRF_TAMPC_DEBUG_TYPE_SPIDEN:
963 #if NRF_TAMPC_KEY_MASK
964 p_reg->PROTECT.DOMAIN[domain].SPIDEN.CTRL =
965 (TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_WRITEPROTECTION_Clear
966 << TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_WRITEPROTECTION_Pos) | NRF_TAMPC_KEY_MASK;
967 #endif
968 p_reg->PROTECT.DOMAIN[domain].SPIDEN.CTRL =
969 ((p_reg->PROTECT.DOMAIN[domain].SPIDEN.CTRL &
970 ~TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_LOCK_Msk) |
971 ((enable ? TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_LOCK_Enabled
972 : TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_LOCK_Disabled)
973 << TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_LOCK_Pos))
974 | NRF_TAMPC_KEY_MASK;
975 break;
976 case NRF_TAMPC_DEBUG_TYPE_SPNIDEN:
977 #if NRF_TAMPC_KEY_MASK
978 p_reg->PROTECT.DOMAIN[domain].SPNIDEN.CTRL =
979 (TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_WRITEPROTECTION_Clear
980 << TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_WRITEPROTECTION_Pos) | NRF_TAMPC_KEY_MASK;
981 #endif
982 p_reg->PROTECT.DOMAIN[domain].SPNIDEN.CTRL =
983 ((p_reg->PROTECT.DOMAIN[domain].SPNIDEN.CTRL &
984 ~TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_LOCK_Msk) |
985 ((enable ? TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_LOCK_Enabled
986 : TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_LOCK_Disabled)
987 << TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_LOCK_Pos))
988 | NRF_TAMPC_KEY_MASK;
989 break;
990 default:
991 NRFX_ASSERT(0);
992 }
993 }
994
nrf_tampc_domain_ctrl_lock_get(NRF_TAMPC_Type const * p_reg,nrf_tampc_debug_type_t type,nrf_domain_t domain)995 NRF_STATIC_INLINE bool nrf_tampc_domain_ctrl_lock_get(NRF_TAMPC_Type const * p_reg,
996 nrf_tampc_debug_type_t type,
997 nrf_domain_t domain)
998 {
999 NRFX_ASSERT(domain > 0);
1000 NRFX_ASSERT(domain < NRF_DOMAIN_COUNT);
1001
1002 switch (type)
1003 {
1004 case NRF_TAMPC_DEBUG_TYPE_DBGEN:
1005 return ((p_reg->PROTECT.DOMAIN[domain].DBGEN.CTRL
1006 & TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_LOCK_Msk)
1007 >> TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_LOCK_Pos);
1008 case NRF_TAMPC_DEBUG_TYPE_NIDEN:
1009 return ((p_reg->PROTECT.DOMAIN[domain].NIDEN.CTRL
1010 & TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_LOCK_Msk)
1011 >> TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_LOCK_Pos);
1012 case NRF_TAMPC_DEBUG_TYPE_SPIDEN:
1013 return ((p_reg->PROTECT.DOMAIN[domain].SPIDEN.CTRL
1014 & TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_LOCK_Msk)
1015 >> TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_LOCK_Pos);
1016 case NRF_TAMPC_DEBUG_TYPE_SPNIDEN:
1017 return ((p_reg->PROTECT.DOMAIN[domain].SPNIDEN.CTRL
1018 & TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_LOCK_Msk)
1019 >> TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_LOCK_Pos);
1020 default:
1021 NRFX_ASSERT(0);
1022 return false;
1023 }
1024 }
1025
nrf_tampc_ap_ctrl_value_set(NRF_TAMPC_Type * p_reg,nrf_tampc_debug_type_t type,nrf_domain_t domain,bool enable)1026 NRF_STATIC_INLINE void nrf_tampc_ap_ctrl_value_set(NRF_TAMPC_Type * p_reg,
1027 nrf_tampc_debug_type_t type,
1028 nrf_domain_t domain,
1029 bool enable)
1030 {
1031 NRFX_ASSERT(domain > 0);
1032 NRFX_ASSERT(domain < NRF_DOMAIN_COUNT);
1033
1034 switch (type)
1035 {
1036 case NRF_TAMPC_DEBUG_TYPE_DBGEN:
1037 #if NRF_TAMPC_KEY_MASK
1038 p_reg->PROTECT.AP[domain].DBGEN.CTRL =
1039 (TAMPC_PROTECT_AP_DBGEN_CTRL_WRITEPROTECTION_Clear
1040 << TAMPC_PROTECT_AP_DBGEN_CTRL_WRITEPROTECTION_Pos) | NRF_TAMPC_KEY_MASK;
1041 #endif
1042 p_reg->PROTECT.AP[domain].DBGEN.CTRL =
1043 ((p_reg->PROTECT.AP[domain].DBGEN.CTRL &
1044 ~TAMPC_PROTECT_AP_DBGEN_CTRL_VALUE_Msk) |
1045 ((enable ? TAMPC_PROTECT_AP_DBGEN_CTRL_VALUE_High :
1046 TAMPC_PROTECT_AP_DBGEN_CTRL_VALUE_Low)
1047 << TAMPC_PROTECT_AP_DBGEN_CTRL_VALUE_Pos))
1048 | NRF_TAMPC_KEY_MASK;
1049 break;
1050 #if NRF_TAMPC_HAS_AP_SPIDEN_PROTECTOR
1051 case NRF_TAMPC_DEBUG_TYPE_SPIDEN:
1052 #if NRF_TAMPC_KEY_MASK
1053 p_reg->PROTECT.AP[domain].SPIDEN.CTRL =
1054 (TAMPC_PROTECT_AP_SPIDEN_CTRL_WRITEPROTECTION_Clear
1055 << TAMPC_PROTECT_AP_SPIDEN_CTRL_WRITEPROTECTION_Pos) | NRF_TAMPC_KEY_MASK;
1056 #endif
1057 p_reg->PROTECT.AP[domain].SPIDEN.CTRL =
1058 ((p_reg->PROTECT.AP[domain].SPIDEN.CTRL &
1059 ~TAMPC_PROTECT_AP_SPIDEN_CTRL_VALUE_Msk) |
1060 ((enable ? TAMPC_PROTECT_AP_SPIDEN_CTRL_VALUE_High :
1061 TAMPC_PROTECT_AP_SPIDEN_CTRL_VALUE_Low)
1062 << TAMPC_PROTECT_AP_SPIDEN_CTRL_VALUE_Pos))
1063 | NRF_TAMPC_KEY_MASK;
1064 break;
1065 #endif
1066 default:
1067 NRFX_ASSERT(0);
1068 }
1069 }
1070
nrf_tampc_ap_ctrl_value_get(NRF_TAMPC_Type const * p_reg,nrf_tampc_debug_type_t type,nrf_domain_t domain)1071 NRF_STATIC_INLINE bool nrf_tampc_ap_ctrl_value_get(NRF_TAMPC_Type const * p_reg,
1072 nrf_tampc_debug_type_t type,
1073 nrf_domain_t domain)
1074 {
1075 NRFX_ASSERT(domain > 0);
1076 NRFX_ASSERT(domain < NRF_DOMAIN_COUNT);
1077
1078 switch (type)
1079 {
1080 case NRF_TAMPC_DEBUG_TYPE_DBGEN:
1081 return ((p_reg->PROTECT.AP[domain].DBGEN.CTRL
1082 & TAMPC_PROTECT_AP_DBGEN_CTRL_VALUE_Msk)
1083 >> TAMPC_PROTECT_AP_DBGEN_CTRL_VALUE_Pos);
1084 #if NRF_TAMPC_HAS_AP_SPIDEN_PROTECTOR
1085 case NRF_TAMPC_DEBUG_TYPE_SPIDEN:
1086 return ((p_reg->PROTECT.AP[domain].SPIDEN.CTRL
1087 & TAMPC_PROTECT_AP_SPIDEN_CTRL_VALUE_Msk)
1088 >> TAMPC_PROTECT_AP_SPIDEN_CTRL_VALUE_Pos);
1089 #endif
1090 default:
1091 NRFX_ASSERT(0);
1092 return false;
1093 }
1094 }
1095
nrf_tampc_ap_ctrl_lock_set(NRF_TAMPC_Type * p_reg,nrf_tampc_debug_type_t type,nrf_domain_t domain,bool enable)1096 NRF_STATIC_INLINE void nrf_tampc_ap_ctrl_lock_set(NRF_TAMPC_Type * p_reg,
1097 nrf_tampc_debug_type_t type,
1098 nrf_domain_t domain,
1099 bool enable)
1100 {
1101 NRFX_ASSERT(domain > 0);
1102 NRFX_ASSERT(domain < NRF_DOMAIN_COUNT);
1103
1104 switch (type)
1105 {
1106 case NRF_TAMPC_DEBUG_TYPE_DBGEN:
1107 #if NRF_TAMPC_KEY_MASK
1108 p_reg->PROTECT.AP[domain].DBGEN.CTRL =
1109 (TAMPC_PROTECT_AP_DBGEN_CTRL_WRITEPROTECTION_Clear
1110 << TAMPC_PROTECT_AP_DBGEN_CTRL_WRITEPROTECTION_Pos) | NRF_TAMPC_KEY_MASK;
1111 #endif
1112 p_reg->PROTECT.AP[domain].DBGEN.CTRL =
1113 ((p_reg->PROTECT.AP[domain].DBGEN.CTRL &
1114 ~TAMPC_PROTECT_AP_DBGEN_CTRL_LOCK_Msk) |
1115 ((enable ? TAMPC_PROTECT_AP_DBGEN_CTRL_LOCK_Enabled :
1116 TAMPC_PROTECT_AP_DBGEN_CTRL_LOCK_Disabled)
1117 << TAMPC_PROTECT_AP_DBGEN_CTRL_LOCK_Pos))
1118 | NRF_TAMPC_KEY_MASK;
1119 break;
1120 #if NRF_TAMPC_HAS_AP_SPIDEN_PROTECTOR
1121 case NRF_TAMPC_DEBUG_TYPE_SPIDEN:
1122 #if NRF_TAMPC_KEY_MASK
1123 p_reg->PROTECT.AP[domain].SPIDEN.CTRL =
1124 (TAMPC_PROTECT_AP_SPIDEN_CTRL_WRITEPROTECTION_Clear
1125 << TAMPC_PROTECT_AP_SPIDEN_CTRL_WRITEPROTECTION_Pos) | NRF_TAMPC_KEY_MASK;
1126 #endif
1127 p_reg->PROTECT.AP[domain].SPIDEN.CTRL =
1128 ((p_reg->PROTECT.AP[domain].SPIDEN.CTRL &
1129 ~TAMPC_PROTECT_AP_SPIDEN_CTRL_LOCK_Msk) |
1130 ((enable ? TAMPC_PROTECT_AP_SPIDEN_CTRL_LOCK_Enabled :
1131 TAMPC_PROTECT_AP_SPIDEN_CTRL_LOCK_Disabled)
1132 << TAMPC_PROTECT_AP_SPIDEN_CTRL_LOCK_Pos))
1133 | NRF_TAMPC_KEY_MASK;
1134 break;
1135 #endif
1136 default:
1137 NRFX_ASSERT(0);
1138 }
1139 }
1140
nrf_tampc_ap_ctrl_lock_get(NRF_TAMPC_Type const * p_reg,nrf_tampc_debug_type_t type,nrf_domain_t domain)1141 NRF_STATIC_INLINE bool nrf_tampc_ap_ctrl_lock_get(NRF_TAMPC_Type const * p_reg,
1142 nrf_tampc_debug_type_t type,
1143 nrf_domain_t domain)
1144 {
1145 NRFX_ASSERT(domain > 0);
1146 NRFX_ASSERT(domain < NRF_DOMAIN_COUNT);
1147
1148 switch (type)
1149 {
1150 case NRF_TAMPC_DEBUG_TYPE_DBGEN:
1151 return ((p_reg->PROTECT.AP[domain].DBGEN.CTRL
1152 & TAMPC_PROTECT_AP_DBGEN_CTRL_LOCK_Msk)
1153 >> TAMPC_PROTECT_AP_DBGEN_CTRL_LOCK_Pos);
1154 #if NRF_TAMPC_HAS_AP_SPIDEN_PROTECTOR
1155 case NRF_TAMPC_DEBUG_TYPE_SPIDEN:
1156 return ((p_reg->PROTECT.AP[domain].SPIDEN.CTRL
1157 & TAMPC_PROTECT_AP_SPIDEN_CTRL_LOCK_Msk)
1158 >> TAMPC_PROTECT_AP_SPIDEN_CTRL_LOCK_Pos);
1159 #endif
1160 default:
1161 NRFX_ASSERT(0);
1162 return false;
1163 }
1164 }
1165
1166 #if NRF_TAMPC_HAS_CORESIGHT
nrf_tampc_coresight_ctrl_value_set(NRF_TAMPC_Type * p_reg,nrf_tampc_debug_type_t type,bool enable)1167 NRF_STATIC_INLINE void nrf_tampc_coresight_ctrl_value_set(NRF_TAMPC_Type * p_reg,
1168 nrf_tampc_debug_type_t type,
1169 bool enable)
1170 {
1171 switch (type)
1172 {
1173 case NRF_TAMPC_DEBUG_TYPE_DEVICEEN:
1174 #if NRF_TAMPC_KEY_MASK
1175 p_reg->PROTECT.CORESIGHT.DEVICEEN.CTRL =
1176 (TAMPC_PROTECT_CORESIGHT_DEVICEEN_CTRL_WRITEPROTECTION_Clear
1177 << TAMPC_PROTECT_CORESIGHT_DEVICEEN_CTRL_WRITEPROTECTION_Pos) | NRF_TAMPC_KEY_MASK;
1178 #endif
1179 p_reg->PROTECT.CORESIGHT.DEVICEEN.CTRL =
1180 ((p_reg->PROTECT.CORESIGHT.DEVICEEN.CTRL &
1181 ~TAMPC_PROTECT_CORESIGHT_DEVICEEN_CTRL_VALUE_Msk) |
1182 ((enable ? TAMPC_PROTECT_CORESIGHT_DEVICEEN_CTRL_VALUE_High :
1183 TAMPC_PROTECT_CORESIGHT_DEVICEEN_CTRL_VALUE_Low)
1184 << TAMPC_PROTECT_CORESIGHT_DEVICEEN_CTRL_VALUE_Pos))
1185 | NRF_TAMPC_KEY_MASK;
1186 break;
1187 case NRF_TAMPC_DEBUG_TYPE_DBGEN:
1188 #if NRF_TAMPC_KEY_MASK
1189 p_reg->PROTECT.CORESIGHT.DBGEN.CTRL =
1190 (TAMPC_PROTECT_CORESIGHT_DBGEN_CTRL_WRITEPROTECTION_Clear
1191 << TAMPC_PROTECT_CORESIGHT_DBGEN_CTRL_WRITEPROTECTION_Pos) | NRF_TAMPC_KEY_MASK;
1192 #endif
1193 p_reg->PROTECT.CORESIGHT.DBGEN.CTRL =
1194 ((p_reg->PROTECT.CORESIGHT.DBGEN.CTRL &
1195 ~TAMPC_PROTECT_CORESIGHT_DBGEN_CTRL_VALUE_Msk) |
1196 ((enable ? TAMPC_PROTECT_CORESIGHT_DBGEN_CTRL_VALUE_High :
1197 TAMPC_PROTECT_CORESIGHT_DBGEN_CTRL_VALUE_Low)
1198 << TAMPC_PROTECT_CORESIGHT_DBGEN_CTRL_VALUE_Pos))
1199 | NRF_TAMPC_KEY_MASK;
1200 break;
1201 case NRF_TAMPC_DEBUG_TYPE_NIDEN:
1202 #if NRF_TAMPC_KEY_MASK
1203 p_reg->PROTECT.CORESIGHT.NIDEN.CTRL =
1204 (TAMPC_PROTECT_CORESIGHT_NIDEN_CTRL_WRITEPROTECTION_Clear
1205 << TAMPC_PROTECT_CORESIGHT_NIDEN_CTRL_WRITEPROTECTION_Pos) | NRF_TAMPC_KEY_MASK;
1206 #endif
1207 p_reg->PROTECT.CORESIGHT.NIDEN.CTRL =
1208 ((p_reg->PROTECT.CORESIGHT.NIDEN.CTRL &
1209 ~TAMPC_PROTECT_CORESIGHT_NIDEN_CTRL_VALUE_Msk) |
1210 ((enable ? TAMPC_PROTECT_CORESIGHT_NIDEN_CTRL_VALUE_High :
1211 TAMPC_PROTECT_CORESIGHT_NIDEN_CTRL_VALUE_Low)
1212 << TAMPC_PROTECT_CORESIGHT_NIDEN_CTRL_VALUE_Pos))
1213 | NRF_TAMPC_KEY_MASK;
1214 break;
1215 case NRF_TAMPC_DEBUG_TYPE_SPIDEN:
1216 #if NRF_TAMPC_KEY_MASK
1217 p_reg->PROTECT.CORESIGHT.SPIDEN.CTRL =
1218 (TAMPC_PROTECT_CORESIGHT_SPIDEN_CTRL_WRITEPROTECTION_Clear
1219 << TAMPC_PROTECT_CORESIGHT_SPIDEN_CTRL_WRITEPROTECTION_Pos) | NRF_TAMPC_KEY_MASK;
1220 #endif
1221 p_reg->PROTECT.CORESIGHT.SPIDEN.CTRL =
1222 ((p_reg->PROTECT.CORESIGHT.SPIDEN.CTRL &
1223 ~TAMPC_PROTECT_CORESIGHT_SPIDEN_CTRL_VALUE_Msk) |
1224 ((enable ? TAMPC_PROTECT_CORESIGHT_SPIDEN_CTRL_VALUE_High :
1225 TAMPC_PROTECT_CORESIGHT_SPIDEN_CTRL_VALUE_Low)
1226 << TAMPC_PROTECT_CORESIGHT_SPIDEN_CTRL_VALUE_Pos))
1227 | NRF_TAMPC_KEY_MASK;
1228 break;
1229 case NRF_TAMPC_DEBUG_TYPE_SPNIDEN:
1230 #if NRF_TAMPC_KEY_MASK
1231 p_reg->PROTECT.CORESIGHT.SPNIDEN.CTRL =
1232 (TAMPC_PROTECT_CORESIGHT_SPNIDEN_CTRL_WRITEPROTECTION_Clear
1233 << TAMPC_PROTECT_CORESIGHT_SPNIDEN_CTRL_WRITEPROTECTION_Pos) | NRF_TAMPC_KEY_MASK;
1234 #endif
1235 p_reg->PROTECT.CORESIGHT.SPNIDEN.CTRL =
1236 ((p_reg->PROTECT.CORESIGHT.SPNIDEN.CTRL &
1237 ~TAMPC_PROTECT_CORESIGHT_SPNIDEN_CTRL_VALUE_Msk) |
1238 ((enable ? TAMPC_PROTECT_CORESIGHT_SPNIDEN_CTRL_VALUE_High :
1239 TAMPC_PROTECT_CORESIGHT_SPNIDEN_CTRL_VALUE_Low)
1240 << TAMPC_PROTECT_CORESIGHT_SPNIDEN_CTRL_VALUE_Pos))
1241 | NRF_TAMPC_KEY_MASK;
1242 break;
1243 default:
1244 NRFX_ASSERT(0);
1245 }
1246 }
1247
nrf_tampc_coresight_ctrl_value_get(NRF_TAMPC_Type const * p_reg,nrf_tampc_debug_type_t type)1248 NRF_STATIC_INLINE bool nrf_tampc_coresight_ctrl_value_get(NRF_TAMPC_Type const * p_reg,
1249 nrf_tampc_debug_type_t type)
1250 {
1251 switch (type)
1252 {
1253 case NRF_TAMPC_DEBUG_TYPE_DEVICEEN:
1254 return ((p_reg->PROTECT.CORESIGHT.DEVICEEN.CTRL &
1255 TAMPC_PROTECT_CORESIGHT_DEVICEEN_CTRL_VALUE_Msk)
1256 >> TAMPC_PROTECT_CORESIGHT_DEVICEEN_CTRL_VALUE_Pos);
1257 case NRF_TAMPC_DEBUG_TYPE_DBGEN:
1258 return ((p_reg->PROTECT.CORESIGHT.DBGEN.CTRL &
1259 TAMPC_PROTECT_CORESIGHT_DBGEN_CTRL_VALUE_Msk)
1260 >> TAMPC_PROTECT_CORESIGHT_DBGEN_CTRL_VALUE_Pos);
1261 case NRF_TAMPC_DEBUG_TYPE_NIDEN:
1262 return ((p_reg->PROTECT.CORESIGHT.NIDEN.CTRL &
1263 TAMPC_PROTECT_CORESIGHT_NIDEN_CTRL_VALUE_Msk)
1264 >> TAMPC_PROTECT_CORESIGHT_NIDEN_CTRL_VALUE_Pos);
1265 case NRF_TAMPC_DEBUG_TYPE_SPIDEN:
1266 return ((p_reg->PROTECT.CORESIGHT.SPIDEN.CTRL &
1267 TAMPC_PROTECT_CORESIGHT_SPIDEN_CTRL_VALUE_Msk)
1268 >> TAMPC_PROTECT_CORESIGHT_SPIDEN_CTRL_VALUE_Pos);
1269 case NRF_TAMPC_DEBUG_TYPE_SPNIDEN:
1270 return ((p_reg->PROTECT.CORESIGHT.SPNIDEN.CTRL &
1271 TAMPC_PROTECT_CORESIGHT_SPNIDEN_CTRL_VALUE_Msk)
1272 >> TAMPC_PROTECT_CORESIGHT_SPNIDEN_CTRL_VALUE_Pos);
1273 default:
1274 NRFX_ASSERT(0);
1275 return false;
1276 }
1277 }
1278
nrf_tampc_coresight_ctrl_lock_set(NRF_TAMPC_Type * p_reg,nrf_tampc_debug_type_t type,bool enable)1279 NRF_STATIC_INLINE void nrf_tampc_coresight_ctrl_lock_set(NRF_TAMPC_Type * p_reg,
1280 nrf_tampc_debug_type_t type,
1281 bool enable)
1282 {
1283 switch (type)
1284 {
1285 case NRF_TAMPC_DEBUG_TYPE_DEVICEEN:
1286 #if NRF_TAMPC_KEY_MASK
1287 p_reg->PROTECT.CORESIGHT.DEVICEEN.CTRL =
1288 (TAMPC_PROTECT_CORESIGHT_DEVICEEN_CTRL_WRITEPROTECTION_Clear
1289 << TAMPC_PROTECT_CORESIGHT_DEVICEEN_CTRL_WRITEPROTECTION_Pos) | NRF_TAMPC_KEY_MASK;
1290 #endif
1291 p_reg->PROTECT.CORESIGHT.DEVICEEN.CTRL =
1292 ((p_reg->PROTECT.CORESIGHT.DEVICEEN.CTRL &
1293 ~TAMPC_PROTECT_CORESIGHT_DEVICEEN_CTRL_LOCK_Msk) |
1294 ((enable ? TAMPC_PROTECT_CORESIGHT_DEVICEEN_CTRL_LOCK_Enabled :
1295 TAMPC_PROTECT_CORESIGHT_DEVICEEN_CTRL_LOCK_Disabled)
1296 << TAMPC_PROTECT_CORESIGHT_DEVICEEN_CTRL_LOCK_Pos))
1297 | NRF_TAMPC_KEY_MASK;
1298 break;
1299 case NRF_TAMPC_DEBUG_TYPE_DBGEN:
1300 #if NRF_TAMPC_KEY_MASK
1301 p_reg->PROTECT.CORESIGHT.DBGEN.CTRL =
1302 (TAMPC_PROTECT_CORESIGHT_DBGEN_CTRL_WRITEPROTECTION_Clear
1303 << TAMPC_PROTECT_CORESIGHT_DBGEN_CTRL_WRITEPROTECTION_Pos) | NRF_TAMPC_KEY_MASK;
1304 #endif
1305 p_reg->PROTECT.CORESIGHT.DBGEN.CTRL =
1306 ((p_reg->PROTECT.CORESIGHT.DBGEN.CTRL &
1307 ~TAMPC_PROTECT_CORESIGHT_DBGEN_CTRL_LOCK_Msk) |
1308 ((enable ? TAMPC_PROTECT_CORESIGHT_DBGEN_CTRL_LOCK_Enabled :
1309 TAMPC_PROTECT_CORESIGHT_DBGEN_CTRL_LOCK_Disabled)
1310 << TAMPC_PROTECT_CORESIGHT_DBGEN_CTRL_LOCK_Pos))
1311 | NRF_TAMPC_KEY_MASK;
1312 break;
1313 case NRF_TAMPC_DEBUG_TYPE_NIDEN:
1314 #if NRF_TAMPC_KEY_MASK
1315 p_reg->PROTECT.CORESIGHT.NIDEN.CTRL =
1316 (TAMPC_PROTECT_CORESIGHT_NIDEN_CTRL_WRITEPROTECTION_Clear
1317 << TAMPC_PROTECT_CORESIGHT_NIDEN_CTRL_WRITEPROTECTION_Pos) | NRF_TAMPC_KEY_MASK;
1318 #endif
1319 p_reg->PROTECT.CORESIGHT.NIDEN.CTRL =
1320 ((p_reg->PROTECT.CORESIGHT.NIDEN.CTRL &
1321 ~TAMPC_PROTECT_CORESIGHT_NIDEN_CTRL_LOCK_Msk) |
1322 ((enable ? TAMPC_PROTECT_CORESIGHT_NIDEN_CTRL_LOCK_Enabled :
1323 TAMPC_PROTECT_CORESIGHT_NIDEN_CTRL_LOCK_Disabled)
1324 << TAMPC_PROTECT_CORESIGHT_NIDEN_CTRL_LOCK_Pos))
1325 | NRF_TAMPC_KEY_MASK;
1326 break;
1327 case NRF_TAMPC_DEBUG_TYPE_SPIDEN:
1328 #if NRF_TAMPC_KEY_MASK
1329 p_reg->PROTECT.CORESIGHT.SPIDEN.CTRL =
1330 (TAMPC_PROTECT_CORESIGHT_SPIDEN_CTRL_WRITEPROTECTION_Clear
1331 << TAMPC_PROTECT_CORESIGHT_SPIDEN_CTRL_WRITEPROTECTION_Pos) | NRF_TAMPC_KEY_MASK;
1332 #endif
1333 p_reg->PROTECT.CORESIGHT.SPIDEN.CTRL =
1334 ((p_reg->PROTECT.CORESIGHT.SPIDEN.CTRL &
1335 ~TAMPC_PROTECT_CORESIGHT_SPIDEN_CTRL_LOCK_Msk) |
1336 ((enable ? TAMPC_PROTECT_CORESIGHT_SPIDEN_CTRL_LOCK_Enabled :
1337 TAMPC_PROTECT_CORESIGHT_SPIDEN_CTRL_LOCK_Disabled)
1338 << TAMPC_PROTECT_CORESIGHT_SPIDEN_CTRL_LOCK_Pos))
1339 | NRF_TAMPC_KEY_MASK;
1340 break;
1341 case NRF_TAMPC_DEBUG_TYPE_SPNIDEN:
1342 #if NRF_TAMPC_KEY_MASK
1343 p_reg->PROTECT.CORESIGHT.SPNIDEN.CTRL =
1344 (TAMPC_PROTECT_CORESIGHT_SPNIDEN_CTRL_WRITEPROTECTION_Clear
1345 << TAMPC_PROTECT_CORESIGHT_SPNIDEN_CTRL_WRITEPROTECTION_Pos) | NRF_TAMPC_KEY_MASK;
1346 #endif
1347 p_reg->PROTECT.CORESIGHT.SPNIDEN.CTRL =
1348 ((p_reg->PROTECT.CORESIGHT.SPNIDEN.CTRL &
1349 ~TAMPC_PROTECT_CORESIGHT_SPNIDEN_CTRL_LOCK_Msk) |
1350 ((enable ? TAMPC_PROTECT_CORESIGHT_SPNIDEN_CTRL_LOCK_Enabled :
1351 TAMPC_PROTECT_CORESIGHT_SPNIDEN_CTRL_LOCK_Disabled)
1352 << TAMPC_PROTECT_CORESIGHT_SPNIDEN_CTRL_LOCK_Pos))
1353 | NRF_TAMPC_KEY_MASK;
1354 break;
1355 default:
1356 NRFX_ASSERT(0);
1357 }
1358 }
1359
nrf_tampc_coresight_ctrl_lock_get(NRF_TAMPC_Type const * p_reg,nrf_tampc_debug_type_t type)1360 NRF_STATIC_INLINE bool nrf_tampc_coresight_ctrl_lock_get(NRF_TAMPC_Type const * p_reg,
1361 nrf_tampc_debug_type_t type)
1362 {
1363 switch (type)
1364 {
1365 case NRF_TAMPC_DEBUG_TYPE_DEVICEEN:
1366 return ((p_reg->PROTECT.CORESIGHT.DEVICEEN.CTRL &
1367 TAMPC_PROTECT_CORESIGHT_DEVICEEN_CTRL_LOCK_Msk)
1368 >> TAMPC_PROTECT_CORESIGHT_DEVICEEN_CTRL_LOCK_Pos);
1369 case NRF_TAMPC_DEBUG_TYPE_DBGEN:
1370 return ((p_reg->PROTECT.CORESIGHT.DBGEN.CTRL &
1371 TAMPC_PROTECT_CORESIGHT_DBGEN_CTRL_LOCK_Msk)
1372 >> TAMPC_PROTECT_CORESIGHT_DBGEN_CTRL_LOCK_Pos);
1373 case NRF_TAMPC_DEBUG_TYPE_NIDEN:
1374 return ((p_reg->PROTECT.CORESIGHT.NIDEN.CTRL &
1375 TAMPC_PROTECT_CORESIGHT_NIDEN_CTRL_LOCK_Msk)
1376 >> TAMPC_PROTECT_CORESIGHT_NIDEN_CTRL_LOCK_Pos);
1377 case NRF_TAMPC_DEBUG_TYPE_SPIDEN:
1378 return ((p_reg->PROTECT.CORESIGHT.SPIDEN.CTRL &
1379 TAMPC_PROTECT_CORESIGHT_SPIDEN_CTRL_LOCK_Msk)
1380 >> TAMPC_PROTECT_CORESIGHT_SPIDEN_CTRL_LOCK_Pos);
1381 case NRF_TAMPC_DEBUG_TYPE_SPNIDEN:
1382 return ((p_reg->PROTECT.CORESIGHT.SPNIDEN.CTRL &
1383 TAMPC_PROTECT_CORESIGHT_SPNIDEN_CTRL_LOCK_Msk)
1384 >> TAMPC_PROTECT_CORESIGHT_SPNIDEN_CTRL_LOCK_Pos);
1385 default:
1386 NRFX_ASSERT(0);
1387 return false;
1388 }
1389 }
1390
nrf_tampc_coresight_ctrl_fault_set(NRF_TAMPC_Type * p_reg,nrf_tampc_debug_type_t type,bool enable)1391 NRF_STATIC_INLINE void nrf_tampc_coresight_ctrl_fault_set(NRF_TAMPC_Type * p_reg,
1392 nrf_tampc_debug_type_t type,
1393 bool enable)
1394 {
1395 switch (type)
1396 {
1397 case NRF_TAMPC_DEBUG_TYPE_DEVICEEN:
1398 #if NRF_TAMPC_KEY_MASK
1399 p_reg->PROTECT.CORESIGHT.DEVICEEN.CTRL =
1400 (TAMPC_PROTECT_CORESIGHT_DEVICEEN_CTRL_WRITEPROTECTION_Clear
1401 << TAMPC_PROTECT_CORESIGHT_DEVICEEN_CTRL_WRITEPROTECTION_Pos) | NRF_TAMPC_KEY_MASK;
1402 #endif
1403 p_reg->PROTECT.CORESIGHT.DEVICEEN.CTRL =
1404 ((p_reg->PROTECT.CORESIGHT.DEVICEEN.CTRL &
1405 ~TAMPC_PROTECT_CORESIGHT_DEVICEEN_CTRL_FAULTTEST_Msk) |
1406 ((enable ? TAMPC_PROTECT_CORESIGHT_DEVICEEN_CTRL_FAULTTEST_Trigger :
1407 TAMPC_PROTECT_CORESIGHT_DEVICEEN_CTRL_FAULTTEST_NoOperation)
1408 << TAMPC_PROTECT_CORESIGHT_DEVICEEN_CTRL_FAULTTEST_Pos))
1409 | NRF_TAMPC_KEY_MASK;
1410 break;
1411 case NRF_TAMPC_DEBUG_TYPE_DBGEN:
1412 #if NRF_TAMPC_KEY_MASK
1413 p_reg->PROTECT.CORESIGHT.DBGEN.CTRL =
1414 (TAMPC_PROTECT_CORESIGHT_DBGEN_CTRL_WRITEPROTECTION_Clear
1415 << TAMPC_PROTECT_CORESIGHT_DBGEN_CTRL_WRITEPROTECTION_Pos) | NRF_TAMPC_KEY_MASK;
1416 #endif
1417 p_reg->PROTECT.CORESIGHT.DBGEN.CTRL =
1418 ((p_reg->PROTECT.CORESIGHT.DBGEN.CTRL &
1419 ~TAMPC_PROTECT_CORESIGHT_DBGEN_CTRL_FAULTTEST_Msk) |
1420 ((enable ? TAMPC_PROTECT_CORESIGHT_DBGEN_CTRL_FAULTTEST_Trigger :
1421 TAMPC_PROTECT_CORESIGHT_DBGEN_CTRL_FAULTTEST_NoOperation)
1422 << TAMPC_PROTECT_CORESIGHT_DBGEN_CTRL_FAULTTEST_Pos))
1423 | NRF_TAMPC_KEY_MASK;
1424 break;
1425 case NRF_TAMPC_DEBUG_TYPE_NIDEN:
1426 #if NRF_TAMPC_KEY_MASK
1427 p_reg->PROTECT.CORESIGHT.NIDEN.CTRL =
1428 (TAMPC_PROTECT_CORESIGHT_NIDEN_CTRL_WRITEPROTECTION_Clear
1429 << TAMPC_PROTECT_CORESIGHT_NIDEN_CTRL_WRITEPROTECTION_Pos) | NRF_TAMPC_KEY_MASK;
1430 #endif
1431 p_reg->PROTECT.CORESIGHT.NIDEN.CTRL =
1432 ((p_reg->PROTECT.CORESIGHT.NIDEN.CTRL &
1433 ~TAMPC_PROTECT_CORESIGHT_NIDEN_CTRL_FAULTTEST_Msk) |
1434 ((enable ? TAMPC_PROTECT_CORESIGHT_NIDEN_CTRL_FAULTTEST_Trigger :
1435 TAMPC_PROTECT_CORESIGHT_NIDEN_CTRL_FAULTTEST_NoOperation)
1436 << TAMPC_PROTECT_CORESIGHT_NIDEN_CTRL_FAULTTEST_Pos))
1437 | NRF_TAMPC_KEY_MASK;
1438 break;
1439 case NRF_TAMPC_DEBUG_TYPE_SPIDEN:
1440 #if NRF_TAMPC_KEY_MASK
1441 p_reg->PROTECT.CORESIGHT.SPIDEN.CTRL =
1442 (TAMPC_PROTECT_CORESIGHT_SPIDEN_CTRL_WRITEPROTECTION_Clear
1443 << TAMPC_PROTECT_CORESIGHT_SPIDEN_CTRL_WRITEPROTECTION_Pos) | NRF_TAMPC_KEY_MASK;
1444 #endif
1445 p_reg->PROTECT.CORESIGHT.SPIDEN.CTRL =
1446 ((p_reg->PROTECT.CORESIGHT.SPIDEN.CTRL &
1447 ~TAMPC_PROTECT_CORESIGHT_SPIDEN_CTRL_FAULTTEST_Msk) |
1448 ((enable ? TAMPC_PROTECT_CORESIGHT_SPIDEN_CTRL_FAULTTEST_Trigger :
1449 TAMPC_PROTECT_CORESIGHT_SPIDEN_CTRL_FAULTTEST_NoOperation)
1450 << TAMPC_PROTECT_CORESIGHT_SPIDEN_CTRL_FAULTTEST_Pos))
1451 | NRF_TAMPC_KEY_MASK;
1452 break;
1453 case NRF_TAMPC_DEBUG_TYPE_SPNIDEN:
1454 #if NRF_TAMPC_KEY_MASK
1455 p_reg->PROTECT.CORESIGHT.SPNIDEN.CTRL =
1456 (TAMPC_PROTECT_CORESIGHT_SPNIDEN_CTRL_WRITEPROTECTION_Clear
1457 << TAMPC_PROTECT_CORESIGHT_SPNIDEN_CTRL_WRITEPROTECTION_Pos) | NRF_TAMPC_KEY_MASK;
1458 #endif
1459 p_reg->PROTECT.CORESIGHT.SPNIDEN.CTRL =
1460 ((p_reg->PROTECT.CORESIGHT.SPNIDEN.CTRL &
1461 ~TAMPC_PROTECT_CORESIGHT_SPNIDEN_CTRL_FAULTTEST_Msk) |
1462 ((enable ? TAMPC_PROTECT_CORESIGHT_SPNIDEN_CTRL_FAULTTEST_Trigger :
1463 TAMPC_PROTECT_CORESIGHT_SPNIDEN_CTRL_FAULTTEST_NoOperation)
1464 << TAMPC_PROTECT_CORESIGHT_SPNIDEN_CTRL_FAULTTEST_Pos))
1465 | NRF_TAMPC_KEY_MASK;
1466 break;
1467 default:
1468 NRFX_ASSERT(0);
1469 }
1470 }
1471
nrf_tampc_coresight_ctrl_fault_get(NRF_TAMPC_Type const * p_reg,nrf_tampc_debug_type_t type)1472 NRF_STATIC_INLINE bool nrf_tampc_coresight_ctrl_fault_get(NRF_TAMPC_Type const * p_reg,
1473 nrf_tampc_debug_type_t type)
1474 {
1475 switch (type)
1476 {
1477 case NRF_TAMPC_DEBUG_TYPE_DEVICEEN:
1478 return ((p_reg->PROTECT.CORESIGHT.DEVICEEN.CTRL &
1479 TAMPC_PROTECT_CORESIGHT_DEVICEEN_CTRL_FAULTTEST_Msk)
1480 >> TAMPC_PROTECT_CORESIGHT_DEVICEEN_CTRL_FAULTTEST_Pos);
1481 case NRF_TAMPC_DEBUG_TYPE_DBGEN:
1482 return ((p_reg->PROTECT.CORESIGHT.DBGEN.CTRL &
1483 TAMPC_PROTECT_CORESIGHT_DBGEN_CTRL_FAULTTEST_Msk)
1484 >> TAMPC_PROTECT_CORESIGHT_DBGEN_CTRL_FAULTTEST_Pos);
1485 case NRF_TAMPC_DEBUG_TYPE_NIDEN:
1486 return ((p_reg->PROTECT.CORESIGHT.NIDEN.CTRL &
1487 TAMPC_PROTECT_CORESIGHT_NIDEN_CTRL_FAULTTEST_Msk)
1488 >> TAMPC_PROTECT_CORESIGHT_NIDEN_CTRL_FAULTTEST_Pos);
1489 case NRF_TAMPC_DEBUG_TYPE_SPIDEN:
1490 return ((p_reg->PROTECT.CORESIGHT.SPIDEN.CTRL &
1491 TAMPC_PROTECT_CORESIGHT_SPIDEN_CTRL_FAULTTEST_Msk)
1492 >> TAMPC_PROTECT_CORESIGHT_SPIDEN_CTRL_FAULTTEST_Pos);
1493 case NRF_TAMPC_DEBUG_TYPE_SPNIDEN:
1494 return ((p_reg->PROTECT.CORESIGHT.SPNIDEN.CTRL &
1495 TAMPC_PROTECT_CORESIGHT_SPNIDEN_CTRL_FAULTTEST_Msk)
1496 >> TAMPC_PROTECT_CORESIGHT_SPNIDEN_CTRL_FAULTTEST_Pos);
1497 default:
1498 NRFX_ASSERT(0);
1499 return false;
1500 }
1501 }
1502 #endif // NRF_TAMPC_HAS_CORESIGHT
1503
1504 #if NRF_TAMPC_HAS_WARMBOOT
nrf_tampc_warmboot_ctrl_value_set(NRF_TAMPC_Type * p_reg,nrf_tampc_warmboot_mode_t mode,bool enable)1505 NRF_STATIC_INLINE void nrf_tampc_warmboot_ctrl_value_set(NRF_TAMPC_Type * p_reg,
1506 nrf_tampc_warmboot_mode_t mode,
1507 bool enable)
1508 {
1509 switch (mode)
1510 {
1511 case NRF_TAMPC_WARMBOOT_MODE_UNRET_IDLE:
1512 #if NRF_TAMPC_KEY_MASK
1513 p_reg->PROTECT.WARMBOOT.UNRETIDLE.CTRL =
1514 (TAMPC_PROTECT_WARMBOOT_UNRETIDLE_CTRL_WRITEPROTECTION_Clear
1515 << TAMPC_PROTECT_WARMBOOT_UNRETIDLE_CTRL_WRITEPROTECTION_Pos) | NRF_TAMPC_KEY_MASK;
1516 #endif
1517 p_reg->PROTECT.WARMBOOT.UNRETIDLE.CTRL =
1518 ((p_reg->PROTECT.WARMBOOT.UNRETIDLE.CTRL &
1519 ~TAMPC_PROTECT_WARMBOOT_UNRETIDLE_CTRL_VALUE_Msk) |
1520 ((enable ? TAMPC_PROTECT_WARMBOOT_UNRETIDLE_CTRL_VALUE_High :
1521 TAMPC_PROTECT_WARMBOOT_UNRETIDLE_CTRL_VALUE_Low)
1522 << TAMPC_PROTECT_WARMBOOT_UNRETIDLE_CTRL_VALUE_Pos))
1523 | NRF_TAMPC_KEY_MASK;
1524 break;
1525 case NRF_TAMPC_WARMBOOT_MODE_SYSTEMOFF:
1526 #if NRF_TAMPC_KEY_MASK
1527 p_reg->PROTECT.WARMBOOT.SYSTEMOFF.CTRL =
1528 (TAMPC_PROTECT_WARMBOOT_SYSTEMOFF_CTRL_WRITEPROTECTION_Clear
1529 << TAMPC_PROTECT_WARMBOOT_SYSTEMOFF_CTRL_WRITEPROTECTION_Pos) | NRF_TAMPC_KEY_MASK;
1530 #endif
1531 p_reg->PROTECT.WARMBOOT.SYSTEMOFF.CTRL =
1532 ((p_reg->PROTECT.WARMBOOT.SYSTEMOFF.CTRL &
1533 ~TAMPC_PROTECT_WARMBOOT_SYSTEMOFF_CTRL_VALUE_Msk) |
1534 ((enable ? TAMPC_PROTECT_WARMBOOT_SYSTEMOFF_CTRL_VALUE_High :
1535 TAMPC_PROTECT_WARMBOOT_SYSTEMOFF_CTRL_VALUE_Low)
1536 << TAMPC_PROTECT_WARMBOOT_SYSTEMOFF_CTRL_VALUE_Pos))
1537 | NRF_TAMPC_KEY_MASK;
1538 break;
1539 default:
1540 NRFX_ASSERT(0);
1541 }
1542 }
1543
nrf_tampc_warmboot_ctrl_value_get(NRF_TAMPC_Type const * p_reg,nrf_tampc_warmboot_mode_t mode)1544 NRF_STATIC_INLINE bool nrf_tampc_warmboot_ctrl_value_get(NRF_TAMPC_Type const * p_reg,
1545 nrf_tampc_warmboot_mode_t mode)
1546 {
1547 switch (mode)
1548 {
1549 case NRF_TAMPC_WARMBOOT_MODE_UNRET_IDLE:
1550 return ((p_reg->PROTECT.WARMBOOT.UNRETIDLE.CTRL &
1551 TAMPC_PROTECT_WARMBOOT_UNRETIDLE_CTRL_VALUE_Msk)
1552 >> TAMPC_PROTECT_WARMBOOT_UNRETIDLE_CTRL_VALUE_Pos);
1553 case NRF_TAMPC_WARMBOOT_MODE_SYSTEMOFF:
1554 return ((p_reg->PROTECT.WARMBOOT.SYSTEMOFF.CTRL &
1555 TAMPC_PROTECT_WARMBOOT_SYSTEMOFF_CTRL_VALUE_Msk)
1556 >> TAMPC_PROTECT_WARMBOOT_SYSTEMOFF_CTRL_VALUE_Pos);
1557 default:
1558 NRFX_ASSERT(0);
1559 return false;
1560 }
1561 }
1562
nrf_tampc_warmboot_ctrl_lock_set(NRF_TAMPC_Type * p_reg,nrf_tampc_warmboot_mode_t mode,bool enable)1563 NRF_STATIC_INLINE void nrf_tampc_warmboot_ctrl_lock_set(NRF_TAMPC_Type * p_reg,
1564 nrf_tampc_warmboot_mode_t mode,
1565 bool enable)
1566 {
1567 switch (mode)
1568 {
1569 case NRF_TAMPC_WARMBOOT_MODE_UNRET_IDLE:
1570 #if NRF_TAMPC_KEY_MASK
1571 p_reg->PROTECT.WARMBOOT.UNRETIDLE.CTRL =
1572 (TAMPC_PROTECT_WARMBOOT_UNRETIDLE_CTRL_WRITEPROTECTION_Clear
1573 << TAMPC_PROTECT_WARMBOOT_UNRETIDLE_CTRL_WRITEPROTECTION_Pos) | NRF_TAMPC_KEY_MASK;
1574 #endif
1575 p_reg->PROTECT.WARMBOOT.UNRETIDLE.CTRL =
1576 ((p_reg->PROTECT.WARMBOOT.UNRETIDLE.CTRL &
1577 ~TAMPC_PROTECT_WARMBOOT_UNRETIDLE_CTRL_LOCK_Msk) |
1578 ((enable ? TAMPC_PROTECT_WARMBOOT_UNRETIDLE_CTRL_LOCK_Enabled :
1579 TAMPC_PROTECT_WARMBOOT_UNRETIDLE_CTRL_LOCK_Disabled)
1580 << TAMPC_PROTECT_WARMBOOT_UNRETIDLE_CTRL_LOCK_Pos))
1581 | NRF_TAMPC_KEY_MASK;
1582 break;
1583 case NRF_TAMPC_WARMBOOT_MODE_SYSTEMOFF:
1584 #if NRF_TAMPC_KEY_MASK
1585 p_reg->PROTECT.WARMBOOT.SYSTEMOFF.CTRL =
1586 (TAMPC_PROTECT_WARMBOOT_SYSTEMOFF_CTRL_WRITEPROTECTION_Clear
1587 << TAMPC_PROTECT_WARMBOOT_SYSTEMOFF_CTRL_WRITEPROTECTION_Pos) | NRF_TAMPC_KEY_MASK;
1588 #endif
1589 p_reg->PROTECT.WARMBOOT.SYSTEMOFF.CTRL =
1590 ((p_reg->PROTECT.WARMBOOT.SYSTEMOFF.CTRL &
1591 ~TAMPC_PROTECT_WARMBOOT_SYSTEMOFF_CTRL_LOCK_Msk) |
1592 ((enable ? TAMPC_PROTECT_WARMBOOT_SYSTEMOFF_CTRL_LOCK_Enabled :
1593 TAMPC_PROTECT_WARMBOOT_SYSTEMOFF_CTRL_LOCK_Disabled)
1594 << TAMPC_PROTECT_WARMBOOT_SYSTEMOFF_CTRL_LOCK_Pos))
1595 | NRF_TAMPC_KEY_MASK;
1596 break;
1597 default:
1598 NRFX_ASSERT(0);
1599 }
1600 }
1601
nrf_tampc_warmboot_ctrl_lock_get(NRF_TAMPC_Type const * p_reg,nrf_tampc_warmboot_mode_t mode)1602 NRF_STATIC_INLINE bool nrf_tampc_warmboot_ctrl_lock_get(NRF_TAMPC_Type const * p_reg,
1603 nrf_tampc_warmboot_mode_t mode)
1604 {
1605 switch (mode)
1606 {
1607 case NRF_TAMPC_WARMBOOT_MODE_UNRET_IDLE:
1608 return ((p_reg->PROTECT.WARMBOOT.UNRETIDLE.CTRL &
1609 TAMPC_PROTECT_WARMBOOT_UNRETIDLE_CTRL_LOCK_Msk)
1610 >> TAMPC_PROTECT_WARMBOOT_UNRETIDLE_CTRL_LOCK_Pos);
1611 case NRF_TAMPC_WARMBOOT_MODE_SYSTEMOFF:
1612 return ((p_reg->PROTECT.WARMBOOT.SYSTEMOFF.CTRL &
1613 TAMPC_PROTECT_WARMBOOT_SYSTEMOFF_CTRL_LOCK_Msk)
1614 >> TAMPC_PROTECT_WARMBOOT_SYSTEMOFF_CTRL_LOCK_Pos);
1615 default:
1616 NRFX_ASSERT(0);
1617 return false;
1618 }
1619 }
1620
nrf_tampc_warmboot_ctrl_fault_set(NRF_TAMPC_Type * p_reg,nrf_tampc_warmboot_mode_t mode,bool enable)1621 NRF_STATIC_INLINE void nrf_tampc_warmboot_ctrl_fault_set(NRF_TAMPC_Type * p_reg,
1622 nrf_tampc_warmboot_mode_t mode,
1623 bool enable)
1624 {
1625 switch (mode)
1626 {
1627 case NRF_TAMPC_WARMBOOT_MODE_UNRET_IDLE:
1628 #if NRF_TAMPC_KEY_MASK
1629 p_reg->PROTECT.WARMBOOT.UNRETIDLE.CTRL =
1630 (TAMPC_PROTECT_WARMBOOT_UNRETIDLE_CTRL_WRITEPROTECTION_Clear
1631 << TAMPC_PROTECT_WARMBOOT_UNRETIDLE_CTRL_WRITEPROTECTION_Pos) | NRF_TAMPC_KEY_MASK;
1632 #endif
1633 p_reg->PROTECT.WARMBOOT.UNRETIDLE.CTRL =
1634 ((p_reg->PROTECT.WARMBOOT.UNRETIDLE.CTRL &
1635 ~TAMPC_PROTECT_WARMBOOT_UNRETIDLE_CTRL_FAULTTEST_Msk) |
1636 ((enable ? TAMPC_PROTECT_WARMBOOT_UNRETIDLE_CTRL_FAULTTEST_Trigger :
1637 TAMPC_PROTECT_WARMBOOT_UNRETIDLE_CTRL_FAULTTEST_NoOperation)
1638 << TAMPC_PROTECT_WARMBOOT_UNRETIDLE_CTRL_FAULTTEST_Pos))
1639 | NRF_TAMPC_KEY_MASK;
1640 break;
1641 case NRF_TAMPC_WARMBOOT_MODE_SYSTEMOFF:
1642 #if NRF_TAMPC_KEY_MASK
1643 p_reg->PROTECT.WARMBOOT.SYSTEMOFF.CTRL =
1644 (TAMPC_PROTECT_WARMBOOT_SYSTEMOFF_CTRL_WRITEPROTECTION_Clear
1645 << TAMPC_PROTECT_WARMBOOT_SYSTEMOFF_CTRL_WRITEPROTECTION_Pos) | NRF_TAMPC_KEY_MASK;
1646 #endif
1647 p_reg->PROTECT.WARMBOOT.SYSTEMOFF.CTRL =
1648 ((p_reg->PROTECT.WARMBOOT.SYSTEMOFF.CTRL &
1649 ~TAMPC_PROTECT_WARMBOOT_SYSTEMOFF_CTRL_FAULTTEST_Msk) |
1650 ((enable ? TAMPC_PROTECT_WARMBOOT_SYSTEMOFF_CTRL_FAULTTEST_Trigger :
1651 TAMPC_PROTECT_WARMBOOT_SYSTEMOFF_CTRL_FAULTTEST_NoOperation)
1652 << TAMPC_PROTECT_WARMBOOT_SYSTEMOFF_CTRL_FAULTTEST_Pos))
1653 | NRF_TAMPC_KEY_MASK;
1654 break;
1655 default:
1656 NRFX_ASSERT(0);
1657 }
1658 }
1659
nrf_tampc_warmboot_ctrl_fault_get(NRF_TAMPC_Type const * p_reg,nrf_tampc_warmboot_mode_t mode)1660 NRF_STATIC_INLINE bool nrf_tampc_warmboot_ctrl_fault_get(NRF_TAMPC_Type const * p_reg,
1661 nrf_tampc_warmboot_mode_t mode)
1662 {
1663 switch (mode)
1664 {
1665 case NRF_TAMPC_WARMBOOT_MODE_UNRET_IDLE:
1666 return ((p_reg->PROTECT.WARMBOOT.UNRETIDLE.CTRL &
1667 TAMPC_PROTECT_WARMBOOT_UNRETIDLE_CTRL_FAULTTEST_Msk)
1668 >> TAMPC_PROTECT_WARMBOOT_UNRETIDLE_CTRL_FAULTTEST_Pos);
1669 case NRF_TAMPC_WARMBOOT_MODE_SYSTEMOFF:
1670 return ((p_reg->PROTECT.WARMBOOT.SYSTEMOFF.CTRL &
1671 TAMPC_PROTECT_WARMBOOT_SYSTEMOFF_CTRL_FAULTTEST_Msk)
1672 >> TAMPC_PROTECT_WARMBOOT_SYSTEMOFF_CTRL_FAULTTEST_Pos);
1673 default:
1674 NRFX_ASSERT(0);
1675 return false;
1676 }
1677 }
1678
nrf_tampc_warmboot_status_check(NRF_TAMPC_Type const * p_reg,nrf_tampc_warmboot_mode_t mode)1679 NRF_STATIC_INLINE bool nrf_tampc_warmboot_status_check(NRF_TAMPC_Type const * p_reg,
1680 nrf_tampc_warmboot_mode_t mode)
1681 {
1682 switch (mode)
1683 {
1684 case NRF_TAMPC_WARMBOOT_MODE_UNRET_IDLE:
1685 return ((p_reg->PROTECT.WARMBOOT.UNRETIDLE.STATUS &
1686 TAMPC_PROTECT_WARMBOOT_UNRETIDLE_STATUS_ERROR_Msk)
1687 >> TAMPC_PROTECT_WARMBOOT_UNRETIDLE_STATUS_ERROR_Pos) ==
1688 TAMPC_PROTECT_WARMBOOT_UNRETIDLE_STATUS_ERROR_Error;
1689 case NRF_TAMPC_WARMBOOT_MODE_SYSTEMOFF:
1690 return ((p_reg->PROTECT.WARMBOOT.SYSTEMOFF.STATUS &
1691 TAMPC_PROTECT_WARMBOOT_SYSTEMOFF_STATUS_ERROR_Msk)
1692 >> TAMPC_PROTECT_WARMBOOT_SYSTEMOFF_STATUS_ERROR_Pos) ==
1693 TAMPC_PROTECT_WARMBOOT_SYSTEMOFF_STATUS_ERROR_Error;
1694 default:
1695 NRFX_ASSERT(0);
1696 return false;
1697 }
1698 }
1699
nrf_tampc_warmboot_status_clear(NRF_TAMPC_Type * p_reg,nrf_tampc_warmboot_mode_t mode)1700 NRF_STATIC_INLINE void nrf_tampc_warmboot_status_clear(NRF_TAMPC_Type * p_reg,
1701 nrf_tampc_warmboot_mode_t mode)
1702 {
1703 switch (mode)
1704 {
1705 case NRF_TAMPC_WARMBOOT_MODE_UNRET_IDLE:
1706 p_reg->PROTECT.WARMBOOT.UNRETIDLE.STATUS =
1707 TAMPC_PROTECT_WARMBOOT_UNRETIDLE_STATUS_ERROR_Msk;
1708 break;
1709 case NRF_TAMPC_WARMBOOT_MODE_SYSTEMOFF:
1710 p_reg->PROTECT.WARMBOOT.SYSTEMOFF.STATUS =
1711 TAMPC_PROTECT_WARMBOOT_SYSTEMOFF_STATUS_ERROR_Msk;
1712 break;
1713 default:
1714 NRFX_ASSERT(0);
1715 }
1716 }
1717 #endif // NRF_TAMPC_HAS_WARMBOOT
1718
1719 #if NRF_TAMPC_HAS_EXTENDED_PROTECTORS
nrf_tampc_protector_ctrl_value_set(NRF_TAMPC_Type * p_reg,nrf_tampc_protect_t ctrl,bool enable)1720 NRF_STATIC_INLINE void nrf_tampc_protector_ctrl_value_set(NRF_TAMPC_Type * p_reg,
1721 nrf_tampc_protect_t ctrl,
1722 bool enable)
1723 {
1724 NRF_TAMPC_PROTECT_ACTIVESHIELD_Type * reg =
1725 ((NRF_TAMPC_PROTECT_ACTIVESHIELD_Type *)((uint8_t *)p_reg + (uint32_t)ctrl));
1726
1727 #if NRF_TAMPC_KEY_MASK
1728 reg->CTRL = (TAMPC_PROTECT_ACTIVESHIELD_CTRL_WRITEPROTECTION_Clear
1729 << TAMPC_PROTECT_ACTIVESHIELD_CTRL_WRITEPROTECTION_Pos) | NRF_TAMPC_KEY_MASK;
1730 #endif
1731 reg->CTRL = ((reg->CTRL & ~TAMPC_PROTECT_ACTIVESHIELD_CTRL_VALUE_Msk) |
1732 ((enable ? TAMPC_PROTECT_ACTIVESHIELD_CTRL_VALUE_High :
1733 TAMPC_PROTECT_ACTIVESHIELD_CTRL_VALUE_Low)
1734 << TAMPC_PROTECT_ACTIVESHIELD_CTRL_VALUE_Pos)) |
1735 NRF_TAMPC_KEY_MASK;
1736 }
1737
nrf_tampc_protector_ctrl_value_get(NRF_TAMPC_Type const * p_reg,nrf_tampc_protect_t ctrl)1738 NRF_STATIC_INLINE bool nrf_tampc_protector_ctrl_value_get(NRF_TAMPC_Type const * p_reg,
1739 nrf_tampc_protect_t ctrl)
1740 {
1741 NRF_TAMPC_PROTECT_ACTIVESHIELD_Type const * reg =
1742 ((NRF_TAMPC_PROTECT_ACTIVESHIELD_Type const *)((uint8_t const *)p_reg + (uint32_t)ctrl));
1743
1744 return ((reg->CTRL & TAMPC_PROTECT_ACTIVESHIELD_CTRL_VALUE_Msk)
1745 >> TAMPC_PROTECT_ACTIVESHIELD_CTRL_VALUE_Pos)
1746 == TAMPC_PROTECT_ACTIVESHIELD_CTRL_VALUE_High;
1747 }
1748
nrf_tampc_protector_ctrl_lock_set(NRF_TAMPC_Type * p_reg,nrf_tampc_protect_t ctrl,bool enable)1749 NRF_STATIC_INLINE void nrf_tampc_protector_ctrl_lock_set(NRF_TAMPC_Type * p_reg,
1750 nrf_tampc_protect_t ctrl,
1751 bool enable)
1752 {
1753 NRF_TAMPC_PROTECT_ACTIVESHIELD_Type * reg =
1754 ((NRF_TAMPC_PROTECT_ACTIVESHIELD_Type *)((uint8_t *)p_reg + (uint32_t)ctrl));
1755
1756 #if NRF_TAMPC_KEY_MASK
1757 reg->CTRL = (TAMPC_PROTECT_ACTIVESHIELD_CTRL_WRITEPROTECTION_Clear
1758 << TAMPC_PROTECT_ACTIVESHIELD_CTRL_WRITEPROTECTION_Pos) | NRF_TAMPC_KEY_MASK;
1759 #endif
1760 reg->CTRL = ((reg->CTRL & ~TAMPC_PROTECT_ACTIVESHIELD_CTRL_LOCK_Msk) |
1761 ((enable ? TAMPC_PROTECT_ACTIVESHIELD_CTRL_LOCK_Enabled :
1762 TAMPC_PROTECT_ACTIVESHIELD_CTRL_LOCK_Disabled)
1763 << TAMPC_PROTECT_ACTIVESHIELD_CTRL_LOCK_Pos)) |
1764 NRF_TAMPC_KEY_MASK;
1765 }
1766
nrf_tampc_protector_ctrl_lock_get(NRF_TAMPC_Type const * p_reg,nrf_tampc_protect_t ctrl)1767 NRF_STATIC_INLINE bool nrf_tampc_protector_ctrl_lock_get(NRF_TAMPC_Type const * p_reg,
1768 nrf_tampc_protect_t ctrl)
1769 {
1770 NRF_TAMPC_PROTECT_ACTIVESHIELD_Type const * reg =
1771 ((NRF_TAMPC_PROTECT_ACTIVESHIELD_Type const *)((uint8_t const *)p_reg + (uint32_t)ctrl));
1772
1773 return ((reg->CTRL & TAMPC_PROTECT_ACTIVESHIELD_CTRL_LOCK_Msk)
1774 >> TAMPC_PROTECT_ACTIVESHIELD_CTRL_LOCK_Pos)
1775 == TAMPC_PROTECT_ACTIVESHIELD_CTRL_LOCK_Enabled;
1776 }
1777
nrf_tampc_protector_status_check(NRF_TAMPC_Type const * p_reg,nrf_tampc_protect_t status)1778 NRF_STATIC_INLINE bool nrf_tampc_protector_status_check(NRF_TAMPC_Type const * p_reg,
1779 nrf_tampc_protect_t status)
1780 {
1781 NRF_TAMPC_PROTECT_ACTIVESHIELD_Type const * reg =
1782 ((NRF_TAMPC_PROTECT_ACTIVESHIELD_Type const *)((uint8_t const *)p_reg + (uint32_t)status));
1783
1784 return ((reg->STATUS & TAMPC_PROTECT_ACTIVESHIELD_STATUS_ERROR_Msk)
1785 >> TAMPC_PROTECT_ACTIVESHIELD_STATUS_ERROR_Pos)
1786 == TAMPC_PROTECT_ACTIVESHIELD_STATUS_ERROR_Error;
1787 }
1788
nrf_tampc_protector_status_clear(NRF_TAMPC_Type * p_reg,nrf_tampc_protect_t status)1789 NRF_STATIC_INLINE void nrf_tampc_protector_status_clear(NRF_TAMPC_Type * p_reg,
1790 nrf_tampc_protect_t status)
1791 {
1792 NRF_TAMPC_PROTECT_ACTIVESHIELD_Type * reg =
1793 ((NRF_TAMPC_PROTECT_ACTIVESHIELD_Type *)((uint8_t *)p_reg + (uint32_t)status));
1794
1795 reg->STATUS = TAMPC_PROTECT_ACTIVESHIELD_STATUS_ERROR_Msk;
1796 }
1797 #endif // NRF_TAMPC_HAS_EXTENDED_PROTECTORS
1798
1799 #endif // NRF_DECLARE_ONLY
1800
1801 /** @} */
1802
1803 #ifdef __cplusplus
1804 }
1805 #endif
1806
1807 #endif /* NRF_TAMPC_H_ */
1808
