1 /*
2 * Copyright (c) 2018 - 2024, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_SPU_H__
35 #define NRF_SPU_H__
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /**
44 * @defgroup nrf_spu_hal SPU HAL
45 * @{
46 * @ingroup nrf_spu
47 * @brief Hardware access layer for managing the System Protection Unit (SPU) peripheral.
48 */
49
50 #if defined(SPU_PERIPHACCERR_ADDRESS_ADDRESS_Msk) || defined(__NRFX_DOXYGEN__)
51 /** @brief Presence of peripheral access feature. */
52 #define NRF_SPU_HAS_PERIPHERAL_ACCESS 1
53 #else
54 #define NRF_SPU_HAS_PERIPHERAL_ACCESS 0
55 #endif
56
57 #if defined(SPU_PERIPHACCERR_INFO_OWNERID_Msk) || defined(__NRFX_DOXYGEN__)
58 /**
59 * @brief Symbol indicating whether register containing information about the transaction
60 * that caused peripheral access error is present.
61 */
62 #define NRF_SPU_HAS_PERIPHERAL_ACCESS_ERROR_INFO 1
63 #else
64 #define NRF_SPU_HAS_PERIPHERAL_ACCESS_ERROR_INFO 0
65 #endif
66
67 #if defined(SPU_PERIPH_PERM_OWNERPROG_Msk) || defined(__NRFX_DOXYGEN__)
68 /** @brief Presence of ownership feature. */
69 #define NRF_SPU_HAS_OWNERSHIP 1
70 #else
71 #define NRF_SPU_HAS_OWNERSHIP 0
72 #endif
73
74 #if defined(SPU_FLASHREGION_PERM_EXECUTE_Msk) || defined(__NRFX_DOXYGEN__)
75 /** @brief Presence of memory feature. */
76 #define NRF_SPU_HAS_MEMORY 1
77 #else
78 #define NRF_SPU_HAS_MEMORY 0
79 #endif
80
81 #if defined(SPU_PERIPH_PERM_BLOCK_Msk) || defined(__NRFX_DOXYGEN__)
82 /** @brief Symbol indicating whether block feature is present. */
83 #define NRF_SPU_HAS_BLOCK 1
84 #else
85 #define NRF_SPU_HAS_BLOCK 0
86 #endif
87
88 #if defined(SPU_FEATURE_BELLS_DOMAIN_MaxCount) || defined(SPU_FEATURE_BELLS_PROCESSOR_MaxCount) \
89 || defined(__NRFX_DOXYGEN__)
90 /** @brief Symbol indicating whether SPU has registers related to BELLS. */
91 #define NRF_SPU_HAS_BELLS 1
92 #else
93 #define NRF_SPU_HAS_BELLS 0
94 #endif
95
96 #if defined(SPU_FEATURE_BELLS_DOMAIN_MaxCount) || defined(__NRFX_DOXYGEN__)
97 /** @brief Symbol indicating whether SPU uses DOMAIN register name. */
98 #define NRF_SPU_HAS_DOMAIN 1
99 #else
100 #define NRF_SPU_HAS_DOMAIN 0
101 #endif
102
103 #if defined(SPU_FEATURE_IPCT_CH_MaxCount) || defined(__NRFX_DOXYGEN__)
104 /** @brief Symbol indicating whether SPU has registers related to IPCT. */
105 #define NRF_SPU_HAS_IPCT 1
106 #else
107 #define NRF_SPU_HAS_IPCT 0
108 #endif
109
110 #if defined(SPU_FEATURE_TDD_MaxCount) || defined(__NRFX_DOXYGEN__)
111 /** @brief Symbol indicating whether SPU has registers related to TDD. */
112 #define NRF_SPU_HAS_TDD 1
113 #else
114 #define NRF_SPU_HAS_TDD 0
115 #endif
116
117 #if defined(SPU_FEATURE_MRAMC_MaxCount) || defined(__NRFX_DOXYGEN__)
118 /** @brief Symbol indicating whether SPU has registers related to MRAMC. */
119 #define NRF_SPU_HAS_MRAMC 1
120 #else
121 #define NRF_SPU_HAS_MRAMC 0
122 #endif
123
124 #if NRF_SPU_HAS_PERIPHERAL_ACCESS
125
126 /** @brief Number of peripherals. */
127 #define NRF_SPU_PERIPH_COUNT SPU_PERIPH_MaxCount
128
129 #if NRF_SPU_HAS_IPCT
130 /** @brief Number of IPCT channels. */
131 #define NRF_SPU_FEATURE_IPCT_CHANNEL_COUNT SPU_FEATURE_IPCT_CH_MaxCount
132
133 /** @brief Number of IPCT interrupts. */
134 #define NRF_SPU_FEATURE_IPCT_INTERRUPT_COUNT SPU_FEATURE_IPCT_INTERRUPT_MaxCount
135 #endif
136
137 /** @brief Number of DPPI channels. */
138 #define NRF_SPU_FEATURE_DPPI_CHANNEL_COUNT SPU_FEATURE_DPPIC_CH_MaxCount
139
140 /** @brief Number of DPPI channel groups. */
141 #define NRF_SPU_FEATURE_DPPI_CHANNEL_GROUP_COUNT SPU_FEATURE_DPPIC_CHG_MaxCount
142
143 /** @brief Number of GPIOTEs. */
144 #define NRF_SPU_FEATURE_GPIOTE_COUNT SPU_FEATURE_GPIOTE_MaxCount
145
146 /** @brief Number of GPIOTE channels. */
147 #define NRF_SPU_FEATURE_GPIOTE_CHANNEL_COUNT SPU_FEATURE_GPIOTE_CH_MaxCount
148
149 /** @brief Number of GPIOTE interrupts. */
150 #define NRF_SPU_FEATURE_GPIOTE_INTERRUPT_COUNT SPU_FEATURE_GPIOTE_INTERRUPT_MaxCount
151
152 /** @brief Number of GPIOs. */
153 #define NRF_SPU_FEATURE_GPIO_COUNT SPU_FEATURE_GPIO_MaxCount
154
155 /** @brief Number of GPIO pins. */
156 #define NRF_SPU_FEATURE_GPIO_PIN_COUNT SPU_FEATURE_GPIO_PIN_MaxCount
157
158 /** @brief Number of GRTC compare channels. */
159 #define NRF_SPU_FEATURE_GRTC_CC_COUNT SPU_FEATURE_GRTC_CC_MaxCount
160
161 /** @brief Number of GRTC interrupts.. */
162 #define NRF_SPU_FEATURE_GRTC_INTERRUPT_COUNT SPU_FEATURE_GRTC_INTERRUPT_MaxCount
163
164 /** @brief Number of BELL domains. */
165 #if NRF_SPU_HAS_DOMAIN
166 #define NRF_SPU_FEATURE_BELL_DOMAIN_COUNT SPU_FEATURE_BELLS_DOMAIN_MaxCount
167 #else
168 #define NRF_SPU_FEATURE_BELLS_PROCESSOR_COUNT SPU_FEATURE_BELLS_PROCESSOR_MaxCount
169 #endif
170
171 /** @brief Number of BELL Domain/Processor features. */
172 #if NRF_SPU_HAS_DOMAIN
173 #define NRF_SPU_FEATURE_BELL_BELL_COUNT SPU_FEATURE_BELLS_DOMAIN_BELL_MaxCount
174 #else
175 #define NRF_SPU_FEATURE_BELLS_TASKS_COUNT SPU_FEATURE_BELLS_PROCESSOR_TASKS_MaxCount
176 #define NRF_SPU_FEATURE_BELLS_EVENTS_COUNT SPU_FEATURE_BELLS_PROCESSOR_EVENTS_MaxCount
177 #define NRF_SPU_FEATURE_BELLS_INTERRUPT_COUNT SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_MaxCount
178 #endif
179
180 #if NRF_SPU_HAS_TDD
181 /** @brief Number of TDDs. */
182 #define NRF_SPU_FEATURE_TDD_COUNT SPU_FEATURE_TDD_MaxCount
183 #endif
184
185 #if NRF_SPU_HAS_MRAMC
186 /** @brief Number of MRAMCs. */
187 #define NRF_SPU_FEATURE_MRAMC_COUNT SPU_FEATURE_MRAMC_MaxCount
188 #endif
189
190 #endif // NRF_SPU_HAS_PERIPHERAL_ACCESS
191
192 /** @brief SPU events. */
193 typedef enum
194 {
195 #if NRF_SPU_HAS_MEMORY
196 NRF_SPU_EVENT_RAMACCERR = offsetof(NRF_SPU_Type, EVENTS_RAMACCERR), ///< A security violation has been detected for the RAM memory space.
197 NRF_SPU_EVENT_FLASHACCERR = offsetof(NRF_SPU_Type, EVENTS_FLASHACCERR), ///< A security violation has been detected for the Flash memory space.
198 #endif
199 NRF_SPU_EVENT_PERIPHACCERR = offsetof(NRF_SPU_Type, EVENTS_PERIPHACCERR), ///< A security violation has been detected on one or several peripherals.
200 } nrf_spu_event_t;
201
202 /** @brief SPU interrupts. */
203 typedef enum
204 {
205 #if NRF_SPU_HAS_MEMORY
206 NRF_SPU_INT_RAMACCERR_MASK = SPU_INTENSET_RAMACCERR_Msk, ///< Interrupt on RAMACCERR event.
207 NRF_SPU_INT_FLASHACCERR_MASK = SPU_INTENSET_FLASHACCERR_Msk, ///< Interrupt on FLASHACCERR event.
208 #endif
209 NRF_SPU_INT_PERIPHACCERR_MASK = SPU_INTENSET_PERIPHACCERR_Msk ///< Interrupt on PERIPHACCERR event.
210 } nrf_spu_int_mask_t;
211
212 #if NRF_SPU_HAS_MEMORY
213 /** @brief SPU Non-Secure Callable (NSC) region size. */
214 typedef enum
215 {
216 NRF_SPU_NSC_SIZE_DISABLED = 0, ///< Not defined as a non-secure callable region.
217 NRF_SPU_NSC_SIZE_32B = 1, ///< Non-Secure Callable region with a 32-byte size
218 NRF_SPU_NSC_SIZE_64B = 2, ///< Non-Secure Callable region with a 64-byte size
219 NRF_SPU_NSC_SIZE_128B = 3, ///< Non-Secure Callable region with a 128-byte size
220 NRF_SPU_NSC_SIZE_256B = 4, ///< Non-Secure Callable region with a 256-byte size
221 NRF_SPU_NSC_SIZE_512B = 5, ///< Non-Secure Callable region with a 512-byte size
222 NRF_SPU_NSC_SIZE_1024B = 6, ///< Non-Secure Callable region with a 1024-byte size
223 NRF_SPU_NSC_SIZE_2048B = 7, ///< Non-Secure Callable region with a 2048-byte size
224 NRF_SPU_NSC_SIZE_4096B = 8 ///< Non-Secure Callable region with a 4096-byte size
225 } nrf_spu_nsc_size_t;
226
227 /** @brief SPU memory region permissions. */
228 typedef enum
229 {
230 NRF_SPU_MEM_PERM_EXECUTE = SPU_FLASHREGION_PERM_EXECUTE_Msk, ///< Allow code execution from particular memory region.
231 NRF_SPU_MEM_PERM_WRITE = SPU_FLASHREGION_PERM_WRITE_Msk, ///< Allow write operation on particular memory region.
232 NRF_SPU_MEM_PERM_READ = SPU_FLASHREGION_PERM_READ_Msk ///< Allow read operation from particular memory region.
233 } nrf_spu_mem_perm_t;
234 #endif
235
236 #if NRF_SPU_HAS_PERIPHERAL_ACCESS
237 /** @brief SPU read capabilities for TrustZone Cortex-M secure attribute. */
238 typedef enum
239 {
240 NRF_SPU_SECUREMAPPING_NONSECURE = SPU_PERIPH_PERM_SECUREMAPPING_NonSecure, /**< Peripheral is always accessible as non-secure. */
241 NRF_SPU_SECUREMAPPING_SECURE = SPU_PERIPH_PERM_SECUREMAPPING_Secure, /**< Peripheral is always accessible as secure. */
242 NRF_SPU_SECUREMAPPING_USERSELECTABLE = SPU_PERIPH_PERM_SECUREMAPPING_UserSelectable, /**< Non-secure or secure attribute for this peripheral is defined by the PERIPH[n].PERM register. */
243 NRF_SPU_SECUREMAPPING_SPLIT = SPU_PERIPH_PERM_SECUREMAPPING_Split, /**< Peripheral implements the split security mechanism. */
244 } nrf_spu_securemapping_t;
245
246 /** @brief SPU DMA capabilities. */
247 typedef enum
248 {
249 NRF_SPU_DMA_NODMA = SPU_PERIPH_PERM_DMA_NoDMA, /**< Peripheral has no DMA capability. */
250 NRF_SPU_DMA_NOSEPARATEATTRIBUTE = SPU_PERIPH_PERM_DMA_NoSeparateAttribute, /**< DMA transfers always have the same security attribute as assigned to the peripheral. */
251 NRF_SPU_DMA_SEPARATEATTRIBUTE = SPU_PERIPH_PERM_DMA_SeparateAttribute, /**< DMA transfers can have a different security attribute than the one assigned to the peripheral. */
252 } nrf_spu_dma_t;
253
254 /** @brief SPU features. */
255 typedef enum
256 {
257 #if NRF_SPU_HAS_IPCT
258 NRF_SPU_FEATURE_IPCT_CHANNEL, /**< IPCT channel. */
259 NRF_SPU_FEATURE_IPCT_INTERRUPT, /**< IPCT interrupt. */
260 #endif
261 NRF_SPU_FEATURE_DPPI_CHANNEL, /**< DPPI channel. */
262 NRF_SPU_FEATURE_DPPI_CHANNEL_GROUP, /**< DPPI channel group. */
263 NRF_SPU_FEATURE_GPIOTE_CHANNEL, /**< GPIOTE channel. */
264 NRF_SPU_FEATURE_GPIOTE_INTERRUPT, /**< GPIOTE interrupt. */
265 NRF_SPU_FEATURE_GPIO_PIN, /**< GPIO pin. */
266 NRF_SPU_FEATURE_GRTC_CC, /**< GRTC compare channel. */
267 NRF_SPU_FEATURE_GRTC_SYSCOUNTER, /**< GRTC SYSCOUNTER. */
268 NRF_SPU_FEATURE_GRTC_INTERRUPT, /**< GRTC interrupt. */
269 #if NRF_SPU_HAS_BELLS
270 #if NRF_SPU_HAS_DOMAIN
271 NRF_SPU_FEATURE_BELLS_BELL, /**< BELLS bell pair. */
272 #else
273 NRF_SPU_FEATURE_BELLS_TASKS, /**< BELLS tasks pair. */
274 NRF_SPU_FEATURE_BELLS_EVENTS, /**< BELLS events pair. */
275 NRF_SPU_FEATURE_BELLS_INTERRUPT, /**< BELLS interrupt pair. */
276 #endif
277 #endif
278 #if NRF_SPU_HAS_TDD
279 NRF_SPU_FEATURE_TDD, /**< TDD. */
280 #endif
281 #if NRF_SPU_HAS_MRAMC
282 NRF_SPU_FEATURE_MRAMC_WAITSTATES, /**< MRAMC waitstates. */
283 NRF_SPU_FEATURE_MRAMC_AUTODPOWERDOWN, /**< MRAMC automatic power-down. */
284 NRF_SPU_FEATURE_MRAMC_READY /**< MRAMC ready. */
285 #endif
286 } nrf_spu_feature_t;
287
288 #endif
289
290 /**
291 * @brief Function for clearing a specific SPU event.
292 *
293 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
294 * @param[in] event Event to clear.
295 */
296 NRF_STATIC_INLINE void nrf_spu_event_clear(NRF_SPU_Type * p_reg,
297 nrf_spu_event_t event);
298
299 /**
300 * @brief Function for retrieving the state of the SPU event.
301 *
302 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
303 * @param[in] event Event to be checked.
304 *
305 * @retval true The event has been generated.
306 * @retval false The event has not been generated.
307 */
308 NRF_STATIC_INLINE bool nrf_spu_event_check(NRF_SPU_Type const * p_reg,
309 nrf_spu_event_t event);
310
311 /**
312 * @brief Function for enabling specified interrupts.
313 *
314 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
315 * @param[in] mask Mask of interrupts to be enabled.
316 * Use @ref nrf_spu_int_mask_t values for bit masking.
317 */
318 NRF_STATIC_INLINE void nrf_spu_int_enable(NRF_SPU_Type * p_reg,
319 uint32_t mask);
320
321 /**
322 * @brief Function for disabling specified interrupts.
323 *
324 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
325 * @param[in] mask Mask of interrupts to be disabled.
326 * Use @ref nrf_spu_int_mask_t values for bit masking.
327 */
328 NRF_STATIC_INLINE void nrf_spu_int_disable(NRF_SPU_Type * p_reg,
329 uint32_t mask);
330
331 /**
332 * @brief Function for checking if the specified interrupts are enabled.
333 *
334 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
335 * @param[in] mask Mask of interrupts to be checked.
336 * Use @ref nrf_spu_int_mask_t values for bit masking.
337 *
338 * @return Mask of enabled interrupts.
339 */
340 NRF_STATIC_INLINE uint32_t nrf_spu_int_enable_check(NRF_SPU_Type const * p_reg, uint32_t mask);
341
342 #if NRF_SPU_HAS_MEMORY
343 /**
344 * @brief Function for setting up publication configuration of a given SPU event.
345 *
346 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
347 * @param[in] event Event to configure.
348 * @param[in] channel Channel to connect with published event.
349 */
350 NRF_STATIC_INLINE void nrf_spu_publish_set(NRF_SPU_Type * p_reg,
351 nrf_spu_event_t event,
352 uint32_t channel);
353
354 /**
355 * @brief Function for clearing publication configuration of a given SPU event.
356 *
357 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
358 * @param[in] event Event to clear.
359 */
360 NRF_STATIC_INLINE void nrf_spu_publish_clear(NRF_SPU_Type * p_reg,
361 nrf_spu_event_t event);
362
363 /**
364 * @brief Function for retrieving the capabilities of the current device.
365 *
366 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
367 *
368 * @retval true ARM TrustZone support is available.
369 * @retval false ARM TrustZone support is not available.
370 */
371 NRF_STATIC_INLINE bool nrf_spu_tz_is_available(NRF_SPU_Type const * p_reg);
372
373 /**
374 * @brief Function for configuring the DPPI channels to be available in particular domains.
375 *
376 * Channels are configured as bitmask. Set one in bitmask to make channels available only in secure
377 * domain. Set zero to make it available in secure and non-secure domains.
378 *
379 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
380 * @param[in] dppi_id DPPI peripheral id.
381 * @param[in] channels_mask Bitmask with channels configuration.
382 * @param[in] lock_conf Lock configuration until next SoC reset.
383 */
384 NRF_STATIC_INLINE void nrf_spu_dppi_config_set(NRF_SPU_Type * p_reg,
385 uint8_t dppi_id,
386 uint32_t channels_mask,
387 bool lock_conf);
388
389 /**
390 * @brief Function for configuring the GPIO pins to be available in particular domains.
391 *
392 * GPIO pins are configured as bitmask. Set one in bitmask to make particular pin available only
393 * in secure domain. Set zero to make it available in secure and non-secure domains.
394 *
395 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
396 * @param[in] gpio_port Port number.
397 * @param[in] gpio_mask Bitmask with gpio configuration.
398 * @param[in] lock_conf Lock configuration until next SoC reset.
399 */
400 NRF_STATIC_INLINE void nrf_spu_gpio_config_set(NRF_SPU_Type * p_reg,
401 uint8_t gpio_port,
402 uint32_t gpio_mask,
403 bool lock_conf);
404
405 /**
406 * @brief Function for configuring non-secure callable flash region.
407 *
408 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
409 * @param[in] flash_nsc_id Non-secure callable flash region ID.
410 * @param[in] flash_nsc_size Non-secure callable flash region size.
411 * @param[in] region_number Flash region number.
412 * @param[in] lock_conf Lock configuration until next SoC reset.
413 */
414 NRF_STATIC_INLINE void nrf_spu_flashnsc_set(NRF_SPU_Type * p_reg,
415 uint8_t flash_nsc_id,
416 nrf_spu_nsc_size_t flash_nsc_size,
417 uint8_t region_number,
418 bool lock_conf);
419
420 /**
421 * @brief Function for configuring non-secure callable RAM region.
422 *
423 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
424 * @param[in] ram_nsc_id Non-secure callable RAM region ID.
425 * @param[in] ram_nsc_size Non-secure callable RAM region size.
426 * @param[in] region_number RAM region number.
427 * @param[in] lock_conf Lock configuration until next SoC reset.
428 */
429 NRF_STATIC_INLINE void nrf_spu_ramnsc_set(NRF_SPU_Type * p_reg,
430 uint8_t ram_nsc_id,
431 nrf_spu_nsc_size_t ram_nsc_size,
432 uint8_t region_number,
433 bool lock_conf);
434
435 /**
436 * @brief Function for configuring security for a particular flash region.
437 *
438 * Permissions parameter must be set by using the logical OR on the @ref nrf_spu_mem_perm_t values.
439 *
440 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
441 * @param[in] region_id Flash region index.
442 * @param[in] secure_attr Set region attribute to secure.
443 * @param[in] permissions Flash region permissions.
444 * @param[in] lock_conf Lock configuration until next SoC reset.
445 */
446 NRF_STATIC_INLINE void nrf_spu_flashregion_set(NRF_SPU_Type * p_reg,
447 uint8_t region_id,
448 bool secure_attr,
449 uint32_t permissions,
450 bool lock_conf);
451
452 /**
453 * @brief Function for configuring security for the RAM region.
454 *
455 * Permissions parameter must be set by using the logical OR on the @ref nrf_spu_mem_perm_t values.
456 *
457 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
458 * @param[in] region_id RAM region index.
459 * @param[in] secure_attr Set region attribute to secure.
460 * @param[in] permissions RAM region permissions.
461 * @param[in] lock_conf Lock configuration until next SoC reset.
462 */
463 NRF_STATIC_INLINE void nrf_spu_ramregion_set(NRF_SPU_Type * p_reg,
464 uint8_t region_id,
465 bool secure_attr,
466 uint32_t permissions,
467 bool lock_conf);
468
469 /**
470 * @brief Function for configuring access permissions of the peripheral.
471 *
472 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
473 * @param[in] peripheral_id ID number of a particular peripheral.
474 * @param[in] secure_attr Peripheral registers accessible only from secure domain.
475 * @param[in] secure_dma DMA transfers possible only from RAM memory in secure domain.
476 * @param[in] lock_conf Lock configuration until next SoC reset.
477 */
478 NRF_STATIC_INLINE void nrf_spu_peripheral_set(NRF_SPU_Type * p_reg,
479 uint32_t peripheral_id,
480 bool secure_attr,
481 bool secure_dma,
482 bool lock_conf);
483
484 /**
485 * @brief Function for configuring bus access permissions of the specified external domain.
486 *
487 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
488 * @param[in] domain_id ID number of a particular external domain.
489 * @param[in] secure_attr Specifies if the bus accesses from this domain have the secure attribute set.
490 * @param[in] lock_conf Specifies if the configuration should be locked until next SoC reset.
491 */
492 NRF_STATIC_INLINE void nrf_spu_extdomain_set(NRF_SPU_Type * p_reg,
493 uint32_t domain_id,
494 bool secure_attr,
495 bool lock_conf);
496 #endif
497
498 #if NRF_SPU_HAS_PERIPHERAL_ACCESS
499
500 /**
501 * @brief Function for getting the address of the security violation.
502 *
503 * @note The event PERIPHACCERR must be cleared to clear this register.
504 *
505 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
506 *
507 * @return Address of the transaction that caused first error.
508 */
509 NRF_STATIC_INLINE uint32_t nrf_spu_periphaccerr_address_get(NRF_SPU_Type const * p_reg);
510
511 #if NRF_SPU_HAS_OWNERSHIP && NRF_SPU_HAS_PERIPHERAL_ACCESS_ERROR_INFO
512 /**
513 * @brief Function for getting the owner ID of the security violation.
514 *
515 * @note The event PERIPHACCERR must be cleared to clear this register.
516 *
517 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
518 *
519 * @return Owner ID of the transaction that caused first error.
520 */
521 NRF_STATIC_INLINE nrf_owner_t nrf_spu_periphaccerr_ownerid_get(NRF_SPU_Type const * p_reg);
522 #endif
523
524 /**
525 * @brief Function for getting the capabilities for TrustZone Cortex-M secure attribute
526 * of the specified slave.
527 *
528 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
529 * @param[in] index Peripheral slave index.
530 *
531 * @return TrustZone capabilities.
532 */
533 NRF_STATIC_INLINE
534 nrf_spu_securemapping_t nrf_spu_periph_perm_securemapping_get(NRF_SPU_Type const * p_reg,
535 uint8_t index);
536
537 /**
538 * @brief Function for getting the DMA capabilities of the specified slave.
539 *
540 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
541 * @param[in] index Peripheral slave index.
542 *
543 * @return DMA capabilities.
544 */
545 NRF_STATIC_INLINE nrf_spu_dma_t nrf_spu_periph_perm_dma_get(NRF_SPU_Type const * p_reg,
546 uint8_t index);
547
548 /**
549 * @brief Function for getting the security mapping of the specified slave.
550 *
551 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
552 * @param[in] index Peripheral slave index.
553 *
554 * @retval true Peripheral is mapped in secure peripheral address space.
555 * @retval false If TrustZone capabilities are @ref NRF_SPU_SECUREMAPPING_USERSELECTABLE,
556 * then peripheral is mapped in non-secure peripheral address space.
557 * If TrustZone capabilities are @ref NRF_SPU_SECUREMAPPING_SPLIT,
558 * then peripheral is mapped in non-secure and secure peripheral address space.
559 */
560 NRF_STATIC_INLINE bool nrf_spu_periph_perm_secattr_get(NRF_SPU_Type const * p_reg,
561 uint8_t index);
562
563 /**
564 * @brief Function for setting the security mapping of the specified slave.
565 *
566 * @note This bit has effect only if TrustZone capabilities are either
567 * @ref NRF_SPU_SECUREMAPPING_USERSELECTABLE or @ref NRF_SPU_SECUREMAPPING_SPLIT.
568 *
569 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
570 * @param[in] index Peripheral slave index.
571 * @param[in] enable True if security mapping is to be set, false otherwise.
572 */
573 NRF_STATIC_INLINE void nrf_spu_periph_perm_secattr_set(NRF_SPU_Type * p_reg,
574 uint8_t index,
575 bool enable);
576
577 /**
578 * @brief Function for getting the security attribution for the DMA transfer
579 * of the specified slave.
580 *
581 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
582 * @param[in] index Peripheral slave index.
583 *
584 * @return True if DMA transfers initiated by this peripheral have the secure attribute set,
585 * false otherwise.
586 */
587 NRF_STATIC_INLINE bool nrf_spu_periph_perm_dmasec_get(NRF_SPU_Type const * p_reg,
588 uint8_t index);
589
590 /**
591 * @brief Function for setting the security attribution for the DMA transfer
592 * of the specified slave.
593 *
594 * @note This bit has effect only if peripheral security mapping is enabled.
595 *
596 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
597 * @param[in] index Peripheral slave index.
598 * @param[in] enable True if secure attribute for the DMA transfer is to be set, false otherwise.
599 */
600 NRF_STATIC_INLINE void nrf_spu_periph_perm_dmasec_set(NRF_SPU_Type * p_reg,
601 uint8_t index,
602 bool enable);
603
604 #if NRF_SPU_HAS_BLOCK
605 /**
606 * @brief Function for getting the status of the peripheral access lock of the specified slave.
607 *
608 * @note When peripheral access lock is enabled, reading or modifying the registers of the peripheral
609 * is blocked.
610 *
611 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
612 * @param[in] index Peripheral slave index.
613 *
614 * @return True if the peripheral access is locked, false otherwise.
615 */
616 NRF_STATIC_INLINE bool nrf_spu_periph_perm_block_get(NRF_SPU_Type const * p_reg,
617 uint8_t index);
618
619 /**
620 * @brief Function for enabling the peripheral access lock of the specified slave.
621 *
622 * @note When peripheral access lock is enabled, reading or modifying the registers of the peripheral
623 * is blocked.
624 *
625 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
626 * @param[in] index Peripheral slave index.
627 */
628 NRF_STATIC_INLINE void nrf_spu_periph_perm_block_enable(NRF_SPU_Type * p_reg,
629 uint8_t index);
630 #endif
631
632 /**
633 * @brief Function for getting the status of the peripheral management lock of the specified slave.
634 *
635 * @note When peripheral management lock is enabled, modifying the SPU configuration associated
636 * with specified peripheral is not possible.
637 *
638 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
639 * @param[in] index Peripheral slave index.
640 *
641 * @return True if the peripheral management is locked, false otherwise.
642 */
643 NRF_STATIC_INLINE bool nrf_spu_periph_perm_lock_get(NRF_SPU_Type const * p_reg,
644 uint8_t index);
645
646 /**
647 * @brief Function for enabling the peripheral management lock of the specified slave.
648 *
649 * @note When peripheral management lock is enabled, modifying the SPU configuration associated
650 * with specified peripheral is not possible.
651 *
652 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
653 * @param[in] index Peripheral slave index.
654 */
655 NRF_STATIC_INLINE void nrf_spu_periph_perm_lock_enable(NRF_SPU_Type * p_reg,
656 uint8_t index);
657
658 #if NRF_SPU_HAS_OWNERSHIP
659 /**
660 * @brief Function for getting the peripheral owner ID of the specified slave.
661 *
662 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
663 * @param[in] index Peripheral slave index.
664 *
665 * @return Owner ID.
666 */
667 NRF_STATIC_INLINE nrf_owner_t nrf_spu_periph_perm_ownerid_get(NRF_SPU_Type const * p_reg,
668 uint8_t index);
669
670 /**
671 * @brief Function for setting the peripheral owner ID of the specified slave.
672 *
673 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
674 * @param[in] index Peripheral slave index.
675 * @param[in] owner_id Owner ID to be set.
676 */
677 NRF_STATIC_INLINE void nrf_spu_periph_perm_ownerid_set(NRF_SPU_Type * p_reg,
678 uint8_t index,
679 nrf_owner_t owner_id);
680
681 /**
682 * @brief Function for getting the indication if owner ID of the specified slave
683 * is programmable or not.
684 *
685 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
686 * @param[in] index Peripheral slave index.
687 *
688 * @return True if owner ID is programmable, false otherwise.
689 */
690 NRF_STATIC_INLINE bool nrf_spu_periph_perm_ownerprog_get(NRF_SPU_Type const * p_reg,
691 uint8_t index);
692 #endif // #if NRF_SPU_HAS_OWNERSHIP
693
694 /**
695 * @brief Function for getting the indication if peripheral with
696 * the specified slave index is present.
697 *
698 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
699 * @param[in] index Peripheral slave index.
700 *
701 * @return True if peripheral is present, false otherwise.
702 */
703 NRF_STATIC_INLINE bool nrf_spu_periph_perm_present_get(NRF_SPU_Type const * p_reg,
704 uint8_t index);
705
706 /**
707 * @brief Function for getting the security mapping of the specified feature.
708 *
709 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
710 * @param[in] feature Feature to be accessed.
711 * @param[in] index Feature index.
712 * @param[in] subindex Feature subindex. Only used for applicable features, otherwise skipped.
713 *
714 * @retval true Feature is available for secure usage.
715 * @retval false Feature is available for non-secure usage.
716 */
717 NRF_STATIC_INLINE bool nrf_spu_feature_secattr_get(NRF_SPU_Type const * p_reg,
718 nrf_spu_feature_t feature,
719 uint8_t index,
720 uint8_t subindex);
721
722 /**
723 * @brief Function for setting the security mapping of the specified feature.
724 *
725 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
726 * @param[in] feature Feature to be accessed.
727 * @param[in] index Feature index.
728 * @param[in] subindex Feature subindex. Only used for applicable features, otherwise skipped.
729 * @param[in] enable True if security mapping is to be set, false otherwise.
730 */
731 NRF_STATIC_INLINE void nrf_spu_feature_secattr_set(NRF_SPU_Type * p_reg,
732 nrf_spu_feature_t feature,
733 uint8_t index,
734 uint8_t subindex,
735 bool enable);
736
737 /**
738 * @brief Function for getting the status of the management lock of the specified feature.
739 *
740 * @note When feature management lock is enabled, modifying the SPU configuration associated
741 * with specified feature is not possible.
742 *
743 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
744 * @param[in] feature Feature to be accessed.
745 * @param[in] index Feature index.
746 * @param[in] subindex Feature subindex. Only used for applicable features, otherwise skipped.
747 *
748 * @return True if feature management is locked, false otherwise.
749 */
750 NRF_STATIC_INLINE bool nrf_spu_feature_lock_get(NRF_SPU_Type const * p_reg,
751 nrf_spu_feature_t feature,
752 uint8_t index,
753 uint8_t subindex);
754
755 /**
756 * @brief Function for enabling the management lock of the specified feature.
757 *
758 * @note When feature management lock is enabled, modifying the SPU configuration associated
759 * with specified feature is not possible.
760 *
761 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
762 * @param[in] feature Feature to be accessed.
763 * @param[in] index Feature index.
764 * @param[in] subindex Feature subindex. Only used for applicable features, otherwise skipped.
765 */
766 NRF_STATIC_INLINE void nrf_spu_feature_lock_enable(NRF_SPU_Type * p_reg,
767 nrf_spu_feature_t feature,
768 uint8_t index,
769 uint8_t subindex);
770
771 #if NRF_SPU_HAS_BLOCK
772 /**
773 * @brief Function for getting status of the access lock of the specified feature.
774 *
775 * @note When feature access lock is enabled, reading or modifying the registers of the feature
776 * is blocked.
777 *
778 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
779 * @param[in] feature Feature to be accessed.
780 * @param[in] index Feature index.
781 * @param[in] subindex Feature subindex. Only used for applicable features, otherwise skipped.
782 *
783 * @return True if the feature access is locked, false otherwise.
784 */
785 NRF_STATIC_INLINE bool nrf_spu_feature_block_get(NRF_SPU_Type const * p_reg,
786 nrf_spu_feature_t feature,
787 uint8_t index,
788 uint8_t subindex);
789
790 /**
791 * @brief Function for enabling the feature block of the specified feature.
792 *
793 * @note When feature access lock is enabled, reading or modifying the registers of the feature
794 * is blocked.
795 *
796 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
797 * @param[in] feature Feature to be accessed.
798 * @param[in] index Feature index.
799 * @param[in] subindex Feature subindex. Only used for applicable features, otherwise skipped.
800 */
801 NRF_STATIC_INLINE void nrf_spu_feature_block_enable(NRF_SPU_Type * p_reg,
802 nrf_spu_feature_t feature,
803 uint8_t index,
804 uint8_t subindex);
805 #endif
806
807 #if NRF_SPU_HAS_OWNERSHIP
808 /**
809 * @brief Function for getting the feature owner ID of the specified feature.
810 *
811 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
812 * @param[in] feature Feature to be accessed.
813 * @param[in] index Feature index.
814 * @param[in] subindex Feature subindex. Only used for applicable features, otherwise skipped.
815 *
816 * @return Owner ID.
817 */
818 NRF_STATIC_INLINE nrf_owner_t nrf_spu_feature_ownerid_get(NRF_SPU_Type const * p_reg,
819 nrf_spu_feature_t feature,
820 uint8_t index,
821 uint8_t subindex);
822
823 /**
824 * @brief Function for setting the feature owner ID of the specified feature.
825 *
826 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
827 * @param[in] feature Feature to be accessed.
828 * @param[in] index Feature index.
829 * @param[in] subindex Feature subindex. Only used for applicable features, otherwise skipped.
830 * @param[in] owner_id Owner ID to be set.
831 */
832 NRF_STATIC_INLINE void nrf_spu_feature_ownerid_set(NRF_SPU_Type * p_reg,
833 nrf_spu_feature_t feature,
834 uint8_t index,
835 uint8_t subindex,
836 nrf_owner_t owner_id);
837 #endif // NRF_SPU_HAS_OWNERSHIP
838 #endif // NRF_SPU_HAS_PERIPHERAL_ACCESS
839
840 #ifndef NRF_DECLARE_ONLY
841
nrf_spu_event_clear(NRF_SPU_Type * p_reg,nrf_spu_event_t event)842 NRF_STATIC_INLINE void nrf_spu_event_clear(NRF_SPU_Type * p_reg,
843 nrf_spu_event_t event)
844 {
845 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
846 nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
847 }
848
nrf_spu_event_check(NRF_SPU_Type const * p_reg,nrf_spu_event_t event)849 NRF_STATIC_INLINE bool nrf_spu_event_check(NRF_SPU_Type const * p_reg,
850 nrf_spu_event_t event)
851 {
852 return nrf_event_check(p_reg, event);
853 }
854
nrf_spu_int_enable(NRF_SPU_Type * p_reg,uint32_t mask)855 NRF_STATIC_INLINE void nrf_spu_int_enable(NRF_SPU_Type * p_reg,
856 uint32_t mask)
857 {
858 p_reg->INTENSET = mask;
859 }
860
nrf_spu_int_disable(NRF_SPU_Type * p_reg,uint32_t mask)861 NRF_STATIC_INLINE void nrf_spu_int_disable(NRF_SPU_Type * p_reg,
862 uint32_t mask)
863 {
864 p_reg->INTENCLR = mask;
865 }
866
nrf_spu_int_enable_check(NRF_SPU_Type const * p_reg,uint32_t mask)867 NRF_STATIC_INLINE uint32_t nrf_spu_int_enable_check(NRF_SPU_Type const * p_reg, uint32_t mask)
868 {
869 return p_reg->INTENSET & mask;
870 }
871
872 #if NRF_SPU_HAS_MEMORY
nrf_spu_publish_set(NRF_SPU_Type * p_reg,nrf_spu_event_t event,uint32_t channel)873 NRF_STATIC_INLINE void nrf_spu_publish_set(NRF_SPU_Type * p_reg,
874 nrf_spu_event_t event,
875 uint32_t channel)
876 {
877 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
878 (channel | (NRF_SUBSCRIBE_PUBLISH_ENABLE));
879 }
880
nrf_spu_publish_clear(NRF_SPU_Type * p_reg,nrf_spu_event_t event)881 NRF_STATIC_INLINE void nrf_spu_publish_clear(NRF_SPU_Type * p_reg,
882 nrf_spu_event_t event)
883 {
884 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
885 }
886
nrf_spu_tz_is_available(NRF_SPU_Type const * p_reg)887 NRF_STATIC_INLINE bool nrf_spu_tz_is_available(NRF_SPU_Type const * p_reg)
888 {
889 return (p_reg->CAP & SPU_CAP_TZM_Msk ? true : false);
890 }
891
nrf_spu_dppi_config_set(NRF_SPU_Type * p_reg,uint8_t dppi_id,uint32_t channels_mask,bool lock_conf)892 NRF_STATIC_INLINE void nrf_spu_dppi_config_set(NRF_SPU_Type * p_reg,
893 uint8_t dppi_id,
894 uint32_t channels_mask,
895 bool lock_conf)
896 {
897 NRFX_ASSERT(!(p_reg->DPPI[dppi_id].LOCK & SPU_DPPI_LOCK_LOCK_Msk));
898
899 p_reg->DPPI[dppi_id].PERM = channels_mask;
900
901 if (lock_conf)
902 {
903 p_reg->DPPI[dppi_id].LOCK = (SPU_DPPI_LOCK_LOCK_Msk);
904 }
905 }
906
nrf_spu_gpio_config_set(NRF_SPU_Type * p_reg,uint8_t gpio_port,uint32_t gpio_mask,bool lock_conf)907 NRF_STATIC_INLINE void nrf_spu_gpio_config_set(NRF_SPU_Type * p_reg,
908 uint8_t gpio_port,
909 uint32_t gpio_mask,
910 bool lock_conf)
911 {
912 NRFX_ASSERT(!(p_reg->GPIOPORT[gpio_port].LOCK & SPU_GPIOPORT_LOCK_LOCK_Msk));
913
914 p_reg->GPIOPORT[gpio_port].PERM = gpio_mask;
915
916 if (lock_conf)
917 {
918 p_reg->GPIOPORT[gpio_port].LOCK = (SPU_GPIOPORT_LOCK_LOCK_Msk);
919 }
920 }
921
nrf_spu_flashnsc_set(NRF_SPU_Type * p_reg,uint8_t flash_nsc_id,nrf_spu_nsc_size_t flash_nsc_size,uint8_t region_number,bool lock_conf)922 NRF_STATIC_INLINE void nrf_spu_flashnsc_set(NRF_SPU_Type * p_reg,
923 uint8_t flash_nsc_id,
924 nrf_spu_nsc_size_t flash_nsc_size,
925 uint8_t region_number,
926 bool lock_conf)
927 {
928 NRFX_ASSERT(!(p_reg->FLASHNSC[flash_nsc_id].REGION & SPU_FLASHNSC_REGION_LOCK_Msk));
929 NRFX_ASSERT(!(p_reg->FLASHNSC[flash_nsc_id].SIZE & SPU_FLASHNSC_SIZE_LOCK_Msk));
930
931 p_reg->FLASHNSC[flash_nsc_id].REGION = (uint32_t)region_number |
932 (lock_conf ? SPU_FLASHNSC_REGION_LOCK_Msk : 0);
933 p_reg->FLASHNSC[flash_nsc_id].SIZE = (uint32_t)flash_nsc_size |
934 (lock_conf ? SPU_FLASHNSC_SIZE_LOCK_Msk : 0);
935 }
936
nrf_spu_ramnsc_set(NRF_SPU_Type * p_reg,uint8_t ram_nsc_id,nrf_spu_nsc_size_t ram_nsc_size,uint8_t region_number,bool lock_conf)937 NRF_STATIC_INLINE void nrf_spu_ramnsc_set(NRF_SPU_Type * p_reg,
938 uint8_t ram_nsc_id,
939 nrf_spu_nsc_size_t ram_nsc_size,
940 uint8_t region_number,
941 bool lock_conf)
942 {
943 NRFX_ASSERT(!(p_reg->RAMNSC[ram_nsc_id].REGION & SPU_RAMNSC_REGION_LOCK_Msk));
944 NRFX_ASSERT(!(p_reg->RAMNSC[ram_nsc_id].SIZE & SPU_RAMNSC_SIZE_LOCK_Msk));
945
946 p_reg->RAMNSC[ram_nsc_id].REGION = (uint32_t)region_number |
947 (lock_conf ? SPU_RAMNSC_REGION_LOCK_Msk : 0);
948 p_reg->RAMNSC[ram_nsc_id].SIZE = (uint32_t)ram_nsc_size |
949 (lock_conf ? SPU_RAMNSC_SIZE_LOCK_Msk : 0);
950 }
951
nrf_spu_flashregion_set(NRF_SPU_Type * p_reg,uint8_t region_id,bool secure_attr,uint32_t permissions,bool lock_conf)952 NRF_STATIC_INLINE void nrf_spu_flashregion_set(NRF_SPU_Type * p_reg,
953 uint8_t region_id,
954 bool secure_attr,
955 uint32_t permissions,
956 bool lock_conf)
957 {
958 NRFX_ASSERT(!(p_reg->FLASHREGION[region_id].PERM & SPU_FLASHREGION_PERM_LOCK_Msk));
959
960 p_reg->FLASHREGION[region_id].PERM = permissions |
961 (secure_attr ? SPU_FLASHREGION_PERM_SECATTR_Msk : 0) |
962 (lock_conf ? SPU_FLASHREGION_PERM_LOCK_Msk : 0);
963 }
964
nrf_spu_ramregion_set(NRF_SPU_Type * p_reg,uint8_t region_id,bool secure_attr,uint32_t permissions,bool lock_conf)965 NRF_STATIC_INLINE void nrf_spu_ramregion_set(NRF_SPU_Type * p_reg,
966 uint8_t region_id,
967 bool secure_attr,
968 uint32_t permissions,
969 bool lock_conf)
970 {
971 NRFX_ASSERT(!(p_reg->RAMREGION[region_id].PERM & SPU_RAMREGION_PERM_LOCK_Msk));
972
973 p_reg->RAMREGION[region_id].PERM = permissions |
974 (secure_attr ? SPU_RAMREGION_PERM_SECATTR_Msk : 0) |
975 (lock_conf ? SPU_RAMREGION_PERM_LOCK_Msk : 0);
976 }
977
nrf_spu_peripheral_set(NRF_SPU_Type * p_reg,uint32_t peripheral_id,bool secure_attr,bool secure_dma,bool lock_conf)978 NRF_STATIC_INLINE void nrf_spu_peripheral_set(NRF_SPU_Type * p_reg,
979 uint32_t peripheral_id,
980 bool secure_attr,
981 bool secure_dma,
982 bool lock_conf)
983 {
984 NRFX_ASSERT(p_reg->PERIPHID[peripheral_id].PERM & SPU_PERIPHID_PERM_PRESENT_Msk);
985 NRFX_ASSERT(!(p_reg->PERIPHID[peripheral_id].PERM & SPU_PERIPHID_PERM_LOCK_Msk));
986
987 p_reg->PERIPHID[peripheral_id].PERM =
988 (secure_attr ? SPU_PERIPHID_PERM_SECATTR_Msk : 0) |
989 (secure_dma ? SPU_PERIPHID_PERM_DMASEC_Msk : 0) |
990 (lock_conf ? SPU_PERIPHID_PERM_LOCK_Msk : 0);
991 }
992
nrf_spu_extdomain_set(NRF_SPU_Type * p_reg,uint32_t domain_id,bool secure_attr,bool lock_conf)993 NRF_STATIC_INLINE void nrf_spu_extdomain_set(NRF_SPU_Type * p_reg,
994 uint32_t domain_id,
995 bool secure_attr,
996 bool lock_conf)
997 {
998 NRFX_ASSERT(!(p_reg->EXTDOMAIN[domain_id].PERM & SPU_EXTDOMAIN_PERM_LOCK_Msk));
999
1000 p_reg->EXTDOMAIN[domain_id].PERM =
1001 (secure_attr ? SPU_EXTDOMAIN_PERM_SECATTR_Msk : 0) |
1002 (lock_conf ? SPU_EXTDOMAIN_PERM_LOCK_Msk : 0);
1003 }
1004 #endif
1005
1006 #if NRF_SPU_HAS_PERIPHERAL_ACCESS
nrf_spu_periphaccerr_address_get(NRF_SPU_Type const * p_reg)1007 NRF_STATIC_INLINE uint32_t nrf_spu_periphaccerr_address_get(NRF_SPU_Type const * p_reg)
1008 {
1009 return p_reg->PERIPHACCERR.ADDRESS;
1010 }
1011
1012 #if NRF_SPU_HAS_OWNERSHIP && NRF_SPU_HAS_PERIPHERAL_ACCESS_ERROR_INFO
nrf_spu_periphaccerr_ownerid_get(NRF_SPU_Type const * p_reg)1013 NRF_STATIC_INLINE nrf_owner_t nrf_spu_periphaccerr_ownerid_get(NRF_SPU_Type const * p_reg)
1014 {
1015 return (nrf_owner_t)p_reg->PERIPHACCERR.INFO;
1016 }
1017 #endif
1018
nrf_spu_periph_perm_present_get(NRF_SPU_Type const * p_reg,uint8_t index)1019 NRF_STATIC_INLINE bool nrf_spu_periph_perm_present_get(NRF_SPU_Type const * p_reg,
1020 uint8_t index)
1021 {
1022 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT);
1023 return (p_reg->PERIPH[index].PERM & SPU_PERIPH_PERM_PRESENT_Msk) >>
1024 SPU_PERIPH_PERM_PRESENT_Pos;
1025 }
1026
1027 #if NRF_SPU_HAS_OWNERSHIP
nrf_spu_periph_perm_ownerprog_get(NRF_SPU_Type const * p_reg,uint8_t index)1028 NRF_STATIC_INLINE bool nrf_spu_periph_perm_ownerprog_get(NRF_SPU_Type const * p_reg,
1029 uint8_t index)
1030 {
1031 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT);
1032 return (p_reg->PERIPH[index].PERM & SPU_PERIPH_PERM_OWNERPROG_Msk) >>
1033 SPU_PERIPH_PERM_OWNERPROG_Pos;
1034 }
1035 #endif
1036
nrf_spu_periph_perm_lock_get(NRF_SPU_Type const * p_reg,uint8_t index)1037 NRF_STATIC_INLINE bool nrf_spu_periph_perm_lock_get(NRF_SPU_Type const * p_reg,
1038 uint8_t index)
1039 {
1040 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT);
1041 return (p_reg->PERIPH[index].PERM & SPU_PERIPH_PERM_LOCK_Msk) >>
1042 SPU_PERIPH_PERM_LOCK_Pos;
1043 }
1044
1045 #if NRF_SPU_HAS_BLOCK
nrf_spu_periph_perm_block_get(NRF_SPU_Type const * p_reg,uint8_t index)1046 NRF_STATIC_INLINE bool nrf_spu_periph_perm_block_get(NRF_SPU_Type const * p_reg,
1047 uint8_t index)
1048 {
1049 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT);
1050 return (p_reg->PERIPH[index].PERM & SPU_PERIPH_PERM_BLOCK_Msk) >>
1051 SPU_PERIPH_PERM_BLOCK_Pos;
1052 }
1053 #endif
1054
nrf_spu_periph_perm_dmasec_get(NRF_SPU_Type const * p_reg,uint8_t index)1055 NRF_STATIC_INLINE bool nrf_spu_periph_perm_dmasec_get(NRF_SPU_Type const * p_reg,
1056 uint8_t index)
1057 {
1058 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT);
1059 return (p_reg->PERIPH[index].PERM & SPU_PERIPH_PERM_DMASEC_Msk) >>
1060 SPU_PERIPH_PERM_DMASEC_Pos;
1061 }
1062
nrf_spu_periph_perm_secattr_get(NRF_SPU_Type const * p_reg,uint8_t index)1063 NRF_STATIC_INLINE bool nrf_spu_periph_perm_secattr_get(NRF_SPU_Type const * p_reg,
1064 uint8_t index)
1065 {
1066 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT);
1067 return (p_reg->PERIPH[index].PERM & SPU_PERIPH_PERM_SECATTR_Msk) >>
1068 SPU_PERIPH_PERM_SECATTR_Pos;
1069 }
1070
nrf_spu_periph_perm_lock_enable(NRF_SPU_Type * p_reg,uint8_t index)1071 NRF_STATIC_INLINE void nrf_spu_periph_perm_lock_enable(NRF_SPU_Type * p_reg,
1072 uint8_t index)
1073 {
1074 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT);
1075 p_reg->PERIPH[index].PERM = ((p_reg->PERIPH[index].PERM & ~SPU_PERIPH_PERM_LOCK_Msk)
1076 | (SPU_PERIPH_PERM_LOCK_Locked <<
1077 SPU_PERIPH_PERM_LOCK_Pos));
1078 }
1079
1080 #if NRF_SPU_HAS_BLOCK
nrf_spu_periph_perm_block_enable(NRF_SPU_Type * p_reg,uint8_t index)1081 NRF_STATIC_INLINE void nrf_spu_periph_perm_block_enable(NRF_SPU_Type * p_reg,
1082 uint8_t index)
1083 {
1084 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT);
1085 p_reg->PERIPH[index].PERM = ((p_reg->PERIPH[index].PERM & ~SPU_PERIPH_PERM_BLOCK_Msk)
1086 | (SPU_PERIPH_PERM_BLOCK_Blocked <<
1087 SPU_PERIPH_PERM_BLOCK_Pos));
1088 }
1089 #endif
1090
nrf_spu_periph_perm_dmasec_set(NRF_SPU_Type * p_reg,uint8_t index,bool enable)1091 NRF_STATIC_INLINE void nrf_spu_periph_perm_dmasec_set(NRF_SPU_Type * p_reg,
1092 uint8_t index,
1093 bool enable)
1094 {
1095 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT);
1096 p_reg->PERIPH[index].PERM = ((p_reg->PERIPH[index].PERM & ~SPU_PERIPH_PERM_DMASEC_Msk)
1097 | ((enable ? SPU_PERIPH_PERM_DMASEC_Secure :
1098 SPU_PERIPH_PERM_DMASEC_NonSecure) <<
1099 SPU_PERIPH_PERM_DMASEC_Pos));
1100 }
1101
nrf_spu_periph_perm_secattr_set(NRF_SPU_Type * p_reg,uint8_t index,bool enable)1102 NRF_STATIC_INLINE void nrf_spu_periph_perm_secattr_set(NRF_SPU_Type * p_reg,
1103 uint8_t index,
1104 bool enable)
1105 {
1106 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT);
1107 p_reg->PERIPH[index].PERM = ((p_reg->PERIPH[index].PERM & ~SPU_PERIPH_PERM_SECATTR_Msk)
1108 | ((enable ? SPU_PERIPH_PERM_SECATTR_Secure :
1109 SPU_PERIPH_PERM_SECATTR_NonSecure) <<
1110 SPU_PERIPH_PERM_SECATTR_Pos));
1111 }
1112
1113 NRF_STATIC_INLINE
nrf_spu_periph_perm_securemapping_get(NRF_SPU_Type const * p_reg,uint8_t index)1114 nrf_spu_securemapping_t nrf_spu_periph_perm_securemapping_get(NRF_SPU_Type const * p_reg,
1115 uint8_t index)
1116 {
1117 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT);
1118
1119 return (nrf_spu_securemapping_t)((p_reg->PERIPH[index].PERM
1120 & SPU_PERIPH_PERM_SECUREMAPPING_Msk) >>
1121 SPU_PERIPH_PERM_SECUREMAPPING_Pos);
1122 }
1123
nrf_spu_periph_perm_dma_get(NRF_SPU_Type const * p_reg,uint8_t index)1124 NRF_STATIC_INLINE nrf_spu_dma_t nrf_spu_periph_perm_dma_get(NRF_SPU_Type const * p_reg,
1125 uint8_t index)
1126 {
1127 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT);
1128
1129 return (nrf_spu_dma_t)((p_reg->PERIPH[index].PERM & SPU_PERIPH_PERM_DMA_Msk) >>
1130 SPU_PERIPH_PERM_DMA_Pos);
1131 }
1132
1133 #if NRF_SPU_HAS_OWNERSHIP
nrf_spu_periph_perm_ownerid_get(NRF_SPU_Type const * p_reg,uint8_t index)1134 NRF_STATIC_INLINE nrf_owner_t nrf_spu_periph_perm_ownerid_get(NRF_SPU_Type const * p_reg,
1135 uint8_t index)
1136 {
1137 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT);
1138
1139 return (nrf_owner_t)((p_reg->PERIPH[index].PERM & SPU_PERIPH_PERM_OWNERID_Msk) >>
1140 SPU_PERIPH_PERM_OWNERID_Pos);
1141 }
1142
nrf_spu_periph_perm_ownerid_set(NRF_SPU_Type * p_reg,uint8_t index,nrf_owner_t owner_id)1143 NRF_STATIC_INLINE void nrf_spu_periph_perm_ownerid_set(NRF_SPU_Type * p_reg,
1144 uint8_t index,
1145 nrf_owner_t owner_id)
1146 {
1147 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT);
1148
1149 p_reg->PERIPH[index].PERM = ((p_reg->PERIPH[index].PERM & ~SPU_PERIPH_PERM_OWNERID_Msk) |
1150 ((owner_id << SPU_PERIPH_PERM_OWNERID_Pos)
1151 & SPU_PERIPH_PERM_OWNERID_Msk));
1152 }
1153 #endif
1154
nrf_spu_feature_secattr_get(NRF_SPU_Type const * p_reg,nrf_spu_feature_t feature,uint8_t index,uint8_t subindex)1155 NRF_STATIC_INLINE bool nrf_spu_feature_secattr_get(NRF_SPU_Type const * p_reg,
1156 nrf_spu_feature_t feature,
1157 uint8_t index,
1158 uint8_t subindex)
1159 {
1160 switch (feature)
1161 {
1162 #if NRF_SPU_HAS_IPCT
1163 case NRF_SPU_FEATURE_IPCT_CHANNEL:
1164 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_CHANNEL_COUNT);
1165 return (p_reg->FEATURE.IPCT.CH[index]
1166 & SPU_FEATURE_IPCT_CH_SECATTR_Msk)
1167 >> SPU_FEATURE_IPCT_CH_SECATTR_Pos;
1168
1169 case NRF_SPU_FEATURE_IPCT_INTERRUPT:
1170 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_INTERRUPT_COUNT);
1171 return (p_reg->FEATURE.IPCT.INTERRUPT[index]
1172 & SPU_FEATURE_IPCT_INTERRUPT_SECATTR_Msk)
1173 >> SPU_FEATURE_IPCT_INTERRUPT_SECATTR_Pos;
1174 #endif // NRF_SPU_HAS_IPCT
1175
1176 case NRF_SPU_FEATURE_DPPI_CHANNEL:
1177 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_COUNT);
1178 return (p_reg->FEATURE.DPPIC.CH[index]
1179 & SPU_FEATURE_DPPIC_CH_SECATTR_Msk)
1180 >> SPU_FEATURE_DPPIC_CH_SECATTR_Pos;
1181
1182 case NRF_SPU_FEATURE_DPPI_CHANNEL_GROUP:
1183 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_GROUP_COUNT);
1184 return (p_reg->FEATURE.DPPIC.CHG[index]
1185 & SPU_FEATURE_DPPIC_CHG_SECATTR_Msk)
1186 >> SPU_FEATURE_DPPIC_CHG_SECATTR_Pos;
1187
1188 case NRF_SPU_FEATURE_GPIOTE_CHANNEL:
1189 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT);
1190 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_CHANNEL_COUNT);
1191 return (p_reg->FEATURE.GPIOTE[index].CH[subindex]
1192 & SPU_FEATURE_GPIOTE_CH_SECATTR_Msk)
1193 >> SPU_FEATURE_GPIOTE_CH_SECATTR_Pos;
1194
1195 case NRF_SPU_FEATURE_GPIOTE_INTERRUPT:
1196 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT);
1197 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_INTERRUPT_COUNT);
1198 return (p_reg->FEATURE.GPIOTE[index].INTERRUPT[subindex]
1199 & SPU_FEATURE_GPIOTE_INTERRUPT_SECATTR_Msk)
1200 >> SPU_FEATURE_GPIOTE_INTERRUPT_SECATTR_Pos;
1201
1202 case NRF_SPU_FEATURE_GPIO_PIN:
1203 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIO_COUNT);
1204 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIO_PIN_COUNT);
1205 return (p_reg->FEATURE.GPIO[index].PIN[subindex]
1206 & SPU_FEATURE_GPIO_PIN_SECATTR_Msk)
1207 >> SPU_FEATURE_GPIO_PIN_SECATTR_Pos;
1208
1209 case NRF_SPU_FEATURE_GRTC_CC:
1210 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_CC_COUNT);
1211 return (p_reg->FEATURE.GRTC.CC[index]
1212 & SPU_FEATURE_GRTC_CC_SECATTR_Msk)
1213 >> SPU_FEATURE_GRTC_CC_SECATTR_Pos;
1214
1215 case NRF_SPU_FEATURE_GRTC_SYSCOUNTER:
1216 return (p_reg->FEATURE.GRTC.SYSCOUNTER
1217 & SPU_FEATURE_GRTC_SYSCOUNTER_SECATTR_Msk)
1218 >> SPU_FEATURE_GRTC_SYSCOUNTER_SECATTR_Pos;
1219
1220 case NRF_SPU_FEATURE_GRTC_INTERRUPT:
1221 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_INTERRUPT_COUNT);
1222 return (p_reg->FEATURE.GRTC.INTERRUPT[index]
1223 & SPU_FEATURE_GRTC_INTERRUPT_SECATTR_Msk)
1224 >> SPU_FEATURE_GRTC_INTERRUPT_SECATTR_Pos;
1225
1226 #if NRF_SPU_HAS_BELLS
1227 #if NRF_SPU_HAS_DOMAIN
1228 case NRF_SPU_FEATURE_BELLS_BELL:
1229 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELL_BELL_COUNT);
1230 return (p_reg->FEATURE.BELLS.DOMAIN[index].BELL[subindex]
1231 & SPU_FEATURE_BELLS_DOMAIN_BELL_SECATTR_Msk)
1232 >> SPU_FEATURE_BELLS_DOMAIN_BELL_SECATTR_Pos;
1233 #else
1234 case NRF_SPU_FEATURE_BELLS_TASKS:
1235 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_TASKS_COUNT);
1236 return (p_reg->FEATURE.BELLS.PROCESSOR[index].TASKS[subindex]
1237 & SPU_FEATURE_BELLS_PROCESSOR_TASKS_SECATTR_Msk)
1238 >> SPU_FEATURE_BELLS_PROCESSOR_TASKS_SECATTR_Pos;
1239
1240 case NRF_SPU_FEATURE_BELLS_EVENTS:
1241 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_EVENTS_COUNT);
1242 return (p_reg->FEATURE.BELLS.PROCESSOR[index].EVENTS[subindex]
1243 & SPU_FEATURE_BELLS_PROCESSOR_EVENTS_SECATTR_Msk)
1244 >> SPU_FEATURE_BELLS_PROCESSOR_EVENTS_SECATTR_Pos;
1245
1246 case NRF_SPU_FEATURE_BELLS_INTERRUPT:
1247 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_INTERRUPT_COUNT);
1248 return (p_reg->FEATURE.BELLS.PROCESSOR[index].INTERRUPT[subindex]
1249 & SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_SECATTR_Msk)
1250 >> SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_SECATTR_Pos;
1251 #endif // NRF_SPU_HAS_DOMAIN
1252 #endif // NRF_SPU_HAS_BELLS
1253
1254 #if NRF_SPU_HAS_TDD
1255 case NRF_SPU_FEATURE_TDD:
1256 NRFX_ASSERT(index < NRF_SPU_FEATURE_TDD_COUNT);
1257 return (p_reg->FEATURE.TDD[index]
1258 & SPU_FEATURE_TDD_SECATTR_Msk)
1259 >> SPU_FEATURE_TDD_SECATTR_Pos;
1260 #endif // NRF_SPU_HAS_TDD
1261
1262 #if NRF_SPU_HAS_MRAMC
1263 case NRF_SPU_FEATURE_MRAMC_WAITSTATES:
1264 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT);
1265 return (p_reg->FEATURE.MRAMC[index].WAITSTATES
1266 & SPU_FEATURE_MRAMC_WAITSTATES_SECATTR_Msk)
1267 >> SPU_FEATURE_MRAMC_WAITSTATES_SECATTR_Pos;
1268
1269 case NRF_SPU_FEATURE_MRAMC_AUTODPOWERDOWN:
1270 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT);
1271 return (p_reg->FEATURE.MRAMC[index].AUTODPOWERDOWN
1272 & SPU_FEATURE_MRAMC_AUTODPOWERDOWN_SECATTR_Msk)
1273 >> SPU_FEATURE_MRAMC_AUTODPOWERDOWN_SECATTR_Pos;
1274
1275 case NRF_SPU_FEATURE_MRAMC_READY:
1276 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT);
1277 return (p_reg->FEATURE.MRAMC[index].READY
1278 & SPU_FEATURE_MRAMC_READY_SECATTR_Msk)
1279 >> SPU_FEATURE_MRAMC_READY_SECATTR_Pos;
1280 #endif // NRF_SPU_HAS_MRAMC
1281
1282 default:
1283 NRFX_ASSERT(0);
1284 return false;
1285 }
1286 }
1287
nrf_spu_feature_lock_get(NRF_SPU_Type const * p_reg,nrf_spu_feature_t feature,uint8_t index,uint8_t subindex)1288 NRF_STATIC_INLINE bool nrf_spu_feature_lock_get(NRF_SPU_Type const * p_reg,
1289 nrf_spu_feature_t feature,
1290 uint8_t index,
1291 uint8_t subindex)
1292 {
1293 switch (feature)
1294 {
1295 #if NRF_SPU_HAS_IPCT
1296 case NRF_SPU_FEATURE_IPCT_CHANNEL:
1297 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_CHANNEL_COUNT);
1298 return (p_reg->FEATURE.IPCT.CH[index]
1299 & SPU_FEATURE_IPCT_CH_LOCK_Msk)
1300 >> SPU_FEATURE_IPCT_CH_LOCK_Pos;
1301
1302 case NRF_SPU_FEATURE_IPCT_INTERRUPT:
1303 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_INTERRUPT_COUNT);
1304 return (p_reg->FEATURE.IPCT.INTERRUPT[index]
1305 & SPU_FEATURE_IPCT_INTERRUPT_LOCK_Msk)
1306 >> SPU_FEATURE_IPCT_INTERRUPT_LOCK_Pos;
1307 #endif // NRF_SPU_HAS_IPCT
1308
1309 case NRF_SPU_FEATURE_DPPI_CHANNEL:
1310 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_COUNT);
1311 return (p_reg->FEATURE.DPPIC.CH[index]
1312 & SPU_FEATURE_DPPIC_CH_LOCK_Msk)
1313 >> SPU_FEATURE_DPPIC_CH_LOCK_Pos;
1314
1315 case NRF_SPU_FEATURE_DPPI_CHANNEL_GROUP:
1316 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_GROUP_COUNT);
1317 return (p_reg->FEATURE.DPPIC.CHG[index]
1318 & SPU_FEATURE_DPPIC_CHG_LOCK_Msk)
1319 >> SPU_FEATURE_DPPIC_CHG_LOCK_Pos;
1320
1321 case NRF_SPU_FEATURE_GPIOTE_CHANNEL:
1322 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT);
1323 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_CHANNEL_COUNT);
1324 return (p_reg->FEATURE.GPIOTE[index].CH[subindex]
1325 & SPU_FEATURE_GPIOTE_CH_LOCK_Msk)
1326 >> SPU_FEATURE_GPIOTE_CH_LOCK_Pos;
1327
1328 case NRF_SPU_FEATURE_GPIOTE_INTERRUPT:
1329 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT);
1330 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_INTERRUPT_COUNT);
1331 return (p_reg->FEATURE.GPIOTE[index].INTERRUPT[subindex]
1332 & SPU_FEATURE_GPIOTE_INTERRUPT_LOCK_Msk)
1333 >> SPU_FEATURE_GPIOTE_INTERRUPT_LOCK_Pos;
1334
1335 case NRF_SPU_FEATURE_GPIO_PIN:
1336 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIO_COUNT);
1337 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIO_PIN_COUNT);
1338 return (p_reg->FEATURE.GPIO[index].PIN[subindex]
1339 & SPU_FEATURE_GPIO_PIN_LOCK_Msk)
1340 >> SPU_FEATURE_GPIO_PIN_LOCK_Pos;
1341
1342 case NRF_SPU_FEATURE_GRTC_CC:
1343 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_CC_COUNT);
1344 return (p_reg->FEATURE.GRTC.CC[index]
1345 & SPU_FEATURE_GRTC_CC_LOCK_Msk)
1346 >> SPU_FEATURE_GRTC_CC_LOCK_Pos;
1347
1348 case NRF_SPU_FEATURE_GRTC_SYSCOUNTER:
1349 return (p_reg->FEATURE.GRTC.SYSCOUNTER
1350 & SPU_FEATURE_GRTC_SYSCOUNTER_LOCK_Msk)
1351 >> SPU_FEATURE_GRTC_SYSCOUNTER_LOCK_Pos;
1352
1353 case NRF_SPU_FEATURE_GRTC_INTERRUPT:
1354 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_INTERRUPT_COUNT);
1355 return (p_reg->FEATURE.GRTC.INTERRUPT[index]
1356 & SPU_FEATURE_GRTC_INTERRUPT_LOCK_Msk)
1357 >> SPU_FEATURE_GRTC_INTERRUPT_LOCK_Pos;
1358
1359 #if NRF_SPU_HAS_BELLS
1360 #if NRF_SPU_HAS_DOMAIN
1361 case NRF_SPU_FEATURE_BELLS_BELL:
1362 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELL_BELL_COUNT);
1363 return (p_reg->FEATURE.BELLS.DOMAIN[index].BELL[subindex]
1364 & SPU_FEATURE_BELLS_DOMAIN_BELL_LOCK_Msk)
1365 >> SPU_FEATURE_BELLS_DOMAIN_BELL_LOCK_Pos;
1366 #else
1367 case NRF_SPU_FEATURE_BELLS_TASKS:
1368 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_TASKS_COUNT);
1369 return (p_reg->FEATURE.BELLS.PROCESSOR[index].TASKS[subindex]
1370 & SPU_FEATURE_BELLS_PROCESSOR_TASKS_LOCK_Msk)
1371 >> SPU_FEATURE_BELLS_PROCESSOR_TASKS_LOCK_Pos;
1372
1373 case NRF_SPU_FEATURE_BELLS_EVENTS:
1374 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_EVENTS_COUNT);
1375 return (p_reg->FEATURE.BELLS.PROCESSOR[index].EVENTS[subindex]
1376 & SPU_FEATURE_BELLS_PROCESSOR_EVENTS_LOCK_Msk)
1377 >> SPU_FEATURE_BELLS_PROCESSOR_EVENTS_LOCK_Pos;
1378
1379 case NRF_SPU_FEATURE_BELLS_INTERRUPT:
1380 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_INTERRUPT_COUNT);
1381 return (p_reg->FEATURE.BELLS.PROCESSOR[index].INTERRUPT[subindex]
1382 & SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_LOCK_Msk)
1383 >> SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_LOCK_Pos;
1384 #endif // NRF_SPU_HAS_DOMAIN
1385 #endif // NRF_SPU_HAS_BELLS
1386
1387 #if NRF_SPU_HAS_TDD
1388 case NRF_SPU_FEATURE_TDD:
1389 NRFX_ASSERT(index < NRF_SPU_FEATURE_TDD_COUNT);
1390 return (p_reg->FEATURE.TDD[index]
1391 & SPU_FEATURE_TDD_LOCK_Msk)
1392 >> SPU_FEATURE_TDD_LOCK_Pos;
1393 #endif // NRF_SPU_HAS_TDD
1394
1395 #if NRF_SPU_HAS_MRAMC
1396 case NRF_SPU_FEATURE_MRAMC_WAITSTATES:
1397 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT);
1398 return (p_reg->FEATURE.MRAMC[index].WAITSTATES
1399 & SPU_FEATURE_MRAMC_WAITSTATES_LOCK_Msk)
1400 >> SPU_FEATURE_MRAMC_WAITSTATES_LOCK_Pos;
1401
1402 case NRF_SPU_FEATURE_MRAMC_AUTODPOWERDOWN:
1403 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT);
1404 return (p_reg->FEATURE.MRAMC[index].AUTODPOWERDOWN
1405 & SPU_FEATURE_MRAMC_AUTODPOWERDOWN_LOCK_Msk)
1406 >> SPU_FEATURE_MRAMC_AUTODPOWERDOWN_LOCK_Pos;
1407
1408 case NRF_SPU_FEATURE_MRAMC_READY:
1409 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT);
1410 return (p_reg->FEATURE.MRAMC[index].READY
1411 & SPU_FEATURE_MRAMC_READY_LOCK_Msk)
1412 >> SPU_FEATURE_MRAMC_READY_LOCK_Pos;
1413 #endif // NRF_SPU_HAS_MRAMC
1414
1415 default:
1416 NRFX_ASSERT(0);
1417 return false;
1418 }
1419 }
1420
1421 #if NRF_SPU_HAS_BLOCK
nrf_spu_feature_block_get(NRF_SPU_Type const * p_reg,nrf_spu_feature_t feature,uint8_t index,uint8_t subindex)1422 NRF_STATIC_INLINE bool nrf_spu_feature_block_get(NRF_SPU_Type const * p_reg,
1423 nrf_spu_feature_t feature,
1424 uint8_t index,
1425 uint8_t subindex)
1426 {
1427 switch (feature)
1428 {
1429 #if NRF_SPU_HAS_IPCT
1430 case NRF_SPU_FEATURE_IPCT_CHANNEL:
1431 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_CHANNEL_COUNT);
1432 return (p_reg->FEATURE.IPCT.CH[index]
1433 & SPU_FEATURE_IPCT_CH_BLOCK_Msk)
1434 >> SPU_FEATURE_IPCT_CH_BLOCK_Pos;
1435
1436 case NRF_SPU_FEATURE_IPCT_INTERRUPT:
1437 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_INTERRUPT_COUNT);
1438 return (p_reg->FEATURE.IPCT.INTERRUPT[index]
1439 & SPU_FEATURE_IPCT_INTERRUPT_BLOCK_Msk)
1440 >> SPU_FEATURE_IPCT_INTERRUPT_BLOCK_Pos;
1441 #endif // NRF_SPU_HAS_IPCT
1442
1443 case NRF_SPU_FEATURE_DPPI_CHANNEL:
1444 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_COUNT);
1445 return (p_reg->FEATURE.DPPIC.CH[index]
1446 & SPU_FEATURE_DPPIC_CH_BLOCK_Msk)
1447 >> SPU_FEATURE_DPPIC_CH_BLOCK_Pos;
1448
1449 case NRF_SPU_FEATURE_DPPI_CHANNEL_GROUP:
1450 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_GROUP_COUNT);
1451 return (p_reg->FEATURE.DPPIC.CHG[index]
1452 & SPU_FEATURE_DPPIC_CHG_BLOCK_Msk)
1453 >> SPU_FEATURE_DPPIC_CHG_BLOCK_Pos;
1454
1455 case NRF_SPU_FEATURE_GPIOTE_CHANNEL:
1456 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT);
1457 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_CHANNEL_COUNT);
1458 return (p_reg->FEATURE.GPIOTE[index].CH[subindex]
1459 & SPU_FEATURE_GPIOTE_CH_BLOCK_Msk)
1460 >> SPU_FEATURE_GPIOTE_CH_BLOCK_Pos;
1461
1462 case NRF_SPU_FEATURE_GPIOTE_INTERRUPT:
1463 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT);
1464 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_INTERRUPT_COUNT);
1465 return (p_reg->FEATURE.GPIOTE[index].INTERRUPT[subindex]
1466 & SPU_FEATURE_GPIOTE_INTERRUPT_BLOCK_Msk)
1467 >> SPU_FEATURE_GPIOTE_INTERRUPT_BLOCK_Pos;
1468
1469 case NRF_SPU_FEATURE_GPIO_PIN:
1470 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIO_COUNT);
1471 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIO_PIN_COUNT);
1472 return (p_reg->FEATURE.GPIO[index].PIN[subindex]
1473 & SPU_FEATURE_GPIO_PIN_BLOCK_Msk)
1474 >> SPU_FEATURE_GPIO_PIN_BLOCK_Pos;
1475
1476 case NRF_SPU_FEATURE_GRTC_CC:
1477 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_CC_COUNT);
1478 return (p_reg->FEATURE.GRTC.CC[index]
1479 & SPU_FEATURE_GRTC_CC_BLOCK_Msk)
1480 >> SPU_FEATURE_GRTC_CC_BLOCK_Pos;
1481
1482 case NRF_SPU_FEATURE_GRTC_SYSCOUNTER:
1483 return (p_reg->FEATURE.GRTC.SYSCOUNTER
1484 & SPU_FEATURE_GRTC_SYSCOUNTER_BLOCK_Msk)
1485 >> SPU_FEATURE_GRTC_SYSCOUNTER_BLOCK_Pos;
1486
1487 case NRF_SPU_FEATURE_GRTC_INTERRUPT:
1488 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_INTERRUPT_COUNT);
1489 return (p_reg->FEATURE.GRTC.INTERRUPT[index]
1490 & SPU_FEATURE_GRTC_INTERRUPT_BLOCK_Msk)
1491 >> SPU_FEATURE_GRTC_INTERRUPT_BLOCK_Pos;
1492
1493 #if NRF_SPU_HAS_BELLS
1494 #if NRF_SPU_HAS_DOMAIN
1495 case NRF_SPU_FEATURE_BELLS_BELL:
1496 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELL_BELL_COUNT);
1497 return (p_reg->FEATURE.BELLS.DOMAIN[index].BELL[subindex]
1498 & SPU_FEATURE_BELLS_DOMAIN_BELL_BLOCK_Msk)
1499 >> SPU_FEATURE_BELLS_DOMAIN_BELL_BLOCK_Pos;
1500 #else
1501 case NRF_SPU_FEATURE_BELLS_TASKS:
1502 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_TASKS_COUNT);
1503 return (p_reg->FEATURE.BELLS.PROCESSOR[index].TASKS[subindex]
1504 & SPU_FEATURE_BELLS_PROCESSOR_TASKS_BLOCK_Msk)
1505 >> SPU_FEATURE_BELLS_PROCESSOR_TASKS_BLOCK_Pos;
1506
1507 case NRF_SPU_FEATURE_BELLS_EVENTS:
1508 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_EVENTS_COUNT);
1509 return (p_reg->FEATURE.BELLS.PROCESSOR[index].EVENTS[subindex]
1510 & SPU_FEATURE_BELLS_PROCESSOR_EVENTS_BLOCK_Msk)
1511 >> SPU_FEATURE_BELLS_PROCESSOR_EVENTS_BLOCK_Pos;
1512
1513 case NRF_SPU_FEATURE_BELLS_INTERRUPT:
1514 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_INTERRUPT_COUNT);
1515 return (p_reg->FEATURE.BELLS.PROCESSOR[index].INTERRUPT[subindex]
1516 & SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_BLOCK_Msk)
1517 >> SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_BLOCK_Pos;
1518 #endif // NRF_SPU_HAS_DOMAIN
1519 #endif // NRF_SPU_HAS_BELLS
1520
1521 #if NRF_SPU_HAS_TDD
1522 case NRF_SPU_FEATURE_TDD:
1523 NRFX_ASSERT(index < NRF_SPU_FEATURE_TDD_COUNT);
1524 return (p_reg->FEATURE.TDD[index]
1525 & SPU_FEATURE_TDD_BLOCK_Msk)
1526 >> SPU_FEATURE_TDD_BLOCK_Pos;
1527 #endif // NRF_SPU_HAS_TDD
1528
1529 #if NRF_SPU_HAS_MRAMC
1530 case NRF_SPU_FEATURE_MRAMC_WAITSTATES:
1531 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT);
1532 return (p_reg->FEATURE.MRAMC[index].WAITSTATES
1533 & SPU_FEATURE_MRAMC_WAITSTATES_BLOCK_Msk)
1534 >> SPU_FEATURE_MRAMC_WAITSTATES_BLOCK_Pos;
1535
1536 case NRF_SPU_FEATURE_MRAMC_AUTODPOWERDOWN:
1537 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT);
1538 return (p_reg->FEATURE.MRAMC[index].AUTODPOWERDOWN
1539 & SPU_FEATURE_MRAMC_AUTODPOWERDOWN_BLOCK_Msk)
1540 >> SPU_FEATURE_MRAMC_AUTODPOWERDOWN_BLOCK_Pos;
1541
1542 case NRF_SPU_FEATURE_MRAMC_READY:
1543 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT);
1544 return (p_reg->FEATURE.MRAMC[index].READY
1545 & SPU_FEATURE_MRAMC_READY_BLOCK_Msk)
1546 >> SPU_FEATURE_MRAMC_READY_BLOCK_Pos;
1547 #endif // NRF_SPU_HAS_MRAMC
1548
1549 default:
1550 NRFX_ASSERT(0);
1551 return false;
1552 }
1553 }
1554 #endif // NRF_SPU_HAS_BLOCK
1555
1556 #if NRF_SPU_HAS_OWNERSHIP
nrf_spu_feature_ownerid_get(NRF_SPU_Type const * p_reg,nrf_spu_feature_t feature,uint8_t index,uint8_t subindex)1557 NRF_STATIC_INLINE nrf_owner_t nrf_spu_feature_ownerid_get(NRF_SPU_Type const * p_reg,
1558 nrf_spu_feature_t feature,
1559 uint8_t index,
1560 uint8_t subindex)
1561 {
1562 switch (feature)
1563 {
1564 #if NRF_SPU_HAS_IPCT
1565 case NRF_SPU_FEATURE_IPCT_CHANNEL:
1566 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_CHANNEL_COUNT);
1567 return (nrf_owner_t)((p_reg->FEATURE.IPCT.CH[index]
1568 & SPU_FEATURE_IPCT_CH_OWNERID_Msk)
1569 >> SPU_FEATURE_IPCT_CH_OWNERID_Pos);
1570
1571 case NRF_SPU_FEATURE_IPCT_INTERRUPT:
1572 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_INTERRUPT_COUNT);
1573 return (nrf_owner_t)((p_reg->FEATURE.IPCT.INTERRUPT[index]
1574 & SPU_FEATURE_IPCT_INTERRUPT_OWNERID_Msk)
1575 >> SPU_FEATURE_IPCT_INTERRUPT_OWNERID_Pos);
1576 #endif // NRF_SPU_HAS_IPCT
1577
1578 case NRF_SPU_FEATURE_DPPI_CHANNEL:
1579 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_COUNT);
1580 return (nrf_owner_t)((p_reg->FEATURE.DPPIC.CH[index]
1581 & SPU_FEATURE_DPPIC_CH_OWNERID_Msk)
1582 >> SPU_FEATURE_DPPIC_CH_OWNERID_Pos);
1583
1584 case NRF_SPU_FEATURE_DPPI_CHANNEL_GROUP:
1585 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_GROUP_COUNT);
1586 return (nrf_owner_t)((p_reg->FEATURE.DPPIC.CHG[index]
1587 & SPU_FEATURE_DPPIC_CHG_OWNERID_Msk)
1588 >> SPU_FEATURE_DPPIC_CHG_OWNERID_Pos);
1589
1590 case NRF_SPU_FEATURE_GPIOTE_CHANNEL:
1591 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT);
1592 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_CHANNEL_COUNT);
1593 return (nrf_owner_t)((p_reg->FEATURE.GPIOTE[index].CH[subindex]
1594 & SPU_FEATURE_GPIOTE_CH_OWNERID_Msk)
1595 >> SPU_FEATURE_GPIOTE_CH_OWNERID_Pos);
1596
1597 case NRF_SPU_FEATURE_GPIOTE_INTERRUPT:
1598 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT);
1599 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_INTERRUPT_COUNT);
1600 return (nrf_owner_t)((p_reg->FEATURE.GPIOTE[index].INTERRUPT[subindex]
1601 & SPU_FEATURE_GPIOTE_INTERRUPT_OWNERID_Msk)
1602 >> SPU_FEATURE_GPIOTE_INTERRUPT_OWNERID_Pos);
1603
1604 case NRF_SPU_FEATURE_GPIO_PIN:
1605 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIO_COUNT);
1606 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIO_PIN_COUNT);
1607 return (nrf_owner_t)((p_reg->FEATURE.GPIO[index].PIN[subindex]
1608 & SPU_FEATURE_GPIO_PIN_OWNERID_Msk)
1609 >> SPU_FEATURE_GPIO_PIN_OWNERID_Pos);
1610
1611 case NRF_SPU_FEATURE_GRTC_CC:
1612 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_CC_COUNT);
1613 return (nrf_owner_t)((p_reg->FEATURE.GRTC.CC[index]
1614 & SPU_FEATURE_GRTC_CC_OWNERID_Msk)
1615 >> SPU_FEATURE_GRTC_CC_OWNERID_Pos);
1616
1617 case NRF_SPU_FEATURE_GRTC_SYSCOUNTER:
1618 return (nrf_owner_t)((p_reg->FEATURE.GRTC.SYSCOUNTER
1619 & SPU_FEATURE_GRTC_SYSCOUNTER_OWNERID_Msk)
1620 >> SPU_FEATURE_GRTC_SYSCOUNTER_OWNERID_Pos);
1621
1622 case NRF_SPU_FEATURE_GRTC_INTERRUPT:
1623 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_INTERRUPT_COUNT);
1624 return (nrf_owner_t)((p_reg->FEATURE.GRTC.INTERRUPT[index]
1625 & SPU_FEATURE_GRTC_INTERRUPT_OWNERID_Msk)
1626 >> SPU_FEATURE_GRTC_INTERRUPT_OWNERID_Pos);
1627
1628 #if NRF_SPU_HAS_BELLS
1629 #if NRF_SPU_HAS_DOMAIN
1630 case NRF_SPU_FEATURE_BELLS_BELL:
1631 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELL_BELL_COUNT);
1632 return (nrf_owner_t)((p_reg->FEATURE.BELLS.DOMAIN[index].BELL[subindex]
1633 & SPU_FEATURE_BELLS_DOMAIN_BELL_OWNERID_Msk)
1634 >> SPU_FEATURE_BELLS_DOMAIN_BELL_OWNERID_Pos);
1635 #else
1636 case NRF_SPU_FEATURE_BELLS_TASKS:
1637 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_TASKS_COUNT);
1638 return (nrf_owner_t)((p_reg->FEATURE.BELLS.PROCESSOR[index].TASKS[subindex]
1639 & SPU_FEATURE_BELLS_PROCESSOR_TASKS_OWNERID_Msk)
1640 >> SPU_FEATURE_BELLS_PROCESSOR_TASKS_OWNERID_Pos);
1641
1642 case NRF_SPU_FEATURE_BELLS_EVENTS:
1643 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_EVENTS_COUNT);
1644 return (nrf_owner_t)((p_reg->FEATURE.BELLS.PROCESSOR[index].EVENTS[subindex]
1645 & SPU_FEATURE_BELLS_PROCESSOR_EVENTS_OWNERID_Msk)
1646 >> SPU_FEATURE_BELLS_PROCESSOR_EVENTS_OWNERID_Pos);
1647
1648 case NRF_SPU_FEATURE_BELLS_INTERRUPT:
1649 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_INTERRUPT_COUNT);
1650 return (nrf_owner_t)((p_reg->FEATURE.BELLS.PROCESSOR[index].INTERRUPT[subindex]
1651 & SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_OWNERID_Msk)
1652 >> SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_OWNERID_Pos);
1653 #endif // NRF_SPU_HAS_DOMAIN
1654 #endif // NRF_SPU_HAS_BELLS
1655
1656 #if NRF_SPU_HAS_TDD
1657 case NRF_SPU_FEATURE_TDD:
1658 NRFX_ASSERT(index < NRF_SPU_FEATURE_TDD_COUNT);
1659 return (nrf_owner_t)((p_reg->FEATURE.TDD[index]
1660 & SPU_FEATURE_TDD_OWNERID_Msk)
1661 >> SPU_FEATURE_TDD_OWNERID_Pos);
1662 #endif // NRF_SPU_HAS_TDD
1663
1664 #if NRF_SPU_HAS_MRAMC
1665 case NRF_SPU_FEATURE_MRAMC_WAITSTATES:
1666 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT);
1667 return (nrf_owner_t)((p_reg->FEATURE.MRAMC[index].WAITSTATES
1668 & SPU_FEATURE_MRAMC_WAITSTATES_OWNERID_Msk)
1669 >> SPU_FEATURE_MRAMC_WAITSTATES_OWNERID_Pos);
1670
1671 case NRF_SPU_FEATURE_MRAMC_AUTODPOWERDOWN:
1672 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT);
1673 return (nrf_owner_t)((p_reg->FEATURE.MRAMC[index].AUTODPOWERDOWN
1674 & SPU_FEATURE_MRAMC_AUTODPOWERDOWN_OWNERID_Msk)
1675 >> SPU_FEATURE_MRAMC_AUTODPOWERDOWN_OWNERID_Pos);
1676
1677 case NRF_SPU_FEATURE_MRAMC_READY:
1678 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT);
1679 return (nrf_owner_t)((p_reg->FEATURE.MRAMC[index].READY
1680 & SPU_FEATURE_MRAMC_READY_OWNERID_Msk)
1681 >> SPU_FEATURE_MRAMC_READY_OWNERID_Pos);
1682 #endif // NRF_SPU_HAS_MRAMC
1683
1684 default:
1685 NRFX_ASSERT(0);
1686 return (nrf_owner_t)0;
1687 }
1688 }
1689 #endif // NRF_SPU_HAS_OWNERSHIP
1690
nrf_spu_feature_secattr_set(NRF_SPU_Type * p_reg,nrf_spu_feature_t feature,uint8_t index,uint8_t subindex,bool enable)1691 NRF_STATIC_INLINE void nrf_spu_feature_secattr_set(NRF_SPU_Type * p_reg,
1692 nrf_spu_feature_t feature,
1693 uint8_t index,
1694 uint8_t subindex,
1695 bool enable)
1696 {
1697 switch (feature)
1698 {
1699 #if NRF_SPU_HAS_IPCT
1700 case NRF_SPU_FEATURE_IPCT_CHANNEL:
1701 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_CHANNEL_COUNT);
1702 p_reg->FEATURE.IPCT.CH[index] =
1703 ((p_reg->FEATURE.IPCT.CH[index] &
1704 ~SPU_FEATURE_IPCT_CH_SECATTR_Msk) |
1705 ((enable ?
1706 SPU_FEATURE_IPCT_CH_SECATTR_Secure :
1707 SPU_FEATURE_IPCT_CH_SECATTR_NonSecure)
1708 << SPU_FEATURE_IPCT_CH_SECATTR_Pos));
1709 break;
1710
1711 case NRF_SPU_FEATURE_IPCT_INTERRUPT:
1712 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_INTERRUPT_COUNT);
1713 p_reg->FEATURE.IPCT.INTERRUPT[index] =
1714 ((p_reg->FEATURE.IPCT.INTERRUPT[index] &
1715 ~SPU_FEATURE_IPCT_INTERRUPT_SECATTR_Msk) |
1716 ((enable ?
1717 SPU_FEATURE_IPCT_INTERRUPT_SECATTR_Secure :
1718 SPU_FEATURE_IPCT_INTERRUPT_SECATTR_NonSecure)
1719 << SPU_FEATURE_IPCT_INTERRUPT_SECATTR_Pos));
1720 break;
1721 #endif // NRF_SPU_HAS_IPCT
1722
1723 case NRF_SPU_FEATURE_DPPI_CHANNEL:
1724 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_COUNT);
1725 p_reg->FEATURE.DPPIC.CH[index] =
1726 ((p_reg->FEATURE.DPPIC.CH[index] &
1727 ~SPU_FEATURE_DPPIC_CH_SECATTR_Msk) |
1728 ((enable ?
1729 SPU_FEATURE_DPPIC_CH_SECATTR_Secure :
1730 SPU_FEATURE_DPPIC_CH_SECATTR_NonSecure)
1731 << SPU_FEATURE_DPPIC_CH_SECATTR_Pos));
1732 break;
1733
1734 case NRF_SPU_FEATURE_DPPI_CHANNEL_GROUP:
1735 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_GROUP_COUNT);
1736 p_reg->FEATURE.DPPIC.CHG[index] =
1737 ((p_reg->FEATURE.DPPIC.CHG[index] &
1738 ~SPU_FEATURE_DPPIC_CHG_SECATTR_Msk) |
1739 ((enable ?
1740 SPU_FEATURE_DPPIC_CHG_SECATTR_Secure :
1741 SPU_FEATURE_DPPIC_CHG_SECATTR_NonSecure)
1742 << SPU_FEATURE_DPPIC_CHG_SECATTR_Pos));
1743 break;
1744
1745 case NRF_SPU_FEATURE_GPIOTE_CHANNEL:
1746 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT);
1747 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_CHANNEL_COUNT);
1748 p_reg->FEATURE.GPIOTE[index].CH[subindex] =
1749 ((p_reg->FEATURE.GPIOTE[index].CH[subindex] &
1750 ~SPU_FEATURE_GPIOTE_CH_SECATTR_Msk) |
1751 ((enable ?
1752 SPU_FEATURE_GPIOTE_CH_SECATTR_Secure :
1753 SPU_FEATURE_GPIOTE_CH_SECATTR_NonSecure)
1754 << SPU_FEATURE_GPIOTE_CH_SECATTR_Pos));
1755 break;
1756
1757 case NRF_SPU_FEATURE_GPIOTE_INTERRUPT:
1758 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT);
1759 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_INTERRUPT_COUNT);
1760 p_reg->FEATURE.GPIOTE[index].INTERRUPT[subindex] =
1761 ((p_reg->FEATURE.GPIOTE[index].INTERRUPT[subindex] &
1762 ~SPU_FEATURE_GPIOTE_INTERRUPT_SECATTR_Msk) |
1763 ((enable ?
1764 SPU_FEATURE_GPIOTE_INTERRUPT_SECATTR_Secure :
1765 SPU_FEATURE_GPIOTE_INTERRUPT_SECATTR_NonSecure)
1766 << SPU_FEATURE_GPIOTE_INTERRUPT_SECATTR_Pos));
1767 break;
1768
1769 case NRF_SPU_FEATURE_GPIO_PIN:
1770 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIO_COUNT);
1771 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIO_PIN_COUNT);
1772 p_reg->FEATURE.GPIO[index].PIN[subindex] =
1773 ((p_reg->FEATURE.GPIO[index].PIN[subindex] &
1774 ~SPU_FEATURE_GPIO_PIN_SECATTR_Msk) |
1775 ((enable ?
1776 SPU_FEATURE_GPIO_PIN_SECATTR_Secure :
1777 SPU_FEATURE_GPIO_PIN_SECATTR_NonSecure)
1778 << SPU_FEATURE_GPIO_PIN_SECATTR_Pos));
1779 break;
1780
1781 case NRF_SPU_FEATURE_GRTC_CC:
1782 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_CC_COUNT);
1783 p_reg->FEATURE.GRTC.CC[index] =
1784 ((p_reg->FEATURE.GRTC.CC[index] &
1785 ~SPU_FEATURE_GRTC_CC_SECATTR_Msk) |
1786 ((enable ?
1787 SPU_FEATURE_GRTC_CC_SECATTR_Secure :
1788 SPU_FEATURE_GRTC_CC_SECATTR_NonSecure)
1789 << SPU_FEATURE_GRTC_CC_SECATTR_Pos));
1790 break;
1791
1792 case NRF_SPU_FEATURE_GRTC_SYSCOUNTER:
1793 p_reg->FEATURE.GRTC.SYSCOUNTER =
1794 ((p_reg->FEATURE.GRTC.SYSCOUNTER &
1795 ~SPU_FEATURE_GRTC_SYSCOUNTER_SECATTR_Msk) |
1796 ((enable ?
1797 SPU_FEATURE_GRTC_SYSCOUNTER_SECATTR_Secure :
1798 SPU_FEATURE_GRTC_SYSCOUNTER_SECATTR_NonSecure)
1799 << SPU_FEATURE_GRTC_SYSCOUNTER_SECATTR_Pos));
1800 break;
1801
1802 case NRF_SPU_FEATURE_GRTC_INTERRUPT:
1803 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_INTERRUPT_COUNT);
1804 p_reg->FEATURE.GRTC.INTERRUPT[index] =
1805 ((p_reg->FEATURE.GRTC.INTERRUPT[index] &
1806 ~SPU_FEATURE_GRTC_INTERRUPT_SECATTR_Msk) |
1807 ((enable ?
1808 SPU_FEATURE_GRTC_INTERRUPT_SECATTR_Secure :
1809 SPU_FEATURE_GRTC_INTERRUPT_SECATTR_NonSecure)
1810 << SPU_FEATURE_GRTC_INTERRUPT_SECATTR_Pos));
1811 break;
1812
1813 #if NRF_SPU_HAS_BELLS
1814 #if NRF_SPU_HAS_DOMAIN
1815 case NRF_SPU_FEATURE_BELLS_BELL:
1816 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELL_BELL_COUNT);
1817 p_reg->FEATURE.BELLS.DOMAIN[index].BELL[subindex] =
1818 ((p_reg->FEATURE.BELLS.DOMAIN[index].BELL[subindex] &
1819 ~SPU_FEATURE_BELLS_DOMAIN_BELL_SECATTR_Msk) |
1820 ((enable ?
1821 SPU_FEATURE_BELLS_DOMAIN_BELL_SECATTR_Secure :
1822 SPU_FEATURE_BELLS_DOMAIN_BELL_SECATTR_NonSecure)
1823 << SPU_FEATURE_BELLS_DOMAIN_BELL_SECATTR_Pos));
1824 break;
1825 #else
1826 case NRF_SPU_FEATURE_BELLS_TASKS:
1827 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_TASKS_COUNT);
1828 p_reg->FEATURE.BELLS.PROCESSOR[index].TASKS[subindex] =
1829 ((p_reg->FEATURE.BELLS.PROCESSOR[index].TASKS[subindex] &
1830 ~SPU_FEATURE_BELLS_PROCESSOR_TASKS_SECATTR_Msk) |
1831 ((enable ?
1832 SPU_FEATURE_BELLS_PROCESSOR_TASKS_SECATTR_Secure :
1833 SPU_FEATURE_BELLS_PROCESSOR_TASKS_SECATTR_NonSecure)
1834 << SPU_FEATURE_BELLS_PROCESSOR_TASKS_SECATTR_Pos));
1835 break;
1836
1837 case NRF_SPU_FEATURE_BELLS_EVENTS:
1838 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_EVENTS_COUNT);
1839 p_reg->FEATURE.BELLS.PROCESSOR[index].EVENTS[subindex] =
1840 ((p_reg->FEATURE.BELLS.PROCESSOR[index].EVENTS[subindex] &
1841 ~SPU_FEATURE_BELLS_PROCESSOR_EVENTS_SECATTR_Msk) |
1842 ((enable ?
1843 SPU_FEATURE_BELLS_PROCESSOR_EVENTS_SECATTR_Secure :
1844 SPU_FEATURE_BELLS_PROCESSOR_EVENTS_SECATTR_NonSecure)
1845 << SPU_FEATURE_BELLS_PROCESSOR_EVENTS_SECATTR_Pos));
1846 break;
1847
1848 case NRF_SPU_FEATURE_BELLS_INTERRUPT:
1849 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_INTERRUPT_COUNT);
1850 p_reg->FEATURE.BELLS.PROCESSOR[index].INTERRUPT[subindex] =
1851 ((p_reg->FEATURE.BELLS.PROCESSOR[index].INTERRUPT[subindex] &
1852 ~SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_SECATTR_Msk) |
1853 ((enable ?
1854 SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_SECATTR_Secure :
1855 SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_SECATTR_NonSecure)
1856 << SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_SECATTR_Pos));
1857 break;
1858 #endif // NRF_SPU_HAS_DOMAIN
1859 #endif // NRF_SPU_HAS_BELLS
1860
1861 #if NRF_SPU_HAS_TDD
1862 case NRF_SPU_FEATURE_TDD:
1863 NRFX_ASSERT(index < NRF_SPU_FEATURE_TDD_COUNT);
1864 p_reg->FEATURE.TDD[index] =
1865 ((p_reg->FEATURE.TDD[index] &
1866 SPU_FEATURE_TDD_SECATTR_Msk) |
1867 ((enable ?
1868 SPU_FEATURE_TDD_SECATTR_Secure :
1869 SPU_FEATURE_TDD_SECATTR_NonSecure)
1870 << SPU_FEATURE_TDD_SECATTR_Pos));
1871 break;
1872 #endif // NRF_SPU_HAS_TDD
1873
1874 #if NRF_SPU_HAS_MRAMC
1875 case NRF_SPU_FEATURE_MRAMC_WAITSTATES:
1876 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT);
1877 p_reg->FEATURE.MRAMC[index].WAITSTATES =
1878 ((p_reg->FEATURE.MRAMC[index].WAITSTATES &
1879 SPU_FEATURE_MRAMC_WAITSTATES_SECATTR_Msk) |
1880 ((enable ?
1881 SPU_FEATURE_MRAMC_WAITSTATES_SECATTR_Secure :
1882 SPU_FEATURE_MRAMC_WAITSTATES_SECATTR_NonSecure)
1883 << SPU_FEATURE_MRAMC_WAITSTATES_SECATTR_Pos));
1884 break;
1885
1886 case NRF_SPU_FEATURE_MRAMC_AUTODPOWERDOWN:
1887 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT);
1888 p_reg->FEATURE.MRAMC[index].AUTODPOWERDOWN =
1889 ((p_reg->FEATURE.MRAMC[index].AUTODPOWERDOWN &
1890 SPU_FEATURE_MRAMC_AUTODPOWERDOWN_SECATTR_Msk) |
1891 ((enable ?
1892 SPU_FEATURE_MRAMC_AUTODPOWERDOWN_SECATTR_Secure :
1893 SPU_FEATURE_MRAMC_AUTODPOWERDOWN_SECATTR_NonSecure)
1894 << SPU_FEATURE_MRAMC_AUTODPOWERDOWN_SECATTR_Pos));
1895 break;
1896
1897 case NRF_SPU_FEATURE_MRAMC_READY:
1898 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT);
1899 p_reg->FEATURE.MRAMC[index].READY =
1900 ((p_reg->FEATURE.MRAMC[index].READY &
1901 SPU_FEATURE_MRAMC_READY_SECATTR_Msk) |
1902 ((enable ?
1903 SPU_FEATURE_MRAMC_READY_SECATTR_Secure :
1904 SPU_FEATURE_MRAMC_READY_SECATTR_NonSecure)
1905 << SPU_FEATURE_MRAMC_READY_SECATTR_Pos));
1906 break;
1907 #endif // NRF_SPU_HAS_MRAMC
1908
1909 default:
1910 NRFX_ASSERT(0);
1911 break;
1912 }
1913 }
1914
nrf_spu_feature_lock_enable(NRF_SPU_Type * p_reg,nrf_spu_feature_t feature,uint8_t index,uint8_t subindex)1915 NRF_STATIC_INLINE void nrf_spu_feature_lock_enable(NRF_SPU_Type * p_reg,
1916 nrf_spu_feature_t feature,
1917 uint8_t index,
1918 uint8_t subindex)
1919 {
1920 switch (feature)
1921 {
1922 #if NRF_SPU_HAS_IPCT
1923 case NRF_SPU_FEATURE_IPCT_CHANNEL:
1924 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_CHANNEL_COUNT);
1925 p_reg->FEATURE.IPCT.CH[index] =
1926 ((p_reg->FEATURE.IPCT.CH[index] &
1927 ~SPU_FEATURE_IPCT_CH_LOCK_Msk) |
1928 (SPU_FEATURE_IPCT_CH_LOCK_Locked
1929 << SPU_FEATURE_IPCT_CH_LOCK_Pos));
1930 break;
1931
1932 case NRF_SPU_FEATURE_IPCT_INTERRUPT:
1933 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_INTERRUPT_COUNT);
1934 p_reg->FEATURE.IPCT.INTERRUPT[index] =
1935 ((p_reg->FEATURE.IPCT.INTERRUPT[index] &
1936 ~SPU_FEATURE_IPCT_INTERRUPT_LOCK_Msk) |
1937 (SPU_FEATURE_IPCT_INTERRUPT_LOCK_Locked
1938 << SPU_FEATURE_IPCT_INTERRUPT_LOCK_Pos));
1939 break;
1940 #endif // NRF_SPU_HAS_IPCT
1941
1942 case NRF_SPU_FEATURE_DPPI_CHANNEL:
1943 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_COUNT);
1944 p_reg->FEATURE.DPPIC.CH[index] =
1945 ((p_reg->FEATURE.DPPIC.CH[index] &
1946 ~SPU_FEATURE_DPPIC_CH_LOCK_Msk) |
1947 (SPU_FEATURE_DPPIC_CH_LOCK_Locked
1948 << SPU_FEATURE_DPPIC_CH_LOCK_Pos));
1949 break;
1950
1951 case NRF_SPU_FEATURE_DPPI_CHANNEL_GROUP:
1952 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_GROUP_COUNT);
1953 p_reg->FEATURE.DPPIC.CHG[index] =
1954 ((p_reg->FEATURE.DPPIC.CHG[index] &
1955 ~SPU_FEATURE_DPPIC_CHG_LOCK_Msk) |
1956 (SPU_FEATURE_DPPIC_CHG_LOCK_Locked
1957 << SPU_FEATURE_DPPIC_CHG_LOCK_Pos));
1958 break;
1959
1960 case NRF_SPU_FEATURE_GPIOTE_CHANNEL:
1961 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT);
1962 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_CHANNEL_COUNT);
1963 p_reg->FEATURE.GPIOTE[index].CH[subindex] =
1964 ((p_reg->FEATURE.GPIOTE[index].CH[subindex] &
1965 ~SPU_FEATURE_GPIOTE_CH_LOCK_Msk) |
1966 (SPU_FEATURE_GPIOTE_CH_LOCK_Locked
1967 << SPU_FEATURE_GPIOTE_CH_LOCK_Pos));
1968 break;
1969
1970 case NRF_SPU_FEATURE_GPIOTE_INTERRUPT:
1971 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT);
1972 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_INTERRUPT_COUNT);
1973 p_reg->FEATURE.GPIOTE[index].INTERRUPT[subindex] =
1974 ((p_reg->FEATURE.GPIOTE[index].INTERRUPT[subindex] &
1975 ~SPU_FEATURE_GPIOTE_INTERRUPT_LOCK_Msk) |
1976 (SPU_FEATURE_GPIOTE_INTERRUPT_LOCK_Locked
1977 << SPU_FEATURE_GPIOTE_INTERRUPT_LOCK_Pos));
1978 break;
1979
1980 case NRF_SPU_FEATURE_GPIO_PIN:
1981 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIO_COUNT);
1982 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIO_PIN_COUNT);
1983 p_reg->FEATURE.GPIO[index].PIN[subindex] =
1984 ((p_reg->FEATURE.GPIO[index].PIN[subindex] &
1985 ~SPU_FEATURE_GPIO_PIN_LOCK_Msk) |
1986 (SPU_FEATURE_GPIO_PIN_LOCK_Locked
1987 << SPU_FEATURE_GPIO_PIN_LOCK_Pos));
1988 break;
1989
1990 case NRF_SPU_FEATURE_GRTC_CC:
1991 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_CC_COUNT);
1992 p_reg->FEATURE.GRTC.CC[index] =
1993 ((p_reg->FEATURE.GRTC.CC[index] &
1994 ~SPU_FEATURE_GRTC_CC_LOCK_Msk) |
1995 (SPU_FEATURE_GRTC_CC_LOCK_Locked
1996 << SPU_FEATURE_GRTC_CC_LOCK_Pos));
1997 break;
1998
1999 case NRF_SPU_FEATURE_GRTC_SYSCOUNTER:
2000 p_reg->FEATURE.GRTC.SYSCOUNTER =
2001 ((p_reg->FEATURE.GRTC.SYSCOUNTER &
2002 ~SPU_FEATURE_GRTC_SYSCOUNTER_LOCK_Msk) |
2003 (SPU_FEATURE_GRTC_SYSCOUNTER_LOCK_Locked
2004 << SPU_FEATURE_GRTC_SYSCOUNTER_LOCK_Pos));
2005 break;
2006
2007 case NRF_SPU_FEATURE_GRTC_INTERRUPT:
2008 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_INTERRUPT_COUNT);
2009 p_reg->FEATURE.GRTC.INTERRUPT[index] =
2010 ((p_reg->FEATURE.GRTC.INTERRUPT[index] &
2011 ~SPU_FEATURE_GRTC_INTERRUPT_LOCK_Msk) |
2012 (SPU_FEATURE_GRTC_INTERRUPT_LOCK_Locked
2013 << SPU_FEATURE_GRTC_INTERRUPT_LOCK_Pos));
2014 break;
2015
2016 #if NRF_SPU_HAS_BELLS
2017 #if NRF_SPU_HAS_DOMAIN
2018 case NRF_SPU_FEATURE_BELLS_BELL:
2019 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELL_BELL_COUNT);
2020 p_reg->FEATURE.BELLS.DOMAIN[index].BELL[subindex] =
2021 ((p_reg->FEATURE.BELLS.DOMAIN[index].BELL[subindex] &
2022 ~SPU_FEATURE_BELLS_DOMAIN_BELL_LOCK_Msk) |
2023 (SPU_FEATURE_BELLS_DOMAIN_BELL_LOCK_Locked
2024 << SPU_FEATURE_BELLS_DOMAIN_BELL_LOCK_Pos));
2025 break;
2026 #else
2027 case NRF_SPU_FEATURE_BELLS_TASKS:
2028 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_TASKS_COUNT);
2029 p_reg->FEATURE.BELLS.PROCESSOR[index].TASKS[subindex] =
2030 ((p_reg->FEATURE.BELLS.PROCESSOR[index].TASKS[subindex] &
2031 ~SPU_FEATURE_BELLS_PROCESSOR_TASKS_LOCK_Msk) |
2032 (SPU_FEATURE_BELLS_PROCESSOR_TASKS_LOCK_Locked
2033 << SPU_FEATURE_BELLS_PROCESSOR_TASKS_LOCK_Pos));
2034 break;
2035
2036 case NRF_SPU_FEATURE_BELLS_EVENTS:
2037 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_EVENTS_COUNT);
2038 p_reg->FEATURE.BELLS.PROCESSOR[index].EVENTS[subindex] =
2039 ((p_reg->FEATURE.BELLS.PROCESSOR[index].EVENTS[subindex] &
2040 ~SPU_FEATURE_BELLS_PROCESSOR_EVENTS_LOCK_Msk) |
2041 (SPU_FEATURE_BELLS_PROCESSOR_EVENTS_LOCK_Locked
2042 << SPU_FEATURE_BELLS_PROCESSOR_EVENTS_LOCK_Pos));
2043 break;
2044
2045 case NRF_SPU_FEATURE_BELLS_INTERRUPT:
2046 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_INTERRUPT_COUNT);
2047 p_reg->FEATURE.BELLS.PROCESSOR[index].INTERRUPT[subindex] =
2048 ((p_reg->FEATURE.BELLS.PROCESSOR[index].INTERRUPT[subindex] &
2049 ~SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_LOCK_Msk) |
2050 (SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_LOCK_Locked
2051 << SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_LOCK_Pos));
2052 break;
2053 #endif // NRF_SPU_HAS_DOMAIN
2054 #endif // NRF_SPU_HAS_BELLS
2055
2056 #if NRF_SPU_HAS_TDD
2057 case NRF_SPU_FEATURE_TDD:
2058 NRFX_ASSERT(index < NRF_SPU_FEATURE_TDD_COUNT);
2059 p_reg->FEATURE.TDD[index] =
2060 ((p_reg->FEATURE.TDD[index] &
2061 SPU_FEATURE_TDD_LOCK_Msk) |
2062 (SPU_FEATURE_TDD_LOCK_Locked
2063 << SPU_FEATURE_TDD_LOCK_Pos));
2064 break;
2065 #endif // NRF_SPU_HAS_TDD
2066
2067 #if NRF_SPU_HAS_MRAMC
2068 case NRF_SPU_FEATURE_MRAMC_WAITSTATES:
2069 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT);
2070 p_reg->FEATURE.MRAMC[index].WAITSTATES =
2071 ((p_reg->FEATURE.MRAMC[index].WAITSTATES &
2072 SPU_FEATURE_MRAMC_WAITSTATES_LOCK_Msk) |
2073 (SPU_FEATURE_MRAMC_WAITSTATES_LOCK_Locked
2074 << SPU_FEATURE_MRAMC_WAITSTATES_LOCK_Pos));
2075 break;
2076
2077 case NRF_SPU_FEATURE_MRAMC_AUTODPOWERDOWN:
2078 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT);
2079 p_reg->FEATURE.MRAMC[index].AUTODPOWERDOWN =
2080 ((p_reg->FEATURE.MRAMC[index].AUTODPOWERDOWN &
2081 SPU_FEATURE_MRAMC_AUTODPOWERDOWN_LOCK_Msk) |
2082 (SPU_FEATURE_MRAMC_AUTODPOWERDOWN_LOCK_Locked
2083 << SPU_FEATURE_MRAMC_AUTODPOWERDOWN_LOCK_Pos));
2084 break;
2085
2086 case NRF_SPU_FEATURE_MRAMC_READY:
2087 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT);
2088 p_reg->FEATURE.MRAMC[index].READY =
2089 ((p_reg->FEATURE.MRAMC[index].READY &
2090 SPU_FEATURE_MRAMC_READY_LOCK_Msk) |
2091 (SPU_FEATURE_MRAMC_READY_LOCK_Locked
2092 << SPU_FEATURE_MRAMC_READY_LOCK_Pos));
2093 break;
2094 #endif // NRF_SPU_HAS_MRAMC
2095
2096 default:
2097 NRFX_ASSERT(0);
2098 break;
2099 }
2100 }
2101
2102 #if NRF_SPU_HAS_BLOCK
nrf_spu_feature_block_enable(NRF_SPU_Type * p_reg,nrf_spu_feature_t feature,uint8_t index,uint8_t subindex)2103 NRF_STATIC_INLINE void nrf_spu_feature_block_enable(NRF_SPU_Type * p_reg,
2104 nrf_spu_feature_t feature,
2105 uint8_t index,
2106 uint8_t subindex)
2107 {
2108 switch (feature)
2109 {
2110 #if NRF_SPU_HAS_IPCT
2111 case NRF_SPU_FEATURE_IPCT_CHANNEL:
2112 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_CHANNEL_COUNT);
2113 p_reg->FEATURE.IPCT.CH[index] =
2114 ((p_reg->FEATURE.IPCT.CH[index] &
2115 ~SPU_FEATURE_IPCT_CH_BLOCK_Msk) |
2116 (SPU_FEATURE_IPCT_CH_BLOCK_Blocked
2117 << SPU_FEATURE_IPCT_CH_BLOCK_Pos));
2118 break;
2119
2120 case NRF_SPU_FEATURE_IPCT_INTERRUPT:
2121 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_INTERRUPT_COUNT);
2122 p_reg->FEATURE.IPCT.INTERRUPT[index] =
2123 ((p_reg->FEATURE.IPCT.INTERRUPT[index] &
2124 ~SPU_FEATURE_IPCT_INTERRUPT_BLOCK_Msk) |
2125 (SPU_FEATURE_IPCT_INTERRUPT_BLOCK_Blocked
2126 << SPU_FEATURE_IPCT_INTERRUPT_BLOCK_Pos));
2127 break;
2128 #endif // NRF_SPU_HAS_IPCT
2129
2130 case NRF_SPU_FEATURE_DPPI_CHANNEL:
2131 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_COUNT);
2132 p_reg->FEATURE.DPPIC.CH[index] =
2133 ((p_reg->FEATURE.DPPIC.CH[index] &
2134 ~SPU_FEATURE_DPPIC_CH_BLOCK_Msk) |
2135 (SPU_FEATURE_DPPIC_CH_BLOCK_Blocked
2136 << SPU_FEATURE_DPPIC_CH_BLOCK_Pos));
2137 break;
2138
2139 case NRF_SPU_FEATURE_DPPI_CHANNEL_GROUP:
2140 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_GROUP_COUNT);
2141 p_reg->FEATURE.DPPIC.CHG[index] =
2142 ((p_reg->FEATURE.DPPIC.CHG[index] &
2143 ~SPU_FEATURE_DPPIC_CHG_BLOCK_Msk) |
2144 (SPU_FEATURE_DPPIC_CHG_BLOCK_Blocked
2145 << SPU_FEATURE_DPPIC_CHG_BLOCK_Pos));
2146 break;
2147
2148 case NRF_SPU_FEATURE_GPIOTE_CHANNEL:
2149 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT);
2150 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_CHANNEL_COUNT);
2151 p_reg->FEATURE.GPIOTE[index].CH[subindex] =
2152 ((p_reg->FEATURE.GPIOTE[index].CH[subindex] &
2153 ~SPU_FEATURE_GPIOTE_CH_BLOCK_Msk) |
2154 (SPU_FEATURE_GPIOTE_CH_BLOCK_Blocked
2155 << SPU_FEATURE_GPIOTE_CH_BLOCK_Pos));
2156 break;
2157
2158 case NRF_SPU_FEATURE_GPIOTE_INTERRUPT:
2159 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT);
2160 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_INTERRUPT_COUNT);
2161 p_reg->FEATURE.GPIOTE[index].INTERRUPT[subindex] =
2162 ((p_reg->FEATURE.GPIOTE[index].INTERRUPT[subindex] &
2163 ~SPU_FEATURE_GPIOTE_INTERRUPT_BLOCK_Msk) |
2164 (SPU_FEATURE_GPIOTE_INTERRUPT_BLOCK_Blocked
2165 << SPU_FEATURE_GPIOTE_INTERRUPT_BLOCK_Pos));
2166 break;
2167
2168 case NRF_SPU_FEATURE_GPIO_PIN:
2169 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIO_COUNT);
2170 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIO_PIN_COUNT);
2171 p_reg->FEATURE.GPIO[index].PIN[subindex] =
2172 ((p_reg->FEATURE.GPIO[index].PIN[subindex] &
2173 ~SPU_FEATURE_GPIO_PIN_BLOCK_Msk) |
2174 (SPU_FEATURE_GPIO_PIN_BLOCK_Blocked
2175 << SPU_FEATURE_GPIO_PIN_BLOCK_Pos));
2176 break;
2177
2178 case NRF_SPU_FEATURE_GRTC_CC:
2179 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_CC_COUNT);
2180 p_reg->FEATURE.GRTC.CC[index] =
2181 ((p_reg->FEATURE.GRTC.CC[index] &
2182 ~SPU_FEATURE_GRTC_CC_BLOCK_Msk) |
2183 (SPU_FEATURE_GRTC_CC_BLOCK_Blocked
2184 << SPU_FEATURE_GRTC_CC_BLOCK_Pos));
2185 break;
2186
2187 case NRF_SPU_FEATURE_GRTC_SYSCOUNTER:
2188 p_reg->FEATURE.GRTC.SYSCOUNTER =
2189 ((p_reg->FEATURE.GRTC.SYSCOUNTER &
2190 ~SPU_FEATURE_GRTC_SYSCOUNTER_BLOCK_Msk) |
2191 (SPU_FEATURE_GRTC_SYSCOUNTER_BLOCK_Blocked
2192 << SPU_FEATURE_GRTC_SYSCOUNTER_BLOCK_Pos));
2193 break;
2194
2195 case NRF_SPU_FEATURE_GRTC_INTERRUPT:
2196 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_INTERRUPT_COUNT);
2197 p_reg->FEATURE.GRTC.INTERRUPT[index] =
2198 ((p_reg->FEATURE.GRTC.INTERRUPT[index] &
2199 ~SPU_FEATURE_GRTC_INTERRUPT_BLOCK_Msk) |
2200 (SPU_FEATURE_GRTC_INTERRUPT_BLOCK_Blocked
2201 << SPU_FEATURE_GRTC_INTERRUPT_BLOCK_Pos));
2202 break;
2203
2204 #if NRF_SPU_HAS_BELLS
2205 #if NRF_SPU_HAS_DOMAIN
2206 case NRF_SPU_FEATURE_BELLS_BELL:
2207 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELL_BELL_COUNT);
2208 p_reg->FEATURE.BELLS.DOMAIN[index].BELL[subindex] =
2209 ((p_reg->FEATURE.BELLS.DOMAIN[index].BELL[subindex] &
2210 ~SPU_FEATURE_BELLS_DOMAIN_BELL_BLOCK_Msk) |
2211 (SPU_FEATURE_BELLS_DOMAIN_BELL_BLOCK_Blocked
2212 << SPU_FEATURE_BELLS_DOMAIN_BELL_BLOCK_Pos));
2213 break;
2214 #else
2215 case NRF_SPU_FEATURE_BELLS_TASKS:
2216 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_TASKS_COUNT);
2217 p_reg->FEATURE.BELLS.PROCESSOR[index].TASKS[subindex] =
2218 ((p_reg->FEATURE.BELLS.PROCESSOR[index].TASKS[subindex] &
2219 ~SPU_FEATURE_BELLS_PROCESSOR_TASKS_BLOCK_Msk) |
2220 (SPU_FEATURE_BELLS_PROCESSOR_TASKS_BLOCK_Blocked
2221 << SPU_FEATURE_BELLS_PROCESSOR_TASKS_BLOCK_Pos));
2222 break;
2223
2224 case NRF_SPU_FEATURE_BELLS_EVENTS:
2225 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_EVENTS_COUNT);
2226 p_reg->FEATURE.BELLS.PROCESSOR[index].EVENTS[subindex] =
2227 ((p_reg->FEATURE.BELLS.PROCESSOR[index].EVENTS[subindex] &
2228 ~SPU_FEATURE_BELLS_PROCESSOR_EVENTS_BLOCK_Msk) |
2229 (SPU_FEATURE_BELLS_PROCESSOR_EVENTS_BLOCK_Blocked
2230 << SPU_FEATURE_BELLS_PROCESSOR_EVENTS_BLOCK_Pos));
2231 break;
2232
2233 case NRF_SPU_FEATURE_BELLS_INTERRUPT:
2234 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_INTERRUPT_COUNT);
2235 p_reg->FEATURE.BELLS.PROCESSOR[index].INTERRUPT[subindex] =
2236 ((p_reg->FEATURE.BELLS.PROCESSOR[index].INTERRUPT[subindex] &
2237 ~SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_BLOCK_Msk) |
2238 (SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_BLOCK_Blocked
2239 << SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_BLOCK_Pos));
2240 break;
2241 #endif // NRF_SPU_HAS_DOMAIN
2242 #endif // NRF_SPU_HAS_BELLS
2243
2244 #if NRF_SPU_HAS_TDD
2245 case NRF_SPU_FEATURE_TDD:
2246 NRFX_ASSERT(index < NRF_SPU_FEATURE_TDD_COUNT);
2247 p_reg->FEATURE.TDD[index] =
2248 ((p_reg->FEATURE.TDD[index] &
2249 SPU_FEATURE_TDD_BLOCK_Msk) |
2250 (SPU_FEATURE_TDD_BLOCK_Blocked
2251 << SPU_FEATURE_TDD_BLOCK_Pos));
2252 break;
2253 #endif // NRF_SPU_HAS_TDD
2254
2255 #if NRF_SPU_HAS_MRAMC
2256 case NRF_SPU_FEATURE_MRAMC_WAITSTATES:
2257 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT);
2258 p_reg->FEATURE.MRAMC[index].WAITSTATES =
2259 ((p_reg->FEATURE.MRAMC[index].WAITSTATES &
2260 SPU_FEATURE_MRAMC_WAITSTATES_BLOCK_Msk) |
2261 (SPU_FEATURE_MRAMC_WAITSTATES_BLOCK_Blocked
2262 << SPU_FEATURE_MRAMC_WAITSTATES_BLOCK_Pos));
2263 break;
2264
2265 case NRF_SPU_FEATURE_MRAMC_AUTODPOWERDOWN:
2266 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT);
2267 p_reg->FEATURE.MRAMC[index].AUTODPOWERDOWN =
2268 ((p_reg->FEATURE.MRAMC[index].AUTODPOWERDOWN &
2269 SPU_FEATURE_MRAMC_AUTODPOWERDOWN_BLOCK_Msk) |
2270 (SPU_FEATURE_MRAMC_AUTODPOWERDOWN_BLOCK_Blocked
2271 << SPU_FEATURE_MRAMC_AUTODPOWERDOWN_BLOCK_Pos));
2272 break;
2273
2274 case NRF_SPU_FEATURE_MRAMC_READY:
2275 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT);
2276 p_reg->FEATURE.MRAMC[index].READY =
2277 ((p_reg->FEATURE.MRAMC[index].READY &
2278 SPU_FEATURE_MRAMC_READY_BLOCK_Msk) |
2279 (SPU_FEATURE_MRAMC_READY_BLOCK_Blocked
2280 << SPU_FEATURE_MRAMC_READY_LOCK_Pos));
2281 break;
2282 #endif // NRF_SPU_HAS_MRAMC
2283
2284 default:
2285 NRFX_ASSERT(0);
2286 break;
2287 }
2288 }
2289 #endif // NRF_SPU_HAS_BLOCK
2290
2291 #if NRF_SPU_HAS_OWNERSHIP
nrf_spu_feature_ownerid_set(NRF_SPU_Type * p_reg,nrf_spu_feature_t feature,uint8_t index,uint8_t subindex,nrf_owner_t owner_id)2292 NRF_STATIC_INLINE void nrf_spu_feature_ownerid_set(NRF_SPU_Type * p_reg,
2293 nrf_spu_feature_t feature,
2294 uint8_t index,
2295 uint8_t subindex,
2296 nrf_owner_t owner_id)
2297 {
2298 switch (feature)
2299 {
2300 #if NRF_SPU_HAS_IPCT
2301 case NRF_SPU_FEATURE_IPCT_CHANNEL:
2302 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_CHANNEL_COUNT);
2303 p_reg->FEATURE.IPCT.CH[index] =
2304 ((p_reg->FEATURE.IPCT.CH[index] &
2305 ~SPU_FEATURE_IPCT_CH_OWNERID_Msk) |
2306 ((owner_id
2307 << SPU_FEATURE_IPCT_CH_OWNERID_Pos) &
2308 SPU_FEATURE_IPCT_CH_OWNERID_Msk));
2309 break;
2310
2311 case NRF_SPU_FEATURE_IPCT_INTERRUPT:
2312 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_INTERRUPT_COUNT);
2313 p_reg->FEATURE.IPCT.INTERRUPT[index] =
2314 ((p_reg->FEATURE.IPCT.INTERRUPT[index] &
2315 ~SPU_FEATURE_IPCT_INTERRUPT_OWNERID_Msk) |
2316 ((owner_id
2317 << SPU_FEATURE_IPCT_INTERRUPT_OWNERID_Pos) &
2318 SPU_FEATURE_IPCT_INTERRUPT_OWNERID_Msk));
2319 break;
2320 #endif // NRF_SPU_HAS_IPCT
2321
2322 case NRF_SPU_FEATURE_DPPI_CHANNEL:
2323 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_COUNT);
2324 p_reg->FEATURE.DPPIC.CH[index] =
2325 ((p_reg->FEATURE.DPPIC.CH[index] &
2326 ~SPU_FEATURE_DPPIC_CH_OWNERID_Msk) |
2327 ((owner_id
2328 << SPU_FEATURE_DPPIC_CH_OWNERID_Pos) &
2329 SPU_FEATURE_DPPIC_CH_OWNERID_Msk));
2330 break;
2331
2332 case NRF_SPU_FEATURE_DPPI_CHANNEL_GROUP:
2333 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_GROUP_COUNT);
2334 p_reg->FEATURE.DPPIC.CHG[index] =
2335 ((p_reg->FEATURE.DPPIC.CHG[index] &
2336 ~SPU_FEATURE_DPPIC_CHG_OWNERID_Msk) |
2337 ((owner_id
2338 << SPU_FEATURE_DPPIC_CHG_OWNERID_Pos) &
2339 SPU_FEATURE_DPPIC_CHG_OWNERID_Msk));
2340 break;
2341
2342 case NRF_SPU_FEATURE_GPIOTE_CHANNEL:
2343 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT);
2344 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_CHANNEL_COUNT);
2345 p_reg->FEATURE.GPIOTE[index].CH[subindex] =
2346 ((p_reg->FEATURE.GPIOTE[index].CH[subindex] &
2347 ~SPU_FEATURE_GPIOTE_CH_OWNERID_Msk) |
2348 ((owner_id
2349 << SPU_FEATURE_GPIOTE_CH_OWNERID_Pos) &
2350 SPU_FEATURE_GPIOTE_CH_OWNERID_Msk));
2351 break;
2352
2353 case NRF_SPU_FEATURE_GPIOTE_INTERRUPT:
2354 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT);
2355 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_INTERRUPT_COUNT);
2356 p_reg->FEATURE.GPIOTE[index].INTERRUPT[subindex] =
2357 ((p_reg->FEATURE.GPIOTE[index].INTERRUPT[subindex] &
2358 ~SPU_FEATURE_GPIOTE_INTERRUPT_OWNERID_Msk) |
2359 ((owner_id
2360 << SPU_FEATURE_GPIOTE_INTERRUPT_OWNERID_Pos) &
2361 SPU_FEATURE_GPIOTE_INTERRUPT_OWNERID_Msk));
2362 break;
2363
2364 case NRF_SPU_FEATURE_GPIO_PIN:
2365 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIO_COUNT);
2366 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIO_PIN_COUNT);
2367 p_reg->FEATURE.GPIO[index].PIN[subindex] =
2368 ((p_reg->FEATURE.GPIO[index].PIN[subindex] &
2369 ~SPU_FEATURE_GPIO_PIN_OWNERID_Msk) |
2370 ((owner_id
2371 << SPU_FEATURE_GPIO_PIN_OWNERID_Pos) &
2372 SPU_FEATURE_GPIO_PIN_OWNERID_Msk));
2373 break;
2374
2375 case NRF_SPU_FEATURE_GRTC_CC:
2376 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_CC_COUNT);
2377 p_reg->FEATURE.GRTC.CC[index] =
2378 ((p_reg->FEATURE.GRTC.CC[index] &
2379 ~SPU_FEATURE_GRTC_CC_OWNERID_Msk) |
2380 ((owner_id
2381 << SPU_FEATURE_GRTC_CC_OWNERID_Pos) &
2382 SPU_FEATURE_GRTC_CC_OWNERID_Msk));
2383 break;
2384
2385 case NRF_SPU_FEATURE_GRTC_SYSCOUNTER:
2386 p_reg->FEATURE.GRTC.SYSCOUNTER =
2387 ((p_reg->FEATURE.GRTC.SYSCOUNTER &
2388 ~SPU_FEATURE_GRTC_SYSCOUNTER_OWNERID_Msk) |
2389 ((owner_id
2390 << SPU_FEATURE_GRTC_SYSCOUNTER_OWNERID_Pos) &
2391 SPU_FEATURE_GRTC_SYSCOUNTER_OWNERID_Msk));
2392 break;
2393
2394 case NRF_SPU_FEATURE_GRTC_INTERRUPT:
2395 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_INTERRUPT_COUNT);
2396 p_reg->FEATURE.GRTC.INTERRUPT[index] =
2397 ((p_reg->FEATURE.GRTC.INTERRUPT[index] &
2398 ~SPU_FEATURE_GRTC_INTERRUPT_OWNERID_Msk) |
2399 ((owner_id
2400 << SPU_FEATURE_GRTC_INTERRUPT_OWNERID_Pos) &
2401 SPU_FEATURE_GRTC_INTERRUPT_OWNERID_Msk));
2402 break;
2403
2404 #if NRF_SPU_HAS_BELLS
2405 #if NRF_SPU_HAS_DOMAIN
2406 case NRF_SPU_FEATURE_BELLS_BELL:
2407 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELL_BELL_COUNT);
2408 p_reg->FEATURE.BELLS.DOMAIN[index].BELL[subindex] =
2409 ((p_reg->FEATURE.BELLS.DOMAIN[index].BELL[subindex] &
2410 ~SPU_FEATURE_BELLS_DOMAIN_BELL_OWNERID_Msk) |
2411 ((owner_id
2412 << SPU_FEATURE_BELLS_DOMAIN_BELL_OWNERID_Pos) &
2413 SPU_FEATURE_BELLS_DOMAIN_BELL_OWNERID_Msk));
2414 break;
2415 #else
2416 case NRF_SPU_FEATURE_BELLS_TASKS:
2417 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_TASKS_COUNT);
2418 p_reg->FEATURE.BELLS.PROCESSOR[index].TASKS[subindex] =
2419 ((p_reg->FEATURE.BELLS.PROCESSOR[index].TASKS[subindex] &
2420 ~SPU_FEATURE_BELLS_PROCESSOR_TASKS_OWNERID_Msk) |
2421 ((owner_id
2422 << SPU_FEATURE_BELLS_PROCESSOR_TASKS_OWNERID_Pos) &
2423 SPU_FEATURE_BELLS_PROCESSOR_TASKS_OWNERID_Msk));
2424 break;
2425
2426 case NRF_SPU_FEATURE_BELLS_EVENTS:
2427 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_EVENTS_COUNT);
2428 p_reg->FEATURE.BELLS.PROCESSOR[index].EVENTS[subindex] =
2429 ((p_reg->FEATURE.BELLS.PROCESSOR[index].EVENTS[subindex] &
2430 ~SPU_FEATURE_BELLS_PROCESSOR_EVENTS_OWNERID_Msk) |
2431 ((owner_id
2432 << SPU_FEATURE_BELLS_PROCESSOR_EVENTS_OWNERID_Pos) &
2433 SPU_FEATURE_BELLS_PROCESSOR_EVENTS_OWNERID_Msk));
2434 break;
2435
2436 case NRF_SPU_FEATURE_BELLS_INTERRUPT:
2437 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_INTERRUPT_COUNT);
2438 p_reg->FEATURE.BELLS.PROCESSOR[index].INTERRUPT[subindex] =
2439 ((p_reg->FEATURE.BELLS.PROCESSOR[index].INTERRUPT[subindex] &
2440 ~SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_OWNERID_Msk) |
2441 ((owner_id
2442 << SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_OWNERID_Pos) &
2443 SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_OWNERID_Msk));
2444 break;
2445 #endif // NRF_SPU_HAS_DOMAIN
2446 #endif // NRF_SPU_HAS_BELLS
2447
2448 #if NRF_SPU_HAS_TDD
2449 case NRF_SPU_FEATURE_TDD:
2450 NRFX_ASSERT(index < NRF_SPU_FEATURE_TDD_COUNT);
2451 p_reg->FEATURE.TDD[index] =
2452 ((p_reg->FEATURE.TDD[index] &
2453 SPU_FEATURE_TDD_OWNERID_Msk) |
2454 ((owner_id
2455 << SPU_FEATURE_TDD_OWNERID_Pos) &
2456 SPU_FEATURE_TDD_OWNERID_Msk));
2457 break;
2458 #endif // NRF_SPU_HAS_TDD
2459
2460 #if NRF_SPU_HAS_MRAMC
2461 case NRF_SPU_FEATURE_MRAMC_WAITSTATES:
2462 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT);
2463 p_reg->FEATURE.MRAMC[index].WAITSTATES =
2464 ((p_reg->FEATURE.MRAMC[index].WAITSTATES &
2465 SPU_FEATURE_MRAMC_WAITSTATES_OWNERID_Msk) |
2466 ((owner_id
2467 << SPU_FEATURE_MRAMC_WAITSTATES_OWNERID_Pos) &
2468 SPU_FEATURE_MRAMC_WAITSTATES_OWNERID_Msk));
2469 break;
2470
2471 case NRF_SPU_FEATURE_MRAMC_AUTODPOWERDOWN:
2472 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT);
2473 p_reg->FEATURE.MRAMC[index].AUTODPOWERDOWN =
2474 ((p_reg->FEATURE.MRAMC[index].AUTODPOWERDOWN &
2475 SPU_FEATURE_MRAMC_AUTODPOWERDOWN_OWNERID_Msk) |
2476 ((owner_id
2477 << SPU_FEATURE_MRAMC_AUTODPOWERDOWN_OWNERID_Pos) &
2478 SPU_FEATURE_MRAMC_AUTODPOWERDOWN_OWNERID_Msk));
2479 break;
2480
2481 case NRF_SPU_FEATURE_MRAMC_READY:
2482 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT);
2483 p_reg->FEATURE.MRAMC[index].READY =
2484 ((p_reg->FEATURE.MRAMC[index].READY &
2485 SPU_FEATURE_MRAMC_READY_OWNERID_Msk) |
2486 ((owner_id
2487 << SPU_FEATURE_MRAMC_READY_OWNERID_Pos) &
2488 SPU_FEATURE_MRAMC_READY_OWNERID_Msk));
2489 break;
2490 #endif // NRF_SPU_HAS_MRAMC
2491
2492 default:
2493 NRFX_ASSERT(0);
2494 break;
2495 }
2496 }
2497 #endif // NRF_SPU_HAS_OWNERSHIP
2498
2499 #endif // NRF_SPU_HAS_PERIPHERAL_ACCESS
2500
2501 #endif // NRF_DECLARE_ONLY
2502
2503 /** @} */
2504
2505 #ifdef __cplusplus
2506 }
2507 #endif
2508
2509 #endif // NRF_SPU_H__
2510
