1 /*
2 * Copyright (c) 2015 - 2024, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_SPIS_H__
35 #define NRF_SPIS_H__
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 #if defined(NRF54H20_XXAA)
44 #define NRF_SPIS_CLOCKPIN_MISO_NEEDED 1
45 #endif
46
47 #if defined(HALTIUM_XXAA)
48 #define NRF_SPIS_CLOCKPIN_SCK_NEEDED 1
49 #endif
50
51 /**
52 * @defgroup nrf_spis_hal SPIS HAL
53 * @{
54 * @ingroup nrf_spis
55 * @brief Hardware access layer for managing the SPIS peripheral.
56 */
57
58 #if defined(SPIS_DMA_TX_PTR_PTR_Msk) || defined(__NRFX_DOXYGEN__)
59 /** @brief Symbol indicating whether dedicated DMA register is present. */
60 #define NRF_SPIS_HAS_DMA_REG 1
61 #else
62 #define NRF_SPIS_HAS_DMA_REG 0
63 #endif
64
65 #if (defined(SPIS_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Msk) && \
66 defined(SPIS_EVENTS_DMA_RX_END_END_Msk)) || \
67 defined(__NRFX_DOXYGEN__)
68 /** @brief Symbol indicating whether SPIS DMA tasks and events are present. */
69 #define NRF_SPIS_HAS_DMA_TASKS_EVENTS 1
70 #else
71 #define NRF_SPIS_HAS_DMA_TASKS_EVENTS 0
72 #endif
73
74 #if NRF_SPIS_HAS_DMA_TASKS_EVENTS
75 /** @brief Maximum number of RX patterns. */
76 #define NRF_SPIS_DMA_RX_PATTERN_MAX_COUNT SPIS_DMA_RX_MATCH_CANDIDATE_MaxCount
77 #endif
78
79 /**
80 * @brief Macro getting pointer to the structure of registers of the SPIS peripheral.
81 *
82 * @param[in] idx SPIS instance index.
83 *
84 * @return Pointer to the structure of registers of the SPIS peripheral.
85 */
86 #define NRF_SPIS_INST_GET(idx) NRFX_CONCAT(NRF_, SPIS, idx)
87
88 /**
89 * @brief This value can be used as a parameter for the @ref nrf_spis_pins_set
90 * function to specify that a given SPI signal (SCK, MOSI, or MISO)
91 * shall not be connected to a physical pin.
92 */
93 #define NRF_SPIS_PIN_NOT_CONNECTED 0xFFFFFFFF
94
95 /** @brief SPIS tasks. */
96 typedef enum
97 {
98 NRF_SPIS_TASK_ACQUIRE = offsetof(NRF_SPIS_Type, TASKS_ACQUIRE), ///< Acquire SPI semaphore.
99 NRF_SPIS_TASK_RELEASE = offsetof(NRF_SPIS_Type, TASKS_RELEASE), ///< Release SPI semaphore, enabling the SPI slave to acquire it.
100 #if NRF_SPIS_HAS_DMA_TASKS_EVENTS
101 NRF_SPIS_TASK_ENABLERXMATCH0 = offsetof(NRF_SPIS_Type, TASKS_DMA.RX.ENABLEMATCH[0]), ///< Enable SPI pattern matching functionality for pattern 0.
102 NRF_SPIS_TASK_ENABLERXMATCH1 = offsetof(NRF_SPIS_Type, TASKS_DMA.RX.ENABLEMATCH[1]), ///< Enable SPI pattern matching functionality for pattern 1.
103 NRF_SPIS_TASK_ENABLERXMATCH2 = offsetof(NRF_SPIS_Type, TASKS_DMA.RX.ENABLEMATCH[2]), ///< Enable SPI pattern matching functionality for pattern 2.
104 NRF_SPIS_TASK_ENABLERXMATCH3 = offsetof(NRF_SPIS_Type, TASKS_DMA.RX.ENABLEMATCH[3]), ///< Enable SPI pattern matching functionality for pattern 3.
105 NRF_SPIS_TASK_DISABLERXMATCH0 = offsetof(NRF_SPIS_Type, TASKS_DMA.RX.DISABLEMATCH[0]), ///< Disable SPI pattern matching functionality for pattern 0.
106 NRF_SPIS_TASK_DISABLERXMATCH1 = offsetof(NRF_SPIS_Type, TASKS_DMA.RX.DISABLEMATCH[1]), ///< Disable SPI pattern matching functionality for pattern 1.
107 NRF_SPIS_TASK_DISABLERXMATCH2 = offsetof(NRF_SPIS_Type, TASKS_DMA.RX.DISABLEMATCH[2]), ///< Disable SPI pattern matching functionality for pattern 2.
108 NRF_SPIS_TASK_DISABLERXMATCH3 = offsetof(NRF_SPIS_Type, TASKS_DMA.RX.DISABLEMATCH[3]) ///< Disable SPI pattern matching functionality for pattern 3.
109 #endif
110 } nrf_spis_task_t;
111
112 /** @brief SPIS events. */
113 typedef enum
114 {
115 #if NRF_SPIS_HAS_DMA_TASKS_EVENTS
116 NRF_SPIS_EVENT_RXSTARTED = offsetof(NRF_SPIS_Type, EVENTS_DMA.RX.READY), ///< Receive sequence started.
117 NRF_SPIS_EVENT_RXBUSERROR = offsetof(NRF_SPIS_Type, EVENTS_DMA.RX.BUSERROR), ///< Memory bus error occurred during the RX transfer.
118 NRF_SPIS_EVENT_RXMATCH0 = offsetof(NRF_SPIS_Type, EVENTS_DMA.RX.MATCH[0]), ///< Pattern match for pattern 0 detected.
119 NRF_SPIS_EVENT_RXMATCH1 = offsetof(NRF_SPIS_Type, EVENTS_DMA.RX.MATCH[1]), ///< Pattern match for pattern 1 detected.
120 NRF_SPIS_EVENT_RXMATCH2 = offsetof(NRF_SPIS_Type, EVENTS_DMA.RX.MATCH[2]), ///< Pattern match for pattern 2 detected.
121 NRF_SPIS_EVENT_RXMATCH3 = offsetof(NRF_SPIS_Type, EVENTS_DMA.RX.MATCH[3]), ///< Pattern match for pattern 3 detected.
122 NRF_SPIS_EVENT_TXSTARTED = offsetof(NRF_SPIS_Type, EVENTS_DMA.TX.READY), ///< Transmit sequence started.
123 NRF_SPIS_EVENT_TXBUSERROR = offsetof(NRF_SPIS_Type, EVENTS_DMA.TX.BUSERROR), ///< Memory bus error occurred during the TX transfer.
124 NRF_SPIS_EVENT_ENDRX = offsetof(NRF_SPIS_Type, EVENTS_DMA.RX.END), ///< End of RXD buffer reached.
125 NRF_SPIS_EVENT_ENDTX = offsetof(NRF_SPIS_Type, EVENTS_DMA.TX.END), ///< End of TXD buffer reached.
126 #endif
127 NRF_SPIS_EVENT_END = offsetof(NRF_SPIS_Type, EVENTS_END), ///< Granted transaction completed.
128 NRF_SPIS_EVENT_ACQUIRED = offsetof(NRF_SPIS_Type, EVENTS_ACQUIRED) ///< Semaphore acquired.
129 } nrf_spis_event_t;
130
131 /** @brief SPIS shortcuts. */
132 typedef enum
133 {
134 NRF_SPIS_SHORT_END_ACQUIRE = SPIS_SHORTS_END_ACQUIRE_Msk, ///< Shortcut between END event and ACQUIRE task.
135 #if NRF_SPIS_HAS_DMA_TASKS_EVENTS
136 NRF_SPIS_SHORT_RXMATCH0_ENABLERXMATCH1_MASK = SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Msk, ///< Shortcut between DMA.RX.MATCH0 event and DMA.RX.ENABLEMATCH1 task.
137 NRF_SPIS_SHORT_RXMATCH1_ENABLERXMATCH2_MASK = SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Msk, ///< Shortcut between DMA.RX.MATCH1 event and DMA.RX.ENABLEMATCH2 task.
138 NRF_SPIS_SHORT_RXMATCH2_ENABLERXMATCH3_MASK = SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Msk, ///< Shortcut between DMA.RX.MATCH2 event and DMA.RX.ENABLEMATCH3 task.
139 NRF_SPIS_SHORT_RXMATCH3_ENABLERXMATCH0_MASK = SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Msk, ///< Shortcut between DMA.RX.MATCH3 event and DMA.RX.ENABLEMATCH0 task.
140 NRF_SPIS_SHORT_RXMATCH0_DISABLERXMATCH0_MASK = SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Msk, ///< Shortcut between DMA.RX.MATCH0 event and DMA.RX.DISABLEMATCH0 task.
141 NRF_SPIS_SHORT_RXMATCH1_DISABLERXMATCH1_MASK = SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Msk, ///< Shortcut between DMA.RX.MATCH1 event and DMA.RX.DISABLEMATCH1 task.
142 NRF_SPIS_SHORT_RXMATCH2_DISABLERXMATCH2_MASK = SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Msk, ///< Shortcut between DMA.RX.MATCH2 event and DMA.RX.DISABLEMATCH2 task.
143 NRF_SPIS_SHORT_RXMATCH3_DISABLERXMATCH3_MASK = SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Msk, ///< Shortcut between DMA.RX.MATCH3 event and DMA.RX.DISABLEMATCH3 task.
144 #endif
145 NRF_SPIS_ALL_SHORTS_MASK = NRF_SPIS_SHORT_END_ACQUIRE
146 #if NRF_SPIS_HAS_DMA_TASKS_EVENTS
147 | NRF_SPIS_SHORT_RXMATCH0_ENABLERXMATCH1_MASK
148 | NRF_SPIS_SHORT_RXMATCH1_ENABLERXMATCH2_MASK
149 | NRF_SPIS_SHORT_RXMATCH2_ENABLERXMATCH3_MASK
150 | NRF_SPIS_SHORT_RXMATCH3_ENABLERXMATCH0_MASK
151 | NRF_SPIS_SHORT_RXMATCH0_DISABLERXMATCH0_MASK
152 | NRF_SPIS_SHORT_RXMATCH1_DISABLERXMATCH1_MASK
153 | NRF_SPIS_SHORT_RXMATCH2_DISABLERXMATCH2_MASK
154 | NRF_SPIS_SHORT_RXMATCH3_DISABLERXMATCH3_MASK ///< All SPIS shortcuts.
155 #endif
156 } nrf_spis_short_mask_t;
157
158 /** @brief SPIS interrupts. */
159 typedef enum
160 {
161 NRF_SPIS_INT_END_MASK = SPIS_INTENSET_END_Msk, ///< Interrupt on END event.
162 NRF_SPIS_INT_ACQUIRED_MASK = SPIS_INTENSET_ACQUIRED_Msk, ///< Interrupt on ACQUIRED event.
163 #if NRF_SPIS_HAS_DMA_TASKS_EVENTS
164 NRF_SPIS_INT_RXREADY_MASK = SPIS_INTENSET_DMARXREADY_Msk, ///< Interrupt on DMA.RX.READY event.
165 NRF_SPIS_INT_RXBUSERROR_MASK = SPIS_INTENSET_DMARXBUSERROR_Msk, ///< Interrupt on DMA.RX.BUSERROR event.
166 NRF_SPIS_INT_RXMATCH0_MASK = SPIS_INTENSET_DMARXMATCH0_Msk, ///< Interrupt on DMA.RX.MATCH0 event.
167 NRF_SPIS_INT_RXMATCH1_MASK = SPIS_INTENSET_DMARXMATCH1_Msk, ///< Interrupt on DMA.RX.MATCH1 event.
168 NRF_SPIS_INT_RXMATCH2_MASK = SPIS_INTENSET_DMARXMATCH2_Msk, ///< Interrupt on DMA.RX.MATCH2 event.
169 NRF_SPIS_INT_RXMATCH3_MASK = SPIS_INTENSET_DMARXMATCH3_Msk, ///< Interrupt on DMA.RX.MATCH3 event.
170 NRF_SPIS_INT_TXREADY_MASK = SPIS_INTENSET_DMATXREADY_Msk, ///< Interrupt on DMA.TX.READY event.
171 NRF_SPIS_INT_TXBUSERROR_MASK = SPIS_INTENSET_DMATXBUSERROR_Msk, ///< Interrupt on DMA.TX.BUSERROR event.
172 NRF_SPIS_INT_ENDRX_MASK = SPIS_INTENSET_DMARXEND_Msk, ///< Interrupt on ENDRX event.
173 NRF_SPIS_INT_ENDTX_MASK = SPIS_INTENSET_DMATXEND_Msk, ///< Interrupt on ENDTX event.
174 #endif
175 NRF_SPIS_ALL_INTS_MASK = NRF_SPIS_INT_END_MASK
176 | NRF_SPIS_INT_ACQUIRED_MASK
177 #if NRF_SPIS_HAS_DMA_TASKS_EVENTS
178 | NRF_SPIS_INT_RXREADY_MASK
179 | NRF_SPIS_INT_RXBUSERROR_MASK
180 | NRF_SPIS_INT_RXMATCH0_MASK
181 | NRF_SPIS_INT_RXMATCH1_MASK
182 | NRF_SPIS_INT_RXMATCH2_MASK
183 | NRF_SPIS_INT_RXMATCH3_MASK
184 | NRF_SPIS_INT_TXREADY_MASK
185 | NRF_SPIS_INT_TXBUSERROR_MASK
186 | NRF_SPIS_INT_ENDRX_MASK
187 | NRF_SPIS_INT_ENDTX_MASK ///< All SPIS interrupts.
188 #endif
189 } nrf_spis_int_mask_t;
190
191 /** @brief SPI modes. */
192 typedef enum
193 {
194 NRF_SPIS_MODE_0, ///< SCK active high, sample on leading edge of clock.
195 NRF_SPIS_MODE_1, ///< SCK active high, sample on trailing edge of clock.
196 NRF_SPIS_MODE_2, ///< SCK active low, sample on leading edge of clock.
197 NRF_SPIS_MODE_3 ///< SCK active low, sample on trailing edge of clock.
198 } nrf_spis_mode_t;
199
200 /** @brief SPI bit orders. */
201 typedef enum
202 {
203 NRF_SPIS_BIT_ORDER_MSB_FIRST = SPIS_CONFIG_ORDER_MsbFirst, ///< Most significant bit shifted out first.
204 NRF_SPIS_BIT_ORDER_LSB_FIRST = SPIS_CONFIG_ORDER_LsbFirst ///< Least significant bit shifted out first.
205 } nrf_spis_bit_order_t;
206
207 /** @brief SPI semaphore status. */
208 typedef enum
209 {
210 NRF_SPIS_SEMSTAT_FREE = 0, ///< Semaphore is free.
211 NRF_SPIS_SEMSTAT_CPU = 1, ///< Semaphore is assigned to the CPU.
212 NRF_SPIS_SEMSTAT_SPIS = 2, ///< Semaphore is assigned to the SPI slave.
213 NRF_SPIS_SEMSTAT_CPUPENDING = 3 ///< Semaphore is assigned to the SPI, but a handover to the CPU is pending.
214 } nrf_spis_semstat_t;
215
216 /** @brief SPIS status. */
217 typedef enum
218 {
219 NRF_SPIS_STATUS_OVERREAD = SPIS_STATUS_OVERREAD_Msk, ///< TX buffer over-read detected and prevented.
220 NRF_SPIS_STATUS_OVERFLOW = SPIS_STATUS_OVERFLOW_Msk ///< RX buffer overflow detected and prevented.
221 } nrf_spis_status_mask_t;
222
223
224 /**
225 * @brief Function for activating the specified SPIS task.
226 *
227 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
228 * @param[in] task Task to be activated.
229 */
230 NRF_STATIC_INLINE void nrf_spis_task_trigger(NRF_SPIS_Type * p_reg,
231 nrf_spis_task_t task);
232
233 /**
234 * @brief Function for getting the address of the specified SPIS task register.
235 *
236 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
237 * @param[in] task The specified task.
238 *
239 * @return Address of the specified task register.
240 */
241 NRF_STATIC_INLINE uint32_t nrf_spis_task_address_get(NRF_SPIS_Type const * p_reg,
242 nrf_spis_task_t task);
243
244 /**
245 * @brief Function for clearing the specified SPIS event.
246 *
247 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
248 * @param[in] event Event to be cleared.
249 */
250 NRF_STATIC_INLINE void nrf_spis_event_clear(NRF_SPIS_Type * p_reg,
251 nrf_spis_event_t event);
252
253 /**
254 * @brief Function for retrieving the state of the SPIS event.
255 *
256 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
257 * @param[in] event Event to be checked.
258 *
259 * @retval true The event has been generated.
260 * @retval false The event has not been generated.
261 */
262 NRF_STATIC_INLINE bool nrf_spis_event_check(NRF_SPIS_Type const * p_reg,
263 nrf_spis_event_t event);
264
265 /**
266 * @brief Function for getting the address of the specified SPIS event register.
267 *
268 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
269 * @param[in] event The specified event.
270 *
271 * @return Address of the specified event register.
272 */
273 NRF_STATIC_INLINE uint32_t nrf_spis_event_address_get(NRF_SPIS_Type const * p_reg,
274 nrf_spis_event_t event);
275
276 /**
277 * @brief Function for enabling the specified shortcuts.
278 *
279 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
280 * @param[in] mask Shortcuts to be enabled.
281 */
282 NRF_STATIC_INLINE void nrf_spis_shorts_enable(NRF_SPIS_Type * p_reg,
283 uint32_t mask);
284
285 /**
286 * @brief Function for disabling the specified shortcuts.
287 *
288 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
289 * @param[in] mask Shortcuts to be disabled.
290 */
291 NRF_STATIC_INLINE void nrf_spis_shorts_disable(NRF_SPIS_Type * p_reg,
292 uint32_t mask);
293
294 /**
295 * @brief Function for enabling the specified interrupts.
296 *
297 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
298 * @param[in] mask Mask of interrupts to be enabled.
299 * Use @ref nrf_spis_int_mask_t values for bit masking.
300 */
301 NRF_STATIC_INLINE void nrf_spis_int_enable(NRF_SPIS_Type * p_reg,
302 uint32_t mask);
303
304 /**
305 * @brief Function for disabling the specified interrupts.
306 *
307 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
308 * @param[in] mask Mask of interrupts to be disabled.
309 * Use @ref nrf_spis_int_mask_t values for bit masking.
310 */
311 NRF_STATIC_INLINE void nrf_spis_int_disable(NRF_SPIS_Type * p_reg,
312 uint32_t mask);
313
314 /**
315 * @brief Function for checking if the specified interrupts are enabled.
316 *
317 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
318 * @param[in] mask Mask of interrupts to be checked.
319 * Use @ref nrf_spis_int_mask_t values for bit masking.
320 *
321 * @return Mask of enabled interrupts.
322 */
323 NRF_STATIC_INLINE uint32_t nrf_spis_int_enable_check(NRF_SPIS_Type const * p_reg, uint32_t mask);
324
325 #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
326 /**
327 * @brief Function for setting the subscribe configuration for a given
328 * SPIS task.
329 *
330 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
331 * @param[in] task Task for which to set the configuration.
332 * @param[in] channel Channel through which to subscribe events.
333 */
334 NRF_STATIC_INLINE void nrf_spis_subscribe_set(NRF_SPIS_Type * p_reg,
335 nrf_spis_task_t task,
336 uint8_t channel);
337
338 /**
339 * @brief Function for clearing the subscribe configuration for a given
340 * SPIS task.
341 *
342 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
343 * @param[in] task Task for which to clear the configuration.
344 */
345 NRF_STATIC_INLINE void nrf_spis_subscribe_clear(NRF_SPIS_Type * p_reg,
346 nrf_spis_task_t task);
347
348 /**
349 * @brief Function for setting the publish configuration for a given
350 * SPIS event.
351 *
352 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
353 * @param[in] event Event for which to set the configuration.
354 * @param[in] channel Channel through which to publish the event.
355 */
356 NRF_STATIC_INLINE void nrf_spis_publish_set(NRF_SPIS_Type * p_reg,
357 nrf_spis_event_t event,
358 uint8_t channel);
359
360 /**
361 * @brief Function for clearing the publish configuration for a given
362 * SPIS event.
363 *
364 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
365 * @param[in] event Event for which to clear the configuration.
366 */
367 NRF_STATIC_INLINE void nrf_spis_publish_clear(NRF_SPIS_Type * p_reg,
368 nrf_spis_event_t event);
369 #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
370
371 /**
372 * @brief Function for enabling the SPIS peripheral.
373 *
374 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
375 */
376 NRF_STATIC_INLINE void nrf_spis_enable(NRF_SPIS_Type * p_reg);
377
378 /**
379 * @brief Function for disabling the SPIS peripheral.
380 *
381 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
382 */
383 NRF_STATIC_INLINE void nrf_spis_disable(NRF_SPIS_Type * p_reg);
384
385 /**
386 * @brief Function for checking if the SPIS peripheral is enabled.
387 *
388 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
389 *
390 * @retval true The SPIS is enabled.
391 * @retval false The SPIS is not enabled.
392 */
393 NRF_STATIC_INLINE bool nrf_spis_enable_check(NRF_SPIS_Type const * p_reg);
394
395 /**
396 * @brief Function for retrieving the SPIS semaphore status.
397 *
398 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
399 *
400 * @returns Current semaphore status.
401 */
402 NRF_STATIC_INLINE nrf_spis_semstat_t nrf_spis_semaphore_status_get(NRF_SPIS_Type const * p_reg);
403
404 /**
405 * @brief Function for retrieving the SPIS status.
406 *
407 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
408 *
409 * @returns Current SPIS status.
410 */
411 NRF_STATIC_INLINE nrf_spis_status_mask_t nrf_spis_status_get(NRF_SPIS_Type const * p_reg);
412
413 /**
414 * @brief Function for configuring SPIS pins.
415 *
416 * If a given signal is not needed, pass the @ref NRF_SPIS_PIN_NOT_CONNECTED
417 * value instead of its pin number.
418 *
419 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
420 * @param[in] sck_pin SCK pin number.
421 * @param[in] mosi_pin MOSI pin number.
422 * @param[in] miso_pin MISO pin number.
423 * @param[in] csn_pin CSN pin number.
424 */
425 NRF_STATIC_INLINE void nrf_spis_pins_set(NRF_SPIS_Type * p_reg,
426 uint32_t sck_pin,
427 uint32_t mosi_pin,
428 uint32_t miso_pin,
429 uint32_t csn_pin);
430
431 /**
432 * @brief Function for getting the SCK pin selection.
433 *
434 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
435 *
436 * @return SCK pin selection.
437 */
438 NRF_STATIC_INLINE uint32_t nrf_spis_sck_pin_get(NRF_SPIS_Type const * p_reg);
439
440 /**
441 * @brief Function for getting the MOSI pin selection.
442 *
443 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
444 *
445 * @return MOSI pin selection.
446 */
447 NRF_STATIC_INLINE uint32_t nrf_spis_mosi_pin_get(NRF_SPIS_Type const * p_reg);
448
449 /**
450 * @brief Function for getting the MISO pin selection.
451 *
452 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
453 *
454 * @return MISO pin selection.
455 */
456 NRF_STATIC_INLINE uint32_t nrf_spis_miso_pin_get(NRF_SPIS_Type const * p_reg);
457
458 /**
459 * @brief Function for getting the CSN pin selection.
460 *
461 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
462 *
463 * @return CSN pin selection.
464 */
465 NRF_STATIC_INLINE uint32_t nrf_spis_csn_pin_get(NRF_SPIS_Type const * p_reg);
466
467 /**
468 * @brief Function for setting the transmit buffer.
469 *
470 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
471 * @param[in] p_buffer Pointer to the buffer that contains the data to send.
472 * @param[in] length Maximum number of data bytes to transmit.
473 */
474 NRF_STATIC_INLINE void nrf_spis_tx_buffer_set(NRF_SPIS_Type * p_reg,
475 uint8_t const * p_buffer,
476 size_t length);
477
478 /**
479 * @brief Function for setting the receive buffer.
480 *
481 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
482 * @param[in] p_buffer Pointer to the buffer for received data.
483 * @param[in] length Maximum number of data bytes to receive.
484 */
485 NRF_STATIC_INLINE void nrf_spis_rx_buffer_set(NRF_SPIS_Type * p_reg,
486 uint8_t * p_buffer,
487 size_t length);
488
489 /**
490 * @brief Function for getting the number of bytes transmitted
491 * in the last granted transaction.
492 *
493 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
494 *
495 * @returns Number of bytes transmitted.
496 */
497 NRF_STATIC_INLINE size_t nrf_spis_tx_amount_get(NRF_SPIS_Type const * p_reg);
498
499 /**
500 * @brief Function for getting the number of bytes received
501 * in the last granted transaction.
502 *
503 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
504 *
505 * @returns Number of bytes received.
506 */
507 NRF_STATIC_INLINE size_t nrf_spis_rx_amount_get(NRF_SPIS_Type const * p_reg);
508
509 /**
510 * @brief Function for setting the SPI configuration.
511 *
512 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
513 * @param[in] spi_mode SPI mode.
514 * @param[in] spi_bit_order SPI bit order.
515 */
516 NRF_STATIC_INLINE void nrf_spis_configure(NRF_SPIS_Type * p_reg,
517 nrf_spis_mode_t spi_mode,
518 nrf_spis_bit_order_t spi_bit_order);
519
520 /**
521 * @brief Function for setting the default character.
522 *
523 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
524 * @param[in] def Default character that is clocked out in case of
525 * an overflow of the RXD buffer.
526 */
527 NRF_STATIC_INLINE void nrf_spis_def_set(NRF_SPIS_Type * p_reg,
528 uint8_t def);
529
530 /**
531 * @brief Function for setting the over-read character.
532 *
533 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
534 * @param[in] orc Over-read character that is clocked out in case of
535 * an over-read of the TXD buffer.
536 */
537 NRF_STATIC_INLINE void nrf_spis_orc_set(NRF_SPIS_Type * p_reg,
538 uint8_t orc);
539
540 #if defined(SPIS_TXD_LIST_LIST_Msk) || defined(__NRFX_DOXYGEN__)
541 /**
542 * @brief Function for enabling the TX list feature.
543 *
544 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
545 */
546 NRF_STATIC_INLINE void nrf_spis_tx_list_enable(NRF_SPIS_Type * p_reg);
547
548 /**
549 * @brief Function for disabling the TX list feature.
550 *
551 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
552 */
553 NRF_STATIC_INLINE void nrf_spis_tx_list_disable(NRF_SPIS_Type * p_reg);
554 #endif // defined(SPIS_TXD_LIST_LIST_Msk) || defined(__NRFX_DOXYGEN__)
555
556 #if defined(SPIS_RXD_LIST_LIST_Msk) || defined(__NRFX_DOXYGEN__)
557 /**
558 * @brief Function for enabling the RX list feature.
559 *
560 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
561 */
562 NRF_STATIC_INLINE void nrf_spis_rx_list_enable(NRF_SPIS_Type * p_reg);
563
564 /**
565 * @brief Function for disabling the RX list feature.
566 *
567 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
568 */
569 NRF_STATIC_INLINE void nrf_spis_rx_list_disable(NRF_SPIS_Type * p_reg);
570 #endif // defined(SPIS_RXD_LIST_LIST_Msk) || defined(__NRFX_DOXYGEN__)
571
572 #if NRF_SPIS_HAS_DMA_TASKS_EVENTS
573 /**
574 * @brief Function for enabling individual pattern match filters.
575 *
576 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
577 * @param[in] index Index of pattern match filter.
578 * @param[in] enable True if pattern match filter is to be enabled, false otherwise.
579 */
580 NRF_STATIC_INLINE void nrf_spis_rx_pattern_match_enable_set(NRF_SPIS_Type * p_reg,
581 uint8_t index,
582 bool enable);
583
584 /**
585 * @brief Function for checking if the specified pattern match filter is enabled.
586 *
587 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
588 * @param[in] index Index of pattern match filter.
589 *
590 * @retval true Pattern match filter is enabled.
591 * @retval false Pattern match filter is disabled.
592 */
593 NRF_STATIC_INLINE bool nrf_spis_rx_pattern_match_enable_check(NRF_SPIS_Type const * p_reg,
594 uint8_t index);
595
596 /**
597 * @brief Function for enabling one-shot operation for the specified match filter.
598 *
599 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
600 * @param[in] index Index of pattern match filter.
601 */
602 NRF_STATIC_INLINE void nrf_spis_rx_pattern_match_one_shot_enable(NRF_SPIS_Type * p_reg,
603 uint8_t index);
604
605 /**
606 * @brief Function for disabling one-shot operation for the specified match filter.
607 *
608 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
609 * @param[in] index Index of pattern match filter.
610 */
611 NRF_STATIC_INLINE void nrf_spis_rx_pattern_match_one_shot_disable(NRF_SPIS_Type * p_reg,
612 uint8_t index);
613
614 /**
615 * @brief Function for checking if specified pattern match filter is configured as one-shot.
616 *
617 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
618 * @param[in] index Index of pattern match filter.
619 *
620 * @retval true Pattern match filter is configured as one-shot.
621 * @retval false Pattern match filter is configured as continuous.
622 */
623 NRF_STATIC_INLINE bool nrf_spis_rx_pattern_match_one_shot_check(NRF_SPIS_Type const * p_reg,
624 uint8_t index);
625
626 /**
627 * @brief Function for setting the pattern to be looked for by the specified match filter.
628 *
629 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
630 * @param[in] index Index of pattern match filter.
631 * @param[in] pattern Pattern to be looked for.
632 * Match will trigger the corresponding event, if enabled.
633 */
634 NRF_STATIC_INLINE void nrf_spis_rx_pattern_match_candidate_set(NRF_SPIS_Type * p_reg,
635 uint8_t index,
636 uint32_t pattern);
637
638 /**
639 * @brief Function for getting the pattern that the specified match filter is looking for.
640 *
641 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
642 * @param[in] index Index of pattern match filter.
643 *
644 * @return Pattern that the specified match filter is looking for.
645 */
646 NRF_STATIC_INLINE uint32_t nrf_spis_rx_pattern_match_candidate_get(NRF_SPIS_Type const * p_reg,
647 uint8_t index);
648 #endif // NRF_SPIS_HAS_DMA_TASKS_EVENTS
649
650 #if NRF_SPIS_HAS_DMA_REG
651 /**
652 * @brief Function for enabling the termination of the RX transaction after detecting the BUSERROR event.
653 *
654 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
655 */
656 NRF_STATIC_INLINE void nrf_spis_rx_terminate_on_bus_error_enable(NRF_SPIS_Type * p_reg);
657
658 /**
659 * @brief Function for disabling the termination of the RX transaction after detecting the BUSERROR event.
660 *
661 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
662 */
663 NRF_STATIC_INLINE void nrf_spis_rx_terminate_on_bus_error_disable(NRF_SPIS_Type * p_reg);
664
665 /**
666 * @brief Function for checking if RX transaction termination after detecting the BUSERROR event is enabled.
667 *
668 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
669 *
670 * @retval true RX transaction termination after detecting a BUSERROR event is enabled.
671 * @retval false RX transaction termination after detecting a BUSERROR event is disabled.
672 */
673 NRF_STATIC_INLINE bool nrf_spis_rx_terminate_on_bus_error_check(NRF_SPIS_Type const * p_reg);
674
675 /**
676 * @brief Function for enabling the termination of the TX transaction after detecting the BUSERROR event.
677 *
678 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
679 */
680 NRF_STATIC_INLINE void nrf_spis_tx_terminate_on_bus_error_enable(NRF_SPIS_Type * p_reg);
681
682 /**
683 * @brief Function for disabling the termination of the TX transaction after detecting the BUSERROR event.
684 *
685 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
686 */
687 NRF_STATIC_INLINE void nrf_spis_tx_terminate_on_bus_error_disable(NRF_SPIS_Type * p_reg);
688
689 /**
690 * @brief Function for checking if TX transaction termination after detecting the BUSERROR event is enabled.
691 *
692 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
693 *
694 * @retval true TX transaction termination after detecting a BUSERROR event is enabled.
695 * @retval false TX transaction termination after detecting a BUSERROR event is disabled.
696 */
697 NRF_STATIC_INLINE bool nrf_spis_tx_terminate_on_bus_error_check(NRF_SPIS_Type const * p_reg);
698 #endif // NRF_SPIS_HAS_DMA_REG
699
700 #ifndef NRF_DECLARE_ONLY
701
nrf_spis_task_trigger(NRF_SPIS_Type * p_reg,nrf_spis_task_t task)702 NRF_STATIC_INLINE void nrf_spis_task_trigger(NRF_SPIS_Type * p_reg,
703 nrf_spis_task_t task)
704 {
705 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
706 }
707
nrf_spis_task_address_get(NRF_SPIS_Type const * p_reg,nrf_spis_task_t task)708 NRF_STATIC_INLINE uint32_t nrf_spis_task_address_get(NRF_SPIS_Type const * p_reg,
709 nrf_spis_task_t task)
710 {
711 return (uint32_t)p_reg + (uint32_t)task;
712 }
713
nrf_spis_event_clear(NRF_SPIS_Type * p_reg,nrf_spis_event_t event)714 NRF_STATIC_INLINE void nrf_spis_event_clear(NRF_SPIS_Type * p_reg,
715 nrf_spis_event_t event)
716 {
717 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
718 nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
719 }
720
nrf_spis_event_check(NRF_SPIS_Type const * p_reg,nrf_spis_event_t event)721 NRF_STATIC_INLINE bool nrf_spis_event_check(NRF_SPIS_Type const * p_reg,
722 nrf_spis_event_t event)
723 {
724 return nrf_event_check(p_reg, event);
725 }
726
nrf_spis_event_address_get(NRF_SPIS_Type const * p_reg,nrf_spis_event_t event)727 NRF_STATIC_INLINE uint32_t nrf_spis_event_address_get(NRF_SPIS_Type const * p_reg,
728 nrf_spis_event_t event)
729 {
730 return (uint32_t)p_reg + (uint32_t)event;
731 }
732
nrf_spis_shorts_enable(NRF_SPIS_Type * p_reg,uint32_t mask)733 NRF_STATIC_INLINE void nrf_spis_shorts_enable(NRF_SPIS_Type * p_reg,
734 uint32_t mask)
735 {
736 p_reg->SHORTS |= mask;
737 }
738
nrf_spis_shorts_disable(NRF_SPIS_Type * p_reg,uint32_t mask)739 NRF_STATIC_INLINE void nrf_spis_shorts_disable(NRF_SPIS_Type * p_reg,
740 uint32_t mask)
741 {
742 p_reg->SHORTS &= ~(mask);
743 }
744
nrf_spis_int_enable(NRF_SPIS_Type * p_reg,uint32_t mask)745 NRF_STATIC_INLINE void nrf_spis_int_enable(NRF_SPIS_Type * p_reg,
746 uint32_t mask)
747 {
748 p_reg->INTENSET = mask;
749 }
750
nrf_spis_int_disable(NRF_SPIS_Type * p_reg,uint32_t mask)751 NRF_STATIC_INLINE void nrf_spis_int_disable(NRF_SPIS_Type * p_reg,
752 uint32_t mask)
753 {
754 p_reg->INTENCLR = mask;
755 }
756
nrf_spis_int_enable_check(NRF_SPIS_Type const * p_reg,uint32_t mask)757 NRF_STATIC_INLINE uint32_t nrf_spis_int_enable_check(NRF_SPIS_Type const * p_reg, uint32_t mask)
758 {
759 return p_reg->INTENSET & mask;
760 }
761
762 #if defined(DPPI_PRESENT)
nrf_spis_subscribe_set(NRF_SPIS_Type * p_reg,nrf_spis_task_t task,uint8_t channel)763 NRF_STATIC_INLINE void nrf_spis_subscribe_set(NRF_SPIS_Type * p_reg,
764 nrf_spis_task_t task,
765 uint8_t channel)
766 {
767 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
768 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
769 }
770
nrf_spis_subscribe_clear(NRF_SPIS_Type * p_reg,nrf_spis_task_t task)771 NRF_STATIC_INLINE void nrf_spis_subscribe_clear(NRF_SPIS_Type * p_reg,
772 nrf_spis_task_t task)
773 {
774 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
775 }
776
nrf_spis_publish_set(NRF_SPIS_Type * p_reg,nrf_spis_event_t event,uint8_t channel)777 NRF_STATIC_INLINE void nrf_spis_publish_set(NRF_SPIS_Type * p_reg,
778 nrf_spis_event_t event,
779 uint8_t channel)
780 {
781 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
782 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
783 }
784
nrf_spis_publish_clear(NRF_SPIS_Type * p_reg,nrf_spis_event_t event)785 NRF_STATIC_INLINE void nrf_spis_publish_clear(NRF_SPIS_Type * p_reg,
786 nrf_spis_event_t event)
787 {
788 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
789 }
790 #endif // defined(DPPI_PRESENT)
791
nrf_spis_enable(NRF_SPIS_Type * p_reg)792 NRF_STATIC_INLINE void nrf_spis_enable(NRF_SPIS_Type * p_reg)
793 {
794 p_reg->ENABLE = (SPIS_ENABLE_ENABLE_Enabled << SPIS_ENABLE_ENABLE_Pos);
795 }
796
nrf_spis_disable(NRF_SPIS_Type * p_reg)797 NRF_STATIC_INLINE void nrf_spis_disable(NRF_SPIS_Type * p_reg)
798 {
799 p_reg->ENABLE = (SPIS_ENABLE_ENABLE_Disabled << SPIS_ENABLE_ENABLE_Pos);
800 }
801
nrf_spis_enable_check(NRF_SPIS_Type const * p_reg)802 NRF_STATIC_INLINE bool nrf_spis_enable_check(NRF_SPIS_Type const * p_reg)
803 {
804 return p_reg->ENABLE == SPIS_ENABLE_ENABLE_Enabled;
805 }
806
nrf_spis_semaphore_status_get(NRF_SPIS_Type const * p_reg)807 NRF_STATIC_INLINE nrf_spis_semstat_t nrf_spis_semaphore_status_get(NRF_SPIS_Type const * p_reg)
808 {
809 return (nrf_spis_semstat_t) ((p_reg->SEMSTAT & SPIS_SEMSTAT_SEMSTAT_Msk)
810 >> SPIS_SEMSTAT_SEMSTAT_Pos);
811 }
812
nrf_spis_status_get(NRF_SPIS_Type const * p_reg)813 NRF_STATIC_INLINE nrf_spis_status_mask_t nrf_spis_status_get(NRF_SPIS_Type const * p_reg)
814 {
815 return (nrf_spis_status_mask_t) p_reg->STATUS;
816 }
817
nrf_spis_pins_set(NRF_SPIS_Type * p_reg,uint32_t sck_pin,uint32_t mosi_pin,uint32_t miso_pin,uint32_t csn_pin)818 NRF_STATIC_INLINE void nrf_spis_pins_set(NRF_SPIS_Type * p_reg,
819 uint32_t sck_pin,
820 uint32_t mosi_pin,
821 uint32_t miso_pin,
822 uint32_t csn_pin)
823 {
824 #if defined (NRF51)
825 p_reg->PSELSCK = sck_pin;
826 p_reg->PSELMOSI = mosi_pin;
827 p_reg->PSELMISO = miso_pin;
828 p_reg->PSELCSN = csn_pin;
829 #else
830 p_reg->PSEL.SCK = sck_pin;
831 p_reg->PSEL.MOSI = mosi_pin;
832 p_reg->PSEL.MISO = miso_pin;
833 p_reg->PSEL.CSN = csn_pin;
834 #endif
835 }
836
nrf_spis_sck_pin_get(NRF_SPIS_Type const * p_reg)837 NRF_STATIC_INLINE uint32_t nrf_spis_sck_pin_get(NRF_SPIS_Type const * p_reg)
838 {
839 #if defined (NRF51)
840 return p_reg->PSELSCK;
841 #else
842 return p_reg->PSEL.SCK;
843 #endif
844 }
845
nrf_spis_mosi_pin_get(NRF_SPIS_Type const * p_reg)846 NRF_STATIC_INLINE uint32_t nrf_spis_mosi_pin_get(NRF_SPIS_Type const * p_reg)
847 {
848 #if defined (NRF51)
849 return p_reg->PSELMOSI;
850 #else
851 return p_reg->PSEL.MOSI;
852 #endif
853 }
854
nrf_spis_miso_pin_get(NRF_SPIS_Type const * p_reg)855 NRF_STATIC_INLINE uint32_t nrf_spis_miso_pin_get(NRF_SPIS_Type const * p_reg)
856 {
857 #if defined (NRF51)
858 return p_reg->PSELMISO;
859 #else
860 return p_reg->PSEL.MISO;
861 #endif
862 }
863
nrf_spis_csn_pin_get(NRF_SPIS_Type const * p_reg)864 NRF_STATIC_INLINE uint32_t nrf_spis_csn_pin_get(NRF_SPIS_Type const * p_reg)
865 {
866 #if defined (NRF51)
867 return p_reg->PSELCSN;
868 #else
869 return p_reg->PSEL.CSN;
870 #endif
871 }
872
nrf_spis_tx_buffer_set(NRF_SPIS_Type * p_reg,uint8_t const * p_buffer,size_t length)873 NRF_STATIC_INLINE void nrf_spis_tx_buffer_set(NRF_SPIS_Type * p_reg,
874 uint8_t const * p_buffer,
875 size_t length)
876 {
877 #if defined (NRF51)
878 p_reg->TXDPTR = (uint32_t)p_buffer;
879 p_reg->MAXTX = length;
880 #elif NRF_SPIS_HAS_DMA_REG
881 p_reg->DMA.TX.PTR = (uint32_t)p_buffer;
882 p_reg->DMA.TX.MAXCNT = length;
883 #else
884 p_reg->TXD.PTR = (uint32_t)p_buffer;
885 p_reg->TXD.MAXCNT = length;
886 #endif
887 }
888
nrf_spis_rx_buffer_set(NRF_SPIS_Type * p_reg,uint8_t * p_buffer,size_t length)889 NRF_STATIC_INLINE void nrf_spis_rx_buffer_set(NRF_SPIS_Type * p_reg,
890 uint8_t * p_buffer,
891 size_t length)
892 {
893 #if defined (NRF51)
894 p_reg->RXDPTR = (uint32_t)p_buffer;
895 p_reg->MAXRX = length;
896 #elif NRF_SPIS_HAS_DMA_REG
897 p_reg->DMA.RX.PTR = (uint32_t)p_buffer;
898 p_reg->DMA.RX.MAXCNT = length;
899 #else
900 p_reg->RXD.PTR = (uint32_t)p_buffer;
901 p_reg->RXD.MAXCNT = length;
902 #endif
903 }
904
nrf_spis_tx_amount_get(NRF_SPIS_Type const * p_reg)905 NRF_STATIC_INLINE size_t nrf_spis_tx_amount_get(NRF_SPIS_Type const * p_reg)
906 {
907 #if defined (NRF51)
908 return p_reg->AMOUNTTX;
909 #elif NRF_SPIS_HAS_DMA_REG
910 return p_reg->DMA.TX.AMOUNT;
911 #else
912 return p_reg->TXD.AMOUNT;
913 #endif
914 }
915
nrf_spis_rx_amount_get(NRF_SPIS_Type const * p_reg)916 NRF_STATIC_INLINE size_t nrf_spis_rx_amount_get(NRF_SPIS_Type const * p_reg)
917 {
918 #if defined (NRF51)
919 return p_reg->AMOUNTRX;
920 #elif NRF_SPIS_HAS_DMA_REG
921 return p_reg->DMA.RX.AMOUNT;
922 #else
923 return p_reg->RXD.AMOUNT;
924 #endif
925 }
926
nrf_spis_configure(NRF_SPIS_Type * p_reg,nrf_spis_mode_t spi_mode,nrf_spis_bit_order_t spi_bit_order)927 NRF_STATIC_INLINE void nrf_spis_configure(NRF_SPIS_Type * p_reg,
928 nrf_spis_mode_t spi_mode,
929 nrf_spis_bit_order_t spi_bit_order)
930 {
931 uint32_t config = (spi_bit_order == NRF_SPIS_BIT_ORDER_MSB_FIRST ?
932 SPIS_CONFIG_ORDER_MsbFirst : SPIS_CONFIG_ORDER_LsbFirst);
933
934 switch (spi_mode)
935 {
936 default:
937 case NRF_SPIS_MODE_0:
938 config |= (SPIS_CONFIG_CPOL_ActiveHigh << SPIS_CONFIG_CPOL_Pos) |
939 (SPIS_CONFIG_CPHA_Leading << SPIS_CONFIG_CPHA_Pos);
940 break;
941
942 case NRF_SPIS_MODE_1:
943 config |= (SPIS_CONFIG_CPOL_ActiveHigh << SPIS_CONFIG_CPOL_Pos) |
944 (SPIS_CONFIG_CPHA_Trailing << SPIS_CONFIG_CPHA_Pos);
945 break;
946
947 case NRF_SPIS_MODE_2:
948 config |= (SPIS_CONFIG_CPOL_ActiveLow << SPIS_CONFIG_CPOL_Pos) |
949 (SPIS_CONFIG_CPHA_Leading << SPIS_CONFIG_CPHA_Pos);
950 break;
951
952 case NRF_SPIS_MODE_3:
953 config |= (SPIS_CONFIG_CPOL_ActiveLow << SPIS_CONFIG_CPOL_Pos) |
954 (SPIS_CONFIG_CPHA_Trailing << SPIS_CONFIG_CPHA_Pos);
955 break;
956 }
957 p_reg->CONFIG = config;
958 }
959
nrf_spis_orc_set(NRF_SPIS_Type * p_reg,uint8_t orc)960 NRF_STATIC_INLINE void nrf_spis_orc_set(NRF_SPIS_Type * p_reg,
961 uint8_t orc)
962 {
963 p_reg->ORC = orc;
964 }
965
nrf_spis_def_set(NRF_SPIS_Type * p_reg,uint8_t def)966 NRF_STATIC_INLINE void nrf_spis_def_set(NRF_SPIS_Type * p_reg,
967 uint8_t def)
968 {
969 p_reg->DEF = def;
970 }
971
972 #if defined(SPIS_TXD_LIST_LIST_Msk)
nrf_spis_tx_list_enable(NRF_SPIS_Type * p_reg)973 NRF_STATIC_INLINE void nrf_spis_tx_list_enable(NRF_SPIS_Type * p_reg)
974 {
975 p_reg->TXD.LIST = SPIS_TXD_LIST_LIST_ArrayList << SPIS_TXD_LIST_LIST_Pos;
976 }
977
nrf_spis_tx_list_disable(NRF_SPIS_Type * p_reg)978 NRF_STATIC_INLINE void nrf_spis_tx_list_disable(NRF_SPIS_Type * p_reg)
979 {
980 p_reg->TXD.LIST = SPIS_TXD_LIST_LIST_Disabled << SPIS_TXD_LIST_LIST_Pos;
981 }
982 #endif // defined(SPIS_TXD_LIST_LIST_Msk)
983
984 #if defined(SPIS_RXD_LIST_LIST_Msk)
nrf_spis_rx_list_enable(NRF_SPIS_Type * p_reg)985 NRF_STATIC_INLINE void nrf_spis_rx_list_enable(NRF_SPIS_Type * p_reg)
986 {
987 p_reg->RXD.LIST = SPIS_RXD_LIST_LIST_ArrayList << SPIS_RXD_LIST_LIST_Pos;
988 }
989
nrf_spis_rx_list_disable(NRF_SPIS_Type * p_reg)990 NRF_STATIC_INLINE void nrf_spis_rx_list_disable(NRF_SPIS_Type * p_reg)
991 {
992 p_reg->RXD.LIST = SPIS_RXD_LIST_LIST_Disabled << SPIS_RXD_LIST_LIST_Pos;
993 }
994 #endif // defined(SPIS_RXD_LIST_LIST_Msk)
995
996 #if NRF_SPIS_HAS_DMA_TASKS_EVENTS
nrf_spis_rx_pattern_match_enable_set(NRF_SPIS_Type * p_reg,uint8_t index,bool enable)997 NRF_STATIC_INLINE void nrf_spis_rx_pattern_match_enable_set(NRF_SPIS_Type * p_reg,
998 uint8_t index,
999 bool enable)
1000 {
1001 NRFX_ASSERT(index < NRF_SPIS_DMA_RX_PATTERN_MAX_COUNT);
1002 switch (index)
1003 {
1004 case 0:
1005 p_reg->DMA.RX.MATCH.CONFIG = ((p_reg->DMA.RX.MATCH.CONFIG &
1006 ~SPIS_DMA_RX_MATCH_CONFIG_ENABLE0_Msk) |
1007 ((enable ?
1008 SPIS_DMA_RX_MATCH_CONFIG_ENABLE0_Enabled :
1009 SPIS_DMA_RX_MATCH_CONFIG_ENABLE0_Disabled)
1010 << SPIS_DMA_RX_MATCH_CONFIG_ENABLE0_Pos));
1011 break;
1012 case 1:
1013 p_reg->DMA.RX.MATCH.CONFIG = ((p_reg->DMA.RX.MATCH.CONFIG &
1014 ~SPIS_DMA_RX_MATCH_CONFIG_ENABLE1_Msk) |
1015 ((enable ?
1016 SPIS_DMA_RX_MATCH_CONFIG_ENABLE1_Enabled :
1017 SPIS_DMA_RX_MATCH_CONFIG_ENABLE1_Disabled)
1018 << SPIS_DMA_RX_MATCH_CONFIG_ENABLE1_Pos));
1019 break;
1020 case 2:
1021 p_reg->DMA.RX.MATCH.CONFIG = ((p_reg->DMA.RX.MATCH.CONFIG &
1022 ~SPIS_DMA_RX_MATCH_CONFIG_ENABLE2_Msk) |
1023 ((enable ?
1024 SPIS_DMA_RX_MATCH_CONFIG_ENABLE2_Enabled :
1025 SPIS_DMA_RX_MATCH_CONFIG_ENABLE2_Disabled)
1026 << SPIS_DMA_RX_MATCH_CONFIG_ENABLE2_Pos));
1027 break;
1028 case 3:
1029 p_reg->DMA.RX.MATCH.CONFIG = ((p_reg->DMA.RX.MATCH.CONFIG &
1030 ~SPIS_DMA_RX_MATCH_CONFIG_ENABLE3_Msk) |
1031 ((enable ?
1032 SPIS_DMA_RX_MATCH_CONFIG_ENABLE3_Enabled :
1033 SPIS_DMA_RX_MATCH_CONFIG_ENABLE3_Disabled)
1034 << SPIS_DMA_RX_MATCH_CONFIG_ENABLE3_Pos));
1035 break;
1036 default:
1037 NRFX_ASSERT(false);
1038 break;
1039 }
1040 }
1041
nrf_spis_rx_pattern_match_enable_check(NRF_SPIS_Type const * p_reg,uint8_t index)1042 NRF_STATIC_INLINE bool nrf_spis_rx_pattern_match_enable_check(NRF_SPIS_Type const * p_reg,
1043 uint8_t index)
1044 {
1045 NRFX_ASSERT(index < NRF_SPIS_DMA_RX_PATTERN_MAX_COUNT);
1046 switch (index)
1047 {
1048 case 0:
1049 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIS_DMA_RX_MATCH_CONFIG_ENABLE0_Msk)
1050 >> SPIS_DMA_RX_MATCH_CONFIG_ENABLE0_Pos) ==
1051 SPIS_DMA_RX_MATCH_CONFIG_ENABLE0_Enabled;
1052 case 1:
1053 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIS_DMA_RX_MATCH_CONFIG_ENABLE1_Msk)
1054 >> SPIS_DMA_RX_MATCH_CONFIG_ENABLE1_Pos) ==
1055 SPIS_DMA_RX_MATCH_CONFIG_ENABLE1_Enabled;
1056 case 2:
1057 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIS_DMA_RX_MATCH_CONFIG_ENABLE2_Msk)
1058 >> SPIS_DMA_RX_MATCH_CONFIG_ENABLE2_Pos) ==
1059 SPIS_DMA_RX_MATCH_CONFIG_ENABLE2_Enabled;
1060 case 3:
1061 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIS_DMA_RX_MATCH_CONFIG_ENABLE3_Msk)
1062 >> SPIS_DMA_RX_MATCH_CONFIG_ENABLE3_Pos) ==
1063 SPIS_DMA_RX_MATCH_CONFIG_ENABLE3_Enabled;
1064 default:
1065 NRFX_ASSERT(false);
1066 return 0;
1067 }
1068 }
1069
nrf_spis_rx_pattern_match_one_shot_enable(NRF_SPIS_Type * p_reg,uint8_t index)1070 NRF_STATIC_INLINE void nrf_spis_rx_pattern_match_one_shot_enable(NRF_SPIS_Type * p_reg,
1071 uint8_t index)
1072 {
1073 NRFX_ASSERT(index < NRF_SPIS_DMA_RX_PATTERN_MAX_COUNT);
1074 switch (index)
1075 {
1076 case 0:
1077 p_reg->DMA.RX.MATCH.CONFIG |= SPIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Msk;
1078 break;
1079 case 1:
1080 p_reg->DMA.RX.MATCH.CONFIG |= SPIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Msk;
1081 break;
1082 case 2:
1083 p_reg->DMA.RX.MATCH.CONFIG |= SPIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Msk;
1084 break;
1085 case 3:
1086 p_reg->DMA.RX.MATCH.CONFIG |= SPIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Msk;
1087 break;
1088 default:
1089 NRFX_ASSERT(false);
1090 break;
1091 }
1092 }
1093
nrf_spis_rx_pattern_match_one_shot_disable(NRF_SPIS_Type * p_reg,uint8_t index)1094 NRF_STATIC_INLINE void nrf_spis_rx_pattern_match_one_shot_disable(NRF_SPIS_Type * p_reg,
1095 uint8_t index)
1096 {
1097 NRFX_ASSERT(index < NRF_SPIS_DMA_RX_PATTERN_MAX_COUNT);
1098 switch (index)
1099 {
1100 case 0:
1101 p_reg->DMA.RX.MATCH.CONFIG &= ~(SPIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Msk);
1102 break;
1103 case 1:
1104 p_reg->DMA.RX.MATCH.CONFIG &= ~(SPIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Msk);
1105 break;
1106 case 2:
1107 p_reg->DMA.RX.MATCH.CONFIG &= ~(SPIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Msk);
1108 break;
1109 case 3:
1110 p_reg->DMA.RX.MATCH.CONFIG &= ~(SPIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Msk);
1111 break;
1112 default:
1113 NRFX_ASSERT(false);
1114 break;
1115 }
1116 }
1117
nrf_spis_rx_pattern_match_one_shot_check(NRF_SPIS_Type const * p_reg,uint8_t index)1118 NRF_STATIC_INLINE bool nrf_spis_rx_pattern_match_one_shot_check(NRF_SPIS_Type const * p_reg,
1119 uint8_t index)
1120 {
1121 NRFX_ASSERT(index < NRF_SPIS_DMA_RX_PATTERN_MAX_COUNT);
1122 switch (index)
1123 {
1124 case 0:
1125 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Msk)
1126 >> SPIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Pos) ==
1127 SPIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Oneshot;
1128 case 1:
1129 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Msk)
1130 >> SPIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Pos) ==
1131 SPIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Oneshot;
1132 case 2:
1133 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Msk)
1134 >> SPIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Pos) ==
1135 SPIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Oneshot;
1136 case 3:
1137 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Msk)
1138 >> SPIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Pos) ==
1139 SPIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Oneshot;
1140 default:
1141 NRFX_ASSERT(false);
1142 return 0;
1143 }
1144 }
1145
nrf_spis_rx_pattern_match_candidate_set(NRF_SPIS_Type * p_reg,uint8_t index,uint32_t pattern)1146 NRF_STATIC_INLINE void nrf_spis_rx_pattern_match_candidate_set(NRF_SPIS_Type * p_reg,
1147 uint8_t index,
1148 uint32_t pattern)
1149 {
1150 NRFX_ASSERT(index < NRF_SPIS_DMA_RX_PATTERN_MAX_COUNT);
1151 p_reg->DMA.RX.MATCH.CANDIDATE[index] = pattern;
1152 }
1153
nrf_spis_rx_pattern_match_candidate_get(NRF_SPIS_Type const * p_reg,uint8_t index)1154 NRF_STATIC_INLINE uint32_t nrf_spis_rx_pattern_match_candidate_get(NRF_SPIS_Type const * p_reg,
1155 uint8_t index)
1156 {
1157 NRFX_ASSERT(index < NRF_SPIS_DMA_RX_PATTERN_MAX_COUNT);
1158 return p_reg->DMA.RX.MATCH.CANDIDATE[index];
1159 }
1160 #endif // NRF_SPIS_HAS_DMA_TASKS_EVENTS
1161
1162 #if NRF_SPIS_HAS_DMA_REG
nrf_spis_rx_terminate_on_bus_error_enable(NRF_SPIS_Type * p_reg)1163 NRF_STATIC_INLINE void nrf_spis_rx_terminate_on_bus_error_enable(NRF_SPIS_Type * p_reg)
1164 {
1165 p_reg->DMA.RX.TERMINATEONBUSERROR |= SPIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Msk;
1166 }
1167
nrf_spis_rx_terminate_on_bus_error_disable(NRF_SPIS_Type * p_reg)1168 NRF_STATIC_INLINE void nrf_spis_rx_terminate_on_bus_error_disable(NRF_SPIS_Type * p_reg)
1169 {
1170 p_reg->DMA.RX.TERMINATEONBUSERROR &= ~(SPIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Msk);
1171 }
1172
nrf_spis_rx_terminate_on_bus_error_check(NRF_SPIS_Type const * p_reg)1173 NRF_STATIC_INLINE bool nrf_spis_rx_terminate_on_bus_error_check(NRF_SPIS_Type const * p_reg)
1174 {
1175 return ((p_reg->DMA.RX.TERMINATEONBUSERROR & SPIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Msk)
1176 >> SPIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos) ==
1177 SPIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Enabled;
1178 }
1179
nrf_spis_tx_terminate_on_bus_error_enable(NRF_SPIS_Type * p_reg)1180 NRF_STATIC_INLINE void nrf_spis_tx_terminate_on_bus_error_enable(NRF_SPIS_Type * p_reg)
1181 {
1182 p_reg->DMA.TX.TERMINATEONBUSERROR |= SPIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Msk;
1183 }
1184
nrf_spis_tx_terminate_on_bus_error_disable(NRF_SPIS_Type * p_reg)1185 NRF_STATIC_INLINE void nrf_spis_tx_terminate_on_bus_error_disable(NRF_SPIS_Type * p_reg)
1186 {
1187 p_reg->DMA.TX.TERMINATEONBUSERROR &= ~(SPIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Msk);
1188 }
1189
nrf_spis_tx_terminate_on_bus_error_check(NRF_SPIS_Type const * p_reg)1190 NRF_STATIC_INLINE bool nrf_spis_tx_terminate_on_bus_error_check(NRF_SPIS_Type const * p_reg)
1191 {
1192 return ((p_reg->DMA.TX.TERMINATEONBUSERROR & SPIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Msk)
1193 >> SPIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos) ==
1194 SPIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Enabled;
1195 }
1196 #endif // NRF_SPIS_HAS_DMA_REG
1197
1198 #endif // NRF_DECLARE_ONLY
1199
1200 /** @} */
1201
1202 #ifdef __cplusplus
1203 }
1204 #endif
1205
1206 #endif // NRF_SPIS_H__
1207
