1 /*
2 * Copyright (c) 2015 - 2024, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_SPIM_H__
35 #define NRF_SPIM_H__
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 #if defined(NRF54H20_XXAA)
44 #define NRF_SPIM_CLOCKPIN_MOSI_NEEDED 1
45 #endif
46
47 #if defined(HALTIUM_XXAA)
48 #define NRF_SPIM_CLOCKPIN_SCK_NEEDED 1
49 #endif
50
51 /*
52 * Macro for generating code blocks that allow extracting
53 * the maximum prescaler value allowed for the specified SPIM instance.
54 */
55 #define _NRF_SPIM_PRESCALER_MAX_GET(periph_name, prefix, idx, p_reg) \
56 (p_reg == NRFX_CONCAT(NRF_, periph_name, prefix, idx)) ? \
57 (NRFX_CONCAT(periph_name, prefix, idx, _PRESCALER_DIVISOR_RANGE_MAX)) :
58
59 /*
60 * Macro for generating code blocks that allow extracting
61 * the minimum prescaler value allowed for the specified SPIM instance.
62 */
63 #define _NRF_SPIM_PRESCALER_MIN_GET(periph_name, prefix, idx, p_reg) \
64 (p_reg == NRFX_CONCAT(NRF_, periph_name, prefix, idx)) ? \
65 (NRFX_CONCAT(periph_name, prefix, idx, _PRESCALER_DIVISOR_RANGE_MIN)) :
66
67 /**
68 * @defgroup nrf_spim_hal SPIM HAL
69 * @{
70 * @ingroup nrf_spim
71 * @brief Hardware access layer for managing the SPIM peripheral.
72 */
73
74 /**
75 * @brief Macro getting pointer to the structure of registers of the SPIM peripheral.
76 *
77 * @param[in] idx SPIM instance index.
78 *
79 * @return Pointer to the structure of registers of the SPIM peripheral.
80 */
81 #define NRF_SPIM_INST_GET(idx) NRFX_CONCAT(NRF_, SPIM, idx)
82
83 #if defined(SPIM_FREQUENCY_FREQUENCY_M16) || defined(__NRFX_DOXYGEN__)
84 /** @brief Symbol indicating whether 16 MHz clock frequency is available. */
85 #define NRF_SPIM_HAS_16_MHZ_FREQ 1
86 #else
87 #define NRF_SPIM_HAS_16_MHZ_FREQ 0
88 #endif
89
90 #if defined(SPIM_FREQUENCY_FREQUENCY_M32) || defined(__NRFX_DOXYGEN__)
91 /** @brief Symbol indicating whether 32 MHz clock frequency is available. */
92 #define NRF_SPIM_HAS_32_MHZ_FREQ 1
93 #else
94 #define NRF_SPIM_HAS_32_MHZ_FREQ 0
95 #endif
96
97 #if defined(SPIM_FREQUENCY_FREQUENCY_Msk) || defined(__NRFX_DOXYGEN__)
98 /** @brief Symbol indicating whether frequency is used. */
99 #define NRF_SPIM_HAS_FREQUENCY 1
100 #else
101 #define NRF_SPIM_HAS_FREQUENCY 0
102 #endif
103
104 #if defined(SPIM_PRESCALER_DIVISOR_Msk) || defined(__NRFX_DOXYGEN__)
105 /** @brief Symbol indicating whether prescaler is used. */
106 #define NRF_SPIM_HAS_PRESCALER 1
107 #else
108 #define NRF_SPIM_HAS_PRESCALER 0
109 #endif
110
111 #if defined(SPIM_TXD_LIST_LIST_ArrayList) || defined(__NRFX_DOXYGEN__)
112 /** @brief Symbol indicating whether EasyDMA array list feature is present. */
113 #define NRF_SPIM_HAS_ARRAY_LIST 1
114 #else
115 #define NRF_SPIM_HAS_ARRAY_LIST 0
116 #endif
117
118 #if defined(SPIM_DMA_RX_PTR_PTR_Msk) || defined(__NRFX_DOXYGEN__)
119 /** @brief Symbol indicating whether dedicated DMA register is present. */
120 #define NRF_SPIM_HAS_DMA_REG 1
121 #else
122 #define NRF_SPIM_HAS_DMA_REG 0
123 #endif
124
125 #if (defined(SPIM_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Msk) && \
126 defined(SPIM_EVENTS_DMA_RX_END_END_Msk)) || \
127 defined(__NRFX_DOXYGEN__)
128 /** @brief Symbol indicating whether SPIM DMA tasks and events are present. */
129 #define NRF_SPIM_HAS_DMA_TASKS_EVENTS 1
130 #else
131 #define NRF_SPIM_HAS_DMA_TASKS_EVENTS 0
132 #endif
133
134 /** @brief Macro for checking if the hardware chip select function is available. */
135 #if NRFX_FEATURE_PRESENT(SPIM, _FEATURE_HARDWARE_CSN_PRESENT) || defined(__NRFX_DOXYGEN__)
136 #define NRF_SPIM_HAS_HW_CSN 1
137 #else
138 #define NRF_SPIM_HAS_HW_CSN 0
139 #endif
140
141 /** @brief Macro for checking if the DCX pin control is available. */
142 #if NRFX_FEATURE_PRESENT(SPIM, _FEATURE_HARDWARE_DCX_PRESENT) || \
143 NRFX_FEATURE_PRESENT(SPIM, _FEATURE_DCX_PRESENT) || \
144 defined(__NRFX_DOXYGEN__)
145 #define NRF_SPIM_HAS_DCX 1
146 #else
147 #define NRF_SPIM_HAS_DCX 0
148 #endif
149
150 /** @brief Macro for checking if the RXDELAY function is available. */
151 #if NRFX_FEATURE_PRESENT(SPIM, _FEATURE_RXDELAY_PRESENT) || defined(__NRFX_DOXYGEN__)
152 #define NRF_SPIM_HAS_RXDELAY 1
153 #else
154 #define NRF_SPIM_HAS_RXDELAY 0
155 #endif
156
157 #if defined(SPIM_STALLSTAT_RX_Msk) || defined(__NRFX_DOXYGEN__)
158 /** @brief Macro for checking if the STALLSTAT feature is available. */
159 #define NRF_SPIM_HAS_STALLSTAT 1
160 #else
161 #define NRF_SPIM_HAS_STALLSTAT 0
162 #endif
163
164 #if NRF_SPIM_HAS_HW_CSN || NRF_SPIM_HAS_DCX || NRF_SPIM_HAS_RXDELAY
165 /** @brief Symbol indicating whether any of the SPIM extended features is available. */
166 #define NRF_SPIM_HAS_EXTENDED 1
167 #else
168 #define NRF_SPIM_HAS_EXTENDED 0
169 #endif
170
171 #if NRF_SPIM_HAS_DCX
172 /**
173 * @brief This value specified in the DCX line configuration causes this line
174 * to be set low during whole transmission (all transmitted bytes are
175 * marked as command bytes). Any lower value causes the DCX line to be
176 * switched from low to high after this number of bytes is transmitted
177 * (all remaining bytes are marked as data bytes).
178 */
179 #define NRF_SPIM_DCX_CNT_ALL_CMD 0xF
180 #endif
181
182 /**
183 * @brief This value can be used as a parameter for the @ref nrf_spim_pins_set
184 * function to specify that a given SPI signal (SCK, MOSI, or MISO)
185 * shall not be connected to a physical pin.
186 */
187 #define NRF_SPIM_PIN_NOT_CONNECTED 0xFFFFFFFF
188
189 #if NRF_SPIM_HAS_DMA_TASKS_EVENTS
190 /** @brief Max number of RX patterns. */
191 #define NRF_SPIM_DMA_RX_PATTERN_MAX_COUNT SPIM_DMA_RX_MATCH_CANDIDATE_MaxCount
192 #endif
193
194 #if NRF_SPIM_HAS_DCX
195 #if defined(SPIM_PSEL_DCX_ResetValue) || defined(__NRFX_DOXYGEN__)
196 /** @brief Symbol specifying default value of DCX pin setting. */
197 #define NRF_SPIM_DCX_DEFAULT SPIM_PSEL_DCX_ResetValue
198 #else
199 #define NRF_SPIM_DCX_DEFAULT 0xFFFFFFFFUL
200 #endif
201 #endif // NRF_SPIM_HAS_DCX
202
203 #if NRF_SPIM_HAS_HW_CSN
204 #if defined(SPIM_PSEL_CSN_ResetValue) || defined(__NRFX_DOXYGEN__)
205 /** @brief Symbol specifying default value of CSN pin setting. */
206 #define NRF_SPIM_CSN_DEFAULT SPIM_PSEL_CSN_ResetValue
207 #else
208 #define NRF_SPIM_CSN_DEFAULT 0xFFFFFFFFUL
209 #endif
210
211 #if defined(SPIM_CSNDUR_ResetValue) || defined(__NRFX_DOXYGEN__)
212 /** @brief Symbol specifying default value of CSN duration setting. */
213 #define NRF_SPIM_CSNDUR_DEFAULT SPIM_CSNDUR_ResetValue
214 #else
215 #define NRF_SPIM_CSNDUR_DEFAULT 0x2UL
216 #endif
217
218 #if defined(SPIM_CSNPOL_ResetValue) || defined(__NRFX_DOXYGEN__)
219 /** @brief Symbol specifying default value of CSN polarity setting. */
220 #define NRF_SPIM_CSNPOL_DEFAULT SPIM_CSNPOL_ResetValue
221 #else
222 #define NRF_SPIM_CSNPOL_DEFAULT 0x0UL
223 #endif
224 #endif // NRF_SPIM_HAS_HW_CSN
225
226 #if NRF_SPIM_HAS_RXDELAY
227 #if defined(SPIM_IFTIMING_RXDELAY_ResetValue) || defined(__NRFX_DOXYGEN__)
228 /** @brief Symbol specifying default value of RX delay setting. */
229 #define NRF_SPIM_RXDELAY_DEFAULT SPIM_IFTIMING_RXDELAY_ResetValue
230 #else
231 #define NRF_SPIM_RXDELAY_DEFAULT 0x2UL
232 #endif
233 #endif // NRF_SPIM_HAS_RXDELAY
234
235 /** @brief Minimal SPIM frequency in Hz. */
236 #define NRF_SPIM_MIN_FREQUENCY (NRFX_KHZ_TO_HZ(125UL))
237
238 /** @brief Base frequency value 320 MHz for SPIM. */
239 #define NRF_SPIM_BASE_FREQUENCY_320MHZ (NRFX_MHZ_TO_HZ(320UL))
240
241 /** @brief Base frequency value 192 MHz for SPIM. */
242 #define NRF_SPIM_BASE_FREQUENCY_192MHZ (NRFX_MHZ_TO_HZ(192UL))
243
244 /** @brief Base frequency value 128 MHz for SPIM. */
245 #define NRF_SPIM_BASE_FREQUENCY_128MHZ (NRFX_MHZ_TO_HZ(128UL))
246
247 /** @brief Base frequency value 64 MHz for SPIM. */
248 #define NRF_SPIM_BASE_FREQUENCY_64MHZ (NRFX_MHZ_TO_HZ(64UL))
249
250 /** @brief Base frequency value 32 MHz for SPIM. */
251 #define NRF_SPIM_BASE_FREQUENCY_32MHZ (NRFX_MHZ_TO_HZ(32UL))
252
253 /** @brief Base frequency value 16 MHz for SPIM. */
254 #define NRF_SPIM_BASE_FREQUENCY_16MHZ (NRFX_MHZ_TO_HZ(16UL))
255
256 #if !defined(NRF_SPIM_IS_320MHZ_SPIM)
257 /** @brief Macro for checking whether the base frequency for the specified SPIM instance is 320 MHz. */
258 #define NRF_SPIM_IS_320MHZ_SPIM(p_reg) \
259 (NRFX_COND_CODE_1(NRFX_INSTANCE_PRESENT(SPIM120), (p_reg == NRF_SPIM120), (false)) || \
260 NRFX_COND_CODE_1(NRFX_INSTANCE_PRESENT(SPIM121), (p_reg == NRF_SPIM121), (false)))
261 #endif
262
263 #if !defined(NRF_SPIM_IS_192MHZ_SPIM)
264 /** @brief Macro for checking whether the base frequency for the specified SPIM instance is 192 MHz. */
265 #define NRF_SPIM_IS_192MHZ_SPIM(p_reg) false
266 #endif
267
268 #if !defined(NRF_SPIM_IS_128MHZ_SPIM)
269 /** @brief Macro for checking whether the base frequency for the specified SPIM instance is 128 MHz. */
270 #define NRF_SPIM_IS_128MHZ_SPIM(p_reg) \
271 (NRFX_COND_CODE_1(NRFX_IS_ENABLED(NRF_CPU_FREQ_IS_128MHZ), \
272 (NRFX_COND_CODE_1(NRFX_INSTANCE_PRESENT(SPIM00), (p_reg == NRF_SPIM00), (false))), \
273 (false)))
274 #endif
275
276 #if !defined(NRF_SPIM_IS_64MHZ_SPIM)
277 /** @brief Macro for checking whether the base frequency for the specified SPIM instance is 64 MHz. */
278 #define NRF_SPIM_IS_64MHZ_SPIM(p_reg) \
279 (NRFX_COND_CODE_1(NRFX_IS_ENABLED(NRF_CPU_FREQ_IS_64MHZ), \
280 (NRFX_COND_CODE_1(NRFX_INSTANCE_PRESENT(SPIM00), (p_reg == NRF_SPIM00), (false))), \
281 (false)))
282 #endif
283
284 #if !defined(NRF_SPIM_IS_32MHZ_SPIM)
285 /** @brief Macro for checking whether the base frequency for the specified SPIM instance is 32 MHz. */
286 #define NRF_SPIM_IS_32MHZ_SPIM(p_reg) false
287 #endif
288
289 /** @brief Macro for getting base frequency value in Hz for the specified SPIM instance. */
290 #define NRF_SPIM_BASE_FREQUENCY_GET(p_reg) \
291 ((NRF_SPIM_IS_320MHZ_SPIM(p_reg)) ? (NRF_SPIM_BASE_FREQUENCY_320MHZ) : \
292 ((NRF_SPIM_IS_192MHZ_SPIM(p_reg)) ? (NRF_SPIM_BASE_FREQUENCY_192MHZ) : \
293 ((NRF_SPIM_IS_128MHZ_SPIM(p_reg)) ? (NRF_SPIM_BASE_FREQUENCY_128MHZ) : \
294 ((NRF_SPIM_IS_64MHZ_SPIM(p_reg)) ? (NRF_SPIM_BASE_FREQUENCY_64MHZ) : \
295 ((NRF_SPIM_IS_32MHZ_SPIM(p_reg)) ? (NRF_SPIM_BASE_FREQUENCY_32MHZ) : \
296 (NRF_SPIM_BASE_FREQUENCY_16MHZ))))))
297
298 #if NRF_SPIM_HAS_PRESCALER
299 /**
300 * @brief Macro for getting the maximum value of PRESCALER register.
301 *
302 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
303 */
304 #define NRF_SPIM_PRESCALER_MAX_GET(p_reg) \
305 (NRFX_FOREACH_ENABLED(SPIM, _NRF_SPIM_PRESCALER_MAX_GET, (), (), p_reg) \
306 SPIM_PRESCALER_DIVISOR_Max)
307
308 /**
309 * @brief Macro for getting the minimum value of PRESCALER register.
310 *
311 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
312 */
313 #define NRF_SPIM_PRESCALER_MIN_GET(p_reg) \
314 (NRFX_FOREACH_ENABLED(SPIM, _NRF_SPIM_PRESCALER_MIN_GET, (), (), p_reg) \
315 SPIM_PRESCALER_DIVISOR_Min)
316
317 /**
318 * @brief Macro for computing prescaler value for a given SPIM instance and desired frequency.
319 *
320 * @warning Not every combination of base and desired frequency is supported.
321 * The @ref NRF_SPIM_FREQUENCY_STATIC_CHECK macro can be used to check if the desired frequency is supported.
322 *
323 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
324 * @param[in] frequency Desired frequency value in Hz.
325 */
326 #define NRF_SPIM_PRESCALER_CALCULATE(p_reg, frequency) \
327 ((uint32_t)(NRF_SPIM_BASE_FREQUENCY_GET(p_reg)) / (uint32_t)(frequency))
328 #endif
329
330 /**
331 * @brief Macro for checking whether specified frequency can be achieved for a given SPIM instance.
332 *
333 * @note This macro uses a compile-time assertion.
334 *
335 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
336 * @param[in] frequency Desired frequency value in Hz.
337 */
338 #define NRF_SPIM_FREQUENCY_STATIC_CHECK(p_reg, frequency) \
339 NRFX_STATIC_ASSERT( \
340 NRFX_COND_CODE_1(NRF_SPIM_HAS_PRESCALER, \
341 ((NRF_SPIM_BASE_FREQUENCY_GET(p_reg) % (uint32_t)frequency == 0) && \
342 (NRFX_IS_EVEN(NRF_SPIM_PRESCALER_CALCULATE(p_reg, (uint32_t)frequency))) && \
343 (NRF_SPIM_PRESCALER_CALCULATE(p_reg, (uint32_t)frequency) >= (NRF_SPIM_PRESCALER_MIN_GET(p_reg))) && \
344 (NRF_SPIM_PRESCALER_CALCULATE(p_reg, (uint32_t)frequency) <= (NRF_SPIM_PRESCALER_MAX_GET(p_reg)))) \
345 , \
346 (((uint32_t)frequency == (uint32_t)NRFX_KHZ_TO_HZ(125)) || \
347 ((uint32_t)frequency == (uint32_t)NRFX_KHZ_TO_HZ(250)) || \
348 ((uint32_t)frequency == (uint32_t)NRFX_KHZ_TO_HZ(500)) || \
349 ((uint32_t)frequency == (uint32_t)NRFX_MHZ_TO_HZ(1)) || \
350 ((uint32_t)frequency == (uint32_t)NRFX_MHZ_TO_HZ(2)) || \
351 ((uint32_t)frequency == (uint32_t)NRFX_MHZ_TO_HZ(4)) || \
352 ((uint32_t)frequency == (uint32_t)NRFX_MHZ_TO_HZ(8)) || \
353 (((uint32_t)frequency == (uint32_t)NRFX_MHZ_TO_HZ(16)) && (NRF_SPIM_HAS_16_MHZ_FREQ)) || \
354 (((uint32_t)frequency == (uint32_t)NRFX_MHZ_TO_HZ(32)) && (NRF_SPIM_HAS_32_MHZ_FREQ)))))
355
356 /** @brief SPIM tasks. */
357 typedef enum
358 {
359 NRF_SPIM_TASK_START = offsetof(NRF_SPIM_Type, TASKS_START), ///< Start SPI transaction.
360 NRF_SPIM_TASK_STOP = offsetof(NRF_SPIM_Type, TASKS_STOP), ///< Stop SPI transaction.
361 NRF_SPIM_TASK_SUSPEND = offsetof(NRF_SPIM_Type, TASKS_SUSPEND), ///< Suspend SPI transaction.
362 NRF_SPIM_TASK_RESUME = offsetof(NRF_SPIM_Type, TASKS_RESUME), ///< Resume SPI transaction.
363 #if NRF_SPIM_HAS_DMA_TASKS_EVENTS
364 NRF_SPIM_TASK_ENABLERXMATCH0 = offsetof(NRF_SPIM_Type, TASKS_DMA.RX.ENABLEMATCH[0]), ///< Enable SPI pattern matching functionality for pattern 0.
365 NRF_SPIM_TASK_ENABLERXMATCH1 = offsetof(NRF_SPIM_Type, TASKS_DMA.RX.ENABLEMATCH[1]), ///< Enable SPI pattern matching functionality for pattern 1.
366 NRF_SPIM_TASK_ENABLERXMATCH2 = offsetof(NRF_SPIM_Type, TASKS_DMA.RX.ENABLEMATCH[2]), ///< Enable SPI pattern matching functionality for pattern 2.
367 NRF_SPIM_TASK_ENABLERXMATCH3 = offsetof(NRF_SPIM_Type, TASKS_DMA.RX.ENABLEMATCH[3]), ///< Enable SPI pattern matching functionality for pattern 3.
368 NRF_SPIM_TASK_DISABLERXMATCH0 = offsetof(NRF_SPIM_Type, TASKS_DMA.RX.DISABLEMATCH[0]), ///< Disable SPI pattern matching functionality for pattern 0.
369 NRF_SPIM_TASK_DISABLERXMATCH1 = offsetof(NRF_SPIM_Type, TASKS_DMA.RX.DISABLEMATCH[1]), ///< Disable SPI pattern matching functionality for pattern 1.
370 NRF_SPIM_TASK_DISABLERXMATCH2 = offsetof(NRF_SPIM_Type, TASKS_DMA.RX.DISABLEMATCH[2]), ///< Disable SPI pattern matching functionality for pattern 2.
371 NRF_SPIM_TASK_DISABLERXMATCH3 = offsetof(NRF_SPIM_Type, TASKS_DMA.RX.DISABLEMATCH[3]) ///< Disable SPI pattern matching functionality for pattern 3.
372 #endif
373 } nrf_spim_task_t;
374
375 /** @brief SPIM events. */
376 typedef enum
377 {
378 NRF_SPIM_EVENT_STARTED = offsetof(NRF_SPIM_Type, EVENTS_STARTED), ///< SPI transaction has started.
379 NRF_SPIM_EVENT_STOPPED = offsetof(NRF_SPIM_Type, EVENTS_STOPPED), ///< SPI transaction has stopped.
380 #if NRF_SPIM_HAS_DMA_TASKS_EVENTS
381 NRF_SPIM_EVENT_RXSTARTED = offsetof(NRF_SPIM_Type, EVENTS_DMA.RX.READY), ///< Receive sequence started.
382 NRF_SPIM_EVENT_RXBUSERROR = offsetof(NRF_SPIM_Type, EVENTS_DMA.RX.BUSERROR), ///< Memory bus error occurred during the RX transfer.
383 NRF_SPIM_EVENT_RXMATCH0 = offsetof(NRF_SPIM_Type, EVENTS_DMA.RX.MATCH[0]), ///< Pattern match for pattern 0 detected.
384 NRF_SPIM_EVENT_RXMATCH1 = offsetof(NRF_SPIM_Type, EVENTS_DMA.RX.MATCH[1]), ///< Pattern match for pattern 1 detected.
385 NRF_SPIM_EVENT_RXMATCH2 = offsetof(NRF_SPIM_Type, EVENTS_DMA.RX.MATCH[2]), ///< Pattern match for pattern 2 detected.
386 NRF_SPIM_EVENT_RXMATCH3 = offsetof(NRF_SPIM_Type, EVENTS_DMA.RX.MATCH[3]), ///< Pattern match for pattern 3 detected.
387 NRF_SPIM_EVENT_TXSTARTED = offsetof(NRF_SPIM_Type, EVENTS_DMA.TX.READY), ///< Transmit sequence started.
388 NRF_SPIM_EVENT_TXBUSERROR = offsetof(NRF_SPIM_Type, EVENTS_DMA.TX.BUSERROR), ///< Memory bus error occurred during the TX transfer.
389 NRF_SPIM_EVENT_ENDRX = offsetof(NRF_SPIM_Type, EVENTS_DMA.RX.END), ///< End of RXD buffer reached.
390 NRF_SPIM_EVENT_ENDTX = offsetof(NRF_SPIM_Type, EVENTS_DMA.TX.END), ///< End of TXD buffer reached.
391 #else
392 NRF_SPIM_EVENT_ENDRX = offsetof(NRF_SPIM_Type, EVENTS_ENDRX), ///< End of RXD buffer reached.
393 NRF_SPIM_EVENT_ENDTX = offsetof(NRF_SPIM_Type, EVENTS_ENDTX), ///< End of TXD buffer reached.
394 #endif
395 NRF_SPIM_EVENT_END = offsetof(NRF_SPIM_Type, EVENTS_END) ///< End of RXD buffer and TXD buffer reached.
396 } nrf_spim_event_t;
397
398 /** @brief SPIM shortcuts. */
399 typedef enum
400 {
401 NRF_SPIM_SHORT_END_START_MASK = SPIM_SHORTS_END_START_Msk, ///< Shortcut between END event and START task.
402 #if NRF_SPIM_HAS_DMA_TASKS_EVENTS
403 NRF_SPIM_SHORT_RXMATCH0_ENABLERXMATCH1_MASK = SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Msk, ///< Shortcut between DMA.RX.MATCH0 event and DMA.RX.ENABLEMATCH1 task.
404 NRF_SPIM_SHORT_RXMATCH1_ENABLERXMATCH2_MASK = SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Msk, ///< Shortcut between DMA.RX.MATCH1 event and DMA.RX.ENABLEMATCH2 task.
405 NRF_SPIM_SHORT_RXMATCH2_ENABLERXMATCH3_MASK = SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Msk, ///< Shortcut between DMA.RX.MATCH2 event and DMA.RX.ENABLEMATCH3 task.
406 NRF_SPIM_SHORT_RXMATCH3_ENABLERXMATCH0_MASK = SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Msk, ///< Shortcut between DMA.RX.MATCH3 event and DMA.RX.ENABLEMATCH4 task.
407 NRF_SPIM_SHORT_RXMATCH0_DISABLERXMATCH0_MASK = SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Msk, ///< Shortcut between DMA.RX.MATCH0 event and DMA.RX.DISABLEMATCH0 task.
408 NRF_SPIM_SHORT_RXMATCH1_DISABLERXMATCH1_MASK = SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Msk, ///< Shortcut between DMA.RX.MATCH1 event and DMA.RX.DISABLEMATCH1 task.
409 NRF_SPIM_SHORT_RXMATCH2_DISABLERXMATCH2_MASK = SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Msk, ///< Shortcut between DMA.RX.MATCH2 event and DMA.RX.DISABLEMATCH2 task.
410 NRF_SPIM_SHORT_RXMATCH3_DISABLERXMATCH3_MASK = SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Msk, ///< Shortcut between DMA.RX.MATCH3 event and DMA.RX.DISABLEMATCH3 task.
411 #endif
412 NRF_SPIM_ALL_SHORTS_MASK = SPIM_SHORTS_END_START_Msk
413 #if NRF_SPIM_HAS_DMA_TASKS_EVENTS
414 | SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Msk
415 | SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Msk
416 | SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Msk
417 | SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Msk
418 | SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Msk
419 | SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Msk
420 | SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Msk
421 | SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Msk ///< All SPIM shortcuts.
422 #endif
423 } nrf_spim_short_mask_t;
424
425 /** @brief SPIM interrupts. */
426 typedef enum
427 {
428 NRF_SPIM_INT_STARTED_MASK = SPIM_INTENSET_STARTED_Msk, ///< Interrupt on STARTED event.
429 NRF_SPIM_INT_STOPPED_MASK = SPIM_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event.
430 #if NRF_SPIM_HAS_DMA_TASKS_EVENTS
431 NRF_SPIM_INT_RXREADY_MASK = SPIM_INTENSET_DMARXREADY_Msk, ///< Interrupt on DMA.RX.READY event.
432 NRF_SPIM_INT_RXBUSERROR_MASK = SPIM_INTENSET_DMARXBUSERROR_Msk, ///< Interrupt on DMA.RX.BUSERROR event.
433 NRF_SPIM_INT_RXMATCH0_MASK = SPIM_INTENSET_DMARXMATCH0_Msk, ///< Interrupt on DMA.RX.MATCH0 event.
434 NRF_SPIM_INT_RXMATCH1_MASK = SPIM_INTENSET_DMARXMATCH1_Msk, ///< Interrupt on DMA.RX.MATCH1 event.
435 NRF_SPIM_INT_RXMATCH2_MASK = SPIM_INTENSET_DMARXMATCH2_Msk, ///< Interrupt on DMA.RX.MATCH2 event.
436 NRF_SPIM_INT_RXMATCH3_MASK = SPIM_INTENSET_DMARXMATCH3_Msk, ///< Interrupt on DMA.RX.MATCH3 event.
437 NRF_SPIM_INT_TXREADY_MASK = SPIM_INTENSET_DMATXREADY_Msk, ///< Interrupt on DMA.TX.READY event.
438 NRF_SPIM_INT_TXBUSERROR_MASK = SPIM_INTENSET_DMATXBUSERROR_Msk, ///< Interrupt on DMA.TX.BUSERROR event.
439 NRF_SPIM_INT_ENDRX_MASK = SPIM_INTENSET_DMARXEND_Msk, ///< Interrupt on ENDRX event.
440 NRF_SPIM_INT_ENDTX_MASK = SPIM_INTENSET_DMATXEND_Msk, ///< Interrupt on ENDTX event.
441 #else
442 NRF_SPIM_INT_ENDRX_MASK = SPIM_INTENSET_ENDRX_Msk, ///< Interrupt on ENDRX event.
443 NRF_SPIM_INT_ENDTX_MASK = SPIM_INTENSET_ENDTX_Msk, ///< Interrupt on ENDTX event.
444 #endif
445 NRF_SPIM_INT_END_MASK = SPIM_INTENSET_END_Msk, ///< Interrupt on END event.
446 NRF_SPIM_ALL_INTS_MASK = NRF_SPIM_INT_STARTED_MASK
447 | NRF_SPIM_INT_STOPPED_MASK
448 #if NRF_SPIM_HAS_DMA_TASKS_EVENTS
449 | NRF_SPIM_INT_RXREADY_MASK
450 | NRF_SPIM_INT_RXBUSERROR_MASK
451 | NRF_SPIM_INT_RXMATCH0_MASK
452 | NRF_SPIM_INT_RXMATCH1_MASK
453 | NRF_SPIM_INT_RXMATCH2_MASK
454 | NRF_SPIM_INT_RXMATCH3_MASK
455 | NRF_SPIM_INT_TXREADY_MASK
456 | NRF_SPIM_INT_TXBUSERROR_MASK
457 #endif
458 | NRF_SPIM_INT_ENDRX_MASK
459 | NRF_SPIM_INT_ENDTX_MASK
460 | NRF_SPIM_INT_END_MASK ///< All SPIM interrupts.
461 } nrf_spim_int_mask_t;
462
463 #if NRF_SPIM_HAS_FREQUENCY
464 /** @brief SPI master data rates. */
465 typedef enum
466 {
467 NRF_SPIM_FREQ_125K = SPIM_FREQUENCY_FREQUENCY_K125, ///< 125 kbps.
468 NRF_SPIM_FREQ_250K = SPIM_FREQUENCY_FREQUENCY_K250, ///< 250 kbps.
469 NRF_SPIM_FREQ_500K = SPIM_FREQUENCY_FREQUENCY_K500, ///< 500 kbps.
470 NRF_SPIM_FREQ_1M = SPIM_FREQUENCY_FREQUENCY_M1, ///< 1 Mbps.
471 NRF_SPIM_FREQ_2M = SPIM_FREQUENCY_FREQUENCY_M2, ///< 2 Mbps.
472 NRF_SPIM_FREQ_4M = SPIM_FREQUENCY_FREQUENCY_M4, ///< 4 Mbps.
473 // Conversion to int is needed to prevent compilers from getting an error message
474 // that the provided value (0x80000000UL) is out of range for int.
475 NRF_SPIM_FREQ_8M = (int)SPIM_FREQUENCY_FREQUENCY_M8, ///< 8 Mbps.
476 #if NRF_SPIM_HAS_16_MHZ_FREQ
477 NRF_SPIM_FREQ_16M = SPIM_FREQUENCY_FREQUENCY_M16, ///< 16 Mbps.
478 #endif
479 #if NRF_SPIM_HAS_32_MHZ_FREQ
480 NRF_SPIM_FREQ_32M = SPIM_FREQUENCY_FREQUENCY_M32 ///< 32 Mbps.
481 #endif
482 } nrf_spim_frequency_t;
483 #endif // NRF_SPIM_HAS_FREQUENCY
484
485 /** @brief SPI modes. */
486 typedef enum
487 {
488 NRF_SPIM_MODE_0, ///< SCK active high, sample on leading edge of clock.
489 NRF_SPIM_MODE_1, ///< SCK active high, sample on trailing edge of clock.
490 NRF_SPIM_MODE_2, ///< SCK active low, sample on leading edge of clock.
491 NRF_SPIM_MODE_3 ///< SCK active low, sample on trailing edge of clock.
492 } nrf_spim_mode_t;
493
494 /** @brief SPI bit orders. */
495 typedef enum
496 {
497 NRF_SPIM_BIT_ORDER_MSB_FIRST = SPIM_CONFIG_ORDER_MsbFirst, ///< Most significant bit shifted out first.
498 NRF_SPIM_BIT_ORDER_LSB_FIRST = SPIM_CONFIG_ORDER_LsbFirst ///< Least significant bit shifted out first.
499 } nrf_spim_bit_order_t;
500
501 #if NRF_SPIM_HAS_HW_CSN
502 /** @brief SPI CSN pin polarity. */
503 typedef enum
504 {
505 #if defined(SPIM_CSNPOL_CSNPOL0_LOW)
506 NRF_SPIM_CSN_POL_LOW = SPIM_CSNPOL_CSNPOL0_LOW, ///< Active low (idle state high).
507 NRF_SPIM_CSN_POL_HIGH = SPIM_CSNPOL_CSNPOL0_HIGH ///< Active high (idle state low).
508 #else
509 NRF_SPIM_CSN_POL_LOW = SPIM_CSNPOL_CSNPOL_LOW, ///< Active low (idle state high).
510 NRF_SPIM_CSN_POL_HIGH = SPIM_CSNPOL_CSNPOL_HIGH ///< Active high (idle state low).
511 #endif
512 } nrf_spim_csn_pol_t;
513 #endif
514
515 /**
516 * @brief Function for activating the specified SPIM task.
517 *
518 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
519 * @param[in] task Task to be activated.
520 */
521 NRF_STATIC_INLINE void nrf_spim_task_trigger(NRF_SPIM_Type * p_reg,
522 nrf_spim_task_t task);
523
524 /**
525 * @brief Function for getting the address of the specified SPIM task register.
526 *
527 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
528 * @param[in] task The specified task.
529 *
530 * @return Address of the specified task register.
531 */
532 NRF_STATIC_INLINE uint32_t nrf_spim_task_address_get(NRF_SPIM_Type const * p_reg,
533 nrf_spim_task_t task);
534
535 /**
536 * @brief Function for clearing the specified SPIM event.
537 *
538 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
539 * @param[in] event Event to be cleared.
540 */
541 NRF_STATIC_INLINE void nrf_spim_event_clear(NRF_SPIM_Type * p_reg,
542 nrf_spim_event_t event);
543
544 /**
545 * @brief Function for retrieving the state of the SPIM event.
546 *
547 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
548 * @param[in] event Event to be checked.
549 *
550 * @retval true The event has been generated.
551 * @retval false The event has not been generated.
552 */
553 NRF_STATIC_INLINE bool nrf_spim_event_check(NRF_SPIM_Type const * p_reg,
554 nrf_spim_event_t event);
555
556 /**
557 * @brief Function for getting the address of the specified SPIM event register.
558 *
559 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
560 * @param[in] event The specified event.
561 *
562 * @return Address of the specified event register.
563 */
564 NRF_STATIC_INLINE uint32_t nrf_spim_event_address_get(NRF_SPIM_Type const * p_reg,
565 nrf_spim_event_t event);
566
567 /**
568 * @brief Function for enabling the specified shortcuts.
569 *
570 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
571 * @param[in] mask Shortcuts to be enabled.
572 */
573 NRF_STATIC_INLINE void nrf_spim_shorts_enable(NRF_SPIM_Type * p_reg,
574 uint32_t mask);
575
576 /**
577 * @brief Function for disabling the specified shortcuts.
578 *
579 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
580 * @param[in] mask Shortcuts to be disabled.
581 */
582 NRF_STATIC_INLINE void nrf_spim_shorts_disable(NRF_SPIM_Type * p_reg,
583 uint32_t mask);
584
585 /**
586 * @brief Function for getting the shortcut setting.
587 *
588 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
589 *
590 * @return Current shortcut configuration.
591 */
592 NRF_STATIC_INLINE uint32_t nrf_spim_shorts_get(NRF_SPIM_Type const * p_reg);
593
594 /**
595 * @brief Function for enabling the specified interrupts.
596 *
597 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
598 * @param[in] mask Mask of interrupts to be enabled.
599 * Use @ref nrf_spim_int_mask_t values for bit masking.
600 */
601 NRF_STATIC_INLINE void nrf_spim_int_enable(NRF_SPIM_Type * p_reg,
602 uint32_t mask);
603
604 /**
605 * @brief Function for disabling the specified interrupts.
606 *
607 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
608 * @param[in] mask Mask of interrupts to be disabled.
609 * Use @ref nrf_spim_int_mask_t values for bit masking.
610 */
611 NRF_STATIC_INLINE void nrf_spim_int_disable(NRF_SPIM_Type * p_reg,
612 uint32_t mask);
613
614 /**
615 * @brief Function for checking if the specified interrupts are enabled.
616 *
617 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
618 * @param[in] mask Mask of interrupts to be checked.
619 * Use @ref nrf_spim_int_mask_t values for bit masking.
620 *
621 * @return Mask of enabled interrupts.
622 */
623 NRF_STATIC_INLINE uint32_t nrf_spim_int_enable_check(NRF_SPIM_Type const * p_reg, uint32_t mask);
624
625 #if NRF_SPIM_HAS_PRESCALER
626 /**
627 * @brief Function for setting the prescaler value.
628 *
629 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
630 * @param[in] prescaler Prescaler value.
631 */
632 NRF_STATIC_INLINE void nrf_spim_prescaler_set(NRF_SPIM_Type * p_reg,
633 uint32_t prescaler);
634
635 /**
636 * @brief Function for getting the prescaler value.
637 *
638 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
639 *
640 * @return Prescaler value.
641 */
642 NRF_STATIC_INLINE uint32_t nrf_spim_prescaler_get(NRF_SPIM_Type const * p_reg);
643 #endif
644
645 #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
646 /**
647 * @brief Function for setting the subscribe configuration for a given
648 * SPIM task.
649 *
650 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
651 * @param[in] task Task for which to set the configuration.
652 * @param[in] channel Channel through which to subscribe events.
653 */
654 NRF_STATIC_INLINE void nrf_spim_subscribe_set(NRF_SPIM_Type * p_reg,
655 nrf_spim_task_t task,
656 uint8_t channel);
657
658 /**
659 * @brief Function for clearing the subscribe configuration for a given
660 * SPIM task.
661 *
662 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
663 * @param[in] task Task for which to clear the configuration.
664 */
665 NRF_STATIC_INLINE void nrf_spim_subscribe_clear(NRF_SPIM_Type * p_reg,
666 nrf_spim_task_t task);
667
668 /**
669 * @brief Function for setting the publish configuration for a given
670 * SPIM event.
671 *
672 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
673 * @param[in] event Event for which to set the configuration.
674 * @param[in] channel Channel through which to publish the event.
675 */
676 NRF_STATIC_INLINE void nrf_spim_publish_set(NRF_SPIM_Type * p_reg,
677 nrf_spim_event_t event,
678 uint8_t channel);
679
680 /**
681 * @brief Function for clearing the publish configuration for a given
682 * SPIM event.
683 *
684 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
685 * @param[in] event Event for which to clear the configuration.
686 */
687 NRF_STATIC_INLINE void nrf_spim_publish_clear(NRF_SPIM_Type * p_reg,
688 nrf_spim_event_t event);
689 #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
690
691 /**
692 * @brief Function for enabling the SPIM peripheral.
693 *
694 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
695 */
696 NRF_STATIC_INLINE void nrf_spim_enable(NRF_SPIM_Type * p_reg);
697
698 /**
699 * @brief Function for disabling the SPIM peripheral.
700 *
701 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
702 */
703 NRF_STATIC_INLINE void nrf_spim_disable(NRF_SPIM_Type * p_reg);
704
705 /**
706 * @brief Function for checking if the SPIM peripheral is enabled.
707 *
708 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
709 *
710 * @retval true The SPIM is enabled.
711 * @retval false The SPIM is not enabled.
712 */
713 NRF_STATIC_INLINE bool nrf_spim_enable_check(NRF_SPIM_Type const * p_reg);
714
715 /**
716 * @brief Function for configuring SPIM pins.
717 *
718 * If a given signal is not needed, pass the @ref NRF_SPIM_PIN_NOT_CONNECTED
719 * value instead of its pin number.
720 *
721 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
722 * @param[in] sck_pin SCK pin number.
723 * @param[in] mosi_pin MOSI pin number.
724 * @param[in] miso_pin MISO pin number.
725 */
726 NRF_STATIC_INLINE void nrf_spim_pins_set(NRF_SPIM_Type * p_reg,
727 uint32_t sck_pin,
728 uint32_t mosi_pin,
729 uint32_t miso_pin);
730
731 /**
732 * @brief Function for getting the SCK pin selection.
733 *
734 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
735 *
736 * @return SCK pin selection.
737 */
738 NRF_STATIC_INLINE uint32_t nrf_spim_sck_pin_get(NRF_SPIM_Type const * p_reg);
739
740 /**
741 * @brief Function for getting the MOSI pin selection.
742 *
743 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
744 *
745 * @return MOSI pin selection.
746 */
747 NRF_STATIC_INLINE uint32_t nrf_spim_mosi_pin_get(NRF_SPIM_Type const * p_reg);
748
749 /**
750 * @brief Function for getting the MISO pin selection.
751 *
752 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
753 *
754 * @return MISO pin selection.
755 */
756 NRF_STATIC_INLINE uint32_t nrf_spim_miso_pin_get(NRF_SPIM_Type const * p_reg);
757
758 #if NRF_SPIM_HAS_HW_CSN
759 /**
760 * @brief Function for configuring the SPIM hardware CSN pin.
761 *
762 * If this signal is not needed, pass the @ref NRF_SPIM_PIN_NOT_CONNECTED
763 * value instead of its pin number.
764 *
765 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
766 * @param[in] pin CSN pin number.
767 * @param[in] polarity CSN pin polarity.
768 * @param[in] duration Minimum duration between the edge of CSN and the edge of SCK
769 * and minimum duration of CSN must stay unselected between transactions.
770 * The value is specified in number of 64 MHz clock cycles (15.625 ns).
771 */
772 NRF_STATIC_INLINE void nrf_spim_csn_configure(NRF_SPIM_Type * p_reg,
773 uint32_t pin,
774 nrf_spim_csn_pol_t polarity,
775 uint32_t duration);
776
777 /**
778 * @brief Function for getting the CSN pin selection.
779 *
780 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
781 *
782 * @return CSN pin selection.
783 */
784 NRF_STATIC_INLINE uint32_t nrf_spim_csn_pin_get(NRF_SPIM_Type const * p_reg);
785 #endif
786
787 #if NRF_SPIM_HAS_DCX
788 /**
789 * @brief Function for configuring the SPIM DCX pin.
790 *
791 * If this signal is not needed, pass the @ref NRF_SPIM_PIN_NOT_CONNECTED
792 * value instead of its pin number.
793 *
794 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
795 * @param[in] dcx_pin DCX pin number.
796 */
797 NRF_STATIC_INLINE void nrf_spim_dcx_pin_set(NRF_SPIM_Type * p_reg,
798 uint32_t dcx_pin);
799
800 /**
801 * @brief Function for getting the DCX pin selection.
802 *
803 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
804 *
805 * @return DCX pin selection.
806 */
807 NRF_STATIC_INLINE uint32_t nrf_spim_dcx_pin_get(NRF_SPIM_Type const * p_reg);
808
809 /**
810 * @brief Function for configuring the number of command bytes.
811 *
812 * Maximum value available for dividing the transmitted bytes into command
813 * bytes and data bytes is @ref NRF_SPIM_DCX_CNT_ALL_CMD - 1.
814 * The @ref NRF_SPIM_DCX_CNT_ALL_CMD value passed as the @c count parameter
815 * causes all transmitted bytes to be marked as command bytes.
816 *
817 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
818 * @param[in] count Number of command bytes preceding the data bytes.
819 */
820 NRF_STATIC_INLINE void nrf_spim_dcx_cnt_set(NRF_SPIM_Type * p_reg,
821 uint32_t count);
822 #endif // NRF_SPIM_HAS_DCX
823
824 #if NRF_SPIM_HAS_RXDELAY
825 /**
826 * @brief Function for configuring the extended SPIM interface.
827 *
828 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
829 * @param[in] rxdelay Sample delay for input serial data on MISO,
830 * specified in 64 MHz clock cycles (15.625 ns) from the sampling edge of SCK.
831 */
832 NRF_STATIC_INLINE void nrf_spim_iftiming_set(NRF_SPIM_Type * p_reg,
833 uint32_t rxdelay);
834 #endif
835
836 #if NRF_SPIM_HAS_STALLSTAT
837 /**
838 * @brief Function for clearing stall status for RX EasyDMA RAM accesses.
839 *
840 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
841 */
842 NRF_STATIC_INLINE void nrf_spim_stallstat_rx_clear(NRF_SPIM_Type * p_reg);
843
844 /**
845 * @brief Function for getting stall status for RX EasyDMA RAM accesses.
846 *
847 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
848 *
849 * @return Stall status of RX EasyDMA RAM accesses.
850 */
851 NRF_STATIC_INLINE bool nrf_spim_stallstat_rx_get(NRF_SPIM_Type const * p_reg);
852
853 /**
854 * @brief Function for clearing stall status for TX EasyDMA RAM accesses.
855 *
856 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
857 */
858 NRF_STATIC_INLINE void nrf_spim_stallstat_tx_clear(NRF_SPIM_Type * p_reg);
859
860 /**
861 * @brief Function for getting stall status for TX EasyDMA RAM accesses.
862 *
863 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
864 *
865 * @return Stall status of TX EasyDMA RAM accesses.
866 */
867 NRF_STATIC_INLINE bool nrf_spim_stallstat_tx_get(NRF_SPIM_Type const * p_reg);
868 #endif // NRF_SPIM_HAS_STALLSTAT
869
870 #if NRF_SPIM_HAS_FREQUENCY
871 /**
872 * @brief Function for setting the SPI master data rate.
873 *
874 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
875 * @param[in] frequency SPI frequency.
876 */
877 NRF_STATIC_INLINE void nrf_spim_frequency_set(NRF_SPIM_Type * p_reg,
878 nrf_spim_frequency_t frequency);
879
880 /**
881 * @brief Function for getting the SPI master data rate.
882 *
883 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
884 *
885 * @retval SPI master frequency.
886 */
887 NRF_STATIC_INLINE nrf_spim_frequency_t nrf_spim_frequency_get(NRF_SPIM_Type * p_reg);
888 #endif
889
890 /**
891 * @brief Function for setting the transmit buffer.
892 *
893 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
894 * @param[in] p_buffer Pointer to the buffer with data to send.
895 * @param[in] length Maximum number of data bytes to transmit.
896 */
897 NRF_STATIC_INLINE void nrf_spim_tx_buffer_set(NRF_SPIM_Type * p_reg,
898 uint8_t const * p_buffer,
899 size_t length);
900
901 /**
902 * @brief Function for getting number of bytes transmitted in the last transaction.
903 *
904 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
905 *
906 * @retval Amount of bytes transmitted.
907 */
908 NRF_STATIC_INLINE uint32_t nrf_spim_tx_amount_get(NRF_SPIM_Type const * p_reg);
909
910 /**
911 * @brief Function for getting number of bytes to be transmitted in the next transaction.
912 *
913 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
914 *
915 * @retval Amount of bytes to be transmitted.
916 */
917 NRF_STATIC_INLINE uint32_t nrf_spim_tx_maxcnt_get(NRF_SPIM_Type const * p_reg);
918
919 /**
920 * @brief Function for setting the receive buffer.
921 *
922 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
923 * @param[in] p_buffer Pointer to the buffer for received data.
924 * @param[in] length Maximum number of data bytes to receive.
925 */
926 NRF_STATIC_INLINE void nrf_spim_rx_buffer_set(NRF_SPIM_Type * p_reg,
927 uint8_t * p_buffer,
928 size_t length);
929
930 /**
931 * @brief Function for getting number of bytes received in the last transaction.
932 *
933 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
934 *
935 * @retval Amount of bytes received.
936 */
937 NRF_STATIC_INLINE uint32_t nrf_spim_rx_amount_get(NRF_SPIM_Type const * p_reg);
938
939 /**
940 * @brief Function for getting number of bytes to be received in the next transaction.
941 *
942 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
943 *
944 * @retval Amount of bytes to be received.
945 */
946 NRF_STATIC_INLINE uint32_t nrf_spim_rx_maxcnt_get(NRF_SPIM_Type const * p_reg);
947
948 /**
949 * @brief Function for setting the SPI configuration.
950 *
951 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
952 * @param[in] spi_mode SPI mode.
953 * @param[in] spi_bit_order SPI bit order.
954 */
955 NRF_STATIC_INLINE void nrf_spim_configure(NRF_SPIM_Type * p_reg,
956 nrf_spim_mode_t spi_mode,
957 nrf_spim_bit_order_t spi_bit_order);
958
959 /**
960 * @brief Function for setting the over-read character.
961 *
962 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
963 * @param[in] orc Over-read character that is clocked out in case of
964 * an over-read of the TXD buffer.
965 */
966 NRF_STATIC_INLINE void nrf_spim_orc_set(NRF_SPIM_Type * p_reg,
967 uint8_t orc);
968
969 #if NRF_SPIM_HAS_ARRAY_LIST
970 /**
971 * @brief Function for enabling the TX list feature.
972 *
973 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
974 */
975 NRF_STATIC_INLINE void nrf_spim_tx_list_enable(NRF_SPIM_Type * p_reg);
976
977 /**
978 * @brief Function for disabling the TX list feature.
979 *
980 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
981 */
982 NRF_STATIC_INLINE void nrf_spim_tx_list_disable(NRF_SPIM_Type * p_reg);
983
984 /**
985 * @brief Function for enabling the RX list feature.
986 *
987 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
988 */
989 NRF_STATIC_INLINE void nrf_spim_rx_list_enable(NRF_SPIM_Type * p_reg);
990
991 /**
992 * @brief Function for disabling the RX list feature.
993 *
994 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
995 */
996 NRF_STATIC_INLINE void nrf_spim_rx_list_disable(NRF_SPIM_Type * p_reg);
997 #endif
998
999 #if NRF_SPIM_HAS_DMA_TASKS_EVENTS
1000 /**
1001 * @brief Function for enabling individual pattern match filters.
1002 *
1003 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1004 * @param[in] index Index of pattern match filter.
1005 * @param[in] enable True if pattern match filter is to be enabled, false otherwise.
1006 */
1007 NRF_STATIC_INLINE void nrf_spim_rx_pattern_match_enable_set(NRF_SPIM_Type * p_reg,
1008 uint8_t index,
1009 bool enable);
1010
1011 /**
1012 * @brief Function for checking if the specified pattern match filter is enabled.
1013 *
1014 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1015 * @param[in] index Index of pattern match filter.
1016 *
1017 * @retval true Pattern match filter is enabled.
1018 * @retval false Pattern match filter is disabled.
1019 */
1020 NRF_STATIC_INLINE bool nrf_spim_rx_pattern_match_enable_check(NRF_SPIM_Type const * p_reg,
1021 uint8_t index);
1022
1023 /**
1024 * @brief Function for enabling one-shot operation for the specified match filter.
1025 *
1026 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1027 * @param[in] index Index of pattern match filter.
1028 */
1029 NRF_STATIC_INLINE void nrf_spim_rx_pattern_match_one_shot_enable(NRF_SPIM_Type * p_reg,
1030 uint8_t index);
1031
1032 /**
1033 * @brief Function for disabling one-shot operation for the specified match filter.
1034 *
1035 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1036 * @param[in] index Index of pattern match filter.
1037 */
1038 NRF_STATIC_INLINE void nrf_spim_rx_pattern_match_one_shot_disable(NRF_SPIM_Type * p_reg,
1039 uint8_t index);
1040
1041 /**
1042 * @brief Function for checking if specified pattern match filter is configured as one-shot.
1043 *
1044 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1045 * @param[in] index Index of pattern match filter.
1046 *
1047 * @retval true Pattern match filter is configured as one-shot.
1048 * @retval false Pattern match filter is configured as continuous.
1049 */
1050 NRF_STATIC_INLINE bool nrf_spim_rx_pattern_match_one_shot_check(NRF_SPIM_Type const * p_reg,
1051 uint8_t index);
1052
1053 /**
1054 * @brief Function for setting the pattern to be looked for by the specified match filter.
1055 *
1056 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1057 * @param[in] index Index of pattern match filter.
1058 * @param[in] pattern Pattern to be looked for.
1059 * Match will trigger the corresponding event, if enabled.
1060 */
1061 NRF_STATIC_INLINE void nrf_spim_rx_pattern_match_candidate_set(NRF_SPIM_Type * p_reg,
1062 uint8_t index,
1063 uint32_t pattern);
1064
1065 /**
1066 * @brief Function for getting the pattern that the specified match filter is looking for.
1067 *
1068 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1069 * @param[in] index Index of pattern match filter.
1070 *
1071 * @return Pattern that the specified match filter is looking for.
1072 */
1073 NRF_STATIC_INLINE uint32_t nrf_spim_rx_pattern_match_candidate_get(NRF_SPIM_Type const * p_reg,
1074 uint8_t index);
1075 #endif // NRF_SPIM_HAS_DMA_TASKS_EVENTS
1076
1077 #if NRF_SPIM_HAS_DMA_REG
1078 /**
1079 * @brief Function for enabling the termination of the RX transaction after detecting the BUSERROR event.
1080 *
1081 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1082 */
1083 NRF_STATIC_INLINE void nrf_spim_rx_terminate_on_bus_error_enable(NRF_SPIM_Type * p_reg);
1084
1085 /**
1086 * @brief Function for disabling the termination of the RX transaction after detecting the BUSERROR event.
1087 *
1088 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1089 */
1090 NRF_STATIC_INLINE void nrf_spim_rx_terminate_on_bus_error_disable(NRF_SPIM_Type * p_reg);
1091
1092 /**
1093 * @brief Function for checking if RX transaction termination after detecting the BUSERROR event is enabled.
1094 *
1095 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1096 *
1097 * @retval true RX transaction termination after detecting a BUSERROR event is enabled.
1098 * @retval false RX transaction termination after detecting a BUSERROR event is disabled.
1099 */
1100 NRF_STATIC_INLINE bool nrf_spim_rx_terminate_on_bus_error_check(NRF_SPIM_Type const * p_reg);
1101
1102 /**
1103 * @brief Function for enabling the termination of the TX transaction after detecting the BUSERROR event.
1104 *
1105 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1106 */
1107 NRF_STATIC_INLINE void nrf_spim_tx_terminate_on_bus_error_enable(NRF_SPIM_Type * p_reg);
1108
1109 /**
1110 * @brief Function for disabling the termination of the TX transaction after detecting the BUSERROR event.
1111 *
1112 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1113 */
1114 NRF_STATIC_INLINE void nrf_spim_tx_terminate_on_bus_error_disable(NRF_SPIM_Type * p_reg);
1115
1116 /**
1117 * @brief Function for checking if TX transaction termination after detecting the BUSERROR event is enabled.
1118 *
1119 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1120 *
1121 * @retval true TX transaction termination after detecting a BUSERROR event is enabled.
1122 * @retval false TX transaction termination after detecting a BUSERROR event is disabled.
1123 */
1124 NRF_STATIC_INLINE bool nrf_spim_tx_terminate_on_bus_error_check(NRF_SPIM_Type const * p_reg);
1125 #endif // NRF_SPIM_HAS_DMA_REG
1126
1127 #ifndef NRF_DECLARE_ONLY
1128
nrf_spim_task_trigger(NRF_SPIM_Type * p_reg,nrf_spim_task_t task)1129 NRF_STATIC_INLINE void nrf_spim_task_trigger(NRF_SPIM_Type * p_reg,
1130 nrf_spim_task_t task)
1131 {
1132 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
1133 }
1134
nrf_spim_task_address_get(NRF_SPIM_Type const * p_reg,nrf_spim_task_t task)1135 NRF_STATIC_INLINE uint32_t nrf_spim_task_address_get(NRF_SPIM_Type const * p_reg,
1136 nrf_spim_task_t task)
1137 {
1138 return nrf_task_event_address_get(p_reg, task);
1139 }
1140
nrf_spim_event_clear(NRF_SPIM_Type * p_reg,nrf_spim_event_t event)1141 NRF_STATIC_INLINE void nrf_spim_event_clear(NRF_SPIM_Type * p_reg,
1142 nrf_spim_event_t event)
1143 {
1144 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
1145 nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
1146 }
1147
nrf_spim_event_check(NRF_SPIM_Type const * p_reg,nrf_spim_event_t event)1148 NRF_STATIC_INLINE bool nrf_spim_event_check(NRF_SPIM_Type const * p_reg,
1149 nrf_spim_event_t event)
1150 {
1151 return nrf_event_check(p_reg, event);
1152 }
1153
nrf_spim_event_address_get(NRF_SPIM_Type const * p_reg,nrf_spim_event_t event)1154 NRF_STATIC_INLINE uint32_t nrf_spim_event_address_get(NRF_SPIM_Type const * p_reg,
1155 nrf_spim_event_t event)
1156 {
1157 return nrf_task_event_address_get(p_reg, event);
1158 }
1159
nrf_spim_shorts_enable(NRF_SPIM_Type * p_reg,uint32_t mask)1160 NRF_STATIC_INLINE void nrf_spim_shorts_enable(NRF_SPIM_Type * p_reg,
1161 uint32_t mask)
1162 {
1163 p_reg->SHORTS |= mask;
1164 }
1165
nrf_spim_shorts_disable(NRF_SPIM_Type * p_reg,uint32_t mask)1166 NRF_STATIC_INLINE void nrf_spim_shorts_disable(NRF_SPIM_Type * p_reg,
1167 uint32_t mask)
1168 {
1169 p_reg->SHORTS &= ~(mask);
1170 }
1171
nrf_spim_shorts_get(NRF_SPIM_Type const * p_reg)1172 NRF_STATIC_INLINE uint32_t nrf_spim_shorts_get(NRF_SPIM_Type const * p_reg)
1173 {
1174 return p_reg->SHORTS;
1175 }
1176
nrf_spim_int_enable(NRF_SPIM_Type * p_reg,uint32_t mask)1177 NRF_STATIC_INLINE void nrf_spim_int_enable(NRF_SPIM_Type * p_reg,
1178 uint32_t mask)
1179 {
1180 p_reg->INTENSET = mask;
1181 }
1182
nrf_spim_int_disable(NRF_SPIM_Type * p_reg,uint32_t mask)1183 NRF_STATIC_INLINE void nrf_spim_int_disable(NRF_SPIM_Type * p_reg,
1184 uint32_t mask)
1185 {
1186 p_reg->INTENCLR = mask;
1187 }
1188
nrf_spim_int_enable_check(NRF_SPIM_Type const * p_reg,uint32_t mask)1189 NRF_STATIC_INLINE uint32_t nrf_spim_int_enable_check(NRF_SPIM_Type const * p_reg, uint32_t mask)
1190 {
1191 return p_reg->INTENSET & mask;
1192 }
1193
1194 #if NRF_SPIM_HAS_PRESCALER
nrf_spim_prescaler_set(NRF_SPIM_Type * p_reg,uint32_t prescaler)1195 NRF_STATIC_INLINE void nrf_spim_prescaler_set(NRF_SPIM_Type * p_reg,
1196 uint32_t prescaler)
1197 {
1198 NRFX_ASSERT(prescaler >= NRF_SPIM_PRESCALER_MIN_GET(p_reg));
1199 NRFX_ASSERT(prescaler <= NRF_SPIM_PRESCALER_MAX_GET(p_reg));
1200 NRFX_ASSERT(NRFX_IS_EVEN(prescaler));
1201 p_reg->PRESCALER = prescaler;
1202 }
1203
nrf_spim_prescaler_get(NRF_SPIM_Type const * p_reg)1204 NRF_STATIC_INLINE uint32_t nrf_spim_prescaler_get(NRF_SPIM_Type const * p_reg)
1205 {
1206 return p_reg->PRESCALER;
1207 }
1208 #endif
1209
1210 #if defined(DPPI_PRESENT)
nrf_spim_subscribe_set(NRF_SPIM_Type * p_reg,nrf_spim_task_t task,uint8_t channel)1211 NRF_STATIC_INLINE void nrf_spim_subscribe_set(NRF_SPIM_Type * p_reg,
1212 nrf_spim_task_t task,
1213 uint8_t channel)
1214 {
1215 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
1216 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
1217 }
1218
nrf_spim_subscribe_clear(NRF_SPIM_Type * p_reg,nrf_spim_task_t task)1219 NRF_STATIC_INLINE void nrf_spim_subscribe_clear(NRF_SPIM_Type * p_reg,
1220 nrf_spim_task_t task)
1221 {
1222 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
1223 }
1224
nrf_spim_publish_set(NRF_SPIM_Type * p_reg,nrf_spim_event_t event,uint8_t channel)1225 NRF_STATIC_INLINE void nrf_spim_publish_set(NRF_SPIM_Type * p_reg,
1226 nrf_spim_event_t event,
1227 uint8_t channel)
1228 {
1229 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
1230 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
1231 }
1232
nrf_spim_publish_clear(NRF_SPIM_Type * p_reg,nrf_spim_event_t event)1233 NRF_STATIC_INLINE void nrf_spim_publish_clear(NRF_SPIM_Type * p_reg,
1234 nrf_spim_event_t event)
1235 {
1236 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
1237 }
1238 #endif
1239
nrf_spim_enable(NRF_SPIM_Type * p_reg)1240 NRF_STATIC_INLINE void nrf_spim_enable(NRF_SPIM_Type * p_reg)
1241 {
1242 p_reg->ENABLE = (SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos);
1243 }
1244
nrf_spim_disable(NRF_SPIM_Type * p_reg)1245 NRF_STATIC_INLINE void nrf_spim_disable(NRF_SPIM_Type * p_reg)
1246 {
1247 p_reg->ENABLE = (SPIM_ENABLE_ENABLE_Disabled << SPIM_ENABLE_ENABLE_Pos);
1248 }
1249
nrf_spim_enable_check(NRF_SPIM_Type const * p_reg)1250 NRF_STATIC_INLINE bool nrf_spim_enable_check(NRF_SPIM_Type const * p_reg)
1251 {
1252 return p_reg->ENABLE == SPIM_ENABLE_ENABLE_Enabled;
1253 }
1254
nrf_spim_pins_set(NRF_SPIM_Type * p_reg,uint32_t sck_pin,uint32_t mosi_pin,uint32_t miso_pin)1255 NRF_STATIC_INLINE void nrf_spim_pins_set(NRF_SPIM_Type * p_reg,
1256 uint32_t sck_pin,
1257 uint32_t mosi_pin,
1258 uint32_t miso_pin)
1259 {
1260 p_reg->PSEL.SCK = sck_pin;
1261 p_reg->PSEL.MOSI = mosi_pin;
1262 p_reg->PSEL.MISO = miso_pin;
1263 }
1264
nrf_spim_sck_pin_get(NRF_SPIM_Type const * p_reg)1265 NRF_STATIC_INLINE uint32_t nrf_spim_sck_pin_get(NRF_SPIM_Type const * p_reg)
1266 {
1267 return p_reg->PSEL.SCK;
1268 }
1269
nrf_spim_mosi_pin_get(NRF_SPIM_Type const * p_reg)1270 NRF_STATIC_INLINE uint32_t nrf_spim_mosi_pin_get(NRF_SPIM_Type const * p_reg)
1271 {
1272 return p_reg->PSEL.MOSI;
1273 }
1274
nrf_spim_miso_pin_get(NRF_SPIM_Type const * p_reg)1275 NRF_STATIC_INLINE uint32_t nrf_spim_miso_pin_get(NRF_SPIM_Type const * p_reg)
1276 {
1277 return p_reg->PSEL.MISO;
1278 }
1279
1280 #if NRF_SPIM_HAS_HW_CSN
nrf_spim_csn_configure(NRF_SPIM_Type * p_reg,uint32_t pin,nrf_spim_csn_pol_t polarity,uint32_t duration)1281 NRF_STATIC_INLINE void nrf_spim_csn_configure(NRF_SPIM_Type * p_reg,
1282 uint32_t pin,
1283 nrf_spim_csn_pol_t polarity,
1284 uint32_t duration)
1285 {
1286 #if defined(SPIM_CSNPOL_CSNPOL0_LOW) && defined(SPIM_PSEL_CSN_MaxCount)
1287 p_reg->PSEL.CSN[0] = pin;
1288 #else
1289 p_reg->PSEL.CSN = pin;
1290 #endif
1291 p_reg->CSNPOL = polarity;
1292 p_reg->IFTIMING.CSNDUR = duration;
1293 }
1294
nrf_spim_csn_pin_get(NRF_SPIM_Type const * p_reg)1295 NRF_STATIC_INLINE uint32_t nrf_spim_csn_pin_get(NRF_SPIM_Type const * p_reg)
1296 {
1297 #if defined(SPIM_CSNPOL_CSNPOL0_LOW) && defined(SPIM_PSEL_CSN_MaxCount)
1298 return p_reg->PSEL.CSN[0];
1299 #else
1300 return p_reg->PSEL.CSN;
1301 #endif
1302 }
1303 #endif // NRF_SPIM_HAS_HW_CSN
1304
1305 #if NRF_SPIM_HAS_DCX
nrf_spim_dcx_pin_set(NRF_SPIM_Type * p_reg,uint32_t dcx_pin)1306 NRF_STATIC_INLINE void nrf_spim_dcx_pin_set(NRF_SPIM_Type * p_reg, uint32_t dcx_pin)
1307 {
1308 #if defined(SPIM_PSEL_DCX_PIN_Msk)
1309 p_reg->PSEL.DCX = dcx_pin;
1310 #else
1311 p_reg->PSELDCX = dcx_pin;
1312 #endif
1313 }
1314
nrf_spim_dcx_pin_get(NRF_SPIM_Type const * p_reg)1315 NRF_STATIC_INLINE uint32_t nrf_spim_dcx_pin_get(NRF_SPIM_Type const * p_reg)
1316 {
1317 #if defined(SPIM_PSEL_DCX_PIN_Msk)
1318 return p_reg->PSEL.DCX;
1319 #else
1320 return p_reg->PSELDCX;
1321 #endif
1322 }
1323
nrf_spim_dcx_cnt_set(NRF_SPIM_Type * p_reg,uint32_t dcx_cnt)1324 NRF_STATIC_INLINE void nrf_spim_dcx_cnt_set(NRF_SPIM_Type * p_reg, uint32_t dcx_cnt)
1325 {
1326 p_reg->DCXCNT = dcx_cnt;
1327 }
1328 #endif // NRF_SPIM_HAS_DCX
1329
1330 #if NRF_SPIM_HAS_RXDELAY
nrf_spim_iftiming_set(NRF_SPIM_Type * p_reg,uint32_t rxdelay)1331 NRF_STATIC_INLINE void nrf_spim_iftiming_set(NRF_SPIM_Type * p_reg,
1332 uint32_t rxdelay)
1333 {
1334 p_reg->IFTIMING.RXDELAY = rxdelay;
1335 }
1336 #endif
1337
1338 #if NRF_SPIM_HAS_STALLSTAT
nrf_spim_stallstat_rx_clear(NRF_SPIM_Type * p_reg)1339 NRF_STATIC_INLINE void nrf_spim_stallstat_rx_clear(NRF_SPIM_Type * p_reg)
1340 {
1341 p_reg->STALLSTAT &= ~(SPIM_STALLSTAT_RX_Msk);
1342 }
1343
nrf_spim_stallstat_rx_get(NRF_SPIM_Type const * p_reg)1344 NRF_STATIC_INLINE bool nrf_spim_stallstat_rx_get(NRF_SPIM_Type const * p_reg)
1345 {
1346 return (p_reg->STALLSTAT & SPIM_STALLSTAT_RX_Msk) != 0;
1347 }
1348
nrf_spim_stallstat_tx_clear(NRF_SPIM_Type * p_reg)1349 NRF_STATIC_INLINE void nrf_spim_stallstat_tx_clear(NRF_SPIM_Type * p_reg)
1350 {
1351 p_reg->STALLSTAT &= ~(SPIM_STALLSTAT_TX_Msk);
1352 }
1353
nrf_spim_stallstat_tx_get(NRF_SPIM_Type const * p_reg)1354 NRF_STATIC_INLINE bool nrf_spim_stallstat_tx_get(NRF_SPIM_Type const * p_reg)
1355 {
1356 return (p_reg->STALLSTAT & SPIM_STALLSTAT_TX_Msk) != 0;
1357 }
1358 #endif
1359
1360 #if NRF_SPIM_HAS_FREQUENCY
nrf_spim_frequency_set(NRF_SPIM_Type * p_reg,nrf_spim_frequency_t frequency)1361 NRF_STATIC_INLINE void nrf_spim_frequency_set(NRF_SPIM_Type * p_reg,
1362 nrf_spim_frequency_t frequency)
1363 {
1364 p_reg->FREQUENCY = (uint32_t)frequency;
1365 }
1366
nrf_spim_frequency_get(NRF_SPIM_Type * p_reg)1367 NRF_STATIC_INLINE nrf_spim_frequency_t nrf_spim_frequency_get(NRF_SPIM_Type * p_reg)
1368 {
1369 return (nrf_spim_frequency_t)(p_reg->FREQUENCY);
1370 }
1371 #endif
1372
nrf_spim_tx_buffer_set(NRF_SPIM_Type * p_reg,uint8_t const * p_buffer,size_t length)1373 NRF_STATIC_INLINE void nrf_spim_tx_buffer_set(NRF_SPIM_Type * p_reg,
1374 uint8_t const * p_buffer,
1375 size_t length)
1376 {
1377 #if NRF_SPIM_HAS_DMA_REG
1378 p_reg->DMA.TX.PTR = (uint32_t)p_buffer;
1379 p_reg->DMA.TX.MAXCNT = length;
1380 #else
1381 p_reg->TXD.PTR = (uint32_t)p_buffer;
1382 p_reg->TXD.MAXCNT = length;
1383 #endif
1384 }
1385
nrf_spim_tx_amount_get(NRF_SPIM_Type const * p_reg)1386 NRF_STATIC_INLINE uint32_t nrf_spim_tx_amount_get(NRF_SPIM_Type const * p_reg)
1387 {
1388 #if NRF_SPIM_HAS_DMA_REG
1389 return p_reg->DMA.TX.AMOUNT;
1390 #else
1391 return p_reg->TXD.AMOUNT;
1392 #endif
1393 }
1394
nrf_spim_tx_maxcnt_get(NRF_SPIM_Type const * p_reg)1395 NRF_STATIC_INLINE uint32_t nrf_spim_tx_maxcnt_get(NRF_SPIM_Type const * p_reg)
1396 {
1397 #if NRF_SPIM_HAS_DMA_REG
1398 return p_reg->DMA.TX.MAXCNT;
1399 #else
1400 return p_reg->TXD.MAXCNT;
1401 #endif
1402 }
1403
nrf_spim_rx_buffer_set(NRF_SPIM_Type * p_reg,uint8_t * p_buffer,size_t length)1404 NRF_STATIC_INLINE void nrf_spim_rx_buffer_set(NRF_SPIM_Type * p_reg,
1405 uint8_t * p_buffer,
1406 size_t length)
1407 {
1408 #if NRF_SPIM_HAS_DMA_REG
1409 p_reg->DMA.RX.PTR = (uint32_t)p_buffer;
1410 p_reg->DMA.RX.MAXCNT = length;
1411 #else
1412 p_reg->RXD.PTR = (uint32_t)p_buffer;
1413 p_reg->RXD.MAXCNT = length;
1414 #endif
1415 }
1416
nrf_spim_rx_amount_get(NRF_SPIM_Type const * p_reg)1417 NRF_STATIC_INLINE uint32_t nrf_spim_rx_amount_get(NRF_SPIM_Type const * p_reg)
1418 {
1419 #if NRF_SPIM_HAS_DMA_REG
1420 return p_reg->DMA.RX.AMOUNT;
1421 #else
1422 return p_reg->RXD.AMOUNT;
1423 #endif
1424 }
1425
nrf_spim_rx_maxcnt_get(NRF_SPIM_Type const * p_reg)1426 NRF_STATIC_INLINE uint32_t nrf_spim_rx_maxcnt_get(NRF_SPIM_Type const * p_reg)
1427 {
1428 #if NRF_SPIM_HAS_DMA_REG
1429 return p_reg->DMA.RX.MAXCNT;
1430 #else
1431 return p_reg->RXD.MAXCNT;
1432 #endif
1433 }
1434
nrf_spim_configure(NRF_SPIM_Type * p_reg,nrf_spim_mode_t spi_mode,nrf_spim_bit_order_t spi_bit_order)1435 NRF_STATIC_INLINE void nrf_spim_configure(NRF_SPIM_Type * p_reg,
1436 nrf_spim_mode_t spi_mode,
1437 nrf_spim_bit_order_t spi_bit_order)
1438 {
1439 uint32_t config = (spi_bit_order == NRF_SPIM_BIT_ORDER_MSB_FIRST ?
1440 SPIM_CONFIG_ORDER_MsbFirst : SPIM_CONFIG_ORDER_LsbFirst);
1441 switch (spi_mode)
1442 {
1443 default:
1444 case NRF_SPIM_MODE_0:
1445 config |= (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) |
1446 (SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos);
1447 break;
1448
1449 case NRF_SPIM_MODE_1:
1450 config |= (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) |
1451 (SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos);
1452 break;
1453
1454 case NRF_SPIM_MODE_2:
1455 config |= (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos) |
1456 (SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos);
1457 break;
1458
1459 case NRF_SPIM_MODE_3:
1460 config |= (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos) |
1461 (SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos);
1462 break;
1463 }
1464 p_reg->CONFIG = config;
1465 }
1466
nrf_spim_orc_set(NRF_SPIM_Type * p_reg,uint8_t orc)1467 NRF_STATIC_INLINE void nrf_spim_orc_set(NRF_SPIM_Type * p_reg,
1468 uint8_t orc)
1469 {
1470 p_reg->ORC = orc;
1471 }
1472
1473 #if NRF_SPIM_HAS_ARRAY_LIST
nrf_spim_tx_list_enable(NRF_SPIM_Type * p_reg)1474 NRF_STATIC_INLINE void nrf_spim_tx_list_enable(NRF_SPIM_Type * p_reg)
1475 {
1476 p_reg->TXD.LIST = SPIM_TXD_LIST_LIST_ArrayList << SPIM_TXD_LIST_LIST_Pos;
1477 }
1478
nrf_spim_tx_list_disable(NRF_SPIM_Type * p_reg)1479 NRF_STATIC_INLINE void nrf_spim_tx_list_disable(NRF_SPIM_Type * p_reg)
1480 {
1481 p_reg->TXD.LIST = SPIM_TXD_LIST_LIST_Disabled << SPIM_TXD_LIST_LIST_Pos;
1482 }
1483
nrf_spim_rx_list_enable(NRF_SPIM_Type * p_reg)1484 NRF_STATIC_INLINE void nrf_spim_rx_list_enable(NRF_SPIM_Type * p_reg)
1485 {
1486 p_reg->RXD.LIST = SPIM_RXD_LIST_LIST_ArrayList << SPIM_RXD_LIST_LIST_Pos;
1487 }
1488
nrf_spim_rx_list_disable(NRF_SPIM_Type * p_reg)1489 NRF_STATIC_INLINE void nrf_spim_rx_list_disable(NRF_SPIM_Type * p_reg)
1490 {
1491 p_reg->RXD.LIST = SPIM_RXD_LIST_LIST_Disabled << SPIM_RXD_LIST_LIST_Pos;
1492 }
1493 #endif
1494
1495 #if NRF_SPIM_HAS_DMA_TASKS_EVENTS
nrf_spim_rx_pattern_match_enable_set(NRF_SPIM_Type * p_reg,uint8_t index,bool enable)1496 NRF_STATIC_INLINE void nrf_spim_rx_pattern_match_enable_set(NRF_SPIM_Type * p_reg,
1497 uint8_t index,
1498 bool enable)
1499 {
1500 NRFX_ASSERT(index < NRF_SPIM_DMA_RX_PATTERN_MAX_COUNT);
1501 switch (index)
1502 {
1503 case 0:
1504 p_reg->DMA.RX.MATCH.CONFIG = ((p_reg->DMA.RX.MATCH.CONFIG &
1505 ~SPIM_DMA_RX_MATCH_CONFIG_ENABLE0_Msk) |
1506 ((enable ?
1507 SPIM_DMA_RX_MATCH_CONFIG_ENABLE0_Enabled :
1508 SPIM_DMA_RX_MATCH_CONFIG_ENABLE0_Disabled)
1509 << SPIM_DMA_RX_MATCH_CONFIG_ENABLE0_Pos));
1510 break;
1511 case 1:
1512 p_reg->DMA.RX.MATCH.CONFIG = ((p_reg->DMA.RX.MATCH.CONFIG &
1513 ~SPIM_DMA_RX_MATCH_CONFIG_ENABLE1_Msk) |
1514 ((enable ?
1515 SPIM_DMA_RX_MATCH_CONFIG_ENABLE1_Enabled :
1516 SPIM_DMA_RX_MATCH_CONFIG_ENABLE1_Disabled)
1517 << SPIM_DMA_RX_MATCH_CONFIG_ENABLE1_Pos));
1518 break;
1519 case 2:
1520 p_reg->DMA.RX.MATCH.CONFIG = ((p_reg->DMA.RX.MATCH.CONFIG &
1521 ~SPIM_DMA_RX_MATCH_CONFIG_ENABLE2_Msk) |
1522 ((enable ?
1523 SPIM_DMA_RX_MATCH_CONFIG_ENABLE2_Enabled :
1524 SPIM_DMA_RX_MATCH_CONFIG_ENABLE2_Disabled)
1525 << SPIM_DMA_RX_MATCH_CONFIG_ENABLE2_Pos));
1526 break;
1527 case 3:
1528 p_reg->DMA.RX.MATCH.CONFIG = ((p_reg->DMA.RX.MATCH.CONFIG &
1529 ~SPIM_DMA_RX_MATCH_CONFIG_ENABLE3_Msk) |
1530 ((enable ?
1531 SPIM_DMA_RX_MATCH_CONFIG_ENABLE3_Enabled :
1532 SPIM_DMA_RX_MATCH_CONFIG_ENABLE3_Disabled)
1533 << SPIM_DMA_RX_MATCH_CONFIG_ENABLE3_Pos));
1534 break;
1535 default:
1536 NRFX_ASSERT(false);
1537 break;
1538 }
1539 }
1540
nrf_spim_rx_pattern_match_enable_check(NRF_SPIM_Type const * p_reg,uint8_t index)1541 NRF_STATIC_INLINE bool nrf_spim_rx_pattern_match_enable_check(NRF_SPIM_Type const * p_reg,
1542 uint8_t index)
1543 {
1544 NRFX_ASSERT(index < NRF_SPIM_DMA_RX_PATTERN_MAX_COUNT);
1545 switch (index)
1546 {
1547 case 0:
1548 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIM_DMA_RX_MATCH_CONFIG_ENABLE0_Msk)
1549 >> SPIM_DMA_RX_MATCH_CONFIG_ENABLE0_Pos) ==
1550 SPIM_DMA_RX_MATCH_CONFIG_ENABLE0_Enabled;
1551 case 1:
1552 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIM_DMA_RX_MATCH_CONFIG_ENABLE1_Msk)
1553 >> SPIM_DMA_RX_MATCH_CONFIG_ENABLE1_Pos) ==
1554 SPIM_DMA_RX_MATCH_CONFIG_ENABLE1_Enabled;
1555 case 2:
1556 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIM_DMA_RX_MATCH_CONFIG_ENABLE2_Msk)
1557 >> SPIM_DMA_RX_MATCH_CONFIG_ENABLE2_Pos) ==
1558 SPIM_DMA_RX_MATCH_CONFIG_ENABLE2_Enabled;
1559 case 3:
1560 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIM_DMA_RX_MATCH_CONFIG_ENABLE3_Msk)
1561 >> SPIM_DMA_RX_MATCH_CONFIG_ENABLE3_Pos) ==
1562 SPIM_DMA_RX_MATCH_CONFIG_ENABLE3_Enabled;
1563 default:
1564 NRFX_ASSERT(false);
1565 return 0;
1566 }
1567 }
1568
nrf_spim_rx_pattern_match_one_shot_enable(NRF_SPIM_Type * p_reg,uint8_t index)1569 NRF_STATIC_INLINE void nrf_spim_rx_pattern_match_one_shot_enable(NRF_SPIM_Type * p_reg,
1570 uint8_t index)
1571 {
1572 NRFX_ASSERT(index < NRF_SPIM_DMA_RX_PATTERN_MAX_COUNT);
1573 switch (index)
1574 {
1575 case 0:
1576 p_reg->DMA.RX.MATCH.CONFIG |= SPIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Msk;
1577 break;
1578 case 1:
1579 p_reg->DMA.RX.MATCH.CONFIG |= SPIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Msk;
1580 break;
1581 case 2:
1582 p_reg->DMA.RX.MATCH.CONFIG |= SPIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Msk;
1583 break;
1584 case 3:
1585 p_reg->DMA.RX.MATCH.CONFIG |= SPIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Msk;
1586 break;
1587 default:
1588 NRFX_ASSERT(false);
1589 break;
1590 }
1591 }
1592
nrf_spim_rx_pattern_match_one_shot_disable(NRF_SPIM_Type * p_reg,uint8_t index)1593 NRF_STATIC_INLINE void nrf_spim_rx_pattern_match_one_shot_disable(NRF_SPIM_Type * p_reg,
1594 uint8_t index)
1595 {
1596 NRFX_ASSERT(index < NRF_SPIM_DMA_RX_PATTERN_MAX_COUNT);
1597 switch (index)
1598 {
1599 case 0:
1600 p_reg->DMA.RX.MATCH.CONFIG &= ~(SPIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Msk);
1601 break;
1602 case 1:
1603 p_reg->DMA.RX.MATCH.CONFIG &= ~(SPIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Msk);
1604 break;
1605 case 2:
1606 p_reg->DMA.RX.MATCH.CONFIG &= ~(SPIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Msk);
1607 break;
1608 case 3:
1609 p_reg->DMA.RX.MATCH.CONFIG &= ~(SPIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Msk);
1610 break;
1611 default:
1612 NRFX_ASSERT(false);
1613 break;
1614 }
1615 }
1616
nrf_spim_rx_pattern_match_one_shot_check(NRF_SPIM_Type const * p_reg,uint8_t index)1617 NRF_STATIC_INLINE bool nrf_spim_rx_pattern_match_one_shot_check(NRF_SPIM_Type const * p_reg,
1618 uint8_t index)
1619 {
1620 NRFX_ASSERT(index < NRF_SPIM_DMA_RX_PATTERN_MAX_COUNT);
1621 switch (index)
1622 {
1623 case 0:
1624 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Msk)
1625 >> SPIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Pos) ==
1626 SPIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Oneshot;
1627 case 1:
1628 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Msk)
1629 >> SPIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Pos) ==
1630 SPIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Oneshot;
1631 case 2:
1632 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Msk)
1633 >> SPIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Pos) ==
1634 SPIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Oneshot;
1635 case 3:
1636 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Msk)
1637 >> SPIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Pos) ==
1638 SPIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Oneshot;
1639 default:
1640 NRFX_ASSERT(false);
1641 return 0;
1642 }
1643 }
1644
nrf_spim_rx_pattern_match_candidate_set(NRF_SPIM_Type * p_reg,uint8_t index,uint32_t pattern)1645 NRF_STATIC_INLINE void nrf_spim_rx_pattern_match_candidate_set(NRF_SPIM_Type * p_reg,
1646 uint8_t index,
1647 uint32_t pattern)
1648 {
1649 NRFX_ASSERT(index < NRF_SPIM_DMA_RX_PATTERN_MAX_COUNT);
1650 p_reg->DMA.RX.MATCH.CANDIDATE[index] = pattern;
1651 }
1652
nrf_spim_rx_pattern_match_candidate_get(NRF_SPIM_Type const * p_reg,uint8_t index)1653 NRF_STATIC_INLINE uint32_t nrf_spim_rx_pattern_match_candidate_get(NRF_SPIM_Type const * p_reg,
1654 uint8_t index)
1655 {
1656 NRFX_ASSERT(index < NRF_SPIM_DMA_RX_PATTERN_MAX_COUNT);
1657 return p_reg->DMA.RX.MATCH.CANDIDATE[index];
1658 }
1659 #endif // NRF_SPIM_HAS_DMA_TASKS_EVENTS
1660
1661 #if NRF_SPIM_HAS_DMA_REG
nrf_spim_rx_terminate_on_bus_error_enable(NRF_SPIM_Type * p_reg)1662 NRF_STATIC_INLINE void nrf_spim_rx_terminate_on_bus_error_enable(NRF_SPIM_Type * p_reg)
1663 {
1664 p_reg->DMA.RX.TERMINATEONBUSERROR |= SPIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Msk;
1665 }
1666
nrf_spim_rx_terminate_on_bus_error_disable(NRF_SPIM_Type * p_reg)1667 NRF_STATIC_INLINE void nrf_spim_rx_terminate_on_bus_error_disable(NRF_SPIM_Type * p_reg)
1668 {
1669 p_reg->DMA.RX.TERMINATEONBUSERROR &= ~(SPIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Msk);
1670 }
1671
nrf_spim_rx_terminate_on_bus_error_check(NRF_SPIM_Type const * p_reg)1672 NRF_STATIC_INLINE bool nrf_spim_rx_terminate_on_bus_error_check(NRF_SPIM_Type const * p_reg)
1673 {
1674 return ((p_reg->DMA.RX.TERMINATEONBUSERROR & SPIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Msk)
1675 >> SPIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos) ==
1676 SPIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Enabled;
1677 }
1678
nrf_spim_tx_terminate_on_bus_error_enable(NRF_SPIM_Type * p_reg)1679 NRF_STATIC_INLINE void nrf_spim_tx_terminate_on_bus_error_enable(NRF_SPIM_Type * p_reg)
1680 {
1681 p_reg->DMA.TX.TERMINATEONBUSERROR |= SPIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Msk;
1682 }
1683
nrf_spim_tx_terminate_on_bus_error_disable(NRF_SPIM_Type * p_reg)1684 NRF_STATIC_INLINE void nrf_spim_tx_terminate_on_bus_error_disable(NRF_SPIM_Type * p_reg)
1685 {
1686 p_reg->DMA.TX.TERMINATEONBUSERROR &= ~(SPIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Msk);
1687 }
1688
nrf_spim_tx_terminate_on_bus_error_check(NRF_SPIM_Type const * p_reg)1689 NRF_STATIC_INLINE bool nrf_spim_tx_terminate_on_bus_error_check(NRF_SPIM_Type const * p_reg)
1690 {
1691 return ((p_reg->DMA.TX.TERMINATEONBUSERROR & SPIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Msk)
1692 >> SPIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos) ==
1693 SPIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Enabled;
1694 }
1695 #endif // NRF_SPIM_HAS_DMA_REG
1696
1697 #endif // NRF_DECLARE_ONLY
1698
1699 /** @} */
1700
1701 #ifdef __cplusplus
1702 }
1703 #endif
1704
1705 #endif // NRF_SPIM_H__
1706
