1 /*
2 * Copyright (c) 2023 - 2024, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_RRAMC_H__
35 #define NRF_RRAMC_H__
36
37 #include <nrfx.h>
38 #include <nrf_bitmask.h>
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 /**
45 * @defgroup nrf_rramc_hal RRAMC HAL
46 * @{
47 * @ingroup nrf_rramc
48 * @brief Hardware access layer for managing the the Resistive Random Access Memory Controller (RRAMC) peripheral.
49 */
50
51 /** @brief Maximum size of a write-buffer in number of 128-bit words. */
52 #define NRF_RRAMC_CONFIG_WRITE_BUFF_SIZE_MAX RRAMC_CONFIG_WRITEBUFSIZE_Max
53
54 /** @brief Maximum preload timeout value for waiting for a next write. */
55 #define NRF_RRAMC_READYNEXTTIMEOUT_MAX RRAMC_READYNEXTTIMEOUT_VALUE_Max
56
57 /** @brief RRAMC region permissions bitmask. */
58 #define NRF_RRAMC_REGION_CONFIG_PERM_MASK (RRAMC_REGION_CONFIG_READ_Msk | \
59 RRAMC_REGION_CONFIG_WRITE_Msk | \
60 RRAMC_REGION_CONFIG_EXECUTE_Msk | \
61 RRAMC_REGION_CONFIG_SECURE_Msk)
62
63 /** @brief RRAMC tasks. */
64 typedef enum
65 {
66 NRF_RRAMC_TASK_WAKEUP = offsetof(NRF_RRAMC_Type, TASKS_WAKEUP), ///< Wakeup the RRAM from low power mode.
67 NRF_RRAMC_TASK_COMMIT_WRITEBUF = offsetof(NRF_RRAMC_Type, TASKS_COMMITWRITEBUF), ///< Commit the data stored in internal write-buffer to RRAM.
68 } nrf_rramc_task_t;
69
70 /** @brief RRAMC events. */
71 typedef enum
72 {
73 NRF_RRAMC_EVENT_WOKENUP = offsetof(NRF_RRAMC_Type, EVENTS_WOKENUP), ///< The RRAM is woken up from low power mode.
74 NRF_RRAMC_EVENT_READY = offsetof(NRF_RRAMC_Type, EVENTS_READY), ///< RRAMC is ready.
75 NRF_RRAMC_EVENT_READY_NEXT = offsetof(NRF_RRAMC_Type, EVENTS_READYNEXT), ///< Ready to accept a new write operation.
76 NRF_RRAMC_EVENT_ERROR_ACCESS = offsetof(NRF_RRAMC_Type, EVENTS_ACCESSERROR), ///< RRAM access error.
77 } nrf_rramc_event_t;
78
79 /** @brief RRAMC interrupts. */
80 typedef enum
81 {
82 NRF_RRAMC_INT_WOKENUP_MASK = RRAMC_INTENSET_WOKENUP_Msk, ///< Interrupt on WOKENUP event.
83 NRF_RRAMC_INT_READY_MASK = RRAMC_INTENSET_READY_Msk, ///< Interrupt on READY event.
84 NRF_RRAMC_INT_READY_NEXT_MASK = RRAMC_INTENSET_READYNEXT_Msk, ///< Interrupt on READYNEXT event.
85 NRF_RRAMC_INT_ERROR_ACCESS_MASK = RRAMC_INTENSET_ACCESSERROR_Msk, ///< Interrupt on ACCESSERROR event.
86 NRF_RRAMC_ALL_INTS_MASK = NRF_RRAMC_INT_WOKENUP_MASK
87 | NRF_RRAMC_INT_READY_MASK
88 | NRF_RRAMC_INT_READY_NEXT_MASK
89 | NRF_RRAMC_INT_ERROR_ACCESS_MASK ///< All RRAMC interrupts.
90 } nrf_rramc_int_mask_t;
91
92 /** @brief RRAMC configuration structure. */
93 typedef struct
94 {
95 bool mode_write; ///< True if write mode is to be enabled, false otherwise.
96 uint8_t write_buff_size; ///< Write-buffer size in case set to 0 buffering is disabled.
97 } nrf_rramc_config_t;
98
99 /** @brief Preload timeout value for waiting for a next write. */
100 typedef struct
101 {
102 uint16_t value; ///< Preload value expressed in clock cycles.
103 bool enable; ///< True if write to the RRAM is to be triggered on the next timeout, false otherwise.
104 } nrf_rramc_ready_next_timeout_t;
105
106 /** @brief Power configuration. */
107 typedef struct
108 {
109 uint16_t access_timeout; ///< Access timeout used for going into standby power mode or remain active on wake up, expressed in clock cycles.
110 bool abort_on_pof; ///< True if the current RRAM write operation is to be aborted on the power failure, false otherwise.
111 } nrf_rramc_power_t;
112
113 /**
114 * @brief RRAMC region permissions mask.
115 *
116 * @note When bit is set, the selected action is allowed.
117 */
118 typedef enum
119 {
120 NRF_RRAMC_REGION_PERM_READ_MASK = RRAMC_REGION_CONFIG_READ_Msk, ///< Read access.
121 NRF_RRAMC_REGION_PERM_WRITE_MASK = RRAMC_REGION_CONFIG_WRITE_Msk, ///< Write access.
122 NRF_RRAMC_REGION_PERM_EXECUTE_MASK = RRAMC_REGION_CONFIG_EXECUTE_Msk, ///< Software execute.
123 NRF_RRAMC_REGION_PERM_SECURE_MASK = RRAMC_REGION_CONFIG_SECURE_Msk, ///< Secure-only access.
124 } nrf_rramc_region_perm_mask_t;
125
126 /** @brief RRAMC region configuration. */
127 typedef struct
128 {
129 uint32_t address; ///< Start address of the region.
130 uint32_t permissions; ///< Permissions created using @ref nrf_rramc_region_perm_mask_t.
131 bool writeonce; ///< True if writes to the region are to be applied only when the current data is 0xFFFFFFFF.
132 bool lock; ///< True if memory belonging to given region is to be read-only.
133 uint16_t size_kb; ///< Region size in kBs. */
134 } nrf_rramc_region_config_t;
135
136 /**
137 * @brief Function for activating the specified RRAMC task.
138 *
139 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
140 * @param[in] task Task to be activated.
141 */
142 NRF_STATIC_INLINE void nrf_rramc_task_trigger(NRF_RRAMC_Type * p_reg, nrf_rramc_task_t task);
143
144 /**
145 * @brief Function for getting the address of the specified RRAMC task register.
146 *
147 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
148 * @param[in] task RRAMC task.
149 *
150 * @return Address of the specified task register.
151 */
152 NRF_STATIC_INLINE uint32_t nrf_rramc_task_address_get(NRF_RRAMC_Type const * p_reg,
153 nrf_rramc_task_t task);
154
155 /**
156 * @brief Function for clearing the specified RRAMC event.
157 *
158 * @param[in] p_reg Pointer to the peripheral register structure.
159 * @param[in] event Event to clear.
160 */
161 NRF_STATIC_INLINE void nrf_rramc_event_clear(NRF_RRAMC_Type * p_reg, nrf_rramc_event_t event);
162
163 /**
164 * @brief Function for retrieving the state of the RRAMC event.
165 *
166 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
167 * @param[in] event Event to be checked.
168 *
169 * @retval true The event has been generated.
170 * @retval false The event has not been generated.
171 */
172 NRF_STATIC_INLINE bool nrf_rramc_event_check(NRF_RRAMC_Type const * p_reg, nrf_rramc_event_t event);
173
174 /**
175 * @brief Function for getting the address of the specified RRAMC event register.
176 *
177 * @param[in] p_reg Pointer to the peripheral register structure.
178 * @param[in] event Requested event.
179 *
180 * @return Address of the specified event register.
181 */
182 NRF_STATIC_INLINE uint32_t nrf_rramc_event_address_get(NRF_RRAMC_Type const * p_reg,
183 nrf_rramc_event_t event);
184
185 /**
186 * @brief Function for enabling the specified interrupts.
187 *
188 * @param[in] p_reg Pointer to the peripheral register structure.
189 * @param[in] mask Mask of interrupts to be enabled.
190 * Use @ref nrf_rramc_int_mask_t values for bit masking.
191 */
192 NRF_STATIC_INLINE void nrf_rramc_int_enable(NRF_RRAMC_Type * p_reg, uint32_t mask);
193
194 /**
195 * @brief Function for disabling the specified interrupts.
196 *
197 * @param[in] p_reg Pointer to the peripheral register structure.
198 * @param[in] mask Mask of interrupts to be disabled.
199 * Use @ref nrf_rramc_int_mask_t values for bit masking.
200 */
201 NRF_STATIC_INLINE void nrf_rramc_int_disable(NRF_RRAMC_Type * p_reg, uint32_t mask);
202
203 /**
204 * @brief Function for checking if the specified interrupts are enabled.
205 *
206 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
207 * @param[in] mask Mask of interrupts to be checked.
208 * Use @ref nrf_rramc_int_mask_t values for bit masking.
209 *
210 * @return Mask of enabled interrupts.
211 */
212 NRF_STATIC_INLINE uint32_t nrf_rramc_int_enable_check(NRF_RRAMC_Type const * p_reg, uint32_t mask);
213
214 /**
215 * @brief Function for getting the state of pending interrupts.
216 *
217 * @note States of pending interrupt are saved as a bitmask.
218 * One set at particular position means that interrupt for event is pending.
219 *
220 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
221 *
222 * @return Bitmask with information about pending interrupts.
223 * Use @ref nrf_rramc_int_mask_t values for bit masking.
224 */
225 NRF_STATIC_INLINE uint32_t nrf_rramc_int_pending_get(NRF_RRAMC_Type const * p_reg);
226
227 #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
228 /**
229 * @brief Function for setting the subscribe configuration for a wakeup
230 * RRAMC task.
231 *
232 * @note Not every task has its corresponding subscribe register.
233 * Refer to the Product Specification for more information.
234 *
235 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
236 * @param[in] task Task for which to set the configuration.
237 * @param[in] channel Channel through which to subscribe events.
238 */
239 NRF_STATIC_INLINE void nrf_rramc_subscribe_set(NRF_RRAMC_Type * p_reg,
240 nrf_rramc_task_t task,
241 uint8_t channel);
242
243 /**
244 * @brief Function for clearing the subscribe configuration for a wakeup
245 * RRAMC task.
246 *
247 * @note Not every task has its corresponding subscribe register.
248 * Refer to the Product Specification for more information.
249 *
250 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
251 * @param[in] task Task for which to clear the configuration.
252 */
253 NRF_STATIC_INLINE void nrf_rramc_subscribe_clear(NRF_RRAMC_Type * p_reg, nrf_rramc_task_t task);
254
255 /**
256 * @brief Function for setting the publish configuration for a wokenup
257 * RRAMC event.
258 *
259 * @note Not every event has its corresponding publish register.
260 * Refer to the Product Specification for more information.
261 *
262 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
263 * @param[in] event Event for which to set the configuration.
264 * @param[in] channel Channel through which to publish the event.
265 */
266 NRF_STATIC_INLINE void nrf_rramc_publish_set(NRF_RRAMC_Type * p_reg,
267 nrf_rramc_event_t event,
268 uint8_t channel);
269
270 /**
271 * @brief Function for clearing the publish configuration for a wokenup
272 * RRAMC event.
273 *
274 * @note Not every event has its corresponding publish register.
275 * Refer to the Product Specification for more information.
276 *
277 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
278 * @param[in] event Event for which to clear the configuration.
279 */
280 NRF_STATIC_INLINE void nrf_rramc_publish_clear(NRF_RRAMC_Type * p_reg, nrf_rramc_event_t event);
281
282 #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
283
284 /**
285 * @brief Function for checking current RRAMC operation status.
286 *
287 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
288 *
289 * @retval true Current operation is completed, and RRAMC is ready.
290 * @retval false RRAMC is busy.
291 */
292 NRF_STATIC_INLINE bool nrf_rramc_ready_check(NRF_RRAMC_Type const * p_reg);
293
294 /**
295 * @brief Function for checking whether RRAMC is ready to accept a new write operation.
296 *
297 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
298 *
299 * @retval true RRAMC is ready to accept a new write operation.
300 * @retval false RRAMC cannot accept any write operation now.
301 */
302 NRF_STATIC_INLINE bool nrf_rramc_write_ready_check(NRF_RRAMC_Type const * p_reg);
303
304 /**
305 * @brief Fuction for checking the address of the first access error.
306 *
307 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
308 *
309 * @return Access error address.
310 */
311 NRF_STATIC_INLINE uint32_t nrf_rramc_error_access_addr_get(NRF_RRAMC_Type const * p_reg);
312
313 /**
314 * @brief Function for checking whether the internal write-buffer has been committed to RRAM and is now empty.
315 *
316 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
317 *
318 * @retval true The internal write-buffer is empty and has no content that needs to be commited.
319 * @retval false The internal write-buffer has data that needs to be committed.
320 */
321 NRF_STATIC_INLINE bool nrf_rramc_empty_buffer_check(NRF_RRAMC_Type const * p_reg);
322
323 /**
324 * @brief Function for getting the RRAMC peripheral configuration.
325 *
326 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
327 * @param[out] p_config Pointer to the structure to be filled with RRAMC configuration data.
328 */
329 NRF_STATIC_INLINE void nrf_rramc_config_get(NRF_RRAMC_Type const * p_reg,
330 nrf_rramc_config_t * p_config);
331
332 /**
333 * @brief Function for setting the RRAMC peripheral configuration.
334 *
335 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
336 * @param[in] p_config Pointer to the structure with configuration to be set.
337 */
338 NRF_STATIC_INLINE void nrf_rramc_config_set(NRF_RRAMC_Type * p_reg,
339 nrf_rramc_config_t const * p_config);
340
341 /**
342 * @brief Function for getting preload timeout value for waiting for a next write.
343 *
344 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
345 * @param[out] p_config Pointer to the structure to be filled with information about
346 * preload timeout value.
347 */
348 NRF_STATIC_INLINE void nrf_rramc_ready_next_timeout_get(NRF_RRAMC_Type const * p_reg,
349 nrf_rramc_ready_next_timeout_t * p_config);
350
351 /**
352 * @brief Function for setting preload timeout value for waiting for a next write.
353 *
354 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
355 * @param[in] p_config Pointer to the structure filled with information about$ preload
356 * timeout value.
357 */
358 NRF_STATIC_INLINE
359 void nrf_rramc_ready_next_timeout_set(NRF_RRAMC_Type * p_reg,
360 nrf_rramc_ready_next_timeout_t const * p_config);
361
362 /**
363 * @brief Function for getting the RRAMC power configuration.
364 *
365 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
366 * @param[out] p_config Pointer to the structure to be filled with information about
367 * power configuration.
368 */
369 NRF_STATIC_INLINE void nrf_rramc_power_config_get(NRF_RRAMC_Type const * p_reg,
370 nrf_rramc_power_t * p_config);
371
372 /**
373 * @brief Function for setting the RRAMC power configuration.
374 *
375 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
376 * @param[in] p_config Pointer to the structure filled with information about power configuration.
377 */
378 NRF_STATIC_INLINE void nrf_rramc_power_config_set(NRF_RRAMC_Type * p_reg,
379 nrf_rramc_power_t const * p_config);
380
381 /**
382 * @brief Function for checking if the erasing operation of the whole RRAM main block has been started.
383 *
384 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
385 *
386 * @retval true Erase of chip started.
387 * @retval false No operation.
388 */
389 NRF_STATIC_INLINE bool nrf_rramc_erase_all_check(NRF_RRAMC_Type const * p_reg);
390
391 /**
392 * @brief Function for erasing whole RRAM main block, that includes the SICR and the UICR.
393 *
394 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
395 */
396 NRF_STATIC_INLINE void nrf_rramc_erase_all_set(NRF_RRAMC_Type * p_reg);
397
398 /**
399 * @brief Function for setting the configuration of the specified RRAMC region.
400 *
401 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
402 * @param[in] region Region number.
403 * @param[in] p_config Pointer to the configuration structure.
404 */
405 NRF_STATIC_INLINE void nrf_rramc_region_config_set(NRF_RRAMC_Type * p_reg,
406 uint8_t region,
407 nrf_rramc_region_config_t const * p_config);
408
409 /**
410 * @brief Function for getting the configuration of the specified RRAMC region.
411 *
412 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
413 * @param[in] region Region number.
414 * @param[in] p_config Pointer to the structure to be filled with RRAMC region settings.
415 */
416 NRF_STATIC_INLINE void nrf_rramc_region_config_get(NRF_RRAMC_Type const * p_reg,
417 uint8_t region,
418 nrf_rramc_region_config_t * p_config);
419
420 /**
421 * @brief Function for getting the raw configuration of the specified RRAMC region.
422 *
423 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
424 * @param[in] region Region number.
425 *
426 * @return Raw configuration.
427 */
428 NRF_STATIC_INLINE uint32_t nrf_rramc_region_config_raw_get(NRF_RRAMC_Type const * p_reg,
429 uint8_t region);
430
431 #ifndef NRF_DECLARE_ONLY
432
nrf_rramc_task_trigger(NRF_RRAMC_Type * p_reg,nrf_rramc_task_t task)433 NRF_STATIC_INLINE void nrf_rramc_task_trigger(NRF_RRAMC_Type * p_reg, nrf_rramc_task_t task)
434 {
435 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
436 }
437
nrf_rramc_task_address_get(NRF_RRAMC_Type const * p_reg,nrf_rramc_task_t task)438 NRF_STATIC_INLINE uint32_t nrf_rramc_task_address_get(NRF_RRAMC_Type const * p_reg,
439 nrf_rramc_task_t task)
440 {
441 return ((uint32_t)p_reg + (uint32_t)task);
442 }
443
nrf_rramc_event_clear(NRF_RRAMC_Type * p_reg,nrf_rramc_event_t event)444 NRF_STATIC_INLINE void nrf_rramc_event_clear(NRF_RRAMC_Type * p_reg, nrf_rramc_event_t event)
445 {
446 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
447 nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
448 }
449
nrf_rramc_event_check(NRF_RRAMC_Type const * p_reg,nrf_rramc_event_t event)450 NRF_STATIC_INLINE bool nrf_rramc_event_check(NRF_RRAMC_Type const * p_reg, nrf_rramc_event_t event)
451 {
452 return nrf_event_check(p_reg, event);
453 }
454
nrf_rramc_event_address_get(NRF_RRAMC_Type const * p_reg,nrf_rramc_event_t event)455 NRF_STATIC_INLINE uint32_t nrf_rramc_event_address_get(NRF_RRAMC_Type const * p_reg,
456 nrf_rramc_event_t event)
457 {
458 return ((uint32_t)p_reg + (uint32_t)event);
459 }
460
nrf_rramc_int_enable(NRF_RRAMC_Type * p_reg,uint32_t mask)461 NRF_STATIC_INLINE void nrf_rramc_int_enable(NRF_RRAMC_Type * p_reg, uint32_t mask)
462 {
463 p_reg->INTENSET = mask;
464 }
465
nrf_rramc_int_disable(NRF_RRAMC_Type * p_reg,uint32_t mask)466 NRF_STATIC_INLINE void nrf_rramc_int_disable(NRF_RRAMC_Type * p_reg, uint32_t mask)
467 {
468 p_reg->INTENCLR = mask;
469 }
470
nrf_rramc_int_enable_check(NRF_RRAMC_Type const * p_reg,uint32_t mask)471 NRF_STATIC_INLINE uint32_t nrf_rramc_int_enable_check(NRF_RRAMC_Type const * p_reg,
472 uint32_t mask)
473 {
474 return p_reg->INTENSET & mask;
475 }
476
nrf_rramc_int_pending_get(NRF_RRAMC_Type const * p_reg)477 NRF_STATIC_INLINE uint32_t nrf_rramc_int_pending_get(NRF_RRAMC_Type const * p_reg)
478 {
479 return p_reg->INTPEND;
480 }
481
482 #if defined(DPPI_PRESENT)
nrf_rramc_subscribe_set(NRF_RRAMC_Type * p_reg,nrf_rramc_task_t task,uint8_t channel)483 NRF_STATIC_INLINE void nrf_rramc_subscribe_set(NRF_RRAMC_Type * p_reg,
484 nrf_rramc_task_t task,
485 uint8_t channel)
486 {
487 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
488 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
489 }
490
nrf_rramc_subscribe_clear(NRF_RRAMC_Type * p_reg,nrf_rramc_task_t task)491 NRF_STATIC_INLINE void nrf_rramc_subscribe_clear(NRF_RRAMC_Type * p_reg, nrf_rramc_task_t task)
492 {
493 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
494 }
495
nrf_rramc_publish_set(NRF_RRAMC_Type * p_reg,nrf_rramc_event_t event,uint8_t channel)496 NRF_STATIC_INLINE void nrf_rramc_publish_set(NRF_RRAMC_Type * p_reg,
497 nrf_rramc_event_t event,
498 uint8_t channel)
499 {
500 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
501 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
502 }
503
nrf_rramc_publish_clear(NRF_RRAMC_Type * p_reg,nrf_rramc_event_t event)504 NRF_STATIC_INLINE void nrf_rramc_publish_clear(NRF_RRAMC_Type * p_reg, nrf_rramc_event_t event)
505 {
506 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
507 }
508 #endif // defined(DPPI_PRESENT)
509
nrf_rramc_ready_check(NRF_RRAMC_Type const * p_reg)510 NRF_STATIC_INLINE bool nrf_rramc_ready_check(NRF_RRAMC_Type const * p_reg)
511 {
512 return ((p_reg->READY & RRAMC_READY_READY_Msk) >>
513 RRAMC_READY_READY_Pos) ==
514 RRAMC_READY_READY_Ready;
515 }
516
nrf_rramc_write_ready_check(NRF_RRAMC_Type const * p_reg)517 NRF_STATIC_INLINE bool nrf_rramc_write_ready_check(NRF_RRAMC_Type const * p_reg)
518 {
519 return ((p_reg->READYNEXT & RRAMC_READYNEXT_READYNEXT_Msk) >>
520 RRAMC_READYNEXT_READYNEXT_Pos) ==
521 RRAMC_READYNEXT_READYNEXT_Ready;
522 }
523
nrf_rramc_error_access_addr_get(NRF_RRAMC_Type const * p_reg)524 NRF_STATIC_INLINE uint32_t nrf_rramc_error_access_addr_get(NRF_RRAMC_Type const * p_reg)
525 {
526 return (uint32_t)p_reg->ACCESSERRORADDR;
527 }
528
nrf_rramc_empty_buffer_check(NRF_RRAMC_Type const * p_reg)529 NRF_STATIC_INLINE bool nrf_rramc_empty_buffer_check(NRF_RRAMC_Type const * p_reg)
530 {
531 return ((p_reg->BUFSTATUS.WRITEBUFEMPTY & RRAMC_BUFSTATUS_WRITEBUFEMPTY_EMPTY_Msk) >>
532 RRAMC_BUFSTATUS_WRITEBUFEMPTY_EMPTY_Pos) ==
533 RRAMC_BUFSTATUS_WRITEBUFEMPTY_EMPTY_Empty;
534 }
535
nrf_rramc_config_get(NRF_RRAMC_Type const * p_reg,nrf_rramc_config_t * p_config)536 NRF_STATIC_INLINE void nrf_rramc_config_get(NRF_RRAMC_Type const * p_reg,
537 nrf_rramc_config_t * p_config)
538 {
539 p_config->mode_write = (bool)((p_reg->CONFIG & RRAMC_CONFIG_WEN_Msk) >>
540 RRAMC_CONFIG_WEN_Pos);
541 p_config->write_buff_size = (uint32_t)((p_reg->CONFIG & RRAMC_CONFIG_WRITEBUFSIZE_Msk) >>
542 RRAMC_CONFIG_WRITEBUFSIZE_Pos);
543 }
544
nrf_rramc_config_set(NRF_RRAMC_Type * p_reg,nrf_rramc_config_t const * p_config)545 NRF_STATIC_INLINE void nrf_rramc_config_set(NRF_RRAMC_Type * p_reg,
546 nrf_rramc_config_t const * p_config)
547 {
548 NRFX_ASSERT(p_config->write_buff_size <= NRF_RRAMC_CONFIG_WRITE_BUFF_SIZE_MAX);
549
550 p_reg->CONFIG = ((uint32_t)p_config->mode_write << RRAMC_CONFIG_WEN_Pos) |
551 ((uint32_t)p_config->write_buff_size << RRAMC_CONFIG_WRITEBUFSIZE_Pos);
552 }
553
nrf_rramc_ready_next_timeout_get(NRF_RRAMC_Type const * p_reg,nrf_rramc_ready_next_timeout_t * p_config)554 NRF_STATIC_INLINE void nrf_rramc_ready_next_timeout_get(NRF_RRAMC_Type const * p_reg,
555 nrf_rramc_ready_next_timeout_t * p_config)
556 {
557 p_config->value = (uint16_t)((p_reg->READYNEXTTIMEOUT & RRAMC_READYNEXTTIMEOUT_VALUE_Msk) >>
558 RRAMC_READYNEXTTIMEOUT_VALUE_Pos);
559 p_config->enable = ((p_reg->READYNEXTTIMEOUT & RRAMC_READYNEXTTIMEOUT_EN_Msk)
560 >> RRAMC_READYNEXTTIMEOUT_EN_Pos) == RRAMC_READYNEXTTIMEOUT_EN_Enable;
561 }
562
563 NRF_STATIC_INLINE void
nrf_rramc_ready_next_timeout_set(NRF_RRAMC_Type * p_reg,nrf_rramc_ready_next_timeout_t const * p_config)564 nrf_rramc_ready_next_timeout_set(NRF_RRAMC_Type * p_reg,
565 nrf_rramc_ready_next_timeout_t const * p_config)
566 {
567 NRFX_ASSERT(p_config->value <= NRF_RRAMC_READYNEXTTIMEOUT_MAX);
568
569 p_reg->READYNEXTTIMEOUT = ((uint32_t)p_config->value << RRAMC_READYNEXTTIMEOUT_VALUE_Pos) |
570 ((p_config->enable ? RRAMC_READYNEXTTIMEOUT_EN_Enable :
571 RRAMC_READYNEXTTIMEOUT_EN_Disable)
572 << RRAMC_READYNEXTTIMEOUT_EN_Pos);
573 }
574
nrf_rramc_power_config_get(NRF_RRAMC_Type const * p_reg,nrf_rramc_power_t * p_config)575 NRF_STATIC_INLINE void nrf_rramc_power_config_get(NRF_RRAMC_Type const * p_reg,
576 nrf_rramc_power_t * p_config)
577 {
578 p_config->access_timeout = (uint16_t)((p_reg->POWER.CONFIG &
579 RRAMC_POWER_CONFIG_ACCESSTIMEOUT_Msk) >>
580 RRAMC_POWER_CONFIG_ACCESSTIMEOUT_Pos);
581 p_config->abort_on_pof = ((p_reg->POWER.CONFIG &
582 RRAMC_POWER_CONFIG_POF_Msk) >>
583 RRAMC_POWER_CONFIG_POF_Pos) ==
584 RRAMC_POWER_CONFIG_POF_Abort;
585 }
586
nrf_rramc_power_config_set(NRF_RRAMC_Type * p_reg,nrf_rramc_power_t const * p_config)587 NRF_STATIC_INLINE void nrf_rramc_power_config_set(NRF_RRAMC_Type * p_reg,
588 nrf_rramc_power_t const * p_config)
589 {
590 p_reg->POWER.CONFIG =
591 ((uint32_t)p_config->access_timeout << RRAMC_POWER_CONFIG_ACCESSTIMEOUT_Pos) |
592 ((uint32_t)p_config->abort_on_pof << RRAMC_POWER_CONFIG_POF_Pos);
593 }
594
nrf_rramc_erase_all_check(NRF_RRAMC_Type const * p_reg)595 NRF_STATIC_INLINE bool nrf_rramc_erase_all_check(NRF_RRAMC_Type const * p_reg)
596 {
597 return ((p_reg->ERASE.ERASEALL & RRAMC_ERASE_ERASEALL_ERASE_Msk) >>
598 RRAMC_ERASE_ERASEALL_ERASE_Pos) ==
599 RRAMC_ERASE_ERASEALL_ERASE_Erase;
600 }
601
nrf_rramc_erase_all_set(NRF_RRAMC_Type * p_reg)602 NRF_STATIC_INLINE void nrf_rramc_erase_all_set(NRF_RRAMC_Type * p_reg)
603 {
604 p_reg->ERASE.ERASEALL = RRAMC_ERASE_ERASEALL_ERASE_Erase;
605 }
606
nrf_rramc_region_config_set(NRF_RRAMC_Type * p_reg,uint8_t region,nrf_rramc_region_config_t const * p_config)607 NRF_STATIC_INLINE void nrf_rramc_region_config_set(NRF_RRAMC_Type * p_reg,
608 uint8_t region,
609 nrf_rramc_region_config_t const * p_config)
610 {
611 p_reg->REGION[region].ADDRESS = p_config->address;
612 p_reg->REGION[region].CONFIG = (((p_config->permissions
613 & NRF_RRAMC_REGION_CONFIG_PERM_MASK)) |
614 ((p_config->writeonce ? RRAMC_REGION_CONFIG_WRITEONCE_Enabled :
615 RRAMC_REGION_CONFIG_WRITEONCE_Disabled)
616 << RRAMC_REGION_CONFIG_WRITEONCE_Pos) |
617 ((p_config->lock ? RRAMC_REGION_CONFIG_LOCK_Enabled:
618 RRAMC_REGION_CONFIG_LOCK_Disabled)
619 << RRAMC_REGION_CONFIG_LOCK_Pos) |
620 ((p_config->size_kb << RRAMC_REGION_CONFIG_SIZE_Pos)
621 & RRAMC_REGION_CONFIG_SIZE_Msk));
622 }
623
nrf_rramc_region_config_get(NRF_RRAMC_Type const * p_reg,uint8_t region,nrf_rramc_region_config_t * p_config)624 NRF_STATIC_INLINE void nrf_rramc_region_config_get(NRF_RRAMC_Type const * p_reg,
625 uint8_t region,
626 nrf_rramc_region_config_t * p_config)
627 {
628 uint32_t reg = p_reg->REGION[region].CONFIG;
629 p_config->permissions = reg & NRF_RRAMC_REGION_CONFIG_PERM_MASK;
630 p_config->writeonce = ((reg & RRAMC_REGION_CONFIG_WRITEONCE_Msk)
631 >> RRAMC_REGION_CONFIG_WRITE_Pos) ==
632 RRAMC_REGION_CONFIG_WRITEONCE_Enabled;
633 p_config->lock = ((reg & RRAMC_REGION_CONFIG_LOCK_Msk)
634 >> RRAMC_REGION_CONFIG_LOCK_Pos) == RRAMC_REGION_CONFIG_LOCK_Enabled;
635 p_config->size_kb = (reg & RRAMC_REGION_CONFIG_SIZE_Msk) >> RRAMC_REGION_CONFIG_SIZE_Pos;
636 p_config->address = p_reg->REGION[region].ADDRESS;
637 }
638
nrf_rramc_region_config_raw_get(NRF_RRAMC_Type const * p_reg,uint8_t region)639 NRF_STATIC_INLINE uint32_t nrf_rramc_region_config_raw_get(NRF_RRAMC_Type const * p_reg,
640 uint8_t region)
641 {
642 return p_reg->REGION[region].CONFIG;
643 }
644
645 #endif // NRF_DECLARE_ONLY
646
647 /** @} */
648
649 #ifdef __cplusplus
650 }
651 #endif
652
653 #endif // NRF_RRAM_H__
654
