1 /*
2 * Copyright (c) 2016 - 2024, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_QSPI_H__
35 #define NRF_QSPI_H__
36
37 #include <nrfx.h>
38 #include <nrf_erratas.h>
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 /**
45 * @defgroup nrf_qspi_hal QSPI HAL
46 * @{
47 * @ingroup nrf_qspi
48 * @brief Hardware access layer for managing the QSPI peripheral.
49 */
50
51 #if defined(QSPI_XIPEN_XIPEN_Msk) || defined(__NRFX_DOXYGEN__)
52 /** @brief Symbol indicating whether XIP can be explicitly enabled or disabled via XIPEN register. */
53 #define NRF_QSPI_HAS_XIPEN 1
54 #else
55 #define NRF_QSPI_HAS_XIPEN 0
56 #endif
57
58 #if defined(QSPI_XIP_ENC_ENABLE_ENABLE_Msk) || defined(__NRFX_DOXYGEN__)
59 /** @brief Symbol indicating whether encryption for XIP is present. */
60 #define NRF_QSPI_HAS_XIP_ENC 1
61 #else
62 #define NRF_QSPI_HAS_XIP_ENC 0
63 #endif
64
65 #if defined(QSPI_DMA_ENC_ENABLE_ENABLE_Msk) || defined(__NRFX_DOXYGEN__)
66 /** @brief Symbol indicating whether encryption for EasyDMA is present. */
67 #define NRF_QSPI_HAS_DMA_ENC 1
68 #else
69 #define NRF_QSPI_HAS_DMA_ENC 0
70 #endif
71
72 #if defined(QSPI_IFCONFIG1_SPIMODE_MODE3) || defined(__NRFX_DOXYGEN__)
73 /** @brief Symbol indicating whether support for QSPI mode 1 is present. */
74 #define NRF_QSPI_HAS_MODE_1 1
75 #else
76 #define NRF_QSPI_HAS_MODE_1 0
77 #endif
78
79 #if defined(NRF53_SERIES) || defined(__NRFX_DOXYGEN__)
80 /** @brief Value representing QSPI base clock frequency. */
81 #define NRF_QSPI_BASE_CLOCK_FREQ 96000000uL
82 #else
83 #define NRF_QSPI_BASE_CLOCK_FREQ 32000000uL
84 #endif
85
86 /**
87 * @brief This value can be used as a parameter for the @ref nrf_qspi_pins_set
88 * function to specify that a given QSPI signal (SCK, CSN, IO0, IO1, IO2, or IO3)
89 * will not be connected to a physical pin.
90 */
91 #define NRF_QSPI_PIN_NOT_CONNECTED 0xFF
92
93 /** @brief Macro for setting proper values to pin registers. */
94 #define NRF_QSPI_PIN_VAL(pin) (pin) == NRF_QSPI_PIN_NOT_CONNECTED ? 0xFFFFFFFF : (pin)
95
96
97 /** @brief QSPI tasks. */
98 typedef enum
99 {
100 NRF_QSPI_TASK_ACTIVATE = offsetof(NRF_QSPI_Type, TASKS_ACTIVATE), /**< Activate the QSPI interface. */
101 NRF_QSPI_TASK_READSTART = offsetof(NRF_QSPI_Type, TASKS_READSTART), /**< Start transfer from external flash memory to internal RAM. */
102 NRF_QSPI_TASK_WRITESTART = offsetof(NRF_QSPI_Type, TASKS_WRITESTART), /**< Start transfer from internal RAM to external flash memory. */
103 NRF_QSPI_TASK_ERASESTART = offsetof(NRF_QSPI_Type, TASKS_ERASESTART), /**< Start external flash memory erase operation. */
104 NRF_QSPI_TASK_DEACTIVATE = offsetof(NRF_QSPI_Type, TASKS_DEACTIVATE), /**< Deactivate the QSPI interface. */
105 } nrf_qspi_task_t;
106
107 /** @brief QSPI events. */
108 typedef enum
109 {
110 NRF_QSPI_EVENT_READY = offsetof(NRF_QSPI_Type, EVENTS_READY) /**< QSPI peripheral is ready after it executes any task. */
111 } nrf_qspi_event_t;
112
113 /** @brief QSPI interrupts. */
114 typedef enum
115 {
116 NRF_QSPI_INT_READY_MASK = QSPI_INTENSET_READY_Msk /**< Interrupt on READY event. */
117 } nrf_qspi_int_mask_t;
118
119 /** @brief QSPI base clock frequency divider values. */
120 typedef enum
121 {
122 NRF_QSPI_FREQ_DIV1, /**< Divide by 1. */
123 NRF_QSPI_FREQ_DIV2, /**< Divide by 2. */
124 NRF_QSPI_FREQ_DIV3, /**< Divide by 3. */
125 NRF_QSPI_FREQ_DIV4, /**< Divide by 4. */
126 NRF_QSPI_FREQ_DIV5, /**< Divide by 5. */
127 NRF_QSPI_FREQ_DIV6, /**< Divide by 6. */
128 NRF_QSPI_FREQ_DIV7, /**< Divide by 7. */
129 NRF_QSPI_FREQ_DIV8, /**< Divide by 8. */
130 NRF_QSPI_FREQ_DIV9, /**< Divide by 9. */
131 NRF_QSPI_FREQ_DIV10, /**< Divide by 10. */
132 NRF_QSPI_FREQ_DIV11, /**< Divide by 11. */
133 NRF_QSPI_FREQ_DIV12, /**< Divide by 12. */
134 NRF_QSPI_FREQ_DIV13, /**< Divide by 13. */
135 NRF_QSPI_FREQ_DIV14, /**< Divide by 14. */
136 NRF_QSPI_FREQ_DIV15, /**< Divide by 15. */
137 NRF_QSPI_FREQ_DIV16, /**< Divide by 16. */
138 } nrf_qspi_frequency_t;
139
140 #if defined(NRF52_SERIES)
141 /** Symbols translation for backward compatibility. */
142 #define NRF_QSPI_FREQ_32MDIV1 NRF_QSPI_FREQ_DIV1
143 #define NRF_QSPI_FREQ_32MDIV2 NRF_QSPI_FREQ_DIV2
144 #define NRF_QSPI_FREQ_32MDIV3 NRF_QSPI_FREQ_DIV3
145 #define NRF_QSPI_FREQ_32MDIV4 NRF_QSPI_FREQ_DIV4
146 #define NRF_QSPI_FREQ_32MDIV5 NRF_QSPI_FREQ_DIV5
147 #define NRF_QSPI_FREQ_32MDIV6 NRF_QSPI_FREQ_DIV6
148 #define NRF_QSPI_FREQ_32MDIV7 NRF_QSPI_FREQ_DIV7
149 #define NRF_QSPI_FREQ_32MDIV8 NRF_QSPI_FREQ_DIV8
150 #define NRF_QSPI_FREQ_32MDIV9 NRF_QSPI_FREQ_DIV9
151 #define NRF_QSPI_FREQ_32MDIV10 NRF_QSPI_FREQ_DIV10
152 #define NRF_QSPI_FREQ_32MDIV11 NRF_QSPI_FREQ_DIV11
153 #define NRF_QSPI_FREQ_32MDIV12 NRF_QSPI_FREQ_DIV12
154 #define NRF_QSPI_FREQ_32MDIV13 NRF_QSPI_FREQ_DIV13
155 #define NRF_QSPI_FREQ_32MDIV14 NRF_QSPI_FREQ_DIV14
156 #define NRF_QSPI_FREQ_32MDIV15 NRF_QSPI_FREQ_DIV15
157 #define NRF_QSPI_FREQ_32MDIV16 NRF_QSPI_FREQ_DIV16
158 #endif
159
160 /** @brief Interface configuration for a read operation. */
161 typedef enum
162 {
163 NRF_QSPI_READOC_FASTREAD = QSPI_IFCONFIG0_READOC_FASTREAD, /**< Single data line SPI. FAST_READ (opcode 0x0B). */
164 NRF_QSPI_READOC_READ2O = QSPI_IFCONFIG0_READOC_READ2O, /**< Dual data line SPI. READ2O (opcode 0x3B). */
165 NRF_QSPI_READOC_READ2IO = QSPI_IFCONFIG0_READOC_READ2IO, /**< Dual data line SPI. READ2IO (opcode 0xBB). */
166 NRF_QSPI_READOC_READ4O = QSPI_IFCONFIG0_READOC_READ4O, /**< Quad data line SPI. READ4O (opcode 0x6B). */
167 NRF_QSPI_READOC_READ4IO = QSPI_IFCONFIG0_READOC_READ4IO /**< Quad data line SPI. READ4IO (opcode 0xEB). */
168 } nrf_qspi_readoc_t;
169
170 /** @brief Interface configuration for a write operation. */
171 typedef enum
172 {
173 NRF_QSPI_WRITEOC_PP = QSPI_IFCONFIG0_WRITEOC_PP, /**< Single data line SPI. PP (opcode 0x02). */
174 NRF_QSPI_WRITEOC_PP2O = QSPI_IFCONFIG0_WRITEOC_PP2O, /**< Dual data line SPI. PP2O (opcode 0xA2). */
175 NRF_QSPI_WRITEOC_PP4O = QSPI_IFCONFIG0_WRITEOC_PP4O, /**< Quad data line SPI. PP4O (opcode 0x32). */
176 NRF_QSPI_WRITEOC_PP4IO = QSPI_IFCONFIG0_WRITEOC_PP4IO, /**< Quad data line SPI. READ4O (opcode 0x38). */
177 } nrf_qspi_writeoc_t;
178
179 /** @brief Interface configuration for addressing mode. */
180 typedef enum
181 {
182 NRF_QSPI_ADDRMODE_24BIT = QSPI_IFCONFIG0_ADDRMODE_24BIT, /**< 24-bit addressing. */
183 NRF_QSPI_ADDRMODE_32BIT = QSPI_IFCONFIG0_ADDRMODE_32BIT /**< 32-bit addressing. */
184 } nrf_qspi_addrmode_t;
185
186 /** @brief QSPI SPI mode. Polarization and phase configuration. */
187 typedef enum
188 {
189 NRF_QSPI_MODE_0 = QSPI_IFCONFIG1_SPIMODE_MODE0, /**< Mode 0 (CPOL=0, CPHA=0). */
190 #if NRF_QSPI_HAS_MODE_1
191 NRF_QSPI_MODE_1 = QSPI_IFCONFIG1_SPIMODE_MODE3 /**< Mode 1 (CPOL=1, CPHA=1). */
192 #endif
193 } nrf_qspi_spi_mode_t;
194
195 /** @brief Addressing configuration mode. */
196 typedef enum
197 {
198 NRF_QSPI_ADDRCONF_MODE_NOINSTR = QSPI_ADDRCONF_MODE_NoInstr, /**< Do not send any instruction. */
199 NRF_QSPI_ADDRCONF_MODE_OPCODE = QSPI_ADDRCONF_MODE_Opcode, /**< Send opcode. */
200 NRF_QSPI_ADDRCONF_MODE_OPBYTE0 = QSPI_ADDRCONF_MODE_OpByte0, /**< Send opcode, byte0. */
201 NRF_QSPI_ADDRCONF_MODE_ALL = QSPI_ADDRCONF_MODE_All /**< Send opcode, byte0, byte1. */
202 } nrf_qspi_addrconfig_mode_t;
203
204 /** @brief Erasing data length. */
205 typedef enum
206 {
207 NRF_QSPI_ERASE_LEN_4KB = QSPI_ERASE_LEN_LEN_4KB, /**< Erase 4 kB block (flash command 0x20). */
208 NRF_QSPI_ERASE_LEN_64KB = QSPI_ERASE_LEN_LEN_64KB, /**< Erase 64 kB block (flash command 0xD8). */
209 NRF_QSPI_ERASE_LEN_ALL = QSPI_ERASE_LEN_LEN_All /**< Erase all (flash command 0xC7). */
210 } nrf_qspi_erase_len_t;
211
212 /** @brief Custom instruction length. */
213 typedef enum
214 {
215 NRF_QSPI_CINSTR_LEN_1B = QSPI_CINSTRCONF_LENGTH_1B, /**< Send opcode only. */
216 NRF_QSPI_CINSTR_LEN_2B = QSPI_CINSTRCONF_LENGTH_2B, /**< Send opcode, CINSTRDAT0.BYTE0. */
217 NRF_QSPI_CINSTR_LEN_3B = QSPI_CINSTRCONF_LENGTH_3B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE1. */
218 NRF_QSPI_CINSTR_LEN_4B = QSPI_CINSTRCONF_LENGTH_4B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE2. */
219 NRF_QSPI_CINSTR_LEN_5B = QSPI_CINSTRCONF_LENGTH_5B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE3. */
220 NRF_QSPI_CINSTR_LEN_6B = QSPI_CINSTRCONF_LENGTH_6B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE4. */
221 NRF_QSPI_CINSTR_LEN_7B = QSPI_CINSTRCONF_LENGTH_7B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE5. */
222 NRF_QSPI_CINSTR_LEN_8B = QSPI_CINSTRCONF_LENGTH_8B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE6. */
223 NRF_QSPI_CINSTR_LEN_9B = QSPI_CINSTRCONF_LENGTH_9B /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE7. */
224 } nrf_qspi_cinstr_len_t;
225
226 /** @brief Pin configuration. */
227 typedef struct
228 {
229 uint32_t sck_pin; /**< SCK pin number. */
230 uint32_t csn_pin; /**< Chip select pin number. */
231 uint32_t io0_pin; /**< IO0/MOSI pin number. */
232 uint32_t io1_pin; /**< IO1/MISO pin number. */
233 uint32_t io2_pin; /**< IO2 pin number (optional).
234 * Set to @ref NRF_QSPI_PIN_NOT_CONNECTED if this signal is not needed.
235 */
236 uint32_t io3_pin; /**< IO3 pin number (optional).
237 * Set to @ref NRF_QSPI_PIN_NOT_CONNECTED if this signal is not needed.
238 */
239 } nrf_qspi_pins_t;
240
241 /** @brief Custom instruction configuration. */
242 typedef struct
243 {
244 uint8_t opcode; /**< Opcode used in custom instruction transmission. */
245 nrf_qspi_cinstr_len_t length; /**< Length of the custom instruction data. */
246 bool io2_level; /**< I/O line level during transmission. */
247 bool io3_level; /**< I/O line level during transmission. */
248 bool wipwait; /**< Wait if a Wait in Progress bit is set in the memory status byte. */
249 bool wren; /**< Send write enable before instruction. */
250 } nrf_qspi_cinstr_conf_t;
251
252 /** @brief Addressing mode register configuration. See @ref nrf_qspi_addrconfig_set */
253 typedef struct
254 {
255 uint8_t opcode; /**< Opcode used to enter the proper addressing mode. */
256 uint8_t byte0; /**< Byte following the opcode. */
257 uint8_t byte1; /**< Byte following byte0. */
258 nrf_qspi_addrconfig_mode_t mode; /**< Extended addresing mode. */
259 bool wipwait; /**< Enable or disable waiting for complete operation execution. */
260 bool wren; /**< Send write enable before instruction. */
261 } nrf_qspi_addrconfig_conf_t;
262
263 /** @brief Structure with QSPI protocol interface configuration. */
264 typedef struct
265 {
266 nrf_qspi_readoc_t readoc; /**< Read operation code. */
267 nrf_qspi_writeoc_t writeoc; /**< Write operation code. */
268 nrf_qspi_addrmode_t addrmode; /**< Addresing mode (24-bit or 32-bit). */
269 bool dpmconfig; /**< Enable the Deep Power-down Mode (DPM) feature. */
270 } nrf_qspi_prot_conf_t;
271
272 /** @brief QSPI physical interface configuration. */
273 typedef struct
274 {
275 uint8_t sck_delay; /**< tSHSL, tWHSL, and tSHWL in number of 16 MHz periods (62.5ns). */
276 bool dpmen; /**< Enable the DPM feature. */
277 nrf_qspi_spi_mode_t spi_mode; /**< SPI phase and polarization. */
278 nrf_qspi_frequency_t sck_freq; /**< SCK frequency given as QSPI base clock frequency divider.
279 * To calculate @p sck_freq value corresponding to chosen frequency,
280 * use the following equation:
281 *
282 * sck_freq = (NRF_QSPI_BASE_CLOCK_FREQ / frequency) - 1
283 *
284 * @note Achievable frequencies are determined by available
285 * divider values and QSPI base clock frequency.
286 */
287 } nrf_qspi_phy_conf_t;
288
289
290 #if NRF_QSPI_HAS_XIP_ENC || NRF_QSPI_HAS_DMA_ENC
291 /** @brief QSPI encryption settings for XIP and DMA transfers. */
292 typedef struct
293 {
294 uint32_t key[4]; /**< AES 128-bit key, stored on 4 32-bit words. */
295 uint32_t nonce[3]; /**< AES 96-bit nonce, stored on 3 32-bit words. */
296 } nrf_qspi_encryption_t;
297 #endif
298
299 /**
300 * @brief Function for activating the specified QSPI task.
301 *
302 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
303 * @param[in] task Task to be activated.
304 */
305 NRF_STATIC_INLINE void nrf_qspi_task_trigger(NRF_QSPI_Type * p_reg, nrf_qspi_task_t task);
306
307 /**
308 * @brief Function for getting the address of the specified QSPI task register.
309 *
310 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
311 * @param[in] task QSPI task.
312 *
313 * @return Address of the specified task register.
314 */
315 NRF_STATIC_INLINE uint32_t nrf_qspi_task_address_get(NRF_QSPI_Type const * p_reg,
316 nrf_qspi_task_t task);
317
318 /**
319 * @brief Function for clearing the specified QSPI event.
320 *
321 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
322 * @param[in] event Event to be cleared.
323 */
324 NRF_STATIC_INLINE void nrf_qspi_event_clear(NRF_QSPI_Type * p_reg, nrf_qspi_event_t event);
325
326 /**
327 * @brief Function for retrieving the state of the QSPI event.
328 *
329 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
330 * @param[in] event Event to be checked.
331 *
332 * @retval true The event has been generated.
333 * @retval false The event has not been generated.
334 */
335 NRF_STATIC_INLINE bool nrf_qspi_event_check(NRF_QSPI_Type const * p_reg, nrf_qspi_event_t event);
336
337 /**
338 * @brief Function for getting the address of the specified QSPI event register.
339 *
340 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
341 * @param[in] event The specified event.
342 *
343 * @return Address of the specified event register.
344 */
345 NRF_STATIC_INLINE uint32_t nrf_qspi_event_address_get(NRF_QSPI_Type const * p_reg,
346 nrf_qspi_event_t event);
347
348 /**
349 * @brief Function for enabling specified interrupts.
350 *
351 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
352 * @param[in] mask Mask of interrupts to be enabled.
353 * Use @ref nrf_qspi_int_mask_t values for bit masking.
354 */
355 NRF_STATIC_INLINE void nrf_qspi_int_enable(NRF_QSPI_Type * p_reg, uint32_t mask);
356
357 /**
358 * @brief Function for disabling specified interrupts.
359 *
360 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
361 * @param[in] mask Mask of interrupts to be disabled.
362 * Use @ref nrf_qspi_int_mask_t values for bit masking.
363 */
364 NRF_STATIC_INLINE void nrf_qspi_int_disable(NRF_QSPI_Type * p_reg, uint32_t mask);
365
366 /**
367 * @brief Function for checking if the specified interrupts are enabled.
368 *
369 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
370 * @param[in] mask Mask of interrupts to be checked.
371 * Use @ref nrf_qspi_int_mask_t values for bit masking.
372 *
373 * @return Mask of enabled interrupts.
374 */
375 NRF_STATIC_INLINE uint32_t nrf_qspi_int_enable_check(NRF_QSPI_Type const * p_reg, uint32_t mask);
376
377 /**
378 * @brief Function for enabling the QSPI peripheral.
379 *
380 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
381 */
382 NRF_STATIC_INLINE void nrf_qspi_enable(NRF_QSPI_Type * p_reg);
383
384 /**
385 * @brief Function for disabling the QSPI peripheral.
386 *
387 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
388 */
389 NRF_STATIC_INLINE void nrf_qspi_disable(NRF_QSPI_Type * p_reg);
390
391 /**
392 * @brief Function for configuring QSPI pins.
393 *
394 * If a given signal is not needed, pass the @ref NRF_QSPI_PIN_NOT_CONNECTED
395 * value instead of its pin number.
396 *
397 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
398 * @param[in] p_pins Pointer to the pins configuration structure. See @ref nrf_qspi_pins_t.
399 */
400 NRF_STATIC_INLINE void nrf_qspi_pins_set(NRF_QSPI_Type * p_reg,
401 nrf_qspi_pins_t const * p_pins);
402
403 /**
404 * @brief Function for getting the currently configured QSPI pins.
405 *
406 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
407 * @param[out] p_pins Pointer to the pins configuration structure to be filled with QSPI pins.
408 */
409 NRF_STATIC_INLINE void nrf_qspi_pins_get(NRF_QSPI_Type const * p_reg,
410 nrf_qspi_pins_t * p_pins);
411
412 /**
413 * @brief Function for setting the QSPI XIPOFFSET register.
414 *
415 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
416 * @param[in] xip_offset Address offset in the external memory for Execute in Place operation.
417 */
418 NRF_STATIC_INLINE void nrf_qspi_xip_offset_set(NRF_QSPI_Type * p_reg,
419 uint32_t xip_offset);
420
421 /**
422 * @brief Function for setting the QSPI IFCONFIG0 register.
423 *
424 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
425 * @param[in] p_config Pointer to the QSPI protocol interface configuration structure.
426 * See @ref nrf_qspi_prot_conf_t.
427 */
428 NRF_STATIC_INLINE void nrf_qspi_ifconfig0_set(NRF_QSPI_Type * p_reg,
429 nrf_qspi_prot_conf_t const * p_config);
430
431 /**
432 * @brief Function for setting the explicit value of the QSPI IFCONFIG0 register.
433 *
434 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
435 * @param[in] regval Register value to be set.
436 */
437 NRF_STATIC_INLINE void nrf_qspi_ifconfig0_raw_set(NRF_QSPI_Type * p_reg, uint32_t regval);
438
439 /**
440 * @brief Function for getting the explicit value of the QSPI IFCONFIG0 register.
441 *
442 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
443 *
444 * @return Value of IFCONFIG0 register.
445 */
446 NRF_STATIC_INLINE uint32_t nrf_qspi_ifconfig0_raw_get(NRF_QSPI_Type const * p_reg);
447
448 /**
449 * @brief Function for setting the QSPI IFCONFIG1 register.
450 *
451 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
452 * @param[in] p_config Pointer to the QSPI physical interface configuration structure.
453 * See @ref nrf_qspi_phy_conf_t.
454 */
455 NRF_STATIC_INLINE void nrf_qspi_ifconfig1_set(NRF_QSPI_Type * p_reg,
456 nrf_qspi_phy_conf_t const * p_config);
457
458 /**
459 * @brief Function for setting the QSPI ADDRCONF register.
460 *
461 * This function must be executed before sending task NRF_QSPI_TASK_ACTIVATE. Data stored in the structure
462 * is sent during the start of the peripheral. Remember that the reset instruction can set
463 * addressing mode to default in the memory device. If memory reset is necessary before configuring
464 * the addressing mode, use custom instruction feature instead of this function.
465 * Case with reset: Enable the peripheral without setting ADDRCONF register, send reset instructions
466 * using a custom instruction feature (reset enable and then reset), set proper addressing mode
467 * using the custom instruction feature.
468 *
469 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
470 * @param[in] p_config Pointer to the addressing mode configuration structure.
471 * See @ref nrf_qspi_addrconfig_conf_t.
472 */
473 NRF_STATIC_INLINE void nrf_qspi_addrconfig_set(NRF_QSPI_Type * p_reg,
474 nrf_qspi_addrconfig_conf_t const * p_config);
475
476 /**
477 * @brief Function for setting write data into the peripheral register (without starting the process).
478 *
479 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
480 * @param[in] p_buffer Pointer to the writing buffer.
481 * @param[in] length Lenght of the writing data.
482 * @param[in] dest_addr Address in memory to write to.
483 */
484 NRF_STATIC_INLINE void nrf_qspi_write_buffer_set(NRF_QSPI_Type * p_reg,
485 void const * p_buffer,
486 uint32_t length,
487 uint32_t dest_addr);
488
489 /**
490 * @brief Function for setting read data into the peripheral register (without starting the process).
491 *
492 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
493 * @param[out] p_buffer Pointer to the reading buffer.
494 * @param[in] length Length of the read data.
495 * @param[in] src_addr Address in memory to read from.
496 */
497 NRF_STATIC_INLINE void nrf_qspi_read_buffer_set(NRF_QSPI_Type * p_reg,
498 void * p_buffer,
499 uint32_t length,
500 uint32_t src_addr);
501
502 /**
503 * @brief Function for setting erase data into the peripheral register (without starting the process).
504 *
505 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
506 * @param[in] erase_addr Start address to erase. Address must have padding set to 4 bytes.
507 * @param[in] len Size of erasing area.
508 */
509 NRF_STATIC_INLINE void nrf_qspi_erase_ptr_set(NRF_QSPI_Type * p_reg,
510 uint32_t erase_addr,
511 nrf_qspi_erase_len_t len);
512
513 /**
514 * @brief Function for getting the currently configured erase pointer.
515 *
516 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
517 *
518 * @return Erase pointer.
519 */
520 NRF_STATIC_INLINE uint32_t nrf_qspi_erase_ptr_get(NRF_QSPI_Type const * p_reg);
521
522 /**
523 * @brief Function for getting the currently configured erase length.
524 *
525 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
526 *
527 * @return Erase length.
528 */
529 NRF_STATIC_INLINE nrf_qspi_erase_len_t nrf_qspi_erase_len_get(NRF_QSPI_Type const * p_reg);
530
531 /**
532 * @brief Function for getting the peripheral status register.
533 *
534 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
535 *
536 * @return Peripheral status register.
537 */
538 NRF_STATIC_INLINE uint32_t nrf_qspi_status_reg_get(NRF_QSPI_Type const * p_reg);
539
540 /**
541 * @brief Function for getting the device status register stored in the peripheral status register.
542 *
543 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
544 *
545 * @return Device status register (lower byte).
546 */
547 NRF_STATIC_INLINE uint8_t nrf_qspi_sreg_get(NRF_QSPI_Type const * p_reg);
548
549 /**
550 * @brief Function for checking if the peripheral is busy or not.
551 *
552 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
553 *
554 * @retval true The QSPI is busy.
555 * @retval false The QSPI is ready.
556 */
557 NRF_STATIC_INLINE bool nrf_qspi_busy_check(NRF_QSPI_Type const * p_reg);
558
559 /**
560 * @brief Function for setting registers sending with custom instruction transmission.
561 *
562 * This function can be ommited when using NRF_QSPI_CINSTR_LEN_1B as the length argument
563 * (sending only opcode without data).
564 *
565 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
566 * @param[in] length Length of the custom instruction data.
567 * @param[in] p_tx_data Pointer to the data to send with the custom instruction.
568 */
569 NRF_STATIC_INLINE void nrf_qspi_cinstrdata_set(NRF_QSPI_Type * p_reg,
570 nrf_qspi_cinstr_len_t length,
571 void const * p_tx_data);
572
573 /**
574 * @brief Function for getting data from register after custom instruction transmission.
575 *
576 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
577 * @param[in] length Length of the custom instruction data.
578 * @param[in] p_rx_data Pointer to the reading buffer.
579 */
580 NRF_STATIC_INLINE void nrf_qspi_cinstrdata_get(NRF_QSPI_Type const * p_reg,
581 nrf_qspi_cinstr_len_t length,
582 void * p_rx_data);
583
584 /**
585 * @brief Function for sending custom instruction to external memory.
586 *
587 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
588 * @param[in] p_config Pointer to the custom instruction configuration structure.
589 * See @ref nrf_qspi_cinstr_conf_t.
590 */
591 NRF_STATIC_INLINE void nrf_qspi_cinstr_transfer_start(NRF_QSPI_Type * p_reg,
592 nrf_qspi_cinstr_conf_t const * p_config);
593
594 /**
595 * @brief Function for starting a custom instruction long transfer.
596 *
597 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
598 * @param[in] p_config Pointer to the custom instruction configuration structure.
599 * See @ref nrf_qspi_cinstr_conf_t.
600 */
601 NRF_STATIC_INLINE void nrf_qspi_cinstr_long_transfer_start(NRF_QSPI_Type * p_reg,
602 nrf_qspi_cinstr_conf_t const * p_config);
603
604 /**
605 * @brief Function for checking whether a custom instruction long transfer is ongoing.
606 *
607 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
608 *
609 * @retval true Custom instruction long transfer is ongoing.
610 * @retval false Custom instruction long transfer is not ongoing.
611 */
612 NRF_STATIC_INLINE bool nrf_qspi_cinstr_long_transfer_is_ongoing(NRF_QSPI_Type const * p_reg);
613
614 /**
615 * @brief Function for continuing a custom instruction long transfer.
616 *
617 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
618 * @param[in] length Length of the custom instruction data.
619 * @param[in] finalize True if the custom instruction long transfer is to be finalized.
620 * False if the custom instruction long transfer is to be continued.
621 */
622 NRF_STATIC_INLINE void nrf_qspi_cinstr_long_transfer_continue(NRF_QSPI_Type * p_reg,
623 nrf_qspi_cinstr_len_t length,
624 bool finalize);
625
626 #if NRF_QSPI_HAS_XIPEN
627 /**
628 * @brief Function for enabling or disabling Execute in Place (XIP) operation.
629 *
630 * @note XIP can be enabled after reset. See Product Specification.
631 *
632 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
633 * @param[in] enable True if XIP is to be enabled, false otherwise.
634 */
635 NRF_STATIC_INLINE void nrf_qspi_xip_set(NRF_QSPI_Type * p_reg, bool enable);
636 #endif
637
638 #if NRF_QSPI_HAS_XIP_ENC
639 /**
640 * @brief Function for configuring the XIP encryption.
641 *
642 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
643 * @param[in] p_cfg Pointer to encryption configuration structure.
644 */
645 NRF_STATIC_INLINE void nrf_qspi_xip_encryption_configure(NRF_QSPI_Type * p_reg,
646 nrf_qspi_encryption_t const * p_cfg);
647
648 /**
649 * @brief Function for enabling or disabling the XIP encryption.
650 *
651 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
652 * @param[in] enable True if XIP encryption is to be enabled, false otherwise.
653 */
654 NRF_STATIC_INLINE void nrf_qspi_xip_encryption_set(NRF_QSPI_Type * p_reg, bool enable);
655 #endif
656
657 #if NRF_QSPI_HAS_DMA_ENC
658 /**
659 * @brief Function for configuring the EasyDMA encryption.
660 *
661 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
662 * @param[in] p_cfg Pointer to encryption configuration structure.
663 */
664 NRF_STATIC_INLINE void nrf_qspi_dma_encryption_configure(NRF_QSPI_Type * p_reg,
665 nrf_qspi_encryption_t const * p_cfg);
666
667 /**
668 * @brief Function for enabling or disabling the EasyDMA encryption.
669 *
670 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
671 * @param[in] enable True if EasyDMA encryption is to be enabled, false otherwise.
672 */
673 NRF_STATIC_INLINE void nrf_qspi_dma_encryption_set(NRF_QSPI_Type * p_reg, bool enable);
674 #endif
675
676 /**
677 * @brief Function for setting the timing related to sampling of the input serial data.
678 *
679 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
680 * @param[in] rxdelay Number of 64 MHz cycles (15.625 ns) delay from the the rising edge of the clock
681 * until the input serial data is sampled.
682 */
683 NRF_STATIC_INLINE void nrf_qspi_iftiming_set(NRF_QSPI_Type * p_reg, uint8_t rxdelay);
684
685 #ifndef NRF_DECLARE_ONLY
686
nrf_qspi_task_trigger(NRF_QSPI_Type * p_reg,nrf_qspi_task_t task)687 NRF_STATIC_INLINE void nrf_qspi_task_trigger(NRF_QSPI_Type * p_reg, nrf_qspi_task_t task)
688 {
689 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
690 }
691
nrf_qspi_task_address_get(NRF_QSPI_Type const * p_reg,nrf_qspi_task_t task)692 NRF_STATIC_INLINE uint32_t nrf_qspi_task_address_get(NRF_QSPI_Type const * p_reg,
693 nrf_qspi_task_t task)
694 {
695 return ((uint32_t)p_reg + (uint32_t)task);
696 }
697
nrf_qspi_event_clear(NRF_QSPI_Type * p_reg,nrf_qspi_event_t event)698 NRF_STATIC_INLINE void nrf_qspi_event_clear(NRF_QSPI_Type * p_reg, nrf_qspi_event_t event)
699 {
700 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
701 }
702
nrf_qspi_event_check(NRF_QSPI_Type const * p_reg,nrf_qspi_event_t event)703 NRF_STATIC_INLINE bool nrf_qspi_event_check(NRF_QSPI_Type const * p_reg, nrf_qspi_event_t event)
704 {
705 return nrf_event_check(p_reg, event);
706 }
707
nrf_qspi_event_address_get(NRF_QSPI_Type const * p_reg,nrf_qspi_event_t event)708 NRF_STATIC_INLINE uint32_t nrf_qspi_event_address_get(NRF_QSPI_Type const * p_reg,
709 nrf_qspi_event_t event)
710 {
711 return nrf_task_event_address_get(p_reg, event);
712 }
713
nrf_qspi_int_enable(NRF_QSPI_Type * p_reg,uint32_t mask)714 NRF_STATIC_INLINE void nrf_qspi_int_enable(NRF_QSPI_Type * p_reg, uint32_t mask)
715 {
716 p_reg->INTENSET = mask;
717 }
718
nrf_qspi_int_disable(NRF_QSPI_Type * p_reg,uint32_t mask)719 NRF_STATIC_INLINE void nrf_qspi_int_disable(NRF_QSPI_Type * p_reg, uint32_t mask)
720 {
721 p_reg->INTENCLR = mask;
722 }
723
nrf_qspi_int_enable_check(NRF_QSPI_Type const * p_reg,uint32_t mask)724 NRF_STATIC_INLINE uint32_t nrf_qspi_int_enable_check(NRF_QSPI_Type const * p_reg, uint32_t mask)
725 {
726 return p_reg->INTENSET & mask;
727 }
728
nrf_qspi_enable(NRF_QSPI_Type * p_reg)729 NRF_STATIC_INLINE void nrf_qspi_enable(NRF_QSPI_Type * p_reg)
730 {
731 p_reg->ENABLE = (QSPI_ENABLE_ENABLE_Enabled << QSPI_ENABLE_ENABLE_Pos);
732 }
733
nrf_qspi_disable(NRF_QSPI_Type * p_reg)734 NRF_STATIC_INLINE void nrf_qspi_disable(NRF_QSPI_Type * p_reg)
735 {
736 if (nrf52_errata_122())
737 {
738 // Workaround for anomaly 122: "QSPI: QSPI uses current after being disabled".
739 *(volatile uint32_t *)0x40029054ul = 1ul;
740 }
741 p_reg->ENABLE = (QSPI_ENABLE_ENABLE_Disabled << QSPI_ENABLE_ENABLE_Pos);
742 }
743
nrf_qspi_pins_set(NRF_QSPI_Type * p_reg,nrf_qspi_pins_t const * p_pins)744 NRF_STATIC_INLINE void nrf_qspi_pins_set(NRF_QSPI_Type * p_reg, nrf_qspi_pins_t const * p_pins)
745 {
746 p_reg->PSEL.SCK = NRF_QSPI_PIN_VAL(p_pins->sck_pin);
747 p_reg->PSEL.CSN = NRF_QSPI_PIN_VAL(p_pins->csn_pin);
748 p_reg->PSEL.IO0 = NRF_QSPI_PIN_VAL(p_pins->io0_pin);
749 p_reg->PSEL.IO1 = NRF_QSPI_PIN_VAL(p_pins->io1_pin);
750 p_reg->PSEL.IO2 = NRF_QSPI_PIN_VAL(p_pins->io2_pin);
751 p_reg->PSEL.IO3 = NRF_QSPI_PIN_VAL(p_pins->io3_pin);
752 }
753
nrf_qspi_pins_get(NRF_QSPI_Type const * p_reg,nrf_qspi_pins_t * p_pins)754 NRF_STATIC_INLINE void nrf_qspi_pins_get(NRF_QSPI_Type const * p_reg,
755 nrf_qspi_pins_t * p_pins)
756 {
757 p_pins->sck_pin = (uint8_t)p_reg->PSEL.SCK;
758 p_pins->csn_pin = (uint8_t)p_reg->PSEL.CSN;
759 p_pins->io0_pin = (uint8_t)p_reg->PSEL.IO0;
760 p_pins->io1_pin = (uint8_t)p_reg->PSEL.IO1;
761 p_pins->io2_pin = (uint8_t)p_reg->PSEL.IO2;
762 p_pins->io3_pin = (uint8_t)p_reg->PSEL.IO3;
763 }
764
nrf_qspi_xip_offset_set(NRF_QSPI_Type * p_reg,uint32_t xip_offset)765 NRF_STATIC_INLINE void nrf_qspi_xip_offset_set(NRF_QSPI_Type * p_reg,
766 uint32_t xip_offset)
767 {
768 p_reg->XIPOFFSET = xip_offset;
769 }
770
nrf_qspi_ifconfig0_set(NRF_QSPI_Type * p_reg,nrf_qspi_prot_conf_t const * p_config)771 NRF_STATIC_INLINE void nrf_qspi_ifconfig0_set(NRF_QSPI_Type * p_reg,
772 nrf_qspi_prot_conf_t const * p_config)
773 {
774 uint32_t config = p_config->readoc;
775 config |= ((uint32_t)p_config->writeoc) << QSPI_IFCONFIG0_WRITEOC_Pos;
776 config |= ((uint32_t)p_config->addrmode) << QSPI_IFCONFIG0_ADDRMODE_Pos;
777 config |= (p_config->dpmconfig ? 1U : 0U ) << QSPI_IFCONFIG0_DPMENABLE_Pos;
778
779 p_reg->IFCONFIG0 = config;
780 }
781
nrf_qspi_ifconfig0_raw_set(NRF_QSPI_Type * p_reg,uint32_t regval)782 NRF_STATIC_INLINE void nrf_qspi_ifconfig0_raw_set(NRF_QSPI_Type * p_reg, uint32_t regval)
783 {
784 p_reg->IFCONFIG0 = regval;
785 }
786
nrf_qspi_ifconfig0_raw_get(NRF_QSPI_Type const * p_reg)787 NRF_STATIC_INLINE uint32_t nrf_qspi_ifconfig0_raw_get(NRF_QSPI_Type const * p_reg)
788 {
789 return p_reg->IFCONFIG0;
790 }
791
nrf_qspi_ifconfig1_set(NRF_QSPI_Type * p_reg,nrf_qspi_phy_conf_t const * p_config)792 NRF_STATIC_INLINE void nrf_qspi_ifconfig1_set(NRF_QSPI_Type * p_reg,
793 nrf_qspi_phy_conf_t const * p_config)
794 {
795 // IFCONFIG1 mask for reserved fields in the register.
796 uint32_t config = p_reg->IFCONFIG1 & 0x00FFFF00;
797 config |= p_config->sck_delay;
798 config |= (p_config->dpmen ? 1U : 0U) << QSPI_IFCONFIG1_DPMEN_Pos;
799 config |= ((uint32_t)(p_config->spi_mode)) << QSPI_IFCONFIG1_SPIMODE_Pos;
800 config |= ((uint32_t)(p_config->sck_freq)) << QSPI_IFCONFIG1_SCKFREQ_Pos;
801
802 p_reg->IFCONFIG1 = config;
803 }
804
nrf_qspi_addrconfig_set(NRF_QSPI_Type * p_reg,nrf_qspi_addrconfig_conf_t const * p_config)805 NRF_STATIC_INLINE void nrf_qspi_addrconfig_set(NRF_QSPI_Type * p_reg,
806 nrf_qspi_addrconfig_conf_t const * p_config)
807 {
808 uint32_t config = p_config->opcode;
809 config |= ((uint32_t)p_config->byte0) << QSPI_ADDRCONF_BYTE0_Pos;
810 config |= ((uint32_t)p_config->byte1) << QSPI_ADDRCONF_BYTE1_Pos;
811 config |= ((uint32_t)(p_config->mode)) << QSPI_ADDRCONF_MODE_Pos;
812 config |= (p_config->wipwait ? 1U : 0U) << QSPI_ADDRCONF_WIPWAIT_Pos;
813 config |= (p_config->wren ? 1U : 0U) << QSPI_ADDRCONF_WREN_Pos;
814
815 p_reg->ADDRCONF = config;
816 }
817
nrf_qspi_write_buffer_set(NRF_QSPI_Type * p_reg,void const * p_buffer,uint32_t length,uint32_t dest_addr)818 NRF_STATIC_INLINE void nrf_qspi_write_buffer_set(NRF_QSPI_Type * p_reg,
819 void const * p_buffer,
820 uint32_t length,
821 uint32_t dest_addr)
822 {
823 p_reg->WRITE.DST = dest_addr;
824 p_reg->WRITE.SRC = (uint32_t) p_buffer;
825 p_reg->WRITE.CNT = length;
826 }
827
nrf_qspi_read_buffer_set(NRF_QSPI_Type * p_reg,void * p_buffer,uint32_t length,uint32_t src_addr)828 NRF_STATIC_INLINE void nrf_qspi_read_buffer_set(NRF_QSPI_Type * p_reg,
829 void * p_buffer,
830 uint32_t length,
831 uint32_t src_addr)
832 {
833 p_reg->READ.SRC = src_addr;
834 p_reg->READ.DST = (uint32_t) p_buffer;
835 p_reg->READ.CNT = length;
836 }
837
nrf_qspi_erase_ptr_set(NRF_QSPI_Type * p_reg,uint32_t erase_addr,nrf_qspi_erase_len_t len)838 NRF_STATIC_INLINE void nrf_qspi_erase_ptr_set(NRF_QSPI_Type * p_reg,
839 uint32_t erase_addr,
840 nrf_qspi_erase_len_t len)
841 {
842 p_reg->ERASE.PTR = erase_addr;
843 p_reg->ERASE.LEN = len;
844 }
845
nrf_qspi_erase_ptr_get(NRF_QSPI_Type const * p_reg)846 NRF_STATIC_INLINE uint32_t nrf_qspi_erase_ptr_get(NRF_QSPI_Type const * p_reg)
847 {
848 return p_reg->ERASE.PTR;
849 }
850
nrf_qspi_erase_len_get(NRF_QSPI_Type const * p_reg)851 NRF_STATIC_INLINE nrf_qspi_erase_len_t nrf_qspi_erase_len_get(NRF_QSPI_Type const * p_reg)
852 {
853 return (nrf_qspi_erase_len_t)p_reg->ERASE.LEN;
854 }
855
nrf_qspi_status_reg_get(NRF_QSPI_Type const * p_reg)856 NRF_STATIC_INLINE uint32_t nrf_qspi_status_reg_get(NRF_QSPI_Type const * p_reg)
857 {
858 return p_reg->STATUS;
859 }
860
nrf_qspi_sreg_get(NRF_QSPI_Type const * p_reg)861 NRF_STATIC_INLINE uint8_t nrf_qspi_sreg_get(NRF_QSPI_Type const * p_reg)
862 {
863 return (uint8_t)(p_reg->STATUS & QSPI_STATUS_SREG_Msk) >> QSPI_STATUS_SREG_Pos;
864 }
865
nrf_qspi_busy_check(NRF_QSPI_Type const * p_reg)866 NRF_STATIC_INLINE bool nrf_qspi_busy_check(NRF_QSPI_Type const * p_reg)
867 {
868 return ((p_reg->STATUS & QSPI_STATUS_READY_Msk) >>
869 QSPI_STATUS_READY_Pos) == QSPI_STATUS_READY_BUSY;
870 }
871
nrf_qspi_cinstrdata_set(NRF_QSPI_Type * p_reg,nrf_qspi_cinstr_len_t length,void const * p_tx_data)872 NRF_STATIC_INLINE void nrf_qspi_cinstrdata_set(NRF_QSPI_Type * p_reg,
873 nrf_qspi_cinstr_len_t length,
874 void const * p_tx_data)
875 {
876 uint32_t reg = 0;
877 uint8_t const *p_tx_data_8 = (uint8_t const *) p_tx_data;
878
879 // Load custom instruction.
880 switch (length)
881 {
882 case NRF_QSPI_CINSTR_LEN_9B:
883 reg |= ((uint32_t)p_tx_data_8[7]) << QSPI_CINSTRDAT1_BYTE7_Pos;
884 /* FALLTHROUGH */
885 case NRF_QSPI_CINSTR_LEN_8B:
886 reg |= ((uint32_t)p_tx_data_8[6]) << QSPI_CINSTRDAT1_BYTE6_Pos;
887 /* FALLTHROUGH */
888 case NRF_QSPI_CINSTR_LEN_7B:
889 reg |= ((uint32_t)p_tx_data_8[5]) << QSPI_CINSTRDAT1_BYTE5_Pos;
890 /* FALLTHROUGH */
891 case NRF_QSPI_CINSTR_LEN_6B:
892 reg |= ((uint32_t)p_tx_data_8[4]);
893 p_reg->CINSTRDAT1 = reg;
894 reg = 0;
895 /* FALLTHROUGH */
896 case NRF_QSPI_CINSTR_LEN_5B:
897 reg |= ((uint32_t)p_tx_data_8[3]) << QSPI_CINSTRDAT0_BYTE3_Pos;
898 /* FALLTHROUGH */
899 case NRF_QSPI_CINSTR_LEN_4B:
900 reg |= ((uint32_t)p_tx_data_8[2]) << QSPI_CINSTRDAT0_BYTE2_Pos;
901 /* FALLTHROUGH */
902 case NRF_QSPI_CINSTR_LEN_3B:
903 reg |= ((uint32_t)p_tx_data_8[1]) << QSPI_CINSTRDAT0_BYTE1_Pos;
904 /* FALLTHROUGH */
905 case NRF_QSPI_CINSTR_LEN_2B:
906 reg |= ((uint32_t)p_tx_data_8[0]);
907 p_reg->CINSTRDAT0 = reg;
908 /* FALLTHROUGH */
909 case NRF_QSPI_CINSTR_LEN_1B:
910 /* Send only opcode. Case to avoid compiler warnings. */
911 break;
912 default:
913 break;
914 }
915 }
916
nrf_qspi_cinstrdata_get(NRF_QSPI_Type const * p_reg,nrf_qspi_cinstr_len_t length,void * p_rx_data)917 NRF_STATIC_INLINE void nrf_qspi_cinstrdata_get(NRF_QSPI_Type const * p_reg,
918 nrf_qspi_cinstr_len_t length,
919 void * p_rx_data)
920 {
921 uint8_t *p_rx_data_8 = (uint8_t *) p_rx_data;
922
923 uint32_t reg1 = p_reg->CINSTRDAT1;
924 uint32_t reg0 = p_reg->CINSTRDAT0;
925 switch (length)
926 {
927 case NRF_QSPI_CINSTR_LEN_9B:
928 p_rx_data_8[7] = (uint8_t)(reg1 >> QSPI_CINSTRDAT1_BYTE7_Pos);
929 /* FALLTHROUGH */
930 case NRF_QSPI_CINSTR_LEN_8B:
931 p_rx_data_8[6] = (uint8_t)(reg1 >> QSPI_CINSTRDAT1_BYTE6_Pos);
932 /* FALLTHROUGH */
933 case NRF_QSPI_CINSTR_LEN_7B:
934 p_rx_data_8[5] = (uint8_t)(reg1 >> QSPI_CINSTRDAT1_BYTE5_Pos);
935 /* FALLTHROUGH */
936 case NRF_QSPI_CINSTR_LEN_6B:
937 p_rx_data_8[4] = (uint8_t)(reg1);
938 /* FALLTHROUGH */
939 case NRF_QSPI_CINSTR_LEN_5B:
940 p_rx_data_8[3] = (uint8_t)(reg0 >> QSPI_CINSTRDAT0_BYTE3_Pos);
941 /* FALLTHROUGH */
942 case NRF_QSPI_CINSTR_LEN_4B:
943 p_rx_data_8[2] = (uint8_t)(reg0 >> QSPI_CINSTRDAT0_BYTE2_Pos);
944 /* FALLTHROUGH */
945 case NRF_QSPI_CINSTR_LEN_3B:
946 p_rx_data_8[1] = (uint8_t)(reg0 >> QSPI_CINSTRDAT0_BYTE1_Pos);
947 /* FALLTHROUGH */
948 case NRF_QSPI_CINSTR_LEN_2B:
949 p_rx_data_8[0] = (uint8_t)(reg0);
950 /* FALLTHROUGH */
951 case NRF_QSPI_CINSTR_LEN_1B:
952 /* Send only opcode. Case to avoid compiler warnings. */
953 break;
954 default:
955 break;
956 }
957 }
958
nrf_qspi_cinstr_transfer_start(NRF_QSPI_Type * p_reg,nrf_qspi_cinstr_conf_t const * p_config)959 NRF_STATIC_INLINE void nrf_qspi_cinstr_transfer_start(NRF_QSPI_Type * p_reg,
960 nrf_qspi_cinstr_conf_t const * p_config)
961 {
962 p_reg->CINSTRCONF = (((uint32_t)p_config->opcode << QSPI_CINSTRCONF_OPCODE_Pos) |
963 ((uint32_t)p_config->length << QSPI_CINSTRCONF_LENGTH_Pos) |
964 ((uint32_t)p_config->io2_level << QSPI_CINSTRCONF_LIO2_Pos) |
965 ((uint32_t)p_config->io3_level << QSPI_CINSTRCONF_LIO3_Pos) |
966 ((uint32_t)p_config->wipwait << QSPI_CINSTRCONF_WIPWAIT_Pos) |
967 ((uint32_t)p_config->wren << QSPI_CINSTRCONF_WREN_Pos));
968 }
969
nrf_qspi_cinstr_long_transfer_start(NRF_QSPI_Type * p_reg,nrf_qspi_cinstr_conf_t const * p_config)970 NRF_STATIC_INLINE void nrf_qspi_cinstr_long_transfer_start(NRF_QSPI_Type * p_reg,
971 nrf_qspi_cinstr_conf_t const * p_config)
972 {
973 p_reg->CINSTRCONF = (((uint32_t)p_config->opcode << QSPI_CINSTRCONF_OPCODE_Pos) |
974 ((uint32_t)p_config->length << QSPI_CINSTRCONF_LENGTH_Pos) |
975 ((uint32_t)p_config->io2_level << QSPI_CINSTRCONF_LIO2_Pos) |
976 ((uint32_t)p_config->io3_level << QSPI_CINSTRCONF_LIO3_Pos) |
977 ((uint32_t)p_config->wipwait << QSPI_CINSTRCONF_WIPWAIT_Pos) |
978 ((uint32_t)p_config->wren << QSPI_CINSTRCONF_WREN_Pos) |
979 (QSPI_CINSTRCONF_LFEN_Msk));
980 }
981
nrf_qspi_cinstr_long_transfer_is_ongoing(NRF_QSPI_Type const * p_reg)982 NRF_STATIC_INLINE bool nrf_qspi_cinstr_long_transfer_is_ongoing(NRF_QSPI_Type const * p_reg)
983 {
984 return (bool)((p_reg->CINSTRCONF & (QSPI_CINSTRCONF_LFEN_Msk | QSPI_CINSTRCONF_LFSTOP_Msk))
985 == QSPI_CINSTRCONF_LFEN_Msk);
986 }
987
nrf_qspi_cinstr_long_transfer_continue(NRF_QSPI_Type * p_reg,nrf_qspi_cinstr_len_t length,bool finalize)988 NRF_STATIC_INLINE void nrf_qspi_cinstr_long_transfer_continue(NRF_QSPI_Type * p_reg,
989 nrf_qspi_cinstr_len_t length,
990 bool finalize)
991 {
992 uint32_t mask = (((uint32_t)length << QSPI_CINSTRCONF_LENGTH_Pos) | (QSPI_CINSTRCONF_LFEN_Msk));
993 mask |= (finalize ? QSPI_CINSTRCONF_LFSTOP_Msk : 0);
994
995 p_reg->CINSTRCONF = mask;
996 }
997
998 #if NRF_QSPI_HAS_XIPEN
nrf_qspi_xip_set(NRF_QSPI_Type * p_reg,bool enable)999 NRF_STATIC_INLINE void nrf_qspi_xip_set(NRF_QSPI_Type * p_reg, bool enable)
1000 {
1001 p_reg->XIPEN = (enable ? QSPI_XIPEN_XIPEN_Enable << QSPI_XIPEN_XIPEN_Pos
1002 : QSPI_XIPEN_XIPEN_Disable << QSPI_XIPEN_XIPEN_Pos);
1003 }
1004 #endif
1005
1006 #if NRF_QSPI_HAS_XIP_ENC
nrf_qspi_xip_encryption_configure(NRF_QSPI_Type * p_reg,nrf_qspi_encryption_t const * p_cfg)1007 NRF_STATIC_INLINE void nrf_qspi_xip_encryption_configure(NRF_QSPI_Type * p_reg,
1008 nrf_qspi_encryption_t const * p_cfg)
1009 {
1010 p_reg->XIP_ENC.KEY0 = p_cfg->key[0];
1011 p_reg->XIP_ENC.KEY1 = p_cfg->key[1];
1012 p_reg->XIP_ENC.KEY2 = p_cfg->key[2];
1013 p_reg->XIP_ENC.KEY3 = p_cfg->key[3];
1014 p_reg->XIP_ENC.NONCE0 = p_cfg->nonce[0];
1015 p_reg->XIP_ENC.NONCE1 = p_cfg->nonce[1];
1016 p_reg->XIP_ENC.NONCE2 = p_cfg->nonce[2];
1017 }
1018
nrf_qspi_xip_encryption_set(NRF_QSPI_Type * p_reg,bool enable)1019 NRF_STATIC_INLINE void nrf_qspi_xip_encryption_set(NRF_QSPI_Type * p_reg, bool enable)
1020 {
1021 p_reg->XIP_ENC.ENABLE =
1022 (enable ? QSPI_XIP_ENC_ENABLE_ENABLE_Enabled << QSPI_XIP_ENC_ENABLE_ENABLE_Pos
1023 : QSPI_XIP_ENC_ENABLE_ENABLE_Disabled << QSPI_XIP_ENC_ENABLE_ENABLE_Pos);
1024 }
1025 #endif
1026
1027 #if NRF_QSPI_HAS_DMA_ENC
nrf_qspi_dma_encryption_configure(NRF_QSPI_Type * p_reg,nrf_qspi_encryption_t const * p_cfg)1028 NRF_STATIC_INLINE void nrf_qspi_dma_encryption_configure(NRF_QSPI_Type * p_reg,
1029 nrf_qspi_encryption_t const * p_cfg)
1030 {
1031 p_reg->DMA_ENC.KEY0 = p_cfg->key[0];
1032 p_reg->DMA_ENC.KEY1 = p_cfg->key[1];
1033 p_reg->DMA_ENC.KEY2 = p_cfg->key[2];
1034 p_reg->DMA_ENC.KEY3 = p_cfg->key[3];
1035 p_reg->DMA_ENC.NONCE0 = p_cfg->nonce[0];
1036 p_reg->DMA_ENC.NONCE1 = p_cfg->nonce[1];
1037 p_reg->DMA_ENC.NONCE2 = p_cfg->nonce[2];
1038 }
1039
nrf_qspi_dma_encryption_set(NRF_QSPI_Type * p_reg,bool enable)1040 NRF_STATIC_INLINE void nrf_qspi_dma_encryption_set(NRF_QSPI_Type * p_reg, bool enable)
1041 {
1042 p_reg->DMA_ENC.ENABLE =
1043 (enable ? QSPI_DMA_ENC_ENABLE_ENABLE_Enabled << QSPI_DMA_ENC_ENABLE_ENABLE_Pos
1044 : QSPI_DMA_ENC_ENABLE_ENABLE_Disabled << QSPI_DMA_ENC_ENABLE_ENABLE_Pos);
1045 }
1046 #endif
1047
nrf_qspi_iftiming_set(NRF_QSPI_Type * p_reg,uint8_t rxdelay)1048 NRF_STATIC_INLINE void nrf_qspi_iftiming_set(NRF_QSPI_Type * p_reg, uint8_t rxdelay)
1049 {
1050 p_reg->IFTIMING = ((uint32_t)rxdelay << QSPI_IFTIMING_RXDELAY_Pos) & QSPI_IFTIMING_RXDELAY_Msk;
1051 }
1052
1053 #endif // NRF_DECLARE_ONLY
1054
1055 /** @} */
1056
1057 #ifdef __cplusplus
1058 }
1059 #endif
1060
1061 #endif // NRF_QSPI_H__
1062
