1 /*
2 * Copyright (c) 2015 - 2024, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_PWM_H__
35 #define NRF_PWM_H__
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /**
44 * @defgroup nrf_pwm_hal PWM HAL
45 * @{
46 * @ingroup nrf_pwm
47 * @brief Hardware access layer for managing the Pulse Width Modulation (PWM) peripheral.
48 */
49
50 #if defined(PWM_DMA_SEQ_PTR_PTR_Msk) || defined(__NRFX_DOXYGEN__)
51 /** @brief Symbol indicating whether dedicated DMA register is present. */
52 #define NRF_PWM_HAS_DMA_REG 1
53 #else
54 #define NRF_PWM_HAS_DMA_REG 0
55 #endif
56
57 #if defined(PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk) || \
58 defined(PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Msk) || defined(__NRFX_DOXYGEN__)
59 /** @brief Symbol indicating whether shorting SEQSTART task with LOOPSDONE event is available. */
60 #define NRF_PWM_HAS_SHORT_LOOPSDONE_SEQSTART 1
61 #else
62 #define NRF_PWM_HAS_SHORT_LOOPSDONE_SEQSTART 0
63 #endif
64
65 #if (defined(PWM_TASKS_DMA_SEQ_START_START_Msk) && defined(PWM_EVENTS_DMA_SEQ_END_END_Msk)) || \
66 defined(__NRFX_DOXYGEN__)
67 /** @brief Symbol indicating whether PWM DMA tasks and events are present. */
68 #define NRF_PWM_HAS_DMA_TASKS_EVENTS 1
69 #else
70 #define NRF_PWM_HAS_DMA_TASKS_EVENTS 0
71 #endif
72
73 #if defined(PWM_SEQ_CNT_CNT_Msk) || defined(__NRFX_DOXYGEN__)
74 /** @brief Symbol indicating whether setting the number of duty cycle values for a sequence is available. */
75 #define NRF_PWM_HAS_SEQ_CNT 1
76 #else
77 #define NRF_PWM_HAS_SEQ_CNT 0
78 #endif
79
80 /**
81 * @brief Macro getting pointer to the structure of registers of the PWM peripheral.
82 *
83 * @param[in] idx PWM instance index.
84 *
85 * @return Pointer to the structure of registers of the PWM peripheral.
86 */
87 #define NRF_PWM_INST_GET(idx) NRFX_CONCAT(NRF_, PWM, idx)
88
89 /**
90 * @brief This value can be provided as a parameter for the @ref nrf_pwm_pins_set
91 * function call to specify that a given output channel shall not be
92 * connected to a physical pin.
93 */
94 #define NRF_PWM_PIN_NOT_CONNECTED 0xFFFFFFFF
95
96 /** @brief Number of channels in each PWM instance. */
97 #define NRF_PWM_CHANNEL_COUNT 4
98
99 /**
100 * @brief Helper macro for calculating the number of 16-bit values in the specified
101 * array of duty cycle values.
102 */
103 #define NRF_PWM_VALUES_LENGTH(array) (sizeof(array) / 2UL)
104
105
106 /** @brief PWM tasks. */
107 typedef enum
108 {
109 NRF_PWM_TASK_STOP = offsetof(NRF_PWM_Type, TASKS_STOP), ///< Stops PWM pulse generation on all channels at the end of the current PWM period, and stops the sequence playback.
110 #if NRF_PWM_HAS_DMA_TASKS_EVENTS
111 NRF_PWM_TASK_SEQSTART0 = offsetof(NRF_PWM_Type, TASKS_DMA.SEQ[0].START), ///< Starts playback of sequence 0.
112 NRF_PWM_TASK_SEQSTART1 = offsetof(NRF_PWM_Type, TASKS_DMA.SEQ[1].START), ///< Starts playback of sequence 1.
113 #else
114 NRF_PWM_TASK_SEQSTART0 = offsetof(NRF_PWM_Type, TASKS_SEQSTART[0]), ///< Starts playback of sequence 0.
115 NRF_PWM_TASK_SEQSTART1 = offsetof(NRF_PWM_Type, TASKS_SEQSTART[1]), ///< Starts playback of sequence 1.
116 #endif
117 NRF_PWM_TASK_NEXTSTEP = offsetof(NRF_PWM_Type, TASKS_NEXTSTEP) ///< Steps by one value in the current sequence if the decoder is set to @ref NRF_PWM_STEP_TRIGGERED mode.
118 } nrf_pwm_task_t;
119
120 /** @brief PWM events. */
121 typedef enum
122 {
123 NRF_PWM_EVENT_STOPPED = offsetof(NRF_PWM_Type, EVENTS_STOPPED), ///< Response to STOP task, emitted when PWM pulses are no longer generated.
124 NRF_PWM_EVENT_SEQSTARTED0 = offsetof(NRF_PWM_Type, EVENTS_SEQSTARTED[0]), ///< First PWM period started on sequence 0.
125 NRF_PWM_EVENT_SEQSTARTED1 = offsetof(NRF_PWM_Type, EVENTS_SEQSTARTED[1]), ///< First PWM period started on sequence 1.
126 NRF_PWM_EVENT_SEQEND0 = offsetof(NRF_PWM_Type, EVENTS_SEQEND[0]), ///< Emitted at the end of every sequence 0 when its last value has been read from RAM.
127 NRF_PWM_EVENT_SEQEND1 = offsetof(NRF_PWM_Type, EVENTS_SEQEND[1]), ///< Emitted at the end of every sequence 1 when its last value has been read from RAM.
128 NRF_PWM_EVENT_PWMPERIODEND = offsetof(NRF_PWM_Type, EVENTS_PWMPERIODEND), ///< Emitted at the end of each PWM period.
129 NRF_PWM_EVENT_LOOPSDONE = offsetof(NRF_PWM_Type, EVENTS_LOOPSDONE) ///< Concatenated sequences have been played the specified number of times.
130 } nrf_pwm_event_t;
131
132 /** @brief PWM interrupts. */
133 typedef enum
134 {
135 NRF_PWM_INT_STOPPED_MASK = PWM_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event.
136 NRF_PWM_INT_SEQSTARTED0_MASK = PWM_INTENSET_SEQSTARTED0_Msk, ///< Interrupt on SEQSTARTED[0] event.
137 NRF_PWM_INT_SEQSTARTED1_MASK = PWM_INTENSET_SEQSTARTED1_Msk, ///< Interrupt on SEQSTARTED[1] event.
138 NRF_PWM_INT_SEQEND0_MASK = PWM_INTENSET_SEQEND0_Msk, ///< Interrupt on SEQEND[0] event.
139 NRF_PWM_INT_SEQEND1_MASK = PWM_INTENSET_SEQEND1_Msk, ///< Interrupt on SEQEND[1] event.
140 NRF_PWM_INT_PWMPERIODEND_MASK = PWM_INTENSET_PWMPERIODEND_Msk, ///< Interrupt on PWMPERIODEND event.
141 NRF_PWM_INT_LOOPSDONE_MASK = PWM_INTENSET_LOOPSDONE_Msk ///< Interrupt on LOOPSDONE event.
142 } nrf_pwm_int_mask_t;
143
144 /** @brief PWM shortcuts. */
145 typedef enum
146 {
147 NRF_PWM_SHORT_SEQEND0_STOP_MASK = PWM_SHORTS_SEQEND0_STOP_Msk, ///< Shortcut between SEQEND[0] event and STOP task.
148 NRF_PWM_SHORT_SEQEND1_STOP_MASK = PWM_SHORTS_SEQEND1_STOP_Msk, ///< Shortcut between SEQEND[1] event and STOP task.
149 #if defined(PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk) || defined(__NRFX_DOXYGEN__)
150 NRF_PWM_SHORT_LOOPSDONE_SEQSTART0_MASK = PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk, ///< Shortcut between LOOPSDONE event and SEQSTART[0] task.
151 NRF_PWM_SHORT_LOOPSDONE_SEQSTART1_MASK = PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk, ///< Shortcut between LOOPSDONE event and SEQSTART[1] task.
152 #else
153 NRF_PWM_SHORT_LOOPSDONE_SEQSTART0_MASK = PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Msk, ///< Shortcut between LOOPSDONE event and DMA.SEQ[0].START task.
154 NRF_PWM_SHORT_LOOPSDONE_SEQSTART1_MASK = PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Msk, ///< Shortcut between LOOPSDONE event and DMA.SEQ[1].START task.
155 #endif
156 NRF_PWM_SHORT_LOOPSDONE_STOP_MASK = PWM_SHORTS_LOOPSDONE_STOP_Msk ///< Shortcut between LOOPSDONE event and STOP task.
157 } nrf_pwm_short_mask_t;
158
159 /** @brief PWM modes of operation. */
160 typedef enum
161 {
162 NRF_PWM_MODE_UP = PWM_MODE_UPDOWN_Up, ///< Up counter (edge-aligned PWM duty cycle).
163 NRF_PWM_MODE_UP_AND_DOWN = PWM_MODE_UPDOWN_UpAndDown, ///< Up and down counter (center-aligned PWM duty cycle).
164 } nrf_pwm_mode_t;
165
166 /** @brief PWM base clock frequencies. */
167 typedef enum
168 {
169 NRF_PWM_CLK_16MHz = PWM_PRESCALER_PRESCALER_DIV_1, ///< 16 MHz / 1 = 16 MHz.
170 NRF_PWM_CLK_8MHz = PWM_PRESCALER_PRESCALER_DIV_2, ///< 16 MHz / 2 = 8 MHz.
171 NRF_PWM_CLK_4MHz = PWM_PRESCALER_PRESCALER_DIV_4, ///< 16 MHz / 4 = 4 MHz.
172 NRF_PWM_CLK_2MHz = PWM_PRESCALER_PRESCALER_DIV_8, ///< 16 MHz / 8 = 2 MHz.
173 NRF_PWM_CLK_1MHz = PWM_PRESCALER_PRESCALER_DIV_16, ///< 16 MHz / 16 = 1 MHz.
174 NRF_PWM_CLK_500kHz = PWM_PRESCALER_PRESCALER_DIV_32, ///< 16 MHz / 32 = 500 kHz.
175 NRF_PWM_CLK_250kHz = PWM_PRESCALER_PRESCALER_DIV_64, ///< 16 MHz / 64 = 250 kHz.
176 NRF_PWM_CLK_125kHz = PWM_PRESCALER_PRESCALER_DIV_128 ///< 16 MHz / 128 = 125 kHz.
177 } nrf_pwm_clk_t;
178
179 /**
180 * @brief PWM decoder load modes.
181 *
182 * The selected mode determines how the sequence data is read from RAM and
183 * spread to the compare registers.
184 */
185 typedef enum
186 {
187 NRF_PWM_LOAD_COMMON = PWM_DECODER_LOAD_Common, ///< 1st half word (16-bit) used in all PWM channels (0-3).
188 NRF_PWM_LOAD_GROUPED = PWM_DECODER_LOAD_Grouped, ///< 1st half word (16-bit) used in channels 0 and 1; 2nd word in channels 2 and 3.
189 NRF_PWM_LOAD_INDIVIDUAL = PWM_DECODER_LOAD_Individual, ///< 1st half word (16-bit) used in channel 0; 2nd in channel 1; 3rd in channel 2; 4th in channel 3.
190 NRF_PWM_LOAD_WAVE_FORM = PWM_DECODER_LOAD_WaveForm ///< 1st half word (16-bit) used in channel 0; 2nd in channel 1; ... ; 4th as the top value for the pulse generator counter.
191 } nrf_pwm_dec_load_t;
192
193 /**
194 * @brief PWM decoder next step modes.
195 *
196 * The selected mode determines when the next value from the active sequence
197 * is loaded.
198 */
199 typedef enum
200 {
201 NRF_PWM_STEP_AUTO = PWM_DECODER_MODE_RefreshCount, ///< Automatically after the current value is played and repeated the requested number of times.
202 NRF_PWM_STEP_TRIGGERED = PWM_DECODER_MODE_NextStep ///< When the @ref NRF_PWM_TASK_NEXTSTEP task is triggered.
203 } nrf_pwm_dec_step_t;
204
205 /**
206 * @brief Type used for defining duty cycle values for a sequence
207 * loaded in @ref NRF_PWM_LOAD_COMMON mode.
208 */
209 typedef uint16_t nrf_pwm_values_common_t;
210
211 /**
212 * @brief Structure for defining duty cycle values for a sequence
213 * loaded in @ref NRF_PWM_LOAD_GROUPED mode.
214 */
215 typedef struct {
216 uint16_t group_0; ///< Duty cycle value for group 0 (channels 0 and 1).
217 uint16_t group_1; ///< Duty cycle value for group 1 (channels 2 and 3).
218 } nrf_pwm_values_grouped_t;
219
220 /**
221 * @brief Structure for defining duty cycle values for a sequence
222 * loaded in @ref NRF_PWM_LOAD_INDIVIDUAL mode.
223 */
224 typedef struct
225 {
226 uint16_t channel_0; ///< Duty cycle value for channel 0.
227 uint16_t channel_1; ///< Duty cycle value for channel 1.
228 uint16_t channel_2; ///< Duty cycle value for channel 2.
229 uint16_t channel_3; ///< Duty cycle value for channel 3.
230 } nrf_pwm_values_individual_t;
231
232 /**
233 * @brief Structure for defining duty cycle values for a sequence
234 * loaded in @ref NRF_PWM_LOAD_WAVE_FORM mode.
235 */
236 typedef struct {
237 uint16_t channel_0; ///< Duty cycle value for channel 0.
238 uint16_t channel_1; ///< Duty cycle value for channel 1.
239 uint16_t channel_2; ///< Duty cycle value for channel 2.
240 uint16_t counter_top; ///< Top value for the pulse generator counter.
241 } nrf_pwm_values_wave_form_t;
242
243 /**
244 * @brief Union grouping pointers to arrays of duty cycle values applicable to
245 * various loading modes.
246 */
247 typedef union {
248 nrf_pwm_values_common_t const * p_common; ///< Pointer to be used in @ref NRF_PWM_LOAD_COMMON mode.
249 nrf_pwm_values_grouped_t const * p_grouped; ///< Pointer to be used in @ref NRF_PWM_LOAD_GROUPED mode.
250 nrf_pwm_values_individual_t const * p_individual; ///< Pointer to be used in @ref NRF_PWM_LOAD_INDIVIDUAL mode.
251 nrf_pwm_values_wave_form_t const * p_wave_form; ///< Pointer to be used in @ref NRF_PWM_LOAD_WAVE_FORM mode.
252 uint16_t const * p_raw; ///< Pointer providing raw access to the values.
253 } nrf_pwm_values_t;
254
255 /**
256 * @brief Structure for defining a sequence of PWM duty cycles.
257 *
258 * When the sequence is set (by a call to @ref nrf_pwm_sequence_set), the
259 * provided duty cycle values are not copied. The @p values pointer is stored
260 * in the internal register of the peripheral, and the values are loaded from RAM
261 * during the sequence playback. Therefore, you must ensure that the values
262 * do not change before and during the sequence playback (for example,
263 * the values cannot be placed in a local variable that is allocated on stack).
264 * If the sequence is played in a loop and the values are to be updated
265 * before the next iteration, it is safe to modify them when the corresponding
266 * event signaling the end of sequence occurs (@ref NRF_PWM_EVENT_SEQEND0
267 * or @ref NRF_PWM_EVENT_SEQEND1, respectively).
268 *
269 * @note The @p repeats and @p end_delay values (which are written to the
270 * SEQ[n].REFRESH and SEQ[n].ENDDELAY registers in the peripheral,
271 * respectively) are ignored at the end of a complex sequence
272 * playback, indicated by the LOOPSDONE event.
273 * See the Product Specification for more information.
274 */
275 typedef struct
276 {
277 nrf_pwm_values_t values; ///< Pointer to an array with duty cycle values. This array must be in Data RAM.
278 /**< This field is defined as an union of pointers
279 * to provide a convenient way to define duty
280 * cycle values in various loading modes
281 * (see @ref nrf_pwm_dec_load_t).
282 * In each value, the most significant bit (15)
283 * determines the polarity of the output and the
284 * others (14-0) compose the 15-bit value to be
285 * compared with the pulse generator counter. */
286 uint16_t length; ///< Number of 16-bit values in the array pointed by @p values.
287 uint32_t repeats; ///< Number of times that each duty cycle is to be repeated (after being played once). Ignored in @ref NRF_PWM_STEP_TRIGGERED mode.
288 uint32_t end_delay; ///< Additional time (in PWM periods) that the last duty cycle is to be kept after the sequence is played. Ignored in @ref NRF_PWM_STEP_TRIGGERED mode.
289 } nrf_pwm_sequence_t;
290
291
292 /**
293 * @brief Function for activating the specified PWM task.
294 *
295 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
296 * @param[in] task Task to be activated.
297 */
298 NRF_STATIC_INLINE void nrf_pwm_task_trigger(NRF_PWM_Type * p_reg,
299 nrf_pwm_task_t task);
300
301 /**
302 * @brief Function for getting the address of the specified PWM task register.
303 *
304 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
305 * @param[in] task PWM task.
306 *
307 * @return Address of the specified task register.
308 */
309 NRF_STATIC_INLINE uint32_t nrf_pwm_task_address_get(NRF_PWM_Type const * p_reg,
310 nrf_pwm_task_t task);
311
312 /**
313 * @brief Function for clearing the specified PWM event.
314 *
315 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
316 * @param[in] event Event to clear.
317 */
318 NRF_STATIC_INLINE void nrf_pwm_event_clear(NRF_PWM_Type * p_reg,
319 nrf_pwm_event_t event);
320
321 /**
322 * @brief Function for retrieving the state of the PWM event.
323 *
324 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
325 * @param[in] event Event to be checked.
326 *
327 * @retval true The event has been generated.
328 * @retval false The event has not been generated.
329 */
330 NRF_STATIC_INLINE bool nrf_pwm_event_check(NRF_PWM_Type const * p_reg,
331 nrf_pwm_event_t event);
332
333 /**
334 * @brief Function for getting the address of the specified PWM event register.
335 *
336 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
337 * @param[in] event PWM event.
338 *
339 * @return Address of the specified event register.
340 */
341 NRF_STATIC_INLINE uint32_t nrf_pwm_event_address_get(NRF_PWM_Type const * p_reg,
342 nrf_pwm_event_t event);
343
344 /**
345 * @brief Function for enabling the specified shortcuts.
346 *
347 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
348 * @param[in] mask Mask of shortcuts to be enabled.
349 */
350 NRF_STATIC_INLINE void nrf_pwm_shorts_enable(NRF_PWM_Type * p_reg,
351 uint32_t mask);
352
353 /**
354 * @brief Function for disabling the specified shortcuts.
355 *
356 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
357 * @param[in] mask Mask of shortcuts to be disabled.
358 */
359 NRF_STATIC_INLINE void nrf_pwm_shorts_disable(NRF_PWM_Type * p_reg,
360 uint32_t mask);
361
362 /**
363 * @brief Function for setting the configuration of PWM shortcuts.
364 *
365 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
366 * @param[in] mask Shortcuts configuration to be set.
367 */
368 NRF_STATIC_INLINE void nrf_pwm_shorts_set(NRF_PWM_Type * p_reg,
369 uint32_t mask);
370
371 /**
372 * @brief Function for enabling specified interrupts.
373 *
374 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
375 * @param[in] mask Mask of interrupts to be enabled.
376 * Use @ref nrf_pwm_int_mask_t values for bit masking.
377 */
378 NRF_STATIC_INLINE void nrf_pwm_int_enable(NRF_PWM_Type * p_reg,
379 uint32_t mask);
380
381 /**
382 * @brief Function for disabling specified interrupts.
383 *
384 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
385 * @param[in] mask Mask of interrupts to be disabled.
386 * Use @ref nrf_pwm_int_mask_t values for bit masking.
387 */
388 NRF_STATIC_INLINE void nrf_pwm_int_disable(NRF_PWM_Type * p_reg,
389 uint32_t mask);
390
391 /**
392 * @brief Function for setting the configuration of PWM interrupts.
393 *
394 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
395 * @param[in] mask Mask of interrupts to be set.
396 * Use @ref nrf_pwm_int_mask_t values for bit masking.
397 */
398 NRF_STATIC_INLINE void nrf_pwm_int_set(NRF_PWM_Type * p_reg,
399 uint32_t mask);
400
401 /**
402 * @brief Function for checking if the specified interrupts are enabled.
403 *
404 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
405 * @param[in] mask Mask of interrupts to be checked.
406 * Use @ref nrf_pwm_int_mask_t values for bit masking.
407 *
408 * @return Mask of enabled interrupts.
409 */
410 NRF_STATIC_INLINE uint32_t nrf_pwm_int_enable_check(NRF_PWM_Type const * p_reg, uint32_t mask);
411
412 #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
413 /**
414 * @brief Function for setting the subscribe configuration for a given
415 * PWM task.
416 *
417 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
418 * @param[in] task Task for which to set the configuration.
419 * @param[in] channel Channel through which to subscribe events.
420 */
421 NRF_STATIC_INLINE void nrf_pwm_subscribe_set(NRF_PWM_Type * p_reg,
422 nrf_pwm_task_t task,
423 uint8_t channel);
424
425 /**
426 * @brief Function for clearing the subscribe configuration for a given
427 * PWM task.
428 *
429 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
430 * @param[in] task Task for which to clear the configuration.
431 */
432 NRF_STATIC_INLINE void nrf_pwm_subscribe_clear(NRF_PWM_Type * p_reg,
433 nrf_pwm_task_t task);
434
435 /**
436 * @brief Function for setting the publish configuration for a given
437 * PWM event.
438 *
439 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
440 * @param[in] event Event for which to set the configuration.
441 * @param[in] channel Channel through which to publish the event.
442 */
443 NRF_STATIC_INLINE void nrf_pwm_publish_set(NRF_PWM_Type * p_reg,
444 nrf_pwm_event_t event,
445 uint8_t channel);
446
447 /**
448 * @brief Function for clearing the publish configuration for a given
449 * PWM event.
450 *
451 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
452 * @param[in] event Event for which to clear the configuration.
453 */
454 NRF_STATIC_INLINE void nrf_pwm_publish_clear(NRF_PWM_Type * p_reg,
455 nrf_pwm_event_t event);
456 #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
457
458 /**
459 * @brief Function for enabling the PWM peripheral.
460 *
461 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
462 */
463 NRF_STATIC_INLINE void nrf_pwm_enable(NRF_PWM_Type * p_reg);
464
465 /**
466 * @brief Function for disabling the PWM peripheral.
467 *
468 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
469 */
470 NRF_STATIC_INLINE void nrf_pwm_disable(NRF_PWM_Type * p_reg);
471
472 /**
473 * @brief Function for checking if the PWM peripheral is enabled.
474 *
475 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
476 *
477 * @retval true The PWM is enabled.
478 * @retval false The PWM is not enabled.
479 */
480 NRF_STATIC_INLINE bool nrf_pwm_enable_check(NRF_PWM_Type const * p_reg);
481
482 /**
483 * @brief Function for assigning pins to PWM output channels.
484 *
485 * Usage of all PWM output channels is optional. If a given channel is not
486 * needed, pass the @ref NRF_PWM_PIN_NOT_CONNECTED value instead of its pin
487 * number.
488 *
489 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
490 * @param[in] out_pins Array with pin numbers for individual PWM output channels.
491 */
492 NRF_STATIC_INLINE void nrf_pwm_pins_set(NRF_PWM_Type * p_reg,
493 uint32_t const out_pins[NRF_PWM_CHANNEL_COUNT]);
494
495 /**
496 * @brief Function for getting pin selection associated with specified PWM output channel.
497 *
498 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
499 * @param[in] channel PWM output channel.
500 *
501 * @return Pin selection associated with specified PWM output channel.
502 */
503 NRF_STATIC_INLINE uint32_t nrf_pwm_pin_get(NRF_PWM_Type const * p_reg, uint8_t channel);
504
505 /**
506 * @brief Function for configuring the PWM peripheral.
507 *
508 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
509 * @param[in] base_clock Base clock frequency.
510 * @param[in] mode Operating mode of the pulse generator counter.
511 * @param[in] top_value Value up to which the pulse generator counter counts.
512 */
513 NRF_STATIC_INLINE void nrf_pwm_configure(NRF_PWM_Type * p_reg,
514 nrf_pwm_clk_t base_clock,
515 nrf_pwm_mode_t mode,
516 uint16_t top_value);
517
518 /**
519 * @brief Function for defining a sequence of PWM duty cycles.
520 *
521 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
522 * @param[in] seq_id Identifier of the sequence (0 or 1).
523 * @param[in] p_seq Pointer to the sequence definition.
524 */
525 NRF_STATIC_INLINE void nrf_pwm_sequence_set(NRF_PWM_Type * p_reg,
526 uint8_t seq_id,
527 nrf_pwm_sequence_t const * p_seq);
528
529 /**
530 * @brief Function for modifying the pointer to the duty cycle values
531 * in the specified sequence.
532 *
533 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
534 * @param[in] seq_id Identifier of the sequence (0 or 1).
535 * @param[in] p_values Pointer to an array with duty cycle values.
536 */
537 NRF_STATIC_INLINE void nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_reg,
538 uint8_t seq_id,
539 uint16_t const * p_values);
540
541 /**
542 * @brief Function for modifying the total number of duty cycle values
543 * in the specified sequence.
544 *
545 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
546 * @param[in] seq_id Identifier of the sequence (0 or 1).
547 * @param[in] length Number of duty cycle values (in 16-bit half words).
548 */
549 NRF_STATIC_INLINE void nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_reg,
550 uint8_t seq_id,
551 uint16_t length);
552
553 /**
554 * @brief Function for modifying the additional number of PWM periods spent
555 * on each duty cycle value in the specified sequence.
556 *
557 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
558 * @param[in] seq_id Identifier of the sequence (0 or 1).
559 * @param[in] refresh Number of additional PWM periods for each duty cycle value.
560 */
561 NRF_STATIC_INLINE void nrf_pwm_seq_refresh_set(NRF_PWM_Type * p_reg,
562 uint8_t seq_id,
563 uint32_t refresh);
564
565 /**
566 * @brief Function for modifying the additional time added after the sequence
567 * is played.
568 *
569 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
570 * @param[in] seq_id Identifier of the sequence (0 or 1).
571 * @param[in] end_delay Number of PWM periods added at the end of the sequence.
572 */
573 NRF_STATIC_INLINE void nrf_pwm_seq_end_delay_set(NRF_PWM_Type * p_reg,
574 uint8_t seq_id,
575 uint32_t end_delay);
576
577 /**
578 * @brief Function for setting the mode of loading sequence data from RAM
579 * and advancing the sequence.
580 *
581 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
582 * @param[in] dec_load Mode of loading sequence data from RAM.
583 * @param[in] dec_step Mode of advancing the active sequence.
584 */
585 NRF_STATIC_INLINE void nrf_pwm_decoder_set(NRF_PWM_Type * p_reg,
586 nrf_pwm_dec_load_t dec_load,
587 nrf_pwm_dec_step_t dec_step);
588
589 /**
590 * @brief Function for setting the number of times the sequence playback
591 * should be performed.
592 *
593 * This function applies to two-sequence playback (concatenated sequence 0 and 1).
594 * A single sequence can be played back only once.
595 *
596 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
597 * @param[in] loop_count Number of times to perform the sequence playback.
598 */
599 NRF_STATIC_INLINE void nrf_pwm_loop_set(NRF_PWM_Type * p_reg, uint16_t loop_count);
600
601 /**
602 * @brief Function for getting the specified PWM SEQSTART task.
603 *
604 * @param[in] seq_id Sequence index.
605 *
606 * @return The specified PWM SEQSTART task.
607 */
608 NRF_STATIC_INLINE nrf_pwm_task_t nrf_pwm_seqstart_task_get(uint8_t seq_id);
609
610 /**
611 * @brief Function for getting the specified PWM SEQEND event.
612 *
613 * @param[in] seq_id Sequence index.
614 *
615 * @return The specified PWM SEQEND event.
616 */
617 NRF_STATIC_INLINE nrf_pwm_event_t nrf_pwm_seqend_event_get(uint8_t seq_id);
618
619
620 #ifndef NRF_DECLARE_ONLY
621
nrf_pwm_task_trigger(NRF_PWM_Type * p_reg,nrf_pwm_task_t task)622 NRF_STATIC_INLINE void nrf_pwm_task_trigger(NRF_PWM_Type * p_reg,
623 nrf_pwm_task_t task)
624 {
625 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
626 }
627
nrf_pwm_task_address_get(NRF_PWM_Type const * p_reg,nrf_pwm_task_t task)628 NRF_STATIC_INLINE uint32_t nrf_pwm_task_address_get(NRF_PWM_Type const * p_reg,
629 nrf_pwm_task_t task)
630 {
631 return ((uint32_t)p_reg + (uint32_t)task);
632 }
633
nrf_pwm_event_clear(NRF_PWM_Type * p_reg,nrf_pwm_event_t event)634 NRF_STATIC_INLINE void nrf_pwm_event_clear(NRF_PWM_Type * p_reg,
635 nrf_pwm_event_t event)
636 {
637 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
638 nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
639 }
640
nrf_pwm_event_check(NRF_PWM_Type const * p_reg,nrf_pwm_event_t event)641 NRF_STATIC_INLINE bool nrf_pwm_event_check(NRF_PWM_Type const * p_reg,
642 nrf_pwm_event_t event)
643 {
644 return nrf_event_check(p_reg, event);
645 }
646
nrf_pwm_event_address_get(NRF_PWM_Type const * p_reg,nrf_pwm_event_t event)647 NRF_STATIC_INLINE uint32_t nrf_pwm_event_address_get(NRF_PWM_Type const * p_reg,
648 nrf_pwm_event_t event)
649 {
650 return ((uint32_t)p_reg + (uint32_t)event);
651 }
652
nrf_pwm_shorts_enable(NRF_PWM_Type * p_reg,uint32_t mask)653 NRF_STATIC_INLINE void nrf_pwm_shorts_enable(NRF_PWM_Type * p_reg, uint32_t mask)
654 {
655 p_reg->SHORTS |= mask;
656 }
657
nrf_pwm_shorts_disable(NRF_PWM_Type * p_reg,uint32_t mask)658 NRF_STATIC_INLINE void nrf_pwm_shorts_disable(NRF_PWM_Type * p_reg, uint32_t mask)
659 {
660 p_reg->SHORTS &= ~(mask);
661 }
662
nrf_pwm_shorts_set(NRF_PWM_Type * p_reg,uint32_t mask)663 NRF_STATIC_INLINE void nrf_pwm_shorts_set(NRF_PWM_Type * p_reg, uint32_t mask)
664 {
665 p_reg->SHORTS = mask;
666 }
667
nrf_pwm_int_enable(NRF_PWM_Type * p_reg,uint32_t mask)668 NRF_STATIC_INLINE void nrf_pwm_int_enable(NRF_PWM_Type * p_reg, uint32_t mask)
669 {
670 p_reg->INTENSET = mask;
671 }
672
nrf_pwm_int_disable(NRF_PWM_Type * p_reg,uint32_t mask)673 NRF_STATIC_INLINE void nrf_pwm_int_disable(NRF_PWM_Type * p_reg, uint32_t mask)
674 {
675 p_reg->INTENCLR = mask;
676 }
677
nrf_pwm_int_set(NRF_PWM_Type * p_reg,uint32_t mask)678 NRF_STATIC_INLINE void nrf_pwm_int_set(NRF_PWM_Type * p_reg, uint32_t mask)
679 {
680 p_reg->INTEN = mask;
681 }
682
nrf_pwm_int_enable_check(NRF_PWM_Type const * p_reg,uint32_t mask)683 NRF_STATIC_INLINE uint32_t nrf_pwm_int_enable_check(NRF_PWM_Type const * p_reg, uint32_t mask)
684 {
685 return p_reg->INTENSET & mask;
686 }
687
688 #if defined(DPPI_PRESENT)
nrf_pwm_subscribe_set(NRF_PWM_Type * p_reg,nrf_pwm_task_t task,uint8_t channel)689 NRF_STATIC_INLINE void nrf_pwm_subscribe_set(NRF_PWM_Type * p_reg,
690 nrf_pwm_task_t task,
691 uint8_t channel)
692 {
693 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
694 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
695 }
696
nrf_pwm_subscribe_clear(NRF_PWM_Type * p_reg,nrf_pwm_task_t task)697 NRF_STATIC_INLINE void nrf_pwm_subscribe_clear(NRF_PWM_Type * p_reg,
698 nrf_pwm_task_t task)
699 {
700 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
701 }
702
nrf_pwm_publish_set(NRF_PWM_Type * p_reg,nrf_pwm_event_t event,uint8_t channel)703 NRF_STATIC_INLINE void nrf_pwm_publish_set(NRF_PWM_Type * p_reg,
704 nrf_pwm_event_t event,
705 uint8_t channel)
706 {
707 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
708 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
709 }
710
nrf_pwm_publish_clear(NRF_PWM_Type * p_reg,nrf_pwm_event_t event)711 NRF_STATIC_INLINE void nrf_pwm_publish_clear(NRF_PWM_Type * p_reg,
712 nrf_pwm_event_t event)
713 {
714 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
715 }
716 #endif // defined(DPPI_PRESENT)
717
nrf_pwm_enable(NRF_PWM_Type * p_reg)718 NRF_STATIC_INLINE void nrf_pwm_enable(NRF_PWM_Type * p_reg)
719 {
720 p_reg->ENABLE = (PWM_ENABLE_ENABLE_Enabled << PWM_ENABLE_ENABLE_Pos);
721 }
722
nrf_pwm_disable(NRF_PWM_Type * p_reg)723 NRF_STATIC_INLINE void nrf_pwm_disable(NRF_PWM_Type * p_reg)
724 {
725 p_reg->ENABLE = (PWM_ENABLE_ENABLE_Disabled << PWM_ENABLE_ENABLE_Pos);
726 }
727
nrf_pwm_enable_check(NRF_PWM_Type const * p_reg)728 NRF_STATIC_INLINE bool nrf_pwm_enable_check(NRF_PWM_Type const * p_reg)
729 {
730 return p_reg->ENABLE == PWM_ENABLE_ENABLE_Enabled;
731 }
732
nrf_pwm_pins_set(NRF_PWM_Type * p_reg,uint32_t const out_pins[NRF_PWM_CHANNEL_COUNT])733 NRF_STATIC_INLINE void nrf_pwm_pins_set(NRF_PWM_Type * p_reg,
734 uint32_t const out_pins[NRF_PWM_CHANNEL_COUNT])
735 {
736 uint8_t i;
737 for (i = 0; i < NRF_PWM_CHANNEL_COUNT; ++i)
738 {
739 p_reg->PSEL.OUT[i] = out_pins[i];
740 }
741 }
742
nrf_pwm_pin_get(NRF_PWM_Type const * p_reg,uint8_t channel)743 NRF_STATIC_INLINE uint32_t nrf_pwm_pin_get(NRF_PWM_Type const * p_reg, uint8_t channel)
744 {
745 NRFX_ASSERT(channel < NRF_PWM_CHANNEL_COUNT);
746 return p_reg->PSEL.OUT[channel];
747 }
748
nrf_pwm_configure(NRF_PWM_Type * p_reg,nrf_pwm_clk_t base_clock,nrf_pwm_mode_t mode,uint16_t top_value)749 NRF_STATIC_INLINE void nrf_pwm_configure(NRF_PWM_Type * p_reg,
750 nrf_pwm_clk_t base_clock,
751 nrf_pwm_mode_t mode,
752 uint16_t top_value)
753 {
754 NRFX_ASSERT(top_value <= PWM_COUNTERTOP_COUNTERTOP_Msk);
755
756 p_reg->PRESCALER = base_clock;
757 p_reg->MODE = mode;
758 p_reg->COUNTERTOP = top_value;
759 }
760
nrf_pwm_sequence_set(NRF_PWM_Type * p_reg,uint8_t seq_id,nrf_pwm_sequence_t const * p_seq)761 NRF_STATIC_INLINE void nrf_pwm_sequence_set(NRF_PWM_Type * p_reg,
762 uint8_t seq_id,
763 nrf_pwm_sequence_t const * p_seq)
764 {
765 NRFX_ASSERT(p_seq != NULL);
766
767 nrf_pwm_seq_ptr_set( p_reg, seq_id, p_seq->values.p_raw);
768 nrf_pwm_seq_cnt_set( p_reg, seq_id, p_seq->length);
769 nrf_pwm_seq_refresh_set( p_reg, seq_id, p_seq->repeats);
770 nrf_pwm_seq_end_delay_set(p_reg, seq_id, p_seq->end_delay);
771 }
772
nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_reg,uint8_t seq_id,uint16_t const * p_values)773 NRF_STATIC_INLINE void nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_reg,
774 uint8_t seq_id,
775 uint16_t const * p_values)
776 {
777 NRFX_ASSERT(seq_id <= 1);
778 NRFX_ASSERT(p_values != NULL);
779 #if NRF_PWM_HAS_DMA_REG
780 p_reg->DMA.SEQ[seq_id].PTR = (uint32_t)p_values;
781 #else
782 p_reg->SEQ[seq_id].PTR = (uint32_t)p_values;
783 #endif
784 }
785
nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_reg,uint8_t seq_id,uint16_t length)786 NRF_STATIC_INLINE void nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_reg,
787 uint8_t seq_id,
788 uint16_t length)
789 {
790 NRFX_ASSERT(seq_id <= 1);
791 NRFX_ASSERT(length != 0);
792 #if NRF_PWM_HAS_DMA_REG
793 NRFX_ASSERT(length * sizeof(uint16_t) <= PWM_DMA_SEQ_MAXCNT_MAXCNT_Msk);
794 p_reg->DMA.SEQ[seq_id].MAXCNT = length * sizeof(uint16_t);
795 #else
796 NRFX_ASSERT(length <= PWM_SEQ_CNT_CNT_Msk);
797 p_reg->SEQ[seq_id].CNT = length;
798 #endif
799 }
800
nrf_pwm_seq_refresh_set(NRF_PWM_Type * p_reg,uint8_t seq_id,uint32_t refresh)801 NRF_STATIC_INLINE void nrf_pwm_seq_refresh_set(NRF_PWM_Type * p_reg,
802 uint8_t seq_id,
803 uint32_t refresh)
804 {
805 NRFX_ASSERT(seq_id <= 1);
806 NRFX_ASSERT(refresh <= PWM_SEQ_REFRESH_CNT_Msk);
807 p_reg->SEQ[seq_id].REFRESH = refresh;
808 }
809
nrf_pwm_seq_end_delay_set(NRF_PWM_Type * p_reg,uint8_t seq_id,uint32_t end_delay)810 NRF_STATIC_INLINE void nrf_pwm_seq_end_delay_set(NRF_PWM_Type * p_reg,
811 uint8_t seq_id,
812 uint32_t end_delay)
813 {
814 NRFX_ASSERT(seq_id <= 1);
815 NRFX_ASSERT(end_delay <= PWM_SEQ_ENDDELAY_CNT_Msk);
816 p_reg->SEQ[seq_id].ENDDELAY = end_delay;
817 }
818
nrf_pwm_decoder_set(NRF_PWM_Type * p_reg,nrf_pwm_dec_load_t dec_load,nrf_pwm_dec_step_t dec_step)819 NRF_STATIC_INLINE void nrf_pwm_decoder_set(NRF_PWM_Type * p_reg,
820 nrf_pwm_dec_load_t dec_load,
821 nrf_pwm_dec_step_t dec_step)
822 {
823 p_reg->DECODER = ((uint32_t)dec_load << PWM_DECODER_LOAD_Pos) |
824 ((uint32_t)dec_step << PWM_DECODER_MODE_Pos);
825 }
826
nrf_pwm_loop_set(NRF_PWM_Type * p_reg,uint16_t loop_count)827 NRF_STATIC_INLINE void nrf_pwm_loop_set(NRF_PWM_Type * p_reg,
828 uint16_t loop_count)
829 {
830 p_reg->LOOP = loop_count;
831 }
832
nrf_pwm_seqstart_task_get(uint8_t seq_id)833 NRF_STATIC_INLINE nrf_pwm_task_t nrf_pwm_seqstart_task_get(uint8_t seq_id)
834 {
835 NRFX_ASSERT(seq_id <= 1);
836 #if NRF_PWM_HAS_DMA_TASKS_EVENTS
837 return (nrf_pwm_task_t)NRFX_OFFSETOF(NRF_PWM_Type, TASKS_DMA.SEQ[seq_id].START);
838 #else
839 return (nrf_pwm_task_t)NRFX_OFFSETOF(NRF_PWM_Type, TASKS_SEQSTART[seq_id]);
840 #endif
841 }
842
nrf_pwm_seqend_event_get(uint8_t seq_id)843 NRF_STATIC_INLINE nrf_pwm_event_t nrf_pwm_seqend_event_get(uint8_t seq_id)
844 {
845 NRFX_ASSERT(seq_id <= 1);
846 #if NRF_PWM_HAS_DMA_TASKS_EVENTS
847 return (nrf_pwm_event_t)NRFX_OFFSETOF(NRF_PWM_Type, EVENTS_DMA.SEQ[seq_id].END);
848 #else
849 return (nrf_pwm_event_t)NRFX_OFFSETOF(NRF_PWM_Type, EVENTS_SEQEND[seq_id]);
850 #endif
851 }
852
853 #endif // NRF_DECLARE_ONLY
854
855 /** @} */
856
857 #ifdef __cplusplus
858 }
859 #endif
860
861 #endif // NRF_PWM_H__
862
863
