1 /*
2 * Copyright (c) 2015 - 2024, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_PPI_H__
35 #define NRF_PPI_H__
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /**
44 * @defgroup nrf_ppi_hal PPI HAL
45 * @{
46 * @ingroup nrf_ppi
47 * @brief Hardware access layer (HAL) for managing the Programmable Peripheral Interconnect (PPI)
48 * channels.
49 */
50
51 /** @brief PPI channels. */
52 typedef enum
53 {
54 NRF_PPI_CHANNEL0 = PPI_CHEN_CH0_Pos, /**< Channel 0. */
55 NRF_PPI_CHANNEL1 = PPI_CHEN_CH1_Pos, /**< Channel 1. */
56 NRF_PPI_CHANNEL2 = PPI_CHEN_CH2_Pos, /**< Channel 2. */
57 NRF_PPI_CHANNEL3 = PPI_CHEN_CH3_Pos, /**< Channel 3. */
58 NRF_PPI_CHANNEL4 = PPI_CHEN_CH4_Pos, /**< Channel 4. */
59 NRF_PPI_CHANNEL5 = PPI_CHEN_CH5_Pos, /**< Channel 5. */
60 NRF_PPI_CHANNEL6 = PPI_CHEN_CH6_Pos, /**< Channel 6. */
61 NRF_PPI_CHANNEL7 = PPI_CHEN_CH7_Pos, /**< Channel 7. */
62 NRF_PPI_CHANNEL8 = PPI_CHEN_CH8_Pos, /**< Channel 8. */
63 NRF_PPI_CHANNEL9 = PPI_CHEN_CH9_Pos, /**< Channel 9. */
64 #if (PPI_CH_NUM > 10) || defined(__NRFX_DOXYGEN__)
65 NRF_PPI_CHANNEL10 = PPI_CHEN_CH10_Pos, /**< Channel 10. */
66 NRF_PPI_CHANNEL11 = PPI_CHEN_CH11_Pos, /**< Channel 11. */
67 NRF_PPI_CHANNEL12 = PPI_CHEN_CH12_Pos, /**< Channel 12. */
68 NRF_PPI_CHANNEL13 = PPI_CHEN_CH13_Pos, /**< Channel 13. */
69 NRF_PPI_CHANNEL14 = PPI_CHEN_CH14_Pos, /**< Channel 14. */
70 NRF_PPI_CHANNEL15 = PPI_CHEN_CH15_Pos, /**< Channel 15. */
71 #endif
72 #if (PPI_CH_NUM > 16) || defined(__NRFX_DOXYGEN__)
73 NRF_PPI_CHANNEL16 = PPI_CHEN_CH16_Pos, /**< Channel 16. */
74 NRF_PPI_CHANNEL17 = PPI_CHEN_CH17_Pos, /**< Channel 17. */
75 NRF_PPI_CHANNEL18 = PPI_CHEN_CH18_Pos, /**< Channel 18. */
76 NRF_PPI_CHANNEL19 = PPI_CHEN_CH19_Pos, /**< Channel 19. */
77 #endif
78 NRF_PPI_CHANNEL20 = PPI_CHEN_CH20_Pos, /**< Channel 20. */
79 NRF_PPI_CHANNEL21 = PPI_CHEN_CH21_Pos, /**< Channel 21. */
80 NRF_PPI_CHANNEL22 = PPI_CHEN_CH22_Pos, /**< Channel 22. */
81 NRF_PPI_CHANNEL23 = PPI_CHEN_CH23_Pos, /**< Channel 23. */
82 NRF_PPI_CHANNEL24 = PPI_CHEN_CH24_Pos, /**< Channel 24. */
83 NRF_PPI_CHANNEL25 = PPI_CHEN_CH25_Pos, /**< Channel 25. */
84 NRF_PPI_CHANNEL26 = PPI_CHEN_CH26_Pos, /**< Channel 26. */
85 NRF_PPI_CHANNEL27 = PPI_CHEN_CH27_Pos, /**< Channel 27. */
86 NRF_PPI_CHANNEL28 = PPI_CHEN_CH28_Pos, /**< Channel 28. */
87 NRF_PPI_CHANNEL29 = PPI_CHEN_CH29_Pos, /**< Channel 29. */
88 NRF_PPI_CHANNEL30 = PPI_CHEN_CH30_Pos, /**< Channel 30. */
89 NRF_PPI_CHANNEL31 = PPI_CHEN_CH31_Pos /**< Channel 31. */
90 } nrf_ppi_channel_t;
91
92 /** @brief PPI channel groups. */
93 typedef enum
94 {
95 NRF_PPI_CHANNEL_GROUP0 = 0, /**< Channel group 0. */
96 NRF_PPI_CHANNEL_GROUP1 = 1, /**< Channel group 1. */
97 NRF_PPI_CHANNEL_GROUP2 = 2, /**< Channel group 2. */
98 NRF_PPI_CHANNEL_GROUP3 = 3, /**< Channel group 3. */
99 #if (PPI_GROUP_NUM > 4) || defined(__NRFX_DOXYGEN__)
100 NRF_PPI_CHANNEL_GROUP4 = 4, /**< Channel group 4. */
101 NRF_PPI_CHANNEL_GROUP5 = 5 /**< Channel group 5. */
102 #endif
103 } nrf_ppi_channel_group_t;
104
105 /** @brief Definition of whether a PPI channel belongs to a group. */
106 typedef enum
107 {
108 NRF_PPI_CHANNEL_EXCLUDE = PPI_CHG_CH0_Excluded, /**< Channel excluded from a group. */
109 NRF_PPI_CHANNEL_INCLUDE = PPI_CHG_CH0_Included /**< Channel included in a group. */
110 } nrf_ppi_channel_include_t;
111
112 /** @brief Definition of whether a PPI channel is enabled. */
113 typedef enum
114 {
115 NRF_PPI_CHANNEL_DISABLED = PPI_CHEN_CH0_Disabled, /**< Channel disabled. */
116 NRF_PPI_CHANNEL_ENABLED = PPI_CHEN_CH0_Enabled /**< Channel enabled. */
117 } nrf_ppi_channel_enable_t;
118
119 /** @brief PPI tasks. */
120 typedef enum
121 {
122 NRF_PPI_TASK_CHG0_EN = offsetof(NRF_PPI_Type, TASKS_CHG[0].EN), /**< Task for enabling channel group 0. */
123 NRF_PPI_TASK_CHG0_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[0].DIS), /**< Task for disabling channel group 0. */
124 NRF_PPI_TASK_CHG1_EN = offsetof(NRF_PPI_Type, TASKS_CHG[1].EN), /**< Task for enabling channel group 1. */
125 NRF_PPI_TASK_CHG1_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[1].DIS), /**< Task for disabling channel group 1. */
126 NRF_PPI_TASK_CHG2_EN = offsetof(NRF_PPI_Type, TASKS_CHG[2].EN), /**< Task for enabling channel group 2. */
127 NRF_PPI_TASK_CHG2_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[2].DIS), /**< Task for disabling channel group 2. */
128 NRF_PPI_TASK_CHG3_EN = offsetof(NRF_PPI_Type, TASKS_CHG[3].EN), /**< Task for enabling channel group 3. */
129 NRF_PPI_TASK_CHG3_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[3].DIS), /**< Task for disabling channel group 3. */
130 #if (PPI_GROUP_NUM > 4) || defined(__NRFX_DOXYGEN__)
131 NRF_PPI_TASK_CHG4_EN = offsetof(NRF_PPI_Type, TASKS_CHG[4].EN), /**< Task for enabling channel group 4. */
132 NRF_PPI_TASK_CHG4_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[4].DIS), /**< Task for disabling channel group 4. */
133 NRF_PPI_TASK_CHG5_EN = offsetof(NRF_PPI_Type, TASKS_CHG[5].EN), /**< Task for enabling channel group 5. */
134 NRF_PPI_TASK_CHG5_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[5].DIS) /**< Task for disabling channel group 5. */
135 #endif
136 } nrf_ppi_task_t;
137
138
139 /**
140 * @brief Function for enabling a given PPI channel.
141 *
142 * @details This function enables only one channel.
143 *
144 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
145 * @param[in] channel Channel to be enabled.
146 */
147 NRF_STATIC_INLINE void nrf_ppi_channel_enable(NRF_PPI_Type * p_reg, nrf_ppi_channel_t channel);
148
149 /**
150 * @brief Function for disabling a given PPI channel.
151 *
152 * @details This function disables only one channel.
153 *
154 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
155 * @param[in] channel Channel to be disabled.
156 */
157 NRF_STATIC_INLINE void nrf_ppi_channel_disable(NRF_PPI_Type * p_reg, nrf_ppi_channel_t channel);
158
159 /**
160 * @brief Function for checking if a given PPI channel is enabled.
161 *
162 * @details This function checks only one channel.
163 *
164 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
165 * @param[in] channel Channel to be checked.
166 *
167 * @retval NRF_PPI_CHANNEL_ENABLED The channel is enabled.
168 * @retval NRF_PPI_CHANNEL_DISABLED The channel is not enabled.
169 *
170 */
171 NRF_STATIC_INLINE nrf_ppi_channel_enable_t nrf_ppi_channel_enable_get(NRF_PPI_Type const * p_reg,
172 nrf_ppi_channel_t channel);
173
174 /**
175 * @brief Function for disabling all PPI channels.
176 *
177 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
178 */
179 NRF_STATIC_INLINE void nrf_ppi_channels_disable_all(NRF_PPI_Type * p_reg);
180
181 /**
182 * @brief Function for enabling multiple PPI channels.
183 *
184 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
185 * @param[in] mask Channel mask.
186 */
187 NRF_STATIC_INLINE void nrf_ppi_channels_enable(NRF_PPI_Type * p_reg, uint32_t mask);
188
189 /**
190 * @brief Function for disabling multiple PPI channels.
191 *
192 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
193 * @param[in] mask Channel mask.
194 */
195 NRF_STATIC_INLINE void nrf_ppi_channels_disable(NRF_PPI_Type * p_reg, uint32_t mask);
196
197 /**
198 * @brief Function for setting up event and task endpoints for a given PPI channel.
199 *
200 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
201 * @param[in] eep Event register address.
202 * @param[in] tep Task register address.
203 * @param[in] channel Channel to which the given endpoints are assigned.
204 */
205 NRF_STATIC_INLINE void nrf_ppi_channel_endpoint_setup(NRF_PPI_Type * p_reg,
206 nrf_ppi_channel_t channel,
207 uint32_t eep,
208 uint32_t tep);
209
210 /**
211 * @brief Function for setting up the event endpoint for a given PPI channel.
212 *
213 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
214 * @param[in] eep Event register address.
215 * @param[in] channel Channel to which the given endpoint is assigned.
216 */
217 NRF_STATIC_INLINE void nrf_ppi_event_endpoint_setup(NRF_PPI_Type * p_reg,
218 nrf_ppi_channel_t channel,
219 uint32_t eep);
220
221 /**
222 * @brief Function for setting up the task endpoint for a given PPI channel.
223 *
224 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
225 * @param[in] tep Task register address.
226 * @param[in] channel Channel to which the given endpoint is assigned.
227 */
228 NRF_STATIC_INLINE void nrf_ppi_task_endpoint_setup(NRF_PPI_Type * p_reg,
229 nrf_ppi_channel_t channel,
230 uint32_t tep);
231
232
233 #if defined(PPI_FEATURE_FORKS_PRESENT) || defined(__NRFX_DOXYGEN__)
234 /**
235 * @brief Function for setting up task endpoint for a given PPI fork.
236 *
237 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
238 * @param[in] fork_tep Task register address.
239 * @param[in] channel Channel to which the given fork endpoint is assigned.
240 */
241 NRF_STATIC_INLINE void nrf_ppi_fork_endpoint_setup(NRF_PPI_Type * p_reg,
242 nrf_ppi_channel_t channel,
243 uint32_t fork_tep);
244
245 /**
246 * @brief Function for setting up event and task endpoints for a given PPI channel and fork.
247 *
248 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
249 * @param[in] eep Event register address.
250 * @param[in] tep Task register address.
251 * @param[in] fork_tep Fork task register address (register value).
252 * @param[in] channel Channel to which the given endpoints are assigned.
253 */
254 NRF_STATIC_INLINE void nrf_ppi_channel_and_fork_endpoint_setup(NRF_PPI_Type * p_reg,
255 nrf_ppi_channel_t channel,
256 uint32_t eep,
257 uint32_t tep,
258 uint32_t fork_tep);
259 #endif
260
261 /**
262 * @brief Function for including a PPI channel in a channel group.
263 *
264 * @details This function adds only one channel to the group.
265 *
266 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
267 * @param[in] channel Channel to be included in the group.
268 * @param[in] channel_group Channel group.
269 */
270 NRF_STATIC_INLINE void nrf_ppi_channel_include_in_group(NRF_PPI_Type * p_reg,
271 nrf_ppi_channel_t channel,
272 nrf_ppi_channel_group_t channel_group);
273
274 /**
275 * @brief Function for setting multiple PPI channels in a channel group.
276 *
277 * @details This function adds all specified channels to the group.
278 *
279 * @warning All channels included previously will be overwritten.
280 *
281 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
282 * @param[in] channel_mask Channels to be assgined in the group.
283 * @param[in] channel_group Channel group.
284 */
285 NRF_STATIC_INLINE void nrf_ppi_channels_group_set(NRF_PPI_Type * p_reg,
286 uint32_t channel_mask,
287 nrf_ppi_channel_group_t channel_group);
288
289 /**
290 * @brief Function for including multiple PPI channels in a channel group.
291 *
292 * @details This function adds all specified channels to the group.
293 *
294 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
295 * @param[in] channel_mask Channels to be included in the group.
296 * @param[in] channel_group Channel group.
297 */
298 NRF_STATIC_INLINE void nrf_ppi_channels_include_in_group(NRF_PPI_Type * p_reg,
299 uint32_t channel_mask,
300 nrf_ppi_channel_group_t channel_group);
301
302 /**
303 * @brief Function for removing a PPI channel from a channel group.
304 *
305 * @details This function removes only one channel from the group.
306 *
307 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
308 * @param[in] channel Channel to be removed from the group.
309 * @param[in] channel_group Channel group.
310 */
311 NRF_STATIC_INLINE void nrf_ppi_channel_remove_from_group(NRF_PPI_Type * p_reg,
312 nrf_ppi_channel_t channel,
313 nrf_ppi_channel_group_t channel_group);
314
315 /**
316 * @brief Function for removing multiple PPI channels from a channel group.
317 *
318 * @details This function removes all specified channels from the group.
319 *
320 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
321 * @param[in] channel_mask Channels to be removed from the group.
322 * @param[in] channel_group Channel group.
323 */
324 NRF_STATIC_INLINE void nrf_ppi_channels_remove_from_group(NRF_PPI_Type * p_reg,
325 uint32_t channel_mask,
326 nrf_ppi_channel_group_t channel_group);
327
328 /**
329 * @brief Function for removing all PPI channels from a channel group.
330 *
331 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
332 * @param[in] group Channel group.
333 */
334 NRF_STATIC_INLINE void nrf_ppi_group_clear(NRF_PPI_Type * p_reg, nrf_ppi_channel_group_t group);
335
336 /**
337 * @brief Function for enabling a channel group.
338 *
339 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
340 * @param[in] group Channel group.
341 */
342 NRF_STATIC_INLINE void nrf_ppi_group_enable(NRF_PPI_Type * p_reg, nrf_ppi_channel_group_t group);
343
344 /**
345 * @brief Function for disabling a channel group.
346 *
347 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
348 * @param[in] group Channel group.
349 */
350 NRF_STATIC_INLINE void nrf_ppi_group_disable(NRF_PPI_Type * p_reg, nrf_ppi_channel_group_t group);
351
352 /**
353 * @brief Function for setting a PPI task.
354 *
355 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
356 * @param[in] ppi_task PPI task to be set.
357 */
358 NRF_STATIC_INLINE void nrf_ppi_task_trigger(NRF_PPI_Type * p_reg, nrf_ppi_task_t ppi_task);
359
360 /**
361 * @brief Function for getting the address of the specified PPI task register.
362 *
363 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
364 * @param[in] ppi_task PPI task.
365 *
366 * @return Address of the requested PPI task register.
367 */
368 NRF_STATIC_INLINE uint32_t nrf_ppi_task_address_get(NRF_PPI_Type const * p_reg,
369 nrf_ppi_task_t ppi_task);
370
371 /**
372 * @brief Function for getting the PPI enable task address of the specified group.
373 *
374 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
375 * @param[in] group PPI group.
376 *
377 * @return PPI enable task address of the specified group.
378 */
379 NRF_STATIC_INLINE uint32_t nrf_ppi_task_group_enable_address_get(NRF_PPI_Type const * p_reg,
380 nrf_ppi_channel_group_t group);
381
382 /**
383 * @brief Function for getting the PPI disable task address of the specified group.
384 *
385 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
386 * @param[in] group PPI group.
387 *
388 * @return PPI disable task address of the specified group.
389 */
390 NRF_STATIC_INLINE uint32_t nrf_ppi_task_group_disable_address_get(NRF_PPI_Type const * p_reg,
391 nrf_ppi_channel_group_t group);
392
393 /**
394 * @brief Function for getting the ENABLE task associated with the specified channel group.
395 *
396 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
397 * @param[in] index Channel group index.
398 *
399 * @return Requested ENABLE task.
400 */
401 NRF_STATIC_INLINE nrf_ppi_task_t nrf_ppi_group_enable_task_get(NRF_PPI_Type const * p_reg,
402 uint8_t index);
403
404 /**
405 * @brief Function for getting the DISABLE task associated with the specified channel group.
406 *
407 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
408 * @param[in] index Channel group index.
409 *
410 * @return Requested DISABLE task.
411 */
412 NRF_STATIC_INLINE nrf_ppi_task_t nrf_ppi_group_disable_task_get(NRF_PPI_Type const * p_reg,
413 uint8_t index);
414
415
416 #ifndef NRF_DECLARE_ONLY
417
nrf_ppi_channel_enable(NRF_PPI_Type * p_reg,nrf_ppi_channel_t channel)418 NRF_STATIC_INLINE void nrf_ppi_channel_enable(NRF_PPI_Type * p_reg, nrf_ppi_channel_t channel)
419 {
420 p_reg->CHENSET = PPI_CHENSET_CH0_Set << ((uint32_t) channel);
421 }
422
nrf_ppi_channel_disable(NRF_PPI_Type * p_reg,nrf_ppi_channel_t channel)423 NRF_STATIC_INLINE void nrf_ppi_channel_disable(NRF_PPI_Type * p_reg, nrf_ppi_channel_t channel)
424 {
425 p_reg->CHENCLR = PPI_CHENCLR_CH0_Clear << ((uint32_t) channel);
426 }
427
nrf_ppi_channel_enable_get(NRF_PPI_Type const * p_reg,nrf_ppi_channel_t channel)428 NRF_STATIC_INLINE nrf_ppi_channel_enable_t nrf_ppi_channel_enable_get(NRF_PPI_Type const * p_reg,
429 nrf_ppi_channel_t channel)
430 {
431 if (p_reg->CHEN & (PPI_CHEN_CH0_Msk << ((uint32_t) channel)))
432 {
433 return NRF_PPI_CHANNEL_ENABLED;
434 }
435 else
436 {
437 return NRF_PPI_CHANNEL_DISABLED;
438 }
439 }
440
nrf_ppi_channels_disable_all(NRF_PPI_Type * p_reg)441 NRF_STATIC_INLINE void nrf_ppi_channels_disable_all(NRF_PPI_Type * p_reg)
442 {
443 p_reg->CHENCLR = ((uint32_t)0xFFFFFFFFuL);
444 }
445
nrf_ppi_channels_enable(NRF_PPI_Type * p_reg,uint32_t mask)446 NRF_STATIC_INLINE void nrf_ppi_channels_enable(NRF_PPI_Type * p_reg, uint32_t mask)
447 {
448 p_reg->CHENSET = mask;
449 }
450
nrf_ppi_channels_disable(NRF_PPI_Type * p_reg,uint32_t mask)451 NRF_STATIC_INLINE void nrf_ppi_channels_disable(NRF_PPI_Type * p_reg, uint32_t mask)
452 {
453 p_reg->CHENCLR = mask;
454 }
455
nrf_ppi_channel_endpoint_setup(NRF_PPI_Type * p_reg,nrf_ppi_channel_t channel,uint32_t eep,uint32_t tep)456 NRF_STATIC_INLINE void nrf_ppi_channel_endpoint_setup(NRF_PPI_Type * p_reg,
457 nrf_ppi_channel_t channel,
458 uint32_t eep,
459 uint32_t tep)
460 {
461 p_reg->CH[(uint32_t) channel].EEP = eep;
462 p_reg->CH[(uint32_t) channel].TEP = tep;
463 }
464
nrf_ppi_event_endpoint_setup(NRF_PPI_Type * p_reg,nrf_ppi_channel_t channel,uint32_t eep)465 NRF_STATIC_INLINE void nrf_ppi_event_endpoint_setup(NRF_PPI_Type * p_reg,
466 nrf_ppi_channel_t channel,
467 uint32_t eep)
468 {
469 p_reg->CH[(uint32_t) channel].EEP = eep;
470 }
471
nrf_ppi_task_endpoint_setup(NRF_PPI_Type * p_reg,nrf_ppi_channel_t channel,uint32_t tep)472 NRF_STATIC_INLINE void nrf_ppi_task_endpoint_setup(NRF_PPI_Type * p_reg,
473 nrf_ppi_channel_t channel,
474 uint32_t tep)
475 {
476 p_reg->CH[(uint32_t) channel].TEP = tep;
477 }
478
479 #if defined(PPI_FEATURE_FORKS_PRESENT)
480
nrf_ppi_fork_endpoint_setup(NRF_PPI_Type * p_reg,nrf_ppi_channel_t channel,uint32_t fork_tep)481 NRF_STATIC_INLINE void nrf_ppi_fork_endpoint_setup(NRF_PPI_Type * p_reg,
482 nrf_ppi_channel_t channel,
483 uint32_t fork_tep)
484 {
485 p_reg->FORK[(uint32_t) channel].TEP = fork_tep;
486 }
487
nrf_ppi_channel_and_fork_endpoint_setup(NRF_PPI_Type * p_reg,nrf_ppi_channel_t channel,uint32_t eep,uint32_t tep,uint32_t fork_tep)488 NRF_STATIC_INLINE void nrf_ppi_channel_and_fork_endpoint_setup(NRF_PPI_Type * p_reg,
489 nrf_ppi_channel_t channel,
490 uint32_t eep,
491 uint32_t tep,
492 uint32_t fork_tep)
493 {
494 nrf_ppi_channel_endpoint_setup(p_reg, channel, eep, tep);
495 nrf_ppi_fork_endpoint_setup(p_reg, channel, fork_tep);
496 }
497 #endif
498
nrf_ppi_channel_include_in_group(NRF_PPI_Type * p_reg,nrf_ppi_channel_t channel,nrf_ppi_channel_group_t channel_group)499 NRF_STATIC_INLINE void nrf_ppi_channel_include_in_group(NRF_PPI_Type * p_reg,
500 nrf_ppi_channel_t channel,
501 nrf_ppi_channel_group_t channel_group)
502 {
503 p_reg->CHG[(uint32_t) channel_group] |= (PPI_CHG_CH0_Included << ((uint32_t) channel));
504 }
505
nrf_ppi_channels_group_set(NRF_PPI_Type * p_reg,uint32_t channel_mask,nrf_ppi_channel_group_t channel_group)506 NRF_STATIC_INLINE void nrf_ppi_channels_group_set(NRF_PPI_Type * p_reg,
507 uint32_t channel_mask,
508 nrf_ppi_channel_group_t channel_group)
509 {
510 p_reg->CHG[(uint32_t) channel_group] = channel_mask;
511 }
512
nrf_ppi_channels_include_in_group(NRF_PPI_Type * p_reg,uint32_t channel_mask,nrf_ppi_channel_group_t channel_group)513 NRF_STATIC_INLINE void nrf_ppi_channels_include_in_group(NRF_PPI_Type * p_reg,
514 uint32_t channel_mask,
515 nrf_ppi_channel_group_t channel_group)
516 {
517 p_reg->CHG[(uint32_t) channel_group] |= channel_mask;
518 }
519
nrf_ppi_channel_remove_from_group(NRF_PPI_Type * p_reg,nrf_ppi_channel_t channel,nrf_ppi_channel_group_t channel_group)520 NRF_STATIC_INLINE void nrf_ppi_channel_remove_from_group(NRF_PPI_Type * p_reg,
521 nrf_ppi_channel_t channel,
522 nrf_ppi_channel_group_t channel_group)
523 {
524 p_reg->CHG[(uint32_t) channel_group] &= ~(PPI_CHG_CH0_Included << ((uint32_t) channel));
525 }
526
nrf_ppi_channels_remove_from_group(NRF_PPI_Type * p_reg,uint32_t channel_mask,nrf_ppi_channel_group_t channel_group)527 NRF_STATIC_INLINE void nrf_ppi_channels_remove_from_group(NRF_PPI_Type * p_reg,
528 uint32_t channel_mask,
529 nrf_ppi_channel_group_t channel_group)
530 {
531 p_reg->CHG[(uint32_t) channel_group] &= ~(channel_mask);
532 }
533
nrf_ppi_group_clear(NRF_PPI_Type * p_reg,nrf_ppi_channel_group_t group)534 NRF_STATIC_INLINE void nrf_ppi_group_clear(NRF_PPI_Type * p_reg, nrf_ppi_channel_group_t group)
535 {
536 p_reg->CHG[(uint32_t) group] = 0;
537 }
538
nrf_ppi_group_enable(NRF_PPI_Type * p_reg,nrf_ppi_channel_group_t group)539 NRF_STATIC_INLINE void nrf_ppi_group_enable(NRF_PPI_Type * p_reg, nrf_ppi_channel_group_t group)
540 {
541 p_reg->TASKS_CHG[(uint32_t) group].EN = 1UL;
542 }
543
nrf_ppi_group_disable(NRF_PPI_Type * p_reg,nrf_ppi_channel_group_t group)544 NRF_STATIC_INLINE void nrf_ppi_group_disable(NRF_PPI_Type * p_reg, nrf_ppi_channel_group_t group)
545 {
546 p_reg->TASKS_CHG[(uint32_t) group].DIS = 1UL;
547 }
548
nrf_ppi_task_trigger(NRF_PPI_Type * p_reg,nrf_ppi_task_t ppi_task)549 NRF_STATIC_INLINE void nrf_ppi_task_trigger(NRF_PPI_Type * p_reg, nrf_ppi_task_t ppi_task)
550 {
551 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) ppi_task)) = 1UL;
552 }
553
nrf_ppi_task_address_get(NRF_PPI_Type const * p_reg,nrf_ppi_task_t ppi_task)554 NRF_STATIC_INLINE uint32_t nrf_ppi_task_address_get(NRF_PPI_Type const * p_reg,
555 nrf_ppi_task_t ppi_task)
556 {
557 return (uint32_t) ((const uint8_t *) p_reg + (uint32_t) ppi_task);
558 }
559
nrf_ppi_task_group_enable_address_get(NRF_PPI_Type const * p_reg,nrf_ppi_channel_group_t group)560 NRF_STATIC_INLINE uint32_t nrf_ppi_task_group_enable_address_get(NRF_PPI_Type const * p_reg,
561 nrf_ppi_channel_group_t group)
562 {
563 return (uint32_t) &p_reg->TASKS_CHG[(uint32_t) group].EN;
564 }
565
nrf_ppi_task_group_disable_address_get(NRF_PPI_Type const * p_reg,nrf_ppi_channel_group_t group)566 NRF_STATIC_INLINE uint32_t nrf_ppi_task_group_disable_address_get(NRF_PPI_Type const * p_reg,
567 nrf_ppi_channel_group_t group)
568 {
569 return (uint32_t) &p_reg->TASKS_CHG[(uint32_t) group].DIS;
570 }
571
nrf_ppi_group_enable_task_get(NRF_PPI_Type const * p_reg,uint8_t index)572 NRF_STATIC_INLINE nrf_ppi_task_t nrf_ppi_group_enable_task_get(NRF_PPI_Type const * p_reg,
573 uint8_t index)
574 {
575 (void)p_reg;
576 NRFX_ASSERT(index < PPI_GROUP_NUM);
577 return (nrf_ppi_task_t)NRFX_OFFSETOF(NRF_PPI_Type, TASKS_CHG[index].EN);
578 }
579
nrf_ppi_group_disable_task_get(NRF_PPI_Type const * p_reg,uint8_t index)580 NRF_STATIC_INLINE nrf_ppi_task_t nrf_ppi_group_disable_task_get(NRF_PPI_Type const * p_reg,
581 uint8_t index)
582 {
583 (void)p_reg;
584 NRFX_ASSERT(index < PPI_GROUP_NUM);
585 return (nrf_ppi_task_t)NRFX_OFFSETOF(NRF_PPI_Type, TASKS_CHG[index].DIS);
586 }
587
588 #endif // NRF_DECLARE_ONLY
589
590 /** @} */
591
592 #ifdef __cplusplus
593 }
594 #endif
595
596 #endif // NRF_PPI_H__
597
