1 /*
2 * Copyright (c) 2017 - 2024, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_POWER_H__
35 #define NRF_POWER_H__
36
37 #include <nrfx.h>
38 #include <nrf_erratas.h>
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 /**
45 * @defgroup nrf_power_hal POWER HAL
46 * @{
47 * @ingroup nrf_power
48 * @brief Hardware access layer for managing the POWER peripheral.
49 */
50
51 #if defined(POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk) || defined(NRF51) || defined(__NRFX_DOXYGEN__)
52 /** @brief Symbol indicating whether Constant Latency mode is present. */
53 #define NRF_POWER_HAS_CONST_LATENCY 1
54 #else
55 #define NRF_POWER_HAS_CONST_LATENCY 0
56 #endif
57
58 #if defined(POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk) || defined(NRF51) || defined(__NRFX_DOXYGEN__)
59 /** @brief Symbol indicating whether Low-Power mode is present. */
60 #define NRF_POWER_HAS_LOW_POWER 1
61 #else
62 #define NRF_POWER_HAS_LOW_POWER 0
63 #endif
64
65 #if defined(POWER_INTENSET_SLEEPENTER_Msk) || defined(__NRFX_DOXYGEN__)
66 /** @brief Symbol indicating whether sleep events are present. */
67 #define NRF_POWER_HAS_SLEEPEVT 1
68 #else
69 #define NRF_POWER_HAS_SLEEPEVT 0
70 #endif
71
72 #if defined(POWER_USBREGSTATUS_VBUSDETECT_Msk) || defined(__NRFX_DOXYGEN__)
73 /** @brief Symbol indicating whether the POWER peripheral controls the USB regulator. */
74 #define NRF_POWER_HAS_USBREG 1
75 #else
76 #define NRF_POWER_HAS_USBREG 0
77 #endif
78
79 #if defined(POWER_DCDCEN0_DCDCEN_Msk) || defined(__NRFX_DOXYGEN__)
80 /** @brief Symbol indicating whether DCDCEN for REG0 is present. */
81 #define NRF_POWER_HAS_DCDCEN_VDDH 1
82 #else
83 #define NRF_POWER_HAS_DCDCEN_VDDH 0
84 #endif
85
86 #if defined(POWER_DCDCEN_DCDCEN_Msk) || defined(__NRFX_DOXYGEN__)
87 /** @brief Symbol indicating whether DCDCEN for REG1 is present. */
88 #define NRF_POWER_HAS_DCDCEN 1
89 #else
90 #define NRF_POWER_HAS_DCDCEN 0
91 #endif
92
93 #if defined(POWER_INTENSET_POFWARN_Msk) || defined(__NRFX_DOXYGEN__)
94 /** @brief Symbol indicating whether power failure event is present. */
95 #define NRF_POWER_HAS_POFWARN 1
96 #else
97 #define NRF_POWER_HAS_POFWARN 0
98 #endif
99
100 #if defined(POWER_POFCON_THRESHOLD_Msk) || defined(__NRFX_DOXYGEN__)
101 /** @brief Symbol indicating whether power failure comparator is present. */
102 #define NRF_POWER_HAS_POFCON 1
103 #else
104 #define NRF_POWER_HAS_POFCON 0
105 #endif
106
107 #if defined(POWER_POFCON_THRESHOLDVDDH_Msk) || defined(__NRFX_DOXYGEN__)
108 /** @brief Symbol indicating whether power failure comparator for VDDH is present. */
109 #define NRF_POWER_HAS_POFCON_VDDH 1
110 #else
111 #define NRF_POWER_HAS_POFCON_VDDH 0
112 #endif
113
114 #if defined(POWER_RESETREAS_RESETPIN_Msk) || defined(__NRFX_DOXYGEN__)
115 /** @brief Symbol indicating whether RESETREAS register is present in POWER */
116 #define NRF_POWER_HAS_RESETREAS 1
117 #else
118 #define NRF_POWER_HAS_RESETREAS 0
119 #endif
120
121 #if defined(POWER_RESETREAS_CTRLAP_Msk) || defined(__NRFX_DOXYGEN__)
122 /** @brief Symbol indicating whether RESETREAS CTRLAP is present. */
123 #define NRF_POWER_HAS_RESETREAS_CTRLAP 1
124 #else
125 #define NRF_POWER_HAS_RESETREAS_CTRLAP 0
126 #endif
127
128 #if defined(POWER_RESETREAS_LPCOMP_Msk) || defined(__NRFX_DOXYGEN__)
129 /** @brief Symbol indicating whether RESETREAS LPCOMP is present. */
130 #define NRF_POWER_HAS_RESETREAS_LPCOMP 1
131 #else
132 #define NRF_POWER_HAS_RESETREAS_LPCOMP 0
133 #endif
134
135 #if defined(POWER_RESETREAS_NFC_Msk) || defined(__NRFX_DOXYGEN__)
136 /** @brief Symbol indicating whether RESETREAS NFC is present. */
137 #define NRF_POWER_HAS_RESETREAS_NFC 1
138 #else
139 #define NRF_POWER_HAS_RESETREAS_NFC 0
140 #endif
141
142 #if defined(POWER_RESETREAS_VBUS_Msk) || defined(__NRFX_DOXYGEN__)
143 /** @brief Symbol indicating whether RESETREAS VBUS is present. */
144 #define NRF_POWER_HAS_RESETREAS_VBUS 1
145 #else
146 #define NRF_POWER_HAS_RESETREAS_VBUS 0
147 #endif
148
149 #if defined(POWER_MAINREGSTATUS_MAINREGSTATUS_Msk) || defined(__NRFX_DOXYGEN__)
150 /** @brief Symbol indicating whether MAINREGSTATUS register is present. */
151 #define NRF_POWER_HAS_MAINREGSTATUS 1
152 #else
153 #define NRF_POWER_HAS_MAINREGSTATUS 0
154 #endif
155
156 #if defined(POWER_GPREGRET_GPREGRET_Msk) || defined(__NRFX_DOXYGEN__)
157 /** @brief Symbol indicating whether GPREGRET register is present. */
158 #define NRF_POWER_HAS_GPREGRET 1
159 #else
160 #define NRF_POWER_HAS_GPREGRET 0
161 #endif
162
163 #if (!defined(POWER_GPREGRET2_GPREGRET_Msk) && !defined(NRF51)) || defined(__NRFX_DOXYGEN__)
164 /** @brief Symbol indicating whether GPREGRET register is treated as an array. */
165 #define NRF_POWER_HAS_GPREGRET_ARRAY 1
166 #else
167 #define NRF_POWER_HAS_GPREGRET_ARRAY 0
168 #endif
169
170 #if NRF_POWER_HAS_GPREGRET_ARRAY && defined(POWER_GPREGRET_MaxCount) || defined(__NRFX_DOXYGEN__)
171 /** @brief Size of GPREGRET register when defined as array. */
172 #define NRFX_POWER_GPREGRET_COUNT POWER_GPREGRET_MaxCount
173 #elif NRF_POWER_HAS_GPREGRET_ARRAY
174 #define NRFX_POWER_GPREGRET_COUNT 2
175 #endif
176
177 #if defined(POWER_TASKS_SEMAPHORE_ACQUIRE_ACQUIRE_Msk) || defined(__NRFX_DOXYGEN__)
178 /** @brief Symbol indicating whether semaphore for regulator voltage scaling procedure is present. */
179 #define NRF_POWER_HAS_SEMAPHORE 1
180 #else
181 #define NRF_POWER_HAS_SEMAPHORE 0
182 #endif
183
184 #if (defined(POWER_TASKS_REGUPDATE_TASKS_REGUPDATE_Msk) && \
185 defined(POWER_EVENTS_REGUPDATED_EVENTS_REGUPDATED_Msk)) || defined(__NRFX_DOXYGEN__)
186 /** @brief Symbol indicating whether task and event responsible for updating voltage regulators configuration are present. */
187 #define NRF_POWER_HAS_VREG_UPDATE_TASK_EVENT 1
188 #else
189 #define NRF_POWER_HAS_VREG_UPDATE_TASK_EVENT 0
190 #endif
191
192 #if defined(POWER_REGCONFIG_VREG1V8_Msk) || defined(__NRFX_DOXYGEN__)
193 /** @brief Symbol indicating whether voltage regulators are configurable. */
194 #define NRF_POWER_HAS_VREG_CONFIG 1
195 #else
196 #define NRF_POWER_HAS_VREG_CONFIG 0
197 #endif
198
199 #if defined(POWER_EVENTS_ABBLOCK_EVENTS_ABBLOCK_Msk) || defined(__NRFX_DOXYGEN__)
200 /** @brief Symbol indicating whether the Adaptive Body Biasing (ABB) domains are present. */
201 #define NRF_POWER_HAS_ABB 1
202 #else
203 #define NRF_POWER_HAS_ABB 0
204 #endif
205
206 #if defined(POWER_BLOCKULPMODE_BLOCK_Msk) || defined(__NRFX_DOXYGEN__)
207 /** @brief Symbol indicating whether the power block modes are present. */
208 #define NRF_POWER_HAS_BLOCK_MODES 1
209 #else
210 #define NRF_POWER_HAS_BLOCK_MODES 0
211 #endif
212
213 #if defined(POWER_BILSENABLE_ENABLE_Msk) || defined(__NRFX_DOXYGEN__)
214 /** @brief Symbol indicating whether the Built-in Leakage Sensors (BILS) are present. */
215 #define NRF_POWER_HAS_BILS 1
216 #else
217 #define NRF_POWER_HAS_BILS 0
218 #endif
219
220 #if defined(POWER_PMICENABLE_ENABLE_Msk) || defined(__NRFX_DOXYGEN__)
221 /** @brief Symbol indicating whether the Power Management IC (PMIC) is present. */
222 #define NRF_POWER_HAS_PMIC 1
223 #else
224 #define NRF_POWER_HAS_PMIC 0
225 #endif
226
227 #if NRF_POWER_HAS_ABB
228 /** @brief Symbol specifying the maximum number of available @p ABB_LOCK events. */
229 #define NRF_POWER_EVENTS_ABB_LOCK_COUNT POWER_EVENTS_ABBLOCK_MaxCount
230 #endif
231
232 /** @brief POWER tasks. */
233 typedef enum
234 {
235 #if NRF_POWER_HAS_CONST_LATENCY
236 NRF_POWER_TASK_CONSTLAT = offsetof(NRF_POWER_Type, TASKS_CONSTLAT), ///< Enable constant latency mode.
237 #endif
238 #if NRF_POWER_HAS_LOW_POWER
239 NRF_POWER_TASK_LOWPWR = offsetof(NRF_POWER_Type, TASKS_LOWPWR), ///< Enable low-power mode (variable latency).
240 #endif
241 #if NRF_POWER_HAS_SEMAPHORE
242 NRF_POWER_TASK_SEMAPHORE_ACQUIRE = offsetof(NRF_POWER_Type, TASKS_SEMAPHORE.ACQUIRE), ///< Acquire the semaphore for regulator voltage scaling procedure.
243 NRF_POWER_TASK_SEMAPHORE_RELEASE = offsetof(NRF_POWER_Type, TASKS_SEMAPHORE.RELEASE), ///< Release the semaphore for regulator voltage scaling procedure.
244 #endif
245 #if NRF_POWER_HAS_VREG_UPDATE_TASK_EVENT
246 NRF_POWER_TASK_REGULATOR_UPDATE = offsetof(NRF_POWER_Type, TASKS_REGUPDATE), ///< Update the regulator configuration.
247 #endif
248 } nrf_power_task_t;
249
250 /** @brief POWER events. */
251 typedef enum
252 {
253 #if NRF_POWER_HAS_POFWARN
254 NRF_POWER_EVENT_POFWARN = offsetof(NRF_POWER_Type, EVENTS_POFWARN), ///< Power failure warning.
255 #endif
256 #if NRF_POWER_HAS_SLEEPEVT
257 NRF_POWER_EVENT_SLEEPENTER = offsetof(NRF_POWER_Type, EVENTS_SLEEPENTER), ///< CPU entered WFI/WFE sleep mode.
258 NRF_POWER_EVENT_SLEEPEXIT = offsetof(NRF_POWER_Type, EVENTS_SLEEPEXIT), ///< CPU exited WFI/WFE sleep mode.
259 #endif
260 #if NRF_POWER_HAS_USBREG
261 NRF_POWER_EVENT_USBDETECTED = offsetof(NRF_POWER_Type, EVENTS_USBDETECTED), ///< Voltage supply detected on VBUS.
262 NRF_POWER_EVENT_USBREMOVED = offsetof(NRF_POWER_Type, EVENTS_USBREMOVED), ///< Voltage supply removed from VBUS.
263 NRF_POWER_EVENT_USBPWRRDY = offsetof(NRF_POWER_Type, EVENTS_USBPWRRDY), ///< USB 3.3 V supply ready.
264 #endif
265 #if NRF_POWER_HAS_SEMAPHORE
266 NRF_POWER_EVENT_SEMAPHORE_ACQUIRED = offsetof(NRF_POWER_Type, EVENTS_SEMAPHORE.ACQUIRED), ///< Acquired the semaphore for regulator voltage scaling procedure.
267 NRF_POWER_EVENT_SEMAPHORE_RELEASED = offsetof(NRF_POWER_Type, EVENTS_SEMAPHORE.RELEASED), ///< Released the semaphore for regulator voltage scaling procedure.
268 #endif
269 #if NRF_POWER_HAS_VREG_UPDATE_TASK_EVENT
270 NRF_POWER_EVENT_REGULATOR_UPDATED = offsetof(NRF_POWER_Type, EVENTS_REGUPDATED), ///< Updated the regulator configuration.
271 #endif
272 #if NRF_POWER_HAS_ABB
273 NRF_POWER_EVENT_ABB_LOCK_0 = offsetof(NRF_POWER_Type, EVENTS_ABBLOCK[0]), ///< ABB lock for the ABB domain 0.
274 NRF_POWER_EVENT_ABB_LOCK_1 = offsetof(NRF_POWER_Type, EVENTS_ABBLOCK[1]), ///< ABB lock for the ABB domain 1.
275 #endif
276 } nrf_power_event_t;
277
278 /** @brief POWER interrupts. */
279 typedef enum
280 {
281 #if NRF_POWER_HAS_POFWARN
282 NRF_POWER_INT_POFWARN_MASK = POWER_INTENSET_POFWARN_Msk, ///< Write '1' to enable interrupt for POFWARN event.
283 #endif
284 #if NRF_POWER_HAS_SLEEPEVT
285 NRF_POWER_INT_SLEEPENTER_MASK = POWER_INTENSET_SLEEPENTER_Msk, ///< Write '1' to enable interrupt for SLEEPENTER event.
286 NRF_POWER_INT_SLEEPEXIT_MASK = POWER_INTENSET_SLEEPEXIT_Msk, ///< Write '1' to enable interrupt for SLEEPEXIT event.
287 #endif
288 #if NRF_POWER_HAS_USBREG
289 NRF_POWER_INT_USBDETECTED_MASK = POWER_INTENSET_USBDETECTED_Msk, ///< Write '1' to enable interrupt for USBDETECTED event.
290 NRF_POWER_INT_USBREMOVED_MASK = POWER_INTENSET_USBREMOVED_Msk, ///< Write '1' to enable interrupt for USBREMOVED event.
291 NRF_POWER_INT_USBPWRRDY_MASK = POWER_INTENSET_USBPWRRDY_Msk, ///< Write '1' to enable interrupt for USBPWRRDY event.
292 #endif
293 #if NRF_POWER_HAS_SEMAPHORE
294 NRF_POWER_INT_SEMAPHORE_ACQUIRED = POWER_INTEN_SEMAPHOREACQUIRED_Msk, ///< Write '1' to enable interrupt for SEMAPHORE_ACQUIRED event.
295 NRF_POWER_INT_SEMAPHORE_RELEASED = POWER_INTEN_SEMAPHORERELEASED_Msk, ///< Write '1' to enable interrupt for SEMAPHORE_RELEASED event.
296 #endif
297 #if NRF_POWER_HAS_VREG_UPDATE_TASK_EVENT
298 NRF_POWER_INT_REGULATOR_UPDATED = POWER_INTEN_REGUPDATED_Msk, ///< Write '1' to enable interrupt for REGULATOR_UPDATED event.
299 #endif
300 #if NRF_POWER_HAS_ABB
301 NRF_POWER_INT_ABB_LOCK_0 = POWER_INTEN_ABBLOCK0_Msk, ///< Write '1' to enable interrupt for ABB_LOCK_0 event.
302 NRF_POWER_INT_ABB_LOCK_1 = POWER_INTEN_ABBLOCK1_Msk, ///< Write '1' to enable interrupt for ABB_LOCK_1 event.
303 #endif
304 } nrf_power_int_mask_t;
305
306 /** @brief Reset reason. */
307 #if NRF_POWER_HAS_RESETREAS
308 typedef enum
309 {
310 NRF_POWER_RESETREAS_RESETPIN_MASK = POWER_RESETREAS_RESETPIN_Msk, /**< Bit mask of RESETPIN field. */
311 NRF_POWER_RESETREAS_DOG_MASK = POWER_RESETREAS_DOG_Msk , /**< Bit mask of DOG field. */
312 NRF_POWER_RESETREAS_SREQ_MASK = POWER_RESETREAS_SREQ_Msk , /**< Bit mask of SREQ field. */
313 NRF_POWER_RESETREAS_LOCKUP_MASK = POWER_RESETREAS_LOCKUP_Msk , /**< Bit mask of LOCKUP field. */
314 NRF_POWER_RESETREAS_OFF_MASK = POWER_RESETREAS_OFF_Msk , /**< Bit mask of OFF field. */
315 #if NRF_POWER_HAS_RESETREAS_LPCOMP
316 NRF_POWER_RESETREAS_LPCOMP_MASK = POWER_RESETREAS_LPCOMP_Msk , /**< Bit mask of LPCOMP field. */
317 #endif
318 NRF_POWER_RESETREAS_DIF_MASK = POWER_RESETREAS_DIF_Msk , /**< Bit mask of DIF field. */
319 #if NRF_POWER_HAS_RESETREAS_NFC
320 NRF_POWER_RESETREAS_NFC_MASK = POWER_RESETREAS_NFC_Msk , /**< Bit mask of NFC field. */
321 #endif
322 #if NRF_POWER_HAS_RESETREAS_VBUS
323 NRF_POWER_RESETREAS_VBUS_MASK = POWER_RESETREAS_VBUS_Msk , /**< Bit mask of VBUS field. */
324 #endif
325 #if NRF_POWER_HAS_RESETREAS_CTRLAP
326 NRF_POWER_RESETREAS_CTRLAP_MASK = POWER_RESETREAS_CTRLAP_Msk , /**< Bit mask of CTRLAP field. */
327 #endif
328 } nrf_power_resetreas_mask_t;
329 #endif // NRF_POWER_HAS_RESETREAS
330
331 #if NRF_POWER_HAS_USBREG
332 /**
333 * @brief USBREGSTATUS register bit masks
334 *
335 * @sa nrf_power_usbregstatus_get
336 */
337 typedef enum
338 {
339 NRF_POWER_USBREGSTATUS_VBUSDETECT_MASK = POWER_USBREGSTATUS_VBUSDETECT_Msk, ///< USB detected or removed.
340 NRF_POWER_USBREGSTATUS_OUTPUTRDY_MASK = POWER_USBREGSTATUS_OUTPUTRDY_Msk ///< USB 3.3 V supply ready.
341 } nrf_power_usbregstatus_mask_t;
342 #endif // NRF_POWER_HAS_USBREG
343
344 #if defined(POWER_RAMSTATUS_RAMBLOCK0_Msk) || defined(__NRFX_DOXYGEN__)
345 /**
346 * @brief Numbers of RAM blocks
347 *
348 * @sa nrf_power_ramblock_mask_t
349 * @note
350 * RAM blocks must be used in nRF51.
351 * In newer SoCs, RAM is divided into segments and this functionality is not supported.
352 * See the PS for mapping between the internal RAM and RAM blocks, because this
353 * mapping is not 1:1, and functions related to old style blocks must not be used.
354 */
355 typedef enum
356 {
357 NRF_POWER_RAMBLOCK0 = POWER_RAMSTATUS_RAMBLOCK0_Pos,
358 NRF_POWER_RAMBLOCK1 = POWER_RAMSTATUS_RAMBLOCK1_Pos,
359 #if defined(POWER_RAMSTATUS_RAMBLOCK2_Pos) || defined(__NRFX_DOXYGEN__)
360 NRF_POWER_RAMBLOCK2 = POWER_RAMSTATUS_RAMBLOCK2_Pos,
361 #endif
362 #if defined(POWER_RAMSTATUS_RAMBLOCK3_Pos) || defined(__NRFX_DOXYGEN__)
363 NRF_POWER_RAMBLOCK3 = POWER_RAMSTATUS_RAMBLOCK3_Pos
364 #endif
365 } nrf_power_ramblock_t;
366
367 /**
368 * @brief Masks of RAM blocks.
369 *
370 * @sa nrf_power_ramblock_t
371 */
372 typedef enum
373 {
374 NRF_POWER_RAMBLOCK0_MASK = POWER_RAMSTATUS_RAMBLOCK0_Msk,
375 NRF_POWER_RAMBLOCK1_MASK = POWER_RAMSTATUS_RAMBLOCK1_Msk,
376 #if defined(POWER_RAMSTATUS_RAMBLOCK2_Msk) || defined(__NRFX_DOXYGEN__)
377 NRF_POWER_RAMBLOCK2_MASK = POWER_RAMSTATUS_RAMBLOCK2_Msk,
378 #endif
379 #if defined(POWER_RAMSTATUS_RAMBLOCK3_Msk) || defined(__NRFX_DOXYGEN__)
380 NRF_POWER_RAMBLOCK3_MASK = POWER_RAMSTATUS_RAMBLOCK3_Msk
381 #endif
382 } nrf_power_ramblock_mask_t;
383 #endif // defined(POWER_RAMSTATUS_RAMBLOCK0_Msk) || defined(__NRFX_DOXYGEN__)
384
385 /**
386 * @brief RAM power state position of the bits
387 *
388 * @sa nrf_power_onoffram_mask_t
389 */
390 typedef enum
391 {
392 NRF_POWER_ONRAM0, /**< Keep RAM block 0 ON or OFF in System ON mode. */
393 NRF_POWER_OFFRAM0, /**< Keep retention on RAM block 0 when RAM block is switched OFF. */
394 NRF_POWER_ONRAM1, /**< Keep RAM block 1 ON or OFF in System ON mode. */
395 NRF_POWER_OFFRAM1, /**< Keep retention on RAM block 1 when RAM block is switched OFF. */
396 NRF_POWER_ONRAM2, /**< Keep RAM block 2 ON or OFF in System ON mode. */
397 NRF_POWER_OFFRAM2, /**< Keep retention on RAM block 2 when RAM block is switched OFF. */
398 NRF_POWER_ONRAM3, /**< Keep RAM block 3 ON or OFF in System ON mode. */
399 NRF_POWER_OFFRAM3, /**< Keep retention on RAM block 3 when RAM block is switched OFF. */
400 }nrf_power_onoffram_t;
401
402 /**
403 * @brief RAM power state bit masks
404 *
405 * @sa nrf_power_onoffram_t
406 */
407 typedef enum
408 {
409 NRF_POWER_ONRAM0_MASK = 1U << NRF_POWER_ONRAM0, /**< Keep RAM block 0 ON or OFF in System ON mode. */
410 NRF_POWER_OFFRAM0_MASK = 1U << NRF_POWER_OFFRAM0, /**< Keep retention on RAM block 0 when RAM block is switched OFF. */
411 NRF_POWER_ONRAM1_MASK = 1U << NRF_POWER_ONRAM1, /**< Keep RAM block 1 ON or OFF in System ON mode. */
412 NRF_POWER_OFFRAM1_MASK = 1U << NRF_POWER_OFFRAM1, /**< Keep retention on RAM block 1 when RAM block is switched OFF. */
413 NRF_POWER_ONRAM2_MASK = 1U << NRF_POWER_ONRAM2, /**< Keep RAM block 2 ON or OFF in System ON mode. */
414 NRF_POWER_OFFRAM2_MASK = 1U << NRF_POWER_OFFRAM2, /**< Keep retention on RAM block 2 when RAM block is switched OFF. */
415 NRF_POWER_ONRAM3_MASK = 1U << NRF_POWER_ONRAM3, /**< Keep RAM block 3 ON or OFF in System ON mode. */
416 NRF_POWER_OFFRAM3_MASK = 1U << NRF_POWER_OFFRAM3, /**< Keep retention on RAM block 3 when RAM block is switched OFF. */
417 }nrf_power_onoffram_mask_t;
418
419 #if NRF_POWER_HAS_POFCON
420 /** @brief Power failure comparator thresholds. */
421 typedef enum
422 {
423 NRF_POWER_POFTHR_V21 = POWER_POFCON_THRESHOLD_V21, ///< Set threshold to 2.1 V.
424 NRF_POWER_POFTHR_V23 = POWER_POFCON_THRESHOLD_V23, ///< Set threshold to 2.3 V.
425 NRF_POWER_POFTHR_V25 = POWER_POFCON_THRESHOLD_V25, ///< Set threshold to 2.5 V.
426 NRF_POWER_POFTHR_V27 = POWER_POFCON_THRESHOLD_V27, ///< Set threshold to 2.7 V.
427 #if defined(POWER_POFCON_THRESHOLD_V17) || defined(__NRFX_DOXYGEN__)
428 NRF_POWER_POFTHR_V17 = POWER_POFCON_THRESHOLD_V17, ///< Set threshold to 1.7 V.
429 NRF_POWER_POFTHR_V18 = POWER_POFCON_THRESHOLD_V18, ///< Set threshold to 1.8 V.
430 NRF_POWER_POFTHR_V19 = POWER_POFCON_THRESHOLD_V19, ///< Set threshold to 1.9 V.
431 NRF_POWER_POFTHR_V20 = POWER_POFCON_THRESHOLD_V20, ///< Set threshold to 2.0 V.
432 NRF_POWER_POFTHR_V22 = POWER_POFCON_THRESHOLD_V22, ///< Set threshold to 2.2 V.
433 NRF_POWER_POFTHR_V24 = POWER_POFCON_THRESHOLD_V24, ///< Set threshold to 2.4 V.
434 NRF_POWER_POFTHR_V26 = POWER_POFCON_THRESHOLD_V26, ///< Set threshold to 2.6 V.
435 NRF_POWER_POFTHR_V28 = POWER_POFCON_THRESHOLD_V28, ///< Set threshold to 2.8 V.
436 #endif // defined(POWER_POFCON_THRESHOLD_V17) || defined(__NRFX_DOXYGEN__)
437 } nrf_power_pof_thr_t;
438 #endif // NRF_POWER_HAS_POFCON
439
440 #if NRF_POWER_HAS_POFCON_VDDH
441 /** @brief Power failure comparator thresholds for VDDH. */
442 typedef enum
443 {
444 NRF_POWER_POFTHRVDDH_V27 = POWER_POFCON_THRESHOLDVDDH_V27, ///< Set threshold to 2.7 V.
445 NRF_POWER_POFTHRVDDH_V28 = POWER_POFCON_THRESHOLDVDDH_V28, ///< Set threshold to 2.8 V.
446 NRF_POWER_POFTHRVDDH_V29 = POWER_POFCON_THRESHOLDVDDH_V29, ///< Set threshold to 2.9 V.
447 NRF_POWER_POFTHRVDDH_V30 = POWER_POFCON_THRESHOLDVDDH_V30, ///< Set threshold to 3.0 V.
448 NRF_POWER_POFTHRVDDH_V31 = POWER_POFCON_THRESHOLDVDDH_V31, ///< Set threshold to 3.1 V.
449 NRF_POWER_POFTHRVDDH_V32 = POWER_POFCON_THRESHOLDVDDH_V32, ///< Set threshold to 3.2 V.
450 NRF_POWER_POFTHRVDDH_V33 = POWER_POFCON_THRESHOLDVDDH_V33, ///< Set threshold to 3.3 V.
451 NRF_POWER_POFTHRVDDH_V34 = POWER_POFCON_THRESHOLDVDDH_V34, ///< Set threshold to 3.4 V.
452 NRF_POWER_POFTHRVDDH_V35 = POWER_POFCON_THRESHOLDVDDH_V35, ///< Set threshold to 3.5 V.
453 NRF_POWER_POFTHRVDDH_V36 = POWER_POFCON_THRESHOLDVDDH_V36, ///< Set threshold to 3.6 V.
454 NRF_POWER_POFTHRVDDH_V37 = POWER_POFCON_THRESHOLDVDDH_V37, ///< Set threshold to 3.7 V.
455 NRF_POWER_POFTHRVDDH_V38 = POWER_POFCON_THRESHOLDVDDH_V38, ///< Set threshold to 3.8 V.
456 NRF_POWER_POFTHRVDDH_V39 = POWER_POFCON_THRESHOLDVDDH_V39, ///< Set threshold to 3.9 V.
457 NRF_POWER_POFTHRVDDH_V40 = POWER_POFCON_THRESHOLDVDDH_V40, ///< Set threshold to 4.0 V.
458 NRF_POWER_POFTHRVDDH_V41 = POWER_POFCON_THRESHOLDVDDH_V41, ///< Set threshold to 4.1 V.
459 NRF_POWER_POFTHRVDDH_V42 = POWER_POFCON_THRESHOLDVDDH_V42, ///< Set threshold to 4.2 V.
460 } nrf_power_pof_thrvddh_t;
461 #endif // NRF_POWER_HAS_POFCON_VDDH
462
463 #if NRF_POWER_HAS_MAINREGSTATUS
464 /** @brief Main regulator status. */
465 typedef enum
466 {
467 NRF_POWER_MAINREGSTATUS_NORMAL = POWER_MAINREGSTATUS_MAINREGSTATUS_Normal, /**< Normal voltage mode. Voltage supplied on VDD. */
468 NRF_POWER_MAINREGSTATUS_HIGH = POWER_MAINREGSTATUS_MAINREGSTATUS_High /**< High voltage mode. Voltage supplied on VDDH. */
469 } nrf_power_mainregstatus_t;
470 #endif
471
472 #if defined(POWER_RAM_POWER_S0POWER_Msk) || defined(__NRFX_DOXYGEN__)
473 /**
474 * @brief Bit positions for RAMPOWER register
475 *
476 * All possible bits described, even if they are not used in selected MCU.
477 */
478 typedef enum
479 {
480 /** Keep RAM section S0 ON in System ON mode */
481 NRF_POWER_RAMPOWER_S0POWER = POWER_RAM_POWER_S0POWER_Pos,
482 NRF_POWER_RAMPOWER_S1POWER, /**< Keep RAM section S1 ON in System ON mode. */
483 NRF_POWER_RAMPOWER_S2POWER, /**< Keep RAM section S2 ON in System ON mode. */
484 NRF_POWER_RAMPOWER_S3POWER, /**< Keep RAM section S3 ON in System ON mode. */
485 NRF_POWER_RAMPOWER_S4POWER, /**< Keep RAM section S4 ON in System ON mode. */
486 NRF_POWER_RAMPOWER_S5POWER, /**< Keep RAM section S5 ON in System ON mode. */
487 NRF_POWER_RAMPOWER_S6POWER, /**< Keep RAM section S6 ON in System ON mode. */
488 NRF_POWER_RAMPOWER_S7POWER, /**< Keep RAM section S7 ON in System ON mode. */
489 NRF_POWER_RAMPOWER_S8POWER, /**< Keep RAM section S8 ON in System ON mode. */
490 NRF_POWER_RAMPOWER_S9POWER, /**< Keep RAM section S9 ON in System ON mode. */
491 NRF_POWER_RAMPOWER_S10POWER, /**< Keep RAM section S10 ON in System ON mode. */
492 NRF_POWER_RAMPOWER_S11POWER, /**< Keep RAM section S11 ON in System ON mode. */
493 NRF_POWER_RAMPOWER_S12POWER, /**< Keep RAM section S12 ON in System ON mode. */
494 NRF_POWER_RAMPOWER_S13POWER, /**< Keep RAM section S13 ON in System ON mode. */
495 NRF_POWER_RAMPOWER_S14POWER, /**< Keep RAM section S14 ON in System ON mode. */
496 NRF_POWER_RAMPOWER_S15POWER, /**< Keep RAM section S15 ON in System ON mode. */
497
498 /** Keep section retention in OFF mode when section is OFF */
499 NRF_POWER_RAMPOWER_S0RETENTION = POWER_RAM_POWER_S0RETENTION_Pos,
500 NRF_POWER_RAMPOWER_S1RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
501 NRF_POWER_RAMPOWER_S2RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
502 NRF_POWER_RAMPOWER_S3RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
503 NRF_POWER_RAMPOWER_S4RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
504 NRF_POWER_RAMPOWER_S5RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
505 NRF_POWER_RAMPOWER_S6RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
506 NRF_POWER_RAMPOWER_S7RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
507 NRF_POWER_RAMPOWER_S8RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
508 NRF_POWER_RAMPOWER_S9RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
509 NRF_POWER_RAMPOWER_S10RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
510 NRF_POWER_RAMPOWER_S11RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
511 NRF_POWER_RAMPOWER_S12RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
512 NRF_POWER_RAMPOWER_S13RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
513 NRF_POWER_RAMPOWER_S14RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
514 NRF_POWER_RAMPOWER_S15RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
515 } nrf_power_rampower_t;
516
517 /**
518 * @brief Bit masks for RAMPOWER register
519 *
520 * All possible bits described, even if they are not used in selected MCU.
521 */
522 typedef enum
523 {
524 NRF_POWER_RAMPOWER_S0POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S0POWER ,
525 NRF_POWER_RAMPOWER_S1POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S1POWER ,
526 NRF_POWER_RAMPOWER_S2POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S2POWER ,
527 NRF_POWER_RAMPOWER_S3POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S3POWER ,
528 NRF_POWER_RAMPOWER_S4POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S4POWER ,
529 NRF_POWER_RAMPOWER_S5POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S5POWER ,
530 NRF_POWER_RAMPOWER_S7POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S7POWER ,
531 NRF_POWER_RAMPOWER_S8POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S8POWER ,
532 NRF_POWER_RAMPOWER_S9POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S9POWER ,
533 NRF_POWER_RAMPOWER_S10POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S10POWER,
534 NRF_POWER_RAMPOWER_S11POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S11POWER,
535 NRF_POWER_RAMPOWER_S12POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S12POWER,
536 NRF_POWER_RAMPOWER_S13POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S13POWER,
537 NRF_POWER_RAMPOWER_S14POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S14POWER,
538 NRF_POWER_RAMPOWER_S15POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S15POWER,
539
540 NRF_POWER_RAMPOWER_S0RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S0RETENTION ,
541 NRF_POWER_RAMPOWER_S1RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S1RETENTION ,
542 NRF_POWER_RAMPOWER_S2RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S2RETENTION ,
543 NRF_POWER_RAMPOWER_S3RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S3RETENTION ,
544 NRF_POWER_RAMPOWER_S4RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S4RETENTION ,
545 NRF_POWER_RAMPOWER_S5RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S5RETENTION ,
546 NRF_POWER_RAMPOWER_S7RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S7RETENTION ,
547 NRF_POWER_RAMPOWER_S8RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S8RETENTION ,
548 NRF_POWER_RAMPOWER_S9RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S9RETENTION ,
549 NRF_POWER_RAMPOWER_S10RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S10RETENTION,
550 NRF_POWER_RAMPOWER_S11RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S11RETENTION,
551 NRF_POWER_RAMPOWER_S12RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S12RETENTION,
552 NRF_POWER_RAMPOWER_S13RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S13RETENTION,
553 NRF_POWER_RAMPOWER_S14RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S14RETENTION,
554 NRF_POWER_RAMPOWER_S15RETENTION_MASK = (int)(1UL << NRF_POWER_RAMPOWER_S15RETENTION),
555 } nrf_power_rampower_mask_t;
556 #endif // defined(POWER_RAM_POWER_S0POWER_Msk) || defined(__NRFX_DOXYGEN__)
557
558 #if NRF_POWER_HAS_VREG_CONFIG
559 /** @brief POWER voltage regulators bit masks. */
560 typedef enum
561 {
562 NRF_POWER_VREG_1V8_MASK = POWER_REGCONFIG_VREG1V8_Msk, ///< 1.8 V regulator.
563 NRF_POWER_VREG_1V0_MASK = POWER_REGCONFIG_VREG1V0_Msk, ///< 1.0 V regulator.
564 NRF_POWER_VREG_0V8_MASK = POWER_REGCONFIG_VREG0V8_Msk, ///< 0.8 V regulator.
565 NRF_POWER_VREG_VS_MASK = POWER_REGCONFIG_VREGVS_Msk, ///< Voltage scaled regulator.
566 NRF_POWER_VREG_MAIN1V8_MASK = POWER_REGCONFIG_VREGMAIN1V8_Msk, ///< 1.8 V rail at VREGMAIN regulator.
567 NRF_POWER_VREG_MAIN1V0_MASK = POWER_REGCONFIG_VREGMAIN1V0_Msk, ///< 1.0 V rail at VREGMAIN regulator.
568 NRF_POWER_VREG_MAINVS_MASK = POWER_REGCONFIG_VREGMAINVS_Msk, ///< Voltage scaled rail at VREGMAIN regulator.
569 NRF_POWER_VREG_FORCE_MASK = POWER_REGCONFIG_FORCE_Msk, ///< Force the regulator enable configuration.
570 } nrf_power_vreg_mask_t;
571 #endif // NRF_POWER_HAS_VREG_CONFIG
572
573 #if NRF_POWER_HAS_ABB
574 /** @brief POWER operating points for ABB domain. */
575 typedef enum
576 {
577 NRF_POWER_OP_POINT_0V4 = POWER_ABB_OPPOINT_OPPOINT_OpPoint0V4, ///< Operating point 0.4 V.
578 NRF_POWER_OP_POINT_0V5 = POWER_ABB_OPPOINT_OPPOINT_OpPoint0V5, ///< Operating point 0.5 V.
579 NRF_POWER_OP_POINT_0V6 = POWER_ABB_OPPOINT_OPPOINT_OpPoint0V6, ///< Operating point 0.6 V.
580 NRF_POWER_OP_POINT_0V8 = POWER_ABB_OPPOINT_OPPOINT_OpPoint0V8, ///< Operating point 0.8 V.
581 } nrf_power_op_point_t;
582
583 /** @brief POWER operating points for ABB domain. */
584 typedef enum
585 {
586 NRF_POWER_OVERRIDE_VALUE_POWER_DOWN = POWER_ABB_OPPOINT_ABBPWROVERRIDEVAL_PowerDown, ///< ABB analog macro powered down.
587 NRF_POWER_OVERRIDE_VALUE_POWER_UP = POWER_ABB_OPPOINT_ABBPWROVERRIDEVAL_PowerUp, ///< ABB analog macro powered up.
588 } nrf_power_override_value_t;
589
590 /** @brief POWER operating point for ABB domain structure. */
591 typedef struct
592 {
593 nrf_power_op_point_t op_point; ///< ABB operating point.
594 nrf_power_override_value_t override_value; ///< Override value of ABB analog macro powerup signal.
595 /**< Value is applied only if @p override_enable is enabled. */
596 bool override_enable; ///< True if the override of ABB analog macro signal is to be applied, false otherwise.
597 } nrf_power_abb_config_t;
598 #endif // NRF_POWER_HAS_ABB
599
600 /**
601 * @brief Function for activating a specific POWER task.
602 *
603 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
604 * @param[in] task Task.
605 */
606 NRF_STATIC_INLINE void nrf_power_task_trigger(NRF_POWER_Type * p_reg, nrf_power_task_t task);
607
608 /**
609 * @brief Function for returning the address of a specific POWER task register.
610 *
611 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
612 * @param[in] task Task.
613 *
614 * @return Task address.
615 */
616 NRF_STATIC_INLINE uint32_t nrf_power_task_address_get(NRF_POWER_Type const * p_reg,
617 nrf_power_task_t task);
618
619 /**
620 * @brief Function for clearing a specific event.
621 *
622 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
623 * @param[in] event Event.
624 */
625 NRF_STATIC_INLINE void nrf_power_event_clear(NRF_POWER_Type * p_reg, nrf_power_event_t event);
626
627 /**
628 * @brief Function for retrieving the state of the POWER event.
629 *
630 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
631 * @param[in] event Event to be checked.
632 *
633 * @retval true The event has been generated.
634 * @retval false The event has not been generated.
635 */
636 NRF_STATIC_INLINE bool nrf_power_event_check(NRF_POWER_Type const * p_reg, nrf_power_event_t event);
637
638 /**
639 * @brief Function for getting and clearing the state of specific event
640 *
641 * This function checks the state of the event and clears it.
642 *
643 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
644 * @param[in] event Event.
645 *
646 * @retval true The event was set.
647 * @retval false The event was not set.
648 */
649 NRF_STATIC_INLINE bool nrf_power_event_get_and_clear(NRF_POWER_Type * p_reg,
650 nrf_power_event_t event);
651
652 /**
653 * @brief Function for returning the address of a specific POWER event register.
654 *
655 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
656 * @param[in] event Event.
657 *
658 * @return Address.
659 */
660 NRF_STATIC_INLINE uint32_t nrf_power_event_address_get(NRF_POWER_Type const * p_reg,
661 nrf_power_event_t event);
662
663 /**
664 * @brief Function for enabling selected interrupts.
665 *
666 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
667 * @param[in] mask Mask of interrupts to be enabled.
668 * Use @ref nrf_power_int_mask_t values for bit masking.
669 */
670 NRF_STATIC_INLINE void nrf_power_int_enable(NRF_POWER_Type * p_reg, uint32_t mask);
671
672 /**
673 * @brief Function for checking if the specified interrupts are enabled.
674 *
675 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
676 * @param[in] mask Mask of interrupts to be checked.
677 * Use @ref nrf_power_int_mask_t values for bit masking.
678 *
679 * @return Mask of enabled interrupts.
680 */
681 NRF_STATIC_INLINE uint32_t nrf_power_int_enable_check(NRF_POWER_Type const * p_reg, uint32_t mask);
682
683 /**
684 * @brief Function for retrieving the information about enabled interrupts.
685 *
686 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
687 *
688 * @return The flags of enabled interrupts.
689 */
690 NRF_STATIC_INLINE uint32_t nrf_power_int_enable_get(NRF_POWER_Type const * p_reg);
691
692 /**
693 * @brief Function for disabling selected interrupts.
694 *
695 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
696 * @param[in] mask Mask of interrupts to be disabled.
697 * Use @ref nrf_power_int_mask_t values for bit masking.
698 */
699 NRF_STATIC_INLINE void nrf_power_int_disable(NRF_POWER_Type * p_reg, uint32_t mask);
700
701 #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
702 /**
703 * @brief Function for setting the subscribe configuration for a given
704 * POWER task.
705 *
706 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
707 * @param[in] task Task for which to set the configuration.
708 * @param[in] channel Channel through which to subscribe events.
709 */
710 NRF_STATIC_INLINE void nrf_power_subscribe_set(NRF_POWER_Type * p_reg,
711 nrf_power_task_t task,
712 uint8_t channel);
713
714 /**
715 * @brief Function for clearing the subscribe configuration for a given
716 * POWER task.
717 *
718 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
719 * @param[in] task Task for which to clear the configuration.
720 */
721 NRF_STATIC_INLINE void nrf_power_subscribe_clear(NRF_POWER_Type * p_reg, nrf_power_task_t task);
722
723 /**
724 * @brief Function for setting the publish configuration for a given
725 * POWER event.
726 *
727 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
728 * @param[in] event Event for which to set the configuration.
729 * @param[in] channel Channel through which to publish the event.
730 */
731 NRF_STATIC_INLINE void nrf_power_publish_set(NRF_POWER_Type * p_reg,
732 nrf_power_event_t event,
733 uint8_t channel);
734
735 /**
736 * @brief Function for clearing the publish configuration for a given
737 * POWER event.
738 *
739 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
740 * @param[in] event Event for which to clear the configuration.
741 */
742 NRF_STATIC_INLINE void nrf_power_publish_clear(NRF_POWER_Type * p_reg, nrf_power_event_t event);
743 #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
744
745 #if NRF_POWER_HAS_RESETREAS
746 /**
747 * @brief Function for getting the reset reason bitmask.
748 *
749 * This function returns the reset reason bitmask.
750 * Unless cleared, the RESETREAS register is cumulative.
751 * A field is cleared by writing '1' to it (see @ref nrf_power_resetreas_clear).
752 * If none of the reset sources is flagged,
753 * the chip was reset from the on-chip reset generator,
754 * which indicates a power-on-reset or a brown out reset.
755 *
756 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
757 *
758 * @return The mask of reset reasons constructed with @ref nrf_power_resetreas_mask_t.
759 */
760 NRF_STATIC_INLINE uint32_t nrf_power_resetreas_get(NRF_POWER_Type const * p_reg);
761
762 /**
763 * @brief Function for clearing the selected reset reason field.
764 *
765 * This function clears the selected reset reason field.
766 *
767 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
768 * @param[in] mask The mask constructed from @ref nrf_power_resetreas_mask_t enumerator values.
769 *
770 * @sa nrf_power_resetreas_get
771 */
772 NRF_STATIC_INLINE void nrf_power_resetreas_clear(NRF_POWER_Type * p_reg, uint32_t mask);
773 #endif // NRF_POWER_HAS_RESETREAS
774
775 #if defined(POWER_POWERSTATUS_LTEMODEM_Msk) || defined(__NRFX_DOXYGEN__)
776 /**
777 * @brief Function for getting power status of the LTE Modem domain.
778 *
779 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
780 *
781 * @retval true The LTE Modem domain is powered on.
782 * @retval false The LTE Modem domain is powered off.
783 */
784 NRF_STATIC_INLINE bool nrf_power_powerstatus_get(NRF_POWER_Type const * p_reg);
785 #endif
786
787 #if defined(POWER_RAMSTATUS_RAMBLOCK0_Msk) || defined(__NRFX_DOXYGEN__)
788 /**
789 * @brief Function for getting the RAMSTATUS register.
790 *
791 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
792 *
793 * @return Value with bits set according to the masks in @ref nrf_power_ramblock_mask_t.
794 */
795 NRF_STATIC_INLINE uint32_t nrf_power_ramstatus_get(NRF_POWER_Type const * p_reg);
796 #endif // defined(POWER_RAMSTATUS_RAMBLOCK0_Msk) || defined(__NRFX_DOXYGEN__)
797
798 #if defined(POWER_SYSTEMOFF_SYSTEMOFF_Enter)
799 /**
800 * @brief Function for going into System OFF mode.
801 *
802 * This function puts the CPU in System OFF mode.
803 * The only way to wake up the CPU is by reset.
804 *
805 * @note This function never returns.
806 *
807 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
808 */
809 NRF_STATIC_INLINE void nrf_power_system_off(NRF_POWER_Type * p_reg);
810 #endif // defined(POWER_SYSTEMOFF_SYSTEMOFF_Enter)
811
812 #if NRF_POWER_HAS_POFCON
813 /**
814 * @brief Function for setting the power failure comparator configuration.
815 *
816 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
817 * @param[in] enable True if the power failure comparator is to be enabled, false otherwise.
818 * @param[in] thr Voltage threshold value.
819 */
820 NRF_STATIC_INLINE void nrf_power_pofcon_set(NRF_POWER_Type * p_reg,
821 bool enable,
822 nrf_power_pof_thr_t thr);
823
824 /**
825 * @brief Function for getting the power failure comparator configuration.
826 *
827 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
828 * @param[out] p_enabled Function sets this boolean variable to true
829 * if power failure comparator is enabled.
830 * The pointer can be NULL if we do not need this information.
831 *
832 * @return Threshold setting for power failure comparator.
833 */
834 NRF_STATIC_INLINE nrf_power_pof_thr_t nrf_power_pofcon_get(NRF_POWER_Type const * p_reg,
835 bool * p_enabled);
836 #endif // NRF_POWER_HAS_POFCON
837
838 #if NRF_POWER_HAS_POFCON_VDDH
839 /**
840 * @brief Function for setting the VDDH power failure comparator threshold.
841 *
842 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
843 * @param[in] thr Threshold to be set.
844 */
845 NRF_STATIC_INLINE void nrf_power_pofcon_vddh_set(NRF_POWER_Type * p_reg,
846 nrf_power_pof_thrvddh_t thr);
847
848 /**
849 * @brief Function for getting the VDDH power failure comparator threshold.
850 *
851 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
852 *
853 * @return VDDH threshold currently configured.
854 */
855 NRF_STATIC_INLINE nrf_power_pof_thrvddh_t nrf_power_pofcon_vddh_get(NRF_POWER_Type const * p_reg);
856 #endif // NRF_POWER_HAS_POFCON_VDDH
857
858 #if NRF_POWER_HAS_GPREGRET
859 /**
860 * @brief Function for setting the general purpose retention register.
861 *
862 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
863 * @param[in] reg_num General purpose retention register number.
864 * @param[in] val Value to be set in the register.
865 */
866 NRF_STATIC_INLINE void nrf_power_gpregret_set(NRF_POWER_Type * p_reg,
867 uint32_t reg_num,
868 uint32_t val);
869
870 /**
871 * @brief Function for getting general purpose retention register.
872 *
873 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
874 * @param[in] reg_num General purpose retention register number.
875 *
876 * @return Value from the register.
877 */
878 NRF_STATIC_INLINE uint32_t nrf_power_gpregret_get(NRF_POWER_Type const * p_reg, uint32_t reg_num);
879 #endif // NRF_POWER_HAS_GPREGRET
880
881 #if NRF_POWER_HAS_DCDCEN
882 /**
883 * @brief Enable or disable DCDC converter
884 *
885 * @note If the device consist of high voltage power input (VDDH), this setting
886 * will relate to the converter on low voltage side (1.3 V output).
887 *
888 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
889 * @param[in] enable True if DCDC converter is to be enabled, false otherwise.
890 */
891 NRF_STATIC_INLINE void nrf_power_dcdcen_set(NRF_POWER_Type * p_reg, bool enable);
892
893 /**
894 * @brief Function for getting the state of the DCDC converter.
895 *
896 * @note If the device consist of high voltage power input (VDDH), this setting
897 * will relate to the converter on low voltage side (1.3 V output).
898 *
899 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
900 *
901 * @retval true Converter is enabled.
902 * @retval false Converter is disabled.
903 */
904 NRF_STATIC_INLINE bool nrf_power_dcdcen_get(NRF_POWER_Type const * p_reg);
905 #endif // NRF_POWER_HAS_DCDCEN
906
907 #if defined(POWER_RAM_POWER_S0POWER_Msk) || defined(__NRFX_DOXYGEN__)
908 /**
909 * @brief Turn ON sections in the selected RAM block.
910 *
911 * This function turns ON several sections in one block and also block retention.
912 *
913 * @sa nrf_power_rampower_mask_t
914 * @sa nrf_power_rampower_mask_off
915 *
916 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
917 * @param[in] block RAM block index.
918 * @param[in] section_mask Mask of the sections created by merging
919 * @ref nrf_power_rampower_mask_t flags.
920 */
921 NRF_STATIC_INLINE void nrf_power_rampower_mask_on(NRF_POWER_Type * p_reg,
922 uint8_t block,
923 uint32_t section_mask);
924
925 /**
926 * @brief Turn ON sections in the selected RAM block.
927 *
928 * This function turns OFF several sections in one block and also block retention.
929 *
930 * @sa nrf_power_rampower_mask_t
931 * @sa nrf_power_rampower_mask_off
932 *
933 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
934 * @param[in] block RAM block index.
935 * @param[in] section_mask Mask of the sections created by merging
936 * @ref nrf_power_rampower_mask_t flags.
937 */
938 NRF_STATIC_INLINE void nrf_power_rampower_mask_off(NRF_POWER_Type * p_reg,
939 uint8_t block,
940 uint32_t section_mask);
941
942 /**
943 * @brief Function for getting the ON mask and retention sections in the selected RAM block.
944 *
945 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
946 * @param[in] block RAM block index.
947 *
948 * @return Mask of sections state composed from @ref nrf_power_rampower_mask_t flags.
949 */
950 NRF_STATIC_INLINE uint32_t nrf_power_rampower_mask_get(NRF_POWER_Type const * p_reg, uint8_t block);
951 #endif /* defined(POWER_RAM_POWER_S0POWER_Msk) || defined(__NRFX_DOXYGEN__) */
952
953 #if NRF_POWER_HAS_DCDCEN_VDDH
954 /**
955 * @brief Function for enabling or disabling the DCDC converter on VDDH.
956 *
957 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
958 * @param[in] enable True if DCDC converter on VDDH is to be enabled, false otherwise.
959 */
960 NRF_STATIC_INLINE void nrf_power_dcdcen_vddh_set(NRF_POWER_Type * p_reg, bool enable);
961
962 /**
963 * @brief Function for getting the state of DCDC converter on VDDH.
964 *
965 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
966 *
967 * @retval true Converter is enabled.
968 * @retval false Converter is disabled.
969 */
970 NRF_STATIC_INLINE bool nrf_power_dcdcen_vddh_get(NRF_POWER_Type const * p_reg);
971 #endif // NRF_POWER_HAS_DCDCEN_VDDH
972
973 #if NRF_POWER_HAS_MAINREGSTATUS
974 /**
975 * @brief Function for getting the main supply status.
976 *
977 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
978 *
979 * @return The current main supply status.
980 */
981 NRF_STATIC_INLINE
982 nrf_power_mainregstatus_t nrf_power_mainregstatus_get(NRF_POWER_Type const * p_reg);
983 #endif // NRF_POWER_HAS_MAINREGSTATUS
984
985 #if NRF_POWER_HAS_USBREG
986 /**
987 * @brief Function for getting the whole USBREGSTATUS register.
988 *
989 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
990 *
991 * @return The USBREGSTATUS register value.
992 * Use @ref nrf_power_usbregstatus_mask_t values for bit masking.
993 *
994 * @sa nrf_power_usbregstatus_vbusdet_get
995 * @sa nrf_power_usbregstatus_outrdy_get
996 */
997 NRF_STATIC_INLINE uint32_t nrf_power_usbregstatus_get(NRF_POWER_Type const * p_reg);
998
999 /**
1000 * @brief Function for getting the VBUS input detection status.
1001 *
1002 * USBDETECTED and USBREMOVED events are derived from this information
1003 *
1004 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1005 *
1006 * @retval false VBUS voltage below valid threshold.
1007 * @retval true VBUS voltage above valid threshold.
1008 *
1009 * @sa nrf_power_usbregstatus_get
1010 */
1011 NRF_STATIC_INLINE bool nrf_power_usbregstatus_vbusdet_get(NRF_POWER_Type const * p_reg);
1012
1013 /**
1014 * @brief Function for getting the state of the elapsed time for the USB supply output settling.
1015 *
1016 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1017 *
1018 * @retval false USBREG output settling time not elapsed.
1019 * @retval true USBREG output settling time elapsed
1020 * (same information as USBPWRRDY event).
1021 *
1022 * @sa nrf_power_usbregstatus_get
1023 */
1024 NRF_STATIC_INLINE bool nrf_power_usbregstatus_outrdy_get(NRF_POWER_Type const * p_reg);
1025 #endif // NRF_POWER_HAS_USBREG
1026
1027 #if NRF_POWER_HAS_ABB
1028 /**
1029 * @brief Function for checking whether the specified ABB domain is busy.
1030 *
1031 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1032 * @param[in] domain_idx Index of ABB domain.
1033 *
1034 * @retval true The ABB is busy with applying the new operating point.
1035 * @retval false The ABB is ready to accept the new operating point.
1036 */
1037 NRF_STATIC_INLINE bool nrf_power_abb_busy_check(NRF_POWER_Type const * p_reg, uint8_t domain_idx);
1038
1039 /**
1040 * @brief Function for setting configuration of the operating point for the specified ABB domain.
1041 *
1042 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1043 * @param[in] domain_idx Index of ABB domain.
1044 * @param[in] p_config Pointer to the structure with configuration to be set.
1045 */
1046 NRF_STATIC_INLINE void nrf_power_abb_config_set(NRF_POWER_Type * p_reg,
1047 uint8_t domain_idx,
1048 nrf_power_abb_config_t const * p_config);
1049
1050 /**
1051 * @brief Function for getting configuration of the operating point for the specified ABB domain.
1052 *
1053 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1054 * @param[in] domain_idx Index of ABB domain.
1055 * @param[in] p_config Pointer to the structure with configuration to be set.
1056 */
1057 NRF_STATIC_INLINE void nrf_power_abb_config_get(NRF_POWER_Type const * p_reg,
1058 uint8_t domain_idx,
1059 nrf_power_abb_config_t * p_config);
1060
1061 /**
1062 * @brief Function for setting the force lock for the specified ABB domain.
1063 *
1064 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1065 * @param[in] domain_idx Index of ABB domain.
1066 * @param[in] enable True if force lock is to be enabled, false otherwise.
1067 */
1068 NRF_STATIC_INLINE void nrf_power_abb_force_lock_set(NRF_POWER_Type * p_reg,
1069 uint8_t domain_idx,
1070 bool enable);
1071
1072 /**
1073 * @brief Function for checking if the force lock for the specified ABB domain is enabled.
1074 *
1075 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1076 * @param[in] domain_idx Index of ABB domain whose status is checked.
1077 *
1078 * @retval true Force lock is enabled.
1079 * @retval false Force lock is disabled.
1080 */
1081 NRF_STATIC_INLINE bool nrf_power_abb_force_lock_check(NRF_POWER_Type const * p_reg,
1082 uint8_t domain_idx);
1083 #endif // NRF_POWER_HAS_ABB
1084
1085 #if NRF_POWER_HAS_VREG_CONFIG
1086 /**
1087 * @brief Function for enabling specified voltage regulator.
1088 *
1089 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1090 * @param[in] mask Mask of voltage regulators to be enabled.
1091 * Use @ref nrf_power_vreg_mask_t values for bit masking.
1092 */
1093 NRF_STATIC_INLINE void nrf_power_vreg_enable(NRF_POWER_Type * p_reg, uint32_t mask);
1094
1095 /**
1096 * @brief Function for disabling specified voltage regulator.
1097 *
1098 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1099 * @param[in] mask Mask of voltage regulators to be disabled.
1100 * Use @ref nrf_power_vreg_mask_t values for bit masking.
1101 */
1102 NRF_STATIC_INLINE void nrf_power_vreg_disable(NRF_POWER_Type * p_reg, uint32_t mask);
1103
1104 /**
1105 * @brief Function for checking if the specified voltage regulator is enabled.
1106 *
1107 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1108 * @param[in] mask Mask of voltage regulator to be checked.
1109 * Use @ref nrf_power_vreg_mask_t values for bit masking.
1110 *
1111 * @return Mask of enabled voltage regulators.
1112 */
1113 NRF_STATIC_INLINE uint32_t nrf_power_vreg_enable_check(NRF_POWER_Type const * p_reg, uint32_t mask);
1114 #endif // NRF_POWER_HAS_VREG_CONFIG
1115
1116 #if NRF_POWER_HAS_BLOCK_MODES
1117 /**
1118 * @brief Function for setting the Ultra Low Power (ULP) mode.
1119 *
1120 * @note Going into ULP mode is allowed only if this mode is enabled - otherwise it is blocked.
1121 * If the ULV mode is blocked, the ULP mode is also blocked.
1122 *
1123 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1124 * @param[in] enable True if ULP mode is to be enabled, false otherwise.
1125 */
1126 NRF_STATIC_INLINE void nrf_power_ulp_mode_set(NRF_POWER_Type * p_reg, bool enable);
1127
1128 /**
1129 * @brief Function for checking if the ULP mode is enabled.
1130 *
1131 * @note Going into ULP mode is allowed only if this mode is enabled - otherwise it is blocked.
1132 * If the ULV mode is blocked, the ULP mode is also blocked.
1133 *
1134 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1135 *
1136 * @retval true ULP mode is enabled.
1137 * @retval false ULP mode is disabled.
1138 */
1139 NRF_STATIC_INLINE bool nrf_power_ulp_mode_check(NRF_POWER_Type const * p_reg);
1140
1141 /**
1142 * @brief Function for setting the Ultra Low Voltage (ULV) mode.
1143 *
1144 * @note Going into ULP mode is allowed only if this mode is enabled - otherwise it is blocked.
1145 * If the ULV mode is blocked, the ULP mode is also blocked.
1146 *
1147 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1148 * @param[in] enable True if ULV mode is to be enabled, false otherwise.
1149 */
1150 NRF_STATIC_INLINE void nrf_power_ulv_mode_set(NRF_POWER_Type * p_reg, bool enable);
1151
1152 /**
1153 * @brief Function for checking if the ULV mode is enabled.
1154 *
1155 * @note Going into ULP mode is allowed only if this mode is enabled - otherwise it is blocked.
1156 * If the ULV mode is blocked, the ULP mode is also blocked.
1157 *
1158 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1159 *
1160 * @retval true ULV mode is enabled.
1161 * @retval false ULV mode is disabled.
1162 */
1163 NRF_STATIC_INLINE bool nrf_power_ulv_mode_check(NRF_POWER_Type const * p_reg);
1164 #endif // NRF_POWER_HAS_BLOCK_MODES
1165
1166 #if NRF_POWER_HAS_SEMAPHORE
1167 /**
1168 * @brief Function for getting the POWER semaphore status.
1169 *
1170 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1171 *
1172 * @retval true Semaphore is acquired.
1173 * @retval false Semaphore is released.
1174 */
1175 NRF_STATIC_INLINE bool nrf_power_sem_status_get(NRF_POWER_Type const * p_reg);
1176 #endif // NRF_POWER_HAS_SEMAPHORE
1177
1178 #if NRF_POWER_HAS_BILS
1179 /**
1180 * @brief Function for setting BILS instances.
1181 *
1182 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1183 * @param[in] enable True if all configured BILS instances are to be enabled, false otherwise.
1184 */
1185 NRF_STATIC_INLINE void nrf_power_bils_set(NRF_POWER_Type * p_reg, bool enable);
1186
1187 /**
1188 * @brief Function for checking if BILS instances are enabled.
1189 *
1190 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1191 *
1192 * @retval true All configured BILS instances are enabled.
1193 * @retval false All BILS instances are disabled.
1194 */
1195 NRF_STATIC_INLINE bool nrf_power_bils_check(NRF_POWER_Type const * p_reg);
1196 #endif // NRF_POWER_HAS_BILS
1197
1198 #if NRF_POWER_HAS_PMIC
1199 /**
1200 * @brief Function for setting the PMIC interface.
1201 *
1202 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1203 * @param[in] enable True if PMIC interface is to be enabled, false otherwise.
1204 */
1205 NRF_STATIC_INLINE void nrf_power_pmic_set(NRF_POWER_Type * p_reg, bool enable);
1206
1207 /**
1208 * @brief Function for checking if the PMIC interface is enabled.
1209 *
1210 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1211 *
1212 * @retval true PMIC interface is enabled.
1213 * @retval false PMIC interface is disabled.
1214 */
1215 NRF_STATIC_INLINE bool nrf_power_pmic_check(NRF_POWER_Type const * p_reg);
1216 #endif // NRF_POWER_HAS_PMIC
1217
1218 #ifndef NRF_DECLARE_ONLY
1219
nrf_power_task_trigger(NRF_POWER_Type * p_reg,nrf_power_task_t task)1220 NRF_STATIC_INLINE void nrf_power_task_trigger(NRF_POWER_Type * p_reg, nrf_power_task_t task)
1221 {
1222 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
1223 }
1224
nrf_power_task_address_get(NRF_POWER_Type const * p_reg,nrf_power_task_t task)1225 NRF_STATIC_INLINE uint32_t nrf_power_task_address_get(NRF_POWER_Type const * p_reg,
1226 nrf_power_task_t task)
1227 {
1228 return ((uint32_t)p_reg + (uint32_t)task);
1229 }
1230
nrf_power_event_clear(NRF_POWER_Type * p_reg,nrf_power_event_t event)1231 NRF_STATIC_INLINE void nrf_power_event_clear(NRF_POWER_Type * p_reg, nrf_power_event_t event)
1232 {
1233 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
1234 nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
1235 }
1236
nrf_power_event_check(NRF_POWER_Type const * p_reg,nrf_power_event_t event)1237 NRF_STATIC_INLINE bool nrf_power_event_check(NRF_POWER_Type const * p_reg, nrf_power_event_t event)
1238 {
1239 return nrf_event_check(p_reg, event);
1240 }
1241
nrf_power_event_get_and_clear(NRF_POWER_Type * p_reg,nrf_power_event_t event)1242 NRF_STATIC_INLINE bool nrf_power_event_get_and_clear(NRF_POWER_Type * p_reg,
1243 nrf_power_event_t event)
1244 {
1245 bool ret = nrf_power_event_check(p_reg, event);
1246 if (ret)
1247 {
1248 nrf_power_event_clear(p_reg, event);
1249 }
1250 return ret;
1251 }
1252
nrf_power_event_address_get(NRF_POWER_Type const * p_reg,nrf_power_event_t event)1253 NRF_STATIC_INLINE uint32_t nrf_power_event_address_get(NRF_POWER_Type const * p_reg,
1254 nrf_power_event_t event)
1255 {
1256 return ((uint32_t)p_reg + (uint32_t)event);
1257 }
1258
nrf_power_int_enable(NRF_POWER_Type * p_reg,uint32_t mask)1259 NRF_STATIC_INLINE void nrf_power_int_enable(NRF_POWER_Type * p_reg, uint32_t mask)
1260 {
1261 p_reg->INTENSET = mask;
1262 }
1263
nrf_power_int_enable_check(NRF_POWER_Type const * p_reg,uint32_t mask)1264 NRF_STATIC_INLINE uint32_t nrf_power_int_enable_check(NRF_POWER_Type const * p_reg, uint32_t mask)
1265 {
1266 return p_reg->INTENSET & mask;
1267 }
1268
nrf_power_int_enable_get(NRF_POWER_Type const * p_reg)1269 NRF_STATIC_INLINE uint32_t nrf_power_int_enable_get(NRF_POWER_Type const * p_reg)
1270 {
1271 return p_reg->INTENSET;
1272 }
1273
nrf_power_int_disable(NRF_POWER_Type * p_reg,uint32_t mask)1274 NRF_STATIC_INLINE void nrf_power_int_disable(NRF_POWER_Type * p_reg, uint32_t mask)
1275 {
1276 p_reg->INTENCLR = mask;
1277 }
1278
1279 #if defined(DPPI_PRESENT)
nrf_power_subscribe_set(NRF_POWER_Type * p_reg,nrf_power_task_t task,uint8_t channel)1280 NRF_STATIC_INLINE void nrf_power_subscribe_set(NRF_POWER_Type * p_reg,
1281 nrf_power_task_t task,
1282 uint8_t channel)
1283 {
1284 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
1285 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
1286 }
1287
nrf_power_subscribe_clear(NRF_POWER_Type * p_reg,nrf_power_task_t task)1288 NRF_STATIC_INLINE void nrf_power_subscribe_clear(NRF_POWER_Type * p_reg, nrf_power_task_t task)
1289 {
1290 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
1291 }
1292
nrf_power_publish_set(NRF_POWER_Type * p_reg,nrf_power_event_t event,uint8_t channel)1293 NRF_STATIC_INLINE void nrf_power_publish_set(NRF_POWER_Type * p_reg,
1294 nrf_power_event_t event,
1295 uint8_t channel)
1296 {
1297 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
1298 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
1299 }
1300
nrf_power_publish_clear(NRF_POWER_Type * p_reg,nrf_power_event_t event)1301 NRF_STATIC_INLINE void nrf_power_publish_clear(NRF_POWER_Type * p_reg, nrf_power_event_t event)
1302 {
1303 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
1304 }
1305 #endif // defined(DPPI_PRESENT)
1306
1307 #if NRF_POWER_HAS_RESETREAS
nrf_power_resetreas_get(NRF_POWER_Type const * p_reg)1308 NRF_STATIC_INLINE uint32_t nrf_power_resetreas_get(NRF_POWER_Type const * p_reg)
1309 {
1310 return p_reg->RESETREAS;
1311 }
1312
nrf_power_resetreas_clear(NRF_POWER_Type * p_reg,uint32_t mask)1313 NRF_STATIC_INLINE void nrf_power_resetreas_clear(NRF_POWER_Type * p_reg, uint32_t mask)
1314 {
1315 p_reg->RESETREAS = mask;
1316 }
1317 #endif // NRF_POWER_HAS_RESETREAS
1318
1319 #if defined(POWER_POWERSTATUS_LTEMODEM_Msk)
nrf_power_powerstatus_get(NRF_POWER_Type const * p_reg)1320 NRF_STATIC_INLINE bool nrf_power_powerstatus_get(NRF_POWER_Type const * p_reg)
1321 {
1322 return (p_reg->POWERSTATUS & POWER_POWERSTATUS_LTEMODEM_Msk) ==
1323 (POWER_POWERSTATUS_LTEMODEM_ON << POWER_POWERSTATUS_LTEMODEM_Pos);
1324 }
1325 #endif // (POWER_POWERSTATUS_LTEMODEM_Msk)
1326
1327 #if defined(POWER_RAMSTATUS_RAMBLOCK0_Msk)
nrf_power_ramstatus_get(NRF_POWER_Type const * p_reg)1328 NRF_STATIC_INLINE uint32_t nrf_power_ramstatus_get(NRF_POWER_Type const * p_reg)
1329 {
1330 return p_reg->RAMSTATUS;
1331 }
1332 #endif // defined(POWER_RAMSTATUS_RAMBLOCK0_Msk)
1333
1334 #if defined(POWER_SYSTEMOFF_SYSTEMOFF_Enter)
nrf_power_system_off(NRF_POWER_Type * p_reg)1335 NRF_STATIC_INLINE void nrf_power_system_off(NRF_POWER_Type * p_reg)
1336 {
1337 p_reg->SYSTEMOFF = POWER_SYSTEMOFF_SYSTEMOFF_Enter;
1338 __DSB();
1339
1340 /* Solution for simulated System OFF in debug mode */
1341 while (true)
1342 {
1343 __WFE();
1344 }
1345 }
1346 #endif // defined(POWER_SYSTEMOFF_SYSTEMOFF_Enter)
1347
1348 #if NRF_POWER_HAS_POFCON
nrf_power_pofcon_set(NRF_POWER_Type * p_reg,bool enable,nrf_power_pof_thr_t thr)1349 NRF_STATIC_INLINE void nrf_power_pofcon_set(NRF_POWER_Type * p_reg,
1350 bool enable,
1351 nrf_power_pof_thr_t thr)
1352 {
1353 NRFX_ASSERT(thr == (thr & (POWER_POFCON_THRESHOLD_Msk >> POWER_POFCON_THRESHOLD_Pos)));
1354 #if NRF_POWER_HAS_POFCON_VDDH
1355 uint32_t pofcon = p_reg->POFCON;
1356 pofcon &= ~(POWER_POFCON_THRESHOLD_Msk | POWER_POFCON_POF_Msk);
1357 pofcon |=
1358 #else // NRF_POWER_HAS_POFCON_VDDH
1359 p_reg->POFCON =
1360 #endif
1361 (((uint32_t)thr) << POWER_POFCON_THRESHOLD_Pos) |
1362 (enable ?
1363 (POWER_POFCON_POF_Enabled << POWER_POFCON_POF_Pos)
1364 :
1365 (POWER_POFCON_POF_Disabled << POWER_POFCON_POF_Pos));
1366 #if NRF_POWER_HAS_POFCON_VDDH
1367 p_reg->POFCON = pofcon;
1368 #endif
1369 }
1370
nrf_power_pofcon_get(NRF_POWER_Type const * p_reg,bool * p_enabled)1371 NRF_STATIC_INLINE nrf_power_pof_thr_t nrf_power_pofcon_get(NRF_POWER_Type const * p_reg,
1372 bool * p_enabled)
1373 {
1374 uint32_t pofcon = p_reg->POFCON;
1375 if (NULL != p_enabled)
1376 {
1377 (*p_enabled) = ((pofcon & POWER_POFCON_POF_Msk) >> POWER_POFCON_POF_Pos)
1378 == POWER_POFCON_POF_Enabled;
1379 }
1380 return (nrf_power_pof_thr_t)((pofcon & POWER_POFCON_THRESHOLD_Msk) >>
1381 POWER_POFCON_THRESHOLD_Pos);
1382 }
1383 #endif // NRF_POWER_HAS_POFCON
1384
1385 #if NRF_POWER_HAS_POFCON_VDDH
nrf_power_pofcon_vddh_set(NRF_POWER_Type * p_reg,nrf_power_pof_thrvddh_t thr)1386 NRF_STATIC_INLINE void nrf_power_pofcon_vddh_set(NRF_POWER_Type * p_reg,
1387 nrf_power_pof_thrvddh_t thr)
1388 {
1389 NRFX_ASSERT(thr == (thr & (POWER_POFCON_THRESHOLDVDDH_Msk >> POWER_POFCON_THRESHOLDVDDH_Pos)));
1390 uint32_t pofcon = p_reg->POFCON;
1391 pofcon &= ~POWER_POFCON_THRESHOLDVDDH_Msk;
1392 pofcon |= (((uint32_t)thr) << POWER_POFCON_THRESHOLDVDDH_Pos);
1393 p_reg->POFCON = pofcon;
1394 }
1395
nrf_power_pofcon_vddh_get(NRF_POWER_Type const * p_reg)1396 NRF_STATIC_INLINE nrf_power_pof_thrvddh_t nrf_power_pofcon_vddh_get(NRF_POWER_Type const * p_reg)
1397 {
1398 return (nrf_power_pof_thrvddh_t)((p_reg->POFCON & POWER_POFCON_THRESHOLDVDDH_Msk) >>
1399 POWER_POFCON_THRESHOLDVDDH_Pos);
1400 }
1401 #endif // NRF_POWER_HAS_POFCON_VDDH
1402
1403 #if NRF_POWER_HAS_GPREGRET
nrf_power_gpregret_set(NRF_POWER_Type * p_reg,uint32_t reg_num,uint32_t val)1404 NRF_STATIC_INLINE void nrf_power_gpregret_set(NRF_POWER_Type * p_reg,
1405 uint32_t reg_num,
1406 uint32_t val)
1407 {
1408 #if NRF_POWER_HAS_GPREGRET_ARRAY
1409 NRFX_ASSERT(reg_num < NRFX_POWER_GPREGRET_COUNT);
1410 #elif defined(POWER_GPREGRET2_GPREGRET_Msk)
1411 NRFX_ASSERT(reg_num < 2);
1412 #else
1413 NRFX_ASSERT(reg_num < 1);
1414 #endif
1415
1416 #if NRF_POWER_HAS_GPREGRET_ARRAY
1417 p_reg->GPREGRET[reg_num] = (val & POWER_GPREGRET_GPREGRET_Msk) << POWER_GPREGRET_GPREGRET_Pos;
1418 #else
1419 switch (reg_num)
1420 {
1421 case 0:
1422 p_reg->GPREGRET = (val & POWER_GPREGRET_GPREGRET_Msk) << POWER_GPREGRET_GPREGRET_Pos;
1423 break;
1424 #if defined(POWER_GPREGRET2_GPREGRET_Msk)
1425 case 1:
1426 p_reg->GPREGRET2 = (val & POWER_GPREGRET2_GPREGRET_Msk) << POWER_GPREGRET2_GPREGRET_Pos;
1427 break;
1428 #endif
1429 default:
1430 break;
1431 }
1432 #endif
1433 }
1434
nrf_power_gpregret_get(NRF_POWER_Type const * p_reg,uint32_t reg_num)1435 NRF_STATIC_INLINE uint32_t nrf_power_gpregret_get(NRF_POWER_Type const * p_reg, uint32_t reg_num)
1436 {
1437 #if NRF_POWER_HAS_GPREGRET_ARRAY
1438 NRFX_ASSERT(reg_num < NRFX_POWER_GPREGRET_COUNT);
1439 #elif defined(POWER_GPREGRET2_GPREGRET_Msk)
1440 NRFX_ASSERT(reg_num < 2);
1441 #else
1442 NRFX_ASSERT(reg_num < 1);
1443 #endif
1444
1445 #if NRF_POWER_HAS_GPREGRET_ARRAY
1446 return p_reg->GPREGRET[reg_num];
1447 #else
1448 switch (reg_num)
1449 {
1450 case 0:
1451 return p_reg->GPREGRET;
1452 #if defined(POWER_GPREGRET2_GPREGRET_Msk)
1453 case 1:
1454 return p_reg->GPREGRET2;
1455 #endif
1456 default:
1457 return 0;
1458 }
1459 #endif
1460 }
1461 #endif // NRF_POWER_HAS_GPREGRET
1462
1463 #if NRF_POWER_HAS_DCDCEN
nrf_power_dcdcen_set(NRF_POWER_Type * p_reg,bool enable)1464 NRF_STATIC_INLINE void nrf_power_dcdcen_set(NRF_POWER_Type * p_reg, bool enable)
1465 {
1466 p_reg->DCDCEN = (enable ? POWER_DCDCEN_DCDCEN_Enabled : POWER_DCDCEN_DCDCEN_Disabled) <<
1467 POWER_DCDCEN_DCDCEN_Pos;
1468 }
1469
nrf_power_dcdcen_get(NRF_POWER_Type const * p_reg)1470 NRF_STATIC_INLINE bool nrf_power_dcdcen_get(NRF_POWER_Type const * p_reg)
1471 {
1472 return (p_reg->DCDCEN & POWER_DCDCEN_DCDCEN_Msk)
1473 ==
1474 (POWER_DCDCEN_DCDCEN_Enabled << POWER_DCDCEN_DCDCEN_Pos);
1475 }
1476 #endif // NRF_POWER_HAS_DCDCEN
1477
1478 #if defined(POWER_RAM_POWER_S0POWER_Msk)
nrf_power_rampower_mask_on(NRF_POWER_Type * p_reg,uint8_t block,uint32_t section_mask)1479 NRF_STATIC_INLINE void nrf_power_rampower_mask_on(NRF_POWER_Type * p_reg,
1480 uint8_t block,
1481 uint32_t section_mask)
1482 {
1483 p_reg->RAM[block].POWERSET = section_mask;
1484 }
1485
nrf_power_rampower_mask_off(NRF_POWER_Type * p_reg,uint8_t block,uint32_t section_mask)1486 NRF_STATIC_INLINE void nrf_power_rampower_mask_off(NRF_POWER_Type * p_reg,
1487 uint8_t block,
1488 uint32_t section_mask)
1489 {
1490 p_reg->RAM[block].POWERCLR = section_mask;
1491 }
1492
nrf_power_rampower_mask_get(NRF_POWER_Type const * p_reg,uint8_t block)1493 NRF_STATIC_INLINE uint32_t nrf_power_rampower_mask_get(NRF_POWER_Type const * p_reg, uint8_t block)
1494 {
1495 return p_reg->RAM[block].POWER;
1496 }
1497 #endif // defined(POWER_RAM_POWER_S0POWER_Msk)
1498
1499 #if NRF_POWER_HAS_DCDCEN_VDDH
nrf_power_dcdcen_vddh_set(NRF_POWER_Type * p_reg,bool enable)1500 NRF_STATIC_INLINE void nrf_power_dcdcen_vddh_set(NRF_POWER_Type * p_reg, bool enable)
1501 {
1502 if (enable && nrf52_errata_197())
1503 {
1504 // Workaround for anomaly 197 "POWER: DCDC of REG0 not functional".
1505 *(volatile uint32_t *)0x40000638ul = 1ul;
1506 }
1507 p_reg->DCDCEN0 = (enable ? POWER_DCDCEN0_DCDCEN_Enabled : POWER_DCDCEN0_DCDCEN_Disabled) <<
1508 POWER_DCDCEN0_DCDCEN_Pos;
1509 }
1510
nrf_power_dcdcen_vddh_get(NRF_POWER_Type const * p_reg)1511 NRF_STATIC_INLINE bool nrf_power_dcdcen_vddh_get(NRF_POWER_Type const * p_reg)
1512 {
1513 return (p_reg->DCDCEN0 & POWER_DCDCEN0_DCDCEN_Msk)
1514 ==
1515 (POWER_DCDCEN0_DCDCEN_Enabled << POWER_DCDCEN0_DCDCEN_Pos);
1516 }
1517 #endif // NRF_POWER_HAS_DCDCEN_VDDH
1518
1519 #if NRF_POWER_HAS_MAINREGSTATUS
1520 NRF_STATIC_INLINE
nrf_power_mainregstatus_get(NRF_POWER_Type const * p_reg)1521 nrf_power_mainregstatus_t nrf_power_mainregstatus_get(NRF_POWER_Type const * p_reg)
1522 {
1523 return (nrf_power_mainregstatus_t)(((p_reg->MAINREGSTATUS) &
1524 POWER_MAINREGSTATUS_MAINREGSTATUS_Msk) >>
1525 POWER_MAINREGSTATUS_MAINREGSTATUS_Pos);
1526 }
1527 #endif // NRF_POWER_HAS_MAINREGSTATUS
1528
1529 #if NRF_POWER_HAS_USBREG
nrf_power_usbregstatus_get(NRF_POWER_Type const * p_reg)1530 NRF_STATIC_INLINE uint32_t nrf_power_usbregstatus_get(NRF_POWER_Type const * p_reg)
1531 {
1532 return p_reg->USBREGSTATUS;
1533 }
1534
nrf_power_usbregstatus_vbusdet_get(NRF_POWER_Type const * p_reg)1535 NRF_STATIC_INLINE bool nrf_power_usbregstatus_vbusdet_get(NRF_POWER_Type const * p_reg)
1536 {
1537 return (nrf_power_usbregstatus_get(p_reg) & NRF_POWER_USBREGSTATUS_VBUSDETECT_MASK) != 0;
1538 }
1539
nrf_power_usbregstatus_outrdy_get(NRF_POWER_Type const * p_reg)1540 NRF_STATIC_INLINE bool nrf_power_usbregstatus_outrdy_get(NRF_POWER_Type const * p_reg)
1541 {
1542 return (nrf_power_usbregstatus_get(p_reg) & NRF_POWER_USBREGSTATUS_OUTPUTRDY_MASK) != 0;
1543 }
1544 #endif // NRF_POWER_HAS_USBREG
1545
1546 #if NRF_POWER_HAS_ABB
nrf_power_abb_busy_check(NRF_POWER_Type const * p_reg,uint8_t domain_idx)1547 NRF_STATIC_INLINE bool nrf_power_abb_busy_check(NRF_POWER_Type const * p_reg, uint8_t domain_idx)
1548 {
1549 return ((p_reg->ABB[domain_idx].STATUS & POWER_ABB_STATUS_STATUS_Msk) ==
1550 (POWER_ABB_STATUS_STATUS_Busy << POWER_ABB_STATUS_STATUS_Pos));
1551 }
1552
nrf_power_abb_config_set(NRF_POWER_Type * p_reg,uint8_t domain_idx,nrf_power_abb_config_t const * p_config)1553 NRF_STATIC_INLINE void nrf_power_abb_config_set(NRF_POWER_Type * p_reg,
1554 uint8_t domain_idx,
1555 nrf_power_abb_config_t const * p_config)
1556 {
1557 p_reg->ABB[domain_idx].OPPOINT = ((p_config->op_point <<
1558 POWER_ABB_OPPOINT_OPPOINT_Pos) &
1559 POWER_ABB_OPPOINT_OPPOINT_Msk) |
1560 ((p_config->override_value <<
1561 POWER_ABB_OPPOINT_ABBPWROVERRIDEVAL_Pos) &
1562 POWER_ABB_OPPOINT_ABBPWROVERRIDEVAL_Msk) |
1563 ((p_config->override_enable ?
1564 POWER_ABB_OPPOINT_ABBPWROVERRIDEEN_Enabled :
1565 POWER_ABB_OPPOINT_ABBPWROVERRIDEEN_Disabled) <<
1566 POWER_ABB_OPPOINT_ABBPWROVERRIDEEN_Pos);
1567 }
1568
nrf_power_abb_config_get(NRF_POWER_Type const * p_reg,uint8_t domain_idx,nrf_power_abb_config_t * p_config)1569 NRF_STATIC_INLINE void nrf_power_abb_config_get(NRF_POWER_Type const * p_reg,
1570 uint8_t domain_idx,
1571 nrf_power_abb_config_t * p_config)
1572 {
1573 p_config->op_point = (nrf_power_op_point_t)((p_reg->ABB[domain_idx].OPPOINT &
1574 POWER_ABB_OPPOINT_OPPOINT_Msk) >>
1575 POWER_ABB_OPPOINT_OPPOINT_Pos);
1576
1577 p_config->override_value = (nrf_power_override_value_t)
1578 ((p_reg->ABB[domain_idx].OPPOINT &
1579 POWER_ABB_OPPOINT_ABBPWROVERRIDEVAL_Msk) >>
1580 POWER_ABB_OPPOINT_ABBPWROVERRIDEVAL_Pos);
1581
1582 p_config->override_enable = ((p_reg->ABB[domain_idx].OPPOINT &
1583 POWER_ABB_OPPOINT_ABBPWROVERRIDEEN_Msk) ==
1584 (POWER_ABB_OPPOINT_ABBPWROVERRIDEEN_Enabled <<
1585 POWER_ABB_OPPOINT_ABBPWROVERRIDEEN_Pos));
1586 }
1587
nrf_power_abb_force_lock_set(NRF_POWER_Type * p_reg,uint8_t domain_idx,bool enable)1588 NRF_STATIC_INLINE void nrf_power_abb_force_lock_set(NRF_POWER_Type * p_reg,
1589 uint8_t domain_idx,
1590 bool enable)
1591 {
1592 p_reg->ABB[domain_idx].FORCELOCK = ((enable ?
1593 POWER_ABB_FORCELOCK_ENABLE_Enabled :
1594 POWER_ABB_FORCELOCK_ENABLE_Disabled) <<
1595 POWER_ABB_FORCELOCK_ENABLE_Pos);
1596 }
1597
nrf_power_abb_force_lock_check(NRF_POWER_Type const * p_reg,uint8_t domain_idx)1598 NRF_STATIC_INLINE bool nrf_power_abb_force_lock_check(NRF_POWER_Type const * p_reg,
1599 uint8_t domain_idx)
1600 {
1601 return (p_reg->ABB[domain_idx].FORCELOCK & POWER_ABB_FORCELOCK_ENABLE_Msk) ==
1602 (POWER_ABB_FORCELOCK_ENABLE_Enabled << POWER_ABB_FORCELOCK_ENABLE_Pos);
1603 }
1604 #endif // NRF_POWER_HAS_ABB
1605
1606 #if NRF_POWER_HAS_VREG_CONFIG
nrf_power_vreg_enable(NRF_POWER_Type * p_reg,uint32_t mask)1607 NRF_STATIC_INLINE void nrf_power_vreg_enable(NRF_POWER_Type * p_reg, uint32_t mask)
1608 {
1609 p_reg->REGCONFIG = mask;
1610 }
1611
nrf_power_vreg_disable(NRF_POWER_Type * p_reg,uint32_t mask)1612 NRF_STATIC_INLINE void nrf_power_vreg_disable(NRF_POWER_Type * p_reg, uint32_t mask)
1613 {
1614 p_reg->REGCONFIG = ~mask;
1615 }
1616
nrf_power_vreg_enable_check(NRF_POWER_Type const * p_reg,uint32_t mask)1617 NRF_STATIC_INLINE uint32_t nrf_power_vreg_enable_check(NRF_POWER_Type const * p_reg, uint32_t mask)
1618 {
1619 return p_reg->REGCONFIG & mask;
1620 }
1621 #endif // NRF_POWER_HAS_VREG_CONFIG
1622
1623 #if NRF_POWER_HAS_BLOCK_MODES
nrf_power_ulp_mode_set(NRF_POWER_Type * p_reg,bool enable)1624 NRF_STATIC_INLINE void nrf_power_ulp_mode_set(NRF_POWER_Type * p_reg, bool enable)
1625 {
1626 p_reg->BLOCKULPMODE = (enable ? POWER_BLOCKULPMODE_BLOCK_Allowed :
1627 POWER_BLOCKULPMODE_BLOCK_Blocked) <<
1628 POWER_BLOCKULPMODE_BLOCK_Pos;
1629 }
1630
nrf_power_ulp_mode_check(NRF_POWER_Type const * p_reg)1631 NRF_STATIC_INLINE bool nrf_power_ulp_mode_check(NRF_POWER_Type const * p_reg)
1632 {
1633 return (p_reg->BLOCKULPMODE & POWER_BLOCKULPMODE_BLOCK_Msk) ==
1634 (POWER_BLOCKULPMODE_BLOCK_Allowed << POWER_BLOCKULPMODE_BLOCK_Pos);
1635 }
1636
nrf_power_ulv_mode_set(NRF_POWER_Type * p_reg,bool enable)1637 NRF_STATIC_INLINE void nrf_power_ulv_mode_set(NRF_POWER_Type * p_reg, bool enable)
1638 {
1639 p_reg->BLOCKULVMODE = (enable ? POWER_BLOCKULVMODE_BLOCK_Allowed :
1640 POWER_BLOCKULVMODE_BLOCK_Blocked) <<
1641 POWER_BLOCKULVMODE_BLOCK_Pos;
1642 }
1643
nrf_power_ulv_mode_check(NRF_POWER_Type const * p_reg)1644 NRF_STATIC_INLINE bool nrf_power_ulv_mode_check(NRF_POWER_Type const * p_reg)
1645 {
1646 return (p_reg->BLOCKULVMODE & POWER_BLOCKULVMODE_BLOCK_Msk) ==
1647 (POWER_BLOCKULVMODE_BLOCK_Allowed << POWER_BLOCKULVMODE_BLOCK_Pos);
1648 }
1649 #endif // NRF_POWER_HAS_BLOCK_MODES
1650
1651 #if NRF_POWER_HAS_SEMAPHORE
nrf_power_sem_status_get(NRF_POWER_Type const * p_reg)1652 NRF_STATIC_INLINE bool nrf_power_sem_status_get(NRF_POWER_Type const * p_reg)
1653 {
1654 return (p_reg->SEMAPHORESTATUS & POWER_SEMAPHORESTATUS_STATUS_Msk) ==
1655 (POWER_SEMAPHORESTATUS_STATUS_Acquired << POWER_SEMAPHORESTATUS_STATUS_Pos);
1656 }
1657 #endif // NRF_POWER_HAS_SEMAPHORE
1658
1659 #if NRF_POWER_HAS_BILS
nrf_power_bils_set(NRF_POWER_Type * p_reg,bool enable)1660 NRF_STATIC_INLINE void nrf_power_bils_set(NRF_POWER_Type * p_reg, bool enable)
1661 {
1662 p_reg->BILSENABLE = (enable ? POWER_BILSENABLE_ENABLE_Enabled :
1663 POWER_BILSENABLE_ENABLE_Disabled) <<
1664 POWER_BILSENABLE_ENABLE_Pos;
1665 }
1666
nrf_power_bils_check(NRF_POWER_Type const * p_reg)1667 NRF_STATIC_INLINE bool nrf_power_bils_check(NRF_POWER_Type const * p_reg)
1668 {
1669 return (p_reg->BILSENABLE & POWER_BILSENABLE_ENABLE_Msk) ==
1670 (POWER_BILSENABLE_ENABLE_Enabled << POWER_BILSENABLE_ENABLE_Pos);
1671 }
1672 #endif // NRF_POWER_HAS_BILS
1673
1674 #if NRF_POWER_HAS_PMIC
nrf_power_pmic_set(NRF_POWER_Type * p_reg,bool enable)1675 NRF_STATIC_INLINE void nrf_power_pmic_set(NRF_POWER_Type * p_reg, bool enable)
1676 {
1677 p_reg->PMICENABLE = (enable ? POWER_PMICENABLE_ENABLE_Enabled :
1678 POWER_PMICENABLE_ENABLE_Disabled) <<
1679 POWER_PMICENABLE_ENABLE_Pos;
1680 }
1681
nrf_power_pmic_check(NRF_POWER_Type const * p_reg)1682 NRF_STATIC_INLINE bool nrf_power_pmic_check(NRF_POWER_Type const * p_reg)
1683 {
1684 return (p_reg->PMICENABLE & POWER_PMICENABLE_ENABLE_Msk) ==
1685 (POWER_PMICENABLE_ENABLE_Enabled << POWER_PMICENABLE_ENABLE_Pos);
1686 }
1687 #endif // NRF_POWER_HAS_PMIC
1688
1689 #endif // NRF_DECLARE_ONLY
1690
1691 /** @} */
1692
1693 #ifdef __cplusplus
1694 }
1695 #endif
1696
1697 #endif // NRF_POWER_H__
1698
