1 /*
2  * Copyright (c) 2019 - 2024, Nordic Semiconductor ASA
3  * All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions are met:
9  *
10  * 1. Redistributions of source code must retain the above copyright notice, this
11  *    list of conditions and the following disclaimer.
12  *
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  *
17  * 3. Neither the name of the copyright holder nor the names of its
18  *    contributors may be used to endorse or promote products derived from this
19  *    software without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31  * POSSIBILITY OF SUCH DAMAGE.
32  */
33 
34 #ifndef NRF_MPU_H__
35 #define NRF_MPU_H__
36 
37 #include <nrfx.h>
38 
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42 
43 /**
44  * @defgroup nrf_mpu_hal MPU HAL
45  * @{
46  * @ingroup nrf_mpu
47  * @brief   Hardware access layer for managing the Memory Protection Unit (MPU) peripheral.
48  */
49 
50 /**
51  * @brief Macro for getting MPU region configuration mask for the specified peripheral.
52  *
53  * @param[in] base_addr Peripheral base address.
54  *
55  * @return MPU configuration mask for the specified peripheral.
56  */
57 #define NRF_MPU_PERIPHERAL_MASK_GET(base_addr) (1UL << NRFX_PERIPHERAL_ID_GET(base_addr))
58 
59 /**
60  * @brief Function for setting the size of the RAM region 0.
61  *
62  * When memory protection is enabled, the Memory Protection Unit enforces
63  * runtime protection and readback protection of resources classified as region 0.
64  * See the product specification for more information.
65  *
66  * @param[in] p_reg Pointer to the structure of registers of the peripheral.
67  * @param[in] size  Size of the RAM region 0, in bytes. Must be word-aligned.
68  */
69 NRF_STATIC_INLINE void nrf_mpu_region0_ram_size_set(NRF_MPU_Type * p_reg, uint32_t size);
70 
71 /**
72  * @brief Function for configuring specified peripherals in the memory region 0.
73  *
74  * When the memory protection is enabled, the Memory Protection Unit enforces
75  * runtime protection and readback protection of resources classified as region 0.
76  * See the product specification for more information.
77  *
78  * After reset, all peripherals are configured as *not* assigned to region 0.
79  *
80  * @param[in] p_reg           Pointer to the structure of registers of the peripheral.
81  * @param[in] peripheral_mask Mask that specifies peripherals to be configured in the memory region 0.
82  *                            Compose this mask using @ref NRF_MPU_PERIPHERAL_MASK_GET macro.
83  */
84 NRF_STATIC_INLINE void nrf_mpu_region0_peripherals_set(NRF_MPU_Type * p_reg,
85                                                        uint32_t       peripheral_mask);
86 
87 /**
88  * @brief Function for getting the bitmask that specifies peripherals configured in the memory region 0.
89  *
90  * @param[in] p_reg Pointer to the structure of registers of the peripheral.
91  *
92  * @return Bitmask representing peripherals configured in region 0.
93  */
94 NRF_STATIC_INLINE uint32_t nrf_mpu_region0_peripherals_get(NRF_MPU_Type const * p_reg);
95 
96 /**
97  * @brief Function for enabling protection for specified non-volatile memory blocks.
98  *
99  * Blocks are arranged into groups of 32 blocks each. Each block size is 4 kB.
100  * Any attempt to write or erase a protected block will result in hard fault.
101  * The memory block protection can be disabled only by resetting the device.
102  *
103  * @param[in] p_reg      Pointer to the structure of registers of the peripheral.
104  * @param[in] group_idx  Non-volatile memory group containing memory blocks to protect.
105  * @param[in] block_mask Non-volatile memory blocks to protect. Each bit in bitmask represents
106  *                       one memory block in the specified group.
107  */
108 NRF_STATIC_INLINE void nrf_mpu_nvm_blocks_protection_enable(NRF_MPU_Type * p_reg,
109                                                             uint8_t        group_idx,
110                                                             uint32_t       block_mask);
111 
112 /**
113  * @brief Function for setting the non-volatile memory (NVM) protection during debug.
114  *
115  * NVM protection during debug is disabled by default.
116  *
117  * @param[in] p_reg  Pointer to the structure of registers of the peripheral.
118  * @param[in] enable True if NVM protection during debug is to be enabled, false otherwise.
119  */
120 NRF_STATIC_INLINE void nrf_mpu_nvm_protection_in_debug_set(NRF_MPU_Type * p_reg,
121                                                            bool           enable);
122 
123 #ifndef NRF_DECLARE_ONLY
124 
nrf_mpu_region0_ram_size_set(NRF_MPU_Type * p_reg,uint32_t size)125 NRF_STATIC_INLINE void nrf_mpu_region0_ram_size_set(NRF_MPU_Type * p_reg, uint32_t size)
126 {
127     NRFX_ASSERT(nrfx_is_word_aligned((const void *)size));
128     p_reg->RLENR0 = size;
129 }
130 
nrf_mpu_region0_peripherals_set(NRF_MPU_Type * p_reg,uint32_t peripheral_mask)131 NRF_STATIC_INLINE void nrf_mpu_region0_peripherals_set(NRF_MPU_Type * p_reg,
132                                                        uint32_t       peripheral_mask)
133 {
134     p_reg->PERR0 = peripheral_mask;
135 }
136 
nrf_mpu_region0_peripherals_get(NRF_MPU_Type const * p_reg)137 NRF_STATIC_INLINE uint32_t nrf_mpu_region0_peripherals_get(NRF_MPU_Type const * p_reg)
138 {
139     return p_reg->PERR0;
140 }
141 
nrf_mpu_nvm_blocks_protection_enable(NRF_MPU_Type * p_reg,uint8_t group_idx,uint32_t block_mask)142 NRF_STATIC_INLINE void nrf_mpu_nvm_blocks_protection_enable(NRF_MPU_Type * p_reg,
143                                                             uint8_t        group_idx,
144                                                             uint32_t       block_mask)
145 {
146     switch (group_idx)
147     {
148         case 0:
149             p_reg->PROTENSET0 = block_mask;
150             break;
151 
152         case 1:
153             p_reg->PROTENSET1 = block_mask;
154             break;
155 
156         default:
157             NRFX_ASSERT(false);
158             break;
159     }
160 }
161 
nrf_mpu_nvm_protection_in_debug_set(NRF_MPU_Type * p_reg,bool enable)162 NRF_STATIC_INLINE void nrf_mpu_nvm_protection_in_debug_set(NRF_MPU_Type * p_reg,
163                                                            bool           enable)
164 {
165     p_reg->DISABLEINDEBUG =
166         (enable ? 0 : MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk);
167 }
168 
169 #endif // NRF_DECLARE_ONLY
170 
171 /** @} */
172 
173 #ifdef __cplusplus
174 }
175 #endif
176 
177 #endif // NRF_MPU_H__
178