1 /*
2 * Copyright (c) 2023 - 2024, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_MPC_H_
35 #define NRF_MPC_H_
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /**
44 * @defgroup nrf_mpc_hal MPC HAL
45 * @{
46 * @ingroup nrf_mpc
47 * @brief Hardware access layer for managing the Memory Privilege Controller (MPC)
48 * peripheral.
49 */
50
51 #if defined(MPC_RTCHOKE_WRITEACCESS_ENABLE0_Msk) || defined(__NRFX_DOXYGEN__)
52 /** @brief Symbol indicating whether RTCHOKE functionality is present. */
53 #define NRF_MPC_HAS_RTCHOKE 1
54 #else
55 #define NRF_MPC_HAS_RTCHOKE 0
56 #endif
57
58 #if defined(MPC_OVERRIDE_CONFIG_SECDOMENABLE_Msk) || defined(__NRFX_DOXYGEN__)
59 /** @brief Symbol indicating whether SECDOM functionality is present. */
60 #define NRF_MPC_HAS_SECDOM 1
61 #else
62 #define NRF_MPC_HAS_SECDOM 0
63 #endif
64
65 #if defined(MPC_OVERRIDE_OFFSET_OFFSET_Msk) || defined(__NRFX_DOXYGEN__)
66 /** @brief Symbol indicating whether OVERRIDE OFFSET functionality is present. */
67 #define NRF_MPC_HAS_OVERRIDE_OFFSET 1
68 #else
69 #define NRF_MPC_HAS_OVERRIDE_OFFSET 0
70 #endif
71
72 /** @brief Number of regions. */
73 #define NRF_MPC_REGION_COUNT MPC_REGION_MaxCount
74
75 /** @brief Number of override regions. */
76 #define NRF_MPC_OVERRIDE_COUNT MPC_OVERRIDE_MaxCount
77
78 /** @brief Number of master ports. */
79 #define NRF_MPC_MASTER_PORTS_COUNT MPC_MASTER_PORTS_MaxCount
80
81 #if NRF_MPC_HAS_RTCHOKE
82 /** @brief Number of Real Time Choke slaves. */
83 #define NRF_MPC_RTCHOKE_COUNT MPC_RTCHOKE_DELAY_MaxCount
84 #endif
85
86 /** @brief MPC events. */
87 typedef enum
88 {
89 NRF_MPC_EVENT_MEMACCERR = offsetof(NRF_MPC_Type, EVENTS_MEMACCERR), /**< Memory access error. */
90 } nrf_mpc_event_t;
91
92 /** @brief MPC interrupts. */
93 typedef enum
94 {
95 NRF_MPC_INT_MEMACCERR_MASK = MPC_INTENSET_MEMACCERR_Msk, /**< Interrupt on MEMACCERR event. */
96 } nrf_mpc_int_mask_t;
97
98 /** @brief Error sources. */
99 typedef enum
100 {
101 NRF_MPC_ERRORSOURCE_SLAVE = MPC_MEMACCERR_INFO_ERRORSOURCE_Slave, /**< Error was triggered by an AXI slave. */
102 NRF_MPC_ERRORSOURCE_MPC = MPC_MEMACCERR_INFO_ERRORSOURCE_MPC, /**< Error was triggered by MCP module. */
103 } nrf_mpc_errorsource_t;
104
105 /**
106 * @brief Permissions mask.
107 *
108 * @note This enum may be used for both permission settings and permission settings mask.
109 */
110 typedef enum
111 {
112 NRF_MPC_PERM_READ_MASK = MPC_OVERRIDE_PERM_READ_Msk, /**< Read access. */
113 NRF_MPC_PERM_WRITE_MASK = MPC_OVERRIDE_PERM_WRITE_Msk, /**< Write access. */
114 NRF_MPC_PERM_EXECUTE_MASK = MPC_OVERRIDE_PERM_EXECUTE_Msk, /**< Software execute. */
115 NRF_MPC_PERM_SECURE_MASK = MPC_OVERRIDE_PERM_SECATTR_Msk, /**< Security mapping. */
116 } nrf_mpc_permission_mask_t;
117
118 /** @brief Masterport mask. */
119 typedef enum
120 {
121 NRF_MPC_MASTERPORT_0_MASK = MPC_REGION_MASTERPORT_ENABLE0_Msk, /**< Enable master port 0. */
122 NRF_MPC_MASTERPORT_1_MASK = MPC_REGION_MASTERPORT_ENABLE1_Msk, /**< Enable master port 1. */
123 NRF_MPC_MASTERPORT_2_MASK = MPC_REGION_MASTERPORT_ENABLE2_Msk, /**< Enable master port 2. */
124 NRF_MPC_MASTERPORT_3_MASK = MPC_REGION_MASTERPORT_ENABLE3_Msk, /**< Enable master port 3. */
125 NRF_MPC_MASTERPORT_4_MASK = MPC_REGION_MASTERPORT_ENABLE4_Msk, /**< Enable master port 4. */
126 NRF_MPC_MASTERPORT_5_MASK = MPC_REGION_MASTERPORT_ENABLE5_Msk, /**< Enable master port 5. */
127 NRF_MPC_MASTERPORT_6_MASK = MPC_REGION_MASTERPORT_ENABLE6_Msk, /**< Enable master port 6. */
128 NRF_MPC_MASTERPORT_7_MASK = MPC_REGION_MASTERPORT_ENABLE7_Msk, /**< Enable master port 7. */
129 NRF_MPC_MASTERPORT_8_MASK = MPC_REGION_MASTERPORT_ENABLE8_Msk, /**< Enable master port 8. */
130 NRF_MPC_MASTERPORT_9_MASK = MPC_REGION_MASTERPORT_ENABLE9_Msk, /**< Enable master port 9. */
131 NRF_MPC_MASTERPORT_10_MASK = MPC_REGION_MASTERPORT_ENABLE10_Msk, /**< Enable master port 10. */
132 NRF_MPC_MASTERPORT_11_MASK = MPC_REGION_MASTERPORT_ENABLE11_Msk, /**< Enable master port 11. */
133 NRF_MPC_MASTERPORT_12_MASK = MPC_REGION_MASTERPORT_ENABLE12_Msk, /**< Enable master port 12. */
134 NRF_MPC_MASTERPORT_13_MASK = MPC_REGION_MASTERPORT_ENABLE13_Msk, /**< Enable master port 13. */
135 NRF_MPC_MASTERPORT_14_MASK = MPC_REGION_MASTERPORT_ENABLE14_Msk, /**< Enable master port 14. */
136 #if (NRF_MPC_MASTER_PORTS_COUNT > 15)
137 NRF_MPC_MASTERPORT_15_MASK = MPC_REGION_MASTERPORT_ENABLE15_Msk, /**< Enable master port 15. */
138 NRF_MPC_MASTERPORT_16_MASK = MPC_REGION_MASTERPORT_ENABLE16_Msk, /**< Enable master port 16. */
139 NRF_MPC_MASTERPORT_17_MASK = MPC_REGION_MASTERPORT_ENABLE17_Msk, /**< Enable master port 17. */
140 NRF_MPC_MASTERPORT_18_MASK = MPC_REGION_MASTERPORT_ENABLE18_Msk, /**< Enable master port 18. */
141 NRF_MPC_MASTERPORT_19_MASK = MPC_REGION_MASTERPORT_ENABLE19_Msk, /**< Enable master port 19. */
142 NRF_MPC_MASTERPORT_20_MASK = MPC_REGION_MASTERPORT_ENABLE20_Msk, /**< Enable master port 20. */
143 NRF_MPC_MASTERPORT_21_MASK = MPC_REGION_MASTERPORT_ENABLE21_Msk, /**< Enable master port 21. */
144 NRF_MPC_MASTERPORT_22_MASK = MPC_REGION_MASTERPORT_ENABLE22_Msk, /**< Enable master port 22. */
145 NRF_MPC_MASTERPORT_23_MASK = MPC_REGION_MASTERPORT_ENABLE23_Msk, /**< Enable master port 23. */
146 NRF_MPC_MASTERPORT_24_MASK = MPC_REGION_MASTERPORT_ENABLE24_Msk, /**< Enable master port 24. */
147 NRF_MPC_MASTERPORT_25_MASK = MPC_REGION_MASTERPORT_ENABLE25_Msk, /**< Enable master port 25. */
148 NRF_MPC_MASTERPORT_26_MASK = MPC_REGION_MASTERPORT_ENABLE26_Msk, /**< Enable master port 26. */
149 NRF_MPC_MASTERPORT_27_MASK = MPC_REGION_MASTERPORT_ENABLE27_Msk, /**< Enable master port 27. */
150 NRF_MPC_MASTERPORT_28_MASK = MPC_REGION_MASTERPORT_ENABLE28_Msk, /**< Enable master port 28. */
151 NRF_MPC_MASTERPORT_29_MASK = MPC_REGION_MASTERPORT_ENABLE29_Msk, /**< Enable master port 29. */
152 NRF_MPC_MASTERPORT_30_MASK = MPC_REGION_MASTERPORT_ENABLE30_Msk, /**< Enable master port 30. */
153 NRF_MPC_MASTERPORT_31_MASK = MPC_REGION_MASTERPORT_ENABLE31_Msk, /**< Enable master port 31. */
154 #endif
155 } nrf_mpc_masterport_mask_t;
156
157 /** @brief Region configuration. */
158 typedef struct
159 {
160 uint8_t slave_number; /**< Target slave number. */
161 bool lock; /**< Lock region until next reset. */
162 bool enable; /**< Enable region. */
163 nrf_owner_t owner; /**< Owner identifier. */
164 uint32_t permissions; /**< Permissions. */
165 } nrf_mpc_region_config_t;
166
167 /** @brief Override region configuration. */
168 typedef struct
169 {
170 uint8_t slave_number; /**< Target slave number. */
171 bool lock; /**< Lock region until next reset. */
172 bool enable; /**< Enable region. */
173 bool secdom_enable; /**< Enable overriding of secure domain permissions. */
174 bool secure_mask; /**< Secure mask. Read only.
175 * If set, the bit 28 of the transaction is ignored while address matching. */
176 } nrf_mpc_override_config_t;
177
178 /**
179 * @brief Function for retrieving the state of the specified MPC event.
180 *
181 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
182 * @param[in] event Event to be checked.
183 *
184 * @retval true The event has been generated.
185 * @retval false The event has not been generated.
186 */
187 NRF_STATIC_INLINE bool nrf_mpc_event_check(NRF_MPC_Type const * p_reg, nrf_mpc_event_t event);
188
189 /**
190 * @brief Function for clearing the specified MPC event.
191 *
192 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
193 * @param[in] event Event to be cleared.
194 */
195 NRF_STATIC_INLINE void nrf_mpc_event_clear(NRF_MPC_Type * p_reg, nrf_mpc_event_t event);
196
197 /**
198 * @brief Function for getting the address of the specified MPC event register.
199 *
200 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
201 * @param[in] event Event to get the address of.
202 *
203 * @return Address of the specified event register.
204 */
205 NRF_STATIC_INLINE uint32_t nrf_mpc_event_address_get(NRF_MPC_Type const * p_reg,
206 nrf_mpc_event_t event);
207
208 /**
209 * @brief Function for enabling the specified interrupts.
210 *
211 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
212 * @param[in] mask Mask of interrupts to be enabled.
213 * Use @ref nrf_mpc_int_mask_t values for bit masking.
214 */
215 NRF_STATIC_INLINE void nrf_mpc_int_enable(NRF_MPC_Type * p_reg, uint32_t mask);
216
217 /**
218 * @brief Function for checking if the specified interrupts are enabled.
219 *
220 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
221 * @param[in] mask Mask of interrupts to be checked.
222 * Use @ref nrf_mpc_int_mask_t values for bit masking.
223 *
224 * @return Mask of enabled interrupts.
225 */
226 NRF_STATIC_INLINE uint32_t nrf_mpc_int_enable_check(NRF_MPC_Type const * p_reg, uint32_t mask);
227
228 /**
229 * @brief Function for disabling the specified interrupts.
230 *
231 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
232 * @param[in] mask Mask of interrupts to be disabled.
233 * Use @ref nrf_mpc_int_mask_t values for bit masking.
234 */
235 NRF_STATIC_INLINE void nrf_mpc_int_disable(NRF_MPC_Type * p_reg, uint32_t mask);
236
237 /**
238 * @brief Function for setting configuration of the region.
239 *
240 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
241 * @param[in] index Region index.
242 * @param[in] p_config Pointer to the structure of the region configuration parameters.
243 */
244 NRF_STATIC_INLINE void nrf_mpc_region_config_set(NRF_MPC_Type * p_reg,
245 uint8_t index,
246 nrf_mpc_region_config_t const * p_config);
247
248 /**
249 * @brief Function for getting configuration of the region.
250 *
251 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
252 * @param[in] index Region index.
253 *
254 * @return Structure with configuration of the region.
255 */
256 NRF_STATIC_INLINE nrf_mpc_region_config_t nrf_mpc_region_config_get(NRF_MPC_Type const * p_reg,
257 uint8_t index);
258
259 /**
260 * @brief Function for setting start address of the region.
261 *
262 * @note Address must be on a 4kB memory boundary.
263 *
264 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
265 * @param[in] index Region index.
266 * @param[in] address Address to be set.
267 */
268 NRF_STATIC_INLINE void nrf_mpc_region_startaddr_set(NRF_MPC_Type * p_reg,
269 uint8_t index,
270 uint32_t address);
271
272 /**
273 * @brief Function for getting start address of the region.
274 *
275 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
276 * @param[in] index Region index.
277 *
278 * @return Start address of the region.
279 */
280 NRF_STATIC_INLINE uint32_t nrf_mpc_region_startaddr_get(NRF_MPC_Type const * p_reg, uint8_t index);
281
282 /**
283 * @brief Function for setting address mask of the region.
284 *
285 * @note Mask must be on a 4kB memory boundary.
286 *
287 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
288 * @param[in] index Region index.
289 * @param[in] address Address to be set.
290 */
291 NRF_STATIC_INLINE void nrf_mpc_region_addrmask_set(NRF_MPC_Type * p_reg,
292 uint8_t index,
293 uint32_t address);
294
295 /**
296 * @brief Function for getting address mask of the region.
297 *
298 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
299 * @param[in] index Region index.
300 *
301 * @return Address mask of the region.
302 */
303 NRF_STATIC_INLINE uint32_t nrf_mpc_region_addrmask_get(NRF_MPC_Type const * p_reg, uint8_t index);
304
305 /**
306 * @brief Function for enabling the specified master ports of the region.
307 *
308 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
309 * @param[in] index Region index.
310 * @param[in] mask Mask of master ports to be enabled,
311 * constructed from @ref nrf_mpc_masterport_mask_t enumerator values.
312 */
313 NRF_STATIC_INLINE void nrf_mpc_region_masterport_set(NRF_MPC_Type * p_reg,
314 uint8_t index,
315 uint32_t mask);
316
317 /**
318 * @brief Function for getting enabled master ports of the region.
319 *
320 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
321 * @param[in] index Region index.
322 *
323 * @return Mask of enabled master ports,
324 * constructed from @ref nrf_mpc_masterport_mask_t enumerator values.
325 */
326 NRF_STATIC_INLINE uint32_t nrf_mpc_region_masterport_get(NRF_MPC_Type const * p_reg, uint8_t index);
327
328 /**
329 * @brief Function for setting configuration of the override region.
330 *
331 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
332 * @param[in] index Override region index.
333 * @param[in] p_config Pointer to the structure of the override region configuration parameters.
334 */
335 NRF_STATIC_INLINE void nrf_mpc_override_config_set(NRF_MPC_Type * p_reg,
336 uint8_t index,
337 nrf_mpc_override_config_t const * p_config);
338
339 /**
340 * @brief Function for getting configuration of the override region.
341 *
342 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
343 * @param[in] index Override region index.
344 *
345 * @return Structure with configuration of the override region.
346 */
347 NRF_STATIC_INLINE nrf_mpc_override_config_t nrf_mpc_override_config_get(NRF_MPC_Type const * p_reg,
348 uint8_t index);
349
350 /**
351 * @brief Function for setting start address of the override region.
352 *
353 * @note Address must be on a 4kB memory boundary.
354 *
355 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
356 * @param[in] index Override region index.
357 * @param[in] address Address to be set.
358 */
359 NRF_STATIC_INLINE void nrf_mpc_override_startaddr_set(NRF_MPC_Type * p_reg,
360 uint8_t index,
361 uint32_t address);
362
363 /**
364 * @brief Function for getting start address of the override region.
365 *
366 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
367 * @param[in] index Override region index.
368 *
369 * @return Start address of the override region.
370 */
371 NRF_STATIC_INLINE uint32_t nrf_mpc_override_startaddr_get(NRF_MPC_Type const * p_reg,
372 uint8_t index);
373
374 /**
375 * @brief Function for setting end address of the override region.
376 *
377 * @note Address must be on a 4kB memory boundary.
378 *
379 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
380 * @param[in] index Override region index.
381 * @param[in] address Address to be set.
382 */
383 NRF_STATIC_INLINE void nrf_mpc_override_endaddr_set(NRF_MPC_Type * p_reg,
384 uint8_t index,
385 uint32_t address);
386
387 /**
388 * @brief Function for getting end address of the override region.
389 *
390 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
391 * @param[in] index Override region index.
392 *
393 * @return End address of the override region.
394 */
395 NRF_STATIC_INLINE uint32_t nrf_mpc_override_endaddr_get(NRF_MPC_Type const * p_reg,
396 uint8_t index);
397
398 #if NRF_MPC_HAS_OVERRIDE_OFFSET
399 /**
400 * @brief Function for setting offset of the override region.
401 *
402 * @note Offset will be left shifted before applying, creating a 33-bit signed integer.
403 *
404 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
405 * @param[in] index Override region index.
406 * @param[in] offset Address offset value divided by 2.
407 */
408 NRF_STATIC_INLINE void nrf_mpc_override_offset_set(NRF_MPC_Type * p_reg,
409 uint8_t index,
410 uint32_t offset);
411
412 /**
413 * @brief Function for getting offset of the override region.
414 *
415 * @note Offset is left shifted before applying, creating a 33-bit signed integer.
416 *
417 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
418 * @param[in] index Override region index.
419 *
420 * @return Address offset value divided by 2.
421 */
422 NRF_STATIC_INLINE uint32_t nrf_mpc_override_offset_get(NRF_MPC_Type const * p_reg,
423 uint8_t index);
424 #endif
425
426 /**
427 * @brief Function for setting permission settings for the override region.
428 *
429 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
430 * @param[in] index Override region index.
431 * @param[in] permissions Mask of permissions to be set,
432 * constructed from @ref nrf_mpc_permission_mask_t enumerator values.
433 */
434 NRF_STATIC_INLINE void nrf_mpc_override_perm_set(NRF_MPC_Type * p_reg,
435 uint8_t index,
436 uint32_t permissions);
437
438 /**
439 * @brief Function for getting permission settings of the override region.
440 *
441 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
442 * @param[in] index Override region index.
443 *
444 * @return Mask of permissions, constructed from @ref nrf_mpc_permission_mask_t enumerator values.
445 */
446 NRF_STATIC_INLINE uint32_t nrf_mpc_override_perm_get(NRF_MPC_Type const * p_reg,
447 uint8_t index);
448
449 /**
450 * @brief Function for setting permission settings mask for the override region.
451 *
452 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
453 * @param[in] index Override region index.
454 * @param[in] permissions Mask of permissions settings mask to be set,
455 * constructed from @ref nrf_mpc_permission_mask_t enumerator values.
456 */
457 NRF_STATIC_INLINE void nrf_mpc_override_permmask_set(NRF_MPC_Type * p_reg,
458 uint8_t index,
459 uint32_t permissions);
460
461 /**
462 * @brief Function for getting permission settings mask of the override region.
463 *
464 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
465 * @param[in] index Override region index.
466 *
467 * @return Mask of permissions settings mask,
468 * constructed from @ref nrf_mpc_permission_mask_t enumerator values.
469 */
470 NRF_STATIC_INLINE uint32_t nrf_mpc_override_permmask_get(NRF_MPC_Type const * p_reg,
471 uint8_t index);
472
473 /**
474 * @brief Function for setting owner ID for the override region.
475 *
476 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
477 * @param[in] index Override region index.
478 * @param[in] owner_id Owner ID to be set.
479 */
480 NRF_STATIC_INLINE void nrf_mpc_override_ownerid_set(NRF_MPC_Type * p_reg,
481 uint8_t index,
482 nrf_owner_t owner_id);
483
484 /**
485 * @brief Function for getting owner ID of the override region.
486 *
487 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
488 * @param[in] index Override region index.
489 *
490 * @return Owner ID of the overridde region.
491 */
492 NRF_STATIC_INLINE nrf_owner_t nrf_mpc_override_ownerid_get(NRF_MPC_Type * p_reg, uint8_t index);
493
494 /**
495 * @brief Function for enabling the specified master ports of the override region.
496 *
497 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
498 * @param[in] index Override region index.
499 * @param[in] mask Mask of master ports to be enabled,
500 * constructed from @ref nrf_mpc_masterport_mask_t enumerator values.
501 */
502 NRF_STATIC_INLINE void nrf_mpc_override_masterport_set(NRF_MPC_Type * p_reg,
503 uint8_t index,
504 uint32_t mask);
505
506 /**
507 * @brief Function for getting enabled master ports of the override region.
508 *
509 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
510 * @param[in] index Override region index.
511 *
512 * @return Mask of enabled master ports,
513 * constructed from @ref nrf_mpc_masterport_mask_t enumerator values.
514 */
515 NRF_STATIC_INLINE uint32_t nrf_mpc_override_masterport_get(NRF_MPC_Type const * p_reg,
516 uint8_t index);
517
518 /**
519 * @brief Function for getting the memory address of memory access error.
520 *
521 * @note Register content will not be changed as long as MEMACCERR event is active.
522 *
523 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
524 *
525 * @return Target address for the errroneous access.
526 */
527 NRF_STATIC_INLINE uint32_t nrf_mpc_memaccerr_address_get(NRF_MPC_Type const * p_reg);
528
529 /**
530 * @brief Function for getting the owner identifier of the transaction that triggered memory access error.
531 *
532 * @note Register content will not be changed as long as MEMACCERR event is active.
533 *
534 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
535 *
536 * @return Owner identifier of the errorneous access.
537 */
538 NRF_STATIC_INLINE nrf_owner_t nrf_mpc_memaccerr_info_ownerid_get(NRF_MPC_Type const * p_reg);
539
540 /**
541 * @brief Function for getting the master port of the transaction that triggered memory access error.
542 *
543 * @note Register content will not be changed as long as MEMACCERR event is active.
544 *
545 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
546 *
547 * @return Master port where errorneous access is detected.
548 */
549 NRF_STATIC_INLINE uint8_t nrf_mpc_memaccerr_info_masterport_get(NRF_MPC_Type const * p_reg);
550
551 /**
552 * @brief Function for getting the permissions of the transaction that triggered memory access error.
553 *
554 * @note Register content will not be changed as long as MEMACCERR event is active.
555 *
556 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
557 *
558 * @return Permission settings of the errorneous access.
559 */
560 NRF_STATIC_INLINE uint32_t nrf_mpc_memaccerr_info_perm_get(NRF_MPC_Type const * p_reg);
561
562 /**
563 * @brief Function for getting the source of the transaction that triggered memory access error.
564 *
565 * @note Register content will not be changed as long as MEMACCERR event is active.
566 *
567 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
568 *
569 * @return Source of the errorneous access.
570 */
571 NRF_STATIC_INLINE nrf_mpc_errorsource_t
572 nrf_mpc_memaccerr_info_errorsource_get(NRF_MPC_Type const * p_reg);
573
574 /**
575 * @brief Function for enabling the specified master ports connection to global slave.
576 *
577 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
578 * @param[in] mask Mask of master ports to be connected,
579 * constructed from @ref nrf_mpc_masterport_mask_t enumerator values.
580 */
581 NRF_STATIC_INLINE void nrf_mpc_globalslave_masterport_set(NRF_MPC_Type * p_reg, uint32_t mask);
582
583 /**
584 * @brief Function for getting enabled master ports connection to global slave.
585 *
586 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
587 *
588 * @return Mask of master ports connected,
589 * constructed from @ref nrf_mpc_masterport_mask_t enumerator values.
590 */
591 NRF_STATIC_INLINE uint32_t nrf_mpc_globalslave_masterport_get(NRF_MPC_Type const * p_reg);
592
593 /**
594 * @brief Function for enabling the global slave registers lock.
595 *
596 * @note When global slave registers is enabled, modifying the global slave configuration
597 * is not possible.
598 *
599 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
600 */
601 NRF_STATIC_INLINE void nrf_mpc_globalslave_lock_enable(NRF_MPC_Type * p_reg);
602
603 /**
604 * @brief Function for getting the status of the global slave registers lock.
605 *
606 * @note When global slave registers is enabled, modifying the global slave configuration
607 * is not possible.
608 *
609 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
610 *
611 * @return True if global slave registers are locked, false otherwise.
612 */
613 NRF_STATIC_INLINE bool nrf_mpc_globalslave_lock_check(NRF_MPC_Type const * p_reg);
614
615 #if NRF_MPC_HAS_RTCHOKE
616 /**
617 * @brief Function for enabling the AXI Write Address Channel Real Time Choke for specified master ports.
618 *
619 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
620 * @param[in] mask Mask of master ports to have the Write Real Time Choke enabled,
621 * constructed from @ref nrf_mpc_masterport_mask_t enumerator values.
622 */
623 NRF_STATIC_INLINE void nrf_mpc_rtchoke_writeaccess_set(NRF_MPC_Type * p_reg, uint32_t mask);
624
625 /**
626 * @brief Function for getting master ports with enabled AXI Write Address Channel Real Time Choke.
627 *
628 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
629 *
630 * @return Mask of master ports with the Write Real Time Choke enabled,
631 * constructed from @ref nrf_mpc_masterport_mask_t enumerator values.
632 */
633 NRF_STATIC_INLINE uint32_t nrf_mpc_rtchoke_writeaccess_get(NRF_MPC_Type const * p_reg);
634
635 /**
636 * @brief Function for enabling the AXI Read Address Channel Real Time Choke for specified master ports.
637 *
638 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
639 * @param[in] mask Mask of master ports to have the Read Real Time Choke enabled,
640 * constructed from @ref nrf_mpc_masterport_mask_t enumerator values.
641 */
642 NRF_STATIC_INLINE void nrf_mpc_rtchoke_readaccess_set(NRF_MPC_Type * p_reg, uint32_t mask);
643
644 /**
645 * @brief Function for getting master ports with enabled AXI Read Address Channel Real Time Choke.
646 *
647 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
648 *
649 * @return Mask of master ports with the Read Real Time Choke enabled,
650 * constructed from @ref nrf_mpc_masterport_mask_t enumerator values.
651 */
652 NRF_STATIC_INLINE uint32_t nrf_mpc_rtchoke_readaccess_get(NRF_MPC_Type const * p_reg);
653
654 /**
655 * @brief Function for setting the Real Time Choke delay for the specified slave.
656 *
657 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
658 * @param[in] slave Slave number.
659 * @param[in] delay Delay value to be set.
660 */
661 NRF_STATIC_INLINE void nrf_mpc_rtchoke_delay_set(NRF_MPC_Type * p_reg,
662 uint8_t slave,
663 uint8_t delay);
664
665 /**
666 * @brief Function for getting the Real Time Choke delay for the specified slave.
667 *
668 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
669 * @param[in] slave Slave number.
670 *
671 * @return Delay value for slave.
672 */
673 NRF_STATIC_INLINE uint8_t nrf_mpc_rtchoke_delay_get(NRF_MPC_Type const * p_reg, uint8_t slave);
674
675 #endif // NRF_MPC_HAS_RTCHOKE
676
677 #ifndef NRF_DECLARE_ONLY
nrf_mpc_event_check(NRF_MPC_Type const * p_reg,nrf_mpc_event_t event)678 NRF_STATIC_INLINE bool nrf_mpc_event_check(NRF_MPC_Type const * p_reg, nrf_mpc_event_t event)
679 {
680 return nrf_event_check(p_reg, event);
681 }
682
nrf_mpc_event_clear(NRF_MPC_Type * p_reg,nrf_mpc_event_t event)683 NRF_STATIC_INLINE void nrf_mpc_event_clear(NRF_MPC_Type * p_reg, nrf_mpc_event_t event)
684 {
685 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
686 nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
687 }
688
nrf_mpc_event_address_get(NRF_MPC_Type const * p_reg,nrf_mpc_event_t event)689 NRF_STATIC_INLINE uint32_t nrf_mpc_event_address_get(NRF_MPC_Type const * p_reg,
690 nrf_mpc_event_t event)
691 {
692 return nrf_task_event_address_get(p_reg, event);
693 }
694
nrf_mpc_int_enable(NRF_MPC_Type * p_reg,uint32_t mask)695 NRF_STATIC_INLINE void nrf_mpc_int_enable(NRF_MPC_Type * p_reg, uint32_t mask)
696 {
697 p_reg->INTENSET = mask;
698 }
699
nrf_mpc_int_enable_check(NRF_MPC_Type const * p_reg,uint32_t mask)700 NRF_STATIC_INLINE uint32_t nrf_mpc_int_enable_check(NRF_MPC_Type const * p_reg, uint32_t mask)
701 {
702 return p_reg->INTENSET & mask;
703 }
704
nrf_mpc_int_disable(NRF_MPC_Type * p_reg,uint32_t mask)705 NRF_STATIC_INLINE void nrf_mpc_int_disable(NRF_MPC_Type * p_reg, uint32_t mask)
706 {
707 p_reg->INTENCLR = mask;
708 }
709
nrf_mpc_region_config_set(NRF_MPC_Type * p_reg,uint8_t index,nrf_mpc_region_config_t const * p_config)710 NRF_STATIC_INLINE void nrf_mpc_region_config_set(NRF_MPC_Type * p_reg,
711 uint8_t index,
712 nrf_mpc_region_config_t const * p_config)
713 {
714 NRFX_ASSERT(index < NRF_MPC_REGION_COUNT);
715 NRFX_ASSERT(p_config != NULL);
716
717 p_reg->REGION[index].CONFIG = (((p_config->slave_number <<
718 MPC_REGION_CONFIG_SLAVENUMBER_Pos) &
719 MPC_REGION_CONFIG_SLAVENUMBER_Msk) |
720 ((p_config->lock ? MPC_REGION_CONFIG_LOCK_Locked :
721 MPC_REGION_CONFIG_LOCK_Unlocked) <<
722 MPC_REGION_CONFIG_LOCK_Pos) |
723 ((p_config->enable ? MPC_REGION_CONFIG_ENABLE_Enabled :
724 MPC_REGION_CONFIG_ENABLE_Disabled) <<
725 MPC_REGION_CONFIG_ENABLE_Pos) |
726 ((p_config->permissions << MPC_REGION_CONFIG_READ_Pos) &
727 (MPC_REGION_CONFIG_READ_Msk | MPC_REGION_CONFIG_WRITE_Msk |
728 MPC_REGION_CONFIG_EXECUTE_Msk |
729 MPC_REGION_CONFIG_SECATTR_Msk)) |
730 ((p_config->owner <<
731 MPC_REGION_CONFIG_OWNERID_Pos) &
732 MPC_REGION_CONFIG_OWNERID_Msk));
733 }
734
nrf_mpc_region_config_get(NRF_MPC_Type const * p_reg,uint8_t index)735 NRF_STATIC_INLINE nrf_mpc_region_config_t nrf_mpc_region_config_get(NRF_MPC_Type const * p_reg,
736 uint8_t index)
737 {
738 NRFX_ASSERT(index < NRF_MPC_REGION_COUNT);
739
740 nrf_mpc_region_config_t ret;
741
742 ret.slave_number = (p_reg->REGION[index].CONFIG & MPC_REGION_CONFIG_SLAVENUMBER_Msk)
743 >> MPC_REGION_CONFIG_SLAVENUMBER_Pos;
744
745 ret.lock = ((p_reg->REGION[index].CONFIG & MPC_REGION_CONFIG_LOCK_Msk)
746 >> MPC_REGION_CONFIG_LOCK_Pos) == MPC_REGION_CONFIG_LOCK_Locked;
747
748 ret.enable = ((p_reg->REGION[index].CONFIG & MPC_REGION_CONFIG_ENABLE_Msk)
749 >> MPC_REGION_CONFIG_ENABLE_Pos) == MPC_REGION_CONFIG_ENABLE_Enabled;
750
751 ret.permissions = (p_reg->REGION[index].CONFIG &
752 (MPC_REGION_CONFIG_READ_Msk | MPC_REGION_CONFIG_WRITE_Msk |
753 MPC_REGION_CONFIG_EXECUTE_Msk | MPC_REGION_CONFIG_SECATTR_Msk))
754 >> MPC_REGION_CONFIG_READ_Pos;
755
756 ret.owner = (nrf_owner_t)((p_reg->REGION[index].CONFIG & MPC_REGION_CONFIG_OWNERID_Msk)
757 >> MPC_REGION_CONFIG_OWNERID_Pos);
758
759 return ret;
760 }
761
nrf_mpc_region_startaddr_set(NRF_MPC_Type * p_reg,uint8_t index,uint32_t address)762 NRF_STATIC_INLINE void nrf_mpc_region_startaddr_set(NRF_MPC_Type * p_reg,
763 uint8_t index,
764 uint32_t address)
765 {
766 NRFX_ASSERT(index < NRF_MPC_REGION_COUNT);
767 NRFX_ASSERT((address & 0xFFFUL) == 0);
768
769 p_reg->REGION[index].STARTADDR = address;
770 }
771
nrf_mpc_region_startaddr_get(NRF_MPC_Type const * p_reg,uint8_t index)772 NRF_STATIC_INLINE uint32_t nrf_mpc_region_startaddr_get(NRF_MPC_Type const * p_reg, uint8_t index)
773 {
774 NRFX_ASSERT(index < NRF_MPC_REGION_COUNT);
775
776 return p_reg->REGION[index].STARTADDR;
777 }
778
nrf_mpc_region_addrmask_set(NRF_MPC_Type * p_reg,uint8_t index,uint32_t address)779 NRF_STATIC_INLINE void nrf_mpc_region_addrmask_set(NRF_MPC_Type * p_reg,
780 uint8_t index,
781 uint32_t address)
782 {
783 NRFX_ASSERT(index < NRF_MPC_REGION_COUNT);
784 NRFX_ASSERT((address & 0xFFFUL) == 0);
785
786 p_reg->REGION[index].ADDRMASK = address;
787 }
788
nrf_mpc_region_addrmask_get(NRF_MPC_Type const * p_reg,uint8_t index)789 NRF_STATIC_INLINE uint32_t nrf_mpc_region_addrmask_get(NRF_MPC_Type const * p_reg, uint8_t index)
790 {
791 NRFX_ASSERT(index < NRF_MPC_REGION_COUNT);
792
793 return p_reg->REGION[index].ADDRMASK;
794 }
795
nrf_mpc_region_masterport_set(NRF_MPC_Type * p_reg,uint8_t index,uint32_t mask)796 NRF_STATIC_INLINE void nrf_mpc_region_masterport_set(NRF_MPC_Type * p_reg,
797 uint8_t index,
798 uint32_t mask)
799 {
800 NRFX_ASSERT(index < NRF_MPC_REGION_COUNT);
801
802 p_reg->REGION[index].MASTERPORT = mask;
803 }
804
nrf_mpc_region_masterport_get(NRF_MPC_Type const * p_reg,uint8_t index)805 NRF_STATIC_INLINE uint32_t nrf_mpc_region_masterport_get(NRF_MPC_Type const * p_reg, uint8_t index)
806 {
807 NRFX_ASSERT(index < NRF_MPC_REGION_COUNT);
808
809 return p_reg->REGION[index].MASTERPORT;
810 }
811
nrf_mpc_override_config_set(NRF_MPC_Type * p_reg,uint8_t index,nrf_mpc_override_config_t const * p_config)812 NRF_STATIC_INLINE void nrf_mpc_override_config_set(NRF_MPC_Type * p_reg,
813 uint8_t index,
814 nrf_mpc_override_config_t const * p_config)
815 {
816 NRFX_ASSERT(index < NRF_MPC_OVERRIDE_COUNT);
817 NRFX_ASSERT(p_config != NULL);
818
819 p_reg->OVERRIDE[index].CONFIG = (((p_config->slave_number <<
820 MPC_OVERRIDE_CONFIG_SLAVENUMBER_Pos) &
821 MPC_OVERRIDE_CONFIG_SLAVENUMBER_Msk) |
822 ((p_config->lock ? MPC_OVERRIDE_CONFIG_LOCK_Locked :
823 MPC_OVERRIDE_CONFIG_LOCK_Unlocked) <<
824 MPC_OVERRIDE_CONFIG_LOCK_Pos) |
825 ((p_config->enable ? MPC_OVERRIDE_CONFIG_ENABLE_Enabled :
826 MPC_OVERRIDE_CONFIG_ENABLE_Disabled) <<
827 MPC_OVERRIDE_CONFIG_ENABLE_Pos) |
828 #if NRF_MPC_HAS_SECDOM
829 ((p_config->secdom_enable ?
830 MPC_OVERRIDE_CONFIG_SECDOMENABLE_Enabled :
831 MPC_OVERRIDE_CONFIG_SECDOMENABLE_Disabled) <<
832 MPC_OVERRIDE_CONFIG_SECDOMENABLE_Pos) |
833 #endif
834 0);
835 }
836
nrf_mpc_override_config_get(NRF_MPC_Type const * p_reg,uint8_t index)837 NRF_STATIC_INLINE nrf_mpc_override_config_t nrf_mpc_override_config_get(NRF_MPC_Type const * p_reg,
838 uint8_t index)
839 {
840 NRFX_ASSERT(index < NRF_MPC_OVERRIDE_COUNT);
841
842 nrf_mpc_override_config_t ret;
843
844 ret.slave_number = (p_reg->OVERRIDE[index].CONFIG & MPC_OVERRIDE_CONFIG_SLAVENUMBER_Msk)
845 >> MPC_OVERRIDE_CONFIG_SLAVENUMBER_Pos;
846
847 ret.lock = ((p_reg->OVERRIDE[index].CONFIG & MPC_OVERRIDE_CONFIG_LOCK_Msk)
848 >> MPC_OVERRIDE_CONFIG_LOCK_Pos) == MPC_OVERRIDE_CONFIG_LOCK_Locked;
849
850 ret.enable = ((p_reg->OVERRIDE[index].CONFIG & MPC_OVERRIDE_CONFIG_ENABLE_Msk)
851 >> MPC_OVERRIDE_CONFIG_ENABLE_Pos) == MPC_OVERRIDE_CONFIG_ENABLE_Enabled;
852 #if NRF_MPC_HAS_SECDOM
853 ret.secdom_enable = ((p_reg->OVERRIDE[index].CONFIG & MPC_OVERRIDE_CONFIG_SECDOMENABLE_Msk)
854 >> MPC_OVERRIDE_CONFIG_SECDOMENABLE_Pos)
855 == MPC_OVERRIDE_CONFIG_SECDOMENABLE_Enabled;
856 #endif
857 ret.secure_mask = ((p_reg->OVERRIDE[index].CONFIG & MPC_OVERRIDE_CONFIG_SECUREMASK_Msk)
858 >> MPC_OVERRIDE_CONFIG_SECUREMASK_Pos) ==
859 MPC_OVERRIDE_CONFIG_SECUREMASK_Enabled;
860
861 return ret;
862 }
863
nrf_mpc_override_startaddr_set(NRF_MPC_Type * p_reg,uint8_t index,uint32_t address)864 NRF_STATIC_INLINE void nrf_mpc_override_startaddr_set(NRF_MPC_Type * p_reg,
865 uint8_t index,
866 uint32_t address)
867 {
868 NRFX_ASSERT(index < NRF_MPC_OVERRIDE_COUNT);
869 NRFX_ASSERT((address & 0xFFFUL) == 0);
870
871 p_reg->OVERRIDE[index].STARTADDR = address;
872 }
873
nrf_mpc_override_startaddr_get(NRF_MPC_Type const * p_reg,uint8_t index)874 NRF_STATIC_INLINE uint32_t nrf_mpc_override_startaddr_get(NRF_MPC_Type const * p_reg,
875 uint8_t index)
876 {
877 NRFX_ASSERT(index < NRF_MPC_OVERRIDE_COUNT);
878
879 return p_reg->OVERRIDE[index].STARTADDR;
880 }
881
nrf_mpc_override_endaddr_set(NRF_MPC_Type * p_reg,uint8_t index,uint32_t address)882 NRF_STATIC_INLINE void nrf_mpc_override_endaddr_set(NRF_MPC_Type * p_reg,
883 uint8_t index,
884 uint32_t address)
885 {
886 NRFX_ASSERT(index < NRF_MPC_OVERRIDE_COUNT);
887 NRFX_ASSERT((address & 0xFFFUL) == 0);
888
889 p_reg->OVERRIDE[index].ENDADDR = address;
890 }
891
nrf_mpc_override_endaddr_get(NRF_MPC_Type const * p_reg,uint8_t index)892 NRF_STATIC_INLINE uint32_t nrf_mpc_override_endaddr_get(NRF_MPC_Type const * p_reg,
893 uint8_t index)
894 {
895 NRFX_ASSERT(index < NRF_MPC_OVERRIDE_COUNT);
896
897 return p_reg->OVERRIDE[index].ENDADDR;
898 }
899
900 #if NRF_MPC_HAS_OVERRIDE_OFFSET
nrf_mpc_override_offset_set(NRF_MPC_Type * p_reg,uint8_t index,uint32_t offset)901 NRF_STATIC_INLINE void nrf_mpc_override_offset_set(NRF_MPC_Type * p_reg,
902 uint8_t index,
903 uint32_t offset)
904 {
905 NRFX_ASSERT(index < NRF_MPC_OVERRIDE_COUNT);
906 NRFX_ASSERT((offset & 0x3FFUL) == 0);
907
908 p_reg->OVERRIDE[index].OFFSET = (int32_t)offset;
909 }
910
nrf_mpc_override_offset_get(NRF_MPC_Type const * p_reg,uint8_t index)911 NRF_STATIC_INLINE uint32_t nrf_mpc_override_offset_get(NRF_MPC_Type const * p_reg,
912 uint8_t index)
913 {
914 NRFX_ASSERT(index < NRF_MPC_OVERRIDE_COUNT);
915
916 return (uint32_t)p_reg->OVERRIDE[index].OFFSET;
917 }
918 #endif
919
nrf_mpc_override_perm_set(NRF_MPC_Type * p_reg,uint8_t index,uint32_t permissions)920 NRF_STATIC_INLINE void nrf_mpc_override_perm_set(NRF_MPC_Type * p_reg,
921 uint8_t index,
922 uint32_t permissions)
923 {
924 NRFX_ASSERT(index < NRF_MPC_OVERRIDE_COUNT);
925
926 p_reg->OVERRIDE[index].PERM = permissions;
927 }
928
nrf_mpc_override_perm_get(NRF_MPC_Type const * p_reg,uint8_t index)929 NRF_STATIC_INLINE uint32_t nrf_mpc_override_perm_get(NRF_MPC_Type const * p_reg,
930 uint8_t index)
931 {
932 NRFX_ASSERT(index < NRF_MPC_OVERRIDE_COUNT);
933
934 return p_reg->OVERRIDE[index].PERM;
935 }
936
nrf_mpc_override_permmask_set(NRF_MPC_Type * p_reg,uint8_t index,uint32_t permissions)937 NRF_STATIC_INLINE void nrf_mpc_override_permmask_set(NRF_MPC_Type * p_reg,
938 uint8_t index,
939 uint32_t permissions)
940 {
941 NRFX_ASSERT(index < NRF_MPC_OVERRIDE_COUNT);
942
943 p_reg->OVERRIDE[index].PERMMASK = permissions;
944 }
945
nrf_mpc_override_permmask_get(NRF_MPC_Type const * p_reg,uint8_t index)946 NRF_STATIC_INLINE uint32_t nrf_mpc_override_permmask_get(NRF_MPC_Type const * p_reg,
947 uint8_t index)
948 {
949 NRFX_ASSERT(index < NRF_MPC_OVERRIDE_COUNT);
950
951 return p_reg->OVERRIDE[index].PERMMASK;
952 }
953
nrf_mpc_override_ownerid_set(NRF_MPC_Type * p_reg,uint8_t index,nrf_owner_t owner_id)954 NRF_STATIC_INLINE void nrf_mpc_override_ownerid_set(NRF_MPC_Type * p_reg,
955 uint8_t index,
956 nrf_owner_t owner_id)
957 {
958 NRFX_ASSERT(index < NRF_MPC_OVERRIDE_COUNT);
959
960 p_reg->OVERRIDE[index].OWNER = (owner_id << MPC_OVERRIDE_OWNER_OWNERID_Pos) &
961 MPC_OVERRIDE_OWNER_OWNERID_Msk;
962 }
963
nrf_mpc_override_ownerid_get(NRF_MPC_Type * p_reg,uint8_t index)964 NRF_STATIC_INLINE nrf_owner_t nrf_mpc_override_ownerid_get(NRF_MPC_Type * p_reg, uint8_t index)
965 {
966 NRFX_ASSERT(index < NRF_MPC_OVERRIDE_COUNT);
967
968 return (nrf_owner_t)p_reg->OVERRIDE[index].OWNER;
969 }
970
nrf_mpc_override_masterport_set(NRF_MPC_Type * p_reg,uint8_t index,uint32_t mask)971 NRF_STATIC_INLINE void nrf_mpc_override_masterport_set(NRF_MPC_Type * p_reg,
972 uint8_t index,
973 uint32_t mask)
974 {
975 NRFX_ASSERT(index < NRF_MPC_OVERRIDE_COUNT);
976
977 p_reg->OVERRIDE[index].MASTERPORT = mask;
978 }
979
nrf_mpc_override_masterport_get(NRF_MPC_Type const * p_reg,uint8_t index)980 NRF_STATIC_INLINE uint32_t nrf_mpc_override_masterport_get(NRF_MPC_Type const * p_reg,
981 uint8_t index)
982 {
983 NRFX_ASSERT(index < NRF_MPC_OVERRIDE_COUNT);
984
985 return p_reg->OVERRIDE[index].MASTERPORT;
986 }
987
nrf_mpc_memaccerr_address_get(NRF_MPC_Type const * p_reg)988 NRF_STATIC_INLINE uint32_t nrf_mpc_memaccerr_address_get(NRF_MPC_Type const * p_reg)
989 {
990 return p_reg->MEMACCERR.ADDRESS;
991 }
992
nrf_mpc_memaccerr_info_ownerid_get(NRF_MPC_Type const * p_reg)993 NRF_STATIC_INLINE nrf_owner_t nrf_mpc_memaccerr_info_ownerid_get(NRF_MPC_Type const * p_reg)
994 {
995 return (nrf_owner_t)((p_reg->MEMACCERR.INFO & MPC_MEMACCERR_INFO_OWNERID_Msk)
996 >> MPC_MEMACCERR_INFO_OWNERID_Pos);
997 }
998
nrf_mpc_memaccerr_info_masterport_get(NRF_MPC_Type const * p_reg)999 NRF_STATIC_INLINE uint8_t nrf_mpc_memaccerr_info_masterport_get(NRF_MPC_Type const * p_reg)
1000 {
1001 return ((p_reg->MEMACCERR.INFO & MPC_MEMACCERR_INFO_MASTERPORT_Msk)
1002 >> MPC_MEMACCERR_INFO_MASTERPORT_Pos);
1003 }
1004
nrf_mpc_memaccerr_info_perm_get(NRF_MPC_Type const * p_reg)1005 NRF_STATIC_INLINE uint32_t nrf_mpc_memaccerr_info_perm_get(NRF_MPC_Type const * p_reg)
1006 {
1007 return ((p_reg->MEMACCERR.INFO &
1008 (MPC_MEMACCERR_INFO_READ_Msk | MPC_MEMACCERR_INFO_WRITE_Msk |
1009 MPC_MEMACCERR_INFO_EXECUTE_Msk | MPC_MEMACCERR_INFO_SECURE_Msk))
1010 >> MPC_MEMACCERR_INFO_READ_Pos);
1011 }
1012
1013 NRF_STATIC_INLINE nrf_mpc_errorsource_t
nrf_mpc_memaccerr_info_errorsource_get(NRF_MPC_Type const * p_reg)1014 nrf_mpc_memaccerr_info_errorsource_get(NRF_MPC_Type const * p_reg)
1015 {
1016 return (nrf_mpc_errorsource_t)((p_reg->MEMACCERR.INFO & MPC_MEMACCERR_INFO_ERRORSOURCE_Msk)
1017 >> MPC_MEMACCERR_INFO_ERRORSOURCE_Pos);
1018 }
1019
nrf_mpc_globalslave_masterport_set(NRF_MPC_Type * p_reg,uint32_t mask)1020 NRF_STATIC_INLINE void nrf_mpc_globalslave_masterport_set(NRF_MPC_Type * p_reg, uint32_t mask)
1021 {
1022 p_reg->GLOBALSLAVE.MASTERPORT = mask;
1023 }
1024
nrf_mpc_globalslave_masterport_get(NRF_MPC_Type const * p_reg)1025 NRF_STATIC_INLINE uint32_t nrf_mpc_globalslave_masterport_get(NRF_MPC_Type const * p_reg)
1026 {
1027 return p_reg->GLOBALSLAVE.MASTERPORT;
1028 }
1029
nrf_mpc_globalslave_lock_enable(NRF_MPC_Type * p_reg)1030 NRF_STATIC_INLINE void nrf_mpc_globalslave_lock_enable(NRF_MPC_Type * p_reg)
1031 {
1032 p_reg->GLOBALSLAVE.LOCK = (MPC_GLOBALSLAVE_LOCK_LOCK_Enabled << MPC_GLOBALSLAVE_LOCK_LOCK_Pos);
1033 }
1034
nrf_mpc_globalslave_lock_check(NRF_MPC_Type const * p_reg)1035 NRF_STATIC_INLINE bool nrf_mpc_globalslave_lock_check(NRF_MPC_Type const * p_reg)
1036 {
1037 return ((p_reg->GLOBALSLAVE.LOCK & MPC_GLOBALSLAVE_LOCK_LOCK_Msk)
1038 >> MPC_GLOBALSLAVE_LOCK_LOCK_Pos) == MPC_GLOBALSLAVE_LOCK_LOCK_Enabled;
1039 }
1040
1041 #if NRF_MPC_HAS_RTCHOKE
nrf_mpc_rtchoke_writeaccess_set(NRF_MPC_Type * p_reg,uint32_t mask)1042 NRF_STATIC_INLINE void nrf_mpc_rtchoke_writeaccess_set(NRF_MPC_Type * p_reg, uint32_t mask)
1043 {
1044 p_reg->RTCHOKE.WRITEACCESS = mask;
1045 }
1046
nrf_mpc_rtchoke_writeaccess_get(NRF_MPC_Type const * p_reg)1047 NRF_STATIC_INLINE uint32_t nrf_mpc_rtchoke_writeaccess_get(NRF_MPC_Type const * p_reg)
1048 {
1049 return p_reg->RTCHOKE.WRITEACCESS;
1050 }
1051
nrf_mpc_rtchoke_readaccess_set(NRF_MPC_Type * p_reg,uint32_t mask)1052 NRF_STATIC_INLINE void nrf_mpc_rtchoke_readaccess_set(NRF_MPC_Type * p_reg, uint32_t mask)
1053 {
1054 p_reg->RTCHOKE.READACCESS = mask;
1055 }
1056
nrf_mpc_rtchoke_readaccess_get(NRF_MPC_Type const * p_reg)1057 NRF_STATIC_INLINE uint32_t nrf_mpc_rtchoke_readaccess_get(NRF_MPC_Type const * p_reg)
1058 {
1059 return p_reg->RTCHOKE.READACCESS;
1060 }
1061
nrf_mpc_rtchoke_delay_set(NRF_MPC_Type * p_reg,uint8_t slave,uint8_t delay)1062 NRF_STATIC_INLINE void nrf_mpc_rtchoke_delay_set(NRF_MPC_Type * p_reg,
1063 uint8_t slave,
1064 uint8_t delay)
1065 {
1066 NRFX_ASSERT(slave < NRF_MPC_RTCHOKE_COUNT);
1067
1068 p_reg->RTCHOKE.DELAY[slave] = delay;
1069 }
1070
nrf_mpc_rtchoke_delay_get(NRF_MPC_Type const * p_reg,uint8_t slave)1071 NRF_STATIC_INLINE uint8_t nrf_mpc_rtchoke_delay_get(NRF_MPC_Type const * p_reg, uint8_t slave)
1072 {
1073 NRFX_ASSERT(slave < NRF_MPC_RTCHOKE_COUNT);
1074
1075 return (uint8_t)p_reg->RTCHOKE.DELAY[slave];
1076 }
1077 #endif
1078
1079 #endif // NRF_DECLARE_ONLY
1080
1081 /** @} */
1082
1083 #ifdef __cplusplus
1084 }
1085 #endif
1086
1087 #endif /* NRF_MPC_H_ */
1088
