1 /*
2 * Copyright (c) 2023 - 2024, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_MEMCONF_H__
35 #define NRF_MEMCONF_H__
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /**
44 * @defgroup nrf_memconf_hal MEMCONF HAL
45 * @{
46 * @ingroup nrf_memconf
47 * @brief Hardware access layer for managing the Memory Configuration (MEMCONF) peripheral.
48 */
49
50 #if defined(MEMCONF_POWER_RET2_MEM0_Msk) || defined(__NRFX_DOXYGEN__)
51 /** @brief Symbol indicating whether the second retention configuration register is present. */
52 #define NRF_MEMCONF_HAS_RET2 1
53 #else
54 #define NRF_MEMCONF_HAS_RET2 0
55 #endif
56
57 #if defined(MEMCONF_REPAIR_BITLINE_ADDR_Msk) || defined(__NRFX_DOXYGEN__)
58 /** @brief Symbol indicating whether the repair configuration for RAM blocks is present. */
59 #define NRF_MEMCONF_HAS_REPAIR 1
60 #else
61 #define NRF_MEMCONF_HAS_REPAIR 0
62 #endif
63
64 #if defined(MEMCONF_BLOCKTYPE_TRIM_MEMTRIM0_Msk) || defined(__NRFX_DOXYGEN__)
65 /** @brief Symbol indicating whether the trim configuration is present. */
66 #define NRF_MEMCONF_HAS_TRIM 1
67 #else
68 #define NRF_MEMCONF_HAS_TRIM 0
69 #endif
70
71 /** @brief Symbol specifying maximum number of available power blocks. */
72 #define NRF_MEMCONF_POWERBLOCK_COUNT MEMCONF_POWER_MaxCount
73
74 /** @brief Symbol specifying maximum number of control RAM blocks. */
75 #define NRF_MEMCONF_POWERBLOCK_RAMBLOCK_CONTROL_COUNT MEMCONF_POWER_CONTROL_MEM31_Pos
76
77 /** @brief Symbol specifying maximum number of retention RAM blocks. */
78 #define NRF_MEMCONF_POWERBLOCK_RAMBLOCK_RET_COUNT MEMCONF_POWER_RET_MEM31_Pos
79
80 /** @brief Symbol specifying maximum number of second bank retention RAM blocks. */
81 #define NRF_MEMCONF_POWERBLOCK_RAMBLOCK_RET2_COUNT MEMCONF_POWER_RET2_MEM31_Pos
82
83 /** @brief Symbol specifying bitmask collecting all memory read and write margin trims. */
84 #define NRF_MEMCONF_BLOCKTYPE_TRIM_MEMTRIM_MASK \
85 (MEMCONF_BLOCKTYPE_TRIM_MEMTRIM0_Msk | MEMCONF_BLOCKTYPE_TRIM_MEMTRIM1_Msk | \
86 MEMCONF_BLOCKTYPE_TRIM_MEMTRIM2_Msk | MEMCONF_BLOCKTYPE_TRIM_MEMTRIM3_Msk | \
87 MEMCONF_BLOCKTYPE_TRIM_MEMTRIM4_Msk | MEMCONF_BLOCKTYPE_TRIM_MEMTRIM5_Msk | \
88 MEMCONF_BLOCKTYPE_TRIM_MEMTRIM6_Msk | MEMCONF_BLOCKTYPE_TRIM_MEMTRIM7_Msk | \
89 MEMCONF_BLOCKTYPE_TRIM_MEMTRIM8_Msk | MEMCONF_BLOCKTYPE_TRIM_MEMTRIM9_Msk | \
90 MEMCONF_BLOCKTYPE_TRIM_MEMTRIM10_Msk | MEMCONF_BLOCKTYPE_TRIM_MEMTRIM11_Msk | \
91 MEMCONF_BLOCKTYPE_TRIM_MEMTRIM12_Msk | MEMCONF_BLOCKTYPE_TRIM_MEMTRIM13_Msk | \
92 MEMCONF_BLOCKTYPE_TRIM_MEMTRIM14_Msk | MEMCONF_BLOCKTYPE_TRIM_MEMTRIM15_Msk)
93
94 /** @brief Symbol specifying bitmask collecting all memory retention trims. */
95 #define NRF_MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM_MASK \
96 (MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM0_Msk | MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM1_Msk | \
97 MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM2_Msk | MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM3_Msk | \
98 MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM4_Msk | MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM5_Msk | \
99 MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM6_Msk | MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM7_Msk | \
100 MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM8_Msk | MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM9_Msk | \
101 MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM10_Msk | MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM11_Msk | \
102 MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM12_Msk | MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM13_Msk | \
103 MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM14_Msk | MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM15_Msk)
104
105 /**
106 * @brief Function for enabling or disabling given RAM block.
107 *
108 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
109 * @param[in] power_id Power block index.
110 * @param[in] ramblock RAM block index.
111 * @param[in] enable True if RAM block is to be enabled, false otherwise.
112 */
113 NRF_STATIC_INLINE void nrf_memconf_ramblock_control_enable_set(NRF_MEMCONF_Type * p_reg,
114 uint8_t power_id,
115 uint8_t ramblock,
116 bool enable);
117
118 /**
119 * @brief Function for enabling or disabling specified RAM blocks.
120 *
121 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
122 * @param[in] power_id Power block index.
123 * @param[in] ramblock_mask Mask of RAM blocks.
124 * @param[in] enable True if RAM blocks are to be enabled, false otherwise.
125 */
126 NRF_STATIC_INLINE
127 void nrf_memconf_ramblock_control_mask_enable_set(NRF_MEMCONF_Type * p_reg,
128 uint8_t power_id,
129 uint32_t ramblock_mask,
130 bool enable);
131
132 /**
133 * @brief Function for checking whether given RAM block is enabled.
134 *
135 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
136 * @param[in] power_id Power block index.
137 * @param[in] ramblock RAM block index.
138 *
139 * @retval true RAM block is enabled.
140 * @retval false RAM block is disabled.
141 */
142 NRF_STATIC_INLINE bool nrf_memconf_ramblock_control_enable_check(NRF_MEMCONF_Type const * p_reg,
143 uint8_t power_id,
144 uint8_t ramblock);
145
146 /**
147 * @brief Function for enabling or disabling the retention for given RAM block.
148 *
149 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
150 * @param[in] power_id Power block index.
151 * @param[in] ramblock RAM block index.
152 * @param[in] enable True if RAM block retention is to be enabled, false otherwise.
153 */
154 NRF_STATIC_INLINE void nrf_memconf_ramblock_ret_enable_set(NRF_MEMCONF_Type * p_reg,
155 uint8_t power_id,
156 uint8_t ramblock,
157 bool enable);
158
159 /**
160 * @brief Function for enabling or disabling retention for the specified RAM blocks.
161 *
162 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
163 * @param[in] power_id Power block index.
164 * @param[in] ramblock_mask Mask of RAM blocks.
165 * @param[in] enable True if retention for RAM blocks is to be enabled, false otherwise.
166 */
167 NRF_STATIC_INLINE void nrf_memconf_ramblock_ret_mask_enable_set(NRF_MEMCONF_Type * p_reg,
168 uint8_t power_id,
169 uint32_t ramblock_mask,
170 bool enable);
171
172 /**
173 * @brief Function for checking whether the retention of specified RAM block is enabled.
174 *
175 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
176 * @param[in] power_id Power block index.
177 * @param[in] ramblock RAM block index.
178 *
179 * @retval true RAM block is enabled.
180 * @retval false RAM block is disabled.
181 */
182 NRF_STATIC_INLINE bool nrf_memconf_ramblock_ret_enable_check(NRF_MEMCONF_Type const * p_reg,
183 uint8_t power_id,
184 uint8_t ramblock);
185
186 #if NRF_MEMCONF_HAS_RET2
187 /**
188 * @brief Function for enabling or disabling the retention within the second bank for given RAM block.
189 *
190 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
191 * @param[in] power_id Power block index.
192 * @param[in] ramblock RAM block index.
193 * @param[in] enable True if RAM block retention is to be enabled, false otherwise.
194 */
195 NRF_STATIC_INLINE void nrf_memconf_ramblock_ret2_enable_set(NRF_MEMCONF_Type * p_reg,
196 uint8_t power_id,
197 uint8_t ramblock,
198 bool enable);
199
200 /**
201 * @brief Function for checking whether the retention of second bank in specified RAM block is enabled.
202 *
203 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
204 * @param[in] power_id Power block index.
205 * @param[in] ramblock RAM block index.
206 *
207 * @retval true RAM block is enabled.
208 * @retval false RAM block is disabled.
209 */
210 NRF_STATIC_INLINE bool nrf_memconf_ramblock_ret2_enable_check(NRF_MEMCONF_Type const * p_reg,
211 uint8_t power_id,
212 uint8_t ramblock);
213 #endif
214
215 #if NRF_MEMCONF_HAS_REPAIR
216 /**
217 * @brief Function for enabling or disabling given bitline.
218 *
219 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
220 * @param[in] bitline Bitline to be enabled/disabled.
221 * @param[in] enable True if bitline is to be enabled, false otherwise.
222 */
223 NRF_STATIC_INLINE void nrf_memconf_bitline_enable_set(NRF_MEMCONF_Type * p_reg,
224 uint8_t bitline,
225 bool enable);
226
227 /**
228 * @brief Function for getting enable status for given bitline.
229 *
230 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
231 * @param[in] bitline Bitline index.
232 *
233 * @return Status of requested bitline.
234 */
235 NRF_STATIC_INLINE bool nrf_memconf_bitline_enable_check(NRF_MEMCONF_Type const * p_reg,
236 uint8_t bitline);
237
238 /**
239 * @brief Function for setting bitline address.
240 *
241 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
242 * @param[in] bitline Bitline index.
243 * @param[in] address Addres for given bitline.
244 *
245 */
246 NRF_STATIC_INLINE void nrf_memconf_bitline_address_set(NRF_MEMCONF_Type * p_reg,
247 uint8_t bitline,
248 uint8_t address);
249
250 /**
251 * @brief Function for getting bitline address.
252 *
253 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
254 * @param[in] bitline Bitline index.
255 *
256 * @return Address of requested bitline.
257 */
258 NRF_STATIC_INLINE uint32_t nrf_memconf_bitline_address_get(NRF_MEMCONF_Type const * p_reg,
259 uint8_t bitline);
260 #endif
261
262 #if NRF_MEMCONF_HAS_TRIM
263 /**
264 * @brief Function for setting memory trim value.
265 *
266 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
267 * @param[in] trim_id Trim index.
268 * @param[in] trim_val Trim value.
269 */
270 NRF_STATIC_INLINE void nrf_memconf_memtrim_set(NRF_MEMCONF_Type * p_reg,
271 uint8_t trim_id,
272 uint16_t trim_val);
273
274 /**
275 * @brief Function for getting memory trim value.
276 *
277 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
278 * @param[in] trim_id Trim index.
279 *
280 * @return Requested trim value.
281 */
282 NRF_STATIC_INLINE uint16_t nrf_memconf_memtrim_get(NRF_MEMCONF_Type const * p_reg,
283 uint8_t trim_id);
284
285 /**
286 * @brief Function for setting retention trim value.
287 *
288 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
289 * @param[in] trim_id Trim index.
290 * @param[in] trim_val Trim value.
291 */
292 NRF_STATIC_INLINE void nrf_memconf_rettrim_set(NRF_MEMCONF_Type * p_reg,
293 uint8_t trim_id,
294 uint16_t trim_val);
295
296 /**
297 * @brief Function for getting retention trim value.
298 *
299 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
300 * @param[in] trim_id Trim index.
301 *
302 * @return Requested trim value.
303 */
304 NRF_STATIC_INLINE uint16_t nrf_memconf_rettrim_get(NRF_MEMCONF_Type const * p_reg,
305 uint8_t trim_id);
306 #endif
307
308 #ifndef NRF_DECLARE_ONLY
nrf_memconf_ramblock_control_enable_set(NRF_MEMCONF_Type * p_reg,uint8_t power_id,uint8_t ramblock,bool enable)309 NRF_STATIC_INLINE void nrf_memconf_ramblock_control_enable_set(NRF_MEMCONF_Type * p_reg,
310 uint8_t power_id,
311 uint8_t ramblock,
312 bool enable)
313 {
314 NRFX_ASSERT(power_id < NRF_MEMCONF_POWERBLOCK_COUNT);
315 NRFX_ASSERT(ramblock <= NRF_MEMCONF_POWERBLOCK_RAMBLOCK_CONTROL_COUNT);
316
317 p_reg->POWER[power_id].CONTROL = ((p_reg->POWER[power_id].CONTROL &
318 ~(MEMCONF_POWER_CONTROL_MEM0_On << ramblock)) |
319 ((enable ?
320 MEMCONF_POWER_CONTROL_MEM0_On :
321 MEMCONF_POWER_CONTROL_MEM0_Off) << ramblock));
322 }
323
324 NRF_STATIC_INLINE
nrf_memconf_ramblock_control_mask_enable_set(NRF_MEMCONF_Type * p_reg,uint8_t power_id,uint32_t ramblock_mask,bool enable)325 void nrf_memconf_ramblock_control_mask_enable_set(NRF_MEMCONF_Type * p_reg,
326 uint8_t power_id,
327 uint32_t ramblock_mask,
328 bool enable)
329 {
330 NRFX_ASSERT(power_id < NRF_MEMCONF_POWERBLOCK_COUNT);
331
332 if (enable)
333 {
334 p_reg->POWER[power_id].CONTROL |= ramblock_mask;
335 }
336 else
337 {
338 p_reg->POWER[power_id].CONTROL &= ~ramblock_mask;
339 }
340 }
341
nrf_memconf_ramblock_control_enable_check(NRF_MEMCONF_Type const * p_reg,uint8_t power_id,uint8_t ramblock)342 NRF_STATIC_INLINE bool nrf_memconf_ramblock_control_enable_check(NRF_MEMCONF_Type const * p_reg,
343 uint8_t power_id,
344 uint8_t ramblock)
345 {
346 NRFX_ASSERT(power_id < NRF_MEMCONF_POWERBLOCK_COUNT);
347 NRFX_ASSERT(ramblock <= NRF_MEMCONF_POWERBLOCK_RAMBLOCK_CONTROL_COUNT);
348
349 return (bool)(p_reg->POWER[power_id].CONTROL & (MEMCONF_POWER_CONTROL_MEM0_Msk << ramblock));
350 }
351
nrf_memconf_ramblock_ret_enable_set(NRF_MEMCONF_Type * p_reg,uint8_t power_id,uint8_t ramblock,bool enable)352 NRF_STATIC_INLINE void nrf_memconf_ramblock_ret_enable_set(NRF_MEMCONF_Type * p_reg,
353 uint8_t power_id,
354 uint8_t ramblock,
355 bool enable)
356 {
357 NRFX_ASSERT(power_id < NRF_MEMCONF_POWERBLOCK_COUNT);
358 NRFX_ASSERT(ramblock <= NRF_MEMCONF_POWERBLOCK_RAMBLOCK_RET_COUNT);
359
360 p_reg->POWER[power_id].RET = ((p_reg->POWER[power_id].RET &
361 ~(MEMCONF_POWER_RET_MEM0_On << ramblock)) |
362 ((enable ?
363 MEMCONF_POWER_RET_MEM0_On :
364 MEMCONF_POWER_RET_MEM0_Off) << ramblock));
365 }
366
nrf_memconf_ramblock_ret_mask_enable_set(NRF_MEMCONF_Type * p_reg,uint8_t power_id,uint32_t ramblock_mask,bool enable)367 NRF_STATIC_INLINE void nrf_memconf_ramblock_ret_mask_enable_set(NRF_MEMCONF_Type * p_reg,
368 uint8_t power_id,
369 uint32_t ramblock_mask,
370 bool enable)
371 {
372 NRFX_ASSERT(power_id < NRF_MEMCONF_POWERBLOCK_COUNT);
373
374 if (enable)
375 {
376 p_reg->POWER[power_id].RET |= ramblock_mask;
377 }
378 else
379 {
380 p_reg->POWER[power_id].RET &= ~ramblock_mask;
381 }
382 }
383
nrf_memconf_ramblock_ret_enable_check(NRF_MEMCONF_Type const * p_reg,uint8_t power_id,uint8_t ramblock)384 NRF_STATIC_INLINE bool nrf_memconf_ramblock_ret_enable_check(NRF_MEMCONF_Type const * p_reg,
385 uint8_t power_id,
386 uint8_t ramblock)
387 {
388 NRFX_ASSERT(power_id < NRF_MEMCONF_POWERBLOCK_COUNT);
389 NRFX_ASSERT(ramblock <= NRF_MEMCONF_POWERBLOCK_RAMBLOCK_RET_COUNT);
390
391 return (bool)(p_reg->POWER[power_id].RET & (MEMCONF_POWER_RET_MEM0_Msk << ramblock));
392 }
393
394 #if NRF_MEMCONF_HAS_RET2
nrf_memconf_ramblock_ret2_enable_set(NRF_MEMCONF_Type * p_reg,uint8_t power_id,uint8_t ramblock,bool enable)395 NRF_STATIC_INLINE void nrf_memconf_ramblock_ret2_enable_set(NRF_MEMCONF_Type * p_reg,
396 uint8_t power_id,
397 uint8_t ramblock,
398 bool enable)
399 {
400 NRFX_ASSERT(power_id < NRF_MEMCONF_POWERBLOCK_COUNT);
401 NRFX_ASSERT(ramblock <= NRF_MEMCONF_POWERBLOCK_RAMBLOCK_RET2_COUNT);
402
403 p_reg->POWER[power_id].RET2 = ((p_reg->POWER[power_id].RET2 &
404 ~(MEMCONF_POWER_RET2_MEM0_On << ramblock)) |
405 ((enable ?
406 MEMCONF_POWER_RET2_MEM0_On :
407 MEMCONF_POWER_RET2_MEM0_Off) << ramblock));
408 }
409
nrf_memconf_ramblock_ret2_enable_check(NRF_MEMCONF_Type const * p_reg,uint8_t power_id,uint8_t ramblock)410 NRF_STATIC_INLINE bool nrf_memconf_ramblock_ret2_enable_check(NRF_MEMCONF_Type const * p_reg,
411 uint8_t power_id,
412 uint8_t ramblock)
413 {
414 NRFX_ASSERT(power_id < NRF_MEMCONF_POWERBLOCK_COUNT);
415 NRFX_ASSERT(ramblock <= NRF_MEMCONF_POWERBLOCK_RAMBLOCK_RET2_COUNT);
416
417 return (bool)(p_reg->POWER[power_id].RET2 & (MEMCONF_POWER_RET2_MEM0_Msk << ramblock));
418 }
419 #endif
420
421 #if NRF_MEMCONF_HAS_REPAIR
nrf_memconf_bitline_enable_set(NRF_MEMCONF_Type * p_reg,uint8_t bitline,bool enable)422 NRF_STATIC_INLINE void nrf_memconf_bitline_enable_set(NRF_MEMCONF_Type * p_reg,
423 uint8_t bitline,
424 bool enable)
425 {
426 p_reg->REPAIR[bitline].BITLINE = ((p_reg->REPAIR[bitline].BITLINE &
427 ~MEMCONF_REPAIR_BITLINE_EN_Msk) |
428 ((enable ?
429 MEMCONF_REPAIR_BITLINE_EN_Enabled :
430 MEMCONF_REPAIR_BITLINE_EN_Disabled)
431 << MEMCONF_REPAIR_BITLINE_EN_Pos));
432 }
433
nrf_memconf_bitline_enable_check(NRF_MEMCONF_Type const * p_reg,uint8_t bitline)434 NRF_STATIC_INLINE bool nrf_memconf_bitline_enable_check(NRF_MEMCONF_Type const * p_reg,
435 uint8_t bitline)
436 {
437 return (bool)(p_reg->REPAIR[bitline].BITLINE & MEMCONF_REPAIR_BITLINE_EN_Msk);
438 }
439
nrf_memconf_bitline_address_set(NRF_MEMCONF_Type * p_reg,uint8_t bitline,uint8_t address)440 NRF_STATIC_INLINE void nrf_memconf_bitline_address_set(NRF_MEMCONF_Type * p_reg,
441 uint8_t bitline,
442 uint8_t address)
443 {
444 p_reg->REPAIR[bitline].BITLINE = (p_reg->REPAIR[bitline].BITLINE &
445 MEMCONF_REPAIR_BITLINE_ADDR_Msk) | (uint32_t)address;
446 }
447
nrf_memconf_bitline_address_get(NRF_MEMCONF_Type const * p_reg,uint8_t bitline)448 NRF_STATIC_INLINE uint32_t nrf_memconf_bitline_address_get(NRF_MEMCONF_Type const * p_reg,
449 uint8_t bitline)
450 {
451 return (uint32_t)(p_reg->REPAIR[bitline].BITLINE & MEMCONF_REPAIR_BITLINE_ADDR_Msk);
452 }
453 #endif
454
455 #if NRF_MEMCONF_HAS_TRIM
nrf_memconf_memtrim_set(NRF_MEMCONF_Type * p_reg,uint8_t trim_id,uint16_t trim_val)456 NRF_STATIC_INLINE void nrf_memconf_memtrim_set(NRF_MEMCONF_Type * p_reg,
457 uint8_t trim_id,
458 uint16_t trim_val)
459 {
460 p_reg->BLOCKTYPE[trim_id].TRIM =
461 (p_reg->BLOCKTYPE[trim_id].TRIM & ~NRF_MEMCONF_BLOCKTYPE_TRIM_MEMTRIM_MASK) |
462 (trim_val << MEMCONF_BLOCKTYPE_TRIM_MEMTRIM0_Pos);
463 }
464
nrf_memconf_memtrim_get(NRF_MEMCONF_Type const * p_reg,uint8_t trim_id)465 NRF_STATIC_INLINE uint16_t nrf_memconf_memtrim_get(NRF_MEMCONF_Type const * p_reg, uint8_t trim_id)
466 {
467 return (uint16_t)((p_reg->BLOCKTYPE[trim_id].TRIM & NRF_MEMCONF_BLOCKTYPE_TRIM_MEMTRIM_MASK)
468 >> MEMCONF_BLOCKTYPE_TRIM_MEMTRIM0_Pos);
469 }
470
nrf_memconf_rettrim_set(NRF_MEMCONF_Type * p_reg,uint8_t trim_id,uint16_t trim_val)471 NRF_STATIC_INLINE void nrf_memconf_rettrim_set(NRF_MEMCONF_Type * p_reg,
472 uint8_t trim_id,
473 uint16_t trim_val)
474 {
475 p_reg->BLOCKTYPE[trim_id].TRIM =
476 (p_reg->BLOCKTYPE[trim_id].TRIM & ~NRF_MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM_MASK) |
477 (trim_val << MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM0_Pos);
478 }
479
nrf_memconf_rettrim_get(NRF_MEMCONF_Type const * p_reg,uint8_t trim_id)480 NRF_STATIC_INLINE uint16_t nrf_memconf_rettrim_get(NRF_MEMCONF_Type const * p_reg, uint8_t trim_id)
481 {
482 return (uint16_t)((p_reg->BLOCKTYPE[trim_id].TRIM & NRF_MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM_MASK)
483 >> MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM0_Pos);
484 }
485 #endif
486
487 #endif // NRF_DECLARE_ONLY
488
489 /** @} */
490
491 #ifdef __cplusplus
492 }
493 #endif
494
495 #endif // NRF_MEMCONF_H__
496
