1 /*
2 * Copyright (c) 2019 - 2024, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_IPC_H__
35 #define NRF_IPC_H__
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 #if !defined(IPC_EVENTS_NUM) && defined(IPC_CH_NUM)
44 #define IPC_EVENTS_NUM IPC_CH_NUM
45 #endif
46
47 #if !defined(IPC_TASKS_NUM) && defined(IPC_CH_NUM)
48 #define IPC_TASKS_NUM IPC_CH_NUM
49 #endif
50
51 /**
52 * @defgroup nrf_ipc_hal IPC HAL
53 * @{
54 * @ingroup nrf_ipc
55 * @brief Hardware access layer for managing the Interprocessor Communication (IPC) peripheral.
56 */
57
58 /** @brief IPC tasks. */
59 typedef enum
60 {
61 NRF_IPC_TASK_SEND_0 = offsetof(NRF_IPC_Type, TASKS_SEND[0]), ///< Trigger events on channels enabled in SEND_CNF[0].
62 NRF_IPC_TASK_SEND_1 = offsetof(NRF_IPC_Type, TASKS_SEND[1]), ///< Trigger events on channels enabled in SEND_CNF[1].
63 NRF_IPC_TASK_SEND_2 = offsetof(NRF_IPC_Type, TASKS_SEND[2]), ///< Trigger events on channels enabled in SEND_CNF[2].
64 NRF_IPC_TASK_SEND_3 = offsetof(NRF_IPC_Type, TASKS_SEND[3]), ///< Trigger events on channels enabled in SEND_CNF[3].
65 NRF_IPC_TASK_SEND_4 = offsetof(NRF_IPC_Type, TASKS_SEND[4]), ///< Trigger events on channels enabled in SEND_CNF[4].
66 NRF_IPC_TASK_SEND_5 = offsetof(NRF_IPC_Type, TASKS_SEND[5]), ///< Trigger events on channels enabled in SEND_CNF[5].
67 NRF_IPC_TASK_SEND_6 = offsetof(NRF_IPC_Type, TASKS_SEND[6]), ///< Trigger events on channels enabled in SEND_CNF[6].
68 NRF_IPC_TASK_SEND_7 = offsetof(NRF_IPC_Type, TASKS_SEND[7]), ///< Trigger events on channels enabled in SEND_CNF[7].
69 #if (IPC_TASKS_NUM > 8) || defined(__NRFX_DOXYGEN__)
70 NRF_IPC_TASK_SEND_8 = offsetof(NRF_IPC_Type, TASKS_SEND[8]), ///< Trigger events on channels enabled in SEND_CNF[8].
71 NRF_IPC_TASK_SEND_9 = offsetof(NRF_IPC_Type, TASKS_SEND[9]), ///< Trigger events on channels enabled in SEND_CNF[9].
72 NRF_IPC_TASK_SEND_10 = offsetof(NRF_IPC_Type, TASKS_SEND[10]), ///< Trigger events on channels enabled in SEND_CNF[10].
73 NRF_IPC_TASK_SEND_11 = offsetof(NRF_IPC_Type, TASKS_SEND[11]), ///< Trigger events on channels enabled in SEND_CNF[11].
74 NRF_IPC_TASK_SEND_12 = offsetof(NRF_IPC_Type, TASKS_SEND[12]), ///< Trigger events on channels enabled in SEND_CNF[12].
75 NRF_IPC_TASK_SEND_13 = offsetof(NRF_IPC_Type, TASKS_SEND[13]), ///< Trigger events on channels enabled in SEND_CNF[13].
76 NRF_IPC_TASK_SEND_14 = offsetof(NRF_IPC_Type, TASKS_SEND[14]), ///< Trigger events on channels enabled in SEND_CNF[14].
77 NRF_IPC_TASK_SEND_15 = offsetof(NRF_IPC_Type, TASKS_SEND[15]), ///< Trigger events on channels enabled in SEND_CNF[15].
78 #endif // (IPC_TASKS_NUM > 8) || defined(__NRFX_DOXYGEN__)
79 } nrf_ipc_task_t;
80
81 /** @brief IPC events. */
82 typedef enum
83 {
84 NRF_IPC_EVENT_RECEIVE_0 = offsetof(NRF_IPC_Type, EVENTS_RECEIVE[0]), ///< Event received on the IPC channels enabled in RECEIVE_CNF[0] register.
85 NRF_IPC_EVENT_RECEIVE_1 = offsetof(NRF_IPC_Type, EVENTS_RECEIVE[1]), ///< Event received on the IPC channels enabled in RECEIVE_CNF[1] register.
86 NRF_IPC_EVENT_RECEIVE_2 = offsetof(NRF_IPC_Type, EVENTS_RECEIVE[2]), ///< Event received on the IPC channels enabled in RECEIVE_CNF[2] register.
87 NRF_IPC_EVENT_RECEIVE_3 = offsetof(NRF_IPC_Type, EVENTS_RECEIVE[3]), ///< Event received on the IPC channels enabled in RECEIVE_CNF[3] register.
88 NRF_IPC_EVENT_RECEIVE_4 = offsetof(NRF_IPC_Type, EVENTS_RECEIVE[4]), ///< Event received on the IPC channels enabled in RECEIVE_CNF[4] register.
89 NRF_IPC_EVENT_RECEIVE_5 = offsetof(NRF_IPC_Type, EVENTS_RECEIVE[5]), ///< Event received on the IPC channels enabled in RECEIVE_CNF[5] register.
90 NRF_IPC_EVENT_RECEIVE_6 = offsetof(NRF_IPC_Type, EVENTS_RECEIVE[6]), ///< Event received on the IPC channels enabled in RECEIVE_CNF[6] register.
91 NRF_IPC_EVENT_RECEIVE_7 = offsetof(NRF_IPC_Type, EVENTS_RECEIVE[7]), ///< Event received on the IPC channels enabled in RECEIVE_CNF[7] register.
92 #if (IPC_EVENTS_NUM > 8) || defined(__NRFX_DOXYGEN__)
93 NRF_IPC_EVENT_RECEIVE_8 = offsetof(NRF_IPC_Type, EVENTS_RECEIVE[8]), ///< Event received on the IPC channels enabled in RECEIVE_CNF[8] register.
94 NRF_IPC_EVENT_RECEIVE_9 = offsetof(NRF_IPC_Type, EVENTS_RECEIVE[9]), ///< Event received on the IPC channels enabled in RECEIVE_CNF[9] register.
95 NRF_IPC_EVENT_RECEIVE_10 = offsetof(NRF_IPC_Type, EVENTS_RECEIVE[10]), ///< Event received on the IPC channels enabled in RECEIVE_CNF[10] register.
96 NRF_IPC_EVENT_RECEIVE_11 = offsetof(NRF_IPC_Type, EVENTS_RECEIVE[11]), ///< Event received on the IPC channels enabled in RECEIVE_CNF[11] register.
97 NRF_IPC_EVENT_RECEIVE_12 = offsetof(NRF_IPC_Type, EVENTS_RECEIVE[12]), ///< Event received on the IPC channels enabled in RECEIVE_CNF[12] register.
98 NRF_IPC_EVENT_RECEIVE_13 = offsetof(NRF_IPC_Type, EVENTS_RECEIVE[13]), ///< Event received on the IPC channels enabled in RECEIVE_CNF[13] register.
99 NRF_IPC_EVENT_RECEIVE_14 = offsetof(NRF_IPC_Type, EVENTS_RECEIVE[14]), ///< Event received on the IPC channels enabled in RECEIVE_CNF[14] register.
100 NRF_IPC_EVENT_RECEIVE_15 = offsetof(NRF_IPC_Type, EVENTS_RECEIVE[15]), ///< Event received on the IPC channels enabled in RECEIVE_CNF[15] register.
101 #endif // (IPC_EVENTS_NUM > 8) || defined(__NRFX_DOXYGEN__)
102 } nrf_ipc_event_t;
103
104 /** @brief IPC channel positions. */
105 typedef enum
106 {
107 NRF_IPC_CHANNEL_0 = IPC_RECEIVE_CNF_CHEN0_Msk, ///< Bitmask position for IPC channel 0.
108 NRF_IPC_CHANNEL_1 = IPC_RECEIVE_CNF_CHEN1_Msk, ///< Bitmask position for IPC channel 1.
109 NRF_IPC_CHANNEL_2 = IPC_RECEIVE_CNF_CHEN2_Msk, ///< Bitmask position for IPC channel 2.
110 NRF_IPC_CHANNEL_3 = IPC_RECEIVE_CNF_CHEN3_Msk, ///< Bitmask position for IPC channel 3.
111 NRF_IPC_CHANNEL_4 = IPC_RECEIVE_CNF_CHEN4_Msk, ///< Bitmask position for IPC channel 4.
112 NRF_IPC_CHANNEL_5 = IPC_RECEIVE_CNF_CHEN5_Msk, ///< Bitmask position for IPC channel 5.
113 NRF_IPC_CHANNEL_6 = IPC_RECEIVE_CNF_CHEN6_Msk, ///< Bitmask position for IPC channel 6.
114 NRF_IPC_CHANNEL_7 = IPC_RECEIVE_CNF_CHEN7_Msk, ///< Bitmask position for IPC channel 7.
115 #if (IPC_CH_NUM > 8) || defined(__NRFX_DOXYGEN__)
116 NRF_IPC_CHANNEL_8 = IPC_RECEIVE_CNF_CHEN8_Msk, ///< Bitmask position for IPC channel 8.
117 NRF_IPC_CHANNEL_9 = IPC_RECEIVE_CNF_CHEN9_Msk, ///< Bitmask position for IPC channel 9.
118 NRF_IPC_CHANNEL_10 = IPC_RECEIVE_CNF_CHEN10_Msk, ///< Bitmask position for IPC channel 10.
119 NRF_IPC_CHANNEL_11 = IPC_RECEIVE_CNF_CHEN11_Msk, ///< Bitmask position for IPC channel 11.
120 NRF_IPC_CHANNEL_12 = IPC_RECEIVE_CNF_CHEN12_Msk, ///< Bitmask position for IPC channel 12.
121 NRF_IPC_CHANNEL_13 = IPC_RECEIVE_CNF_CHEN13_Msk, ///< Bitmask position for IPC channel 13.
122 NRF_IPC_CHANNEL_14 = IPC_RECEIVE_CNF_CHEN14_Msk, ///< Bitmask position for IPC channel 14.
123 NRF_IPC_CHANNEL_15 = IPC_RECEIVE_CNF_CHEN15_Msk, ///< Bitmask position for IPC channel 15.
124 #endif // (IPC_CH_NUM > 8) || defined(__NRFX_DOXYGEN__)
125 } nrf_ipc_channel_t;
126
127 /** @brief IPC interrupts. */
128 typedef enum
129 {
130 NRF_IPC_INT_RECEIVE_0 = IPC_INTEN_RECEIVE0_Msk, ///< Interrupt on receive event 0.
131 NRF_IPC_INT_RECEIVE_1 = IPC_INTEN_RECEIVE1_Msk, ///< Interrupt on receive event 1.
132 NRF_IPC_INT_RECEIVE_2 = IPC_INTEN_RECEIVE2_Msk, ///< Interrupt on receive event 2.
133 NRF_IPC_INT_RECEIVE_3 = IPC_INTEN_RECEIVE3_Msk, ///< Interrupt on receive event 3.
134 NRF_IPC_INT_RECEIVE_4 = IPC_INTEN_RECEIVE4_Msk, ///< Interrupt on receive event 4.
135 NRF_IPC_INT_RECEIVE_5 = IPC_INTEN_RECEIVE5_Msk, ///< Interrupt on receive event 5.
136 NRF_IPC_INT_RECEIVE_6 = IPC_INTEN_RECEIVE6_Msk, ///< Interrupt on receive event 6.
137 NRF_IPC_INT_RECEIVE_7 = IPC_INTEN_RECEIVE7_Msk, ///< Interrupt on receive event 7.
138 #if (IPC_EVENTS_NUM > 8) || defined(__NRFX_DOXYGEN__)
139 NRF_IPC_INT_RECEIVE_8 = IPC_INTEN_RECEIVE8_Msk, ///< Interrupt on receive event 8.
140 NRF_IPC_INT_RECEIVE_9 = IPC_INTEN_RECEIVE9_Msk, ///< Interrupt on receive event 9.
141 NRF_IPC_INT_RECEIVE_10 = IPC_INTEN_RECEIVE10_Msk, ///< Interrupt on receive event 10.
142 NRF_IPC_INT_RECEIVE_11 = IPC_INTEN_RECEIVE11_Msk, ///< Interrupt on receive event 11.
143 NRF_IPC_INT_RECEIVE_12 = IPC_INTEN_RECEIVE12_Msk, ///< Interrupt on receive event 12.
144 NRF_IPC_INT_RECEIVE_13 = IPC_INTEN_RECEIVE13_Msk, ///< Interrupt on receive event 13.
145 NRF_IPC_INT_RECEIVE_14 = IPC_INTEN_RECEIVE14_Msk, ///< Interrupt on receive event 14.
146 NRF_IPC_INT_RECEIVE_15 = IPC_INTEN_RECEIVE15_Msk, ///< Interrupt on receive event 15.
147 #endif // (IPC_EVENTS_NUM > 8) || defined(__NRFX_DOXYGEN__)
148 } nrf_ipc_int_mask_t;
149
150
151 /**
152 * @brief Function for triggering the specified IPC task.
153 *
154 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
155 * @param[in] task Task to be triggered.
156 */
157 NRF_STATIC_INLINE void nrf_ipc_task_trigger(NRF_IPC_Type * p_reg, nrf_ipc_task_t task);
158
159 /**
160 * @brief Function for getting the address of the specified IPC task register.
161 *
162 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
163 * @param[in] task Specified task.
164 *
165 * @return Address of the specified task register.
166 */
167 NRF_STATIC_INLINE uint32_t nrf_ipc_task_address_get(NRF_IPC_Type const * p_reg,
168 nrf_ipc_task_t task);
169
170 /**
171 * @brief Function for clearing the specified IPC event.
172 *
173 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
174 * @param[in] event Event to clear.
175 */
176 NRF_STATIC_INLINE void nrf_ipc_event_clear(NRF_IPC_Type * p_reg, nrf_ipc_event_t event);
177
178 /**
179 * @brief Function for retrieving the state of the IPC event.
180 *
181 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
182 * @param[in] event Event to be checked.
183 *
184 * @retval true The event has been generated.
185 * @retval false The event has not been generated.
186 */
187 NRF_STATIC_INLINE bool nrf_ipc_event_check(NRF_IPC_Type const * p_reg, nrf_ipc_event_t event);
188
189 /**
190 * @brief Function for getting the address of the specified IPC event register.
191 *
192 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
193 * @param[in] event Specified event.
194 *
195 * @return Address of the specified event register.
196 */
197 NRF_STATIC_INLINE uint32_t nrf_ipc_event_address_get(NRF_IPC_Type const * p_reg,
198 nrf_ipc_event_t event);
199
200 /**
201 * @brief Function for enabling specified interrupts.
202 *
203 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
204 * @param[in] mask Mask of interrupts to be enabled.
205 * Use @ref nrf_ipc_int_mask_t values for bit masking.
206 */
207 NRF_STATIC_INLINE void nrf_ipc_int_enable(NRF_IPC_Type * p_reg, uint32_t mask);
208
209 /**
210 * @brief Function for disabling specified interrupts.
211 *
212 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
213 * @param[in] mask Mask of interrupts to be disabled.
214 * Use @ref nrf_ipc_int_mask_t values for bit masking.
215 */
216 NRF_STATIC_INLINE void nrf_ipc_int_disable(NRF_IPC_Type * p_reg, uint32_t mask);
217
218 /**
219 * @brief Function for checking if the specified interrupts are enabled.
220 *
221 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
222 * @param[in] mask Mask of interrupts to be checked.
223 * Use @ref nrf_ipc_int_mask_t values for bit masking.
224 *
225 * @return Mask of enabled interrupts.
226 */
227 NRF_STATIC_INLINE uint32_t nrf_ipc_int_enable_check(NRF_IPC_Type const * p_reg, uint32_t mask);
228
229 /**
230 * @brief Function for retrieving the state of pending interrupts of the receive event.
231 *
232 * States of pending interrupt are saved as a bitmask. First position corresponds with
233 * EVENTS_RECEIVE[0] event, second one with EVENTS_RECEIVE[1] etc.
234 * One set at particular position means that interrupt for event is pending.
235 *
236 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
237 *
238 * @return Bitmask with information about pending interrupts of EVENTS_RECEIVE[n] events.
239 * Use @ref nrf_ipc_int_mask_t values for bit masking.
240 */
241 NRF_STATIC_INLINE uint32_t nrf_ipc_int_pending_get(NRF_IPC_Type const * p_reg);
242
243 /**
244 * @brief Function for setting the DPPI subscribe configuration for a given
245 * IPC task.
246 *
247 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
248 * @param[in] task Task for which to set the configuration.
249 * @param[in] channel DPPI channel through which to subscribe events.
250 */
251 NRF_STATIC_INLINE void nrf_ipc_subscribe_set(NRF_IPC_Type * p_reg,
252 nrf_ipc_task_t task,
253 uint8_t channel);
254
255 /**
256 * @brief Function for clearing the DPPI subscribe configuration for a given
257 * IPC task.
258 *
259 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
260 * @param[in] task Task for which to clear the configuration.
261 */
262 NRF_STATIC_INLINE void nrf_ipc_subscribe_clear(NRF_IPC_Type * p_reg, nrf_ipc_task_t task);
263
264 /**
265 * @brief Function for setting the DPPI publish configuration for a given
266 * IPC event.
267 *
268 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
269 * @param[in] event Event for which to set the configuration.
270 * @param[in] channel DPPI channel through which to publish the event.
271 */
272 NRF_STATIC_INLINE void nrf_ipc_publish_set(NRF_IPC_Type * p_reg,
273 nrf_ipc_event_t event,
274 uint8_t channel);
275
276 /**
277 * @brief Function for clearing the DPPI publish configuration for a given
278 * IPC event.
279 *
280 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
281 * @param[in] event Event for which to clear the configuration.
282 */
283 NRF_STATIC_INLINE void nrf_ipc_publish_clear(NRF_IPC_Type * p_reg, nrf_ipc_event_t event);
284
285 /**
286 * @brief Function for setting the configuration of the specified send task.
287 *
288 * @p channels_mask bitmask must be created with @ref nrf_ipc_channel_t values:
289 * NRF_IPC_CHANNEL_0 | NRF_IPC_CHANNEL_1 | ... | NRF_IPC_CHANNEL_n
290 *
291 * @note This function overrides current configuration.
292 *
293 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
294 * @param[in] index Index of the send task.
295 * @param[in] channels_mask Bitmask specifying channels that are to be enabled for this task.
296 */
297 NRF_STATIC_INLINE void nrf_ipc_send_config_set(NRF_IPC_Type * p_reg,
298 uint8_t index,
299 uint32_t channels_mask);
300
301 /**
302 * @brief Function for getting the configuration of the specified send task.
303 *
304 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
305 * @param[in] index Index of the send event configuration.
306 *
307 * @retval Bitmask of channels enabled for this task.
308 */
309 NRF_STATIC_INLINE uint32_t nrf_ipc_send_config_get(NRF_IPC_Type * const p_reg, uint8_t index);
310
311 /**
312 * @brief Function for assigning receive event to the IPC channels.
313 *
314 * @p channels_mask bitmask must be created with @ref nrf_ipc_channel_t values:
315 * NRF_IPC_CHANNEL_0 | NRF_IPC_CHANNEL_1 | ... | NRF_IPC_CHANNEL_n
316 *
317 * @note This function overrides current configuration.
318 *
319 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
320 * @param[in] index Index of the receive event configuration.
321 * @param[in] channels_mask Bitmask with IPC channels from which the receive event
322 * will generate interrupts.
323 */
324 NRF_STATIC_INLINE void nrf_ipc_receive_config_set(NRF_IPC_Type * p_reg,
325 uint8_t index,
326 uint32_t channels_mask);
327
328 /**
329 * @brief Function for getting receive event configuration.
330 *
331 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
332 * @param[in] index Index of the receive event configuration.
333 *
334 * @return Mask of channels connected with receive event.
335 */
336 NRF_STATIC_INLINE uint32_t nrf_ipc_receive_config_get(NRF_IPC_Type * const p_reg, uint8_t index);
337
338 /**
339 * @brief Function for storing data in general purpose memory cell.
340 *
341 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
342 * @param[in] index Index of the general purpose memory cell.
343 * @param[in] data Data to be stored.
344 */
345 NRF_STATIC_INLINE void nrf_ipc_gpmem_set(NRF_IPC_Type * p_reg,
346 uint8_t index,
347 uint32_t data);
348
349 /**
350 * @brief Function for getting value of the general purpose memory cell.
351 *
352 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
353 * @param[in] index Index of the general purpose memory cell.
354 *
355 * @return Stored data.
356 */
357 NRF_STATIC_INLINE uint32_t nrf_ipc_gpmem_get(NRF_IPC_Type const * p_reg, uint8_t index);
358
359 /**
360 * @brief Function for getting SEND task by its index.
361 *
362 * @param[in] index Index of the SEND task.
363 *
364 * @return SEND task.
365 */
366 NRF_STATIC_INLINE nrf_ipc_task_t nrf_ipc_send_task_get(uint8_t index);
367
368 /**
369 * @brief Function for getting RECEIVE event by its index.
370 *
371 * @param[in] index Index of the RECEIVE event.
372 *
373 * @return RECEIVE event.
374 */
375 NRF_STATIC_INLINE nrf_ipc_event_t nrf_ipc_receive_event_get(uint8_t index);
376
377 #ifndef NRF_DECLARE_ONLY
378
nrf_ipc_task_trigger(NRF_IPC_Type * p_reg,nrf_ipc_task_t task)379 NRF_STATIC_INLINE void nrf_ipc_task_trigger(NRF_IPC_Type * p_reg, nrf_ipc_task_t task)
380 {
381 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
382 }
383
nrf_ipc_task_address_get(NRF_IPC_Type const * p_reg,nrf_ipc_task_t task)384 NRF_STATIC_INLINE uint32_t nrf_ipc_task_address_get(NRF_IPC_Type const * p_reg,
385 nrf_ipc_task_t task)
386 {
387 return ((uint32_t)p_reg + (uint32_t)task);
388 }
389
nrf_ipc_event_clear(NRF_IPC_Type * p_reg,nrf_ipc_event_t event)390 NRF_STATIC_INLINE void nrf_ipc_event_clear(NRF_IPC_Type * p_reg, nrf_ipc_event_t event)
391 {
392 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
393 }
394
nrf_ipc_event_check(NRF_IPC_Type const * p_reg,nrf_ipc_event_t event)395 NRF_STATIC_INLINE bool nrf_ipc_event_check(NRF_IPC_Type const * p_reg, nrf_ipc_event_t event)
396 {
397 return nrf_event_check(p_reg, event);
398 }
399
nrf_ipc_event_address_get(NRF_IPC_Type const * p_reg,nrf_ipc_event_t event)400 NRF_STATIC_INLINE uint32_t nrf_ipc_event_address_get(NRF_IPC_Type const * p_reg,
401 nrf_ipc_event_t event)
402 {
403 return ((uint32_t)p_reg + (uint32_t)event);
404 }
405
nrf_ipc_int_enable(NRF_IPC_Type * p_reg,uint32_t mask)406 NRF_STATIC_INLINE void nrf_ipc_int_enable(NRF_IPC_Type * p_reg, uint32_t mask)
407 {
408 p_reg->INTENSET = mask;
409 }
410
nrf_ipc_int_disable(NRF_IPC_Type * p_reg,uint32_t mask)411 NRF_STATIC_INLINE void nrf_ipc_int_disable(NRF_IPC_Type * p_reg, uint32_t mask)
412 {
413 p_reg->INTENCLR = mask;
414 }
415
nrf_ipc_int_enable_check(NRF_IPC_Type const * p_reg,uint32_t mask)416 NRF_STATIC_INLINE uint32_t nrf_ipc_int_enable_check(NRF_IPC_Type const * p_reg, uint32_t mask)
417 {
418 return p_reg->INTENSET & mask;
419 }
420
nrf_ipc_int_pending_get(NRF_IPC_Type const * p_reg)421 NRF_STATIC_INLINE uint32_t nrf_ipc_int_pending_get(NRF_IPC_Type const * p_reg)
422 {
423 return p_reg->INTPEND;
424 }
425
nrf_ipc_subscribe_set(NRF_IPC_Type * p_reg,nrf_ipc_task_t task,uint8_t channel)426 NRF_STATIC_INLINE void nrf_ipc_subscribe_set(NRF_IPC_Type * p_reg,
427 nrf_ipc_task_t task,
428 uint8_t channel)
429 {
430 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
431 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
432 }
433
nrf_ipc_subscribe_clear(NRF_IPC_Type * p_reg,nrf_ipc_task_t task)434 NRF_STATIC_INLINE void nrf_ipc_subscribe_clear(NRF_IPC_Type * p_reg, nrf_ipc_task_t task)
435 {
436 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
437 }
438
nrf_ipc_publish_set(NRF_IPC_Type * p_reg,nrf_ipc_event_t event,uint8_t channel)439 NRF_STATIC_INLINE void nrf_ipc_publish_set(NRF_IPC_Type * p_reg,
440 nrf_ipc_event_t event,
441 uint8_t channel)
442 {
443 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
444 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
445 }
446
nrf_ipc_publish_clear(NRF_IPC_Type * p_reg,nrf_ipc_event_t event)447 NRF_STATIC_INLINE void nrf_ipc_publish_clear(NRF_IPC_Type * p_reg, nrf_ipc_event_t event)
448 {
449 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
450 }
451
nrf_ipc_send_config_set(NRF_IPC_Type * p_reg,uint8_t index,uint32_t channels_mask)452 NRF_STATIC_INLINE void nrf_ipc_send_config_set(NRF_IPC_Type * p_reg,
453 uint8_t index,
454 uint32_t channels_mask)
455 {
456 p_reg->SEND_CNF[index] = channels_mask;
457 }
458
nrf_ipc_send_config_get(NRF_IPC_Type * const p_reg,uint8_t index)459 NRF_STATIC_INLINE uint32_t nrf_ipc_send_config_get(NRF_IPC_Type * const p_reg, uint8_t index)
460 {
461 return p_reg->SEND_CNF[index];
462 }
463
nrf_ipc_receive_config_set(NRF_IPC_Type * p_reg,uint8_t index,uint32_t channels_mask)464 NRF_STATIC_INLINE void nrf_ipc_receive_config_set(NRF_IPC_Type * p_reg,
465 uint8_t index,
466 uint32_t channels_mask)
467 {
468 p_reg->RECEIVE_CNF[index] = channels_mask;
469 }
470
471
nrf_ipc_receive_config_get(NRF_IPC_Type * const p_reg,uint8_t index)472 NRF_STATIC_INLINE uint32_t nrf_ipc_receive_config_get(NRF_IPC_Type * const p_reg, uint8_t index)
473 {
474 return p_reg->RECEIVE_CNF[index];
475 }
476
nrf_ipc_gpmem_set(NRF_IPC_Type * p_reg,uint8_t index,uint32_t data)477 NRF_STATIC_INLINE void nrf_ipc_gpmem_set(NRF_IPC_Type * p_reg,
478 uint8_t index,
479 uint32_t data)
480 {
481 NRFX_ASSERT(index < IPC_GPMEM_NUM);
482 p_reg->GPMEM[index] = data;
483 }
484
nrf_ipc_gpmem_get(NRF_IPC_Type const * p_reg,uint8_t index)485 NRF_STATIC_INLINE uint32_t nrf_ipc_gpmem_get(NRF_IPC_Type const * p_reg, uint8_t index)
486 {
487 NRFX_ASSERT(index < IPC_GPMEM_NUM);
488 return p_reg->GPMEM[index];
489 }
490
nrf_ipc_send_task_get(uint8_t index)491 NRF_STATIC_INLINE nrf_ipc_task_t nrf_ipc_send_task_get(uint8_t index)
492 {
493 NRFX_ASSERT(index < IPC_CH_NUM);
494 return (nrf_ipc_task_t)(NRFX_OFFSETOF(NRF_IPC_Type, TASKS_SEND[index]));
495 }
496
nrf_ipc_receive_event_get(uint8_t index)497 NRF_STATIC_INLINE nrf_ipc_event_t nrf_ipc_receive_event_get(uint8_t index)
498 {
499 NRFX_ASSERT(index < IPC_CH_NUM);
500 return (nrf_ipc_event_t)(NRFX_OFFSETOF(NRF_IPC_Type, EVENTS_RECEIVE[index]));
501 }
502
503 #endif // NRF_DECLARE_ONLY
504
505 /** @} */
506
507 #ifdef __cplusplus
508 }
509 #endif
510
511 #endif // NRF_IPC_H__
512
