1 /*
2 * Copyright (c) 2023 - 2024, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_HSFLL_H__
35 #define NRF_HSFLL_H__
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /**
44 * @defgroup nrf_hsfll_hal HSFLL HAL
45 * @{
46 * @ingroup nrf_clock
47 * @brief Hardware access layer for managing the High Speed Frequency Locked Loop (HSFLL).
48 */
49
50 #if defined(HSFLL_CLOCKCTRL_DITHERING_INITVALUE_Msk) || defined(__NRFX_DOXYGEN__)
51 /** @brief Symbol indicating whether initial value for clock dithering configuration is present. */
52 #define NRF_HSFLL_HAS_DITHERING_INITVALUE 1
53 #else
54 #define NRF_HSFLL_HAS_DITHERING_INITVALUE 0
55 #endif
56
57 #if defined(HSFLL_CLOCKCTRL_DITHERINIT_ResetValue) || defined(__NRFX_DOXYGEN__)
58 /** @brief Symbol indicating whether initial value for clock dithering seed configuration is present. */
59 #define NRF_HSFLL_HAS_DITHERINIT 1
60 #else
61 #define NRF_HSFLL_HAS_DITHERINIT 0
62 #endif
63
64 /** @brief HSFLL tasks. */
65 typedef enum
66 {
67 NRF_HSFLL_TASK_START = offsetof(NRF_HSFLL_Type, TASKS_START), ///< Start the HSFLL.
68 NRF_HSFLL_TASK_STOP = offsetof(NRF_HSFLL_Type, TASKS_STOP), ///< Stop the HSFLL.
69 NRF_HSFLL_TASK_FREQ_MEAS = offsetof(NRF_HSFLL_Type, TASKS_FREQMEAS), ///< Start frequency measurement in software-controlled mode.
70 NRF_HSFLL_TASK_FREQ_CHANGE = offsetof(NRF_HSFLL_Type, TASKS_FREQCHANGE), ///< Trigger frequency change.
71 } nrf_hsfll_task_t;
72
73 /** @brief HSFLL events. */
74 typedef enum
75 {
76 NRF_HSFLL_EVENT_STARTED = offsetof(NRF_HSFLL_Type, EVENTS_STARTED), ///< HSFLL started.
77 NRF_HSFLL_EVENT_STOPPED = offsetof(NRF_HSFLL_Type, EVENTS_STOPPED), ///< HSFLL stopped.
78 NRF_HSFLL_EVENT_FREQM_DONE = offsetof(NRF_HSFLL_Type, EVENTS_FREQMDONE), ///< HSFLL frequency measurement done.
79 NRF_HSFLL_EVENT_FREQ_CHANGED = offsetof(NRF_HSFLL_Type, EVENTS_FREQCHANGED), ///< HSFLL frequency change done.
80 } nrf_hsfll_event_t;
81
82 /** @brief HSFLL clock status operating modes. */
83 typedef enum
84 {
85 NRF_HSFLL_MODE_STATUS_OPEN_LOOP = HSFLL_CLOCKSTATUS_MODE_OpenLoop, ///< Open loop mode.
86 NRF_HSFLL_MODE_STATUS_CLOSED_LOOP = HSFLL_CLOCKSTATUS_MODE_ClosedLoop, ///< Closed loop mode.
87 NRF_HSFLL_MODE_STATUS_BYPASS = HSFLL_CLOCKSTATUS_MODE_Bypass, ///< Bypass mode.
88 } nrf_hsfll_mode_status_t;
89
90 /** @brief HSFLL clock status. */
91 typedef struct
92 {
93 nrf_hsfll_mode_status_t mode; ///< HSFLL operating mode.
94 bool override; ///< HSFLL override mode is enabled.
95 bool accuracy; ///< Clock accurracy is within 2%.
96 bool locked; ///< HSFLL locked to reference clock.
97 } nrf_hsfll_status_clk_t;
98
99 /** @brief HSFLL frequency measurements errors. */
100 typedef struct
101 {
102 bool error; ///< Trim error status. True if outside limit, false if within.
103 bool trim_underflow; ///< Underflow error status. True if outside limit, false if within.
104 bool trim_overflow; ///< Overflow error status. True if outside limit, false if within.
105 } nrf_hsfll_freqm_error_t;
106
107 /** @brief HSFLL clock control operating mode settings. */
108 typedef enum
109 {
110 NRF_HSFLL_MODE_CTRL_AUTO = HSFLL_CLOCKCTRL_MODE_MODE_Auto, ///< The PCGC controls the mode automatically.
111 NRF_HSFLL_MODE_CTRL_OPEN_LOOP = HSFLL_CLOCKCTRL_MODE_MODE_OpenLoop, ///< Open loop mode.
112 NRF_HSFLL_MODE_CTRL_CLOSED_LOOP = HSFLL_CLOCKCTRL_MODE_MODE_ClosedLoop, ///< Closed loop mode.
113 NRF_HSFLL_MODE_CTRL_BYPASS = HSFLL_CLOCKCTRL_MODE_MODE_Bypass, ///< Bypass mode.
114 } nrf_hsfll_mode_ctrl_t;
115
116 /** @brief HSFLL clock control. */
117 typedef struct
118 {
119 nrf_hsfll_mode_ctrl_t mode; ///< HSFLL operating mode.
120 bool override; ///< HSFLL override mode. True if enabled, false otherwise.
121 } nrf_hsfll_clkctrl_t;
122
123 /** @brief HSFLL clock dithering configuration. */
124 typedef struct
125 {
126 uint8_t cyclecount; ///< Cycle count configuration for clock dithering.
127 uint8_t maxoffset; ///< Maximum offset configuration for clock dithering.
128 #if NRF_HSFLL_HAS_DITHERING_INITVALUE
129 uint16_t initvalue; ///< Initial value for the clock dithering.
130 #endif
131 bool enable; ///< Enable the clock dithering.
132 } nrf_hsfll_dithering_t;
133
134 /** @brief HSFLL clock sleep configuration. */
135 typedef struct
136 {
137 bool mode; ///< Power down the HSFLL core. True if powered down, false if in normal mode.
138 bool retain; ///< Retain all inputs while powered down. True if retention is enabled, false otherwise.
139 } nrf_hsfll_sleep_t;
140
141 /** @brief HSFLL trims configuration. */
142 typedef struct
143 {
144 uint16_t coarse; ///< Coarse frequance trimming.
145 uint16_t fine; ///< Fine frequency trimming.
146 uint8_t vsup; ///< Internal regulator voltage supply level trimming.
147 } nrf_hsfll_trim_t;
148
149 /**
150 * @brief Function for getting the address of the specified task.
151 *
152 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
153 * @param[in] task HSFLL task.
154 *
155 * @return Address of the requested task register.
156 */
157 NRF_STATIC_INLINE uint32_t nrf_hsfll_task_address_get(NRF_HSFLL_Type const * p_reg,
158 nrf_hsfll_task_t task);
159
160 /**
161 * @brief Function for triggering the specified task.
162 *
163 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
164 * @param[in] task Task to be activated.
165 */
166 NRF_STATIC_INLINE void nrf_hsfll_task_trigger(NRF_HSFLL_Type * p_reg, nrf_hsfll_task_t task);
167
168 /**
169 * @brief Function for retrieving the address of the specified event.
170 *
171 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
172 * @param[in] event HSFLL event.
173 *
174 * @return Address of the specified event register.
175 */
176 NRF_STATIC_INLINE uint32_t nrf_hsfll_event_address_get(NRF_HSFLL_Type const * p_reg,
177 nrf_hsfll_event_t event);
178
179 /**
180 * @brief Function for clearing the specified event.
181 *
182 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
183 * @param[in] event Event to be cleared.
184 */
185 NRF_STATIC_INLINE void nrf_hsfll_event_clear(NRF_HSFLL_Type * p_reg, nrf_hsfll_event_t event);
186
187 /**
188 * @brief Function for retrieving the state of the specified event.
189 *
190 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
191 * @param[in] event Event to be checked.
192 *
193 * @retval true The event has been generated.
194 * @retval false The event has not been generated.
195 */
196 NRF_STATIC_INLINE bool nrf_hsfll_event_check(NRF_HSFLL_Type const * p_reg,
197 nrf_hsfll_event_t event);
198
199 /**
200 * @brief Function for getting the HSFLL status.
201 *
202 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
203 * @param[out] p_status Pointer to the structure to be filled with the HSFLL status.
204 */
205 NRF_STATIC_INLINE void nrf_hsfll_status_clk_get(NRF_HSFLL_Type const * p_reg,
206 nrf_hsfll_status_clk_t * p_status);
207
208 /**
209 * @brief Function for checking whether the HSFLL frequency measurement is completed.
210 *
211 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
212 *
213 * @retval true The frequency measurement is completed.
214 * @retval false The frequency measurement is in progress.
215 */
216 NRF_STATIC_INLINE bool nrf_hsfll_freqm_done_check(NRF_HSFLL_Type const * p_reg);
217
218 /**
219 * @brief Function for getting HSFLL frequency measurement errors.
220 *
221 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
222 * @param[out] p_error Pointer to the structure to be filled with HSFLL frequency measurement
223 * errors.
224 */
225 NRF_STATIC_INLINE void nrf_hsfll_freqm_error_get(NRF_HSFLL_Type const * p_reg,
226 nrf_hsfll_freqm_error_t * p_error);
227
228 /**
229 * @brief Function for getting HSFLL frequency measurement.
230 *
231 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
232 *
233 * @return The last frequency measurement value. Measures the number of reference clock cycles.
234 */
235 NRF_STATIC_INLINE uint32_t nrf_hsfll_freqm_meas_get(NRF_HSFLL_Type const * p_reg);
236
237 /**
238 * @brief Function for setting HSFLL clock control mode settings.
239 *
240 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
241 * @param[in] p_clkctrl Pointer to the structure with new HSFLL clock control mode settings.
242 */
243 NRF_STATIC_INLINE void nrf_hsfll_clkctrl_mode_set(NRF_HSFLL_Type * p_reg,
244 nrf_hsfll_clkctrl_t const * p_clkctrl);
245
246 /**
247 * @brief Function for getting HSFLL clock control mode settings.
248 *
249 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
250 * @param[out] p_clkctrl Pointer to the structure to be filled with HSFLL clock control settings.
251 */
252 NRF_STATIC_INLINE void nrf_hsfll_clkctrl_mode_get(NRF_HSFLL_Type const * p_reg,
253 nrf_hsfll_clkctrl_t * p_clkctrl);
254
255 /**
256 * @brief Function for setting HSFLL clock dithering configuration.
257 *
258 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
259 * @param[in] p_config Pointer to the structure with new HSFLL clock dithering configuration.
260 */
261 NRF_STATIC_INLINE void nrf_hsfll_clkctrl_dithering_set(NRF_HSFLL_Type * p_reg,
262 nrf_hsfll_dithering_t const * p_config);
263
264 /**
265 * @brief Function for getting HSFLL clock dithering configuration.
266 *
267 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
268 * @param[out] p_config Pointer to the structure to be filled with HSFLL clock dithering
269 * configuration.
270 */
271 NRF_STATIC_INLINE void nrf_hsfll_clkctrl_dithering_get(NRF_HSFLL_Type const * p_reg,
272 nrf_hsfll_dithering_t * p_config);
273
274 /**
275 * @brief Function for setting HSFLL frequency multiplier.
276 *
277 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
278 * @param[in] multiplier Value of new multiplier. Valid @c multiplier range is from 4 to 25.
279 */
280 NRF_STATIC_INLINE void nrf_hsfll_clkctrl_mult_set(NRF_HSFLL_Type * p_reg, uint32_t multiplier);
281
282 /**
283 * @brief Function for getting HSFLL frequency multiplier.
284 *
285 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
286 *
287 * @return Current value of frequency multiplier used by HSFLL.
288 */
289 NRF_STATIC_INLINE uint32_t nrf_hsfll_clkctrl_mult_get(NRF_HSFLL_Type const * p_reg);
290
291 /**
292 * @brief Function for setting HSFLL clock sleep configuration.
293 *
294 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
295 * @param[in] p_config Pointer to the structure with new HSFLL clock sleep configuration.
296 */
297 NRF_STATIC_INLINE void nrf_hsfll_clkctrl_sleep_set(NRF_HSFLL_Type * p_reg,
298 nrf_hsfll_sleep_t const * p_config);
299
300 /**
301 * @brief Function for getting HSFLL clock sleep configuration.
302 *
303 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
304 * @param[out] p_config Pointer to the structure to be filled with HSFLL clock sleep configuration.
305 */
306 NRF_STATIC_INLINE void nrf_hsfll_clkctrl_sleep_get(NRF_HSFLL_Type const * p_reg,
307 nrf_hsfll_sleep_t * p_config);
308
309 /**
310 * @brief Function for enabling or disabling the retention of HSFLL fine trim control.
311 *
312 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
313 * @param[in] retain True if the fine trim control is to be retained when HSFLL goes to open-loop
314 * mode, false otherwise.
315 */
316 NRF_STATIC_INLINE void nrf_hsfll_clkctrl_retainfinetrim_enable_set(NRF_HSFLL_Type * p_reg,
317 bool retain);
318
319 /**
320 * @brief Function for enabling or disabling the override of the HSFLL LOCKED signal.
321 *
322 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
323 * @param[in] override True if the override is to be enabled, false otherwise.
324 */
325 NRF_STATIC_INLINE void nrf_hsfll_clkctrl_overridelocked_enable_set(NRF_HSFLL_Type * p_reg,
326 bool override);
327
328 #if NRF_HSFLL_HAS_DITHERINIT
329 /**
330 * @brief Function for setting the configurable seed of HSFLL clock dithering.
331 *
332 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
333 * @param[in] seed 32-bit initial value for the PRBS.
334 */
335 NRF_STATIC_INLINE void nrf_hsfll_clkctrl_dither_init_set(NRF_HSFLL_Type * p_reg, uint32_t seed);
336 #endif // NRF_HSFLL_HAS_DITHERINIT
337
338 /**
339 * @brief Function for enabling or disabling lock for mirrored registers.
340 *
341 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
342 * @param[in] enable True if the lock is to be enabled, false otherwise.
343 */
344 NRF_STATIC_INLINE void nrf_hsfll_mirror_lock_set(NRF_HSFLL_Type * p_reg, bool enable);
345
346 /**
347 * @brief Function to setup trims configuration.
348 *
349 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
350 * @param[in] p_trim Pointer to the structure with new HSFLL trim configuration.
351 */
352 NRF_STATIC_INLINE void nrf_hsfll_trim_set(NRF_HSFLL_Type * p_reg,
353 nrf_hsfll_trim_t const * p_trim);
354
355 /**
356 * @brief Function to getting trims configuration.
357 *
358 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
359 * @param[in] p_trim Pointer to the structure to be filled with HSFLL trim configuration.
360 */
361 NRF_STATIC_INLINE void nrf_hsfll_trim_get(NRF_HSFLL_Type const * p_reg,
362 nrf_hsfll_trim_t * p_trim);
363
364 #ifndef NRF_DECLARE_ONLY
365
nrf_hsfll_task_address_get(NRF_HSFLL_Type const * p_reg,nrf_hsfll_task_t task)366 NRF_STATIC_INLINE uint32_t nrf_hsfll_task_address_get(NRF_HSFLL_Type const * p_reg,
367 nrf_hsfll_task_t task)
368 {
369 return nrf_task_event_address_get(p_reg, task);
370 }
371
nrf_hsfll_task_trigger(NRF_HSFLL_Type * p_reg,nrf_hsfll_task_t task)372 NRF_STATIC_INLINE void nrf_hsfll_task_trigger(NRF_HSFLL_Type * p_reg, nrf_hsfll_task_t task)
373 {
374 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
375 }
376
nrf_hsfll_event_address_get(NRF_HSFLL_Type const * p_reg,nrf_hsfll_event_t event)377 NRF_STATIC_INLINE uint32_t nrf_hsfll_event_address_get(NRF_HSFLL_Type const * p_reg,
378 nrf_hsfll_event_t event)
379 {
380 return nrf_task_event_address_get(p_reg, event);
381 }
382
nrf_hsfll_event_clear(NRF_HSFLL_Type * p_reg,nrf_hsfll_event_t event)383 NRF_STATIC_INLINE void nrf_hsfll_event_clear(NRF_HSFLL_Type * p_reg, nrf_hsfll_event_t event)
384 {
385 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
386 nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
387 }
388
nrf_hsfll_event_check(NRF_HSFLL_Type const * p_reg,nrf_hsfll_event_t event)389 NRF_STATIC_INLINE bool nrf_hsfll_event_check(NRF_HSFLL_Type const * p_reg,
390 nrf_hsfll_event_t event)
391 {
392 return nrf_event_check(p_reg, event);
393 }
394
nrf_hsfll_status_clk_get(NRF_HSFLL_Type const * p_reg,nrf_hsfll_status_clk_t * p_status)395 NRF_STATIC_INLINE void nrf_hsfll_status_clk_get(NRF_HSFLL_Type const * p_reg,
396 nrf_hsfll_status_clk_t * p_status)
397 {
398 NRFX_ASSERT(p_status);
399 uint32_t reg = p_reg->CLOCKSTATUS;
400
401 p_status->mode =
402 (nrf_hsfll_mode_status_t)((reg & HSFLL_CLOCKSTATUS_MODE_Msk) >> HSFLL_CLOCKSTATUS_MODE_Pos);
403 p_status->override = ((reg & HSFLL_CLOCKSTATUS_OVERRIDE_Msk)
404 >> HSFLL_CLOCKSTATUS_OVERRIDE_Pos) ==
405 HSFLL_CLOCKSTATUS_OVERRIDE_Enabled;
406 p_status->accuracy = ((reg & HSFLL_CLOCKSTATUS_ACCURACY_Msk)
407 >> HSFLL_CLOCKSTATUS_ACCURACY_Pos) ==
408 HSFLL_CLOCKSTATUS_ACCURACY_WithinLimit;
409 p_status->locked = ((reg & HSFLL_CLOCKSTATUS_LOCKED_Msk)
410 >> HSFLL_CLOCKSTATUS_LOCKED_Pos) ==
411 HSFLL_CLOCKSTATUS_LOCKED_Locked;
412 }
413
nrf_hsfll_freqm_done_check(NRF_HSFLL_Type const * p_reg)414 NRF_STATIC_INLINE bool nrf_hsfll_freqm_done_check(NRF_HSFLL_Type const * p_reg)
415 {
416 return ((p_reg->FREQM.DONE & HSFLL_FREQM_DONE_DONE_Msk) >> HSFLL_FREQM_DONE_DONE_Pos) ==
417 HSFLL_FREQM_DONE_DONE_Completed;
418 }
419
nrf_hsfll_freqm_error_get(NRF_HSFLL_Type const * p_reg,nrf_hsfll_freqm_error_t * p_error)420 NRF_STATIC_INLINE void nrf_hsfll_freqm_error_get(NRF_HSFLL_Type const * p_reg,
421 nrf_hsfll_freqm_error_t * p_error)
422 {
423 NRFX_ASSERT(p_error);
424 p_error->error =
425 ((p_reg->FREQM.ERROR & HSFLL_FREQM_ERROR_ERROR_Msk) >> HSFLL_FREQM_ERROR_ERROR_Pos) ==
426 HSFLL_FREQM_ERROR_ERROR_OutsideLimit;
427 p_error->trim_underflow = ((p_reg->FREQM.ERROR & HSFLL_FREQM_ERROR_TRIMUNDERFLOW_Msk)
428 >> HSFLL_FREQM_ERROR_TRIMUNDERFLOW_Pos) ==
429 HSFLL_FREQM_ERROR_TRIMUNDERFLOW_OutsideLimit;
430 p_error->trim_overflow = ((p_reg->FREQM.ERROR & HSFLL_FREQM_ERROR_TRIMOVERFLOW_Msk)
431 >> HSFLL_FREQM_ERROR_TRIMOVERFLOW_Pos) ==
432 HSFLL_FREQM_ERROR_TRIMOVERFLOW_OutsideLimit;
433 }
434
nrf_hsfll_freqm_meas_get(NRF_HSFLL_Type const * p_reg)435 NRF_STATIC_INLINE uint32_t nrf_hsfll_freqm_meas_get(NRF_HSFLL_Type const * p_reg)
436 {
437 return (p_reg->FREQM.MEAS & HSFLL_FREQM_MEAS_VALUE_Msk) >> HSFLL_FREQM_MEAS_VALUE_Pos;
438 }
439
nrf_hsfll_clkctrl_mode_set(NRF_HSFLL_Type * p_reg,nrf_hsfll_clkctrl_t const * p_clkctrl)440 NRF_STATIC_INLINE void nrf_hsfll_clkctrl_mode_set(NRF_HSFLL_Type * p_reg,
441 nrf_hsfll_clkctrl_t const * p_clkctrl)
442 {
443 NRFX_ASSERT(p_clkctrl);
444 p_reg->CLOCKCTRL.MODE = ((p_clkctrl->mode << HSFLL_CLOCKCTRL_MODE_MODE_Pos) &
445 HSFLL_CLOCKCTRL_MODE_MODE_Msk) |
446 (((p_clkctrl->override ?
447 HSFLL_CLOCKCTRL_MODE_OVERRIDE_Enabled :
448 HSFLL_CLOCKCTRL_MODE_OVERRIDE_Disabled)
449 << HSFLL_CLOCKCTRL_MODE_OVERRIDE_Pos) &
450 HSFLL_CLOCKCTRL_MODE_OVERRIDE_Msk);
451 }
452
nrf_hsfll_clkctrl_mode_get(NRF_HSFLL_Type const * p_reg,nrf_hsfll_clkctrl_t * p_clkctrl)453 NRF_STATIC_INLINE void nrf_hsfll_clkctrl_mode_get(NRF_HSFLL_Type const * p_reg,
454 nrf_hsfll_clkctrl_t * p_clkctrl)
455 {
456 NRFX_ASSERT(p_clkctrl);
457 uint32_t reg = p_reg->CLOCKCTRL.MODE;
458
459 p_clkctrl->mode =
460 (nrf_hsfll_mode_ctrl_t)((reg & HSFLL_CLOCKCTRL_MODE_MODE_Msk)
461 >> HSFLL_CLOCKCTRL_MODE_MODE_Pos);
462 p_clkctrl->override = ((reg & HSFLL_CLOCKCTRL_MODE_OVERRIDE_Msk)
463 >> HSFLL_CLOCKCTRL_MODE_OVERRIDE_Pos) ==
464 HSFLL_CLOCKCTRL_MODE_OVERRIDE_Enabled;
465 }
466
nrf_hsfll_clkctrl_dithering_set(NRF_HSFLL_Type * p_reg,nrf_hsfll_dithering_t const * p_config)467 NRF_STATIC_INLINE void nrf_hsfll_clkctrl_dithering_set(NRF_HSFLL_Type * p_reg,
468 nrf_hsfll_dithering_t const * p_config)
469 {
470 NRFX_ASSERT(p_config);
471 p_reg->CLOCKCTRL.DITHERING =
472 #if NRF_HSFLL_HAS_DITHERING_INITVALUE
473 ((p_config->initvalue << HSFLL_CLOCKCTRL_DITHERING_INITVALUE_Pos) &
474 HSFLL_CLOCKCTRL_DITHERING_INITVALUE_Msk) |
475 #endif
476 ((p_config->cyclecount << HSFLL_CLOCKCTRL_DITHERING_CYCLECOUNT_Pos) &
477 HSFLL_CLOCKCTRL_DITHERING_CYCLECOUNT_Msk) |
478 ((p_config->maxoffset << HSFLL_CLOCKCTRL_DITHERING_MAXOFFSET_Pos) &
479 HSFLL_CLOCKCTRL_DITHERING_MAXOFFSET_Msk) |
480 (((p_config->enable ?
481 HSFLL_CLOCKCTRL_DITHERING_EN_Enabled :
482 HSFLL_CLOCKCTRL_DITHERING_EN_Disabled) << HSFLL_CLOCKCTRL_DITHERING_EN_Pos) &
483 HSFLL_CLOCKCTRL_DITHERING_EN_Msk);
484 }
485
nrf_hsfll_clkctrl_dithering_get(NRF_HSFLL_Type const * p_reg,nrf_hsfll_dithering_t * p_config)486 NRF_STATIC_INLINE void nrf_hsfll_clkctrl_dithering_get(NRF_HSFLL_Type const * p_reg,
487 nrf_hsfll_dithering_t * p_config)
488 {
489 NRFX_ASSERT(p_config);
490 p_config->cyclecount = (p_reg->CLOCKCTRL.MODE & HSFLL_CLOCKCTRL_DITHERING_CYCLECOUNT_Msk)
491 >> HSFLL_CLOCKCTRL_DITHERING_CYCLECOUNT_Pos;
492 p_config->maxoffset = (p_reg->CLOCKCTRL.MODE & HSFLL_CLOCKCTRL_DITHERING_MAXOFFSET_Msk)
493 >> HSFLL_CLOCKCTRL_DITHERING_MAXOFFSET_Pos;
494 p_config->enable = ((p_reg->CLOCKCTRL.MODE & HSFLL_CLOCKCTRL_DITHERING_EN_Msk)
495 >> HSFLL_CLOCKCTRL_DITHERING_MAXOFFSET_Pos) ==
496 HSFLL_CLOCKCTRL_DITHERING_EN_Enabled;
497 #if NRF_HSFLL_HAS_DITHERING_INITVALUE
498 p_config->initvalue = (p_reg->CLOCKCTRL.MODE & HSFLL_CLOCKCTRL_DITHERING_INITVALUE_Msk)
499 >> HSFLL_CLOCKCTRL_DITHERING_INITVALUE_Pos;
500 #endif
501 }
502
nrf_hsfll_clkctrl_mult_set(NRF_HSFLL_Type * p_reg,uint32_t multiplier)503 NRF_STATIC_INLINE void nrf_hsfll_clkctrl_mult_set(NRF_HSFLL_Type * p_reg,
504 uint32_t multiplier)
505 {
506 p_reg->CLOCKCTRL.MULT = (multiplier << HSFLL_CLOCKCTRL_MULT_VAL_Pos) &
507 HSFLL_CLOCKCTRL_MULT_VAL_Msk;
508 }
509
nrf_hsfll_clkctrl_mult_get(NRF_HSFLL_Type const * p_reg)510 NRF_STATIC_INLINE uint32_t nrf_hsfll_clkctrl_mult_get(NRF_HSFLL_Type const * p_reg)
511 {
512 return (p_reg->CLOCKCTRL.MULT & HSFLL_CLOCKCTRL_MULT_VAL_Msk) >> HSFLL_CLOCKCTRL_MULT_VAL_Pos;
513 }
514
nrf_hsfll_clkctrl_sleep_set(NRF_HSFLL_Type * p_reg,nrf_hsfll_sleep_t const * p_config)515 NRF_STATIC_INLINE void nrf_hsfll_clkctrl_sleep_set(NRF_HSFLL_Type * p_reg,
516 nrf_hsfll_sleep_t const * p_config)
517 {
518 NRFX_ASSERT(p_config);
519 p_reg->CLOCKCTRL.SLEEP = (((p_config->mode ?
520 HSFLL_CLOCKCTRL_SLEEP_MODE_Sleep :
521 HSFLL_CLOCKCTRL_SLEEP_MODE_Normal)
522 << HSFLL_CLOCKCTRL_SLEEP_MODE_Pos) &
523 HSFLL_CLOCKCTRL_SLEEP_MODE_Msk) |
524 (((p_config->retain ?
525 HSFLL_CLOCKCTRL_SLEEP_RETAIN_Enabled :
526 HSFLL_CLOCKCTRL_SLEEP_RETAIN_Disabled)
527 << HSFLL_CLOCKCTRL_SLEEP_RETAIN_Pos) &
528 HSFLL_CLOCKCTRL_SLEEP_RETAIN_Msk);
529 }
530
nrf_hsfll_clkctrl_sleep_get(NRF_HSFLL_Type const * p_reg,nrf_hsfll_sleep_t * p_config)531 NRF_STATIC_INLINE void nrf_hsfll_clkctrl_sleep_get(NRF_HSFLL_Type const * p_reg,
532 nrf_hsfll_sleep_t * p_config)
533 {
534 NRFX_ASSERT(p_config);
535 p_config->mode = ((p_reg->CLOCKCTRL.SLEEP & HSFLL_CLOCKCTRL_SLEEP_MODE_Msk)
536 >> HSFLL_CLOCKCTRL_SLEEP_MODE_Pos) == HSFLL_CLOCKCTRL_SLEEP_MODE_Sleep;
537 p_config->retain = ((p_reg->CLOCKCTRL.SLEEP & HSFLL_CLOCKCTRL_SLEEP_RETAIN_Msk)
538 >> HSFLL_CLOCKCTRL_SLEEP_RETAIN_Pos) ==
539 HSFLL_CLOCKCTRL_SLEEP_RETAIN_Enabled;
540 }
541
nrf_hsfll_clkctrl_retainfinetrim_enable_set(NRF_HSFLL_Type * p_reg,bool retain)542 NRF_STATIC_INLINE void nrf_hsfll_clkctrl_retainfinetrim_enable_set(NRF_HSFLL_Type * p_reg,
543 bool retain)
544 {
545 p_reg->CLOCKCTRL.RETAINFINETRIM = ((retain ?
546 HSFLL_CLOCKCTRL_RETAINFINETRIM_RETAIN_Retain :
547 HSFLL_CLOCKCTRL_RETAINFINETRIM_RETAIN_NoRetain)
548 << HSFLL_CLOCKCTRL_RETAINFINETRIM_RETAIN_Pos) &
549 HSFLL_CLOCKCTRL_RETAINFINETRIM_RETAIN_Msk;
550 }
551
nrf_hsfll_clkctrl_overridelocked_enable_set(NRF_HSFLL_Type * p_reg,bool override)552 NRF_STATIC_INLINE void nrf_hsfll_clkctrl_overridelocked_enable_set(NRF_HSFLL_Type * p_reg,
553 bool override)
554 {
555 p_reg->CLOCKCTRL.OVERRIDELOCKED = ((override ?
556 HSFLL_CLOCKCTRL_OVERRIDELOCKED_OVERRIDE_Override :
557 HSFLL_CLOCKCTRL_OVERRIDELOCKED_OVERRIDE_NoOperation)
558 << HSFLL_CLOCKCTRL_OVERRIDELOCKED_OVERRIDE_Pos) &
559 HSFLL_CLOCKCTRL_OVERRIDELOCKED_OVERRIDE_Msk;
560 }
561
562 #if NRF_HSFLL_HAS_DITHERINIT
nrf_hsfll_clkctrl_dither_init_set(NRF_HSFLL_Type * p_reg,uint32_t seed)563 NRF_STATIC_INLINE void nrf_hsfll_clkctrl_dither_init_set(NRF_HSFLL_Type * p_reg, uint32_t seed)
564 {
565 p_reg->CLOCKCTRL.DITHERINIT = (seed << HSFLL_CLOCKCTRL_DITHERINIT_SEED_Pos) &
566 HSFLL_CLOCKCTRL_DITHERINIT_SEED_Msk;
567 }
568
569 #endif // NRF_HSFLL_HAS_DITHERINIT
570
nrf_hsfll_mirror_lock_set(NRF_HSFLL_Type * p_reg,bool enable)571 NRF_STATIC_INLINE void nrf_hsfll_mirror_lock_set(NRF_HSFLL_Type * p_reg, bool enable)
572 {
573 p_reg->MIRROR = ((enable ? HSFLL_MIRROR_LOCK_Enabled : HSFLL_MIRROR_LOCK_Disabled)
574 << HSFLL_MIRROR_LOCK_Pos) & HSFLL_MIRROR_LOCK_Msk;
575 }
576
nrf_hsfll_trim_set(NRF_HSFLL_Type * p_reg,nrf_hsfll_trim_t const * p_trim)577 NRF_STATIC_INLINE void nrf_hsfll_trim_set(NRF_HSFLL_Type * p_reg,
578 nrf_hsfll_trim_t const * p_trim)
579 {
580 NRFX_ASSERT(p_trim);
581 nrf_hsfll_mirror_lock_set(p_reg, true);
582
583 p_reg->TRIM.VSUP = p_trim->vsup;
584 p_reg->TRIM.COARSE = p_trim->coarse;
585 p_reg->TRIM.FINE = p_trim->fine;
586
587 nrf_hsfll_mirror_lock_set(p_reg, false);
588 }
589
nrf_hsfll_trim_get(NRF_HSFLL_Type const * p_reg,nrf_hsfll_trim_t * p_trim)590 NRF_STATIC_INLINE void nrf_hsfll_trim_get(NRF_HSFLL_Type const * p_reg,
591 nrf_hsfll_trim_t * p_trim)
592 {
593 NRFX_ASSERT(p_trim);
594
595 p_trim->vsup = (uint8_t)p_reg->TRIM.VSUP;
596 p_trim->coarse = (uint8_t)p_reg->TRIM.COARSE;
597 p_trim->fine = (uint8_t)p_reg->TRIM.FINE;
598 }
599
600 #endif // NRF_DECLARE_ONLY
601
602 /** @} */
603
604 #ifdef __cplusplus
605 }
606 #endif
607
608 #endif // NRF_HSFLL_H__
609
