1 /*
2 * Copyright (c) 2023 - 2024, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_GRTC_H
35 #define NRF_GRTC_H
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 #if defined(LUMOS_XXAA)
44 #if defined(NRF_APPLICATION) && defined(NRF_TRUSTZONE_NONSECURE)
45 #define GRTC_IRQn GRTC_1_IRQn
46 #define GRTC_IRQHandler GRTC_1_IRQHandler
47 #elif defined(NRF_APPLICATION) && !defined(NRF_TRUSTZONE_NONSECURE)
48 #define GRTC_IRQn GRTC_2_IRQn
49 #define GRTC_IRQHandler GRTC_2_IRQHandler
50 #elif defined(NRF_FLPR)
51 #define GRTC_IRQn GRTC_0_IRQn
52 #define GRTC_IRQHandler GRTC_0_IRQHandler
53 #endif
54 #endif
55
56 #if defined(HALTIUM_XXAA)
57 #if (defined(ISA_ARM) && defined(NRF_TRUSTZONE_NONSECURE)) || defined(ISA_RISCV)
58 #define GRTC_IRQn GRTC_0_IRQn
59 #define GRTC_IRQHandler GRTC_0_IRQHandler
60 #else
61 #define GRTC_IRQn GRTC_1_IRQn
62 #define GRTC_IRQHandler GRTC_1_IRQHandler
63 #endif
64 #endif
65
66 /**
67 * @defgroup nrf_grtc_hal GRTC HAL
68 * @{
69 * @ingroup nrf_grtc
70 * @brief Hardware access layer for managing the Global Real Time Counter (GRTC) peripheral.
71 */
72
73 #if NRFX_CHECK(GRTC_PWMREGS) || defined(__NRFX_DOXYGEN__)
74 /** @brief Symbol indicating whether GRTC has PWM registers. */
75 #define NRF_GRTC_HAS_PWM 1
76 #else
77 #define NRF_GRTC_HAS_PWM 0
78 #endif
79
80 #if NRFX_CHECK(GRTC_CLKOUTREG) || defined(__NRFX_DOXYGEN__)
81 /** @brief Symbol indicating whether GRTC has clock output registers. */
82 #define NRF_GRTC_HAS_CLKOUT 1
83 #else
84 #define NRF_GRTC_HAS_CLKOUT 0
85 #endif
86
87 #if defined(GRTC_CLKCFG_CLKSEL_Msk) || defined(__NRFX_DOXYGEN__)
88 /** @brief Symbol indicating whether GRTC has clock source selection. */
89 #define NRF_GRTC_HAS_CLKSEL 1
90 #else
91 #define NRF_GRTC_HAS_CLKSEL 0
92 #endif
93
94 #if defined(GRTC_SYSCOUNTER_SYSCOUNTERL_VALUE_Msk) || defined(__NRFX_DOXYGEN__)
95 /** @brief Symbol indicating whether GRTC has multiple SYSCOUNTER registers. */
96 #define NRF_GRTC_HAS_SYSCOUNTER_ARRAY 1
97 #else
98 #define NRF_GRTC_HAS_SYSCOUNTER_ARRAY 0
99 #endif
100
101 #if defined(__NRFX_DOXYGEN__)
102 /** @brief Symbol indicating whether GRTC has RTCOUNTER. */
103 #define NRF_GRTC_HAS_RTCOUNTER 1
104 #elif !defined(NRF_GRTC_HAS_RTCOUNTER)
105 #define NRF_GRTC_HAS_RTCOUNTER 0
106 #endif
107
108 #if !defined(NRF_GRTC_HAS_EXTENDED)
109 #if defined(LUMOS_XXAA) || defined(__NRFX_DOXYGEN__)
110 /** @brief Symbol indicating whether GRTC has extended functionality. */
111 #define NRF_GRTC_HAS_EXTENDED 1
112 #else
113 #define NRF_GRTC_HAS_EXTENDED 0
114 #endif
115 #endif // !defined(NRF_GRTC_HAS_EXTENDED)
116
117 /** @brief Symbol indicating actual domain index. */
118 #define NRF_GRTC_DOMAIN_INDEX GRTC_IRQ_GROUP
119
120 /** @brief Symbol indicating actual SYSCOUNTER index. */
121 #if NRF_GRTC_HAS_SYSCOUNTER_ARRAY
122 #define GRTC_SYSCOUNTER SYSCOUNTER[NRF_GRTC_DOMAIN_INDEX]
123 #endif
124
125 /** @brief Interrupts INTEN register definition. */
126 #define GRTC_INTEN NRFX_CONCAT_2(INTEN, GRTC_IRQ_GROUP)
127 /** @brief Interrupts INTENSET register definition. */
128 #define GRTC_INTENSET NRFX_CONCAT_2(INTENSET, GRTC_IRQ_GROUP)
129 /** @brief Interrupts INTENCLR register definition. */
130 #define GRTC_INTENCLR NRFX_CONCAT_2(INTENCLR, GRTC_IRQ_GROUP)
131 /** @brief Interrupts INTPEND register definition. */
132 #define GRTC_INTPEND NRFX_CONCAT_2(INTPEND, GRTC_IRQ_GROUP)
133
134 /** @brief Main SYSCOUNTER frequency in Hz. */
135 #define NRF_GRTC_SYSCOUNTER_MAIN_FREQUENCY_HZ 1000000UL
136
137 /** @brief Number of capture/compare channels for SYSCOUNTER. */
138 #define NRF_GRTC_SYSCOUNTER_CC_COUNT GRTC_CC_MaxCount
139
140 /** @brief Bitmask of the higher 32-bits of capture/compare register for the SYSCOUNTER. */
141 #define NRF_GRTC_SYSCOUNTER_CCH_MASK GRTC_CC_CCH_CCH_Msk
142
143 /** @brief Bitmask of CCADD register for the SYSCOUNTER. */
144 #define NRF_GRTC_SYSCOUNTER_CCADD_MASK GRTC_CC_CCADD_VALUE_Msk
145
146 #if defined(GRTC_SYSCOUNTERL_VALUE_Msk) || defined(__NRFX_DOXYGEN__)
147 /** @brief Bitmask of the lower part of the SYSCOUNTER value. */
148 #define NRF_GRTC_SYSCOUNTERL_VALUE_MASK GRTC_SYSCOUNTERL_VALUE_Msk
149 #else
150 #define NRF_GRTC_SYSCOUNTERL_VALUE_MASK GRTC_SYSCOUNTER_SYSCOUNTERL_VALUE_Msk
151 #endif
152
153 #if defined(GRTC_SYSCOUNTERH_VALUE_Msk) || defined(__NRFX_DOXYGEN__)
154 /** @brief Bitmask of the higher part of the SYSCOUNTER value. */
155 #define NRF_GRTC_SYSCOUNTERH_VALUE_MASK GRTC_SYSCOUNTERH_VALUE_Msk
156 #else
157 #define NRF_GRTC_SYSCOUNTERH_VALUE_MASK GRTC_SYSCOUNTER_SYSCOUNTERH_VALUE_Msk
158 #endif
159
160 /** @brief Bitmask of the higher 32-bits of capture/compare register for the RTCOUNTER. */
161 #define NRF_GRTC_RTCOUNTER_CCH_MASK GRTC_RTCOMPAREH_VALUE_Msk
162
163 #if defined(GRTC_SYSCOUNTERH_OVERFLOW_Msk) || defined(__NRFX_DOXYGEN__)
164 /** @brief Bitmask of the OVERFLOW bit. */
165 #define NRF_GRTC_SYSCOUNTERH_OVERFLOW_MASK GRTC_SYSCOUNTERH_OVERFLOW_Msk
166 #else
167 #define NRF_GRTC_SYSCOUNTERH_OVERFLOW_MASK GRTC_SYSCOUNTER_SYSCOUNTERH_OVERFLOW_Msk
168 #endif
169
170 #if defined(GRTC_SYSCOUNTERH_BUSY_Msk) || defined(__NRFX_DOXYGEN__)
171 /** @brief Bitmask of the BUSY bit. */
172 #define NRF_GRTC_SYSCOUNTERH_BUSY_MASK GRTC_SYSCOUNTERH_BUSY_Msk
173 #else
174 #define NRF_GRTC_SYSCOUNTERH_BUSY_MASK GRTC_SYSCOUNTER_SYSCOUNTERH_BUSY_Msk
175 #endif
176
177 /** @brief Maximum value of TIMEOUT register content. */
178 #define NRF_GRTC_TIMEOUT_MAX_VALUE (GRTC_TIMEOUT_VALUE_Msk >> GRTC_TIMEOUT_VALUE_Pos)
179
180 /** @brief Maximum value of WAKETIME register content. */
181 #define NRF_GRTC_WAKETIME_MAX_VALUE (GRTC_WAKETIME_VALUE_Msk >> GRTC_WAKETIME_VALUE_Pos)
182
183 /** @brief Maximum value of CLKFASTDIV register content. */
184 #define NRF_GRTC_CLKCFG_CLKFASTDIV_MAX_VALUE GRTC_CLKCFG_CLKFASTDIV_Max
185
186 /** @brief Macro for creating the interrupt bitmask for the specified compare channel. */
187 #define NRF_GRTC_CHANNEL_INT_MASK(ch) ((uint32_t)(NRF_GRTC_INT_COMPARE0_MASK) << (ch))
188
189 /** @brief Main channel that can be used only by the owner of GRTC. */
190 #if defined(LUMOS_XXAA)
191 #if defined(ISA_RISCV)
192 #define NRF_GRTC_MAIN_CC_CHANNEL 4
193 #else
194 #define NRF_GRTC_MAIN_CC_CHANNEL 0
195 #endif
196 #else
197 #define NRF_GRTC_MAIN_CC_CHANNEL 1
198 #endif
199
200 /** @brief Bitmask of interrupt enable. */
201 #define NRF_GRTC_INTEN_MASK NRFX_BIT_MASK(GRTC_CC_MaxCount)
202
203 /** @brief Mask for all channels represented by CC channels. */
204 #define NRF_GRTC_SYSCOUNTER_ALL_CHANNELS_INT_MASK \
205 ((uint32_t)(((1 << NRF_GRTC_SYSCOUNTER_CC_COUNT) - 1) << GRTC_INTEN0_COMPARE0_Pos))
206
207 /** @brief GRTC tasks. */
208 typedef enum
209 {
210 #if NRF_GRTC_HAS_EXTENDED
211 NRF_GRTC_TASK_START = offsetof(NRF_GRTC_Type, TASKS_START), /**< Start. */
212 NRF_GRTC_TASK_STOP = offsetof(NRF_GRTC_Type, TASKS_STOP), /**< Stop. */
213 NRF_GRTC_TASK_CLEAR = offsetof(NRF_GRTC_Type, TASKS_CLEAR), /**< Clear. */
214 #endif
215 #if NRF_GRTC_HAS_PWM
216 NRF_GRTC_TASK_PWM_START = offsetof(NRF_GRTC_Type, TASKS_PWMSTART), /**< Start the PWM. */
217 NRF_GRTC_TASK_PWM_STOP = offsetof(NRF_GRTC_Type, TASKS_PWMSTOP), /**< Stop the PWM. */
218 #endif // NRF_GRTC_HAS_PWM
219 NRF_GRTC_TASK_CAPTURE_0 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[0]), /**< Capture the counter value on channel 0. */
220 NRF_GRTC_TASK_CAPTURE_1 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[1]), /**< Capture the counter value on channel 1. */
221 NRF_GRTC_TASK_CAPTURE_2 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[2]), /**< Capture the counter value on channel 2. */
222 NRF_GRTC_TASK_CAPTURE_3 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[3]), /**< Capture the counter value on channel 3. */
223 NRF_GRTC_TASK_CAPTURE_4 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[4]), /**< Capture the counter value on channel 4. */
224 NRF_GRTC_TASK_CAPTURE_5 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[5]), /**< Capture the counter value on channel 5. */
225 NRF_GRTC_TASK_CAPTURE_6 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[6]), /**< Capture the counter value on channel 6. */
226 NRF_GRTC_TASK_CAPTURE_7 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[7]), /**< Capture the counter value on channel 7. */
227 NRF_GRTC_TASK_CAPTURE_8 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[8]), /**< Capture the counter value on channel 8. */
228 NRF_GRTC_TASK_CAPTURE_9 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[9]), /**< Capture the counter value on channel 9. */
229 NRF_GRTC_TASK_CAPTURE_10 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[10]), /**< Capture the counter value on channel 10. */
230 NRF_GRTC_TASK_CAPTURE_11 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[11]), /**< Capture the counter value on channel 11. */
231 #if NRF_GRTC_SYSCOUNTER_CC_COUNT > 12
232 NRF_GRTC_TASK_CAPTURE_12 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[12]), /**< Capture the counter value on channel 12. */
233 NRF_GRTC_TASK_CAPTURE_13 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[13]), /**< Capture the counter value on channel 13. */
234 NRF_GRTC_TASK_CAPTURE_14 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[14]), /**< Capture the counter value on channel 14. */
235 NRF_GRTC_TASK_CAPTURE_15 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[15]), /**< Capture the counter value on channel 15. */
236 #endif
237 #if NRF_GRTC_SYSCOUNTER_CC_COUNT > 16
238 NRF_GRTC_TASK_CAPTURE_16 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[16]), /**< Capture the counter value on channel 16. */
239 NRF_GRTC_TASK_CAPTURE_17 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[17]), /**< Capture the counter value on channel 17. */
240 #endif
241 #if NRF_GRTC_SYSCOUNTER_CC_COUNT > 18
242 NRF_GRTC_TASK_CAPTURE_18 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[18]), /**< Capture the counter value on channel 18. */
243 #endif
244 #if NRF_GRTC_SYSCOUNTER_CC_COUNT > 19
245 NRF_GRTC_TASK_CAPTURE_19 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[19]), /**< Capture the counter value on channel 19. */
246 #endif
247 #if NRF_GRTC_SYSCOUNTER_CC_COUNT > 20
248 NRF_GRTC_TASK_CAPTURE_20 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[20]), /**< Capture the counter value on channel 20. */
249 NRF_GRTC_TASK_CAPTURE_21 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[21]), /**< Capture the counter value on channel 21. */
250 NRF_GRTC_TASK_CAPTURE_22 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[22]), /**< Capture the counter value on channel 22. */
251 NRF_GRTC_TASK_CAPTURE_23 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[23]), /**< Capture the counter value on channel 23. */
252 #endif
253 } nrf_grtc_task_t;
254
255 /** @brief GRTC events. */
256 typedef enum
257 {
258 NRF_GRTC_EVENT_COMPARE_0 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[0]), /**< Compare 0 event. */
259 NRF_GRTC_EVENT_COMPARE_1 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[1]), /**< Compare 1 event. */
260 NRF_GRTC_EVENT_COMPARE_2 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[2]), /**< Compare 2 event. */
261 NRF_GRTC_EVENT_COMPARE_3 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[3]), /**< Compare 3 event. */
262 NRF_GRTC_EVENT_COMPARE_4 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[4]), /**< Compare 4 event. */
263 NRF_GRTC_EVENT_COMPARE_5 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[5]), /**< Compare 5 event. */
264 NRF_GRTC_EVENT_COMPARE_6 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[6]), /**< Compare 6 event. */
265 NRF_GRTC_EVENT_COMPARE_7 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[7]), /**< Compare 7 event. */
266 NRF_GRTC_EVENT_COMPARE_8 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[8]), /**< Compare 8 event. */
267 NRF_GRTC_EVENT_COMPARE_9 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[9]), /**< Compare 9 event. */
268 NRF_GRTC_EVENT_COMPARE_10 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[10]), /**< Compare 10 event. */
269 NRF_GRTC_EVENT_COMPARE_11 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[11]), /**< Compare 11 event. */
270 NRF_GRTC_EVENT_COMPARE_12 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[12]), /**< Compare 12 event. */
271 #if NRF_GRTC_SYSCOUNTER_CC_COUNT > 12
272 NRF_GRTC_EVENT_COMPARE_13 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[13]), /**< Compare 13 event. */
273 NRF_GRTC_EVENT_COMPARE_14 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[14]), /**< Compare 14 event. */
274 NRF_GRTC_EVENT_COMPARE_15 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[15]), /**< Compare 15 event. */
275 #endif
276 #if NRF_GRTC_SYSCOUNTER_CC_COUNT > 16
277 NRF_GRTC_EVENT_COMPARE_16 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[16]), /**< Compare 16 event. */
278 NRF_GRTC_EVENT_COMPARE_17 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[17]), /**< Compare 17 event. */
279 #endif
280 #if NRF_GRTC_SYSCOUNTER_CC_COUNT > 18
281 NRF_GRTC_EVENT_COMPARE_18 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[18]), /**< Compare 18 event. */
282 #endif
283 #if NRF_GRTC_SYSCOUNTER_CC_COUNT > 19
284 NRF_GRTC_EVENT_COMPARE_19 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[19]), /**< Compare 19 event. */
285 #endif
286 #if NRF_GRTC_SYSCOUNTER_CC_COUNT > 20
287 NRF_GRTC_EVENT_COMPARE_20 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[20]), /**< Compare 20 event. */
288 NRF_GRTC_EVENT_COMPARE_21 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[21]), /**< Compare 21 event. */
289 NRF_GRTC_EVENT_COMPARE_22 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[22]), /**< Compare 22 event. */
290 NRF_GRTC_EVENT_COMPARE_23 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[23]), /**< Compare 23 event. */
291 #endif
292 #if NRF_GRTC_HAS_RTCOUNTER
293 NRF_GRTC_EVENT_RTCOMPARE = offsetof(NRF_GRTC_Type, EVENTS_RTCOMPARE), /**< RTCOUNTER compare event. */
294 NRF_GRTC_EVENT_RTCOMPARESYNC = offsetof(NRF_GRTC_Type, EVENTS_RTCOMPARESYNC), /**< RTCOUNTER synchronized compare event. */
295 #endif
296 NRF_GRTC_EVENT_SYSCOUNTERVALID = offsetof(NRF_GRTC_Type, EVENTS_SYSCOUNTERVALID), /**< SYSCOUNTER value valid event. */
297 #if NRF_GRTC_HAS_PWM
298 NRF_GRTC_EVENT_PWM_PERIOD_END = offsetof(NRF_GRTC_Type, EVENTS_PWMPERIODEND), /**< End of PWM period event. */
299 #endif // NRF_GRTC_HAS_PWM
300 } nrf_grtc_event_t;
301
302 #if NRF_GRTC_HAS_RTCOUNTER
303 /** @brief Types of GRTC shortcuts. */
304 typedef enum
305 {
306 NRF_GRTC_SHORT_RTCOMPARE_CLEAR_MASK = GRTC_SHORTS_RTCOMPARE_CLEAR_Msk, /**< Shortcut between RTCOMPARE event and CLEAR task. */
307 } nrf_grtc_short_mask_t;
308 #endif
309
310 /** @brief Types of GRTC CC references. */
311 typedef enum
312 {
313 NRF_GRTC_CC_ADD_REFERENCE_SYSCOUNTER = GRTC_CC_CCADD_REFERENCE_SYSCOUNTER, /**< The SYSCOUNTER register's content will be used as the reference. */
314 NRF_GRTC_CC_ADD_REFERENCE_CC = GRTC_CC_CCADD_REFERENCE_CC /**< The CC[n] register's content will be used as the reference. */
315 } nrf_grtc_cc_add_reference_t;
316
317 /** @brief GRTC interrupts. */
318 typedef enum
319 {
320 NRF_GRTC_INT_COMPARE0_MASK = GRTC_INTENSET0_COMPARE0_Msk, /**< GRTC interrupt from compare event on channel 0. */
321 NRF_GRTC_INT_COMPARE1_MASK = GRTC_INTENSET0_COMPARE1_Msk, /**< GRTC interrupt from compare event on channel 1. */
322 NRF_GRTC_INT_COMPARE2_MASK = GRTC_INTENSET0_COMPARE2_Msk, /**< GRTC interrupt from compare event on channel 2. */
323 NRF_GRTC_INT_COMPARE3_MASK = GRTC_INTENSET0_COMPARE3_Msk, /**< GRTC interrupt from compare event on channel 3. */
324 NRF_GRTC_INT_COMPARE4_MASK = GRTC_INTENSET0_COMPARE4_Msk, /**< GRTC interrupt from compare event on channel 4. */
325 NRF_GRTC_INT_COMPARE5_MASK = GRTC_INTENSET0_COMPARE5_Msk, /**< GRTC interrupt from compare event on channel 5. */
326 NRF_GRTC_INT_COMPARE6_MASK = GRTC_INTENSET0_COMPARE6_Msk, /**< GRTC interrupt from compare event on channel 6. */
327 NRF_GRTC_INT_COMPARE7_MASK = GRTC_INTENSET0_COMPARE7_Msk, /**< GRTC interrupt from compare event on channel 7. */
328 NRF_GRTC_INT_COMPARE8_MASK = GRTC_INTENSET0_COMPARE8_Msk, /**< GRTC interrupt from compare event on channel 8. */
329 NRF_GRTC_INT_COMPARE9_MASK = GRTC_INTENSET0_COMPARE9_Msk, /**< GRTC interrupt from compare event on channel 9. */
330 NRF_GRTC_INT_COMPARE10_MASK = GRTC_INTENSET0_COMPARE10_Msk, /**< GRTC interrupt from compare event on channel 10. */
331 NRF_GRTC_INT_COMPARE11_MASK = GRTC_INTENSET0_COMPARE11_Msk, /**< GRTC interrupt from compare event on channel 11. */
332 #if NRF_GRTC_SYSCOUNTER_CC_COUNT > 12
333 NRF_GRTC_INT_COMPARE12_MASK = GRTC_INTENSET0_COMPARE12_Msk, /**< GRTC interrupt from compare event on channel 12. */
334 NRF_GRTC_INT_COMPARE13_MASK = GRTC_INTENSET0_COMPARE13_Msk, /**< GRTC interrupt from compare event on channel 13. */
335 NRF_GRTC_INT_COMPARE14_MASK = GRTC_INTENSET0_COMPARE14_Msk, /**< GRTC interrupt from compare event on channel 14. */
336 NRF_GRTC_INT_COMPARE15_MASK = GRTC_INTENSET0_COMPARE15_Msk, /**< GRTC interrupt from compare event on channel 15. */
337 #endif
338 #if NRF_GRTC_SYSCOUNTER_CC_COUNT > 16
339 NRF_GRTC_INT_COMPARE16_MASK = GRTC_INTENSET0_COMPARE16_Msk, /**< GRTC interrupt from compare event on channel 16. */
340 NRF_GRTC_INT_COMPARE17_MASK = GRTC_INTENSET0_COMPARE17_Msk, /**< GRTC interrupt from compare event on channel 17. */
341 #endif
342 #if NRF_GRTC_SYSCOUNTER_CC_COUNT > 18
343 NRF_GRTC_INT_COMPARE18_MASK = GRTC_INTENSET0_COMPARE18_Msk, /**< GRTC interrupt from compare event on channel 18. */
344 #endif
345 #if NRF_GRTC_SYSCOUNTER_CC_COUNT > 19
346 NRF_GRTC_INT_COMPARE19_MASK = GRTC_INTENSET0_COMPARE19_Msk, /**< GRTC interrupt from compare event on channel 19. */
347 #endif
348 #if NRF_GRTC_SYSCOUNTER_CC_COUNT > 20
349 NRF_GRTC_INT_COMPARE20_MASK = GRTC_INTENSET0_COMPARE20_Msk, /**< GRTC interrupt from compare event on channel 20. */
350 NRF_GRTC_INT_COMPARE21_MASK = GRTC_INTENSET0_COMPARE21_Msk, /**< GRTC interrupt from compare event on channel 21. */
351 NRF_GRTC_INT_COMPARE22_MASK = GRTC_INTENSET0_COMPARE22_Msk, /**< GRTC interrupt from compare event on channel 22. */
352 NRF_GRTC_INT_COMPARE23_MASK = GRTC_INTENSET0_COMPARE23_Msk, /**< GRTC interrupt from compare event on channel 23. */
353 #endif
354 #if NRF_GRTC_HAS_RTCOUNTER
355 NRF_GRTC_INT_RTCOMPARE_MASK = GRTC_INTENSET0_RTCOMPARE_Msk, /**< GRTC interrupt from RTCOUNTER compare event. */
356 NRF_GRTC_INT_RTCOMPARESYNC_MASK = GRTC_INTENSET0_RTCOMPARESYNC_Msk, /**< GRTC interrupt from RTCOUNTER synchronized compare event. */
357 #endif
358 NRF_GRTC_INT_SYSCOUNTERVALID_MASK = GRTC_INTENSET0_SYSCOUNTERVALID_Msk, /**< GRTC interrupt from SYSCOUNTER valid event. */
359 } nrf_grtc_int_mask_t;
360
361 #if NRF_GRTC_HAS_CLKOUT
362 /** @brief Configuration of clock output. */
363 typedef enum
364 {
365 NRF_GRTC_CLKOUT_32K = GRTC_CLKOUT_CLKOUT32K_Msk, /**< Enable 32K clock output on pin. */
366 NRF_GRTC_CLKOUT_FAST = GRTC_CLKOUT_CLKOUTFAST_Msk, /**< Enable fast clock output on pin. */
367 } nrf_grtc_clkout_t;
368 #endif
369
370 #if NRF_GRTC_HAS_CLKSEL
371 /** @brief Configuration of the GRTC clock source selection. */
372 typedef enum
373 {
374 NRF_GRTC_CLKSEL_LFXO = GRTC_CLKCFG_CLKSEL_LFXO, /**< LFXO oscillator as the clock source. */
375 NRF_GRTC_CLKSEL_LFCLK = GRTC_CLKCFG_CLKSEL_SystemLFCLK, /**< System LFCLK as the clock source. */
376 } nrf_grtc_clksel_t;
377 #endif
378
379 /**
380 * @brief Function for setting the compare value of channel for the SYSCOUNTER.
381 *
382 * @note The corresponding event is automatically disabled by hardware during the operation.
383 *
384 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
385 * @param[in] cc_channel The specified capture/compare channel.
386 * @param[in] cc_value Compare value to be set in 1 MHz units.
387 */
388 NRF_STATIC_INLINE void nrf_grtc_sys_counter_cc_set(NRF_GRTC_Type * p_reg,
389 uint8_t cc_channel,
390 uint64_t cc_value);
391
392 /**
393 * @brief Function for getting the capture/compare value of channel for the SYSCOUNTER.
394 *
395 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
396 * @param[in] cc_channel The specified capture/compare channel.
397 *
398 * @return Value from the specified capture/compare register in 1MHz units.
399 */
400 NRF_STATIC_INLINE uint64_t nrf_grtc_sys_counter_cc_get(NRF_GRTC_Type const * p_reg,
401 uint8_t cc_channel);
402
403 /**
404 * @brief Function for setting the value to be added to capture/compare register for
405 * the SYSCOUNTER.
406 *
407 * @note There are two available configurations of adding operation:
408 * When @p reference value equals @ref NRF_GRTC_CC_ADD_REFERENCE_SYSCOUNTER then
409 * the final value of capture/compare register is a sum of SYSCOUNTER current value
410 * and @p value.
411 * When @p reference value equals @ref NRF_GRTC_CC_ADD_REFERENCE_CC then
412 * the final value of capture/compare register is a sum of current capture/compare
413 * value and @p value.
414 * If the capture/compare register overflows after this write, then the corresponding event
415 * is generated immediately.
416 *
417 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
418 * @param[in] cc_channel The specified capture/compare channel.
419 * @param[in] value Value to be added in 1 MHz units.
420 * @param[in] reference Configuration of adding mode.
421 */
422 NRF_STATIC_INLINE void nrf_grtc_sys_counter_cc_add_set(NRF_GRTC_Type * p_reg,
423 uint8_t cc_channel,
424 uint32_t value,
425 nrf_grtc_cc_add_reference_t reference);
426
427 #if NRF_GRTC_HAS_RTCOUNTER
428 /**
429 * @brief Function for setting a compare value for the RTCOUNTER.
430 *
431 * @note The internal synchronization mechanism ensures that the desired value will be properly
432 * latched by the GRTC. However when @p sync parameter is true then the process of capturing
433 * the value lasts up to two 32 kHz cycles.
434 * If the @p sync parameter is false then the capturing the value will occur on the
435 * following rising edge of 32 kHz clock. In this case it is user's responsibility
436 * to execute the function between the 32 kHz rising edges.
437 *
438 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
439 * @param[in] cc_value Compare value to be set in 32 kHz units.
440 * @param[in] sync True if the internal synchronization mechanism shall be used,
441 * false otherwise.
442 */
443 NRF_STATIC_INLINE void nrf_grtc_rt_counter_cc_set(NRF_GRTC_Type * p_reg,
444 uint64_t cc_value,
445 bool sync);
446
447 /**
448 * @brief Function for returning the compare value for the RTCOUNTER.
449 *
450 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
451 *
452 * @return Value from the capture/compare register in 32 kHz units.
453 */
454 NRF_STATIC_INLINE uint64_t nrf_grtc_rt_counter_cc_get(NRF_GRTC_Type const * p_reg);
455 #endif // NRF_GRTC_HAS_RTCOUNTER
456
457 /**
458 * @brief Function for enabling specified interrupts.
459 *
460 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
461 * @param[in] mask Mask of interrupts to be enabled.
462 * Use @ref nrf_grtc_int_mask_t values for bit masking.
463 */
464 NRF_STATIC_INLINE void nrf_grtc_int_enable(NRF_GRTC_Type * p_reg, uint32_t mask);
465
466 /**
467 * @brief Function for disabling specified interrupts.
468 *
469 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
470 * @param[in] mask Mask of interrupts to be disabled.
471 * Use @ref nrf_grtc_int_mask_t values for bit masking.
472 */
473 NRF_STATIC_INLINE void nrf_grtc_int_disable(NRF_GRTC_Type * p_reg, uint32_t mask);
474
475 /**
476 * @brief Function for checking if the specified interrupts are enabled.
477 *
478 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
479 * @param[in] mask Mask of interrupts to be checked.
480 * Use @ref nrf_grtc_int_mask_t values for bit masking.
481 *
482 * @return Mask of enabled interrupts.
483 */
484 NRF_STATIC_INLINE uint32_t nrf_grtc_int_enable_check(NRF_GRTC_Type const * p_reg, uint32_t mask);
485
486 /**
487 * @brief Function for retrieving the state of pending interrupts.
488 *
489 * @note States of pending interrupt are saved as a bitmask.
490 * One set at particular position means that interrupt for event is pending.
491 *
492 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
493 *
494 * @return Bitmask with information about pending interrupts.
495 * Use @ref nrf_grtc_int_mask_t values for bit masking.
496 */
497 NRF_STATIC_INLINE uint32_t nrf_grtc_int_pending_get(NRF_GRTC_Type const * p_reg);
498
499 #if NRF_GRTC_HAS_PWM
500 /**
501 * @brief Function for enabling events.
502 *
503 * @note Only specific events can be individually enabled or disabled.
504 *
505 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
506 * @param[in] mask Mask of event flags to be enabled.
507 */
508 NRF_STATIC_INLINE void nrf_grtc_event_enable(NRF_GRTC_Type * p_reg, uint32_t mask);
509
510 /**
511 * @brief Function for disabling events.
512 *
513 * @note Only specific events can be individually enabled or disabled.
514 *
515 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
516 * @param[in] mask Mask of event flags to be disabled.
517 */
518 NRF_STATIC_INLINE void nrf_grtc_event_disable(NRF_GRTC_Type * p_reg, uint32_t mask);
519 #endif // NRF_GRTC_HAS_PWM
520
521 #if NRF_GRTC_HAS_EXTENDED
522 /**
523 * @brief Function for enabling the specified shortcuts.
524 *
525 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
526 * @param[in] mask Bitmask of shortcuts to be enabled.
527 */
528 NRF_STATIC_INLINE void nrf_grtc_shorts_enable(NRF_GRTC_Type * p_reg, uint32_t mask);
529
530 /**
531 * @brief Function for disabling the specified shortcuts.
532 *
533 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
534 * @param[in] mask Bitmask of shortcuts to be disabled.
535 */
536 NRF_STATIC_INLINE void nrf_grtc_shorts_disable(NRF_GRTC_Type * p_reg, uint32_t mask);
537
538 /**
539 * @brief Function for setting the specified shortcuts.
540 *
541 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
542 * @param[in] mask Bitmask of shortcuts to be set.
543 */
544 NRF_STATIC_INLINE void nrf_grtc_shorts_set(NRF_GRTC_Type * p_reg, uint32_t mask);
545 #endif // NRF_GRTC_HAS_EXTENDED
546
547 /**
548 * @brief Function for setting the subscribe configuration for a given
549 * GRTC task.
550 *
551 * @note Not every task has its corresponding subscribe register.
552 * Refer to the Product Specification for more information.
553 *
554 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
555 * @param[in] task Task for which to set the configuration.
556 * @param[in] channel Channel through which to subscribe events.
557 */
558 NRF_STATIC_INLINE void nrf_grtc_subscribe_set(NRF_GRTC_Type * p_reg,
559 nrf_grtc_task_t task,
560 uint8_t channel);
561
562 /**
563 * @brief Function for clearing the subscribe configuration for a given
564 * GRTC task.
565 *
566 * @note Not every task has its corresponding subscribe register.
567 * Refer to the Product Specification for more information.
568 *
569 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
570 * @param[in] task Task for which to clear the configuration.
571 */
572 NRF_STATIC_INLINE void nrf_grtc_subscribe_clear(NRF_GRTC_Type * p_reg,
573 nrf_grtc_task_t task);
574
575 /**
576 * @brief Function for setting the publish configuration for a given
577 * GRTC event.
578 *
579 * @note Not every event has its corresponding publish register.
580 * Refer to the Product Specification for more information.
581 *
582 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
583 * @param[in] event Event for which to set the configuration.
584 * @param[in] channel Channel through which to publish the event.
585 */
586 NRF_STATIC_INLINE void nrf_grtc_publish_set(NRF_GRTC_Type * p_reg,
587 nrf_grtc_event_t event,
588 uint8_t channel);
589
590 /**
591 * @brief Function for clearing the publish configuration for a given
592 * GRTC event.
593 *
594 * @note Not every event has its corresponding publish register.
595 * Refer to the Product Specification for more information.
596 *
597 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
598 * @param[in] event Event for which to clear the configuration.
599 */
600 NRF_STATIC_INLINE void nrf_grtc_publish_clear(NRF_GRTC_Type * p_reg,
601 nrf_grtc_event_t event);
602
603 /**
604 * @brief Function for retrieving the state of the GRTC event.
605 *
606 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
607 * @param[in] event Event to be checked.
608 *
609 * @retval true The event has been generated.
610 * @retval false The event has not been generated.
611 */
612 NRF_STATIC_INLINE bool nrf_grtc_event_check(NRF_GRTC_Type const * p_reg, nrf_grtc_event_t event);
613
614 /**
615 * @brief Function for clearing an event.
616 *
617 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
618 * @param[in] event Event to be cleared.
619 */
620 NRF_STATIC_INLINE void nrf_grtc_event_clear(NRF_GRTC_Type * p_reg, nrf_grtc_event_t event);
621
622 #if NRF_GRTC_HAS_RTCOUNTER
623 /**
624 * @brief Function for returning the lower 32-bits of RTCOUNTER value.
625 *
626 * @note The whole RTCOUNTER value is latched when @ref nrf_grtc_rt_counter_low_get function
627 * is executed. Thus @ref nrf_grtc_rt_counter_low_get must be executed before calling
628 * @ref nrf_grtc_rt_counter_high_get.
629 *
630 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
631 *
632 * @return Lower part of RTCOUNTER value.
633 */
634 NRF_STATIC_INLINE uint32_t nrf_grtc_rt_counter_low_get(NRF_GRTC_Type const * p_reg);
635
636 /**
637 * @brief Function for returning the higher 32-bits of RTCOUNTER value.
638 *
639 * @note The whole RTCOUNTER value is latched when @ref nrf_grtc_rt_counter_low_get function
640 * is executed. Thus @ref nrf_grtc_rt_counter_low_get must be executed before calling
641 * @ref nrf_grtc_rt_counter_high_get.
642 *
643 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
644 *
645 * @return Higher part of RTCOUNTER value.
646 */
647 NRF_STATIC_INLINE uint32_t nrf_grtc_rt_counter_high_get(NRF_GRTC_Type const * p_reg);
648 #endif // NRF_GRTC_HAS_RTCOUNTER
649
650 /**
651 * @brief Function for returning the lower 32-bits of SYSCOUNTER value.
652 *
653 * @note @ref nrf_grtc_sys_counter_low_get must be executed before calling
654 * @ref nrf_grtc_sys_counter_high_get. In addition, after this,
655 * @ref nrf_grtc_sys_counter_overflow_check should be called. If it retuns true,
656 * whole procedure should be repeated.
657 *
658 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
659 *
660 * @return Lower part of SYSCOUNTER value.
661 */
662 NRF_STATIC_INLINE uint32_t nrf_grtc_sys_counter_low_get(NRF_GRTC_Type const * p_reg);
663
664 /**
665 * @brief Function for returning the higher 32-bits of SYSCOUNTER value.
666 *
667 * @note @ref nrf_grtc_sys_counter_low_get must be executed before calling
668 * @ref nrf_grtc_sys_counter_high_get. In addition, after this,
669 * @ref nrf_grtc_sys_counter_overflow_check should be called. If it retuns true,
670 * whole procedure should be repeated.
671 *
672 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
673 *
674 * @return Higher part SYSCOUNTER value.
675 */
676 NRF_STATIC_INLINE uint32_t nrf_grtc_sys_counter_high_get(NRF_GRTC_Type const * p_reg);
677
678 /**
679 * @brief Function for returning the 64-bit SYSCOUNTER value.
680 *
681 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
682 *
683 * @return SYSCOUNTER value.
684 */
685 NRF_STATIC_INLINE uint64_t nrf_grtc_sys_counter_get(NRF_GRTC_Type const * p_reg);
686
687 /**
688 * @brief Function for checking whether the lower 32-bits of SYSCOUNTER overflowed after
689 * last execution of @ref nrf_grtc_sys_counter_low_get.
690 *
691 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
692 *
693 * @retval True if the lower 32-bits of SYSCOUNTER overflowed, false otherwise.
694 */
695 NRF_STATIC_INLINE bool nrf_grtc_sys_counter_overflow_check(NRF_GRTC_Type const * p_reg);
696
697 #if NRF_GRTC_HAS_SYSCOUNTER_ARRAY
698 /**
699 * @brief Function for setting the request to keep the specified SYSCOUNTER channel active.
700 *
701 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
702 * @param[in] enable True if the SYSCOUNTER channel is to be kept active, false otherwise.
703 */
704 NRF_STATIC_INLINE void nrf_grtc_sys_counter_active_set(NRF_GRTC_Type * p_reg, bool enable);
705
706 /**
707 * @brief Function for checking whether the specified SYSCOUNTER channel is requested to remain active.
708 *
709 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
710 *
711 * @retval True if SYSCOUNTER channel is requested to remain active, false otherwise.
712 */
713 NRF_STATIC_INLINE
714 bool nrf_grtc_sys_counter_active_check(NRF_GRTC_Type const * p_reg);
715 #endif // NRF_GRTC_HAS_SYSCOUNTER_ARRAY
716
717 /**
718 * @brief Function for returning the address of an event.
719 *
720 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
721 * @param[in] event Requested event.
722 *
723 * @return Address of the requested event register.
724 */
725 NRF_STATIC_INLINE uint32_t nrf_grtc_event_address_get(NRF_GRTC_Type const * p_reg,
726 nrf_grtc_event_t event);
727
728 /**
729 * @brief Function for returning the address of a task.
730 *
731 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
732 * @param[in] task Requested task.
733 *
734 * @return Address of the requested task register.
735 */
736 NRF_STATIC_INLINE uint32_t nrf_grtc_task_address_get(NRF_GRTC_Type const * p_reg,
737 nrf_grtc_task_t task);
738
739 /**
740 * @brief Function for starting a task.
741 *
742 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
743 * @param[in] task Requested task.
744 */
745 NRF_STATIC_INLINE void nrf_grtc_task_trigger(NRF_GRTC_Type * p_reg, nrf_grtc_task_t task);
746
747 /**
748 * @brief Function for getting the 1 MHz SYSCOUNTER timer capture task associated with the
749 * specified channel.
750 *
751 * @param[in] cc_channel Capture channel.
752 *
753 * @return Capture task.
754 */
755 NRF_STATIC_INLINE nrf_grtc_task_t nrf_grtc_sys_counter_capture_task_get(uint8_t cc_channel);
756
757 /**
758 * @brief Function for enabling SYSCOUNTER compare event.
759 *
760 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
761 * @param[in] cc_channel Channel number of compare event to be enabled.
762 */
763 NRF_STATIC_INLINE void nrf_grtc_sys_counter_compare_event_enable(NRF_GRTC_Type * p_reg,
764 uint8_t cc_channel);
765
766 /**
767 * @brief Function for disabling SYSCOUNTER compare event.
768 *
769 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
770 * @param[in] cc_channel Channel number of compare event to be disabled.
771 */
772 NRF_STATIC_INLINE void nrf_grtc_sys_counter_compare_event_disable(NRF_GRTC_Type * p_reg,
773 uint8_t cc_channel);
774
775 /**
776 * @brief Function for getting the SYSCOUNTER compare event associated with the specified
777 * compare cc_channel.
778 *
779 * @param[in] cc_channel Compare channel number.
780 *
781 * @return Requested compare event.
782 */
783 NRF_STATIC_INLINE nrf_grtc_event_t nrf_grtc_sys_counter_compare_event_get(uint8_t cc_channel);
784
785 /**
786 * @brief Function for checking whether the specified capture/compare channel is enabled.
787 *
788 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
789 * @param[in] cc_channel Channel to be checked.
790 *
791 * @retval true Specified channel is enabled.
792 * @retval false Specified channel is disabled.
793 */
794 NRF_STATIC_INLINE bool nrf_grtc_sys_counter_cc_enable_check(NRF_GRTC_Type const * p_reg,
795 uint8_t cc_channel);
796
797 #if NRF_GRTC_HAS_EXTENDED
798 /**
799 * @brief Function for setting the SYSCOUNTER.
800 *
801 * @note When the SYSCOUNTER is disabled the GRTC uses RTCOUNTER by default.
802 *
803 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
804 * @param[in] enable True if SYSCOUNTER is to be enabled, false otherwise.
805 */
806 NRF_STATIC_INLINE void nrf_grtc_sys_counter_set(NRF_GRTC_Type * p_reg, bool enable);
807
808 /**
809 * @brief Function for setting automatic mode for the SYSCOUNTER.
810 *
811 * @note When @p enable is false then the SYSCOUNTER remains active when KEEPRUNNING is set,
812 * or any task register, INT register or SYSCOUNTER register is being accessed.
813 * When @p enable is true then in addition the SYSCOUNTER remains active when
814 * any local CPU that is not sleeping keeps the SYSCOUNTER active.
815 *
816 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
817 * @param[in] enable True if the automatic mode is to be enabled, false otherwise.
818 */
819 NRF_STATIC_INLINE void nrf_grtc_sys_counter_auto_mode_set(NRF_GRTC_Type * p_reg, bool enable);
820
821 /**
822 * @brief Function for checking whether the SYSCOUNTER has automatic mode enabled.
823 *
824 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
825 *
826 * @return True Automatic mode is enabled.
827 * @return False Automatic mode is disabled.
828 */
829 NRF_STATIC_INLINE bool nrf_grtc_sys_counter_auto_mode_check(NRF_GRTC_Type * p_reg);
830 #endif // NRF_GRTC_HAS_EXTENDED
831
832 /**
833 * @brief Function for checking whether the SYSCOUNTER is in active state.
834 *
835 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
836 *
837 * @retval True if the SYSCOUNTER is active, false otherwise.
838 */
839 NRF_STATIC_INLINE bool nrf_grtc_sys_counter_check(NRF_GRTC_Type const * p_reg);
840
841 /**
842 * @brief Function for setting the request to keep the SYSCOUNTER active.
843 *
844 * @note This function modifies the KEEPRUNNING register, which possesses information
845 * whether any local CPU needs keeping the SYSCOUNTER active.
846 *
847 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
848 * @param[in] enable True if the automatic mode is to be enabled, false otherwise.
849 */
850 NRF_STATIC_INLINE void nrf_grtc_sys_counter_active_state_request_set(NRF_GRTC_Type * p_reg,
851 bool enable);
852
853 /**
854 * @brief Function for checking whether the SYSCOUNTER is requested to remain active.
855 *
856 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
857 *
858 * @retval True if request for keeping the SYSCOUNTER is active, false otherwise.
859 */
860 NRF_STATIC_INLINE
861 bool nrf_grtc_sys_counter_active_state_request_check(NRF_GRTC_Type const * p_reg);
862
863 /**
864 * @brief Function for getting the domains that requested the SYSCOUNTER to remain active.
865 *
866 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
867 * @param[in] mask Domains mask.
868 *
869 * @retval Bitmask of domains that keep the SYSCOUNTER active.
870 */
871 NRF_STATIC_INLINE
872 uint32_t nrf_grtc_sys_counter_active_state_request_get(NRF_GRTC_Type const * p_reg,
873 uint32_t mask);
874 #if NRF_GRTC_HAS_EXTENDED
875 /**
876 * @brief Function for setting the periodic compare event for capture/compare channel 0.
877 *
878 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
879 * @param[in] value Period value in 1 MHz units.
880 */
881 NRF_STATIC_INLINE void nrf_grtc_sys_counter_interval_set(NRF_GRTC_Type * p_reg, uint32_t value);
882
883 /**
884 * @brief Function for getting the value of interval for periodic capture/compare event
885 * for channel 0.
886 *
887 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
888 *
889 * @retval Value of the interval in 1 MHz units.
890 */
891 NRF_STATIC_INLINE uint32_t nrf_grtc_sys_counter_interval_get(NRF_GRTC_Type const * p_reg);
892
893 /**
894 * @brief Function for setting the timeout value for GRTC.
895 *
896 * @note Timeout between all CPUs going to sleep and stopping the SYSCOUNTER.
897 *
898 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
899 * @param[in] value Timeout value in 32 kHz units.
900 */
901 NRF_STATIC_INLINE void nrf_grtc_timeout_set(NRF_GRTC_Type * p_reg, uint32_t value);
902
903 /**
904 * @brief Function for getting the value of the timeout value for GRTC.
905 *
906 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
907 *
908 * @retval Value of the timeout in 32 kHz units.
909 */
910 NRF_STATIC_INLINE uint32_t nrf_grtc_timeout_get(NRF_GRTC_Type const * p_reg);
911
912 /**
913 * @brief Function for setting the wake time value for GRTC.
914 *
915 * @note The wake time is maximum number of 32 kHz cycles takes to restore the APB registers
916 * when waking from sleep state.
917 *
918 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
919 * @param[in] value Wake time value in 32 kHz units.
920 */
921 NRF_STATIC_INLINE void nrf_grtc_waketime_set(NRF_GRTC_Type * p_reg, uint32_t value);
922
923 /**
924 * @brief Function for getting the wake time value.
925 *
926 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
927 *
928 * @retval Value of wake time in 32 kHz units.
929 */
930 NRF_STATIC_INLINE uint32_t nrf_grtc_waketime_get(NRF_GRTC_Type const * p_reg);
931 #endif // NRF_GRTC_HAS_EXTENDED
932
933 #if NRF_GRTC_HAS_PWM
934 /**
935 * @brief Function for setting the PWM compare value.
936 *
937 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
938 * @param[in] value PWM compare value.
939 */
940 NRF_STATIC_INLINE void nrf_grtc_pwm_compare_set(NRF_GRTC_Type * p_reg, uint32_t value);
941
942 /**
943 * @brief Function for getting the PWM compare value.
944 *
945 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
946 *
947 * @retval Value of PWM compare.
948 */
949 NRF_STATIC_INLINE uint32_t nrf_grtc_pwm_compare_get(NRF_GRTC_Type const * p_reg);
950 #endif // NRF_GRTC_HAS_PWM
951
952 #if NRF_GRTC_HAS_CLKOUT
953 /**
954 * @brief Function for setting the specified clock source to be connected to output pin.
955 *
956 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
957 * @param[in] clkout Selected clkout source.
958 * @param[in] enable True if the clkout source is to be enabled, false otherwise.
959 */
960 NRF_STATIC_INLINE void nrf_grtc_clkout_set(NRF_GRTC_Type * p_reg,
961 nrf_grtc_clkout_t clkout,
962 bool enable);
963
964 /**
965 * @brief Function for checking whether clock source is connected to clkout pin.
966 *
967 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
968 * @param[in] clkout Selected clkout source.
969 *
970 * @retval True if the clkout source is enabled, false otherwise.
971 */
972 NRF_STATIC_INLINE bool nrf_grtc_clkout_enable_check(NRF_GRTC_Type const * p_reg,
973 nrf_grtc_clkout_t clkout);
974
975 /**
976 * @brief Function for setting the fast clock divisor value of clock output.
977 *
978 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
979 * @param[in] value Fast clock divisor value.
980 */
981 NRF_STATIC_INLINE void nrf_grtc_clkout_divider_set(NRF_GRTC_Type * p_reg, uint32_t value);
982
983 /**
984 * @brief Function for getting the fast clock divisor value of clock output.
985 *
986 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
987 *
988 * @retval Fast clock divisor value.
989 */
990 NRF_STATIC_INLINE uint32_t nrf_grtc_clkout_divider_get(NRF_GRTC_Type const * p_reg);
991 #endif // NRF_GRTC_HAS_CLKOUT
992
993 #if NRF_GRTC_HAS_CLKSEL
994 /**
995 * @brief Function for setting the clock source for the GRTC low-frequency clock.
996 *
997 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
998 * @param[in] clksel Selected clock source.
999 */
1000 NRF_STATIC_INLINE void nrf_grtc_clksel_set(NRF_GRTC_Type * p_reg, nrf_grtc_clksel_t clksel);
1001
1002 /**
1003 * @brief Function for getting the clock source of the GRTC low-frequency clock.
1004 *
1005 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1006 *
1007 * @return Clock source configuration.
1008 */
1009 NRF_STATIC_INLINE nrf_grtc_clksel_t nrf_grtc_clksel_get(NRF_GRTC_Type const * p_reg);
1010 #endif // NRF_GRTC_HAS_CLKSEL
1011
1012 #ifndef NRF_DECLARE_ONLY
1013
nrf_grtc_sys_counter_cc_set(NRF_GRTC_Type * p_reg,uint8_t cc_channel,uint64_t cc_value)1014 NRF_STATIC_INLINE void nrf_grtc_sys_counter_cc_set(NRF_GRTC_Type * p_reg,
1015 uint8_t cc_channel,
1016 uint64_t cc_value)
1017 {
1018 #if NRF_GRTC_HAS_EXTENDED
1019 NRFX_ASSERT(cc_channel < NRF_GRTC_SYSCOUNTER_CC_COUNT);
1020 #else
1021 NRFX_ASSERT(cc_channel < NRF_GRTC_SYSCOUNTER_CC_COUNT &&
1022 cc_channel > NRF_GRTC_MAIN_CC_CHANNEL);
1023 #endif
1024 uint32_t cc_h = (uint32_t)(cc_value >> 32);
1025 NRFX_ASSERT(cc_h <= NRF_GRTC_SYSCOUNTER_CCH_MASK);
1026
1027 p_reg->CC[cc_channel].CCL = (uint32_t)cc_value;
1028 p_reg->CC[cc_channel].CCH = cc_h & NRF_GRTC_SYSCOUNTER_CCH_MASK;
1029 }
1030
nrf_grtc_sys_counter_cc_get(NRF_GRTC_Type const * p_reg,uint8_t cc_channel)1031 NRF_STATIC_INLINE uint64_t nrf_grtc_sys_counter_cc_get(NRF_GRTC_Type const * p_reg,
1032 uint8_t cc_channel)
1033 {
1034 #if NRF_GRTC_HAS_EXTENDED
1035 NRFX_ASSERT(cc_channel < NRF_GRTC_SYSCOUNTER_CC_COUNT);
1036 #else
1037 NRFX_ASSERT(cc_channel < NRF_GRTC_SYSCOUNTER_CC_COUNT &&
1038 cc_channel > NRF_GRTC_MAIN_CC_CHANNEL);
1039 #endif
1040 uint32_t cc_h = p_reg->CC[cc_channel].CCH;
1041
1042 return (uint64_t)p_reg->CC[cc_channel].CCL | ((uint64_t)cc_h << 32);
1043 }
1044
nrf_grtc_sys_counter_cc_add_set(NRF_GRTC_Type * p_reg,uint8_t cc_channel,uint32_t value,nrf_grtc_cc_add_reference_t reference)1045 NRF_STATIC_INLINE void nrf_grtc_sys_counter_cc_add_set(NRF_GRTC_Type * p_reg,
1046 uint8_t cc_channel,
1047 uint32_t value,
1048 nrf_grtc_cc_add_reference_t reference)
1049 {
1050 #if NRF_GRTC_HAS_EXTENDED
1051 NRFX_ASSERT(cc_channel < NRF_GRTC_SYSCOUNTER_CC_COUNT);
1052 #else
1053 NRFX_ASSERT(cc_channel < NRF_GRTC_SYSCOUNTER_CC_COUNT &&
1054 cc_channel > NRF_GRTC_MAIN_CC_CHANNEL);
1055 #endif
1056 NRFX_ASSERT(value <= NRF_GRTC_SYSCOUNTER_CCADD_MASK);
1057
1058 p_reg->CC[cc_channel].CCADD = ((uint32_t)reference << GRTC_CC_CCADD_REFERENCE_Pos) |
1059 (value & NRF_GRTC_SYSCOUNTER_CCADD_MASK);
1060 }
1061
1062 #if NRF_GRTC_HAS_RTCOUNTER
nrf_grtc_rt_counter_cc_set(NRF_GRTC_Type * p_reg,uint64_t cc_value,bool sync)1063 NRF_STATIC_INLINE void nrf_grtc_rt_counter_cc_set(NRF_GRTC_Type * p_reg,
1064 uint64_t cc_value,
1065 bool sync)
1066 {
1067 uint32_t cc_h = (uint32_t)(cc_value >> 32);
1068 NRFX_ASSERT(cc_h <= NRF_GRTC_RTCOUNTER_CCH_MASK);
1069
1070 if (sync)
1071 {
1072 p_reg->RTCOMPARESYNCL = (uint32_t)cc_value;
1073 p_reg->RTCOMPARESYNCH = cc_h & NRF_GRTC_RTCOUNTER_CCH_MASK;
1074 }
1075 else
1076 {
1077 p_reg->RTCOMPAREL = (uint32_t)cc_value;
1078 p_reg->RTCOMPAREH = cc_h & NRF_GRTC_RTCOUNTER_CCH_MASK;
1079 }
1080 }
1081
nrf_grtc_rt_counter_cc_get(NRF_GRTC_Type const * p_reg)1082 NRF_STATIC_INLINE uint64_t nrf_grtc_rt_counter_cc_get(NRF_GRTC_Type const * p_reg)
1083 {
1084 uint32_t cc_h = p_reg->RTCOMPAREH;
1085
1086 return (uint64_t)p_reg->RTCOMPAREL | ((uint64_t)cc_h << 32);
1087 }
1088 #endif // NRF_GRTC_HAS_RTCOUNTER
1089
nrf_grtc_int_enable(NRF_GRTC_Type * p_reg,uint32_t mask)1090 NRF_STATIC_INLINE void nrf_grtc_int_enable(NRF_GRTC_Type * p_reg, uint32_t mask)
1091 {
1092 p_reg->GRTC_INTENSET = mask;
1093 }
1094
nrf_grtc_int_disable(NRF_GRTC_Type * p_reg,uint32_t mask)1095 NRF_STATIC_INLINE void nrf_grtc_int_disable(NRF_GRTC_Type * p_reg, uint32_t mask)
1096 {
1097 p_reg->GRTC_INTENCLR = mask;
1098 }
1099
nrf_grtc_int_enable_check(NRF_GRTC_Type const * p_reg,uint32_t mask)1100 NRF_STATIC_INLINE uint32_t nrf_grtc_int_enable_check(NRF_GRTC_Type const * p_reg, uint32_t mask)
1101 {
1102 return p_reg->GRTC_INTEN & mask;
1103 }
1104
nrf_grtc_int_pending_get(NRF_GRTC_Type const * p_reg)1105 NRF_STATIC_INLINE uint32_t nrf_grtc_int_pending_get(NRF_GRTC_Type const * p_reg)
1106 {
1107 return p_reg->GRTC_INTPEND;
1108 }
1109
1110 #if NRF_GRTC_HAS_PWM
nrf_grtc_event_enable(NRF_GRTC_Type * p_reg,uint32_t mask)1111 NRF_STATIC_INLINE void nrf_grtc_event_enable(NRF_GRTC_Type * p_reg, uint32_t mask)
1112 {
1113 p_reg->EVTENSET = mask;
1114 }
1115
nrf_grtc_event_disable(NRF_GRTC_Type * p_reg,uint32_t mask)1116 NRF_STATIC_INLINE void nrf_grtc_event_disable(NRF_GRTC_Type * p_reg, uint32_t mask)
1117 {
1118 p_reg->EVTENCLR = mask;
1119 }
1120 #endif // NRF_GRTC_HAS_PWM
1121
1122 #if NRF_GRTC_HAS_EXTENDED
nrf_grtc_shorts_enable(NRF_GRTC_Type * p_reg,uint32_t mask)1123 NRF_STATIC_INLINE void nrf_grtc_shorts_enable(NRF_GRTC_Type * p_reg, uint32_t mask)
1124 {
1125 p_reg->SHORTS |= mask;
1126 }
1127
nrf_grtc_shorts_disable(NRF_GRTC_Type * p_reg,uint32_t mask)1128 NRF_STATIC_INLINE void nrf_grtc_shorts_disable(NRF_GRTC_Type * p_reg, uint32_t mask)
1129 {
1130 p_reg->SHORTS &= ~(mask);
1131 }
1132
nrf_grtc_shorts_set(NRF_GRTC_Type * p_reg,uint32_t mask)1133 NRF_STATIC_INLINE void nrf_grtc_shorts_set(NRF_GRTC_Type * p_reg, uint32_t mask)
1134 {
1135 p_reg->SHORTS = mask;
1136 }
1137 #endif // NRF_GRTC_HAS_EXTENDED
1138
nrf_grtc_subscribe_set(NRF_GRTC_Type * p_reg,nrf_grtc_task_t task,uint8_t channel)1139 NRF_STATIC_INLINE void nrf_grtc_subscribe_set(NRF_GRTC_Type * p_reg,
1140 nrf_grtc_task_t task,
1141 uint8_t channel)
1142 {
1143 #if NRF_GRTC_HAS_EXTENDED
1144 NRFX_ASSERT((task != NRF_GRTC_TASK_START) &&
1145 (task != NRF_GRTC_TASK_CLEAR) &&
1146 (task != NRF_GRTC_TASK_STOP));
1147 #endif
1148
1149 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
1150 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
1151 }
1152
nrf_grtc_subscribe_clear(NRF_GRTC_Type * p_reg,nrf_grtc_task_t task)1153 NRF_STATIC_INLINE void nrf_grtc_subscribe_clear(NRF_GRTC_Type * p_reg,
1154 nrf_grtc_task_t task)
1155 {
1156 #if NRF_GRTC_HAS_EXTENDED
1157 NRFX_ASSERT((task != NRF_GRTC_TASK_START) &&
1158 (task != NRF_GRTC_TASK_CLEAR) &&
1159 (task != NRF_GRTC_TASK_STOP));
1160 #endif
1161
1162 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
1163 }
1164
nrf_grtc_publish_set(NRF_GRTC_Type * p_reg,nrf_grtc_event_t event,uint8_t channel)1165 NRF_STATIC_INLINE void nrf_grtc_publish_set(NRF_GRTC_Type * p_reg,
1166 nrf_grtc_event_t event,
1167 uint8_t channel)
1168 {
1169 NRFX_ASSERT(event != NRF_GRTC_EVENT_SYSCOUNTERVALID);
1170 #if NRF_GRTC_HAS_RTCOUNTER
1171 NRFX_ASSERT(event != NRF_GRTC_EVENT_RTCOMPARESYNC);
1172 #endif
1173
1174 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80UL)) =
1175 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
1176 }
1177
nrf_grtc_publish_clear(NRF_GRTC_Type * p_reg,nrf_grtc_event_t event)1178 NRF_STATIC_INLINE void nrf_grtc_publish_clear(NRF_GRTC_Type * p_reg,
1179 nrf_grtc_event_t event)
1180 {
1181 NRFX_ASSERT(event != NRF_GRTC_EVENT_SYSCOUNTERVALID);
1182 #if NRF_GRTC_HAS_RTCOUNTER
1183 NRFX_ASSERT(event != NRF_GRTC_EVENT_RTCOMPARESYNC);
1184 #endif
1185
1186 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80UL)) = 0x0UL;
1187 }
1188
nrf_grtc_event_check(NRF_GRTC_Type const * p_reg,nrf_grtc_event_t event)1189 NRF_STATIC_INLINE bool nrf_grtc_event_check(NRF_GRTC_Type const * p_reg, nrf_grtc_event_t event)
1190 {
1191 return nrf_event_check(p_reg, event);
1192 }
1193
nrf_grtc_event_clear(NRF_GRTC_Type * p_reg,nrf_grtc_event_t event)1194 NRF_STATIC_INLINE void nrf_grtc_event_clear(NRF_GRTC_Type * p_reg, nrf_grtc_event_t event)
1195 {
1196 NRFX_ASSERT(event != NRF_GRTC_EVENT_SYSCOUNTERVALID);
1197
1198 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
1199 nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
1200 }
1201
1202 #if NRF_GRTC_HAS_RTCOUNTER
nrf_grtc_rt_counter_low_get(NRF_GRTC_Type const * p_reg)1203 NRF_STATIC_INLINE uint32_t nrf_grtc_rt_counter_low_get(NRF_GRTC_Type const * p_reg)
1204 {
1205 return p_reg->RTCOUNTERL;
1206 }
1207
nrf_grtc_rt_counter_high_get(NRF_GRTC_Type const * p_reg)1208 NRF_STATIC_INLINE uint32_t nrf_grtc_rt_counter_high_get(NRF_GRTC_Type const * p_reg)
1209 {
1210 return p_reg->RTCOUNTERH;
1211 }
1212 #endif // NRF_GRTC_HAS_RTCOUNTER
1213
nrf_grtc_sys_counter_low_get(NRF_GRTC_Type const * p_reg)1214 NRF_STATIC_INLINE uint32_t nrf_grtc_sys_counter_low_get(NRF_GRTC_Type const * p_reg)
1215 {
1216 #if NRF_GRTC_HAS_SYSCOUNTER_ARRAY
1217 return p_reg->GRTC_SYSCOUNTER.SYSCOUNTERL;
1218 #else
1219 return p_reg->SYSCOUNTERL;
1220 #endif // NRF_GRTC_HAS_SYSCOUNTER_ARRAY
1221 }
1222
nrf_grtc_sys_counter_high_get(NRF_GRTC_Type const * p_reg)1223 NRF_STATIC_INLINE uint32_t nrf_grtc_sys_counter_high_get(NRF_GRTC_Type const * p_reg)
1224 {
1225 #if NRF_GRTC_HAS_SYSCOUNTER_ARRAY
1226 return p_reg->GRTC_SYSCOUNTER.SYSCOUNTERH;
1227 #else
1228 return p_reg->SYSCOUNTERH;
1229 #endif // NRF_GRTC_HAS_SYSCOUNTER_ARRAY
1230 }
1231
nrf_grtc_sys_counter_get(NRF_GRTC_Type const * p_reg)1232 NRF_STATIC_INLINE uint64_t nrf_grtc_sys_counter_get(NRF_GRTC_Type const * p_reg)
1233 {
1234 #if NRF_GRTC_HAS_SYSCOUNTER_ARRAY
1235 return *((const uint64_t volatile *)&p_reg->GRTC_SYSCOUNTER.SYSCOUNTERL);
1236 #else
1237 return *((const uint64_t volatile *)&p_reg->SYSCOUNTERL);
1238 #endif // NRF_GRTC_HAS_SYSCOUNTER_ARRAY
1239 }
1240
nrf_grtc_sys_counter_overflow_check(NRF_GRTC_Type const * p_reg)1241 NRF_STATIC_INLINE bool nrf_grtc_sys_counter_overflow_check(NRF_GRTC_Type const * p_reg)
1242 {
1243 #if NRF_GRTC_HAS_SYSCOUNTER_ARRAY
1244 return (p_reg->GRTC_SYSCOUNTER.SYSCOUNTERH &
1245 GRTC_SYSCOUNTER_SYSCOUNTERH_OVERFLOW_Msk) ? true : false;
1246 #else
1247 return (p_reg->SYSCOUNTERH & GRTC_SYSCOUNTERH_OVERFLOW_Msk) ? true : false;
1248 #endif // NRF_GRTC_HAS_SYSCOUNTER_ARRAY
1249 }
1250
1251 #if NRF_GRTC_HAS_SYSCOUNTER_ARRAY
nrf_grtc_sys_counter_active_set(NRF_GRTC_Type * p_reg,bool enable)1252 NRF_STATIC_INLINE void nrf_grtc_sys_counter_active_set(NRF_GRTC_Type * p_reg, bool enable)
1253 {
1254 p_reg->GRTC_SYSCOUNTER.ACTIVE = ((p_reg->GRTC_SYSCOUNTER.ACTIVE &
1255 ~(GRTC_SYSCOUNTER_ACTIVE_ACTIVE_Msk)) |
1256 (enable ? GRTC_SYSCOUNTER_ACTIVE_ACTIVE_Active :
1257 GRTC_SYSCOUNTER_ACTIVE_ACTIVE_NotActive));
1258 }
1259
nrf_grtc_sys_counter_active_check(NRF_GRTC_Type const * p_reg)1260 NRF_STATIC_INLINE bool nrf_grtc_sys_counter_active_check(NRF_GRTC_Type const * p_reg)
1261 {
1262 return (p_reg->GRTC_SYSCOUNTER.ACTIVE & GRTC_SYSCOUNTER_ACTIVE_ACTIVE_Msk) ==
1263 GRTC_SYSCOUNTER_ACTIVE_ACTIVE_Active;
1264 }
1265 #endif // NRF_GRTC_HAS_SYSCOUNTER_ARRAY
1266
nrf_grtc_event_address_get(NRF_GRTC_Type const * p_reg,nrf_grtc_event_t event)1267 NRF_STATIC_INLINE uint32_t nrf_grtc_event_address_get(NRF_GRTC_Type const * p_reg,
1268 nrf_grtc_event_t event)
1269 {
1270 return (uint32_t)p_reg + (uint32_t)event;
1271 }
1272
nrf_grtc_task_address_get(NRF_GRTC_Type const * p_reg,nrf_grtc_task_t task)1273 NRF_STATIC_INLINE uint32_t nrf_grtc_task_address_get(NRF_GRTC_Type const * p_reg,
1274 nrf_grtc_task_t task)
1275 {
1276 return (uint32_t)p_reg + (uint32_t)task;
1277 }
1278
nrf_grtc_task_trigger(NRF_GRTC_Type * p_reg,nrf_grtc_task_t task)1279 NRF_STATIC_INLINE void nrf_grtc_task_trigger(NRF_GRTC_Type * p_reg, nrf_grtc_task_t task)
1280 {
1281 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
1282 }
1283
nrf_grtc_sys_counter_capture_task_get(uint8_t cc_channel)1284 NRF_STATIC_INLINE nrf_grtc_task_t nrf_grtc_sys_counter_capture_task_get(uint8_t cc_channel)
1285 {
1286 return (nrf_grtc_task_t)NRFX_OFFSETOF(NRF_GRTC_Type, TASKS_CAPTURE[cc_channel]);
1287 }
1288
nrf_grtc_sys_counter_compare_event_enable(NRF_GRTC_Type * p_reg,uint8_t cc_channel)1289 NRF_STATIC_INLINE void nrf_grtc_sys_counter_compare_event_enable(NRF_GRTC_Type * p_reg,
1290 uint8_t cc_channel)
1291 {
1292
1293 #if NRF_GRTC_HAS_EXTENDED
1294 NRFX_ASSERT(cc_channel < NRF_GRTC_SYSCOUNTER_CC_COUNT);
1295 #else
1296 NRFX_ASSERT(cc_channel < NRF_GRTC_SYSCOUNTER_CC_COUNT &&
1297 cc_channel > NRF_GRTC_MAIN_CC_CHANNEL);
1298 #endif
1299 p_reg->CC[cc_channel].CCEN = GRTC_CC_CCEN_ACTIVE_Enable;
1300 }
1301
nrf_grtc_sys_counter_compare_event_disable(NRF_GRTC_Type * p_reg,uint8_t cc_channel)1302 NRF_STATIC_INLINE void nrf_grtc_sys_counter_compare_event_disable(NRF_GRTC_Type * p_reg,
1303 uint8_t cc_channel)
1304 {
1305 #if NRF_GRTC_HAS_EXTENDED
1306 NRFX_ASSERT(cc_channel < NRF_GRTC_SYSCOUNTER_CC_COUNT);
1307 #else
1308 NRFX_ASSERT(cc_channel < NRF_GRTC_SYSCOUNTER_CC_COUNT &&
1309 cc_channel > NRF_GRTC_MAIN_CC_CHANNEL);
1310 #endif
1311 p_reg->CC[cc_channel].CCEN = GRTC_CC_CCEN_ACTIVE_Disable;
1312 }
1313
nrf_grtc_sys_counter_compare_event_get(uint8_t cc_channel)1314 NRF_STATIC_INLINE nrf_grtc_event_t nrf_grtc_sys_counter_compare_event_get(uint8_t cc_channel)
1315 {
1316 return (nrf_grtc_event_t)NRFX_OFFSETOF(NRF_GRTC_Type, EVENTS_COMPARE[cc_channel]);
1317 }
1318
nrf_grtc_sys_counter_cc_enable_check(NRF_GRTC_Type const * p_reg,uint8_t cc_channel)1319 NRF_STATIC_INLINE bool nrf_grtc_sys_counter_cc_enable_check(NRF_GRTC_Type const * p_reg,
1320 uint8_t cc_channel)
1321 {
1322 return ((p_reg->CC[cc_channel].CCEN & GRTC_CC_CCEN_ACTIVE_Msk) >> GRTC_CC_CCEN_ACTIVE_Pos) ==
1323 GRTC_CC_CCEN_ACTIVE_Enable;
1324 }
1325
1326 #if NRF_GRTC_HAS_EXTENDED
nrf_grtc_sys_counter_set(NRF_GRTC_Type * p_reg,bool enable)1327 NRF_STATIC_INLINE void nrf_grtc_sys_counter_set(NRF_GRTC_Type * p_reg, bool enable)
1328 {
1329 p_reg->MODE = ((p_reg->MODE & ~GRTC_MODE_SYSCOUNTEREN_Msk) |
1330 ((enable ? GRTC_MODE_SYSCOUNTEREN_Enabled :
1331 GRTC_MODE_SYSCOUNTEREN_Disabled) << GRTC_MODE_SYSCOUNTEREN_Pos));
1332 }
1333
nrf_grtc_sys_counter_auto_mode_set(NRF_GRTC_Type * p_reg,bool enable)1334 NRF_STATIC_INLINE void nrf_grtc_sys_counter_auto_mode_set(NRF_GRTC_Type * p_reg, bool enable)
1335 {
1336 p_reg->MODE = ((p_reg->MODE & ~GRTC_MODE_AUTOEN_Msk) |
1337 ((enable ? GRTC_MODE_AUTOEN_CpuActive :
1338 GRTC_MODE_AUTOEN_Default) << GRTC_MODE_AUTOEN_Pos));
1339 }
1340
nrf_grtc_sys_counter_auto_mode_check(NRF_GRTC_Type * p_reg)1341 NRF_STATIC_INLINE bool nrf_grtc_sys_counter_auto_mode_check(NRF_GRTC_Type * p_reg)
1342 {
1343 return (p_reg->MODE & GRTC_MODE_AUTOEN_Msk) == GRTC_MODE_AUTOEN_CpuActive;
1344 }
1345
1346 #endif // NRF_GRTC_HAS_EXTENDED
1347
nrf_grtc_sys_counter_check(NRF_GRTC_Type const * p_reg)1348 NRF_STATIC_INLINE bool nrf_grtc_sys_counter_check(NRF_GRTC_Type const * p_reg)
1349 {
1350 return (p_reg->MODE & GRTC_MODE_SYSCOUNTEREN_Msk) ? true : false;
1351 }
1352
nrf_grtc_sys_counter_active_state_request_set(NRF_GRTC_Type * p_reg,bool enable)1353 NRF_STATIC_INLINE void nrf_grtc_sys_counter_active_state_request_set(NRF_GRTC_Type * p_reg,
1354 bool enable)
1355 {
1356 #if defined(GRTC_KEEPRUNNING_DOMAIN0_Msk)
1357 p_reg->KEEPRUNNING = ((p_reg->KEEPRUNNING &
1358 ~(GRTC_KEEPRUNNING_DOMAIN0_Active << NRF_GRTC_DOMAIN_INDEX)) |
1359 ((enable ? GRTC_KEEPRUNNING_DOMAIN0_Active :
1360 GRTC_KEEPRUNNING_DOMAIN0_NotActive) << NRF_GRTC_DOMAIN_INDEX));
1361 #else
1362 p_reg->KEEPRUNNING = ((p_reg->KEEPRUNNING &
1363 ~(GRTC_KEEPRUNNING_REQUEST0_Active << NRF_GRTC_DOMAIN_INDEX)) |
1364 ((enable ? GRTC_KEEPRUNNING_REQUEST0_Active :
1365 GRTC_KEEPRUNNING_REQUEST0_NotActive) << NRF_GRTC_DOMAIN_INDEX));
1366 #endif
1367 }
1368
1369 NRF_STATIC_INLINE
nrf_grtc_sys_counter_active_state_request_check(NRF_GRTC_Type const * p_reg)1370 bool nrf_grtc_sys_counter_active_state_request_check(NRF_GRTC_Type const * p_reg)
1371 {
1372 #if defined(GRTC_KEEPRUNNING_DOMAIN0_Msk)
1373 return (p_reg->KEEPRUNNING &
1374 (GRTC_KEEPRUNNING_DOMAIN0_Active << NRF_GRTC_DOMAIN_INDEX)) ? true : false;
1375 #else
1376 return (p_reg->KEEPRUNNING &
1377 (GRTC_KEEPRUNNING_REQUEST0_Active << NRF_GRTC_DOMAIN_INDEX)) ? true : false;
1378 #endif
1379 }
1380
1381 NRF_STATIC_INLINE
nrf_grtc_sys_counter_active_state_request_get(NRF_GRTC_Type const * p_reg,uint32_t mask)1382 uint32_t nrf_grtc_sys_counter_active_state_request_get(NRF_GRTC_Type const * p_reg,
1383 uint32_t mask)
1384 {
1385 return p_reg->KEEPRUNNING & mask;
1386 }
1387
1388 #if NRF_GRTC_HAS_EXTENDED
nrf_grtc_sys_counter_interval_set(NRF_GRTC_Type * p_reg,uint32_t value)1389 NRF_STATIC_INLINE void nrf_grtc_sys_counter_interval_set(NRF_GRTC_Type * p_reg, uint32_t value)
1390 {
1391 p_reg->INTERVAL = value;
1392 }
1393
nrf_grtc_sys_counter_interval_get(NRF_GRTC_Type const * p_reg)1394 NRF_STATIC_INLINE uint32_t nrf_grtc_sys_counter_interval_get(NRF_GRTC_Type const * p_reg)
1395 {
1396 return p_reg->INTERVAL;
1397 }
1398
nrf_grtc_timeout_set(NRF_GRTC_Type * p_reg,uint32_t value)1399 NRF_STATIC_INLINE void nrf_grtc_timeout_set(NRF_GRTC_Type * p_reg, uint32_t value)
1400 {
1401 NRFX_ASSERT(value <= NRF_GRTC_TIMEOUT_MAX_VALUE);
1402 p_reg->TIMEOUT = (value << GRTC_TIMEOUT_VALUE_Pos);
1403 }
1404
nrf_grtc_timeout_get(NRF_GRTC_Type const * p_reg)1405 NRF_STATIC_INLINE uint32_t nrf_grtc_timeout_get(NRF_GRTC_Type const * p_reg)
1406 {
1407 return (p_reg->TIMEOUT >> GRTC_TIMEOUT_VALUE_Pos);
1408 }
1409
nrf_grtc_waketime_set(NRF_GRTC_Type * p_reg,uint32_t value)1410 NRF_STATIC_INLINE void nrf_grtc_waketime_set(NRF_GRTC_Type * p_reg, uint32_t value)
1411 {
1412 NRFX_ASSERT(value <= NRF_GRTC_WAKETIME_MAX_VALUE);
1413 p_reg->WAKETIME = (value << GRTC_WAKETIME_VALUE_Pos);
1414 }
1415
nrf_grtc_waketime_get(NRF_GRTC_Type const * p_reg)1416 NRF_STATIC_INLINE uint32_t nrf_grtc_waketime_get(NRF_GRTC_Type const * p_reg)
1417 {
1418 return (p_reg->WAKETIME >> GRTC_WAKETIME_VALUE_Pos);
1419 }
1420 #endif // NRF_GRTC_HAS_EXTENDED
1421
1422 #if NRF_GRTC_HAS_PWM
nrf_grtc_pwm_compare_set(NRF_GRTC_Type * p_reg,uint32_t value)1423 NRF_STATIC_INLINE void nrf_grtc_pwm_compare_set(NRF_GRTC_Type * p_reg, uint32_t value)
1424 {
1425 p_reg->PWMCONFIG = (value << GRTC_PWMCONFIG_COMPAREVALUE_Pos) & GRTC_PWMCONFIG_COMPAREVALUE_Msk;
1426 }
1427
nrf_grtc_pwm_compare_get(NRF_GRTC_Type const * p_reg)1428 NRF_STATIC_INLINE uint32_t nrf_grtc_pwm_compare_get(NRF_GRTC_Type const * p_reg)
1429 {
1430 return (p_reg->PWMCONFIG >> GRTC_PWMCONFIG_COMPAREVALUE_Pos);
1431 }
1432 #endif // NRF_GRTC_HAS_PWM
1433
1434 #if NRF_GRTC_HAS_CLKOUT
nrf_grtc_clkout_set(NRF_GRTC_Type * p_reg,nrf_grtc_clkout_t clkout,bool enable)1435 NRF_STATIC_INLINE void nrf_grtc_clkout_set(NRF_GRTC_Type * p_reg,
1436 nrf_grtc_clkout_t clkout,
1437 bool enable)
1438 {
1439 if (enable)
1440 {
1441 p_reg->CLKOUT |= (uint32_t)clkout;
1442 }
1443 else
1444 {
1445 p_reg->CLKOUT &= ~((uint32_t)clkout);
1446 }
1447 }
1448
nrf_grtc_clkout_enable_check(NRF_GRTC_Type const * p_reg,nrf_grtc_clkout_t clkout)1449 NRF_STATIC_INLINE bool nrf_grtc_clkout_enable_check(NRF_GRTC_Type const * p_reg,
1450 nrf_grtc_clkout_t clkout)
1451 {
1452 return p_reg->CLKOUT == (uint32_t)clkout;
1453 }
1454
nrf_grtc_clkout_divider_set(NRF_GRTC_Type * p_reg,uint32_t value)1455 NRF_STATIC_INLINE void nrf_grtc_clkout_divider_set(NRF_GRTC_Type * p_reg, uint32_t value)
1456 {
1457 NRFX_ASSERT(value <= NRF_GRTC_CLKCFG_CLKFASTDIV_MAX_VALUE);
1458 p_reg->CLKCFG = (p_reg->CLKCFG & ~GRTC_CLKCFG_CLKFASTDIV_Msk) |
1459 ((value & GRTC_CLKCFG_CLKFASTDIV_Msk) << GRTC_CLKCFG_CLKFASTDIV_Pos);
1460 }
1461
nrf_grtc_clkout_divider_get(NRF_GRTC_Type const * p_reg)1462 NRF_STATIC_INLINE uint32_t nrf_grtc_clkout_divider_get(NRF_GRTC_Type const * p_reg)
1463 {
1464 return (p_reg->CLKCFG & GRTC_CLKCFG_CLKFASTDIV_Msk) >> GRTC_CLKCFG_CLKFASTDIV_Pos;
1465 }
1466 #endif // NRF_GRTC_HAS_CLKOUT
1467
1468 #if NRF_GRTC_HAS_CLKSEL
nrf_grtc_clksel_set(NRF_GRTC_Type * p_reg,nrf_grtc_clksel_t clksel)1469 NRF_STATIC_INLINE void nrf_grtc_clksel_set(NRF_GRTC_Type * p_reg, nrf_grtc_clksel_t clksel)
1470 {
1471 p_reg->CLKCFG = (p_reg->CLKCFG & ~GRTC_CLKCFG_CLKSEL_Msk) |
1472 (clksel << GRTC_CLKCFG_CLKSEL_Pos);
1473 }
1474
nrf_grtc_clksel_get(NRF_GRTC_Type const * p_reg)1475 NRF_STATIC_INLINE nrf_grtc_clksel_t nrf_grtc_clksel_get(NRF_GRTC_Type const * p_reg)
1476 {
1477 return (nrf_grtc_clksel_t)((p_reg->CLKCFG & GRTC_CLKCFG_CLKSEL_Msk) >> GRTC_CLKCFG_CLKSEL_Pos);
1478 }
1479 #endif // NRF_GRTC_HAS_CLKSEL
1480
1481 #endif // NRF_DECLARE_ONLY
1482
1483 /** @} */
1484
1485 #ifdef __cplusplus
1486 }
1487 #endif
1488
1489 #endif /* NRF_GRTC_H */
1490
