1 /*
2 * Copyright (c) 2015 - 2024, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_GPIOTE_H__
35 #define NRF_GPIOTE_H__
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 #if !defined(NRF_GPIOTE0) && defined(NRF_GPIOTE)
44 #define NRF_GPIOTE0 NRF_GPIOTE
45 #endif
46
47 #if !defined(GPIOTE0_CH_NUM) && defined(GPIOTE_CH_NUM) && \
48 (defined(NRF_GPIOTE) || defined(NRF_GPIOTE0))
49 #define GPIOTE0_CH_NUM GPIOTE_CH_NUM
50 #endif
51
52 #if !defined(GPIOTE1_CH_NUM) && defined(GPIOTE_CH_NUM) && defined(NRF_GPIOTE1)
53 #define GPIOTE1_CH_NUM GPIOTE_CH_NUM
54 #endif
55
56 #if !defined(GPIOTE0_AVAILABLE_GPIO_PORTS) && defined(GPIO_COUNT) && \
57 (defined(NRF_GPIOTE) || defined(NRF_GPIOTE0))
58 #define GPIOTE0_AVAILABLE_GPIO_PORTS NRFX_BIT_MASK(GPIO_COUNT)
59 #endif
60
61 #if !defined(GPIOTE1_AVAILABLE_GPIO_PORTS) && defined(GPIO_COUNT) && defined(NRF_GPIOTE1)
62 #define GPIOTE1_AVAILABLE_GPIO_PORTS NRFX_BIT_MASK(GPIO_COUNT)
63 #endif
64
65 #if defined(LUMOS_XXAA)
66 #if (defined(ISA_ARM) && defined(NRF_TRUSTZONE_NONSECURE)) || defined(ISA_RISCV)
67 #define GPIOTE20_IRQn GPIOTE20_0_IRQn
68 #define GPIOTE20_IRQHandler GPIOTE20_0_IRQHandler
69 #define GPIOTE30_IRQn GPIOTE30_0_IRQn
70 #define GPIOTE30_IRQHandler GPIOTE30_0_IRQHandler
71 #else
72 #define GPIOTE20_IRQn GPIOTE20_1_IRQn
73 #define GPIOTE20_IRQHandler GPIOTE20_1_IRQHandler
74 #define GPIOTE30_IRQn GPIOTE30_1_IRQn
75 #define GPIOTE30_IRQHandler GPIOTE30_1_IRQHandler
76 #endif
77 #endif
78
79 #if defined(HALTIUM_XXAA)
80 #if (defined(ISA_ARM) && defined(NRF_TRUSTZONE_NONSECURE)) || defined(ISA_RISCV)
81 #define GPIOTE130_IRQn GPIOTE130_0_IRQn
82 #define GPIOTE130_IRQHandler GPIOTE130_0_IRQHandler
83 #else
84 #define GPIOTE130_IRQn GPIOTE130_1_IRQn
85 #define GPIOTE130_IRQHandler GPIOTE130_1_IRQHandler
86 #endif
87 #endif
88
89 /* Internal macro used for NRF_GPIOTE_INT_IN_MASK. */
90 #define NRF_GPIOTE_INT_IN(idx, _) NRFX_CONCAT(NRF_GPIOTE_INT_IN, idx, _MASK)
91
92 /**
93 * @defgroup nrf_gpiote_hal GPIOTE HAL
94 * @{
95 * @ingroup nrf_gpiote
96 * @brief Hardware access layer (HAL) for managing the GPIOTE peripheral.
97 */
98
99 /**
100 * @brief Macro for getting a pointer to the structure of registers of the GPIOTE peripheral.
101 *
102 * @param[in] idx GPIOTE instance index.
103 *
104 * @return Pointer to the structure of registers of the GPIOTE peripheral.
105 */
106 #define NRF_GPIOTE_INST_GET(idx) NRFX_CONCAT(NRF_, GPIOTE, idx)
107
108 #if defined(GPIOTE_CONFIG_PORT_Msk) || defined(__NRFX_DOXYGEN__)
109 /** @brief Mask for covering port and pin bits in registers. */
110 #define GPIOTE_CONFIG_PORT_PIN_Msk (GPIOTE_CONFIG_PORT_Msk | GPIOTE_CONFIG_PSEL_Msk)
111 #else
112 #define GPIOTE_CONFIG_PORT_PIN_Msk GPIOTE_CONFIG_PSEL_Msk
113 #endif
114
115 #if defined(GPIOTE_LATENCY_LATENCY_Msk) || defined(__NRFX_DOXYGEN__)
116 /** @brief Presence of the latency setting. */
117 #define NRF_GPIOTE_HAS_LATENCY 1
118 #else
119 #define NRF_GPIOTE_HAS_LATENCY 0
120 #endif
121
122 #if defined(GPIOTE_IRQ_GROUP) || defined(GPIOTE130_IRQ_GROUP) || defined(__NRFX_DOXYGEN__)
123 /** @brief Symbol indicating whether GPIOTE interrupt groups are present. */
124 #define NRF_GPIOTE_HAS_INT_GROUPS 1
125 #else
126 #define NRF_GPIOTE_HAS_INT_GROUPS 0
127 #endif
128
129 #if defined(GPIOTE_IRQ_GROUP) || defined(__NRFX_DOXYGEN__)
130 /** @brief Symbol indicating which interrupt group to use. Empty if there are no groups. */
131 #define NRF_GPIOTE_IRQ_GROUP GPIOTE_IRQ_GROUP
132 #elif defined(GPIOTE130_IRQ_GROUP)
133 #define NRF_GPIOTE_IRQ_GROUP GPIOTE130_IRQ_GROUP
134 #else
135 #define NRF_GPIOTE_IRQ_GROUP
136 #endif
137
138 #if defined(GPIOTE_INTENSET0_PORT0SECURE_Msk)
139 #if defined(NRF_TRUSTZONE_NONSECURE) || \
140 (defined(ISA_RISCV) && defined(HALTIUM_XXAA))
141 #define NRF_GPIOTE_SECURE_SUFFIX NONSECURE
142 #else
143 #define NRF_GPIOTE_SECURE_SUFFIX SECURE
144 #endif
145 #else
146 /** @brief Symbol indicating a TrustZone suffix added to the register name. */
147 #define NRF_GPIOTE_SECURE_SUFFIX
148 #endif
149
150 #if defined(GPIOTE_INTENSET0_IN0_Msk)
151 #if defined(LUMOS_XXAA)
152 #define NRF_GPIOTE_PORT_ID 0
153 #elif defined(NRF_APPLICATION) || defined(NRF_PPR)
154 #define NRF_GPIOTE_PORT_ID 1
155 #elif defined(NRF_RADIOCORE)
156 #define NRF_GPIOTE_PORT_ID 2
157 #endif
158 #endif
159
160 #if defined(NRF_GPIOTE_PORT_ID)
161 #define NRF_GPIOTE_EVENTS_PORT_REG EVENTS_PORT[NRF_GPIOTE_PORT_ID].NRF_GPIOTE_SECURE_SUFFIX
162
163 #define NRF_GPIOTE_INT_PORT_MASK_NAME \
164 NRFX_CONCAT(GPIOTE_INTENSET, \
165 NRF_GPIOTE_IRQ_GROUP, \
166 _PORT, \
167 NRF_GPIOTE_PORT_ID, \
168 NRF_GPIOTE_SECURE_SUFFIX, \
169 _Msk)
170 #else
171 /** @brief Symbol indicating a name of PORT event register to be used. */
172 #define NRF_GPIOTE_EVENTS_PORT_REG EVENTS_PORT
173
174 /** @brief Symbol specifying interrupt bitmask associated with the PORT event. */
175 #define NRF_GPIOTE_INT_PORT_MASK_NAME GPIOTE_INTENSET_PORT_Msk
176 #endif
177
178 /** @brief Polarity for the GPIOTE channel. */
179 typedef enum
180 {
181 NRF_GPIOTE_POLARITY_NONE = GPIOTE_CONFIG_POLARITY_None, ///< None.
182 NRF_GPIOTE_POLARITY_LOTOHI = GPIOTE_CONFIG_POLARITY_LoToHi, ///< Low to high.
183 NRF_GPIOTE_POLARITY_HITOLO = GPIOTE_CONFIG_POLARITY_HiToLo, ///< High to low.
184 NRF_GPIOTE_POLARITY_TOGGLE = GPIOTE_CONFIG_POLARITY_Toggle, ///< Toggle.
185 } nrf_gpiote_polarity_t;
186
187 /** @brief Initial output value for the GPIOTE channel. */
188 typedef enum
189 {
190 NRF_GPIOTE_INITIAL_VALUE_LOW = GPIOTE_CONFIG_OUTINIT_Low, ///< Low to high.
191 NRF_GPIOTE_INITIAL_VALUE_HIGH = GPIOTE_CONFIG_OUTINIT_High, ///< High to low.
192 } nrf_gpiote_outinit_t;
193
194 #if NRF_GPIOTE_HAS_LATENCY
195 /** @brief Latency setting. */
196 typedef enum
197 {
198 NRF_GPIOTE_LATENCY_LOWPOWER = GPIOTE_LATENCY_LATENCY_LowPower, ///< Low Power.
199 NRF_GPIOTE_LATENCY_LOWLATENCY = GPIOTE_LATENCY_LATENCY_LowLatency, ///< Low Latency.
200 } nrf_gpiote_latency_t;
201 #endif
202
203 /** @brief GPIOTE tasks. */
204 typedef enum
205 {
206 NRF_GPIOTE_TASK_OUT_0 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[0]), ///< Out task 0.
207 NRF_GPIOTE_TASK_OUT_1 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[1]), ///< Out task 1.
208 NRF_GPIOTE_TASK_OUT_2 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[2]), ///< Out task 2.
209 NRF_GPIOTE_TASK_OUT_3 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[3]), ///< Out task 3.
210 #if (GPIOTE_CH_NUM > 4) || defined(__NRFX_DOXYGEN__)
211 NRF_GPIOTE_TASK_OUT_4 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[4]), ///< Out task 4.
212 NRF_GPIOTE_TASK_OUT_5 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[5]), ///< Out task 5.
213 NRF_GPIOTE_TASK_OUT_6 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[6]), ///< Out task 6.
214 NRF_GPIOTE_TASK_OUT_7 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[7]), ///< Out task 7.
215 #endif
216 #if defined(GPIOTE_FEATURE_SET_PRESENT) || defined(__NRFX_DOXYGEN__)
217 NRF_GPIOTE_TASK_SET_0 = offsetof(NRF_GPIOTE_Type, TASKS_SET[0]), ///< Set task 0.
218 NRF_GPIOTE_TASK_SET_1 = offsetof(NRF_GPIOTE_Type, TASKS_SET[1]), ///< Set task 1.
219 NRF_GPIOTE_TASK_SET_2 = offsetof(NRF_GPIOTE_Type, TASKS_SET[2]), ///< Set task 2.
220 NRF_GPIOTE_TASK_SET_3 = offsetof(NRF_GPIOTE_Type, TASKS_SET[3]), ///< Set task 3.
221 NRF_GPIOTE_TASK_SET_4 = offsetof(NRF_GPIOTE_Type, TASKS_SET[4]), ///< Set task 4.
222 NRF_GPIOTE_TASK_SET_5 = offsetof(NRF_GPIOTE_Type, TASKS_SET[5]), ///< Set task 5.
223 NRF_GPIOTE_TASK_SET_6 = offsetof(NRF_GPIOTE_Type, TASKS_SET[6]), ///< Set task 6.
224 NRF_GPIOTE_TASK_SET_7 = offsetof(NRF_GPIOTE_Type, TASKS_SET[7]), ///< Set task 7.
225 #endif
226 #if defined(GPIOTE_FEATURE_CLR_PRESENT) || defined(__NRFX_DOXYGEN__)
227 NRF_GPIOTE_TASK_CLR_0 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[0]), ///< Clear task 0.
228 NRF_GPIOTE_TASK_CLR_1 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[1]), ///< Clear task 1.
229 NRF_GPIOTE_TASK_CLR_2 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[2]), ///< Clear task 2.
230 NRF_GPIOTE_TASK_CLR_3 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[3]), ///< Clear task 3.
231 NRF_GPIOTE_TASK_CLR_4 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[4]), ///< Clear task 4.
232 NRF_GPIOTE_TASK_CLR_5 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[5]), ///< Clear task 5.
233 NRF_GPIOTE_TASK_CLR_6 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[6]), ///< Clear task 6.
234 NRF_GPIOTE_TASK_CLR_7 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[7]), ///< Clear task 7.
235 #endif
236 } nrf_gpiote_task_t;
237
238 /** @brief GPIOTE events. */
239 typedef enum
240 {
241 NRF_GPIOTE_EVENT_IN_0 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[0]), ///< In event 0.
242 NRF_GPIOTE_EVENT_IN_1 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[1]), ///< In event 1.
243 NRF_GPIOTE_EVENT_IN_2 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[2]), ///< In event 2.
244 NRF_GPIOTE_EVENT_IN_3 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[3]), ///< In event 3.
245 #if (GPIOTE_CH_NUM > 4) || defined(__NRFX_DOXYGEN__)
246 NRF_GPIOTE_EVENT_IN_4 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[4]), ///< In event 4.
247 NRF_GPIOTE_EVENT_IN_5 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[5]), ///< In event 5.
248 NRF_GPIOTE_EVENT_IN_6 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[6]), ///< In event 6.
249 NRF_GPIOTE_EVENT_IN_7 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[7]), ///< In event 7.
250 #endif
251 NRF_GPIOTE_EVENT_PORT = offsetof(NRF_GPIOTE_Type, NRF_GPIOTE_EVENTS_PORT_REG), ///< Port event.
252 } nrf_gpiote_event_t;
253
254 #if defined(__GNUC__)
255 #pragma GCC diagnostic push
256 #pragma GCC diagnostic ignored "-Wpedantic"
257 #endif
258 /** @brief GPIOTE interrupts. */
259 typedef enum
260 {
261 NRF_GPIOTE_INT_IN0_MASK = NRFX_CONCAT(GPIOTE_INTENSET, NRF_GPIOTE_IRQ_GROUP, _IN0_Msk), ///< GPIOTE interrupt from IN0.
262 NRF_GPIOTE_INT_IN1_MASK = NRFX_CONCAT(GPIOTE_INTENSET, NRF_GPIOTE_IRQ_GROUP, _IN1_Msk), ///< GPIOTE interrupt from IN1.
263 NRF_GPIOTE_INT_IN2_MASK = NRFX_CONCAT(GPIOTE_INTENSET, NRF_GPIOTE_IRQ_GROUP, _IN2_Msk), ///< GPIOTE interrupt from IN2.
264 NRF_GPIOTE_INT_IN3_MASK = NRFX_CONCAT(GPIOTE_INTENSET, NRF_GPIOTE_IRQ_GROUP, _IN3_Msk), ///< GPIOTE interrupt from IN3.
265 #if (GPIOTE_CH_NUM > 4) || defined(__NRFX_DOXYGEN__)
266 NRF_GPIOTE_INT_IN4_MASK = NRFX_CONCAT(GPIOTE_INTENSET, NRF_GPIOTE_IRQ_GROUP, _IN4_Msk), ///< GPIOTE interrupt from IN4.
267 NRF_GPIOTE_INT_IN5_MASK = NRFX_CONCAT(GPIOTE_INTENSET, NRF_GPIOTE_IRQ_GROUP, _IN5_Msk), ///< GPIOTE interrupt from IN5.
268 NRF_GPIOTE_INT_IN6_MASK = NRFX_CONCAT(GPIOTE_INTENSET, NRF_GPIOTE_IRQ_GROUP, _IN6_Msk), ///< GPIOTE interrupt from IN6.
269 NRF_GPIOTE_INT_IN7_MASK = NRFX_CONCAT(GPIOTE_INTENSET, NRF_GPIOTE_IRQ_GROUP, _IN7_Msk), ///< GPIOTE interrupt from IN7.
270 #endif
271 #if defined(__CC_ARM) || defined(__NRFX_DOXYGEN__)
272 NRF_GPIOTE_INT_PORT_MASK = (int)NRF_GPIOTE_INT_PORT_MASK_NAME, ///< GPIOTE interrupt from PORT event.
273 #else
274 NRF_GPIOTE_INT_PORT_MASK = NRF_GPIOTE_INT_PORT_MASK_NAME,
275 #endif
276 } nrf_gpiote_int_t;
277
278 #if defined(__GNUC__)
279 #pragma GCC diagnostic pop
280 #endif
281
282 /** @brief Symbol specifying bitmask collecting all IN events interrupts. */
283 #define NRF_GPIOTE_INT_IN_MASK (NRFX_LISTIFY(GPIOTE_CH_NUM, NRF_GPIOTE_INT_IN, (|), _))
284
285 /**
286 * @brief Function for activating the specified GPIOTE task.
287 *
288 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
289 * @param[in] task Task.
290 */
291 NRF_STATIC_INLINE void nrf_gpiote_task_trigger(NRF_GPIOTE_Type * p_reg, nrf_gpiote_task_t task);
292
293 /**
294 * @brief Function for getting the address of the specified GPIOTE task.
295 *
296 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
297 * @param[in] task Task.
298 *
299 * @return Address of the specified task.
300 */
301 NRF_STATIC_INLINE uint32_t nrf_gpiote_task_address_get(NRF_GPIOTE_Type const * p_reg,
302 nrf_gpiote_task_t task);
303
304 /**
305 * @brief Function for getting the state of the specified GPIOTE event.
306 *
307 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
308 * @param[in] event Event.
309 *
310 * @retval true The event is set.
311 * @retval false The event is not set.
312 */
313 NRF_STATIC_INLINE bool nrf_gpiote_event_check(NRF_GPIOTE_Type const * p_reg,
314 nrf_gpiote_event_t event);
315
316 /**
317 * @brief Function for clearing the specified GPIOTE event.
318 *
319 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
320 * @param[in] event Event.
321 */
322 NRF_STATIC_INLINE void nrf_gpiote_event_clear(NRF_GPIOTE_Type * p_reg, nrf_gpiote_event_t event);
323
324 /**
325 * @brief Function for getting the address of the specified GPIOTE event.
326 *
327 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
328 * @param[in] event Event.
329 *
330 * @return Address of the specified event.
331 */
332 NRF_STATIC_INLINE uint32_t nrf_gpiote_event_address_get(NRF_GPIOTE_Type const * p_reg,
333 nrf_gpiote_event_t event);
334
335 /**
336 * @brief Function for enabling interrupts.
337 *
338 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
339 * @param[in] mask Mask of interrupts to be enabled.
340 * Use @ref nrf_gpiote_int_t values for bit masking.
341 */
342 NRF_STATIC_INLINE void nrf_gpiote_int_enable(NRF_GPIOTE_Type * p_reg, uint32_t mask);
343
344 /**
345 * @brief Function for disabling interrupts.
346 *
347 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
348 * @param[in] mask Mask of interrupts to be disabled.
349 * Use @ref nrf_gpiote_int_t values for bit masking.
350 */
351 NRF_STATIC_INLINE void nrf_gpiote_int_disable(NRF_GPIOTE_Type * p_reg, uint32_t mask);
352
353 /**
354 * @brief Function for checking if the specified interrupts are enabled.
355 *
356 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
357 * @param[in] mask Mask of interrupts to be checked.
358 * Use @ref nrf_gpiote_int_t values for bit masking.
359 *
360 * @return Mask of enabled interrupts.
361 */
362 NRF_STATIC_INLINE uint32_t nrf_gpiote_int_enable_check(NRF_GPIOTE_Type const * p_reg,
363 uint32_t mask);
364
365 #if NRF_GPIOTE_HAS_INT_GROUPS
366 /**
367 * @brief Function for enabling interrupts in the specified group.
368 *
369 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
370 * @param[in] group_idx Index of interrupt group to be enabled.
371 * @param[in] mask Mask of interrupts to be enabled.
372 * Use @ref nrf_gpiote_int_t values for bit masking.
373 */
374 NRF_STATIC_INLINE void nrf_gpiote_int_group_enable(NRF_GPIOTE_Type * p_reg,
375 uint8_t group_idx,
376 uint32_t mask);
377
378 /**
379 * @brief Function for disabling interrupts in the specified group.
380 *
381 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
382 * @param[in] group_idx Index of interrupt group to be disabled.
383 * @param[in] mask Mask of interrupts to be disabled.
384 * Use @ref nrf_gpiote_int_t values for bit masking.
385 */
386 NRF_STATIC_INLINE void nrf_gpiote_int_group_disable(NRF_GPIOTE_Type * p_reg,
387 uint8_t group_idx,
388 uint32_t mask);
389
390 /**
391 * @brief Function for checking if the specified interrupts from a given group are enabled.
392 *
393 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
394 * @param[in] group_idx Index of interrupt group to be checked.
395 * @param[in] mask Mask of interrupts to be checked.
396 * Use @ref nrf_gpiote_int_t values for bit masking.
397 *
398 * @return Mask of enabled interrupts.
399 */
400 NRF_STATIC_INLINE uint32_t nrf_gpiote_int_group_enable_check(NRF_GPIOTE_Type const * p_reg,
401 uint8_t group_idx,
402 uint32_t mask);
403 #endif
404
405 #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
406 /**
407 * @brief Function for setting the subscribe configuration for a given
408 * GPIOTE task.
409 *
410 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
411 * @param[in] task Task for which to set the configuration.
412 * @param[in] channel Channel through which to subscribe events.
413 */
414 NRF_STATIC_INLINE void nrf_gpiote_subscribe_set(NRF_GPIOTE_Type * p_reg,
415 nrf_gpiote_task_t task,
416 uint8_t channel);
417
418 /**
419 * @brief Function for clearing the subscribe configuration for a given
420 * GPIOTE task.
421 *
422 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
423 * @param[in] task Task for which to clear the configuration.
424 */
425 NRF_STATIC_INLINE void nrf_gpiote_subscribe_clear(NRF_GPIOTE_Type * p_reg, nrf_gpiote_task_t task);
426
427 /**
428 * @brief Function for setting the publish configuration for a given
429 * GPIOTE event.
430 *
431 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
432 * @param[in] event Event for which to set the configuration.
433 * @param[in] channel Channel through which to publish the event.
434 */
435 NRF_STATIC_INLINE void nrf_gpiote_publish_set(NRF_GPIOTE_Type * p_reg,
436 nrf_gpiote_event_t event,
437 uint8_t channel);
438
439 /**
440 * @brief Function for clearing the publish configuration for a given
441 * GPIOTE event.
442 *
443 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
444 * @param[in] event Event for which to clear the configuration.
445 */
446 NRF_STATIC_INLINE void nrf_gpiote_publish_clear(NRF_GPIOTE_Type * p_reg, nrf_gpiote_event_t event);
447 #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
448
449 /**
450 * @brief Function for enabling a GPIOTE event.
451 *
452 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
453 * @param[in] idx Task-Event index.
454 */
455 NRF_STATIC_INLINE void nrf_gpiote_event_enable(NRF_GPIOTE_Type * p_reg, uint32_t idx);
456
457 /**
458 * @brief Function for disabling a GPIOTE event.
459 *
460 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
461 * @param[in] idx Task-Event index.
462 */
463 NRF_STATIC_INLINE void nrf_gpiote_event_disable(NRF_GPIOTE_Type * p_reg, uint32_t idx);
464
465 /**
466 * @brief Function for configuring a GPIOTE event.
467 *
468 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
469 * @param[in] idx Task-Event index.
470 * @param[in] pin Pin associated with event.
471 * @param[in] polarity Transition that should generate an event.
472 */
473 NRF_STATIC_INLINE void nrf_gpiote_event_configure(NRF_GPIOTE_Type * p_reg,
474 uint32_t idx,
475 uint32_t pin,
476 nrf_gpiote_polarity_t polarity);
477
478 /**
479 * @brief Function for getting the pin associated with a GPIOTE event.
480 *
481 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
482 * @param[in] idx Task-Event index.
483 *
484 * @return Pin number.
485 */
486 NRF_STATIC_INLINE uint32_t nrf_gpiote_event_pin_get(NRF_GPIOTE_Type const * p_reg, uint32_t idx);
487
488 /**
489 * @brief Function for getting the polarity associated with a GPIOTE event.
490 *
491 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
492 * @param[in] idx Task-Event index.
493 *
494 * @return Polarity.
495 */
496 NRF_STATIC_INLINE nrf_gpiote_polarity_t nrf_gpiote_event_polarity_get(NRF_GPIOTE_Type const * p_reg,
497 uint32_t idx);
498
499 /**
500 * @brief Function for enabling a GPIOTE task.
501 *
502 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
503 * @param[in] idx Task-Event index.
504 */
505 NRF_STATIC_INLINE void nrf_gpiote_task_enable(NRF_GPIOTE_Type * p_reg, uint32_t idx);
506
507 /**
508 * @brief Function for disabling a GPIOTE task.
509 *
510 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
511 * @param[in] idx Task-Event index.
512 */
513 NRF_STATIC_INLINE void nrf_gpiote_task_disable(NRF_GPIOTE_Type * p_reg, uint32_t idx);
514
515 /**
516 * @brief Function for configuring a GPIOTE task.
517 *
518 * @note Function is not configuring mode field so task is disabled after this function is called.
519 *
520 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
521 * @param[in] idx Task-Event index.
522 * @param[in] pin Pin associated with event.
523 * @param[in] polarity Transition that should generate an event.
524 * @param[in] init_val Initial value of the pin.
525 */
526 NRF_STATIC_INLINE void nrf_gpiote_task_configure(NRF_GPIOTE_Type * p_reg,
527 uint32_t idx,
528 uint32_t pin,
529 nrf_gpiote_polarity_t polarity,
530 nrf_gpiote_outinit_t init_val);
531
532 /**
533 * @brief Function for forcing the specified state on the pin connected to GPIOTE.
534 *
535 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
536 * @param[in] idx Task-Event index.
537 * @param[in] init_val Pin state.
538 */
539 NRF_STATIC_INLINE void nrf_gpiote_task_force(NRF_GPIOTE_Type * p_reg,
540 uint32_t idx,
541 nrf_gpiote_outinit_t init_val);
542
543 /**
544 * @brief Function for resetting a GPIOTE task event configuration to the default state.
545 *
546 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
547 * @param[in] idx Task-Event index.
548 */
549 NRF_STATIC_INLINE void nrf_gpiote_te_default(NRF_GPIOTE_Type * p_reg, uint32_t idx);
550
551 /**
552 * @brief Function for checking if particular Task-Event is enabled.
553 *
554 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
555 * @param[in] idx Task-Event index.
556 *
557 * @retval true The Task-Event mode is set to Task or Event.
558 * @retval false The Task-Event mode is set to Disabled.
559 */
560 NRF_STATIC_INLINE bool nrf_gpiote_te_is_enabled(NRF_GPIOTE_Type const * p_reg, uint32_t idx);
561
562 /**
563 * @brief Function for getting the OUT task associated with the specified GPIOTE channel.
564 *
565 * @param[in] index Channel index.
566 *
567 * @return Requested OUT task.
568 */
569 NRF_STATIC_INLINE nrf_gpiote_task_t nrf_gpiote_out_task_get(uint8_t index);
570
571 #if defined(GPIOTE_FEATURE_SET_PRESENT) || defined(__NRFX_DOXYGEN__)
572 /**
573 * @brief Function for getting the SET task associated with the specified GPIOTE channel.
574 *
575 * @param[in] index Channel index.
576 *
577 * @return Requested SET task.
578 */
579 NRF_STATIC_INLINE nrf_gpiote_task_t nrf_gpiote_set_task_get(uint8_t index);
580 #endif
581
582 #if defined(GPIOTE_FEATURE_CLR_PRESENT) || defined(__NRFX_DOXYGEN__)
583 /**
584 * @brief Function for getting the CLR task associated with the specified GPIOTE channel.
585 *
586 * @param[in] index Channel index.
587 *
588 * @return Requested CLR task.
589 */
590 NRF_STATIC_INLINE nrf_gpiote_task_t nrf_gpiote_clr_task_get(uint8_t index);
591 #endif
592
593 /**
594 * @brief Function for getting the IN event associated with the specified GPIOTE channel.
595 *
596 * @param[in] index Channel index.
597 *
598 * @return Requested IN event.
599 */
600 NRF_STATIC_INLINE nrf_gpiote_event_t nrf_gpiote_in_event_get(uint8_t index);
601
602 #if NRF_GPIOTE_HAS_LATENCY
603 /**
604 * @brief Function for setting the latency setting.
605 *
606 * @note Available for event mode with rising or falling edge detection on the pin.
607 * Toggle task mode can only be used with low latency setting.
608 *
609 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
610 * @param[in] latency Latency setting to be set.
611 */
612 NRF_STATIC_INLINE void nrf_gpiote_latency_set(NRF_GPIOTE_Type * p_reg,
613 nrf_gpiote_latency_t latency);
614
615 /**
616 * @brief Function for retrieving the latency setting.
617 *
618 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
619 *
620 * @return Latency setting.
621 */
622 NRF_STATIC_INLINE nrf_gpiote_latency_t nrf_gpiote_latency_get(NRF_GPIOTE_Type const * p_reg);
623 #endif
624
625 #ifndef NRF_DECLARE_ONLY
626
nrf_gpiote_task_trigger(NRF_GPIOTE_Type * p_reg,nrf_gpiote_task_t task)627 NRF_STATIC_INLINE void nrf_gpiote_task_trigger(NRF_GPIOTE_Type * p_reg, nrf_gpiote_task_t task)
628 {
629 *(volatile uint32_t *)((uint32_t)p_reg + task) = 0x1UL;
630 }
631
nrf_gpiote_task_address_get(NRF_GPIOTE_Type const * p_reg,nrf_gpiote_task_t task)632 NRF_STATIC_INLINE uint32_t nrf_gpiote_task_address_get(NRF_GPIOTE_Type const * p_reg,
633 nrf_gpiote_task_t task)
634 {
635 return ((uint32_t)p_reg + task);
636 }
637
nrf_gpiote_event_check(NRF_GPIOTE_Type const * p_reg,nrf_gpiote_event_t event)638 NRF_STATIC_INLINE bool nrf_gpiote_event_check(NRF_GPIOTE_Type const * p_reg,
639 nrf_gpiote_event_t event)
640 {
641 return nrf_event_check(p_reg, event);
642 }
643
nrf_gpiote_event_clear(NRF_GPIOTE_Type * p_reg,nrf_gpiote_event_t event)644 NRF_STATIC_INLINE void nrf_gpiote_event_clear(NRF_GPIOTE_Type * p_reg, nrf_gpiote_event_t event)
645 {
646 *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
647 nrf_event_readback((void *)nrf_gpiote_event_address_get(p_reg, event));
648 }
649
nrf_gpiote_event_address_get(NRF_GPIOTE_Type const * p_reg,nrf_gpiote_event_t event)650 NRF_STATIC_INLINE uint32_t nrf_gpiote_event_address_get(NRF_GPIOTE_Type const * p_reg,
651 nrf_gpiote_event_t event)
652 {
653 return ((uint32_t)p_reg + event);
654 }
655
nrf_gpiote_int_enable(NRF_GPIOTE_Type * p_reg,uint32_t mask)656 NRF_STATIC_INLINE void nrf_gpiote_int_enable(NRF_GPIOTE_Type * p_reg, uint32_t mask)
657 {
658 p_reg->NRFX_CONCAT_2(INTENSET, NRF_GPIOTE_IRQ_GROUP) = mask;
659 }
660
nrf_gpiote_int_disable(NRF_GPIOTE_Type * p_reg,uint32_t mask)661 NRF_STATIC_INLINE void nrf_gpiote_int_disable(NRF_GPIOTE_Type * p_reg, uint32_t mask)
662 {
663 p_reg->NRFX_CONCAT_2(INTENCLR, NRF_GPIOTE_IRQ_GROUP) = mask;
664 }
665
nrf_gpiote_int_enable_check(NRF_GPIOTE_Type const * p_reg,uint32_t mask)666 NRF_STATIC_INLINE uint32_t nrf_gpiote_int_enable_check(NRF_GPIOTE_Type const * p_reg, uint32_t mask)
667 {
668 return p_reg->NRFX_CONCAT_2(INTENSET, NRF_GPIOTE_IRQ_GROUP) & mask;
669 }
670
671 #if NRF_GPIOTE_HAS_INT_GROUPS
nrf_gpiote_int_group_enable(NRF_GPIOTE_Type * p_reg,uint8_t group_idx,uint32_t mask)672 NRF_STATIC_INLINE void nrf_gpiote_int_group_enable(NRF_GPIOTE_Type * p_reg,
673 uint8_t group_idx,
674 uint32_t mask)
675 {
676 switch (group_idx)
677 {
678 case 0:
679 p_reg->INTENSET0 = mask;
680 break;
681 case 1:
682 p_reg->INTENSET1 = mask;
683 break;
684 #if defined(GPIOTE_INTENSET2_IN0_Msk)
685 case 2:
686 p_reg->INTENSET2 = mask;
687 break;
688 #endif
689 #if defined(GPIOTE_INTENSET3_IN0_Msk)
690 case 3:
691 p_reg->INTENSET3 = mask;
692 break;
693 #endif
694 #if defined(GPIOTE_INTENSET4_IN0_Msk)
695 case 4:
696 p_reg->INTENSET4 = mask;
697 break;
698 #endif
699 #if defined(GPIOTE_INTENSET5_IN0_Msk)
700 case 5:
701 p_reg->INTENSET5 = mask;
702 break;
703 #endif
704 #if defined(GPIOTE_INTENSET6_IN0_Msk)
705 case 6:
706 p_reg->INTENSET6 = mask;
707 break;
708 #endif
709 default:
710 NRFX_ASSERT(false);
711 break;
712 }
713 }
714
nrf_gpiote_int_group_disable(NRF_GPIOTE_Type * p_reg,uint8_t group_idx,uint32_t mask)715 NRF_STATIC_INLINE void nrf_gpiote_int_group_disable(NRF_GPIOTE_Type * p_reg,
716 uint8_t group_idx,
717 uint32_t mask)
718 {
719 switch (group_idx)
720 {
721 case 0:
722 p_reg->INTENCLR0 = mask;
723 break;
724 case 1:
725 p_reg->INTENCLR1 = mask;
726 break;
727 #if defined(GPIOTE_INTENCLR2_IN0_Msk)
728 case 2:
729 p_reg->INTENCLR2 = mask;
730 break;
731 #endif
732 #if defined(GPIOTE_INTENCLR3_IN0_Msk)
733 case 3:
734 p_reg->INTENCLR3 = mask;
735 break;
736 #endif
737 #if defined(GPIOTE_INTENCLR4_IN0_Msk)
738 case 4:
739 p_reg->INTENCLR4 = mask;
740 break;
741 #endif
742 #if defined(GPIOTE_INTENCLR5_IN0_Msk)
743 case 5:
744 p_reg->INTENCLR5 = mask;
745 break;
746 #endif
747 #if defined(GPIOTE_INTENCLR6_IN0_Msk)
748 case 6:
749 p_reg->INTENCLR6 = mask;
750 break;
751 #endif
752 default:
753 NRFX_ASSERT(false);
754 break;
755 }
756 }
757
nrf_gpiote_int_group_enable_check(NRF_GPIOTE_Type const * p_reg,uint8_t group_idx,uint32_t mask)758 NRF_STATIC_INLINE uint32_t nrf_gpiote_int_group_enable_check(NRF_GPIOTE_Type const * p_reg,
759 uint8_t group_idx,
760 uint32_t mask)
761 {
762 switch (group_idx)
763 {
764 case 0:
765 return p_reg->INTENSET0 & mask;
766 case 1:
767 return p_reg->INTENSET1 & mask;
768 #if defined(GPIOTE_INTENSET2_IN0_Msk)
769 case 2:
770 return p_reg->INTENSET2 & mask;
771 #endif
772 #if defined(GPIOTE_INTENSET3_IN0_Msk)
773 case 3:
774 return p_reg->INTENSET3 & mask;
775 #endif
776 #if defined(GPIOTE_INTENSET4_IN0_Msk)
777 case 4:
778 return p_reg->INTENSET4 & mask;
779 #endif
780 #if defined(GPIOTE_INTENSET5_IN0_Msk)
781 case 5:
782 return p_reg->INTENSET5 & mask;
783 #endif
784 #if defined(GPIOTE_INTENSET6_IN0_Msk)
785 case 6:
786 return p_reg->INTENSET6 & mask;
787 #endif
788 default:
789 NRFX_ASSERT(false);
790 return 0;
791 }
792 }
793 #endif
794
795 #if defined(DPPI_PRESENT)
nrf_gpiote_subscribe_set(NRF_GPIOTE_Type * p_reg,nrf_gpiote_task_t task,uint8_t channel)796 NRF_STATIC_INLINE void nrf_gpiote_subscribe_set(NRF_GPIOTE_Type * p_reg,
797 nrf_gpiote_task_t task,
798 uint8_t channel)
799 {
800 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
801 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
802 }
803
nrf_gpiote_subscribe_clear(NRF_GPIOTE_Type * p_reg,nrf_gpiote_task_t task)804 NRF_STATIC_INLINE void nrf_gpiote_subscribe_clear(NRF_GPIOTE_Type * p_reg, nrf_gpiote_task_t task)
805 {
806 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
807 }
808
nrf_gpiote_publish_set(NRF_GPIOTE_Type * p_reg,nrf_gpiote_event_t event,uint8_t channel)809 NRF_STATIC_INLINE void nrf_gpiote_publish_set(NRF_GPIOTE_Type * p_reg,
810 nrf_gpiote_event_t event,
811 uint8_t channel)
812 {
813 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
814 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
815 }
816
nrf_gpiote_publish_clear(NRF_GPIOTE_Type * p_reg,nrf_gpiote_event_t event)817 NRF_STATIC_INLINE void nrf_gpiote_publish_clear(NRF_GPIOTE_Type * p_reg, nrf_gpiote_event_t event)
818 {
819 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
820 }
821 #endif // defined(DPPI_PRESENT)
822
nrf_gpiote_event_enable(NRF_GPIOTE_Type * p_reg,uint32_t idx)823 NRF_STATIC_INLINE void nrf_gpiote_event_enable(NRF_GPIOTE_Type * p_reg, uint32_t idx)
824 {
825 p_reg->CONFIG[idx] |= GPIOTE_CONFIG_MODE_Event;
826 }
827
nrf_gpiote_event_disable(NRF_GPIOTE_Type * p_reg,uint32_t idx)828 NRF_STATIC_INLINE void nrf_gpiote_event_disable(NRF_GPIOTE_Type * p_reg, uint32_t idx)
829 {
830 p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Msk;
831 }
832
nrf_gpiote_event_configure(NRF_GPIOTE_Type * p_reg,uint32_t idx,uint32_t pin,nrf_gpiote_polarity_t polarity)833 NRF_STATIC_INLINE void nrf_gpiote_event_configure(NRF_GPIOTE_Type * p_reg,
834 uint32_t idx,
835 uint32_t pin,
836 nrf_gpiote_polarity_t polarity)
837 {
838 p_reg->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk | GPIOTE_CONFIG_POLARITY_Msk);
839 p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
840 ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk);
841 }
842
nrf_gpiote_event_pin_get(NRF_GPIOTE_Type const * p_reg,uint32_t idx)843 NRF_STATIC_INLINE uint32_t nrf_gpiote_event_pin_get(NRF_GPIOTE_Type const * p_reg, uint32_t idx)
844 {
845 return ((p_reg->CONFIG[idx] & GPIOTE_CONFIG_PORT_PIN_Msk) >> GPIOTE_CONFIG_PSEL_Pos);
846 }
847
nrf_gpiote_event_polarity_get(NRF_GPIOTE_Type const * p_reg,uint32_t idx)848 NRF_STATIC_INLINE nrf_gpiote_polarity_t nrf_gpiote_event_polarity_get(NRF_GPIOTE_Type const * p_reg,
849 uint32_t idx)
850 {
851 return (nrf_gpiote_polarity_t)((p_reg->CONFIG[idx] & GPIOTE_CONFIG_POLARITY_Msk) >>
852 GPIOTE_CONFIG_POLARITY_Pos);
853 }
854
nrf_gpiote_task_enable(NRF_GPIOTE_Type * p_reg,uint32_t idx)855 NRF_STATIC_INLINE void nrf_gpiote_task_enable(NRF_GPIOTE_Type * p_reg, uint32_t idx)
856 {
857 uint32_t final_config = p_reg->CONFIG[idx] | GPIOTE_CONFIG_MODE_Task;
858 #ifdef NRF51
859 /* Workaround for the OUTINIT PAN. When nrf_gpiote_task_config() is called a glitch happens
860 on the GPIO if the GPIO in question is already assigned to GPIOTE and the pin is in the
861 correct state in GPIOTE, but not in the OUT register.
862 Configure channel to not existing, not connected to the pin,
863 and configure as a tasks that will set it to proper level */
864 p_reg->CONFIG[idx] = final_config |
865 (((31) << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk);
866 __NOP();
867 __NOP();
868 __NOP();
869 #endif
870 p_reg->CONFIG[idx] = final_config;
871 }
872
nrf_gpiote_task_disable(NRF_GPIOTE_Type * p_reg,uint32_t idx)873 NRF_STATIC_INLINE void nrf_gpiote_task_disable(NRF_GPIOTE_Type * p_reg, uint32_t idx)
874 {
875 p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Msk;
876 }
877
nrf_gpiote_task_configure(NRF_GPIOTE_Type * p_reg,uint32_t idx,uint32_t pin,nrf_gpiote_polarity_t polarity,nrf_gpiote_outinit_t init_val)878 NRF_STATIC_INLINE void nrf_gpiote_task_configure(NRF_GPIOTE_Type * p_reg,
879 uint32_t idx,
880 uint32_t pin,
881 nrf_gpiote_polarity_t polarity,
882 nrf_gpiote_outinit_t init_val)
883 {
884 p_reg->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk |
885 GPIOTE_CONFIG_POLARITY_Msk |
886 GPIOTE_CONFIG_OUTINIT_Msk);
887
888 p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
889 ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk) |
890 ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk);
891 }
892
nrf_gpiote_task_force(NRF_GPIOTE_Type * p_reg,uint32_t idx,nrf_gpiote_outinit_t init_val)893 NRF_STATIC_INLINE void nrf_gpiote_task_force(NRF_GPIOTE_Type * p_reg,
894 uint32_t idx,
895 nrf_gpiote_outinit_t init_val)
896 {
897 p_reg->CONFIG[idx] = (p_reg->CONFIG[idx] & ~GPIOTE_CONFIG_OUTINIT_Msk) |
898 ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk);
899 }
900
nrf_gpiote_te_default(NRF_GPIOTE_Type * p_reg,uint32_t idx)901 NRF_STATIC_INLINE void nrf_gpiote_te_default(NRF_GPIOTE_Type * p_reg, uint32_t idx)
902 {
903 p_reg->CONFIG[idx] = 0;
904 #if !defined(NRF51_SERIES) && !defined(NRF52_SERIES)
905 p_reg->CONFIG[idx] = 0;
906 #endif
907 }
908
nrf_gpiote_te_is_enabled(NRF_GPIOTE_Type const * p_reg,uint32_t idx)909 NRF_STATIC_INLINE bool nrf_gpiote_te_is_enabled(NRF_GPIOTE_Type const * p_reg, uint32_t idx)
910 {
911 return (p_reg->CONFIG[idx] & GPIOTE_CONFIG_MODE_Msk) != GPIOTE_CONFIG_MODE_Disabled;
912 }
913
nrf_gpiote_out_task_get(uint8_t index)914 NRF_STATIC_INLINE nrf_gpiote_task_t nrf_gpiote_out_task_get(uint8_t index)
915 {
916 NRFX_ASSERT(index < GPIOTE_CH_NUM);
917 return (nrf_gpiote_task_t)NRFX_OFFSETOF(NRF_GPIOTE_Type, TASKS_OUT[index]);
918 }
919
920 #if defined(GPIOTE_FEATURE_SET_PRESENT)
nrf_gpiote_set_task_get(uint8_t index)921 NRF_STATIC_INLINE nrf_gpiote_task_t nrf_gpiote_set_task_get(uint8_t index)
922 {
923 NRFX_ASSERT(index < GPIOTE_CH_NUM);
924 return (nrf_gpiote_task_t)NRFX_OFFSETOF(NRF_GPIOTE_Type, TASKS_SET[index]);
925 }
926 #endif
927
928 #if defined(GPIOTE_FEATURE_CLR_PRESENT)
nrf_gpiote_clr_task_get(uint8_t index)929 NRF_STATIC_INLINE nrf_gpiote_task_t nrf_gpiote_clr_task_get(uint8_t index)
930 {
931 NRFX_ASSERT(index < GPIOTE_CH_NUM);
932 return (nrf_gpiote_task_t)NRFX_OFFSETOF(NRF_GPIOTE_Type, TASKS_CLR[index]);
933 }
934 #endif
935
nrf_gpiote_in_event_get(uint8_t index)936 NRF_STATIC_INLINE nrf_gpiote_event_t nrf_gpiote_in_event_get(uint8_t index)
937 {
938 NRFX_ASSERT(index < GPIOTE_CH_NUM);
939 return (nrf_gpiote_event_t)NRFX_OFFSETOF(NRF_GPIOTE_Type, EVENTS_IN[index]);
940 }
941
942 #if NRF_GPIOTE_HAS_LATENCY
nrf_gpiote_latency_set(NRF_GPIOTE_Type * p_reg,nrf_gpiote_latency_t latency)943 NRF_STATIC_INLINE void nrf_gpiote_latency_set(NRF_GPIOTE_Type * p_reg,
944 nrf_gpiote_latency_t latency)
945 {
946 p_reg->LATENCY = (latency << GPIOTE_LATENCY_LATENCY_Pos) & GPIOTE_LATENCY_LATENCY_Msk;
947 }
948
nrf_gpiote_latency_get(NRF_GPIOTE_Type const * p_reg)949 NRF_STATIC_INLINE nrf_gpiote_latency_t nrf_gpiote_latency_get(NRF_GPIOTE_Type const * p_reg)
950 {
951 return (nrf_gpiote_latency_t)((p_reg->LATENCY & GPIOTE_LATENCY_LATENCY_Msk) >>
952 GPIOTE_LATENCY_LATENCY_Pos);
953 }
954 #endif // NRF_GPIOTE_HAS_LATENCY
955 #endif // NRF_DECLARE_ONLY
956
957 /** @} */
958
959 #ifdef __cplusplus
960 }
961 #endif
962
963 #endif
964
