1 /*
2 * Copyright (c) 2015 - 2024, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_GPIO_H__
35 #define NRF_GPIO_H__
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 #ifndef NRF_P0
44 #define NRF_P0 NRF_GPIO
45 #endif
46
47 #define GPIO_PORT_NUM(periph_name, prefix, i, _) i,
48 #define GPIO_REG(periph_name, prefix, i, _) NRFX_CONCAT(NRF_, periph_name, prefix, i),
49 #define GPIO_NUM_OF_PINS(periph_name, prefix, i, _) \
50 NRFX_CONCAT(periph_name, prefix, i, _PIN_NUM)
51
52 #define GPIO_PORT_NUM_LIST {NRFX_FOREACH_PRESENT(P, GPIO_PORT_NUM, (), (), _)}
53 #define GPIO_REG_LIST {NRFX_FOREACH_PRESENT(P, GPIO_REG, (), (), _)}
54 #define NUMBER_OF_PINS (NRFX_FOREACH_PRESENT(P, GPIO_NUM_OF_PINS, (+), (0), _))
55
56 #if !defined(GPIO_REG_LIST)
57 #error "Not supported."
58 #endif
59
60 #if defined(GPIO_PIN_CNF_DRIVE0_Msk)
61 #define GPIO_PIN_CNF_DRIVE1_OFFSET (GPIO_PIN_CNF_DRIVE1_Pos - GPIO_PIN_CNF_DRIVE0_Pos)
62 #endif
63
64 #if defined(NRF52820_XXAA)
65 #include <nrf_erratas.h>
66 #endif
67
68 /*
69 * Macro for generating case code blocks that return token NRF_<periph_name><prefix><i>
70 * for case value equal to <i>.
71 *
72 * Used by NRF_INTERNAL_GPIO_PORT_EXTRACT.
73 */
74 #define NRF_INTERNAL_GPIO_PORT_EXTRACT_1(periph_name, prefix, i, port) \
75 case i: \
76 port = NRFX_CONCAT(NRF_, periph_name, prefix, i); \
77 break;
78
79 /*
80 * Macro for generating case code blocks for switch statement used in function nrf_gpio_pin_port_decode.
81 * It allows extracting the port number relative to the decoded pin.
82 */
83 #define NRF_INTERNAL_GPIO_PORT_EXTRACT(port) \
84 NRFX_FOREACH_PRESENT(P, NRF_INTERNAL_GPIO_PORT_EXTRACT_1, (), (), port)
85
86 /*
87 * Macro for generating case code blocks that set mask to <periph_name><prefix><i>_FEATURE_PINS_PRESENT
88 * for case value equal to <i>.
89 *
90 * Used by NRF_INTERNAL_GPIO_PORT_MASK_SET.
91 */
92 #define NRF_INTERNAL_GPIO_PORT_MASK_SET_1(periph_name, prefix, i, mask) \
93 case i: \
94 mask = NRFX_CONCAT(periph_name, prefix, i, _FEATURE_PINS_PRESENT); \
95 break;
96
97 /*
98 * Macro for generating case code blocks for switch statement used in function nrf_gpio_pin_present_check.
99 * It allows setting the mask to a value associated with the specific port.
100 */
101 #define NRF_INTERNAL_GPIO_PORT_MASK_SET(mask) \
102 NRFX_FOREACH_PRESENT(P, NRF_INTERNAL_GPIO_PORT_MASK_SET_1, (), (), mask)
103
104 /**
105 * @defgroup nrf_gpio_hal GPIO HAL
106 * @{
107 * @ingroup nrf_gpio
108 * @brief Hardware access layer for managing the GPIO peripheral.
109 */
110
111 #if defined(GPIO_LATCH_PIN0_Msk) || defined(__NRFX_DOXYGEN__)
112 /** @brief Symbol indicating whether the functionality of latching GPIO state change is present. */
113 #define NRF_GPIO_LATCH_PRESENT
114 #endif
115
116 #if defined(GPIO_PIN_CNF_MCUSEL_Msk) || defined(GPIO_PIN_CNF_CTRLSEL_Msk) \
117 || defined(__NRFX_DOXYGEN__)
118 /** @brief Presence of MCU/Subsystem control selection. */
119 #define NRF_GPIO_HAS_SEL 1
120 #else
121 #define NRF_GPIO_HAS_SEL 0
122 #endif
123
124 #if defined(GPIO_PIN_CNF_CTRLSEL_Msk) || defined(__NRFX_DOXYGEN__)
125 /** @brief Presence of MCU/Subsystem control selection for multiple peripherals. */
126 #define NRF_GPIO_HAS_MULTIPERIPH_SEL 1
127 #else
128 #define NRF_GPIO_HAS_MULTIPERIPH_SEL 0
129 #endif
130
131 #if defined(GPIO_PIN_CNF_CLOCKPIN_Msk) || defined(__NRFX_DOXYGEN__)
132 /** @brief Presence of clock pin enable. */
133 #define NRF_GPIO_HAS_CLOCKPIN 1
134 #else
135 #define NRF_GPIO_HAS_CLOCKPIN 0
136 #endif
137
138 #if defined(GPIO_PORTCNF_DRIVECTRL_IMPEDANCE50_Msk) || defined(__NRFX_DOXYGEN__)
139 /** @brief Presence of drive control for impedance. */
140 #define NRF_GPIO_HAS_PORT_IMPEDANCE 1
141 #else
142 #define NRF_GPIO_HAS_PORT_IMPEDANCE 0
143 #endif
144
145 #if defined(GPIO_RETAIN_ResetValue) || defined(__NRFX_DOXYGEN__)
146 /** @brief Presence of register retention. */
147 #define NRF_GPIO_HAS_RETENTION 1
148 #else
149 #define NRF_GPIO_HAS_RETENTION 0
150 #endif
151
152 #if defined(GPIO_DETECTMODE_DETECTMODE_Msk) || defined(__NRFX_DOXYGEN__)
153 /** @brief Presence of detect mode. */
154 #define NRF_GPIO_HAS_DETECT_MODE 1
155 #else
156 #define NRF_GPIO_HAS_DETECT_MODE 0
157 #endif
158
159 /** @brief Macro for mapping port and pin numbers to values understandable for nrf_gpio functions. */
160 #define NRF_GPIO_PIN_MAP(port, pin) NRF_PIN_PORT_TO_PIN_NUMBER(pin, port)
161
162 #if NRF_GPIO_HAS_PORT_IMPEDANCE
163 /** @brief Mask of all impedances. */
164 #define NRF_GPIO_PORT_IMPEDANCE_ALL_MASK (GPIO_PORTCNF_DRIVECTRL_IMPEDANCE50_Msk | \
165 GPIO_PORTCNF_DRIVECTRL_IMPEDANCE100_Msk | \
166 GPIO_PORTCNF_DRIVECTRL_IMPEDANCE200_Msk | \
167 GPIO_PORTCNF_DRIVECTRL_IMPEDANCE400_Msk | \
168 GPIO_PORTCNF_DRIVECTRL_IMPEDANCE800_Msk | \
169 GPIO_PORTCNF_DRIVECTRL_IMPEDANCE1600_Msk)
170 #endif
171
172 /** @brief Pin direction definitions. */
173 typedef enum
174 {
175 NRF_GPIO_PIN_DIR_INPUT = GPIO_PIN_CNF_DIR_Input, ///< Input.
176 NRF_GPIO_PIN_DIR_OUTPUT = GPIO_PIN_CNF_DIR_Output ///< Output.
177 } nrf_gpio_pin_dir_t;
178
179 /** @brief Connection of input buffer. */
180 typedef enum
181 {
182 NRF_GPIO_PIN_INPUT_CONNECT = GPIO_PIN_CNF_INPUT_Connect, ///< Connect input buffer.
183 NRF_GPIO_PIN_INPUT_DISCONNECT = GPIO_PIN_CNF_INPUT_Disconnect ///< Disconnect input buffer.
184 } nrf_gpio_pin_input_t;
185
186 /**
187 * @brief Enumerator used for selecting the pin to be pulled down or up at the time of pin
188 * configuration.
189 */
190 typedef enum
191 {
192 NRF_GPIO_PIN_NOPULL = GPIO_PIN_CNF_PULL_Disabled, ///< Pin pull-up resistor disabled.
193 NRF_GPIO_PIN_PULLDOWN = GPIO_PIN_CNF_PULL_Pulldown, ///< Pin pull-down resistor enabled.
194 NRF_GPIO_PIN_PULLUP = GPIO_PIN_CNF_PULL_Pullup, ///< Pin pull-up resistor enabled.
195 } nrf_gpio_pin_pull_t;
196
197 /** @brief Enumerator used for selecting output drive mode. */
198 typedef enum
199 {
200 #if defined(GPIO_PIN_CNF_DRIVE_Msk) || defined(__NRFX_DOXYGEN__)
201 NRF_GPIO_PIN_S0S1 = GPIO_PIN_CNF_DRIVE_S0S1, ///< Standard '0', standard '1'.
202 NRF_GPIO_PIN_H0S1 = GPIO_PIN_CNF_DRIVE_H0S1, ///< High drive '0', standard '1'.
203 NRF_GPIO_PIN_S0H1 = GPIO_PIN_CNF_DRIVE_S0H1, ///< Standard '0', high drive '1'.
204 NRF_GPIO_PIN_H0H1 = GPIO_PIN_CNF_DRIVE_H0H1, ///< High drive '0', high drive '1'.
205 NRF_GPIO_PIN_D0S1 = GPIO_PIN_CNF_DRIVE_D0S1, ///< Disconnect '0' standard '1'.
206 NRF_GPIO_PIN_D0H1 = GPIO_PIN_CNF_DRIVE_D0H1, ///< Disconnect '0', high drive '1'.
207 NRF_GPIO_PIN_S0D1 = GPIO_PIN_CNF_DRIVE_S0D1, ///< Standard '0', disconnect '1'.
208 NRF_GPIO_PIN_H0D1 = GPIO_PIN_CNF_DRIVE_H0D1, ///< High drive '0', disconnect '1'.
209 #if defined(GPIO_PIN_CNF_DRIVE_E0S1) || defined(__NRFX_DOXYGEN__)
210 NRF_GPIO_PIN_E0S1 = GPIO_PIN_CNF_DRIVE_E0S1, ///< Extra high drive '0', standard '1'.
211 #endif
212 #if defined(GPIO_PIN_CNF_DRIVE_S0E1) || defined(__NRFX_DOXYGEN__)
213 NRF_GPIO_PIN_S0E1 = GPIO_PIN_CNF_DRIVE_S0E1, ///< Standard '0', extra high drive '1'.
214 #endif
215 #if defined(GPIO_PIN_CNF_DRIVE_E0E1) || defined(__NRFX_DOXYGEN__)
216 NRF_GPIO_PIN_E0E1 = GPIO_PIN_CNF_DRIVE_E0E1, ///< Extra high drive '0', extra high drive '1'.
217 #endif
218 #if defined(GPIO_PIN_CNF_DRIVE_E0H1) || defined(__NRFX_DOXYGEN__)
219 NRF_GPIO_PIN_E0H1 = GPIO_PIN_CNF_DRIVE_E0H1, ///< Extra high drive '0', high drive '1'.
220 #endif
221 #if defined(GPIO_PIN_CNF_DRIVE_H0E1) || defined(__NRFX_DOXYGEN__)
222 NRF_GPIO_PIN_H0E1 = GPIO_PIN_CNF_DRIVE_H0E1, ///< High drive '0', extra high drive '1'.
223 #endif
224 #if defined(GPIO_PIN_CNF_DRIVE_D0E1) || defined(__NRFX_DOXYGEN__)
225 NRF_GPIO_PIN_D0E1 = GPIO_PIN_CNF_DRIVE_D0E1, ///< Disconnect '0', extra high drive '1'.
226 #endif
227 #if defined(GPIO_PIN_CNF_DRIVE_E0D1) || defined(__NRFX_DOXYGEN__)
228 NRF_GPIO_PIN_E0D1 = GPIO_PIN_CNF_DRIVE_E0D1, ///< Extra high drive '0', disconnect '1'.
229 #endif
230 #else
231 NRF_GPIO_PIN_S0S1 = GPIO_PIN_CNF_DRIVE0_S0 |
232 (GPIO_PIN_CNF_DRIVE1_S1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
233 NRF_GPIO_PIN_H0S1 = GPIO_PIN_CNF_DRIVE0_H0 |
234 (GPIO_PIN_CNF_DRIVE1_S1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
235 NRF_GPIO_PIN_S0H1 = GPIO_PIN_CNF_DRIVE0_S0 |
236 (GPIO_PIN_CNF_DRIVE1_H1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
237 NRF_GPIO_PIN_H0H1 = GPIO_PIN_CNF_DRIVE0_H0 |
238 (GPIO_PIN_CNF_DRIVE1_H1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
239 NRF_GPIO_PIN_D0S1 = GPIO_PIN_CNF_DRIVE0_D0 |
240 (GPIO_PIN_CNF_DRIVE1_S1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
241 NRF_GPIO_PIN_D0H1 = GPIO_PIN_CNF_DRIVE0_D0 |
242 (GPIO_PIN_CNF_DRIVE1_H1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
243 NRF_GPIO_PIN_S0D1 = GPIO_PIN_CNF_DRIVE0_S0 |
244 (GPIO_PIN_CNF_DRIVE1_D1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
245 NRF_GPIO_PIN_H0D1 = GPIO_PIN_CNF_DRIVE0_H0 |
246 (GPIO_PIN_CNF_DRIVE1_D1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
247 NRF_GPIO_PIN_E0S1 = GPIO_PIN_CNF_DRIVE0_E0 |
248 (GPIO_PIN_CNF_DRIVE1_S1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
249 NRF_GPIO_PIN_S0E1 = GPIO_PIN_CNF_DRIVE0_S0 |
250 (GPIO_PIN_CNF_DRIVE1_E1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
251 NRF_GPIO_PIN_E0E1 = GPIO_PIN_CNF_DRIVE0_E0 |
252 (GPIO_PIN_CNF_DRIVE1_E1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
253 NRF_GPIO_PIN_E0H1 = GPIO_PIN_CNF_DRIVE0_E0 |
254 (GPIO_PIN_CNF_DRIVE1_H1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
255 NRF_GPIO_PIN_H0E1 = GPIO_PIN_CNF_DRIVE0_H0 |
256 (GPIO_PIN_CNF_DRIVE1_E1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
257 NRF_GPIO_PIN_D0E1 = GPIO_PIN_CNF_DRIVE0_D0 |
258 (GPIO_PIN_CNF_DRIVE1_E1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
259 NRF_GPIO_PIN_E0D1 = GPIO_PIN_CNF_DRIVE0_E0 |
260 (GPIO_PIN_CNF_DRIVE1_D1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
261 #endif // defined(GPIO_PIN_CNF_DRIVE_Msk) || defined(__NRFX_DOXYGEN__)
262 } nrf_gpio_pin_drive_t;
263
264 /** @brief Enumerator used for selecting the pin to sense high or low level on the pin input. */
265 typedef enum
266 {
267 NRF_GPIO_PIN_NOSENSE = GPIO_PIN_CNF_SENSE_Disabled, ///< Pin sense level disabled.
268 NRF_GPIO_PIN_SENSE_LOW = GPIO_PIN_CNF_SENSE_Low, ///< Pin sense low level.
269 NRF_GPIO_PIN_SENSE_HIGH = GPIO_PIN_CNF_SENSE_High, ///< Pin sense high level.
270 } nrf_gpio_pin_sense_t;
271
272 #if NRF_GPIO_HAS_SEL
273 /** @brief Enumerator used for selecting the MCU/Subsystem to control the specified pin. */
274 typedef enum
275 {
276 #if defined(GPIO_PIN_CNF_MCUSEL_Msk) || defined(__NRFX_DOXYGEN__)
277 NRF_GPIO_PIN_SEL_APP = GPIO_PIN_CNF_MCUSEL_AppMCU, ///< Pin controlled by Application MCU.
278 NRF_GPIO_PIN_SEL_NETWORK = GPIO_PIN_CNF_MCUSEL_NetworkMCU, ///< Pin controlled by Network MCU.
279 NRF_GPIO_PIN_SEL_PERIPHERAL = GPIO_PIN_CNF_MCUSEL_Peripheral, ///< Pin controlled by dedicated peripheral.
280 #endif
281 #if defined(GPIO_PIN_CNF_MCUSEL_TND) || defined(__NRFX_DOXYGEN__)
282 NRF_GPIO_PIN_SEL_TND = GPIO_PIN_CNF_MCUSEL_TND, ///< Pin controlled by Trace and Debug Subsystem.
283 #elif defined(GPIO_PIN_CNF_CTRLSEL_TND)
284 NRF_GPIO_PIN_SEL_TND = GPIO_PIN_CNF_CTRLSEL_TND, ///< Pin controlled by Trace and Debug Subsystem.
285 #endif
286 #if defined(GPIO_PIN_CNF_CTRLSEL_GPIO) || defined(__NRFX_DOXYGEN__)
287 NRF_GPIO_PIN_SEL_GPIO = GPIO_PIN_CNF_CTRLSEL_GPIO, ///< Pin controlled by GPIO or peripherals with configurable pins.
288 #endif
289 #if defined(GPIO_PIN_CNF_CTRLSEL_VPR) || defined(__NRFX_DOXYGEN__)
290 NRF_GPIO_PIN_SEL_VPR = GPIO_PIN_CNF_CTRLSEL_VPR, ///< Pin controlled by VPR.
291 #endif
292 #if defined(GPIO_PIN_CNF_CTRLSEL_GRTC) || defined(__NRFX_DOXYGEN__)
293 NRF_GPIO_PIN_SEL_GRTC = GPIO_PIN_CNF_CTRLSEL_GRTC, ///< Pin controlled by GRTC peripheral.
294 #endif
295 #if defined(NRF_GPIO_PIN_SEL_EXT)
296 NRF_GPIO_PIN_SEL_EXT
297 #endif
298 } nrf_gpio_pin_sel_t;
299 #endif // NRF_GPIO_HAS_SEL
300
301 #if NRF_GPIO_HAS_PORT_IMPEDANCE
302 /** @brief Port impedance enable mask. */
303 typedef enum
304 {
305 NRF_GPIO_PORT_IMPEDANCE_50_MASK = GPIO_PORTCNF_DRIVECTRL_IMPEDANCE50_Msk, ///< Enable 50 Ohm impedance.
306 NRF_GPIO_PORT_IMPEDANCE_100_MASK = GPIO_PORTCNF_DRIVECTRL_IMPEDANCE100_Msk, ///< Enable 100 Ohm impedance.
307 NRF_GPIO_PORT_IMPEDANCE_200_MASK = GPIO_PORTCNF_DRIVECTRL_IMPEDANCE200_Msk, ///< Enable 200 Ohm impedance.
308 NRF_GPIO_PORT_IMPEDANCE_400_MASK = GPIO_PORTCNF_DRIVECTRL_IMPEDANCE400_Msk, ///< Enable 400 Ohm impedance.
309 NRF_GPIO_PORT_IMPEDANCE_800_MASK = GPIO_PORTCNF_DRIVECTRL_IMPEDANCE800_Msk, ///< Enable 800 Ohm impedance.
310 NRF_GPIO_PORT_IMPEDANCE_1600_MASK = GPIO_PORTCNF_DRIVECTRL_IMPEDANCE1600_Msk, ///< Enable 1600 Ohm impedance.
311 } nrf_gpio_port_impedance_mask_t;
312 #endif
313
314 #if NRF_GPIO_HAS_RETENTION
315 /** @brief Retention enable mask. */
316 typedef enum
317 {
318 #if defined(GPIO_RETAIN_APPLICAION_Msk) || defined(__NRFX_DOXYGEN__)
319 NRF_GPIO_RETAIN_APPLICATION_MASK = GPIO_RETAIN_APPLICAION_Msk, ///< Enable retention for GPIO registers for Application domain
320 #endif
321 #if defined(GPIO_RETAIN_RADIOCORE_Msk) || defined(__NRFX_DOXYGEN__)
322 NRF_GPIO_RETAIN_NETWORK_MASK = GPIO_RETAIN_RADIOCORE_Msk, ///< Enable retention for GPIO registers for Radio core
323 #endif
324 #if defined(GPIO_RETAIN_PIN0_Msk) || defined(__NRFX_DOXYGEN__)
325 NRF_GPIO_RETAIN_PIN0_MASK = GPIO_RETAIN_PIN0_Msk, ///< Enable retention for pin 0.
326 NRF_GPIO_RETAIN_PIN1_MASK = GPIO_RETAIN_PIN1_Msk, ///< Enable retention for pin 1.
327 NRF_GPIO_RETAIN_PIN2_MASK = GPIO_RETAIN_PIN2_Msk, ///< Enable retention for pin 2.
328 NRF_GPIO_RETAIN_PIN3_MASK = GPIO_RETAIN_PIN3_Msk, ///< Enable retention for pin 3.
329 NRF_GPIO_RETAIN_PIN4_MASK = GPIO_RETAIN_PIN4_Msk, ///< Enable retention for pin 4.
330 NRF_GPIO_RETAIN_PIN5_MASK = GPIO_RETAIN_PIN5_Msk, ///< Enable retention for pin 5.
331 NRF_GPIO_RETAIN_PIN6_MASK = GPIO_RETAIN_PIN6_Msk, ///< Enable retention for pin 6.
332 NRF_GPIO_RETAIN_PIN7_MASK = GPIO_RETAIN_PIN7_Msk, ///< Enable retention for pin 7.
333 NRF_GPIO_RETAIN_PIN8_MASK = GPIO_RETAIN_PIN8_Msk, ///< Enable retention for pin 8.
334 NRF_GPIO_RETAIN_PIN9_MASK = GPIO_RETAIN_PIN9_Msk, ///< Enable retention for pin 9.
335 NRF_GPIO_RETAIN_PIN10_MASK = GPIO_RETAIN_PIN10_Msk, ///< Enable retention for pin 10.
336 NRF_GPIO_RETAIN_PIN11_MASK = GPIO_RETAIN_PIN11_Msk, ///< Enable retention for pin 11.
337 NRF_GPIO_RETAIN_PIN12_MASK = GPIO_RETAIN_PIN12_Msk, ///< Enable retention for pin 12.
338 NRF_GPIO_RETAIN_PIN13_MASK = GPIO_RETAIN_PIN13_Msk, ///< Enable retention for pin 13.
339 NRF_GPIO_RETAIN_PIN14_MASK = GPIO_RETAIN_PIN14_Msk, ///< Enable retention for pin 14.
340 NRF_GPIO_RETAIN_PIN15_MASK = GPIO_RETAIN_PIN15_Msk, ///< Enable retention for pin 15.
341 NRF_GPIO_RETAIN_PIN16_MASK = GPIO_RETAIN_PIN16_Msk, ///< Enable retention for pin 16.
342 NRF_GPIO_RETAIN_PIN17_MASK = GPIO_RETAIN_PIN17_Msk, ///< Enable retention for pin 17.
343 NRF_GPIO_RETAIN_PIN18_MASK = GPIO_RETAIN_PIN18_Msk, ///< Enable retention for pin 18.
344 NRF_GPIO_RETAIN_PIN19_MASK = GPIO_RETAIN_PIN19_Msk, ///< Enable retention for pin 19.
345 NRF_GPIO_RETAIN_PIN20_MASK = GPIO_RETAIN_PIN20_Msk, ///< Enable retention for pin 20.
346 NRF_GPIO_RETAIN_PIN21_MASK = GPIO_RETAIN_PIN21_Msk, ///< Enable retention for pin 21.
347 NRF_GPIO_RETAIN_PIN22_MASK = GPIO_RETAIN_PIN22_Msk, ///< Enable retention for pin 22.
348 NRF_GPIO_RETAIN_PIN23_MASK = GPIO_RETAIN_PIN23_Msk, ///< Enable retention for pin 23.
349 NRF_GPIO_RETAIN_PIN24_MASK = GPIO_RETAIN_PIN24_Msk, ///< Enable retention for pin 24.
350 NRF_GPIO_RETAIN_PIN25_MASK = GPIO_RETAIN_PIN25_Msk, ///< Enable retention for pin 25.
351 NRF_GPIO_RETAIN_PIN26_MASK = GPIO_RETAIN_PIN26_Msk, ///< Enable retention for pin 26.
352 NRF_GPIO_RETAIN_PIN27_MASK = GPIO_RETAIN_PIN27_Msk, ///< Enable retention for pin 27.
353 NRF_GPIO_RETAIN_PIN28_MASK = GPIO_RETAIN_PIN28_Msk, ///< Enable retention for pin 28.
354 NRF_GPIO_RETAIN_PIN29_MASK = GPIO_RETAIN_PIN29_Msk, ///< Enable retention for pin 29.
355 NRF_GPIO_RETAIN_PIN30_MASK = GPIO_RETAIN_PIN30_Msk, ///< Enable retention for pin 30.
356 NRF_GPIO_RETAIN_PIN31_MASK = GPIO_RETAIN_PIN31_Msk, ///< Enable retention for pin 31.
357 #endif
358 #if defined(NRF_GPIO_RETAIN_EXT)
359 NRF_GPIO_RETAIN_EXT
360 #endif
361 } nrf_gpio_retain_mask_t;
362 #endif
363
364 /**
365 * @brief Function for configuring the GPIO pin range as output pins with normal drive strength.
366 * This function can be used to configure pin range as simple output with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases).
367 *
368 * @note For configuring only one pin as output, use @ref nrf_gpio_cfg_output.
369 * Sense capability on the pin is disabled and input is disconnected from the buffer as the pins are configured as output.
370 *
371 * @param pin_range_start Specifies the start number (inclusive) in the range of pin numbers to be configured.
372 * @param pin_range_end Specifies the end number (inclusive) in the range of pin numbers to be configured.
373 */
374 NRF_STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end);
375
376 /**
377 * @brief Function for configuring the GPIO pin range as input pins with given initial value set, hiding inner details.
378 * This function can be used to configure pin range as simple input.
379 *
380 * @note For configuring only one pin as input, use @ref nrf_gpio_cfg_input.
381 * Sense capability on the pin is disabled and input is connected to buffer so that the GPIO->IN register is readable.
382 *
383 * @param pin_range_start Specifies the start number (inclusive) in the range of pin numbers to be configured.
384 * @param pin_range_end Specifies the end number (inclusive) in the range of pin numbers to be configured.
385 * @param pull_config State of the pin range pull resistor (no pull, pulled down, or pulled high).
386 */
387 NRF_STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_start,
388 uint32_t pin_range_end,
389 nrf_gpio_pin_pull_t pull_config);
390
391 /**
392 * @brief Pin configuration function.
393 *
394 * The main pin configuration function.
395 * This function allows to set any aspect in PIN_CNF register.
396 *
397 * @param pin_number Specifies the pin number.
398 * @param dir Pin direction.
399 * @param input Connect or disconnect the input buffer.
400 * @param pull Pull configuration.
401 * @param drive Drive configuration.
402 * @param sense Pin sensing mechanism.
403 */
404 NRF_STATIC_INLINE void nrf_gpio_cfg(
405 uint32_t pin_number,
406 nrf_gpio_pin_dir_t dir,
407 nrf_gpio_pin_input_t input,
408 nrf_gpio_pin_pull_t pull,
409 nrf_gpio_pin_drive_t drive,
410 nrf_gpio_pin_sense_t sense);
411
412 /**
413 * @brief Function for reconfiguring pin.
414 *
415 * @note This function selectively updates fields in PIN_CNF register. Reconfiguration
416 * is performed in single register write. Fields for which new configuration is
417 * not provided remain unchanged.
418 *
419 * @param pin_number Specifies the pin number.
420 * @param p_dir Pin direction. If NULL, previous setting remains.
421 * @param p_input Connect or disconnect the input buffer. If NULL, previous setting remains.
422 * @param p_pull Pull configuration. If NULL, previous setting remains.
423 * @param p_drive Drive configuration. If NULL, previous setting remains.
424 * @param p_sense Pin sensing mechanism. If NULL, previous setting remains.
425 */
426 NRF_STATIC_INLINE void nrf_gpio_reconfigure(uint32_t pin_number,
427 const nrf_gpio_pin_dir_t * p_dir,
428 const nrf_gpio_pin_input_t * p_input,
429 const nrf_gpio_pin_pull_t * p_pull,
430 const nrf_gpio_pin_drive_t * p_drive,
431 const nrf_gpio_pin_sense_t * p_sense);
432
433 /**
434 * @brief Function for configuring the given GPIO pin number as output, hiding inner details.
435 * This function can be used to configure a pin as simple output with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases).
436 *
437 * @note Sense capability on the pin is disabled and input is disconnected from the buffer as the pins are configured as output.
438 *
439 * @param pin_number Specifies the pin number.
440 */
441 NRF_STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number);
442
443 /**
444 * @brief Function for configuring the given GPIO pin number as input, hiding inner details.
445 * This function can be used to configure a pin as simple input.
446 *
447 * @note Sense capability on the pin is disabled and input is connected to buffer so that the GPIO->IN register is readable.
448 *
449 * @param pin_number Specifies the pin number.
450 * @param pull_config State of the pin range pull resistor (no pull, pulled down, or pulled high).
451 */
452 NRF_STATIC_INLINE void nrf_gpio_cfg_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config);
453
454 /**
455 * @brief Function for resetting pin configuration to its default state.
456 *
457 * @param pin_number Specifies the pin number.
458 */
459 NRF_STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number);
460
461 /**
462 * @brief Function for configuring the given GPIO pin number as a watcher. Only input is connected.
463 *
464 * @param pin_number Specifies the pin number.
465 *
466 */
467 NRF_STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number);
468
469 /**
470 * @brief Function for disconnecting input for the given GPIO.
471 *
472 * @param pin_number Specifies the pin number.
473 */
474 NRF_STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number);
475
476 /**
477 * @brief Function for configuring the given GPIO pin number as input, hiding inner details.
478 * This function can be used to configure pin range as simple input.
479 * Sense capability on the pin is configurable and input is connected to buffer so that the GPIO->IN register is readable.
480 *
481 * @param pin_number Specifies the pin number.
482 * @param pull_config State of the pin pull resistor (no pull, pulled down, or pulled high).
483 * @param sense_config Sense level of the pin (no sense, sense low, or sense high).
484 */
485 NRF_STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number,
486 nrf_gpio_pin_pull_t pull_config,
487 nrf_gpio_pin_sense_t sense_config);
488
489 /**
490 * @brief Function for configuring sense level for the given GPIO.
491 *
492 * @param pin_number Specifies the pin number.
493 * @param sense_config Sense configuration.
494 */
495 NRF_STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number,
496 nrf_gpio_pin_sense_t sense_config);
497
498 /**
499 * @brief Function for setting the direction for a GPIO pin.
500 *
501 * @param pin_number Specifies the pin number for which to set the direction.
502 * @param direction Specifies the direction.
503 */
504 NRF_STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction);
505
506 /**
507 * @brief Function for setting a GPIO pin.
508 *
509 * @param pin_number Specifies the pin number to be set.
510 */
511 NRF_STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number);
512
513 /**
514 * @brief Function for clearing a GPIO pin.
515 *
516 * @param pin_number Specifies the pin number to clear.
517 */
518 NRF_STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number);
519
520 /**
521 * @brief Function for toggling a GPIO pin.
522 *
523 * @param pin_number Specifies the pin number to toggle.
524 */
525 NRF_STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number);
526
527 /**
528 * @brief Function for writing a value to a GPIO pin.
529 *
530 * @param pin_number Specifies the pin number to write.
531 * @param value Specifies the value to be written to the pin.
532 * @arg 0 Clears the pin.
533 * @arg >=1 Sets the pin.
534 */
535 NRF_STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value);
536
537 /**
538 * @brief Function for reading the input level of a GPIO pin.
539 *
540 * If the value returned by this function is to be valid, the pin's input buffer must be connected.
541 *
542 * @param pin_number Specifies the pin number to read.
543 *
544 * @return 0 if the pin input level is low. Positive value if the pin is high.
545 */
546 NRF_STATIC_INLINE uint32_t nrf_gpio_pin_read(uint32_t pin_number);
547
548 /**
549 * @brief Function for reading the output level of a GPIO pin.
550 *
551 * @param pin_number Specifies the pin number to read.
552 *
553 * @return 0 if the pin output level is low. Positive value if pin output is high.
554 */
555 NRF_STATIC_INLINE uint32_t nrf_gpio_pin_out_read(uint32_t pin_number);
556
557 /**
558 * @brief Function for reading the sense configuration of a GPIO pin.
559 *
560 * @param pin_number Specifies the pin number to read.
561 *
562 * @return Sense configuration.
563 */
564 NRF_STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number);
565
566 /**
567 * @brief Function for reading the direction configuration of a GPIO pin.
568 *
569 * @param pin_number Specifies the pin number to read.
570 *
571 * @return Direction configuration.
572 */
573 NRF_STATIC_INLINE nrf_gpio_pin_dir_t nrf_gpio_pin_dir_get(uint32_t pin_number);
574
575 /**
576 * @brief Function for reading the status of GPIO pin input buffer.
577 *
578 * @param pin_number Pin number to be read.
579 *
580 * @retval Input buffer configuration.
581 */
582 NRF_STATIC_INLINE nrf_gpio_pin_input_t nrf_gpio_pin_input_get(uint32_t pin_number);
583
584 /**
585 * @brief Function for reading the pull configuration of a GPIO pin.
586 *
587 * @param pin_number Specifies the pin number to read.
588 *
589 * @retval Pull configuration.
590 */
591 NRF_STATIC_INLINE nrf_gpio_pin_pull_t nrf_gpio_pin_pull_get(uint32_t pin_number);
592
593 /**
594 * @brief Function for setting output direction on the selected pins on the given port.
595 *
596 * @param p_reg Pointer to the structure of registers of the peripheral.
597 * @param out_mask Mask specifying the pins to set as output.
598 */
599 NRF_STATIC_INLINE void nrf_gpio_port_dir_output_set(NRF_GPIO_Type * p_reg, uint32_t out_mask);
600
601 /**
602 * @brief Function for setting input direction on selected pins on a given port.
603 *
604 * @param p_reg Pointer to the structure of registers of the peripheral.
605 * @param in_mask Mask that specifies the pins to be set as input.
606 */
607 NRF_STATIC_INLINE void nrf_gpio_port_dir_input_set(NRF_GPIO_Type * p_reg, uint32_t in_mask);
608
609 /**
610 * @brief Function for writing the direction configuration of the GPIO pins in the given port.
611 *
612 * @warning This register is retained when retention is enabled.
613 *
614 * @param p_reg Pointer to the structure of registers of the peripheral.
615 * @param dir_mask Mask that specifies the direction of pins. Bit set means that the given pin is configured as output.
616 */
617 NRF_STATIC_INLINE void nrf_gpio_port_dir_write(NRF_GPIO_Type * p_reg, uint32_t dir_mask);
618
619 /**
620 * @brief Function for reading the direction configuration of a GPIO port.
621 *
622 * @warning This register is retained when retention is enabled.
623 *
624 * @param p_reg Pointer to the structure of registers of the peripheral.
625 *
626 * @return Pin configuration of the current direction settings. Bit set means that the given pin is configured as output.
627 */
628 NRF_STATIC_INLINE uint32_t nrf_gpio_port_dir_read(NRF_GPIO_Type const * p_reg);
629
630 /**
631 * @brief Function for reading the input signals of the GPIO pins on the given port.
632 *
633 * @param p_reg Pointer to the peripheral registers structure.
634 *
635 * @return Port input values.
636 */
637 NRF_STATIC_INLINE uint32_t nrf_gpio_port_in_read(NRF_GPIO_Type const * p_reg);
638
639 /**
640 * @brief Function for reading the output signals of the GPIO pins on the given port.
641 *
642 * @warning This register is retained when retention is enabled.
643 *
644 * @param p_reg Pointer to the peripheral registers structure.
645 *
646 * @return Port output values.
647 */
648 NRF_STATIC_INLINE uint32_t nrf_gpio_port_out_read(NRF_GPIO_Type const * p_reg);
649
650 /**
651 * @brief Function for writing the GPIO pins output on a given port.
652 *
653 * @warning This register is retained when retention is enabled.
654 *
655 * @param p_reg Pointer to the structure of registers of the peripheral.
656 * @param value Output port mask.
657 */
658 NRF_STATIC_INLINE void nrf_gpio_port_out_write(NRF_GPIO_Type * p_reg, uint32_t value);
659
660 /**
661 * @brief Function for setting high level on selected the GPIO pins on the given port.
662 *
663 * @param p_reg Pointer to the structure of registers of the peripheral.
664 * @param set_mask Mask with pins to be set as logical high level.
665 */
666 NRF_STATIC_INLINE void nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg, uint32_t set_mask);
667
668 /**
669 * @brief Function for setting low level on selected the GPIO pins on the given port.
670 *
671 * @param p_reg Pointer to the structure of registers of the peripheral.
672 * @param clr_mask Mask with pins to be set as logical low level.
673 */
674 NRF_STATIC_INLINE void nrf_gpio_port_out_clear(NRF_GPIO_Type * p_reg, uint32_t clr_mask);
675
676 /**
677 * @brief Function for reading pin state of multiple consecutive ports.
678 *
679 * @param start_port Index of the first port to read.
680 * @param length Number of ports to read.
681 * @param p_masks Pointer to output array where port states will be stored.
682 */
683 NRF_STATIC_INLINE void nrf_gpio_ports_read(uint32_t start_port,
684 uint32_t length,
685 uint32_t * p_masks);
686
687 #if NRF_GPIO_HAS_PORT_IMPEDANCE
688 /**
689 * @brief Function for setting the impedance matching of the pins on the given port.
690 *
691 * @note Each bit sets certain impedance and have them in parallel when more than one bit is set.
692 * High impedance is set for the pin when all bits are disabled.
693 * When all bits are enabled, the resulting impedance is about 25 Ohm.
694 *
695 * @warning This register is retained when retention is enabled.
696 *
697 * @param p_reg Pointer to the structure of registers of the peripheral.
698 * @param mask Mask of impedances to be set, created using @ref nrf_gpio_port_impedance_mask_t.
699 */
700 NRF_STATIC_INLINE void nrf_gpio_port_impedance_set(NRF_GPIO_Type * p_reg, uint32_t mask);
701
702 /**
703 * @brief Function for geting the impedance matching of the pins on the given port.
704 *
705 * @warning This register is retained when retention is enabled.
706 *
707 * @param p_reg Pointer to the structure of registers of the peripheral.
708 *
709 * @return Mask of impedances set, created using @ref nrf_gpio_port_impedance_mask_t.
710 */
711 NRF_STATIC_INLINE uint32_t nrf_gpio_port_impedance_get(NRF_GPIO_Type const * p_reg);
712 #endif
713
714 #if NRF_GPIO_HAS_RETENTION
715 /**
716 * @brief Function for setting the retention of the registers.
717 *
718 * @param p_reg Pointer to the structure of registers of the peripheral.
719 * @param mask Mask of retention domains to be enabled, created using @ref nrf_gpio_retain_mask_t.
720 */
721 NRF_STATIC_INLINE void nrf_gpio_port_retain_set(NRF_GPIO_Type * p_reg, uint32_t mask);
722
723 /**
724 * @brief Function for geting the retention setting of the registers.
725 *
726 * @param p_reg Pointer to the structure of registers of the peripheral.
727 *
728 * @return Mask of retention domains set, created using @ref nrf_gpio_retain_mask_t.
729 */
730 NRF_STATIC_INLINE uint32_t nrf_gpio_port_retain_get(NRF_GPIO_Type const * p_reg);
731 #endif
732
733 #if NRF_GPIO_HAS_DETECT_MODE
734 /**
735 * @brief Function for setting the latched detect behaviour.
736 *
737 * @param p_reg Pointer to the structure of registers of the peripheral.
738 * @param enable True if the latched LDETECT behaviour is to be used, false if DETECT is to be
739 * directly connected to PIN DETECT signals.
740 */
741 NRF_STATIC_INLINE void nrf_gpio_port_detect_latch_set(NRF_GPIO_Type * p_reg, bool enable);
742
743 /**
744 * @brief Function for checking the latched detect behaviour.
745 *
746 * @param p_reg Pointer to the structure of registers of the peripheral.
747 *
748 * @retval true Latched LDETECT behaviour is used.
749 * @retval false DETECT is directly connected to PIN DETECT signals.
750 */
751 NRF_STATIC_INLINE bool nrf_gpio_port_detect_latch_check(NRF_GPIO_Type const * p_reg);
752 #endif
753
754 #if defined(NRF_GPIO_LATCH_PRESENT)
755 /**
756 * @brief Function for reading latch state of multiple consecutive ports.
757 *
758 * @warning This register is retained when retention is enabled.
759 *
760 * @param start_port Index of the first port to read.
761 * @param length Number of ports to read.
762 * @param p_masks Pointer to output array where latch states will be stored.
763 */
764 NRF_STATIC_INLINE void nrf_gpio_latches_read(uint32_t start_port,
765 uint32_t length,
766 uint32_t * p_masks);
767
768 /**
769 * @brief Function for reading and immediate clearing latch state of multiple consecutive ports.
770 *
771 * @warning This register is retained when retention is enabled.
772 *
773 * @param start_port Index of the first port to read and clear.
774 * @param length Number of ports to read and clear.
775 * @param p_masks Pointer to output array where latch states will be stored.
776 */
777 NRF_STATIC_INLINE void nrf_gpio_latches_read_and_clear(uint32_t start_port,
778 uint32_t length,
779 uint32_t * p_masks);
780
781 /**
782 * @brief Function for reading latch state of single pin.
783 *
784 * @warning This register is retained when retention is enabled.
785 *
786 * @param pin_number Pin number.
787 *
788 * @return 0 if latch is not set. Positive value otherwise.
789 */
790 NRF_STATIC_INLINE uint32_t nrf_gpio_pin_latch_get(uint32_t pin_number);
791
792 /**
793 * @brief Function for clearing latch state of a single pin.
794 *
795 * @warning This register is retained when retention is enabled.
796 *
797 * @param pin_number Pin number.
798 */
799 NRF_STATIC_INLINE void nrf_gpio_pin_latch_clear(uint32_t pin_number);
800 #endif // defined(NRF_GPIO_LATCH_PRESENT)
801
802 #if NRF_GPIO_HAS_SEL
803 /**
804 * @brief Function for selecting the MCU or Subsystem to control a GPIO pin.
805 *
806 * @warning This register is retained when retention is enabled.
807 *
808 * @param pin_number Pin_number.
809 * @param ctrl MCU/Subsystem to control the pin.
810 */
811 NRF_STATIC_INLINE void nrf_gpio_pin_control_select(uint32_t pin_number, nrf_gpio_pin_sel_t ctrl);
812 #endif
813
814 #if NRF_GPIO_HAS_CLOCKPIN
815 /**
816 * @brief Function for setting whether the clock should be enabled for the specified GPIO pin.
817 *
818 * @warning This register is retained when retention is enabled.
819 *
820 * @param[in] pin_number Pin number.
821 * @param[in] enable True if clock is to be enabled, false otherwise.
822 */
823 NRF_STATIC_INLINE void nrf_gpio_pin_clock_set(uint32_t pin_number, bool enable);
824
825 /**
826 * @brief Function for getting the clock enable setting for the specified GPIO pin.
827 *
828 * @warning This register is retained when retention is enabled.
829 *
830 * @param[in] pin_number Pin number.
831 *
832 * @retval true Clock is enabled.
833 * @retval false Clock is disabled.
834 */
835 NRF_STATIC_INLINE bool nrf_gpio_pin_clock_check(uint32_t pin_number);
836 #endif
837
838 /**
839 * @brief Function for checking if provided pin is present on the MCU.
840 *
841 * @param[in] pin_number Number of the pin to be checked.
842 *
843 * @retval true Pin is present.
844 * @retval false Pin is not present.
845 */
846 NRF_STATIC_INLINE bool nrf_gpio_pin_present_check(uint32_t pin_number);
847
848 /**
849 * @brief Function for extracting port number and the relative pin number
850 * from the absolute pin number.
851 *
852 * @param[in,out] p_pin Pointer to the absolute pin number overridden by the pin number
853 * that is relative to the port.
854 *
855 * @return Port number.
856 */
857 NRF_STATIC_INLINE uint32_t nrf_gpio_pin_port_number_extract(uint32_t * p_pin);
858
859 /**
860 * @brief Function for extracting port and the relative pin number from the absolute pin number.
861 *
862 * @param[in,out] p_pin Pointer to the absolute pin number overridden by the pin number
863 * that is relative to the port.
864 *
865 * @return Pointer to port register set.
866 */
867 NRF_STATIC_INLINE NRF_GPIO_Type * nrf_gpio_pin_port_decode(uint32_t * p_pin);
868
869 #ifndef NRF_DECLARE_ONLY
870
nrf_gpio_pin_port_decode(uint32_t * p_pin)871 NRF_STATIC_INLINE NRF_GPIO_Type * nrf_gpio_pin_port_decode(uint32_t * p_pin)
872 {
873 NRFX_ASSERT(nrf_gpio_pin_present_check(*p_pin));
874
875 NRF_GPIO_Type * p_port = NULL;
876
877 switch (nrf_gpio_pin_port_number_extract(p_pin))
878 {
879 NRF_INTERNAL_GPIO_PORT_EXTRACT(p_port);
880
881 default:
882 NRFX_ASSERT(0);
883 }
884 return p_port;
885 }
886
887
nrf_gpio_range_cfg_output(uint32_t pin_range_start,uint32_t pin_range_end)888 NRF_STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end)
889 {
890 for (; pin_range_start <= pin_range_end; pin_range_start++)
891 {
892 nrf_gpio_cfg_output(pin_range_start);
893 }
894 }
895
896
nrf_gpio_range_cfg_input(uint32_t pin_range_start,uint32_t pin_range_end,nrf_gpio_pin_pull_t pull_config)897 NRF_STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_start,
898 uint32_t pin_range_end,
899 nrf_gpio_pin_pull_t pull_config)
900 {
901 for (; pin_range_start <= pin_range_end; pin_range_start++)
902 {
903 nrf_gpio_cfg_input(pin_range_start, pull_config);
904 }
905 }
906
907
nrf_gpio_cfg(uint32_t pin_number,nrf_gpio_pin_dir_t dir,nrf_gpio_pin_input_t input,nrf_gpio_pin_pull_t pull,nrf_gpio_pin_drive_t drive,nrf_gpio_pin_sense_t sense)908 NRF_STATIC_INLINE void nrf_gpio_cfg(
909 uint32_t pin_number,
910 nrf_gpio_pin_dir_t dir,
911 nrf_gpio_pin_input_t input,
912 nrf_gpio_pin_pull_t pull,
913 nrf_gpio_pin_drive_t drive,
914 nrf_gpio_pin_sense_t sense)
915 {
916 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
917 uint32_t cnf = reg->PIN_CNF[pin_number];
918
919 uint32_t to_update = GPIO_PIN_CNF_DIR_Msk |
920 GPIO_PIN_CNF_INPUT_Msk |
921 GPIO_PIN_CNF_PULL_Msk |
922 #if defined(GPIO_PIN_CNF_DRIVE_Msk)
923 GPIO_PIN_CNF_DRIVE_Msk |
924 #else
925 GPIO_PIN_CNF_DRIVE0_Msk |
926 GPIO_PIN_CNF_DRIVE1_Msk |
927 #endif
928 GPIO_PIN_CNF_SENSE_Msk;
929
930 /* Clear fields that will be updated. */
931 cnf &= ~to_update;
932 cnf |= ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos) |
933 ((uint32_t)input << GPIO_PIN_CNF_INPUT_Pos) |
934 ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos) |
935 #if defined(GPIO_PIN_CNF_DRIVE_Pos)
936 ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos) |
937 #else
938 ((uint32_t)drive << GPIO_PIN_CNF_DRIVE0_Pos) |
939 #endif
940 ((uint32_t)sense << GPIO_PIN_CNF_SENSE_Pos);
941
942 reg->PIN_CNF[pin_number] = cnf;
943 }
944
nrf_gpio_reconfigure(uint32_t pin_number,const nrf_gpio_pin_dir_t * p_dir,const nrf_gpio_pin_input_t * p_input,const nrf_gpio_pin_pull_t * p_pull,const nrf_gpio_pin_drive_t * p_drive,const nrf_gpio_pin_sense_t * p_sense)945 NRF_STATIC_INLINE void nrf_gpio_reconfigure(uint32_t pin_number,
946 const nrf_gpio_pin_dir_t * p_dir,
947 const nrf_gpio_pin_input_t * p_input,
948 const nrf_gpio_pin_pull_t * p_pull,
949 const nrf_gpio_pin_drive_t * p_drive,
950 const nrf_gpio_pin_sense_t * p_sense)
951 {
952 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
953 uint32_t cnf = reg->PIN_CNF[pin_number];
954 uint32_t to_update = (p_dir ? GPIO_PIN_CNF_DIR_Msk : 0) |
955 (p_input ? GPIO_PIN_CNF_INPUT_Msk : 0) |
956 (p_pull ? GPIO_PIN_CNF_PULL_Msk : 0) |
957 #if defined(GPIO_PIN_CNF_DRIVE_Msk)
958 (p_drive ? GPIO_PIN_CNF_DRIVE_Msk : 0) |
959 #else
960 (p_drive ? (GPIO_PIN_CNF_DRIVE0_Msk | GPIO_PIN_CNF_DRIVE1_Msk) : 0) |
961 #endif
962 (p_sense ? GPIO_PIN_CNF_SENSE_Msk : 0);
963
964 /* Clear fields that will be updated. */
965 cnf &= ~to_update;
966 cnf |= ((uint32_t)(p_dir ? *p_dir : 0) << GPIO_PIN_CNF_DIR_Pos) |
967 ((uint32_t)(p_input ? *p_input : 0) << GPIO_PIN_CNF_INPUT_Pos) |
968 ((uint32_t)(p_pull ? *p_pull : 0) << GPIO_PIN_CNF_PULL_Pos) |
969 #if defined(GPIO_PIN_CNF_DRIVE_Pos)
970 ((uint32_t)(p_drive ? *p_drive : 0) << GPIO_PIN_CNF_DRIVE_Pos) |
971 #else
972 ((uint32_t)(p_drive ? *p_drive : 0) << GPIO_PIN_CNF_DRIVE0_Pos) |
973 #endif
974 ((uint32_t)(p_sense ? *p_sense : 0)<< GPIO_PIN_CNF_SENSE_Pos);
975
976 reg->PIN_CNF[pin_number] = cnf;
977 }
978
nrf_gpio_cfg_output(uint32_t pin_number)979 NRF_STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number)
980 {
981 nrf_gpio_cfg(
982 pin_number,
983 NRF_GPIO_PIN_DIR_OUTPUT,
984 NRF_GPIO_PIN_INPUT_DISCONNECT,
985 NRF_GPIO_PIN_NOPULL,
986 NRF_GPIO_PIN_S0S1,
987 NRF_GPIO_PIN_NOSENSE);
988 }
989
990
nrf_gpio_cfg_input(uint32_t pin_number,nrf_gpio_pin_pull_t pull_config)991 NRF_STATIC_INLINE void nrf_gpio_cfg_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config)
992 {
993 nrf_gpio_cfg(
994 pin_number,
995 NRF_GPIO_PIN_DIR_INPUT,
996 NRF_GPIO_PIN_INPUT_CONNECT,
997 pull_config,
998 NRF_GPIO_PIN_S0S1,
999 NRF_GPIO_PIN_NOSENSE);
1000 }
1001
1002
nrf_gpio_cfg_default(uint32_t pin_number)1003 NRF_STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number)
1004 {
1005 nrf_gpio_cfg(
1006 pin_number,
1007 NRF_GPIO_PIN_DIR_INPUT,
1008 NRF_GPIO_PIN_INPUT_DISCONNECT,
1009 NRF_GPIO_PIN_NOPULL,
1010 NRF_GPIO_PIN_S0S1,
1011 NRF_GPIO_PIN_NOSENSE);
1012 }
1013
1014
nrf_gpio_cfg_watcher(uint32_t pin_number)1015 NRF_STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number)
1016 {
1017 nrf_gpio_pin_input_t input = NRF_GPIO_PIN_INPUT_CONNECT;
1018
1019 nrf_gpio_reconfigure(pin_number, NULL, &input, NULL, NULL, NULL);
1020 }
1021
1022
nrf_gpio_input_disconnect(uint32_t pin_number)1023 NRF_STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number)
1024 {
1025 nrf_gpio_pin_input_t input = NRF_GPIO_PIN_INPUT_DISCONNECT;
1026
1027 nrf_gpio_reconfigure(pin_number, NULL, &input, NULL, NULL, NULL);
1028 }
1029
1030
nrf_gpio_cfg_sense_input(uint32_t pin_number,nrf_gpio_pin_pull_t pull_config,nrf_gpio_pin_sense_t sense_config)1031 NRF_STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number,
1032 nrf_gpio_pin_pull_t pull_config,
1033 nrf_gpio_pin_sense_t sense_config)
1034 {
1035 nrf_gpio_cfg(
1036 pin_number,
1037 NRF_GPIO_PIN_DIR_INPUT,
1038 NRF_GPIO_PIN_INPUT_CONNECT,
1039 pull_config,
1040 NRF_GPIO_PIN_S0S1,
1041 sense_config);
1042 }
1043
1044
nrf_gpio_cfg_sense_set(uint32_t pin_number,nrf_gpio_pin_sense_t sense_config)1045 NRF_STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number,
1046 nrf_gpio_pin_sense_t sense_config)
1047 {
1048 nrf_gpio_reconfigure(pin_number, NULL, NULL, NULL, NULL, &sense_config);
1049 }
1050
nrf_gpio_pin_dir_set(uint32_t pin_number,nrf_gpio_pin_dir_t direction)1051 NRF_STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction)
1052 {
1053 if (direction == NRF_GPIO_PIN_DIR_INPUT)
1054 {
1055 nrf_gpio_cfg(
1056 pin_number,
1057 NRF_GPIO_PIN_DIR_INPUT,
1058 NRF_GPIO_PIN_INPUT_CONNECT,
1059 NRF_GPIO_PIN_NOPULL,
1060 NRF_GPIO_PIN_S0S1,
1061 NRF_GPIO_PIN_NOSENSE);
1062 }
1063 else
1064 {
1065 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1066 reg->DIRSET = (1UL << pin_number);
1067 }
1068 }
1069
1070
nrf_gpio_pin_set(uint32_t pin_number)1071 NRF_STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number)
1072 {
1073 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1074
1075 nrf_gpio_port_out_set(reg, 1UL << pin_number);
1076 }
1077
1078
nrf_gpio_pin_clear(uint32_t pin_number)1079 NRF_STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number)
1080 {
1081 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1082
1083 nrf_gpio_port_out_clear(reg, 1UL << pin_number);
1084 }
1085
1086
nrf_gpio_pin_toggle(uint32_t pin_number)1087 NRF_STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number)
1088 {
1089 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1090 uint32_t pins_state = reg->OUT;
1091
1092 reg->OUTSET = (~pins_state & (1UL << pin_number));
1093 reg->OUTCLR = (pins_state & (1UL << pin_number));
1094 }
1095
1096
nrf_gpio_pin_write(uint32_t pin_number,uint32_t value)1097 NRF_STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value)
1098 {
1099 if (value == 0)
1100 {
1101 nrf_gpio_pin_clear(pin_number);
1102 }
1103 else
1104 {
1105 nrf_gpio_pin_set(pin_number);
1106 }
1107 }
1108
1109
nrf_gpio_pin_read(uint32_t pin_number)1110 NRF_STATIC_INLINE uint32_t nrf_gpio_pin_read(uint32_t pin_number)
1111 {
1112 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1113
1114 return ((nrf_gpio_port_in_read(reg) >> pin_number) & 1UL);
1115 }
1116
1117
nrf_gpio_pin_out_read(uint32_t pin_number)1118 NRF_STATIC_INLINE uint32_t nrf_gpio_pin_out_read(uint32_t pin_number)
1119 {
1120 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1121
1122 return ((nrf_gpio_port_out_read(reg) >> pin_number) & 1UL);
1123 }
1124
1125
nrf_gpio_pin_sense_get(uint32_t pin_number)1126 NRF_STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number)
1127 {
1128 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1129
1130 return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] &
1131 GPIO_PIN_CNF_SENSE_Msk) >> GPIO_PIN_CNF_SENSE_Pos);
1132 }
1133
1134
nrf_gpio_pin_dir_get(uint32_t pin_number)1135 NRF_STATIC_INLINE nrf_gpio_pin_dir_t nrf_gpio_pin_dir_get(uint32_t pin_number)
1136 {
1137 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1138
1139 return (nrf_gpio_pin_dir_t)((reg->PIN_CNF[pin_number] &
1140 GPIO_PIN_CNF_DIR_Msk) >> GPIO_PIN_CNF_DIR_Pos);
1141 }
1142
nrf_gpio_pin_input_get(uint32_t pin_number)1143 NRF_STATIC_INLINE nrf_gpio_pin_input_t nrf_gpio_pin_input_get(uint32_t pin_number)
1144 {
1145 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1146
1147 return (nrf_gpio_pin_input_t)((reg->PIN_CNF[pin_number] &
1148 GPIO_PIN_CNF_INPUT_Msk) >> GPIO_PIN_CNF_INPUT_Pos);
1149 }
1150
nrf_gpio_pin_pull_get(uint32_t pin_number)1151 NRF_STATIC_INLINE nrf_gpio_pin_pull_t nrf_gpio_pin_pull_get(uint32_t pin_number)
1152 {
1153 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1154
1155 return (nrf_gpio_pin_pull_t)((reg->PIN_CNF[pin_number] &
1156 GPIO_PIN_CNF_PULL_Msk) >> GPIO_PIN_CNF_PULL_Pos);
1157 }
1158
1159
nrf_gpio_port_dir_output_set(NRF_GPIO_Type * p_reg,uint32_t out_mask)1160 NRF_STATIC_INLINE void nrf_gpio_port_dir_output_set(NRF_GPIO_Type * p_reg, uint32_t out_mask)
1161 {
1162 p_reg->DIRSET = out_mask;
1163 }
1164
1165
nrf_gpio_port_dir_input_set(NRF_GPIO_Type * p_reg,uint32_t in_mask)1166 NRF_STATIC_INLINE void nrf_gpio_port_dir_input_set(NRF_GPIO_Type * p_reg, uint32_t in_mask)
1167 {
1168 p_reg->DIRCLR = in_mask;
1169 }
1170
1171
nrf_gpio_port_dir_write(NRF_GPIO_Type * p_reg,uint32_t value)1172 NRF_STATIC_INLINE void nrf_gpio_port_dir_write(NRF_GPIO_Type * p_reg, uint32_t value)
1173 {
1174 p_reg->DIR = value;
1175 }
1176
1177
nrf_gpio_port_dir_read(NRF_GPIO_Type const * p_reg)1178 NRF_STATIC_INLINE uint32_t nrf_gpio_port_dir_read(NRF_GPIO_Type const * p_reg)
1179 {
1180 return p_reg->DIR;
1181 }
1182
1183
nrf_gpio_port_in_read(NRF_GPIO_Type const * p_reg)1184 NRF_STATIC_INLINE uint32_t nrf_gpio_port_in_read(NRF_GPIO_Type const * p_reg)
1185 {
1186 return p_reg->IN;
1187 }
1188
1189
nrf_gpio_port_out_read(NRF_GPIO_Type const * p_reg)1190 NRF_STATIC_INLINE uint32_t nrf_gpio_port_out_read(NRF_GPIO_Type const * p_reg)
1191 {
1192 return p_reg->OUT;
1193 }
1194
1195
nrf_gpio_port_out_write(NRF_GPIO_Type * p_reg,uint32_t value)1196 NRF_STATIC_INLINE void nrf_gpio_port_out_write(NRF_GPIO_Type * p_reg, uint32_t value)
1197 {
1198 p_reg->OUT = value;
1199 }
1200
1201
nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg,uint32_t set_mask)1202 NRF_STATIC_INLINE void nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg, uint32_t set_mask)
1203 {
1204 p_reg->OUTSET = set_mask;
1205 }
1206
1207
nrf_gpio_port_out_clear(NRF_GPIO_Type * p_reg,uint32_t clr_mask)1208 NRF_STATIC_INLINE void nrf_gpio_port_out_clear(NRF_GPIO_Type * p_reg, uint32_t clr_mask)
1209 {
1210 p_reg->OUTCLR = clr_mask;
1211 }
1212
1213
nrf_gpio_ports_read(uint32_t start_port,uint32_t length,uint32_t * p_masks)1214 NRF_STATIC_INLINE void nrf_gpio_ports_read(uint32_t start_port,
1215 uint32_t length,
1216 uint32_t * p_masks)
1217 {
1218 NRF_GPIO_Type * gpio_regs[GPIO_COUNT] = GPIO_REG_LIST;
1219
1220 NRFX_ASSERT(start_port + length <= GPIO_COUNT);
1221 uint32_t i;
1222
1223 for (i = start_port; i < (start_port + length); i++)
1224 {
1225 *p_masks = nrf_gpio_port_in_read(gpio_regs[i]);
1226 p_masks++;
1227 }
1228 }
1229
1230 #if NRF_GPIO_HAS_PORT_IMPEDANCE
nrf_gpio_port_impedance_set(NRF_GPIO_Type * p_reg,uint32_t mask)1231 NRF_STATIC_INLINE void nrf_gpio_port_impedance_set(NRF_GPIO_Type * p_reg, uint32_t mask)
1232 {
1233 p_reg->PORTCNF.DRIVECTRL = ((p_reg->PORTCNF.DRIVECTRL & ~NRF_GPIO_PORT_IMPEDANCE_ALL_MASK) |
1234 (mask & NRF_GPIO_PORT_IMPEDANCE_ALL_MASK));
1235 }
1236
nrf_gpio_port_impedance_get(NRF_GPIO_Type const * p_reg)1237 NRF_STATIC_INLINE uint32_t nrf_gpio_port_impedance_get(NRF_GPIO_Type const * p_reg)
1238 {
1239 return p_reg->PORTCNF.DRIVECTRL & NRF_GPIO_PORT_IMPEDANCE_ALL_MASK;
1240 }
1241 #endif
1242
1243 #if NRF_GPIO_HAS_RETENTION
nrf_gpio_port_retain_set(NRF_GPIO_Type * p_reg,uint32_t mask)1244 NRF_STATIC_INLINE void nrf_gpio_port_retain_set(NRF_GPIO_Type * p_reg, uint32_t mask)
1245 {
1246 p_reg->RETAIN = mask;
1247 }
1248
nrf_gpio_port_retain_get(NRF_GPIO_Type const * p_reg)1249 NRF_STATIC_INLINE uint32_t nrf_gpio_port_retain_get(NRF_GPIO_Type const * p_reg)
1250 {
1251 return p_reg->RETAIN;
1252 }
1253 #endif
1254
1255 #if NRF_GPIO_HAS_DETECT_MODE
nrf_gpio_port_detect_latch_set(NRF_GPIO_Type * p_reg,bool enable)1256 NRF_STATIC_INLINE void nrf_gpio_port_detect_latch_set(NRF_GPIO_Type * p_reg, bool enable)
1257 {
1258 p_reg->DETECTMODE = (enable ? GPIO_DETECTMODE_DETECTMODE_LDETECT :
1259 GPIO_DETECTMODE_DETECTMODE_Default);
1260 }
1261
nrf_gpio_port_detect_latch_check(NRF_GPIO_Type const * p_reg)1262 NRF_STATIC_INLINE bool nrf_gpio_port_detect_latch_check(NRF_GPIO_Type const * p_reg)
1263 {
1264 return (p_reg->DETECTMODE == GPIO_DETECTMODE_DETECTMODE_LDETECT);
1265 }
1266 #endif
1267
1268 #if defined(NRF_GPIO_LATCH_PRESENT)
nrf_gpio_latches_read(uint32_t start_port,uint32_t length,uint32_t * p_masks)1269 NRF_STATIC_INLINE void nrf_gpio_latches_read(uint32_t start_port,
1270 uint32_t length,
1271 uint32_t * p_masks)
1272 {
1273 NRF_GPIO_Type * gpio_regs[GPIO_COUNT] = GPIO_REG_LIST;
1274 uint32_t i;
1275
1276 for (i = start_port; i < (start_port + length); i++)
1277 {
1278 *p_masks = gpio_regs[i]->LATCH;
1279 p_masks++;
1280 }
1281 }
1282
nrf_gpio_latches_read_and_clear(uint32_t start_port,uint32_t length,uint32_t * p_masks)1283 NRF_STATIC_INLINE void nrf_gpio_latches_read_and_clear(uint32_t start_port,
1284 uint32_t length,
1285 uint32_t * p_masks)
1286 {
1287 NRF_GPIO_Type * gpio_regs[GPIO_COUNT] = GPIO_REG_LIST;
1288 uint32_t i;
1289
1290 for (i = start_port; i < (start_port + length); i++)
1291 {
1292 *p_masks = gpio_regs[i]->LATCH;
1293
1294 // The LATCH register is cleared by writing a '1' to the bit that shall be cleared.
1295 gpio_regs[i]->LATCH = *p_masks;
1296
1297 p_masks++;
1298 }
1299 }
1300
nrf_gpio_pin_latch_get(uint32_t pin_number)1301 NRF_STATIC_INLINE uint32_t nrf_gpio_pin_latch_get(uint32_t pin_number)
1302 {
1303 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1304
1305 return (reg->LATCH & (1 << pin_number)) ? 1 : 0;
1306 }
1307
1308
nrf_gpio_pin_latch_clear(uint32_t pin_number)1309 NRF_STATIC_INLINE void nrf_gpio_pin_latch_clear(uint32_t pin_number)
1310 {
1311 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1312
1313 reg->LATCH = (1 << pin_number);
1314 }
1315 #endif // defined(NRF_GPIO_LATCH_PRESENT)
1316
1317 #if NRF_GPIO_HAS_SEL
nrf_gpio_pin_control_select(uint32_t pin_number,nrf_gpio_pin_sel_t ctrl)1318 NRF_STATIC_INLINE void nrf_gpio_pin_control_select(uint32_t pin_number, nrf_gpio_pin_sel_t ctrl)
1319 {
1320 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1321 #if defined(GPIO_PIN_CNF_MCUSEL_Msk)
1322 uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_MCUSEL_Msk;
1323 reg->PIN_CNF[pin_number] = cnf | (ctrl << GPIO_PIN_CNF_MCUSEL_Pos);
1324 #else
1325 uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_CTRLSEL_Msk;
1326 reg->PIN_CNF[pin_number] = cnf | (ctrl << GPIO_PIN_CNF_CTRLSEL_Pos);
1327 #endif
1328 }
1329 #endif // NRF_GPIO_HAS_SEL
1330
1331 #if NRF_GPIO_HAS_CLOCKPIN
nrf_gpio_pin_clock_set(uint32_t pin_number,bool enable)1332 NRF_STATIC_INLINE void nrf_gpio_pin_clock_set(uint32_t pin_number, bool enable)
1333 {
1334 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1335
1336 reg->PIN_CNF[pin_number] = ((reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_CLOCKPIN_Msk) |
1337 ((enable ? GPIO_PIN_CNF_CLOCKPIN_Enabled :
1338 GPIO_PIN_CNF_CLOCKPIN_Disabled) << GPIO_PIN_CNF_CLOCKPIN_Pos));
1339 }
1340
nrf_gpio_pin_clock_check(uint32_t pin_number)1341 NRF_STATIC_INLINE bool nrf_gpio_pin_clock_check(uint32_t pin_number)
1342 {
1343 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1344
1345 return (((reg->PIN_CNF[pin_number] & GPIO_PIN_CNF_CLOCKPIN_Msk) >> GPIO_PIN_CNF_CLOCKPIN_Pos)
1346 == GPIO_PIN_CNF_CLOCKPIN_Enabled);
1347 }
1348 #endif
1349
nrf_gpio_pin_present_check(uint32_t pin_number)1350 NRF_STATIC_INLINE bool nrf_gpio_pin_present_check(uint32_t pin_number)
1351 {
1352 uint32_t port = pin_number >> 5;
1353 uint32_t mask = 0;
1354
1355 switch (port)
1356 {
1357 NRF_INTERNAL_GPIO_PORT_MASK_SET(mask);
1358
1359 default:
1360 return false;
1361 }
1362
1363 #ifdef P0_FEATURE_PINS_PRESENT
1364 #if defined(NRF52820_XXAA) && defined(DEVELOP_IN_NRF52833)
1365 /* Allow use of the following additional GPIOs that are connected to LEDs and buttons
1366 * on the nRF52833 DK:
1367 * - P0.11 - Button 1
1368 * - P0.12 - Button 2
1369 * - P0.13 - LED 1
1370 * - P0.24 - Button 3
1371 * - P0.25 - Button 4
1372 */
1373 mask |= 0x03003800;
1374 #endif // defined(NRF52820_XXAA) && defined(DEVELOP_IN_NRF52833)
1375 #endif
1376
1377 pin_number &= 0x1F;
1378
1379 return (mask & (1UL << pin_number)) ? true : false;
1380 }
1381
nrf_gpio_pin_port_number_extract(uint32_t * p_pin)1382 NRF_STATIC_INLINE uint32_t nrf_gpio_pin_port_number_extract(uint32_t * p_pin)
1383 {
1384 uint32_t pin_number = *p_pin;
1385 *p_pin = NRF_PIN_NUMBER_TO_PIN(pin_number);
1386
1387 return NRF_PIN_NUMBER_TO_PORT(pin_number);
1388 }
1389
1390 #endif // NRF_DECLARE_ONLY
1391
1392 /** @} */
1393
1394 #ifdef __cplusplus
1395 }
1396 #endif
1397
1398 #endif // NRF_GPIO_H__
1399