1 /*
2 * Copyright (c) 2019 - 2024, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_FPU_H__
35 #define NRF_FPU_H__
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /**
44 * @defgroup nrf_fpu_hal FPU HAL
45 * @{
46 * @ingroup nrf_fpu
47 * @brief Hardware access layer (HAL) for managing the Floating Point Unit configuration.
48 */
49
50 /** @brief FPU events. */
51 typedef enum
52 {
53 NRF_FPU_EVENT_INVALIDOPERATION = offsetof(NRF_FPU_Type, EVENTS_INVALIDOPERATION), /**< An FPUIOC exception triggered by an invalid operation has occurred in the FPU. */
54 NRF_FPU_EVENT_DIVIDEBYZERO = offsetof(NRF_FPU_Type, EVENTS_DIVIDEBYZERO), /**< An FPUDZC exception triggered by a floating-point divide-by-zero operation has occurred in the FPU. */
55 NRF_FPU_EVENT_OVERFLOW = offsetof(NRF_FPU_Type, EVENTS_OVERFLOW), /**< An FPUOFC exception triggered by a floating-point overflow has occurred in the FPU. */
56 NRF_FPU_EVENT_UNDERFLOW = offsetof(NRF_FPU_Type, EVENTS_UNDERFLOW), /**< An FPUUFC exception triggered by a floating-point underflow has occurred in the FPU. */
57 NRF_FPU_EVENT_INEXACT = offsetof(NRF_FPU_Type, EVENTS_INEXACT), /**< An FPUIXC exception triggered by an inexact floating-point operation has occurred in the FPU. */
58 NRF_FPU_EVENT_DENORMALINPUT = offsetof(NRF_FPU_Type, EVENTS_DENORMALINPUT), /**< An FPUIDC exception triggered by a denormal floating-point input has occurred in the FPU. */
59 } nrf_fpu_event_t;
60
61 /** @brief FPU interrupts. */
62 typedef enum
63 {
64 NRF_FPU_INT_INVALIDOPERATION = FPU_INTEN_INVALIDOPERATION_Msk, /**< Interrupt on event INVALIDOPERATION. */
65 NRF_FPU_INT_DIVIDEBYZERO = FPU_INTEN_DIVIDEBYZERO_Msk, /**< Interrupt on event DIVIDEBYZERO. */
66 NRF_FPU_INT_OVERFLOW = FPU_INTEN_OVERFLOW_Msk, /**< Interrupt on event OVERFLOW. */
67 NRF_FPU_INT_UNDERFLOW = FPU_INTEN_UNDERFLOW_Msk, /**< Interrupt on event UNDERFLOW. */
68 NRF_FPU_INT_INEXACT = FPU_INTEN_INEXACT_Msk, /**< Interrupt on event INEXACT. */
69 NRF_FPU_INT_DENORMALINPUT = FPU_INTEN_DENORMALINPUT_Msk, /**< Interrupt on event DENORMALINPUT. */
70 } nrf_fpu_int_mask_t;
71
72 /**
73 * @brief Function for clearing the specified FPU event.
74 *
75 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
76 * @param[in] event Event to be cleared.
77 */
78 NRF_STATIC_INLINE void nrf_fpu_event_clear(NRF_FPU_Type * p_reg,
79 nrf_fpu_event_t event);
80
81 /**
82 * @brief Function for retrieving the state of the FPU event.
83 *
84 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
85 * @param[in] event Event to be checked.
86 *
87 * @retval true The event has been generated.
88 * @retval false The event has not been generated.
89 */
90 NRF_STATIC_INLINE bool nrf_fpu_event_check(NRF_FPU_Type const * p_reg,
91 nrf_fpu_event_t event);
92
93 /**
94 * @brief Function for enabling specified interrupts.
95 *
96 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
97 * @param[in] mask Mask of interrupts to be enabled.
98 * Use @ref nrf_fpu_int_mask_t values for bit masking.
99 */
100 NRF_STATIC_INLINE void nrf_fpu_int_enable(NRF_FPU_Type * p_reg, uint32_t mask);
101
102 /**
103 * @brief Function for disabling specified interrupts.
104 *
105 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
106 * @param[in] mask Mask of interrupts to be disabled.
107 * Use @ref nrf_fpu_int_mask_t values for bit masking.
108 */
109 NRF_STATIC_INLINE void nrf_fpu_int_disable(NRF_FPU_Type * p_reg, uint32_t mask);
110
111 /**
112 * @brief Function for checking if the specified interrupts are enabled.
113 *
114 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
115 * @param[in] mask Mask of interrupts to be checked.
116 * Use @ref nrf_fpu_int_mask_t values for bit masking.
117 *
118 * @return Mask of enabled interrupts.
119 */
120 NRF_STATIC_INLINE uint32_t nrf_fpu_int_enable_check(NRF_FPU_Type const * p_reg, uint32_t mask);
121
122 #ifndef NRF_DECLARE_ONLY
123
nrf_fpu_event_clear(NRF_FPU_Type * p_reg,nrf_fpu_event_t event)124 NRF_STATIC_INLINE void nrf_fpu_event_clear(NRF_FPU_Type * p_reg,
125 nrf_fpu_event_t event)
126 {
127 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
128 }
129
nrf_fpu_event_check(NRF_FPU_Type const * p_reg,nrf_fpu_event_t event)130 NRF_STATIC_INLINE bool nrf_fpu_event_check(NRF_FPU_Type const * p_reg,
131 nrf_fpu_event_t event)
132 {
133 return nrf_event_check(p_reg, event);
134 }
135
nrf_fpu_int_enable(NRF_FPU_Type * p_reg,uint32_t mask)136 NRF_STATIC_INLINE void nrf_fpu_int_enable(NRF_FPU_Type * p_reg, uint32_t mask)
137 {
138 p_reg->INTENSET = mask;
139 }
140
nrf_fpu_int_disable(NRF_FPU_Type * p_reg,uint32_t mask)141 NRF_STATIC_INLINE void nrf_fpu_int_disable(NRF_FPU_Type * p_reg, uint32_t mask)
142 {
143 p_reg->INTENCLR = mask;
144 }
145
nrf_fpu_int_enable_check(NRF_FPU_Type const * p_reg,uint32_t mask)146 NRF_STATIC_INLINE uint32_t nrf_fpu_int_enable_check(NRF_FPU_Type const * p_reg, uint32_t mask)
147 {
148 return p_reg->INTENSET & mask;
149 }
150
151 #endif // NRF_DECLARE_ONLY
152
153 /** @} */
154
155 #ifdef __cplusplus
156 }
157 #endif
158
159 #endif // NRF_FPU_H__
160
