1 /*
2 * Copyright (c) 2015 - 2024, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_EGU_H__
35 #define NRF_EGU_H__
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /*
44 * Macro for generating if statement code blocks that allow extracting
45 * the number of channels associated with the specific EGU instance.
46 */
47 #define NRF_INTERNAL_EGU_CHAN_NUM_EXTRACT(chan_num, p_reg) \
48 if (0) {} \
49 NRFX_FOREACH_PRESENT(EGU, NRF_INTERNAL_ELSE_IF_EXTRACT_1, (), (), chan_num, _CH_NUM, p_reg) \
50 else \
51 { \
52 chan_num = 0; \
53 }
54
55 /**
56 * @defgroup nrf_egu_hal EGU HAL
57 * @{
58 * @ingroup nrf_egu
59 * @brief Hardware access layer for managing the Event Generator Unit (EGU) peripheral.
60 */
61
62 /**
63 * @brief Macro getting pointer to the structure of registers of the EGU peripheral.
64 *
65 * @param[in] idx EGU instance index.
66 *
67 * @return Pointer to the structure of registers of the EGU peripheral.
68 */
69 #define NRF_EGU_INST_GET(idx) NRFX_CONCAT(NRF_, EGU, idx)
70
71 /** @brief EGU tasks. */
72 typedef enum
73 {
74 NRF_EGU_TASK_TRIGGER0 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[0]), /**< Trigger 0 for triggering the corresponding TRIGGERED[0] event. */
75 NRF_EGU_TASK_TRIGGER1 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[1]), /**< Trigger 1 for triggering the corresponding TRIGGERED[1] event. */
76 NRF_EGU_TASK_TRIGGER2 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[2]), /**< Trigger 2 for triggering the corresponding TRIGGERED[2] event. */
77 NRF_EGU_TASK_TRIGGER3 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[3]), /**< Trigger 3 for triggering the corresponding TRIGGERED[3] event. */
78 NRF_EGU_TASK_TRIGGER4 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[4]), /**< Trigger 4 for triggering the corresponding TRIGGERED[4] event. */
79 NRF_EGU_TASK_TRIGGER5 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[5]), /**< Trigger 5 for triggering the corresponding TRIGGERED[5] event. */
80 NRF_EGU_TASK_TRIGGER6 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[6]), /**< Trigger 6 for triggering the corresponding TRIGGERED[6] event. */
81 NRF_EGU_TASK_TRIGGER7 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[7]), /**< Trigger 7 for triggering the corresponding TRIGGERED[7] event. */
82 NRF_EGU_TASK_TRIGGER8 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[8]), /**< Trigger 8 for triggering the corresponding TRIGGERED[8] event. */
83 NRF_EGU_TASK_TRIGGER9 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[9]), /**< Trigger 9 for triggering the corresponding TRIGGERED[9] event. */
84 NRF_EGU_TASK_TRIGGER10 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[10]), /**< Trigger 10 for triggering the corresponding TRIGGERED[10] event. */
85 NRF_EGU_TASK_TRIGGER11 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[11]), /**< Trigger 11 for triggering the corresponding TRIGGERED[11] event. */
86 NRF_EGU_TASK_TRIGGER12 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[12]), /**< Trigger 12 for triggering the corresponding TRIGGERED[12] event. */
87 NRF_EGU_TASK_TRIGGER13 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[13]), /**< Trigger 13 for triggering the corresponding TRIGGERED[13] event. */
88 NRF_EGU_TASK_TRIGGER14 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[14]), /**< Trigger 14 for triggering the corresponding TRIGGERED[14] event. */
89 NRF_EGU_TASK_TRIGGER15 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[15]) /**< Trigger 15 for triggering the corresponding TRIGGERED[15] event. */
90 } nrf_egu_task_t;
91
92 /** @brief EGU events. */
93 typedef enum
94 {
95 NRF_EGU_EVENT_TRIGGERED0 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[0]), /**< Event number 0 generated by triggering the corresponding TRIGGER[0] task. */
96 NRF_EGU_EVENT_TRIGGERED1 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[1]), /**< Event number 1 generated by triggering the corresponding TRIGGER[1] task. */
97 NRF_EGU_EVENT_TRIGGERED2 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[2]), /**< Event number 2 generated by triggering the corresponding TRIGGER[2] task. */
98 NRF_EGU_EVENT_TRIGGERED3 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[3]), /**< Event number 3 generated by triggering the corresponding TRIGGER[3] task. */
99 NRF_EGU_EVENT_TRIGGERED4 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[4]), /**< Event number 4 generated by triggering the corresponding TRIGGER[4] task. */
100 NRF_EGU_EVENT_TRIGGERED5 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[5]), /**< Event number 5 generated by triggering the corresponding TRIGGER[5] task. */
101 NRF_EGU_EVENT_TRIGGERED6 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[6]), /**< Event number 6 generated by triggering the corresponding TRIGGER[6] task. */
102 NRF_EGU_EVENT_TRIGGERED7 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[7]), /**< Event number 7 generated by triggering the corresponding TRIGGER[7] task. */
103 NRF_EGU_EVENT_TRIGGERED8 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[8]), /**< Event number 8 generated by triggering the corresponding TRIGGER[8] task. */
104 NRF_EGU_EVENT_TRIGGERED9 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[9]), /**< Event number 9 generated by triggering the corresponding TRIGGER[9] task. */
105 NRF_EGU_EVENT_TRIGGERED10 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[10]), /**< Event number 10 generated by triggering the corresponding TRIGGER[10] task. */
106 NRF_EGU_EVENT_TRIGGERED11 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[11]), /**< Event number 11 generated by triggering the corresponding TRIGGER[11] task. */
107 NRF_EGU_EVENT_TRIGGERED12 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[12]), /**< Event number 12 generated by triggering the corresponding TRIGGER[12] task. */
108 NRF_EGU_EVENT_TRIGGERED13 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[13]), /**< Event number 13 generated by triggering the corresponding TRIGGER[13] task. */
109 NRF_EGU_EVENT_TRIGGERED14 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[14]), /**< Event number 14 generated by triggering the corresponding TRIGGER[14] task. */
110 NRF_EGU_EVENT_TRIGGERED15 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[15]) /**< Event number 15 generated by triggering the corresponding TRIGGER[15] task. */
111 } nrf_egu_event_t;
112
113 /** @brief EGU interrupts. */
114 typedef enum
115 {
116 NRF_EGU_INT_TRIGGERED0 = EGU_INTENSET_TRIGGERED0_Msk, /**< Interrupt on EVENTS_TRIGGERED[0] event. */
117 NRF_EGU_INT_TRIGGERED1 = EGU_INTENSET_TRIGGERED1_Msk, /**< Interrupt on EVENTS_TRIGGERED[1] event. */
118 NRF_EGU_INT_TRIGGERED2 = EGU_INTENSET_TRIGGERED2_Msk, /**< Interrupt on EVENTS_TRIGGERED[2] event. */
119 NRF_EGU_INT_TRIGGERED3 = EGU_INTENSET_TRIGGERED3_Msk, /**< Interrupt on EVENTS_TRIGGERED[3] event. */
120 NRF_EGU_INT_TRIGGERED4 = EGU_INTENSET_TRIGGERED4_Msk, /**< Interrupt on EVENTS_TRIGGERED[4] event. */
121 NRF_EGU_INT_TRIGGERED5 = EGU_INTENSET_TRIGGERED5_Msk, /**< Interrupt on EVENTS_TRIGGERED[5] event. */
122 NRF_EGU_INT_TRIGGERED6 = EGU_INTENSET_TRIGGERED6_Msk, /**< Interrupt on EVENTS_TRIGGERED[6] event. */
123 NRF_EGU_INT_TRIGGERED7 = EGU_INTENSET_TRIGGERED7_Msk, /**< Interrupt on EVENTS_TRIGGERED[7] event. */
124 NRF_EGU_INT_TRIGGERED8 = EGU_INTENSET_TRIGGERED8_Msk, /**< Interrupt on EVENTS_TRIGGERED[8] event. */
125 NRF_EGU_INT_TRIGGERED9 = EGU_INTENSET_TRIGGERED9_Msk, /**< Interrupt on EVENTS_TRIGGERED[9] event. */
126 NRF_EGU_INT_TRIGGERED10 = EGU_INTENSET_TRIGGERED10_Msk, /**< Interrupt on EVENTS_TRIGGERED[10] event. */
127 NRF_EGU_INT_TRIGGERED11 = EGU_INTENSET_TRIGGERED11_Msk, /**< Interrupt on EVENTS_TRIGGERED[11] event. */
128 NRF_EGU_INT_TRIGGERED12 = EGU_INTENSET_TRIGGERED12_Msk, /**< Interrupt on EVENTS_TRIGGERED[12] event. */
129 NRF_EGU_INT_TRIGGERED13 = EGU_INTENSET_TRIGGERED13_Msk, /**< Interrupt on EVENTS_TRIGGERED[13] event. */
130 NRF_EGU_INT_TRIGGERED14 = EGU_INTENSET_TRIGGERED14_Msk, /**< Interrupt on EVENTS_TRIGGERED[14] event. */
131 NRF_EGU_INT_TRIGGERED15 = EGU_INTENSET_TRIGGERED15_Msk, /**< Interrupt on EVENTS_TRIGGERED[15] event. */
132 NRF_EGU_INT_ALL = 0xFFFFuL
133 } nrf_egu_int_mask_t;
134
135
136 /**
137 * @brief Function for getting the maximum channel number of the given EGU.
138 *
139 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
140 *
141 * @return Number of available channels.
142 */
143 NRF_STATIC_INLINE uint32_t nrf_egu_channel_count(NRF_EGU_Type const * p_reg);
144
145 /**
146 * @brief Function for triggering the specified EGU task.
147 *
148 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
149 * @param[in] egu_task EGU task.
150 */
151 NRF_STATIC_INLINE void nrf_egu_task_trigger(NRF_EGU_Type * p_reg, nrf_egu_task_t egu_task);
152
153 /**
154 * @brief Function for returning the address of the specified EGU task register.
155 *
156 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
157 * @param[in] egu_task EGU task.
158 *
159 * @return Address of the specified EGU task register.
160 */
161 NRF_STATIC_INLINE uint32_t nrf_egu_task_address_get(NRF_EGU_Type const * p_reg,
162 nrf_egu_task_t egu_task);
163
164 /**
165 * @brief Function for returning the specified EGU TRIGGER task.
166 *
167 * @param[in] channel Channel number.
168 *
169 * @return The specified EGU TRIGGER task.
170 */
171 NRF_STATIC_INLINE nrf_egu_task_t nrf_egu_trigger_task_get(uint8_t channel);
172
173 /**
174 * @brief Function for retrieving the state of the EGU event.
175 *
176 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
177 * @param[in] egu_event EGU event to be checked.
178 *
179 * @retval true The event has been generated.
180 * @retval false The event has not been generated.
181 */
182 NRF_STATIC_INLINE bool nrf_egu_event_check(NRF_EGU_Type const * p_reg, nrf_egu_event_t egu_event);
183
184 /**
185 * @brief Function for clearing the specified EGU event.
186 *
187 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
188 * @param[in] egu_event EGU event to clear.
189 */
190 NRF_STATIC_INLINE void nrf_egu_event_clear(NRF_EGU_Type * p_reg, nrf_egu_event_t egu_event);
191
192 /**
193 * @brief Function for returning the address of the specified EGU event register.
194 *
195 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
196 * @param[in] egu_event EGU event.
197 *
198 * @return Address of the specified EGU event register.
199 */
200 NRF_STATIC_INLINE uint32_t nrf_egu_event_address_get(NRF_EGU_Type const * p_reg,
201 nrf_egu_event_t egu_event);
202
203 /**
204 * @brief Function for returning the specified EGU TRIGGERED event.
205 *
206 * @param[in] channel Channel number.
207 *
208 * @return The specified EGU TRIGGERED event.
209 */
210 NRF_STATIC_INLINE nrf_egu_event_t nrf_egu_triggered_event_get(uint8_t channel);
211
212 /**
213 * @brief Function for enabling one or more of the EGU interrupts.
214 *
215 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
216 * @param[in] mask Mask of interrupts to be enabled.
217 * Use @ref nrf_egu_int_mask_t values for bit masking.
218 */
219 NRF_STATIC_INLINE void nrf_egu_int_enable(NRF_EGU_Type * p_reg, uint32_t mask);
220
221 /**
222 * @brief Function for retrieving the state of one or more of the EGU interrupts.
223 *
224 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
225 * @param[in] mask Mask of interrupts to be checked.
226 * Use @ref nrf_egu_int_mask_t values for bit masking.
227 *
228 * @return Mask of enabled interrupts.
229 */
230 NRF_STATIC_INLINE uint32_t nrf_egu_int_enable_check(NRF_EGU_Type const * p_reg, uint32_t mask);
231
232 /**
233 * @brief Function for disabling one or more of the EGU interrupts.
234 *
235 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
236 * @param[in] mask Mask of interrupts to be disabled.
237 * Use @ref nrf_egu_int_mask_t values for bit masking.
238 */
239 NRF_STATIC_INLINE void nrf_egu_int_disable(NRF_EGU_Type * p_reg, uint32_t mask);
240
241 /**
242 * @brief Function for retrieving the state of interrupt of the specified EGU channel.
243 *
244 * @param[in] channel Channel number.
245 *
246 * @return EGU interrupt mask.
247 */
248 NRF_STATIC_INLINE nrf_egu_int_mask_t nrf_egu_channel_int_get(uint8_t channel);
249
250 #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
251 /**
252 * @brief Function for setting the subscribe configuration for a given
253 * EGU task.
254 *
255 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
256 * @param[in] task Task for which to set the configuration.
257 * @param[in] channel Channel through which to subscribe events.
258 */
259 NRF_STATIC_INLINE void nrf_egu_subscribe_set(NRF_EGU_Type * p_reg,
260 nrf_egu_task_t task,
261 uint8_t channel);
262
263 /**
264 * @brief Function for clearing the subscribe configuration for a given
265 * EGU task.
266 *
267 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
268 * @param[in] task Task for which to clear the configuration.
269 */
270 NRF_STATIC_INLINE void nrf_egu_subscribe_clear(NRF_EGU_Type * p_reg,
271 nrf_egu_task_t task);
272
273 /**
274 * @brief Function for setting the publish configuration for a given
275 * EGU event.
276 *
277 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
278 * @param[in] event Event for which to set the configuration.
279 * @param[in] channel Channel through which to publish the event.
280 */
281 NRF_STATIC_INLINE void nrf_egu_publish_set(NRF_EGU_Type * p_reg,
282 nrf_egu_event_t event,
283 uint8_t channel);
284
285 /**
286 * @brief Function for clearing the publish configuration for a given
287 * EGU event.
288 *
289 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
290 * @param[in] event Event for which to clear the configuration.
291 */
292 NRF_STATIC_INLINE void nrf_egu_publish_clear(NRF_EGU_Type * p_reg,
293 nrf_egu_event_t event);
294 #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
295
296 #ifndef NRF_DECLARE_ONLY
297
nrf_egu_channel_count(NRF_EGU_Type const * p_reg)298 NRF_STATIC_INLINE uint32_t nrf_egu_channel_count(NRF_EGU_Type const * p_reg)
299 {
300 uint8_t chan_num = 0;
301 NRF_INTERNAL_EGU_CHAN_NUM_EXTRACT(chan_num, p_reg);
302
303 return chan_num;
304 }
305
nrf_egu_task_trigger(NRF_EGU_Type * p_reg,nrf_egu_task_t egu_task)306 NRF_STATIC_INLINE void nrf_egu_task_trigger(NRF_EGU_Type * p_reg, nrf_egu_task_t egu_task)
307 {
308 NRFX_ASSERT(p_reg);
309 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)egu_task)) = 0x1UL;
310 }
311
nrf_egu_task_address_get(NRF_EGU_Type const * p_reg,nrf_egu_task_t egu_task)312 NRF_STATIC_INLINE uint32_t nrf_egu_task_address_get(NRF_EGU_Type const * p_reg,
313 nrf_egu_task_t egu_task)
314 {
315 return nrf_task_event_address_get(p_reg, egu_task);
316 }
317
nrf_egu_trigger_task_get(uint8_t channel)318 NRF_STATIC_INLINE nrf_egu_task_t nrf_egu_trigger_task_get(uint8_t channel)
319 {
320 return (nrf_egu_task_t)NRFX_OFFSETOF(NRF_EGU_Type, TASKS_TRIGGER[channel]);
321 }
322
nrf_egu_event_check(NRF_EGU_Type const * p_reg,nrf_egu_event_t egu_event)323 NRF_STATIC_INLINE bool nrf_egu_event_check(NRF_EGU_Type const * p_reg, nrf_egu_event_t egu_event)
324 {
325 return nrf_event_check(p_reg, egu_event);
326 }
327
nrf_egu_event_clear(NRF_EGU_Type * p_reg,nrf_egu_event_t egu_event)328 NRF_STATIC_INLINE void nrf_egu_event_clear(NRF_EGU_Type * p_reg, nrf_egu_event_t egu_event)
329 {
330 NRFX_ASSERT(p_reg);
331 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)egu_event)) = 0x0UL;
332 nrf_event_readback((uint8_t *)p_reg + (uint32_t)egu_event);
333 }
334
nrf_egu_event_address_get(NRF_EGU_Type const * p_reg,nrf_egu_event_t egu_event)335 NRF_STATIC_INLINE uint32_t nrf_egu_event_address_get(NRF_EGU_Type const * p_reg,
336 nrf_egu_event_t egu_event)
337 {
338 return nrf_task_event_address_get(p_reg, egu_event);
339 }
340
nrf_egu_triggered_event_get(uint8_t channel)341 NRF_STATIC_INLINE nrf_egu_event_t nrf_egu_triggered_event_get(uint8_t channel)
342 {
343 return (nrf_egu_event_t)NRFX_OFFSETOF(NRF_EGU_Type, EVENTS_TRIGGERED[channel]);
344 }
345
nrf_egu_int_enable(NRF_EGU_Type * p_reg,uint32_t mask)346 NRF_STATIC_INLINE void nrf_egu_int_enable(NRF_EGU_Type * p_reg, uint32_t mask)
347 {
348 NRFX_ASSERT(p_reg);
349 p_reg->INTENSET = mask;
350 }
351
nrf_egu_int_enable_check(NRF_EGU_Type const * p_reg,uint32_t mask)352 NRF_STATIC_INLINE uint32_t nrf_egu_int_enable_check(NRF_EGU_Type const * p_reg, uint32_t mask)
353 {
354 NRFX_ASSERT(p_reg);
355 return p_reg->INTENSET & mask;
356 }
357
nrf_egu_int_disable(NRF_EGU_Type * p_reg,uint32_t mask)358 NRF_STATIC_INLINE void nrf_egu_int_disable(NRF_EGU_Type * p_reg, uint32_t mask)
359 {
360 NRFX_ASSERT(p_reg);
361 p_reg->INTENCLR = mask;
362 }
363
nrf_egu_channel_int_get(uint8_t channel)364 NRF_STATIC_INLINE nrf_egu_int_mask_t nrf_egu_channel_int_get(uint8_t channel)
365 {
366 return (nrf_egu_int_mask_t)((uint32_t) (EGU_INTENSET_TRIGGERED0_Msk << channel));
367 }
368
369 #if defined(DPPI_PRESENT)
nrf_egu_subscribe_set(NRF_EGU_Type * p_reg,nrf_egu_task_t task,uint8_t channel)370 NRF_STATIC_INLINE void nrf_egu_subscribe_set(NRF_EGU_Type * p_reg,
371 nrf_egu_task_t task,
372 uint8_t channel)
373 {
374 NRFX_ASSERT(p_reg);
375 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
376 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
377 }
378
nrf_egu_subscribe_clear(NRF_EGU_Type * p_reg,nrf_egu_task_t task)379 NRF_STATIC_INLINE void nrf_egu_subscribe_clear(NRF_EGU_Type * p_reg,
380 nrf_egu_task_t task)
381 {
382 NRFX_ASSERT(p_reg);
383 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
384 }
385
nrf_egu_publish_set(NRF_EGU_Type * p_reg,nrf_egu_event_t event,uint8_t channel)386 NRF_STATIC_INLINE void nrf_egu_publish_set(NRF_EGU_Type * p_reg,
387 nrf_egu_event_t event,
388 uint8_t channel)
389 {
390 NRFX_ASSERT(p_reg);
391 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
392 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
393 }
394
nrf_egu_publish_clear(NRF_EGU_Type * p_reg,nrf_egu_event_t event)395 NRF_STATIC_INLINE void nrf_egu_publish_clear(NRF_EGU_Type * p_reg,
396 nrf_egu_event_t event)
397 {
398 NRFX_ASSERT(p_reg);
399 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
400 }
401 #endif // defined(DPPI_PRESENT)
402
403 #endif // NRF_DECLARE_ONLY
404
405 /** @} */
406
407 #ifdef __cplusplus
408 }
409 #endif
410
411 #endif
412
