1 /*
2 * Copyright (c) 2018 - 2024, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_DPPI_H__
35 #define NRF_DPPI_H__
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /*
44 * Macro for generating if statement code blocks that allow extracting
45 * the number of channels associated with the specific DPPIC instance.
46 */
47 #define NRF_INTERNAL_DPPI_CHAN_NUM_EXTRACT(chan_num, p_reg) \
48 if (0) {} \
49 NRFX_FOREACH_PRESENT(DPPIC, NRF_INTERNAL_ELSE_IF_EXTRACT_1, (), (), chan_num, _CH_NUM, p_reg) \
50 else \
51 { \
52 chan_num = 0; \
53 }
54
55 /*
56 * Macro for generating if statement code blocks that allow extracting
57 * the number of groups associated with the specific DPPIC instance.
58 */
59 #define NRF_INTERNAL_DPPI_GROUP_NUM_EXTRACT(group_num, p_reg) \
60 if (0) {} \
61 NRFX_FOREACH_PRESENT(DPPIC, NRF_INTERNAL_ELSE_IF_EXTRACT_1, (), (), group_num, _GROUP_NUM, p_reg) \
62 else \
63 { \
64 group_num = 0; \
65 }
66
67 /* Symbol specifying the maximal number of channels associated with the DPPIC instances. */
68 #define NRF_DPPI_CH_NUM_MAX \
69 NRFX_MAX_N(NRFX_FOREACH_PRESENT(DPPIC, NRFX_INTERNAL_CHAN_NUM, (), (), _) 0)
70
71 /* Symbol specifying the maximal number of groups associated with the DPPIC instances. */
72 #define NRF_DPPI_GROUP_NUM_MAX \
73 NRFX_MAX_N(NRFX_FOREACH_PRESENT(DPPIC, NRFX_INTERNAL_GROUP_NUM, (), (), _) 0)
74
75 /**
76 * @defgroup nrf_dppi_hal DPPI Controller HAL
77 * @{
78 * @ingroup nrf_dppi
79 * @brief Hardware access layer for managing the Distributed Programmable Peripheral
80 * Interconnect Controller (DPPIC).
81 */
82
83 /**
84 * @brief Macro for setting publish/subscribe register corresponding to specified event/task.
85 *
86 * @param[in] task_or_event Address of the event or task for which publish/subscribe
87 * register is to be set.
88 * @param[in] dppi_chan DPPIC channel number.
89 */
90 #if !defined(NRF_DPPI_ENDPOINT_SETUP)
91 #define NRF_DPPI_ENDPOINT_SETUP(task_or_event, dppi_chan) \
92 (*((volatile uint32_t *)(task_or_event + NRF_SUBSCRIBE_PUBLISH_OFFSET(task_or_event))) = \
93 ((uint32_t)dppi_chan | NRF_SUBSCRIBE_PUBLISH_ENABLE))
94 #endif
95
96 /**
97 * @brief Macro for clearing publish/subscribe register corresponding to specified event/task.
98 *
99 * @param[in] task_or_event Address of the event or task for which publish/subscribe
100 * register is to be cleared.
101 */
102 #if !defined(NRF_DPPI_ENDPOINT_CLEAR)
103 #define NRF_DPPI_ENDPOINT_CLEAR(task_or_event) \
104 (*((volatile uint32_t *)(task_or_event + NRF_SUBSCRIBE_PUBLISH_OFFSET(task_or_event))) = 0)
105 #endif
106
107 /** @brief DPPI channel groups. */
108 typedef enum
109 {
110 NRF_DPPI_CHANNEL_GROUP0 = 0, /**< Channel group 0. */
111 NRF_DPPI_CHANNEL_GROUP1 = 1, /**< Channel group 1. */
112 #if NRF_DPPI_GROUP_NUM_MAX > 2 || defined(__NRFX_DOXYGEN__)
113 NRF_DPPI_CHANNEL_GROUP2 = 2, /**< Channel group 2. */
114 NRF_DPPI_CHANNEL_GROUP3 = 3, /**< Channel group 3. */
115 #endif
116 #if NRF_DPPI_GROUP_NUM_MAX > 4 || defined(__NRFX_DOXYGEN__)
117 NRF_DPPI_CHANNEL_GROUP4 = 4, /**< Channel group 4. */
118 NRF_DPPI_CHANNEL_GROUP5 = 5 /**< Channel group 5. */
119 #endif
120 } nrf_dppi_channel_group_t;
121
122 /** @brief DPPI tasks. */
123 typedef enum
124 {
125 NRF_DPPI_TASK_CHG0_EN = offsetof(NRF_DPPIC_Type, TASKS_CHG[0].EN), /**< Enable channel group 0. */
126 NRF_DPPI_TASK_CHG0_DIS = offsetof(NRF_DPPIC_Type, TASKS_CHG[0].DIS), /**< Disable channel group 0. */
127 NRF_DPPI_TASK_CHG1_EN = offsetof(NRF_DPPIC_Type, TASKS_CHG[1].EN), /**< Enable channel group 1. */
128 NRF_DPPI_TASK_CHG1_DIS = offsetof(NRF_DPPIC_Type, TASKS_CHG[1].DIS), /**< Disable channel group 1. */
129 #if NRF_DPPI_GROUP_NUM_MAX > 2 || defined(__NRFX_DOXYGEN__)
130 NRF_DPPI_TASK_CHG2_EN = offsetof(NRF_DPPIC_Type, TASKS_CHG[2].EN), /**< Enable channel group 2. */
131 NRF_DPPI_TASK_CHG2_DIS = offsetof(NRF_DPPIC_Type, TASKS_CHG[2].DIS), /**< Disable channel group 2. */
132 NRF_DPPI_TASK_CHG3_EN = offsetof(NRF_DPPIC_Type, TASKS_CHG[3].EN), /**< Enable channel group 3. */
133 NRF_DPPI_TASK_CHG3_DIS = offsetof(NRF_DPPIC_Type, TASKS_CHG[3].DIS), /**< Disable channel group 3. */
134 #endif
135 #if NRF_DPPI_GROUP_NUM_MAX > 4 || defined(__NRFX_DOXYGEN__)
136 NRF_DPPI_TASK_CHG4_EN = offsetof(NRF_DPPIC_Type, TASKS_CHG[4].EN), /**< Enable channel group 4. */
137 NRF_DPPI_TASK_CHG4_DIS = offsetof(NRF_DPPIC_Type, TASKS_CHG[4].DIS), /**< Disable channel group 4. */
138 NRF_DPPI_TASK_CHG5_EN = offsetof(NRF_DPPIC_Type, TASKS_CHG[5].EN), /**< Enable channel group 5. */
139 NRF_DPPI_TASK_CHG5_DIS = offsetof(NRF_DPPIC_Type, TASKS_CHG[5].DIS) /**< Disable channel group 5. */
140 #endif
141 } nrf_dppi_task_t;
142
143 /**
144 * @brief Function for getting the total number of available channels for the given DPPIC instance.
145 *
146 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
147 *
148 * @return Number of available channels.
149 */
150 NRF_STATIC_INLINE uint8_t nrf_dppi_channel_number_get(NRF_DPPIC_Type const * p_reg);
151
152 /**
153 * @brief Function for getting the total number of available groups for the given DPPIC instance.
154 *
155 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
156 *
157 * @return Number of available groups.
158 */
159 NRF_STATIC_INLINE uint8_t nrf_dppi_group_number_get(NRF_DPPIC_Type const * p_reg);
160
161 /**
162 * @brief Function for activating a DPPI task.
163 *
164 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
165 * @param[in] dppi_task Task to be activated.
166 */
167 NRF_STATIC_INLINE void nrf_dppi_task_trigger(NRF_DPPIC_Type * p_reg, nrf_dppi_task_t dppi_task);
168
169 /**
170 * @brief Function for getting the address of the specified DPPI task register.
171 *
172 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
173 * @param[in] task Requested task.
174 *
175 * @return Address of the specified task register.
176 */
177 NRF_STATIC_INLINE uint32_t nrf_dppi_task_address_get(NRF_DPPIC_Type const * p_reg,
178 nrf_dppi_task_t task);
179
180 /**
181 * @brief Function for checking the state of a specific DPPI channel.
182 *
183 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
184 * @param[in] channel Channel to be checked.
185 *
186 * @retval true The channel is enabled.
187 * @retval false The channel is not enabled.
188 */
189 NRF_STATIC_INLINE bool nrf_dppi_channel_check(NRF_DPPIC_Type const * p_reg, uint8_t channel);
190
191 /**
192 * @brief Function for enabling multiple DPPI channels.
193 *
194 * The bits in @c mask value correspond to particular channels. It means that
195 * writing 1 to bit 0 enables channel 0, writing 1 to bit 1 enables channel 1 etc.
196 *
197 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
198 * @param[in] mask Channel mask.
199 */
200 NRF_STATIC_INLINE void nrf_dppi_channels_enable(NRF_DPPIC_Type * p_reg, uint32_t mask);
201
202 /**
203 * @brief Function for disabling multiple DPPI channels.
204 *
205 * The bits in @c mask value correspond to particular channels. It means that
206 * writing 1 to bit 0 disables channel 0, writing 1 to bit 1 disables channel 1 etc.
207 *
208 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
209 * @param[in] mask Channel mask.
210 */
211 NRF_STATIC_INLINE void nrf_dppi_channels_disable(NRF_DPPIC_Type * p_reg, uint32_t mask);
212
213 /**
214 * @brief Function for disabling all DPPI channels.
215 *
216 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
217 */
218 NRF_STATIC_INLINE void nrf_dppi_channels_disable_all(NRF_DPPIC_Type * p_reg);
219
220 /**
221 * @brief Function for setting the subscribe configuration for a given
222 * DPPI task.
223 *
224 * @warning After setting the subscription for a given task, channel group configuration
225 * associated with this task cannot be modified until @ref nrf_dppi_subscribe_clear is used.
226 *
227 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
228 * @param[in] task Task for which to set the configuration.
229 * @param[in] channel Channel through which to subscribe events.
230 */
231 NRF_STATIC_INLINE void nrf_dppi_subscribe_set(NRF_DPPIC_Type * p_reg,
232 nrf_dppi_task_t task,
233 uint8_t channel);
234
235 /**
236 * @brief Function for clearing the subscribe configuration for a given
237 * DPPI task.
238 *
239 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
240 * @param[in] task Task for which to clear the configuration.
241 */
242 NRF_STATIC_INLINE void nrf_dppi_subscribe_clear(NRF_DPPIC_Type * p_reg, nrf_dppi_task_t task);
243
244 /**
245 * @brief Function for setting multiple DPPI channels in a channel group.
246 *
247 * @details This function assigns all specified channels to the group.
248 * The bits in @p channel_mask value correspond to particular channels. It means that
249 * writing 1 to bit 0 includes channel 0, writing 1 to bit 1 includes channel 1, and so on.
250 *
251 * @warning All channels included previously will be overwritten.
252 *
253 * @warning Channel group configuration can be modified only if subscriptions for tasks
254 * associated with this group are disabled.
255 *
256 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
257 * @param[in] channel_mask Channels to be assigned in the group.
258 * @param[in] channel_group Channel group.
259 */
260 NRF_STATIC_INLINE void nrf_dppi_channels_group_set(NRF_DPPIC_Type * p_reg,
261 uint32_t channel_mask,
262 nrf_dppi_channel_group_t channel_group);
263
264 /**
265 * @brief Function for including multiple DPPI channels in a channel group.
266 *
267 * @details This function adds all specified channels to the group.
268 * The bits in @p channel_mask value correspond to particular channels. It means that
269 * writing 1 to bit 0 includes channel 0, writing 1 to bit 1 includes channel 1 etc.
270 *
271 * @warning Channel group configuration can be modified only if subscriptions for tasks
272 * associated with this group are disabled.
273 *
274 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
275 * @param[in] channel_mask Channels to be included in the group.
276 * @param[in] channel_group Channel group.
277 */
278 NRF_STATIC_INLINE void nrf_dppi_channels_include_in_group(NRF_DPPIC_Type * p_reg,
279 uint32_t channel_mask,
280 nrf_dppi_channel_group_t channel_group);
281
282 /**
283 * @brief Function for removing multiple DPPI channels from a channel group.
284 *
285 * @details This function removes all specified channels from the group.
286 * The bits in @c channel_mask value correspond to particular channels. It means that
287 * writing 1 to bit 0 removes channel 0, writing 1 to bit 1 removes channel 1 etc.
288 *
289 * @warning Channel group configuration can be modified only if subscriptions for tasks
290 * associated with this group are disabled.
291 *
292 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
293 * @param[in] channel_mask Channels to be removed from the group.
294 * @param[in] channel_group Channel group.
295 */
296 NRF_STATIC_INLINE void nrf_dppi_channels_remove_from_group(NRF_DPPIC_Type * p_reg,
297 uint32_t channel_mask,
298 nrf_dppi_channel_group_t channel_group);
299
300 /**
301 * @brief Function for removing all DPPI channels from a channel group.
302 *
303 * @warning Channel group configuration can be modified only if subscriptions for tasks
304 * associated with this group are disabled.
305 *
306 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
307 * @param[in] group Channel group.
308 */
309 NRF_STATIC_INLINE void nrf_dppi_group_clear(NRF_DPPIC_Type * p_reg,
310 nrf_dppi_channel_group_t group);
311
312 /**
313 * @brief Function for enabling a channel group.
314 *
315 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
316 * @param[in] group Channel group.
317 */
318 NRF_STATIC_INLINE void nrf_dppi_group_enable(NRF_DPPIC_Type * p_reg,
319 nrf_dppi_channel_group_t group);
320
321 /**
322 * @brief Function for disabling a channel group.
323 *
324 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
325 * @param[in] group Channel group.
326 */
327 NRF_STATIC_INLINE void nrf_dppi_group_disable(NRF_DPPIC_Type * p_reg,
328 nrf_dppi_channel_group_t group);
329
330 /**
331 * @brief Function for getting the ENABLE task associated with the specified channel group.
332 *
333 * @param[in] index Channel group index.
334 *
335 * @return Requested ENABLE task.
336 */
337 NRF_STATIC_INLINE nrf_dppi_task_t nrf_dppi_group_enable_task_get(uint8_t index);
338
339 /**
340 * @brief Function for getting the DISABLE task associated with the specified channel group.
341 *
342 * @param[in] index Channel group index.
343 *
344 * @return Requested DISABLE task.
345 */
346 NRF_STATIC_INLINE nrf_dppi_task_t nrf_dppi_group_disable_task_get(uint8_t index);
347
348 #ifndef NRF_DECLARE_ONLY
349
nrf_dppi_channel_number_get(NRF_DPPIC_Type const * p_reg)350 NRF_STATIC_INLINE uint8_t nrf_dppi_channel_number_get(NRF_DPPIC_Type const * p_reg)
351 {
352 uint8_t chan_num = 0;
353 NRF_INTERNAL_DPPI_CHAN_NUM_EXTRACT(chan_num, p_reg);
354 return chan_num;
355 }
356
nrf_dppi_group_number_get(NRF_DPPIC_Type const * p_reg)357 NRF_STATIC_INLINE uint8_t nrf_dppi_group_number_get(NRF_DPPIC_Type const * p_reg)
358 {
359 uint8_t group_num = 0;
360 NRF_INTERNAL_DPPI_GROUP_NUM_EXTRACT(group_num, p_reg);
361 return group_num;
362 }
363
nrf_dppi_task_trigger(NRF_DPPIC_Type * p_reg,nrf_dppi_task_t dppi_task)364 NRF_STATIC_INLINE void nrf_dppi_task_trigger(NRF_DPPIC_Type * p_reg, nrf_dppi_task_t dppi_task)
365 {
366 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) dppi_task)) = 1;
367 }
368
nrf_dppi_task_address_get(NRF_DPPIC_Type const * p_reg,nrf_dppi_task_t task)369 NRF_STATIC_INLINE uint32_t nrf_dppi_task_address_get(NRF_DPPIC_Type const * p_reg,
370 nrf_dppi_task_t task)
371 {
372 return nrf_task_event_address_get(p_reg, task);
373 }
374
nrf_dppi_channel_check(NRF_DPPIC_Type const * p_reg,uint8_t channel)375 NRF_STATIC_INLINE bool nrf_dppi_channel_check(NRF_DPPIC_Type const * p_reg, uint8_t channel)
376 {
377 NRFX_ASSERT(channel < nrf_dppi_channel_number_get(p_reg));
378 return ((p_reg->CHEN & (DPPIC_CHEN_CH0_Enabled << (DPPIC_CHEN_CH0_Pos + channel))) != 0);
379 }
380
nrf_dppi_channels_disable_all(NRF_DPPIC_Type * p_reg)381 NRF_STATIC_INLINE void nrf_dppi_channels_disable_all(NRF_DPPIC_Type * p_reg)
382 {
383 p_reg->CHENCLR = 0xFFFFFFFFuL;
384 }
385
nrf_dppi_channels_enable(NRF_DPPIC_Type * p_reg,uint32_t mask)386 NRF_STATIC_INLINE void nrf_dppi_channels_enable(NRF_DPPIC_Type * p_reg, uint32_t mask)
387 {
388 p_reg->CHENSET = mask;
389 }
390
nrf_dppi_channels_disable(NRF_DPPIC_Type * p_reg,uint32_t mask)391 NRF_STATIC_INLINE void nrf_dppi_channels_disable(NRF_DPPIC_Type * p_reg, uint32_t mask)
392 {
393 p_reg->CHENCLR = mask;
394 }
395
nrf_dppi_subscribe_set(NRF_DPPIC_Type * p_reg,nrf_dppi_task_t task,uint8_t channel)396 NRF_STATIC_INLINE void nrf_dppi_subscribe_set(NRF_DPPIC_Type * p_reg,
397 nrf_dppi_task_t task,
398 uint8_t channel)
399 {
400 NRFX_ASSERT(channel < nrf_dppi_channel_number_get(p_reg));
401 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
402 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
403 }
404
nrf_dppi_subscribe_clear(NRF_DPPIC_Type * p_reg,nrf_dppi_task_t task)405 NRF_STATIC_INLINE void nrf_dppi_subscribe_clear(NRF_DPPIC_Type * p_reg, nrf_dppi_task_t task)
406 {
407 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
408 }
409
nrf_dppi_channels_group_set(NRF_DPPIC_Type * p_reg,uint32_t channel_mask,nrf_dppi_channel_group_t channel_group)410 NRF_STATIC_INLINE void nrf_dppi_channels_group_set(NRF_DPPIC_Type * p_reg,
411 uint32_t channel_mask,
412 nrf_dppi_channel_group_t channel_group)
413 {
414 p_reg->CHG[(uint32_t) channel_group] = channel_mask;
415 }
416
nrf_dppi_channels_include_in_group(NRF_DPPIC_Type * p_reg,uint32_t channel_mask,nrf_dppi_channel_group_t channel_group)417 NRF_STATIC_INLINE void nrf_dppi_channels_include_in_group(NRF_DPPIC_Type * p_reg,
418 uint32_t channel_mask,
419 nrf_dppi_channel_group_t channel_group)
420 {
421 p_reg->CHG[(uint32_t) channel_group] =
422 p_reg->CHG[(uint32_t) channel_group] | (channel_mask);
423 }
424
nrf_dppi_channels_remove_from_group(NRF_DPPIC_Type * p_reg,uint32_t channel_mask,nrf_dppi_channel_group_t channel_group)425 NRF_STATIC_INLINE void nrf_dppi_channels_remove_from_group(NRF_DPPIC_Type * p_reg,
426 uint32_t channel_mask,
427 nrf_dppi_channel_group_t channel_group)
428 {
429 p_reg->CHG[(uint32_t) channel_group] =
430 p_reg->CHG[(uint32_t) channel_group] & ~(channel_mask);
431 }
432
nrf_dppi_group_clear(NRF_DPPIC_Type * p_reg,nrf_dppi_channel_group_t group)433 NRF_STATIC_INLINE void nrf_dppi_group_clear(NRF_DPPIC_Type * p_reg,
434 nrf_dppi_channel_group_t group)
435 {
436 p_reg->CHG[(uint32_t) group] = 0;
437 }
438
nrf_dppi_group_enable(NRF_DPPIC_Type * p_reg,nrf_dppi_channel_group_t group)439 NRF_STATIC_INLINE void nrf_dppi_group_enable(NRF_DPPIC_Type * p_reg, nrf_dppi_channel_group_t group)
440 {
441 p_reg->TASKS_CHG[(uint32_t) group].EN = 1;
442 }
443
nrf_dppi_group_disable(NRF_DPPIC_Type * p_reg,nrf_dppi_channel_group_t group)444 NRF_STATIC_INLINE void nrf_dppi_group_disable(NRF_DPPIC_Type * p_reg,
445 nrf_dppi_channel_group_t group)
446 {
447 p_reg->TASKS_CHG[(uint32_t) group].DIS = 1;
448 }
449
nrf_dppi_group_enable_task_get(uint8_t index)450 NRF_STATIC_INLINE nrf_dppi_task_t nrf_dppi_group_enable_task_get(uint8_t index)
451 {
452 return (nrf_dppi_task_t)NRFX_OFFSETOF(NRF_DPPIC_Type, TASKS_CHG[index].EN);
453 }
454
nrf_dppi_group_disable_task_get(uint8_t index)455 NRF_STATIC_INLINE nrf_dppi_task_t nrf_dppi_group_disable_task_get(uint8_t index)
456 {
457 return (nrf_dppi_task_t)NRFX_OFFSETOF(NRF_DPPIC_Type, TASKS_CHG[index].DIS);
458 }
459
460 #endif // NRF_DECLARE_ONLY
461
462 /** @} */
463
464 #ifdef __cplusplus
465 }
466 #endif
467
468 #endif // NRF_DPPIC_H__
469
