1 /*
2 * Copyright (c) 2023 - 2024, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_CRACEN_H__
35 #define NRF_CRACEN_H__
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /**
44 * @defgroup nrf_cracen_hal CRACEN HAL
45 * @{
46 * @ingroup nrf_cracen
47 * @brief Hardware access layer for managing the Crypto Accelerator Engine (CRACEN) peripheral.
48 */
49
50 /** @brief Number of seed words for private key generation. */
51 #define NRF_CRACEN_SEED_COUNT CRACEN_SEED_MaxCount
52
53 /** @brief CRACEN events. */
54 typedef enum
55 {
56 NRF_CRACEN_EVENT_CRYPTOMASTER = offsetof(NRF_CRACEN_Type, EVENTS_CRYPTOMASTER), ///< Interrupt triggered at Cryptomaster.
57 NRF_CRACEN_EVENT_RNG = offsetof(NRF_CRACEN_Type, EVENTS_RNG), ///< Interrupt triggered at RNG.
58 NRF_CRACEN_EVENT_PKE_IKG = offsetof(NRF_CRACEN_Type, EVENTS_PKEIKG), ///< Interrupt triggered at PKE or IKG.
59 } nrf_cracen_event_t;
60
61 /** @brief CRACEN interrupts. */
62 typedef enum
63 {
64 NRF_CRACEN_INT_CRYPTOMASTER_MASK = CRACEN_INTENSET_CRYPTOMASTER_Msk, ///< Interrupt on CRYPTOMASTER event.
65 NRF_CRACEN_INT_RNG_MASK = CRACEN_INTENSET_RNG_Msk, ///< Interrupt on RNG event.
66 NRF_CRACEN_INT_PKE_IKG_MASK = CRACEN_INTENSET_PKEIKG_Msk, ///< Interrupt on PKEIKG event.
67 } nrf_cracen_int_mask_t;
68
69 /** @brief CRACEN modules mask. */
70 typedef enum
71 {
72 NRF_CRACEN_MODULE_CRYPTOMASTER_MASK = CRACEN_ENABLE_CRYPTOMASTER_Msk, ///< Cryptomaster module.
73 NRF_CRACEN_MODULE_RNG_MASK = CRACEN_ENABLE_RNG_Msk, ///< RNG module.
74 NRF_CRACEN_MODULE_PKE_IKG_MASK = CRACEN_ENABLE_PKEIKG_Msk, ///< PKE and IKG module.
75 } nrf_cracen_module_mask_t;
76
77
78 /**
79 * @brief Function for getting the address of the specified CRACEN event.
80 *
81 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
82 * @param[in] event CRACEN event.
83 *
84 * @return Address of the specified event register.
85 */
86 NRF_STATIC_INLINE uint32_t nrf_cracen_event_address_get(NRF_CRACEN_Type const * p_reg,
87 nrf_cracen_event_t event);
88
89 /**
90 * @brief Function for clearing the specified CRACEN event.
91 *
92 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
93 * @param[in] event CRACEN event to be cleared.
94 */
95 NRF_STATIC_INLINE void nrf_cracen_event_clear(NRF_CRACEN_Type * p_reg,
96 nrf_cracen_event_t event);
97
98 /**
99 * @brief Function for checking the state of the specified CRACEN event.
100 *
101 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
102 * @param[in] event CRACEN event to be checked.
103 *
104 * @retval true The event has been generated.
105 * @retval false The event has not been generated.
106 */
107 NRF_STATIC_INLINE bool nrf_cracen_event_check(NRF_CRACEN_Type const * p_reg,
108 nrf_cracen_event_t event);
109
110 /**
111 * @brief Function for enabling the specified interrupts.
112 *
113 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
114 * @param[in] mask Mask of interrupts to be enabled.
115 * Use @ref nrf_cracen_int_mask_t values for bit masking.
116 */
117 NRF_STATIC_INLINE void nrf_cracen_int_enable(NRF_CRACEN_Type * p_reg, uint32_t mask);
118
119 /**
120 * @brief Function for checking if the specified interrupts are enabled.
121 *
122 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
123 * @param[in] mask Mask of interrupts to be checked.
124 * Use @ref nrf_cracen_int_mask_t values for bit masking.
125 *
126 * @return Mask of enabled interrupts.
127 */
128 NRF_STATIC_INLINE uint32_t nrf_cracen_int_enable_check(NRF_CRACEN_Type const * p_reg, uint32_t mask);
129
130 /**
131 * @brief Function for disabling the specified interrupts.
132 *
133 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
134 * @param[in] mask Mask of interrupts to be disabled.
135 * Use @ref nrf_cracen_int_mask_t values for bit masking.
136 */
137 NRF_STATIC_INLINE void nrf_cracen_int_disable(NRF_CRACEN_Type * p_reg, uint32_t mask);
138
139 /**
140 * @brief Function for enabling CRACEN modules.
141 *
142 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
143 * @param[in] modules Mask of modules to be enabled. See @ref nrf_cracen_module_mask_t.
144 */
145 NRF_STATIC_INLINE void nrf_cracen_module_enable(NRF_CRACEN_Type * p_reg, uint32_t modules);
146
147 /**
148 * @brief Function for disabling CRACEN modules.
149 *
150 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
151 * @param[in] modules Mask of modules to be disabled. See @ref nrf_cracen_module_mask_t.
152 */
153 NRF_STATIC_INLINE void nrf_cracen_module_disable(NRF_CRACEN_Type * p_reg, uint32_t modules);
154
155 /**
156 * @brief Function for getting enabled CRACEN modules.
157 *
158 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
159 *
160 * @return Mask of enabled modules. See @ref nrf_cracen_module_mask_t.
161 */
162 NRF_STATIC_INLINE uint32_t nrf_cracen_module_get(NRF_CRACEN_Type const * p_reg);
163
164 /**
165 * @brief Function for enabling or disabling lock on access to the RAM used for the seed.
166 *
167 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
168 * @param[in] enable True if lock is to be enabled, false otherwise.
169 */
170 NRF_STATIC_INLINE void nrf_cracen_seedram_lock_enable_set(NRF_CRACEN_Type * p_reg, bool enable);
171
172 /**
173 * @brief Function for checking if access to the RAM used for the seed is locked.
174 *
175 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
176 *
177 * @retval true Access to the RAM used for the seed is locked.
178 * @retval false Access to the RAM used for the seed is unlocked.
179 */
180 NRF_STATIC_INLINE bool nrf_cracen_seedram_lock_check(NRF_CRACEN_Type const * p_reg);
181
182 /**
183 * @brief Function for setting specified seed word for private key generation.
184 *
185 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
186 * @param[in] idx Index of the seed word.
187 * @param[in] value Seed value to be set.
188 */
189 NRF_STATIC_INLINE void nrf_cracen_seed_set(NRF_CRACEN_Type * p_reg, uint8_t idx, uint32_t value);
190
191 #ifndef NRF_DECLARE_ONLY
nrf_cracen_event_address_get(NRF_CRACEN_Type const * p_reg,nrf_cracen_event_t event)192 NRF_STATIC_INLINE uint32_t nrf_cracen_event_address_get(NRF_CRACEN_Type const * p_reg,
193 nrf_cracen_event_t event)
194 {
195 return nrf_task_event_address_get(p_reg, event);
196 }
197
nrf_cracen_event_clear(NRF_CRACEN_Type * p_reg,nrf_cracen_event_t event)198 NRF_STATIC_INLINE void nrf_cracen_event_clear(NRF_CRACEN_Type * p_reg,
199 nrf_cracen_event_t event)
200 {
201 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
202 nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
203 }
204
nrf_cracen_event_check(NRF_CRACEN_Type const * p_reg,nrf_cracen_event_t event)205 NRF_STATIC_INLINE bool nrf_cracen_event_check(NRF_CRACEN_Type const * p_reg,
206 nrf_cracen_event_t event)
207 {
208 return nrf_event_check(p_reg, event);
209 }
210
nrf_cracen_int_enable(NRF_CRACEN_Type * p_reg,uint32_t mask)211 NRF_STATIC_INLINE void nrf_cracen_int_enable(NRF_CRACEN_Type * p_reg, uint32_t mask)
212 {
213 p_reg->INTENSET = mask;
214 }
215
nrf_cracen_int_enable_check(NRF_CRACEN_Type const * p_reg,uint32_t mask)216 NRF_STATIC_INLINE uint32_t nrf_cracen_int_enable_check(NRF_CRACEN_Type const * p_reg, uint32_t mask)
217 {
218 return p_reg->INTENSET & mask;
219 }
220
nrf_cracen_int_disable(NRF_CRACEN_Type * p_reg,uint32_t mask)221 NRF_STATIC_INLINE void nrf_cracen_int_disable(NRF_CRACEN_Type * p_reg, uint32_t mask)
222 {
223 p_reg->INTENCLR = mask;
224 }
225
nrf_cracen_module_enable(NRF_CRACEN_Type * p_reg,uint32_t modules)226 NRF_STATIC_INLINE void nrf_cracen_module_enable(NRF_CRACEN_Type * p_reg, uint32_t modules)
227 {
228 p_reg->ENABLE |= modules;
229 }
230
nrf_cracen_module_disable(NRF_CRACEN_Type * p_reg,uint32_t modules)231 NRF_STATIC_INLINE void nrf_cracen_module_disable(NRF_CRACEN_Type * p_reg, uint32_t modules)
232 {
233 p_reg->ENABLE &= ~modules;
234 }
235
nrf_cracen_module_get(NRF_CRACEN_Type const * p_reg)236 NRF_STATIC_INLINE uint32_t nrf_cracen_module_get(NRF_CRACEN_Type const * p_reg)
237 {
238 return p_reg->ENABLE;
239 }
240
nrf_cracen_seedram_lock_enable_set(NRF_CRACEN_Type * p_reg,bool enable)241 NRF_STATIC_INLINE void nrf_cracen_seedram_lock_enable_set(NRF_CRACEN_Type * p_reg, bool enable)
242 {
243 #if defined(CRACEN_SEEDRAMLOCK_ENABLE_Enabled)
244 p_reg->SEEDRAMLOCK = (enable ? CRACEN_SEEDRAMLOCK_ENABLE_Enabled
245 : CRACEN_SEEDRAMLOCK_ENABLE_Disabled) << CRACEN_SEEDRAMLOCK_ENABLE_Pos;
246 #elif defined(CRACEN_SEEDLOCK_ENABLE_Enabled)
247 p_reg->SEEDLOCK = (enable ? CRACEN_SEEDLOCK_ENABLE_Enabled
248 : CRACEN_SEEDLOCK_ENABLE_Disabled) << CRACEN_SEEDLOCK_ENABLE_Pos;
249 #else
250 p_reg->KEYLOCK = (enable ? CRACEN_KEYLOCK_ENABLE_Enabled : CRACEN_KEYLOCK_ENABLE_Disabled)
251 << CRACEN_KEYLOCK_ENABLE_Pos;
252 #endif
253 }
254
nrf_cracen_seedram_lock_check(NRF_CRACEN_Type const * p_reg)255 NRF_STATIC_INLINE bool nrf_cracen_seedram_lock_check(NRF_CRACEN_Type const * p_reg)
256 {
257 #if defined(CRACEN_SEEDRAMLOCK_ENABLE_Enabled)
258 return p_reg->SEEDRAMLOCK == (CRACEN_SEEDRAMLOCK_ENABLE_Enabled
259 << CRACEN_SEEDRAMLOCK_ENABLE_Pos);
260 #elif defined(CRACEN_SEEDLOCK_ENABLE_Enabled)
261 return p_reg->SEEDLOCK == (CRACEN_SEEDLOCK_ENABLE_Enabled
262 << CRACEN_SEEDLOCK_ENABLE_Pos);
263 #else
264 return p_reg->KEYLOCK == (CRACEN_KEYLOCK_ENABLE_Enabled << CRACEN_KEYLOCK_ENABLE_Pos);
265 #endif
266 }
267
nrf_cracen_seed_set(NRF_CRACEN_Type * p_reg,uint8_t idx,uint32_t value)268 NRF_STATIC_INLINE void nrf_cracen_seed_set(NRF_CRACEN_Type * p_reg, uint8_t idx, uint32_t value)
269 {
270 NRFX_ASSERT(idx < NRF_CRACEN_SEED_COUNT);
271 p_reg->SEED[idx] = value;
272 }
273 #endif // NRF_DECLARE_ONLY
274
275 /** @} */
276
277 #ifdef __cplusplus
278 }
279 #endif
280
281 #endif // NRF_CRACEN_H__
282
