1 /* 2 3 Copyright (c) 2009-2023 ARM Limited. All rights reserved. 4 5 SPDX-License-Identifier: Apache-2.0 6 7 Licensed under the Apache License, Version 2.0 (the License); you may 8 not use this file except in compliance with the License. 9 You may obtain a copy of the License at 10 11 www.apache.org/licenses/LICENSE-2.0 12 13 Unless required by applicable law or agreed to in writing, software 14 distributed under the License is distributed on an AS IS BASIS, WITHOUT 15 WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 16 See the License for the specific language governing permissions and 17 limitations under the License. 18 19 NOTICE: This file has been modified by Nordic Semiconductor ASA. 20 21 */ 22 23 /* NOTE: Template files (including this one) are application specific and therefore expected to 24 be copied into the application project folder prior to its use! */ 25 26 #include <stdint.h> 27 #include <stdbool.h> 28 #include "nrf.h" 29 #include "system_nrf54l.h" 30 #include "system_nrf54l_approtect.h" 31 #include "system_config_sau.h" 32 33 /*lint ++flb "Enter library region" */ 34 35 #define __SYSTEM_CLOCK_DEFAULT (64000000ul) 36 37 #if defined ( __CC_ARM ) || defined ( __GNUC__ ) 38 uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_DEFAULT; 39 #elif defined ( __ICCARM__ ) 40 __root uint32_t SystemCoreClock = __SYSTEM_CLOCK_DEFAULT; 41 #endif 42 SystemCoreClockUpdate(void)43void SystemCoreClockUpdate(void) 44 { 45 switch(NRF_OSCILLATORS->PLL.CURRENTFREQ) 46 { 47 case OSCILLATORS_PLL_CURRENTFREQ_CURRENTFREQ_CK64M: 48 SystemCoreClock = 64000000ul; 49 break; 50 case OSCILLATORS_PLL_CURRENTFREQ_CURRENTFREQ_CK128M: 51 SystemCoreClock = 128000000ul; 52 break; 53 } 54 } 55 SystemInit(void)56void SystemInit(void) 57 { 58 #ifdef __CORTEX_M 59 #ifndef NRF_SKIP_CLOCK_CONFIGURATION 60 #if defined(NRF_CONFIG_CPU_FREQ_MHZ) && (NRF_CONFIG_CPU_FREQ_MHZ==64) 61 NRF_OSCILLATORS->PLL.FREQ = OSCILLATORS_PLL_FREQ_FREQ_CK64M; 62 #elif defined(NRF_CONFIG_CPU_FREQ_MHZ) && (NRF_CONFIG_CPU_FREQ_MHZ==128) 63 NRF_OSCILLATORS->PLL.FREQ = OSCILLATORS_PLL_FREQ_FREQ_CK128M; 64 #elif defined(NRF_CONFIG_CPU_FREQ_MHZ) 65 #error "Illegal CPU frequency set" 66 #else 67 NRF_OSCILLATORS->PLL.FREQ = OSCILLATORS_PLL_FREQ_FREQ_CK128M; 68 #endif 69 #endif 70 71 #if !defined(NRF_TRUSTZONE_NONSECURE) && defined(__ARM_FEATURE_CMSE) 72 #ifndef NRF_SKIP_TAMPC_SETUP 73 nrf54l_handle_approtect(); 74 #endif 75 #if defined(__FPU_PRESENT) && __FPU_PRESENT 76 /* Allow Non-Secure code to run FPU instructions. 77 * If only the secure code should control FPU power state these registers should be configured accordingly in the secure application code. */ 78 SCB->NSACR |= (3UL << 10ul); 79 #endif 80 81 #ifndef NRF_SKIP_SAU_CONFIGURATION 82 configure_default_sau(); 83 #endif 84 #endif 85 86 #if !defined (NRF_DISABLE_FICR_TRIMCNF) 87 /* Trimming of the device. Copy all the trimming values from FICR into the target addresses. Trim 88 until one ADDR is not initialized. */ 89 uint32_t index = 0ul; 90 for (index = 0ul; index < FICR_TRIMCNF_MaxCount && NRF_FICR_NS->TRIMCNF[index].ADDR != 0xFFFFFFFFul && NRF_FICR_NS->TRIMCNF[index].ADDR != 0x00000000ul; index++) { 91 #if defined ( __ICCARM__ ) 92 /* IAR will complain about the order of volatile pointer accesses. */ 93 #pragma diag_suppress=Pa082 94 #endif 95 * ((volatile uint32_t*)NRF_FICR_NS->TRIMCNF[index].ADDR) = NRF_FICR_NS->TRIMCNF[index].DATA; 96 #if defined ( __ICCARM__ ) 97 #pragma diag_default=Pa082 98 #endif 99 } 100 #endif 101 102 /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the 103 * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit 104 * operations are not used in your code. */ 105 106 /* Allow Non-Secure code to run FPU instructions. 107 * If only the secure code should control FPU power state these registers should be configured accordingly in the secure application code. */ 108 SCB->NSACR |= (3UL << 10ul); 109 110 #if (__FPU_USED == 1ul) 111 SCB->CPACR |= (3UL << 20ul) | (3UL << 22ul); 112 __DSB(); 113 __ISB(); 114 #endif 115 116 #if defined(NRF_CONFIG_NFCT_PINS_AS_GPIOS) 117 NRF_NFCT_S->PADCONFIG = (NFCT_PADCONFIG_ENABLE_Disabled << NFCT_PADCONFIG_ENABLE_Pos); 118 #endif 119 120 /* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product 121 Specification to see which one). */ 122 #if defined (ENABLE_SWO) 123 // Enable Trace And Debug peripheral 124 NRF_TAD_S->ENABLE = TAD_ENABLE_ENABLE_Msk; 125 NRF_TAD_S->CLOCKSTART = TAD_CLOCKSTART_START_Msk; 126 127 // Set up Trace pad SPU firewall 128 NRF_SPU_S->GPIOPORT[0].PERM &= ~(1ul << TRACE_TRACEDATA0_PIN); 129 130 // Configure trace port pad 131 NRF_P0_S->PIN_CNF[TRACE_TRACEDATA0_PIN] = TRACE_PIN_CNF_VALUE; 132 133 // Select trace pin 134 NRF_TAD_S->PSEL.TRACEDATA0 = TRACE_TRACEDATA0_PIN; 135 136 // Set trace port speed to 64 MHz 137 NRF_TAD_S->TRACEPORTSPEED = TAD_TRACEPORTSPEED_TRACEPORTSPEED_64MHz; 138 #endif 139 140 /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product 141 Specification to see which ones). */ 142 #if defined (ENABLE_TRACE) 143 // Enable Trace And Debug peripheral 144 NRF_TAD_S->ENABLE = TAD_ENABLE_ENABLE_Msk; 145 NRF_TAD_S->CLOCKSTART = TAD_CLOCKSTART_START_Msk; 146 147 // Set up Trace pads SPU firewall 148 NRF_SPU_S->GPIOPORT[0].PERM &= ~(1ul << TRACE_TRACECLK_PIN); 149 NRF_SPU_S->GPIOPORT[0].PERM &= ~(1ul << TRACE_TRACEDATA0_PIN); 150 NRF_SPU_S->GPIOPORT[0].PERM &= ~(1ul << TRACE_TRACEDATA1_PIN); 151 NRF_SPU_S->GPIOPORT[0].PERM &= ~(1ul << TRACE_TRACEDATA2_PIN); 152 NRF_SPU_S->GPIOPORT[0].PERM &= ~(1ul << TRACE_TRACEDATA3_PIN); 153 154 // Configure trace port pads 155 NRF_P0_S->PIN_CNF[TRACE_TRACECLK_PIN] = TRACE_PIN_CNF_VALUE; 156 NRF_P0_S->PIN_CNF[TRACE_TRACEDATA0_PIN] = TRACE_PIN_CNF_VALUE; 157 NRF_P0_S->PIN_CNF[TRACE_TRACEDATA1_PIN] = TRACE_PIN_CNF_VALUE; 158 NRF_P0_S->PIN_CNF[TRACE_TRACEDATA2_PIN] = TRACE_PIN_CNF_VALUE; 159 NRF_P0_S->PIN_CNF[TRACE_TRACEDATA3_PIN] = TRACE_PIN_CNF_VALUE; 160 161 // Select trace pins 162 NRF_TAD_S->PSEL.TRACECLK = TRACE_TRACECLK_PIN; 163 NRF_TAD_S->PSEL.TRACEDATA0 = TRACE_TRACEDATA0_PIN; 164 NRF_TAD_S->PSEL.TRACEDATA1 = TRACE_TRACEDATA1_PIN; 165 NRF_TAD_S->PSEL.TRACEDATA2 = TRACE_TRACEDATA2_PIN; 166 NRF_TAD_S->PSEL.TRACEDATA3 = TRACE_TRACEDATA3_PIN; 167 168 // Set trace port speed to 64 MHz 169 NRF_TAD_S->TRACEPORTSPEED = TAD_TRACEPORTSPEED_TRACEPORTSPEED_64MHz; 170 171 #endif 172 173 #if !defined (NRF_SKIP_GLITCHDETECTOR_DISABLE) 174 /* Disable glitch detector */ 175 NRF_GLITCHDET_S->GLITCHDETECTOR.CONFIG = (GLITCHDET_GLITCHDETECTOR_CONFIG_ENABLE_Disable << GLITCHDET_GLITCHDETECTOR_CONFIG_ENABLE_Pos); 176 #endif 177 #endif 178 } 179 180 /*lint --flb "Leave library region" */ 181
