1 /*
2 * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_GPIOTE_H__
35 #define NRF_GPIOTE_H__
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /* Internal macro used for NRF_GPIOTE_INT_IN_MASK. */
44 #define NRF_GPIOTE_INT_IN(idx, _) NRFX_CONCAT(NRF_GPIOTE_INT_IN, idx, _MASK)
45
46 /**
47 * @defgroup nrf_gpiote_hal GPIOTE HAL
48 * @{
49 * @ingroup nrf_gpiote
50 * @brief Hardware access layer (HAL) for managing the GPIOTE peripheral.
51 */
52
53 #if defined(GPIOTE_CONFIG_PORT_Msk) || defined(__NRFX_DOXYGEN__)
54 /** @brief Mask for covering port and pin bits in registers. */
55 #define GPIOTE_CONFIG_PORT_PIN_Msk (GPIOTE_CONFIG_PORT_Msk | GPIOTE_CONFIG_PSEL_Msk)
56 #else
57 #define GPIOTE_CONFIG_PORT_PIN_Msk GPIOTE_CONFIG_PSEL_Msk
58 #endif
59
60 #if defined(GPIOTE_LATENCY_LATENCY_Msk) || defined(__NRFX_DOXYGEN__)
61 /** @brief Presence of the latency setting. */
62 #define NRF_GPIOTE_HAS_LATENCY 1
63 #else
64 #define NRF_GPIOTE_HAS_LATENCY 0
65 #endif
66
67 #if !defined(NRF_GPIOTE_IRQ_GROUP) || defined(__NRFX_DOXYGEN__)
68 /** @brief Symbol indicating which interrupt group to use. Empty if there are no groups. */
69 #define NRF_GPIOTE_IRQ_GROUP
70 #endif
71
72 #if defined(GPIOTE_INTENSET0_PORT0SECURE_Msk)
73 #if defined(NRF_TRUSTZONE_NONSECURE) || defined(ISA_RISCV)
74 #define NRF_GPIOTE_SECURE_SUFFIX NONSECURE
75 #else
76 #define NRF_GPIOTE_SECURE_SUFFIX SECURE
77 #endif
78 #else
79 /** @brief Symbol indicating a TrustZone suffix added to the register name. */
80 #define NRF_GPIOTE_SECURE_SUFFIX
81 #endif
82
83 #if defined(NRF_GPIOTE_PORT_ID)
84 #define NRF_GPIOTE_EVENTS_PORT_REG EVENTS_PORT[NRF_GPIOTE_PORT_ID].NRF_GPIOTE_SECURE_SUFFIX
85
86 #define NRF_GPIOTE_INT_PORT_MASK_NAME \
87 NRFX_CONCAT(GPIOTE_INTENSET, \
88 NRF_GPIOTE_IRQ_GROUP, \
89 _PORT, \
90 NRF_GPIOTE_PORT_ID, \
91 NRF_GPIOTE_SECURE_SUFFIX, \
92 _Msk)
93 #else
94 /** @brief Symbol indicating a name of PORT event register to be used. */
95 #define NRF_GPIOTE_EVENTS_PORT_REG EVENTS_PORT
96
97 /** @brief Symbol specifying interrupt bitmask associated with the PORT event. */
98 #define NRF_GPIOTE_INT_PORT_MASK_NAME GPIOTE_INTENSET_PORT_Msk
99 #endif
100
101 /** @brief Polarity for the GPIOTE channel. */
102 typedef enum
103 {
104 NRF_GPIOTE_POLARITY_NONE = GPIOTE_CONFIG_POLARITY_None, ///< None.
105 NRF_GPIOTE_POLARITY_LOTOHI = GPIOTE_CONFIG_POLARITY_LoToHi, ///< Low to high.
106 NRF_GPIOTE_POLARITY_HITOLO = GPIOTE_CONFIG_POLARITY_HiToLo, ///< High to low.
107 NRF_GPIOTE_POLARITY_TOGGLE = GPIOTE_CONFIG_POLARITY_Toggle, ///< Toggle.
108 } nrf_gpiote_polarity_t;
109
110 /** @brief Initial output value for the GPIOTE channel. */
111 typedef enum
112 {
113 NRF_GPIOTE_INITIAL_VALUE_LOW = GPIOTE_CONFIG_OUTINIT_Low, ///< Low to high.
114 NRF_GPIOTE_INITIAL_VALUE_HIGH = GPIOTE_CONFIG_OUTINIT_High, ///< High to low.
115 } nrf_gpiote_outinit_t;
116
117 #if NRF_GPIOTE_HAS_LATENCY
118 /** @brief Latency setting. */
119 typedef enum
120 {
121 NRF_GPIOTE_LATENCY_LOWPOWER = GPIOTE_LATENCY_LATENCY_LowPower, ///< Low Power.
122 NRF_GPIOTE_LATENCY_LOWLATENCY = GPIOTE_LATENCY_LATENCY_LowLatency, ///< Low Latency.
123 } nrf_gpiote_latency_t;
124 #endif
125
126 /** @brief GPIOTE tasks. */
127 typedef enum
128 {
129 NRF_GPIOTE_TASK_OUT_0 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[0]), ///< Out task 0.
130 NRF_GPIOTE_TASK_OUT_1 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[1]), ///< Out task 1.
131 NRF_GPIOTE_TASK_OUT_2 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[2]), ///< Out task 2.
132 NRF_GPIOTE_TASK_OUT_3 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[3]), ///< Out task 3.
133 #if (GPIOTE_CH_NUM > 4) || defined(__NRFX_DOXYGEN__)
134 NRF_GPIOTE_TASK_OUT_4 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[4]), ///< Out task 4.
135 NRF_GPIOTE_TASK_OUT_5 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[5]), ///< Out task 5.
136 NRF_GPIOTE_TASK_OUT_6 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[6]), ///< Out task 6.
137 NRF_GPIOTE_TASK_OUT_7 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[7]), ///< Out task 7.
138 #endif
139 #if defined(GPIOTE_FEATURE_SET_PRESENT) || defined(__NRFX_DOXYGEN__)
140 NRF_GPIOTE_TASK_SET_0 = offsetof(NRF_GPIOTE_Type, TASKS_SET[0]), ///< Set task 0.
141 NRF_GPIOTE_TASK_SET_1 = offsetof(NRF_GPIOTE_Type, TASKS_SET[1]), ///< Set task 1.
142 NRF_GPIOTE_TASK_SET_2 = offsetof(NRF_GPIOTE_Type, TASKS_SET[2]), ///< Set task 2.
143 NRF_GPIOTE_TASK_SET_3 = offsetof(NRF_GPIOTE_Type, TASKS_SET[3]), ///< Set task 3.
144 NRF_GPIOTE_TASK_SET_4 = offsetof(NRF_GPIOTE_Type, TASKS_SET[4]), ///< Set task 4.
145 NRF_GPIOTE_TASK_SET_5 = offsetof(NRF_GPIOTE_Type, TASKS_SET[5]), ///< Set task 5.
146 NRF_GPIOTE_TASK_SET_6 = offsetof(NRF_GPIOTE_Type, TASKS_SET[6]), ///< Set task 6.
147 NRF_GPIOTE_TASK_SET_7 = offsetof(NRF_GPIOTE_Type, TASKS_SET[7]), ///< Set task 7.
148 #endif
149 #if defined(GPIOTE_FEATURE_CLR_PRESENT) || defined(__NRFX_DOXYGEN__)
150 NRF_GPIOTE_TASK_CLR_0 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[0]), ///< Clear task 0.
151 NRF_GPIOTE_TASK_CLR_1 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[1]), ///< Clear task 1.
152 NRF_GPIOTE_TASK_CLR_2 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[2]), ///< Clear task 2.
153 NRF_GPIOTE_TASK_CLR_3 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[3]), ///< Clear task 3.
154 NRF_GPIOTE_TASK_CLR_4 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[4]), ///< Clear task 4.
155 NRF_GPIOTE_TASK_CLR_5 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[5]), ///< Clear task 5.
156 NRF_GPIOTE_TASK_CLR_6 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[6]), ///< Clear task 6.
157 NRF_GPIOTE_TASK_CLR_7 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[7]), ///< Clear task 7.
158 #endif
159 } nrf_gpiote_task_t;
160
161 /** @brief GPIOTE events. */
162 typedef enum
163 {
164 NRF_GPIOTE_EVENT_IN_0 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[0]), ///< In event 0.
165 NRF_GPIOTE_EVENT_IN_1 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[1]), ///< In event 1.
166 NRF_GPIOTE_EVENT_IN_2 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[2]), ///< In event 2.
167 NRF_GPIOTE_EVENT_IN_3 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[3]), ///< In event 3.
168 #if (GPIOTE_CH_NUM > 4) || defined(__NRFX_DOXYGEN__)
169 NRF_GPIOTE_EVENT_IN_4 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[4]), ///< In event 4.
170 NRF_GPIOTE_EVENT_IN_5 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[5]), ///< In event 5.
171 NRF_GPIOTE_EVENT_IN_6 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[6]), ///< In event 6.
172 NRF_GPIOTE_EVENT_IN_7 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[7]), ///< In event 7.
173 #endif
174 NRF_GPIOTE_EVENT_PORT = offsetof(NRF_GPIOTE_Type, NRF_GPIOTE_EVENTS_PORT_REG), ///< Port event.
175 } nrf_gpiote_event_t;
176
177 /** @brief GPIOTE interrupts. */
178 typedef enum
179 {
180 NRF_GPIOTE_INT_IN0_MASK = NRFX_CONCAT(GPIOTE_INTENSET, NRF_GPIOTE_IRQ_GROUP, _IN0_Msk), ///< GPIOTE interrupt from IN0.
181 NRF_GPIOTE_INT_IN1_MASK = NRFX_CONCAT(GPIOTE_INTENSET, NRF_GPIOTE_IRQ_GROUP, _IN1_Msk), ///< GPIOTE interrupt from IN1.
182 NRF_GPIOTE_INT_IN2_MASK = NRFX_CONCAT(GPIOTE_INTENSET, NRF_GPIOTE_IRQ_GROUP, _IN2_Msk), ///< GPIOTE interrupt from IN2.
183 NRF_GPIOTE_INT_IN3_MASK = NRFX_CONCAT(GPIOTE_INTENSET, NRF_GPIOTE_IRQ_GROUP, _IN3_Msk), ///< GPIOTE interrupt from IN3.
184 #if (GPIOTE_CH_NUM > 4) || defined(__NRFX_DOXYGEN__)
185 NRF_GPIOTE_INT_IN4_MASK = NRFX_CONCAT(GPIOTE_INTENSET, NRF_GPIOTE_IRQ_GROUP, _IN4_Msk), ///< GPIOTE interrupt from IN4.
186 NRF_GPIOTE_INT_IN5_MASK = NRFX_CONCAT(GPIOTE_INTENSET, NRF_GPIOTE_IRQ_GROUP, _IN5_Msk), ///< GPIOTE interrupt from IN5.
187 NRF_GPIOTE_INT_IN6_MASK = NRFX_CONCAT(GPIOTE_INTENSET, NRF_GPIOTE_IRQ_GROUP, _IN6_Msk), ///< GPIOTE interrupt from IN6.
188 NRF_GPIOTE_INT_IN7_MASK = NRFX_CONCAT(GPIOTE_INTENSET, NRF_GPIOTE_IRQ_GROUP, _IN7_Msk), ///< GPIOTE interrupt from IN7.
189 #endif
190 NRF_GPIOTE_INT_PORT_MASK = (int)NRF_GPIOTE_INT_PORT_MASK_NAME ///< GPIOTE interrupt from PORT event.
191 } nrf_gpiote_int_t;
192
193 /** @brief Symbol specifying bitmask collecting all IN events interrupts. */
194 #define NRF_GPIOTE_INT_IN_MASK (NRFX_LISTIFY(GPIOTE_CH_NUM, NRF_GPIOTE_INT_IN, (|), _))
195
196 /**
197 * @brief Function for activating the specified GPIOTE task.
198 *
199 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
200 * @param[in] task Task.
201 */
202 NRF_STATIC_INLINE void nrf_gpiote_task_trigger(NRF_GPIOTE_Type * p_reg, nrf_gpiote_task_t task);
203
204 /**
205 * @brief Function for getting the address of the specified GPIOTE task.
206 *
207 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
208 * @param[in] task Task.
209 *
210 * @return Address of the specified task.
211 */
212 NRF_STATIC_INLINE uint32_t nrf_gpiote_task_address_get(NRF_GPIOTE_Type const * p_reg,
213 nrf_gpiote_task_t task);
214
215 /**
216 * @brief Function for getting the state of the specified GPIOTE event.
217 *
218 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
219 * @param[in] event Event.
220 *
221 * @retval true The event is set.
222 * @retval false The event is not set.
223 */
224 NRF_STATIC_INLINE bool nrf_gpiote_event_check(NRF_GPIOTE_Type const * p_reg,
225 nrf_gpiote_event_t event);
226
227 /**
228 * @brief Function for clearing the specified GPIOTE event.
229 *
230 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
231 * @param[in] event Event.
232 */
233 NRF_STATIC_INLINE void nrf_gpiote_event_clear(NRF_GPIOTE_Type * p_reg, nrf_gpiote_event_t event);
234
235 /**
236 * @brief Function for getting the address of the specified GPIOTE event.
237 *
238 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
239 * @param[in] event Event.
240 *
241 * @return Address of the specified event.
242 */
243 NRF_STATIC_INLINE uint32_t nrf_gpiote_event_address_get(NRF_GPIOTE_Type const * p_reg,
244 nrf_gpiote_event_t event);
245
246 /**
247 * @brief Function for enabling interrupts.
248 *
249 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
250 * @param[in] mask Mask of interrupts to be enabled.
251 */
252 NRF_STATIC_INLINE void nrf_gpiote_int_enable(NRF_GPIOTE_Type * p_reg, uint32_t mask);
253
254 /**
255 * @brief Function for disabling interrupts.
256 *
257 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
258 * @param[in] mask Mask of interrupts to be disabled.
259 */
260 NRF_STATIC_INLINE void nrf_gpiote_int_disable(NRF_GPIOTE_Type * p_reg, uint32_t mask);
261
262 /**
263 * @brief Function for checking if the specified interrupts are enabled.
264 *
265 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
266 * @param[in] mask Mask of interrupts to be checked.
267 *
268 * @return Mask of enabled interrupts.
269 */
270 NRF_STATIC_INLINE uint32_t nrf_gpiote_int_enable_check(NRF_GPIOTE_Type const * p_reg,
271 uint32_t mask);
272
273 #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
274 /**
275 * @brief Function for setting the subscribe configuration for a given
276 * GPIOTE task.
277 *
278 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
279 * @param[in] task Task for which to set the configuration.
280 * @param[in] channel Channel through which to subscribe events.
281 */
282 NRF_STATIC_INLINE void nrf_gpiote_subscribe_set(NRF_GPIOTE_Type * p_reg,
283 nrf_gpiote_task_t task,
284 uint8_t channel);
285
286 /**
287 * @brief Function for clearing the subscribe configuration for a given
288 * GPIOTE task.
289 *
290 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
291 * @param[in] task Task for which to clear the configuration.
292 */
293 NRF_STATIC_INLINE void nrf_gpiote_subscribe_clear(NRF_GPIOTE_Type * p_reg, nrf_gpiote_task_t task);
294
295 /**
296 * @brief Function for setting the publish configuration for a given
297 * GPIOTE event.
298 *
299 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
300 * @param[in] event Event for which to set the configuration.
301 * @param[in] channel Channel through which to publish the event.
302 */
303 NRF_STATIC_INLINE void nrf_gpiote_publish_set(NRF_GPIOTE_Type * p_reg,
304 nrf_gpiote_event_t event,
305 uint8_t channel);
306
307 /**
308 * @brief Function for clearing the publish configuration for a given
309 * GPIOTE event.
310 *
311 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
312 * @param[in] event Event for which to clear the configuration.
313 */
314 NRF_STATIC_INLINE void nrf_gpiote_publish_clear(NRF_GPIOTE_Type * p_reg, nrf_gpiote_event_t event);
315 #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
316
317 /**
318 * @brief Function for enabling a GPIOTE event.
319 *
320 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
321 * @param[in] idx Task-Event index.
322 */
323 NRF_STATIC_INLINE void nrf_gpiote_event_enable(NRF_GPIOTE_Type * p_reg, uint32_t idx);
324
325 /**
326 * @brief Function for disabling a GPIOTE event.
327 *
328 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
329 * @param[in] idx Task-Event index.
330 */
331 NRF_STATIC_INLINE void nrf_gpiote_event_disable(NRF_GPIOTE_Type * p_reg, uint32_t idx);
332
333 /**
334 * @brief Function for configuring a GPIOTE event.
335 *
336 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
337 * @param[in] idx Task-Event index.
338 * @param[in] pin Pin associated with event.
339 * @param[in] polarity Transition that should generate an event.
340 */
341 NRF_STATIC_INLINE void nrf_gpiote_event_configure(NRF_GPIOTE_Type * p_reg,
342 uint32_t idx,
343 uint32_t pin,
344 nrf_gpiote_polarity_t polarity);
345
346 /**
347 * @brief Function for getting the pin associated with a GPIOTE event.
348 *
349 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
350 * @param[in] idx Task-Event index.
351 *
352 * @return Pin number.
353 */
354 NRF_STATIC_INLINE uint32_t nrf_gpiote_event_pin_get(NRF_GPIOTE_Type const * p_reg, uint32_t idx);
355
356 /**
357 * @brief Function for getting the polarity associated with a GPIOTE event.
358 *
359 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
360 * @param[in] idx Task-Event index.
361 *
362 * @return Polarity.
363 */
364 NRF_STATIC_INLINE nrf_gpiote_polarity_t nrf_gpiote_event_polarity_get(NRF_GPIOTE_Type const * p_reg,
365 uint32_t idx);
366
367 /**
368 * @brief Function for enabling a GPIOTE task.
369 *
370 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
371 * @param[in] idx Task-Event index.
372 */
373 NRF_STATIC_INLINE void nrf_gpiote_task_enable(NRF_GPIOTE_Type * p_reg, uint32_t idx);
374
375 /**
376 * @brief Function for disabling a GPIOTE task.
377 *
378 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
379 * @param[in] idx Task-Event index.
380 */
381 NRF_STATIC_INLINE void nrf_gpiote_task_disable(NRF_GPIOTE_Type * p_reg, uint32_t idx);
382
383 /**
384 * @brief Function for configuring a GPIOTE task.
385 *
386 * @note Function is not configuring mode field so task is disabled after this function is called.
387 *
388 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
389 * @param[in] idx Task-Event index.
390 * @param[in] pin Pin associated with event.
391 * @param[in] polarity Transition that should generate an event.
392 * @param[in] init_val Initial value of the pin.
393 */
394 NRF_STATIC_INLINE void nrf_gpiote_task_configure(NRF_GPIOTE_Type * p_reg,
395 uint32_t idx,
396 uint32_t pin,
397 nrf_gpiote_polarity_t polarity,
398 nrf_gpiote_outinit_t init_val);
399
400 /**
401 * @brief Function for forcing the specified state on the pin connected to GPIOTE.
402 *
403 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
404 * @param[in] idx Task-Event index.
405 * @param[in] init_val Pin state.
406 */
407 NRF_STATIC_INLINE void nrf_gpiote_task_force(NRF_GPIOTE_Type * p_reg,
408 uint32_t idx,
409 nrf_gpiote_outinit_t init_val);
410
411 /**
412 * @brief Function for resetting a GPIOTE task event configuration to the default state.
413 *
414 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
415 * @param[in] idx Task-Event index.
416 */
417 NRF_STATIC_INLINE void nrf_gpiote_te_default(NRF_GPIOTE_Type * p_reg, uint32_t idx);
418
419 /**
420 * @brief Function for checking if particular Task-Event is enabled.
421 *
422 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
423 * @param[in] idx Task-Event index.
424 *
425 * @retval true The Task-Event mode is set to Task or Event.
426 * @retval false The Task-Event mode is set to Disabled.
427 */
428 NRF_STATIC_INLINE bool nrf_gpiote_te_is_enabled(NRF_GPIOTE_Type const * p_reg, uint32_t idx);
429
430 /**
431 * @brief Function for getting the OUT task associated with the specified GPIOTE channel.
432 *
433 * @param[in] index Channel index.
434 *
435 * @return Requested OUT task.
436 */
437 NRF_STATIC_INLINE nrf_gpiote_task_t nrf_gpiote_out_task_get(uint8_t index);
438
439 #if defined(GPIOTE_FEATURE_SET_PRESENT) || defined(__NRFX_DOXYGEN__)
440 /**
441 * @brief Function for getting the SET task associated with the specified GPIOTE channel.
442 *
443 * @param[in] index Channel index.
444 *
445 * @return Requested SET task.
446 */
447 NRF_STATIC_INLINE nrf_gpiote_task_t nrf_gpiote_set_task_get(uint8_t index);
448 #endif
449
450 #if defined(GPIOTE_FEATURE_CLR_PRESENT) || defined(__NRFX_DOXYGEN__)
451 /**
452 * @brief Function for getting the CLR task associated with the specified GPIOTE channel.
453 *
454 * @param[in] index Channel index.
455 *
456 * @return Requested CLR task.
457 */
458 NRF_STATIC_INLINE nrf_gpiote_task_t nrf_gpiote_clr_task_get(uint8_t index);
459 #endif
460
461 /**
462 * @brief Function for getting the IN event associated with the specified GPIOTE channel.
463 *
464 * @param[in] index Channel index.
465 *
466 * @return Requested IN event.
467 */
468 NRF_STATIC_INLINE nrf_gpiote_event_t nrf_gpiote_in_event_get(uint8_t index);
469
470 #if NRF_GPIOTE_HAS_LATENCY
471 /**
472 * @brief Function for setting the latency setting.
473 *
474 * @note Available for event mode with rising or falling edge detection on the pin.
475 * Toggle task mode can only be used with low latency setting.
476 *
477 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
478 * @param[in] latency Latency setting to be set.
479 */
480 NRF_STATIC_INLINE void nrf_gpiote_latency_set(NRF_GPIOTE_Type * p_reg,
481 nrf_gpiote_latency_t latency);
482
483 /**
484 * @brief Function for retrieving the latency setting.
485 *
486 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
487 *
488 * @return Latency setting.
489 */
490 NRF_STATIC_INLINE nrf_gpiote_latency_t nrf_gpiote_latency_get(NRF_GPIOTE_Type const * p_reg);
491 #endif
492
493 #ifndef NRF_DECLARE_ONLY
494
nrf_gpiote_task_trigger(NRF_GPIOTE_Type * p_reg,nrf_gpiote_task_t task)495 NRF_STATIC_INLINE void nrf_gpiote_task_trigger(NRF_GPIOTE_Type * p_reg, nrf_gpiote_task_t task)
496 {
497 *(volatile uint32_t *)((uint32_t)p_reg + task) = 0x1UL;
498 }
499
nrf_gpiote_task_address_get(NRF_GPIOTE_Type const * p_reg,nrf_gpiote_task_t task)500 NRF_STATIC_INLINE uint32_t nrf_gpiote_task_address_get(NRF_GPIOTE_Type const * p_reg,
501 nrf_gpiote_task_t task)
502 {
503 return ((uint32_t)p_reg + task);
504 }
505
nrf_gpiote_event_check(NRF_GPIOTE_Type const * p_reg,nrf_gpiote_event_t event)506 NRF_STATIC_INLINE bool nrf_gpiote_event_check(NRF_GPIOTE_Type const * p_reg,
507 nrf_gpiote_event_t event)
508 {
509 return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
510 }
511
nrf_gpiote_event_clear(NRF_GPIOTE_Type * p_reg,nrf_gpiote_event_t event)512 NRF_STATIC_INLINE void nrf_gpiote_event_clear(NRF_GPIOTE_Type * p_reg, nrf_gpiote_event_t event)
513 {
514 *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
515 nrf_event_readback((void *)nrf_gpiote_event_address_get(p_reg, event));
516 }
517
nrf_gpiote_event_address_get(NRF_GPIOTE_Type const * p_reg,nrf_gpiote_event_t event)518 NRF_STATIC_INLINE uint32_t nrf_gpiote_event_address_get(NRF_GPIOTE_Type const * p_reg,
519 nrf_gpiote_event_t event)
520 {
521 return ((uint32_t)p_reg + event);
522 }
523
nrf_gpiote_int_enable(NRF_GPIOTE_Type * p_reg,uint32_t mask)524 NRF_STATIC_INLINE void nrf_gpiote_int_enable(NRF_GPIOTE_Type * p_reg, uint32_t mask)
525 {
526 p_reg->NRFX_CONCAT_2(INTENSET, NRF_GPIOTE_IRQ_GROUP) = mask;
527 }
528
nrf_gpiote_int_disable(NRF_GPIOTE_Type * p_reg,uint32_t mask)529 NRF_STATIC_INLINE void nrf_gpiote_int_disable(NRF_GPIOTE_Type * p_reg, uint32_t mask)
530 {
531 p_reg->NRFX_CONCAT_2(INTENCLR, NRF_GPIOTE_IRQ_GROUP) = mask;
532 }
533
nrf_gpiote_int_enable_check(NRF_GPIOTE_Type const * p_reg,uint32_t mask)534 NRF_STATIC_INLINE uint32_t nrf_gpiote_int_enable_check(NRF_GPIOTE_Type const * p_reg, uint32_t mask)
535 {
536 return p_reg->NRFX_CONCAT_2(INTENSET, NRF_GPIOTE_IRQ_GROUP) & mask;
537 }
538
539 #if defined(DPPI_PRESENT)
nrf_gpiote_subscribe_set(NRF_GPIOTE_Type * p_reg,nrf_gpiote_task_t task,uint8_t channel)540 NRF_STATIC_INLINE void nrf_gpiote_subscribe_set(NRF_GPIOTE_Type * p_reg,
541 nrf_gpiote_task_t task,
542 uint8_t channel)
543 {
544 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
545 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
546 }
547
nrf_gpiote_subscribe_clear(NRF_GPIOTE_Type * p_reg,nrf_gpiote_task_t task)548 NRF_STATIC_INLINE void nrf_gpiote_subscribe_clear(NRF_GPIOTE_Type * p_reg, nrf_gpiote_task_t task)
549 {
550 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
551 }
552
nrf_gpiote_publish_set(NRF_GPIOTE_Type * p_reg,nrf_gpiote_event_t event,uint8_t channel)553 NRF_STATIC_INLINE void nrf_gpiote_publish_set(NRF_GPIOTE_Type * p_reg,
554 nrf_gpiote_event_t event,
555 uint8_t channel)
556 {
557 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
558 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
559 }
560
nrf_gpiote_publish_clear(NRF_GPIOTE_Type * p_reg,nrf_gpiote_event_t event)561 NRF_STATIC_INLINE void nrf_gpiote_publish_clear(NRF_GPIOTE_Type * p_reg, nrf_gpiote_event_t event)
562 {
563 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
564 }
565 #endif // defined(DPPI_PRESENT)
566
nrf_gpiote_event_enable(NRF_GPIOTE_Type * p_reg,uint32_t idx)567 NRF_STATIC_INLINE void nrf_gpiote_event_enable(NRF_GPIOTE_Type * p_reg, uint32_t idx)
568 {
569 p_reg->CONFIG[idx] |= GPIOTE_CONFIG_MODE_Event;
570 }
571
nrf_gpiote_event_disable(NRF_GPIOTE_Type * p_reg,uint32_t idx)572 NRF_STATIC_INLINE void nrf_gpiote_event_disable(NRF_GPIOTE_Type * p_reg, uint32_t idx)
573 {
574 p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Msk;
575 }
576
nrf_gpiote_event_configure(NRF_GPIOTE_Type * p_reg,uint32_t idx,uint32_t pin,nrf_gpiote_polarity_t polarity)577 NRF_STATIC_INLINE void nrf_gpiote_event_configure(NRF_GPIOTE_Type * p_reg,
578 uint32_t idx,
579 uint32_t pin,
580 nrf_gpiote_polarity_t polarity)
581 {
582 p_reg->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk | GPIOTE_CONFIG_POLARITY_Msk);
583 p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
584 ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk);
585 }
586
nrf_gpiote_event_pin_get(NRF_GPIOTE_Type const * p_reg,uint32_t idx)587 NRF_STATIC_INLINE uint32_t nrf_gpiote_event_pin_get(NRF_GPIOTE_Type const * p_reg, uint32_t idx)
588 {
589 return ((p_reg->CONFIG[idx] & GPIOTE_CONFIG_PORT_PIN_Msk) >> GPIOTE_CONFIG_PSEL_Pos);
590 }
591
nrf_gpiote_event_polarity_get(NRF_GPIOTE_Type const * p_reg,uint32_t idx)592 NRF_STATIC_INLINE nrf_gpiote_polarity_t nrf_gpiote_event_polarity_get(NRF_GPIOTE_Type const * p_reg,
593 uint32_t idx)
594 {
595 return (nrf_gpiote_polarity_t)((p_reg->CONFIG[idx] & GPIOTE_CONFIG_POLARITY_Msk) >>
596 GPIOTE_CONFIG_POLARITY_Pos);
597 }
598
nrf_gpiote_task_enable(NRF_GPIOTE_Type * p_reg,uint32_t idx)599 NRF_STATIC_INLINE void nrf_gpiote_task_enable(NRF_GPIOTE_Type * p_reg, uint32_t idx)
600 {
601 uint32_t final_config = p_reg->CONFIG[idx] | GPIOTE_CONFIG_MODE_Task;
602 #ifdef NRF51
603 /* Workaround for the OUTINIT PAN. When nrf_gpiote_task_config() is called a glitch happens
604 on the GPIO if the GPIO in question is already assigned to GPIOTE and the pin is in the
605 correct state in GPIOTE, but not in the OUT register.
606 Configure channel to not existing, not connected to the pin,
607 and configure as a tasks that will set it to proper level */
608 p_reg->CONFIG[idx] = final_config |
609 (((31) << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk);
610 __NOP();
611 __NOP();
612 __NOP();
613 #endif
614 p_reg->CONFIG[idx] = final_config;
615 }
616
nrf_gpiote_task_disable(NRF_GPIOTE_Type * p_reg,uint32_t idx)617 NRF_STATIC_INLINE void nrf_gpiote_task_disable(NRF_GPIOTE_Type * p_reg, uint32_t idx)
618 {
619 p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Msk;
620 }
621
nrf_gpiote_task_configure(NRF_GPIOTE_Type * p_reg,uint32_t idx,uint32_t pin,nrf_gpiote_polarity_t polarity,nrf_gpiote_outinit_t init_val)622 NRF_STATIC_INLINE void nrf_gpiote_task_configure(NRF_GPIOTE_Type * p_reg,
623 uint32_t idx,
624 uint32_t pin,
625 nrf_gpiote_polarity_t polarity,
626 nrf_gpiote_outinit_t init_val)
627 {
628 p_reg->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk |
629 GPIOTE_CONFIG_POLARITY_Msk |
630 GPIOTE_CONFIG_OUTINIT_Msk);
631
632 p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
633 ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk) |
634 ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk);
635 }
636
nrf_gpiote_task_force(NRF_GPIOTE_Type * p_reg,uint32_t idx,nrf_gpiote_outinit_t init_val)637 NRF_STATIC_INLINE void nrf_gpiote_task_force(NRF_GPIOTE_Type * p_reg,
638 uint32_t idx,
639 nrf_gpiote_outinit_t init_val)
640 {
641 p_reg->CONFIG[idx] = (p_reg->CONFIG[idx] & ~GPIOTE_CONFIG_OUTINIT_Msk) |
642 ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk);
643 }
644
nrf_gpiote_te_default(NRF_GPIOTE_Type * p_reg,uint32_t idx)645 NRF_STATIC_INLINE void nrf_gpiote_te_default(NRF_GPIOTE_Type * p_reg, uint32_t idx)
646 {
647 p_reg->CONFIG[idx] = 0;
648 #if !defined(NRF51_SERIES) && !defined(NRF52_SERIES)
649 p_reg->CONFIG[idx] = 0;
650 #endif
651 }
652
nrf_gpiote_te_is_enabled(NRF_GPIOTE_Type const * p_reg,uint32_t idx)653 NRF_STATIC_INLINE bool nrf_gpiote_te_is_enabled(NRF_GPIOTE_Type const * p_reg, uint32_t idx)
654 {
655 return (p_reg->CONFIG[idx] & GPIOTE_CONFIG_MODE_Msk) != GPIOTE_CONFIG_MODE_Disabled;
656 }
657
nrf_gpiote_out_task_get(uint8_t index)658 NRF_STATIC_INLINE nrf_gpiote_task_t nrf_gpiote_out_task_get(uint8_t index)
659 {
660 NRFX_ASSERT(index < GPIOTE_CH_NUM);
661 return (nrf_gpiote_task_t)NRFX_OFFSETOF(NRF_GPIOTE_Type, TASKS_OUT[index]);
662 }
663
664 #if defined(GPIOTE_FEATURE_SET_PRESENT)
nrf_gpiote_set_task_get(uint8_t index)665 NRF_STATIC_INLINE nrf_gpiote_task_t nrf_gpiote_set_task_get(uint8_t index)
666 {
667 NRFX_ASSERT(index < GPIOTE_CH_NUM);
668 return (nrf_gpiote_task_t)NRFX_OFFSETOF(NRF_GPIOTE_Type, TASKS_SET[index]);
669 }
670 #endif
671
672 #if defined(GPIOTE_FEATURE_CLR_PRESENT)
nrf_gpiote_clr_task_get(uint8_t index)673 NRF_STATIC_INLINE nrf_gpiote_task_t nrf_gpiote_clr_task_get(uint8_t index)
674 {
675 NRFX_ASSERT(index < GPIOTE_CH_NUM);
676 return (nrf_gpiote_task_t)NRFX_OFFSETOF(NRF_GPIOTE_Type, TASKS_CLR[index]);
677 }
678 #endif
679
nrf_gpiote_in_event_get(uint8_t index)680 NRF_STATIC_INLINE nrf_gpiote_event_t nrf_gpiote_in_event_get(uint8_t index)
681 {
682 NRFX_ASSERT(index < GPIOTE_CH_NUM);
683 return (nrf_gpiote_event_t)NRFX_OFFSETOF(NRF_GPIOTE_Type, EVENTS_IN[index]);
684 }
685
686 #if NRF_GPIOTE_HAS_LATENCY
nrf_gpiote_latency_set(NRF_GPIOTE_Type * p_reg,nrf_gpiote_latency_t latency)687 NRF_STATIC_INLINE void nrf_gpiote_latency_set(NRF_GPIOTE_Type * p_reg,
688 nrf_gpiote_latency_t latency)
689 {
690 p_reg->LATENCY = (latency << GPIOTE_LATENCY_LATENCY_Pos) & GPIOTE_LATENCY_LATENCY_Msk;
691 }
692
nrf_gpiote_latency_get(NRF_GPIOTE_Type const * p_reg)693 NRF_STATIC_INLINE nrf_gpiote_latency_t nrf_gpiote_latency_get(NRF_GPIOTE_Type const * p_reg)
694 {
695 return (nrf_gpiote_latency_t)((p_reg->LATENCY & GPIOTE_LATENCY_LATENCY_Msk) >>
696 GPIOTE_LATENCY_LATENCY_Pos);
697 }
698 #endif // NRF_GPIOTE_HAS_LATENCY
699 #endif // NRF_DECLARE_ONLY
700
701 /** @} */
702
703 #ifdef __cplusplus
704 }
705 #endif
706
707 #endif
708
