1 /* 2 * Instance header file for PIC32CX1025SG61128 3 * 4 * Copyright (c) 2023 Microchip Technology Inc. and its subsidiaries. 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 */ 19 20 /* file generated from device description file (ATDF) version 2023-03-17T09:48:59Z */ 21 #ifndef _PIC32CXSG61_OSCCTRL_INSTANCE_ 22 #define _PIC32CXSG61_OSCCTRL_INSTANCE_ 23 24 25 /* ========== Instance Parameter definitions for OSCCTRL peripheral ========== */ 26 #define OSCCTRL_DFLL48M_BIASTESTPT_IMPLEMENTED (0) /* DFLL48M bias test mode implemented */ 27 #define OSCCTRL_DFLL48M_CDACSTEPSIZE_SIZE (2) /* Size COARSE DAC STEP */ 28 #define OSCCTRL_DFLL48M_COARSE_RESET_VALUE (32) /* DFLL48M Frequency Coarse Reset Value (Before Calibration) */ 29 #define OSCCTRL_DFLL48M_COARSE_SIZE (6) /* Size COARSE CALIBRATION */ 30 #define OSCCTRL_DFLL48M_ENABLE_RESET_VALUE (1) /* Run oscillator at reset */ 31 #define OSCCTRL_DFLL48M_FDACSTEPSIZE_SIZE (2) /* Size FINE DAC STEP */ 32 #define OSCCTRL_DFLL48M_FINE_RESET_VALUE (128) /* DFLL48M Frequency Fine Reset Value (Before Calibration) */ 33 #define OSCCTRL_DFLL48M_FINE_SIZE (8) /* Size FINE CALIBRATION */ 34 #define OSCCTRL_DFLL48M_ONDEMAND_RESET_VALUE (1) /* Run oscillator always or only when requested */ 35 #define OSCCTRL_DFLL48M_RUNSTDBY_RESET_VALUE (0) /* Run oscillator even if standby mode */ 36 #define OSCCTRL_DFLL48M_TCAL_SIZE (4) /* Size TEMP CALIBRATION */ 37 #define OSCCTRL_DFLL48M_TCBIAS_SIZE (2) /* Size TC BIAS CALIBRATION */ 38 #define OSCCTRL_DFLL48M_TESTPTSEL_SIZE (3) /* Size TEST POINT SELECTOR */ 39 #define OSCCTRL_DFLL48M_VERSION (0x100) 40 #define OSCCTRL_DFLL48M_WAITLOCK_ACTIVE (1) /* Enable Wait Lock Feature */ 41 #define OSCCTRL_DFLLS_NUM (1) /* Number of DFLLs */ 42 #define OSCCTRL_DFLL_IMPLEMENTED (1) /* DFLL implemented */ 43 #define OSCCTRL_DPLL0_I12ND_I12NDFRAC_PAD_CONTROL (0) /* NOT_IMPLEMENTED: The ND and NDFRAC pad tests are not used, use registers instead */ 44 #define OSCCTRL_DPLL0_IMPLEMENTED (1) /* DPLL0 implemented */ 45 #define OSCCTRL_DPLL0_OCC_IMPLEMENTED (1) /* DPLL0 OCC Implemented */ 46 #define OSCCTRL_DPLL1_I12ND_I12NDFRAC_PAD_CONTROL (0) /* NOT_IMPLEMENTED: The ND and NDFRAC pad tests are not used, use registers instead */ 47 #define OSCCTRL_DPLL1_IMPLEMENTED (1) /* DPLL1 implemented */ 48 #define OSCCTRL_DPLL1_OCC_IMPLEMENTED (0) /* DPLL1 OCC Implemented */ 49 #define OSCCTRL_DPLLS_NUM (2) /* Number of DPLLs */ 50 #define OSCCTRL_FDPLL_VERSION (0x100) 51 #define OSCCTRL_GCLK_ID_DFLL48 (0) /* Index of Generic Clock for DFLL48 */ 52 #define OSCCTRL_GCLK_ID_FDPLL0 (1) /* Index of Generic Clock for DPLL0 */ 53 #define OSCCTRL_GCLK_ID_FDPLL032K (3) /* Index of Generic Clock for DPLL0 32K */ 54 #define OSCCTRL_GCLK_ID_FDPLL1 (2) /* Index of Generic Clock for DPLL1 */ 55 #define OSCCTRL_GCLK_ID_FDPLL132K (3) /* Index of Generic Clock for DPLL1 32K */ 56 #define OSCCTRL_INSTANCE_ID (4) /* Instance index for OSCCTRL */ 57 #define OSCCTRL_OSC16M_IMPLEMENTED (0) /* OSC16M implemented */ 58 #define OSCCTRL_OSC48M_IMPLEMENTED (0) /* OSC48M implemented */ 59 #define OSCCTRL_OSC48M_NUM (1) 60 #define OSCCTRL_RCOSCS_NUM (1) /* Number of RCOSCs (min 1) */ 61 #define OSCCTRL_XOSC0_CFD_CLK_SELECT_SIZE (4) /* Clock fail prescaler size */ 62 #define OSCCTRL_XOSC0_CFD_IMPLEMENTED (1) /* Clock fail detected for xosc implemented */ 63 #define OSCCTRL_XOSC0_IMPLEMENTED (1) /* XOSC0 implemented */ 64 #define OSCCTRL_XOSC0_ONDEMAND_RESET_VALUE (1) /* Run oscillator always or only when requested */ 65 #define OSCCTRL_XOSC0_RUNSTDBY_RESET_VALUE (0) /* Run oscillator even if standby mode */ 66 #define OSCCTRL_XOSC1_CFD_CLK_SELECT_SIZE (4) /* Clock fail prescaler size */ 67 #define OSCCTRL_XOSC1_CFD_IMPLEMENTED (1) /* Clock fail detected for xosc implemented */ 68 #define OSCCTRL_XOSC1_IMPLEMENTED (1) /* XOSC1 implemented */ 69 #define OSCCTRL_XOSC1_ONDEMAND_RESET_VALUE (1) /* Run oscillator always or only when requested */ 70 #define OSCCTRL_XOSC1_RUNSTDBY_RESET_VALUE (0) /* Run oscillator even if standby mode */ 71 #define OSCCTRL_XOSCS_NUM (2) /* Number of XOSCs */ 72 #define OSCCTRL_XOSC_VERSION (0x100) 73 74 #endif /* _PIC32CXSG61_OSCCTRL_INSTANCE_ */ 75
