1 /* 2 * Instance header file for PIC32CX1025SG61128 3 * 4 * Copyright (c) 2023 Microchip Technology Inc. and its subsidiaries. 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 */ 19 20 /* file generated from device description file (ATDF) version 2023-03-17T09:48:59Z */ 21 #ifndef _PIC32CXSG61_CAN0_INSTANCE_ 22 #define _PIC32CXSG61_CAN0_INSTANCE_ 23 24 25 /* ========== Instance Parameter definitions for CAN0 peripheral ========== */ 26 #define CAN0_DMAC_ID_DEBUG (20) /* DMA CAN Debug Req */ 27 #define CAN0_GCLK_ID (27) /* Index of Generic Clock */ 28 #define CAN0_INSTANCE_ID (64) /* Instance index for CAN0 */ 29 #define CAN0_MSG_RAM_ADDR (0x20000000) 30 #define CAN0_QOS_RESET_VAL (1) /* QOS reset value */ 31 32 #endif /* _PIC32CXSG61_CAN0_INSTANCE_ */ 33
