1 /* 2 * Component description for WDT 3 * 4 * Copyright (c) 2023 Microchip Technology Inc. and its subsidiaries. 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 */ 19 20 /* file generated from device description file (ATDF) version 2023-03-17T09:48:59Z */ 21 #ifndef _PIC32CXSG61_WDT_COMPONENT_H_ 22 #define _PIC32CXSG61_WDT_COMPONENT_H_ 23 24 /* ************************************************************************** */ 25 /* SOFTWARE API DEFINITION FOR WDT */ 26 /* ************************************************************************** */ 27 28 /* -------- WDT_CTRLA : (WDT Offset: 0x00) (R/W 8) Control -------- */ 29 #define WDT_CTRLA_RESETVALUE _UINT8_(0x00) /* (WDT_CTRLA) Control Reset Value */ 30 31 #define WDT_CTRLA_ENABLE_Pos _UINT8_(1) /* (WDT_CTRLA) Enable Position */ 32 #define WDT_CTRLA_ENABLE_Msk (_UINT8_(0x1) << WDT_CTRLA_ENABLE_Pos) /* (WDT_CTRLA) Enable Mask */ 33 #define WDT_CTRLA_ENABLE(value) (WDT_CTRLA_ENABLE_Msk & (_UINT8_(value) << WDT_CTRLA_ENABLE_Pos)) /* Assigment of value for ENABLE in the WDT_CTRLA register */ 34 #define WDT_CTRLA_WEN_Pos _UINT8_(2) /* (WDT_CTRLA) Watchdog Timer Window Mode Enable Position */ 35 #define WDT_CTRLA_WEN_Msk (_UINT8_(0x1) << WDT_CTRLA_WEN_Pos) /* (WDT_CTRLA) Watchdog Timer Window Mode Enable Mask */ 36 #define WDT_CTRLA_WEN(value) (WDT_CTRLA_WEN_Msk & (_UINT8_(value) << WDT_CTRLA_WEN_Pos)) /* Assigment of value for WEN in the WDT_CTRLA register */ 37 #define WDT_CTRLA_ALWAYSON_Pos _UINT8_(7) /* (WDT_CTRLA) Always-On Position */ 38 #define WDT_CTRLA_ALWAYSON_Msk (_UINT8_(0x1) << WDT_CTRLA_ALWAYSON_Pos) /* (WDT_CTRLA) Always-On Mask */ 39 #define WDT_CTRLA_ALWAYSON(value) (WDT_CTRLA_ALWAYSON_Msk & (_UINT8_(value) << WDT_CTRLA_ALWAYSON_Pos)) /* Assigment of value for ALWAYSON in the WDT_CTRLA register */ 40 #define WDT_CTRLA_Msk _UINT8_(0x86) /* (WDT_CTRLA) Register Mask */ 41 42 43 /* -------- WDT_CONFIG : (WDT Offset: 0x01) (R/W 8) Configuration -------- */ 44 #define WDT_CONFIG_RESETVALUE _UINT8_(0xBB) /* (WDT_CONFIG) Configuration Reset Value */ 45 46 #define WDT_CONFIG_PER_Pos _UINT8_(0) /* (WDT_CONFIG) Time-Out Period Position */ 47 #define WDT_CONFIG_PER_Msk (_UINT8_(0xF) << WDT_CONFIG_PER_Pos) /* (WDT_CONFIG) Time-Out Period Mask */ 48 #define WDT_CONFIG_PER(value) (WDT_CONFIG_PER_Msk & (_UINT8_(value) << WDT_CONFIG_PER_Pos)) /* Assigment of value for PER in the WDT_CONFIG register */ 49 #define WDT_CONFIG_PER_CYC8_Val _UINT8_(0x0) /* (WDT_CONFIG) 8 clock cycles */ 50 #define WDT_CONFIG_PER_CYC16_Val _UINT8_(0x1) /* (WDT_CONFIG) 16 clock cycles */ 51 #define WDT_CONFIG_PER_CYC32_Val _UINT8_(0x2) /* (WDT_CONFIG) 32 clock cycles */ 52 #define WDT_CONFIG_PER_CYC64_Val _UINT8_(0x3) /* (WDT_CONFIG) 64 clock cycles */ 53 #define WDT_CONFIG_PER_CYC128_Val _UINT8_(0x4) /* (WDT_CONFIG) 128 clock cycles */ 54 #define WDT_CONFIG_PER_CYC256_Val _UINT8_(0x5) /* (WDT_CONFIG) 256 clock cycles */ 55 #define WDT_CONFIG_PER_CYC512_Val _UINT8_(0x6) /* (WDT_CONFIG) 512 clock cycles */ 56 #define WDT_CONFIG_PER_CYC1024_Val _UINT8_(0x7) /* (WDT_CONFIG) 1024 clock cycles */ 57 #define WDT_CONFIG_PER_CYC2048_Val _UINT8_(0x8) /* (WDT_CONFIG) 2048 clock cycles */ 58 #define WDT_CONFIG_PER_CYC4096_Val _UINT8_(0x9) /* (WDT_CONFIG) 4096 clock cycles */ 59 #define WDT_CONFIG_PER_CYC8192_Val _UINT8_(0xA) /* (WDT_CONFIG) 8192 clock cycles */ 60 #define WDT_CONFIG_PER_CYC16384_Val _UINT8_(0xB) /* (WDT_CONFIG) 16384 clock cycles */ 61 #define WDT_CONFIG_PER_CYC8 (WDT_CONFIG_PER_CYC8_Val << WDT_CONFIG_PER_Pos) /* (WDT_CONFIG) 8 clock cycles Position */ 62 #define WDT_CONFIG_PER_CYC16 (WDT_CONFIG_PER_CYC16_Val << WDT_CONFIG_PER_Pos) /* (WDT_CONFIG) 16 clock cycles Position */ 63 #define WDT_CONFIG_PER_CYC32 (WDT_CONFIG_PER_CYC32_Val << WDT_CONFIG_PER_Pos) /* (WDT_CONFIG) 32 clock cycles Position */ 64 #define WDT_CONFIG_PER_CYC64 (WDT_CONFIG_PER_CYC64_Val << WDT_CONFIG_PER_Pos) /* (WDT_CONFIG) 64 clock cycles Position */ 65 #define WDT_CONFIG_PER_CYC128 (WDT_CONFIG_PER_CYC128_Val << WDT_CONFIG_PER_Pos) /* (WDT_CONFIG) 128 clock cycles Position */ 66 #define WDT_CONFIG_PER_CYC256 (WDT_CONFIG_PER_CYC256_Val << WDT_CONFIG_PER_Pos) /* (WDT_CONFIG) 256 clock cycles Position */ 67 #define WDT_CONFIG_PER_CYC512 (WDT_CONFIG_PER_CYC512_Val << WDT_CONFIG_PER_Pos) /* (WDT_CONFIG) 512 clock cycles Position */ 68 #define WDT_CONFIG_PER_CYC1024 (WDT_CONFIG_PER_CYC1024_Val << WDT_CONFIG_PER_Pos) /* (WDT_CONFIG) 1024 clock cycles Position */ 69 #define WDT_CONFIG_PER_CYC2048 (WDT_CONFIG_PER_CYC2048_Val << WDT_CONFIG_PER_Pos) /* (WDT_CONFIG) 2048 clock cycles Position */ 70 #define WDT_CONFIG_PER_CYC4096 (WDT_CONFIG_PER_CYC4096_Val << WDT_CONFIG_PER_Pos) /* (WDT_CONFIG) 4096 clock cycles Position */ 71 #define WDT_CONFIG_PER_CYC8192 (WDT_CONFIG_PER_CYC8192_Val << WDT_CONFIG_PER_Pos) /* (WDT_CONFIG) 8192 clock cycles Position */ 72 #define WDT_CONFIG_PER_CYC16384 (WDT_CONFIG_PER_CYC16384_Val << WDT_CONFIG_PER_Pos) /* (WDT_CONFIG) 16384 clock cycles Position */ 73 #define WDT_CONFIG_WINDOW_Pos _UINT8_(4) /* (WDT_CONFIG) Window Mode Time-Out Period Position */ 74 #define WDT_CONFIG_WINDOW_Msk (_UINT8_(0xF) << WDT_CONFIG_WINDOW_Pos) /* (WDT_CONFIG) Window Mode Time-Out Period Mask */ 75 #define WDT_CONFIG_WINDOW(value) (WDT_CONFIG_WINDOW_Msk & (_UINT8_(value) << WDT_CONFIG_WINDOW_Pos)) /* Assigment of value for WINDOW in the WDT_CONFIG register */ 76 #define WDT_CONFIG_WINDOW_CYC8_Val _UINT8_(0x0) /* (WDT_CONFIG) 8 clock cycles */ 77 #define WDT_CONFIG_WINDOW_CYC16_Val _UINT8_(0x1) /* (WDT_CONFIG) 16 clock cycles */ 78 #define WDT_CONFIG_WINDOW_CYC32_Val _UINT8_(0x2) /* (WDT_CONFIG) 32 clock cycles */ 79 #define WDT_CONFIG_WINDOW_CYC64_Val _UINT8_(0x3) /* (WDT_CONFIG) 64 clock cycles */ 80 #define WDT_CONFIG_WINDOW_CYC128_Val _UINT8_(0x4) /* (WDT_CONFIG) 128 clock cycles */ 81 #define WDT_CONFIG_WINDOW_CYC256_Val _UINT8_(0x5) /* (WDT_CONFIG) 256 clock cycles */ 82 #define WDT_CONFIG_WINDOW_CYC512_Val _UINT8_(0x6) /* (WDT_CONFIG) 512 clock cycles */ 83 #define WDT_CONFIG_WINDOW_CYC1024_Val _UINT8_(0x7) /* (WDT_CONFIG) 1024 clock cycles */ 84 #define WDT_CONFIG_WINDOW_CYC2048_Val _UINT8_(0x8) /* (WDT_CONFIG) 2048 clock cycles */ 85 #define WDT_CONFIG_WINDOW_CYC4096_Val _UINT8_(0x9) /* (WDT_CONFIG) 4096 clock cycles */ 86 #define WDT_CONFIG_WINDOW_CYC8192_Val _UINT8_(0xA) /* (WDT_CONFIG) 8192 clock cycles */ 87 #define WDT_CONFIG_WINDOW_CYC16384_Val _UINT8_(0xB) /* (WDT_CONFIG) 16384 clock cycles */ 88 #define WDT_CONFIG_WINDOW_CYC8 (WDT_CONFIG_WINDOW_CYC8_Val << WDT_CONFIG_WINDOW_Pos) /* (WDT_CONFIG) 8 clock cycles Position */ 89 #define WDT_CONFIG_WINDOW_CYC16 (WDT_CONFIG_WINDOW_CYC16_Val << WDT_CONFIG_WINDOW_Pos) /* (WDT_CONFIG) 16 clock cycles Position */ 90 #define WDT_CONFIG_WINDOW_CYC32 (WDT_CONFIG_WINDOW_CYC32_Val << WDT_CONFIG_WINDOW_Pos) /* (WDT_CONFIG) 32 clock cycles Position */ 91 #define WDT_CONFIG_WINDOW_CYC64 (WDT_CONFIG_WINDOW_CYC64_Val << WDT_CONFIG_WINDOW_Pos) /* (WDT_CONFIG) 64 clock cycles Position */ 92 #define WDT_CONFIG_WINDOW_CYC128 (WDT_CONFIG_WINDOW_CYC128_Val << WDT_CONFIG_WINDOW_Pos) /* (WDT_CONFIG) 128 clock cycles Position */ 93 #define WDT_CONFIG_WINDOW_CYC256 (WDT_CONFIG_WINDOW_CYC256_Val << WDT_CONFIG_WINDOW_Pos) /* (WDT_CONFIG) 256 clock cycles Position */ 94 #define WDT_CONFIG_WINDOW_CYC512 (WDT_CONFIG_WINDOW_CYC512_Val << WDT_CONFIG_WINDOW_Pos) /* (WDT_CONFIG) 512 clock cycles Position */ 95 #define WDT_CONFIG_WINDOW_CYC1024 (WDT_CONFIG_WINDOW_CYC1024_Val << WDT_CONFIG_WINDOW_Pos) /* (WDT_CONFIG) 1024 clock cycles Position */ 96 #define WDT_CONFIG_WINDOW_CYC2048 (WDT_CONFIG_WINDOW_CYC2048_Val << WDT_CONFIG_WINDOW_Pos) /* (WDT_CONFIG) 2048 clock cycles Position */ 97 #define WDT_CONFIG_WINDOW_CYC4096 (WDT_CONFIG_WINDOW_CYC4096_Val << WDT_CONFIG_WINDOW_Pos) /* (WDT_CONFIG) 4096 clock cycles Position */ 98 #define WDT_CONFIG_WINDOW_CYC8192 (WDT_CONFIG_WINDOW_CYC8192_Val << WDT_CONFIG_WINDOW_Pos) /* (WDT_CONFIG) 8192 clock cycles Position */ 99 #define WDT_CONFIG_WINDOW_CYC16384 (WDT_CONFIG_WINDOW_CYC16384_Val << WDT_CONFIG_WINDOW_Pos) /* (WDT_CONFIG) 16384 clock cycles Position */ 100 #define WDT_CONFIG_Msk _UINT8_(0xFF) /* (WDT_CONFIG) Register Mask */ 101 102 103 /* -------- WDT_EWCTRL : (WDT Offset: 0x02) (R/W 8) Early Warning Interrupt Control -------- */ 104 #define WDT_EWCTRL_RESETVALUE _UINT8_(0x0B) /* (WDT_EWCTRL) Early Warning Interrupt Control Reset Value */ 105 106 #define WDT_EWCTRL_EWOFFSET_Pos _UINT8_(0) /* (WDT_EWCTRL) Early Warning Interrupt Time Offset Position */ 107 #define WDT_EWCTRL_EWOFFSET_Msk (_UINT8_(0xF) << WDT_EWCTRL_EWOFFSET_Pos) /* (WDT_EWCTRL) Early Warning Interrupt Time Offset Mask */ 108 #define WDT_EWCTRL_EWOFFSET(value) (WDT_EWCTRL_EWOFFSET_Msk & (_UINT8_(value) << WDT_EWCTRL_EWOFFSET_Pos)) /* Assigment of value for EWOFFSET in the WDT_EWCTRL register */ 109 #define WDT_EWCTRL_EWOFFSET_CYC8_Val _UINT8_(0x0) /* (WDT_EWCTRL) 8 clock cycles */ 110 #define WDT_EWCTRL_EWOFFSET_CYC16_Val _UINT8_(0x1) /* (WDT_EWCTRL) 16 clock cycles */ 111 #define WDT_EWCTRL_EWOFFSET_CYC32_Val _UINT8_(0x2) /* (WDT_EWCTRL) 32 clock cycles */ 112 #define WDT_EWCTRL_EWOFFSET_CYC64_Val _UINT8_(0x3) /* (WDT_EWCTRL) 64 clock cycles */ 113 #define WDT_EWCTRL_EWOFFSET_CYC128_Val _UINT8_(0x4) /* (WDT_EWCTRL) 128 clock cycles */ 114 #define WDT_EWCTRL_EWOFFSET_CYC256_Val _UINT8_(0x5) /* (WDT_EWCTRL) 256 clock cycles */ 115 #define WDT_EWCTRL_EWOFFSET_CYC512_Val _UINT8_(0x6) /* (WDT_EWCTRL) 512 clock cycles */ 116 #define WDT_EWCTRL_EWOFFSET_CYC1024_Val _UINT8_(0x7) /* (WDT_EWCTRL) 1024 clock cycles */ 117 #define WDT_EWCTRL_EWOFFSET_CYC2048_Val _UINT8_(0x8) /* (WDT_EWCTRL) 2048 clock cycles */ 118 #define WDT_EWCTRL_EWOFFSET_CYC4096_Val _UINT8_(0x9) /* (WDT_EWCTRL) 4096 clock cycles */ 119 #define WDT_EWCTRL_EWOFFSET_CYC8192_Val _UINT8_(0xA) /* (WDT_EWCTRL) 8192 clock cycles */ 120 #define WDT_EWCTRL_EWOFFSET_CYC8 (WDT_EWCTRL_EWOFFSET_CYC8_Val << WDT_EWCTRL_EWOFFSET_Pos) /* (WDT_EWCTRL) 8 clock cycles Position */ 121 #define WDT_EWCTRL_EWOFFSET_CYC16 (WDT_EWCTRL_EWOFFSET_CYC16_Val << WDT_EWCTRL_EWOFFSET_Pos) /* (WDT_EWCTRL) 16 clock cycles Position */ 122 #define WDT_EWCTRL_EWOFFSET_CYC32 (WDT_EWCTRL_EWOFFSET_CYC32_Val << WDT_EWCTRL_EWOFFSET_Pos) /* (WDT_EWCTRL) 32 clock cycles Position */ 123 #define WDT_EWCTRL_EWOFFSET_CYC64 (WDT_EWCTRL_EWOFFSET_CYC64_Val << WDT_EWCTRL_EWOFFSET_Pos) /* (WDT_EWCTRL) 64 clock cycles Position */ 124 #define WDT_EWCTRL_EWOFFSET_CYC128 (WDT_EWCTRL_EWOFFSET_CYC128_Val << WDT_EWCTRL_EWOFFSET_Pos) /* (WDT_EWCTRL) 128 clock cycles Position */ 125 #define WDT_EWCTRL_EWOFFSET_CYC256 (WDT_EWCTRL_EWOFFSET_CYC256_Val << WDT_EWCTRL_EWOFFSET_Pos) /* (WDT_EWCTRL) 256 clock cycles Position */ 126 #define WDT_EWCTRL_EWOFFSET_CYC512 (WDT_EWCTRL_EWOFFSET_CYC512_Val << WDT_EWCTRL_EWOFFSET_Pos) /* (WDT_EWCTRL) 512 clock cycles Position */ 127 #define WDT_EWCTRL_EWOFFSET_CYC1024 (WDT_EWCTRL_EWOFFSET_CYC1024_Val << WDT_EWCTRL_EWOFFSET_Pos) /* (WDT_EWCTRL) 1024 clock cycles Position */ 128 #define WDT_EWCTRL_EWOFFSET_CYC2048 (WDT_EWCTRL_EWOFFSET_CYC2048_Val << WDT_EWCTRL_EWOFFSET_Pos) /* (WDT_EWCTRL) 2048 clock cycles Position */ 129 #define WDT_EWCTRL_EWOFFSET_CYC4096 (WDT_EWCTRL_EWOFFSET_CYC4096_Val << WDT_EWCTRL_EWOFFSET_Pos) /* (WDT_EWCTRL) 4096 clock cycles Position */ 130 #define WDT_EWCTRL_EWOFFSET_CYC8192 (WDT_EWCTRL_EWOFFSET_CYC8192_Val << WDT_EWCTRL_EWOFFSET_Pos) /* (WDT_EWCTRL) 8192 clock cycles Position */ 131 #define WDT_EWCTRL_Msk _UINT8_(0x0F) /* (WDT_EWCTRL) Register Mask */ 132 133 134 /* -------- WDT_INTENCLR : (WDT Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ 135 #define WDT_INTENCLR_RESETVALUE _UINT8_(0x00) /* (WDT_INTENCLR) Interrupt Enable Clear Reset Value */ 136 137 #define WDT_INTENCLR_EW_Pos _UINT8_(0) /* (WDT_INTENCLR) Early Warning Interrupt Enable Position */ 138 #define WDT_INTENCLR_EW_Msk (_UINT8_(0x1) << WDT_INTENCLR_EW_Pos) /* (WDT_INTENCLR) Early Warning Interrupt Enable Mask */ 139 #define WDT_INTENCLR_EW(value) (WDT_INTENCLR_EW_Msk & (_UINT8_(value) << WDT_INTENCLR_EW_Pos)) /* Assigment of value for EW in the WDT_INTENCLR register */ 140 #define WDT_INTENCLR_Msk _UINT8_(0x01) /* (WDT_INTENCLR) Register Mask */ 141 142 143 /* -------- WDT_INTENSET : (WDT Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ 144 #define WDT_INTENSET_RESETVALUE _UINT8_(0x00) /* (WDT_INTENSET) Interrupt Enable Set Reset Value */ 145 146 #define WDT_INTENSET_EW_Pos _UINT8_(0) /* (WDT_INTENSET) Early Warning Interrupt Enable Position */ 147 #define WDT_INTENSET_EW_Msk (_UINT8_(0x1) << WDT_INTENSET_EW_Pos) /* (WDT_INTENSET) Early Warning Interrupt Enable Mask */ 148 #define WDT_INTENSET_EW(value) (WDT_INTENSET_EW_Msk & (_UINT8_(value) << WDT_INTENSET_EW_Pos)) /* Assigment of value for EW in the WDT_INTENSET register */ 149 #define WDT_INTENSET_Msk _UINT8_(0x01) /* (WDT_INTENSET) Register Mask */ 150 151 152 /* -------- WDT_INTFLAG : (WDT Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ 153 #define WDT_INTFLAG_RESETVALUE _UINT8_(0x00) /* (WDT_INTFLAG) Interrupt Flag Status and Clear Reset Value */ 154 155 #define WDT_INTFLAG_EW_Pos _UINT8_(0) /* (WDT_INTFLAG) Early Warning Position */ 156 #define WDT_INTFLAG_EW_Msk (_UINT8_(0x1) << WDT_INTFLAG_EW_Pos) /* (WDT_INTFLAG) Early Warning Mask */ 157 #define WDT_INTFLAG_EW(value) (WDT_INTFLAG_EW_Msk & (_UINT8_(value) << WDT_INTFLAG_EW_Pos)) /* Assigment of value for EW in the WDT_INTFLAG register */ 158 #define WDT_INTFLAG_Msk _UINT8_(0x01) /* (WDT_INTFLAG) Register Mask */ 159 160 161 /* -------- WDT_SYNCBUSY : (WDT Offset: 0x08) ( R/ 32) Synchronization Busy -------- */ 162 #define WDT_SYNCBUSY_RESETVALUE _UINT32_(0x00) /* (WDT_SYNCBUSY) Synchronization Busy Reset Value */ 163 164 #define WDT_SYNCBUSY_ENABLE_Pos _UINT32_(1) /* (WDT_SYNCBUSY) Enable Synchronization Busy Position */ 165 #define WDT_SYNCBUSY_ENABLE_Msk (_UINT32_(0x1) << WDT_SYNCBUSY_ENABLE_Pos) /* (WDT_SYNCBUSY) Enable Synchronization Busy Mask */ 166 #define WDT_SYNCBUSY_ENABLE(value) (WDT_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << WDT_SYNCBUSY_ENABLE_Pos)) /* Assigment of value for ENABLE in the WDT_SYNCBUSY register */ 167 #define WDT_SYNCBUSY_WEN_Pos _UINT32_(2) /* (WDT_SYNCBUSY) Window Enable Synchronization Busy Position */ 168 #define WDT_SYNCBUSY_WEN_Msk (_UINT32_(0x1) << WDT_SYNCBUSY_WEN_Pos) /* (WDT_SYNCBUSY) Window Enable Synchronization Busy Mask */ 169 #define WDT_SYNCBUSY_WEN(value) (WDT_SYNCBUSY_WEN_Msk & (_UINT32_(value) << WDT_SYNCBUSY_WEN_Pos)) /* Assigment of value for WEN in the WDT_SYNCBUSY register */ 170 #define WDT_SYNCBUSY_ALWAYSON_Pos _UINT32_(3) /* (WDT_SYNCBUSY) Always-On Synchronization Busy Position */ 171 #define WDT_SYNCBUSY_ALWAYSON_Msk (_UINT32_(0x1) << WDT_SYNCBUSY_ALWAYSON_Pos) /* (WDT_SYNCBUSY) Always-On Synchronization Busy Mask */ 172 #define WDT_SYNCBUSY_ALWAYSON(value) (WDT_SYNCBUSY_ALWAYSON_Msk & (_UINT32_(value) << WDT_SYNCBUSY_ALWAYSON_Pos)) /* Assigment of value for ALWAYSON in the WDT_SYNCBUSY register */ 173 #define WDT_SYNCBUSY_CLEAR_Pos _UINT32_(4) /* (WDT_SYNCBUSY) Clear Synchronization Busy Position */ 174 #define WDT_SYNCBUSY_CLEAR_Msk (_UINT32_(0x1) << WDT_SYNCBUSY_CLEAR_Pos) /* (WDT_SYNCBUSY) Clear Synchronization Busy Mask */ 175 #define WDT_SYNCBUSY_CLEAR(value) (WDT_SYNCBUSY_CLEAR_Msk & (_UINT32_(value) << WDT_SYNCBUSY_CLEAR_Pos)) /* Assigment of value for CLEAR in the WDT_SYNCBUSY register */ 176 #define WDT_SYNCBUSY_Msk _UINT32_(0x0000001E) /* (WDT_SYNCBUSY) Register Mask */ 177 178 179 /* -------- WDT_CLEAR : (WDT Offset: 0x0C) ( /W 8) Clear -------- */ 180 #define WDT_CLEAR_RESETVALUE _UINT8_(0x00) /* (WDT_CLEAR) Clear Reset Value */ 181 182 #define WDT_CLEAR_CLEAR_Pos _UINT8_(0) /* (WDT_CLEAR) Watchdog Clear Position */ 183 #define WDT_CLEAR_CLEAR_Msk (_UINT8_(0xFF) << WDT_CLEAR_CLEAR_Pos) /* (WDT_CLEAR) Watchdog Clear Mask */ 184 #define WDT_CLEAR_CLEAR(value) (WDT_CLEAR_CLEAR_Msk & (_UINT8_(value) << WDT_CLEAR_CLEAR_Pos)) /* Assigment of value for CLEAR in the WDT_CLEAR register */ 185 #define WDT_CLEAR_CLEAR_KEY_Val _UINT8_(0xA5) /* (WDT_CLEAR) Clear Key */ 186 #define WDT_CLEAR_CLEAR_KEY (WDT_CLEAR_CLEAR_KEY_Val << WDT_CLEAR_CLEAR_Pos) /* (WDT_CLEAR) Clear Key Position */ 187 #define WDT_CLEAR_Msk _UINT8_(0xFF) /* (WDT_CLEAR) Register Mask */ 188 189 190 /** \brief WDT register offsets definitions */ 191 #define WDT_CTRLA_REG_OFST _UINT32_(0x00) /* (WDT_CTRLA) Control Offset */ 192 #define WDT_CONFIG_REG_OFST _UINT32_(0x01) /* (WDT_CONFIG) Configuration Offset */ 193 #define WDT_EWCTRL_REG_OFST _UINT32_(0x02) /* (WDT_EWCTRL) Early Warning Interrupt Control Offset */ 194 #define WDT_INTENCLR_REG_OFST _UINT32_(0x04) /* (WDT_INTENCLR) Interrupt Enable Clear Offset */ 195 #define WDT_INTENSET_REG_OFST _UINT32_(0x05) /* (WDT_INTENSET) Interrupt Enable Set Offset */ 196 #define WDT_INTFLAG_REG_OFST _UINT32_(0x06) /* (WDT_INTFLAG) Interrupt Flag Status and Clear Offset */ 197 #define WDT_SYNCBUSY_REG_OFST _UINT32_(0x08) /* (WDT_SYNCBUSY) Synchronization Busy Offset */ 198 #define WDT_CLEAR_REG_OFST _UINT32_(0x0C) /* (WDT_CLEAR) Clear Offset */ 199 200 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 201 /** \brief WDT register API structure */ 202 typedef struct 203 { /* Watchdog Timer */ 204 __IO uint8_t WDT_CTRLA; /**< Offset: 0x00 (R/W 8) Control */ 205 __IO uint8_t WDT_CONFIG; /**< Offset: 0x01 (R/W 8) Configuration */ 206 __IO uint8_t WDT_EWCTRL; /**< Offset: 0x02 (R/W 8) Early Warning Interrupt Control */ 207 __I uint8_t Reserved1[0x01]; 208 __IO uint8_t WDT_INTENCLR; /**< Offset: 0x04 (R/W 8) Interrupt Enable Clear */ 209 __IO uint8_t WDT_INTENSET; /**< Offset: 0x05 (R/W 8) Interrupt Enable Set */ 210 __IO uint8_t WDT_INTFLAG; /**< Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ 211 __I uint8_t Reserved2[0x01]; 212 __I uint32_t WDT_SYNCBUSY; /**< Offset: 0x08 (R/ 32) Synchronization Busy */ 213 __O uint8_t WDT_CLEAR; /**< Offset: 0x0C ( /W 8) Clear */ 214 } wdt_registers_t; 215 216 217 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 218 #endif /* _PIC32CXSG61_WDT_COMPONENT_H_ */ 219
