1 /* 2 * Component description for TRNG 3 * 4 * Copyright (c) 2023 Microchip Technology Inc. and its subsidiaries. 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 */ 19 20 /* file generated from device description file (ATDF) version 2023-03-17T09:48:59Z */ 21 #ifndef _PIC32CXSG61_TRNG_COMPONENT_H_ 22 #define _PIC32CXSG61_TRNG_COMPONENT_H_ 23 24 /* ************************************************************************** */ 25 /* SOFTWARE API DEFINITION FOR TRNG */ 26 /* ************************************************************************** */ 27 28 /* -------- TRNG_CTRLA : (TRNG Offset: 0x00) (R/W 8) Control A -------- */ 29 #define TRNG_CTRLA_RESETVALUE _UINT8_(0x00) /* (TRNG_CTRLA) Control A Reset Value */ 30 31 #define TRNG_CTRLA_ENABLE_Pos _UINT8_(1) /* (TRNG_CTRLA) Enable Position */ 32 #define TRNG_CTRLA_ENABLE_Msk (_UINT8_(0x1) << TRNG_CTRLA_ENABLE_Pos) /* (TRNG_CTRLA) Enable Mask */ 33 #define TRNG_CTRLA_ENABLE(value) (TRNG_CTRLA_ENABLE_Msk & (_UINT8_(value) << TRNG_CTRLA_ENABLE_Pos)) /* Assigment of value for ENABLE in the TRNG_CTRLA register */ 34 #define TRNG_CTRLA_RUNSTDBY_Pos _UINT8_(6) /* (TRNG_CTRLA) Run in Standby Position */ 35 #define TRNG_CTRLA_RUNSTDBY_Msk (_UINT8_(0x1) << TRNG_CTRLA_RUNSTDBY_Pos) /* (TRNG_CTRLA) Run in Standby Mask */ 36 #define TRNG_CTRLA_RUNSTDBY(value) (TRNG_CTRLA_RUNSTDBY_Msk & (_UINT8_(value) << TRNG_CTRLA_RUNSTDBY_Pos)) /* Assigment of value for RUNSTDBY in the TRNG_CTRLA register */ 37 #define TRNG_CTRLA_Msk _UINT8_(0x42) /* (TRNG_CTRLA) Register Mask */ 38 39 40 /* -------- TRNG_EVCTRL : (TRNG Offset: 0x04) (R/W 8) Event Control -------- */ 41 #define TRNG_EVCTRL_RESETVALUE _UINT8_(0x00) /* (TRNG_EVCTRL) Event Control Reset Value */ 42 43 #define TRNG_EVCTRL_DATARDYEO_Pos _UINT8_(0) /* (TRNG_EVCTRL) Data Ready Event Output Position */ 44 #define TRNG_EVCTRL_DATARDYEO_Msk (_UINT8_(0x1) << TRNG_EVCTRL_DATARDYEO_Pos) /* (TRNG_EVCTRL) Data Ready Event Output Mask */ 45 #define TRNG_EVCTRL_DATARDYEO(value) (TRNG_EVCTRL_DATARDYEO_Msk & (_UINT8_(value) << TRNG_EVCTRL_DATARDYEO_Pos)) /* Assigment of value for DATARDYEO in the TRNG_EVCTRL register */ 46 #define TRNG_EVCTRL_Msk _UINT8_(0x01) /* (TRNG_EVCTRL) Register Mask */ 47 48 49 /* -------- TRNG_INTENCLR : (TRNG Offset: 0x08) (R/W 8) Interrupt Enable Clear -------- */ 50 #define TRNG_INTENCLR_RESETVALUE _UINT8_(0x00) /* (TRNG_INTENCLR) Interrupt Enable Clear Reset Value */ 51 52 #define TRNG_INTENCLR_DATARDY_Pos _UINT8_(0) /* (TRNG_INTENCLR) Data Ready Interrupt Enable Position */ 53 #define TRNG_INTENCLR_DATARDY_Msk (_UINT8_(0x1) << TRNG_INTENCLR_DATARDY_Pos) /* (TRNG_INTENCLR) Data Ready Interrupt Enable Mask */ 54 #define TRNG_INTENCLR_DATARDY(value) (TRNG_INTENCLR_DATARDY_Msk & (_UINT8_(value) << TRNG_INTENCLR_DATARDY_Pos)) /* Assigment of value for DATARDY in the TRNG_INTENCLR register */ 55 #define TRNG_INTENCLR_Msk _UINT8_(0x01) /* (TRNG_INTENCLR) Register Mask */ 56 57 58 /* -------- TRNG_INTENSET : (TRNG Offset: 0x09) (R/W 8) Interrupt Enable Set -------- */ 59 #define TRNG_INTENSET_RESETVALUE _UINT8_(0x00) /* (TRNG_INTENSET) Interrupt Enable Set Reset Value */ 60 61 #define TRNG_INTENSET_DATARDY_Pos _UINT8_(0) /* (TRNG_INTENSET) Data Ready Interrupt Enable Position */ 62 #define TRNG_INTENSET_DATARDY_Msk (_UINT8_(0x1) << TRNG_INTENSET_DATARDY_Pos) /* (TRNG_INTENSET) Data Ready Interrupt Enable Mask */ 63 #define TRNG_INTENSET_DATARDY(value) (TRNG_INTENSET_DATARDY_Msk & (_UINT8_(value) << TRNG_INTENSET_DATARDY_Pos)) /* Assigment of value for DATARDY in the TRNG_INTENSET register */ 64 #define TRNG_INTENSET_Msk _UINT8_(0x01) /* (TRNG_INTENSET) Register Mask */ 65 66 67 /* -------- TRNG_INTFLAG : (TRNG Offset: 0x0A) (R/W 8) Interrupt Flag Status and Clear -------- */ 68 #define TRNG_INTFLAG_RESETVALUE _UINT8_(0x00) /* (TRNG_INTFLAG) Interrupt Flag Status and Clear Reset Value */ 69 70 #define TRNG_INTFLAG_DATARDY_Pos _UINT8_(0) /* (TRNG_INTFLAG) Data Ready Interrupt Flag Position */ 71 #define TRNG_INTFLAG_DATARDY_Msk (_UINT8_(0x1) << TRNG_INTFLAG_DATARDY_Pos) /* (TRNG_INTFLAG) Data Ready Interrupt Flag Mask */ 72 #define TRNG_INTFLAG_DATARDY(value) (TRNG_INTFLAG_DATARDY_Msk & (_UINT8_(value) << TRNG_INTFLAG_DATARDY_Pos)) /* Assigment of value for DATARDY in the TRNG_INTFLAG register */ 73 #define TRNG_INTFLAG_Msk _UINT8_(0x01) /* (TRNG_INTFLAG) Register Mask */ 74 75 76 /* -------- TRNG_DATA : (TRNG Offset: 0x20) ( R/ 32) Output Data -------- */ 77 #define TRNG_DATA_RESETVALUE _UINT32_(0x00) /* (TRNG_DATA) Output Data Reset Value */ 78 79 #define TRNG_DATA_DATA_Pos _UINT32_(0) /* (TRNG_DATA) Output Data Position */ 80 #define TRNG_DATA_DATA_Msk (_UINT32_(0xFFFFFFFF) << TRNG_DATA_DATA_Pos) /* (TRNG_DATA) Output Data Mask */ 81 #define TRNG_DATA_DATA(value) (TRNG_DATA_DATA_Msk & (_UINT32_(value) << TRNG_DATA_DATA_Pos)) /* Assigment of value for DATA in the TRNG_DATA register */ 82 #define TRNG_DATA_Msk _UINT32_(0xFFFFFFFF) /* (TRNG_DATA) Register Mask */ 83 84 85 /** \brief TRNG register offsets definitions */ 86 #define TRNG_CTRLA_REG_OFST _UINT32_(0x00) /* (TRNG_CTRLA) Control A Offset */ 87 #define TRNG_EVCTRL_REG_OFST _UINT32_(0x04) /* (TRNG_EVCTRL) Event Control Offset */ 88 #define TRNG_INTENCLR_REG_OFST _UINT32_(0x08) /* (TRNG_INTENCLR) Interrupt Enable Clear Offset */ 89 #define TRNG_INTENSET_REG_OFST _UINT32_(0x09) /* (TRNG_INTENSET) Interrupt Enable Set Offset */ 90 #define TRNG_INTFLAG_REG_OFST _UINT32_(0x0A) /* (TRNG_INTFLAG) Interrupt Flag Status and Clear Offset */ 91 #define TRNG_DATA_REG_OFST _UINT32_(0x20) /* (TRNG_DATA) Output Data Offset */ 92 93 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 94 /** \brief TRNG register API structure */ 95 typedef struct 96 { /* True Random Generator */ 97 __IO uint8_t TRNG_CTRLA; /**< Offset: 0x00 (R/W 8) Control A */ 98 __I uint8_t Reserved1[0x03]; 99 __IO uint8_t TRNG_EVCTRL; /**< Offset: 0x04 (R/W 8) Event Control */ 100 __I uint8_t Reserved2[0x03]; 101 __IO uint8_t TRNG_INTENCLR; /**< Offset: 0x08 (R/W 8) Interrupt Enable Clear */ 102 __IO uint8_t TRNG_INTENSET; /**< Offset: 0x09 (R/W 8) Interrupt Enable Set */ 103 __IO uint8_t TRNG_INTFLAG; /**< Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */ 104 __I uint8_t Reserved3[0x15]; 105 __I uint32_t TRNG_DATA; /**< Offset: 0x20 (R/ 32) Output Data */ 106 } trng_registers_t; 107 108 109 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 110 #endif /* _PIC32CXSG61_TRNG_COMPONENT_H_ */ 111
