1 /* 2 * Component description for SDHC 3 * 4 * Copyright (c) 2023 Microchip Technology Inc. and its subsidiaries. 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 */ 19 20 /* file generated from device description file (ATDF) version 2023-03-17T09:48:59Z */ 21 #ifndef _PIC32CXSG61_SDHC_COMPONENT_H_ 22 #define _PIC32CXSG61_SDHC_COMPONENT_H_ 23 24 /* ************************************************************************** */ 25 /* SOFTWARE API DEFINITION FOR SDHC */ 26 /* ************************************************************************** */ 27 28 /* -------- SDHC_SSAR : (SDHC Offset: 0x00) (R/W 32) SDMA System Address / Argument 2 -------- */ 29 #define SDHC_SSAR_RESETVALUE _UINT32_(0x00) /* (SDHC_SSAR) SDMA System Address / Argument 2 Reset Value */ 30 31 #define SDHC_SSAR_ADDR_Pos _UINT32_(0) /* (SDHC_SSAR) SDMA System Address Position */ 32 #define SDHC_SSAR_ADDR_Msk (_UINT32_(0xFFFFFFFF) << SDHC_SSAR_ADDR_Pos) /* (SDHC_SSAR) SDMA System Address Mask */ 33 #define SDHC_SSAR_ADDR(value) (SDHC_SSAR_ADDR_Msk & (_UINT32_(value) << SDHC_SSAR_ADDR_Pos)) /* Assigment of value for ADDR in the SDHC_SSAR register */ 34 #define SDHC_SSAR_Msk _UINT32_(0xFFFFFFFF) /* (SDHC_SSAR) Register Mask */ 35 36 /* CMD23 mode */ 37 #define SDHC_SSAR_CMD23_ARG2_Pos _UINT32_(0) /* (SDHC_SSAR) Argument 2 Position */ 38 #define SDHC_SSAR_CMD23_ARG2_Msk (_UINT32_(0xFFFFFFFF) << SDHC_SSAR_CMD23_ARG2_Pos) /* (SDHC_SSAR) Argument 2 Mask */ 39 #define SDHC_SSAR_CMD23_ARG2(value) (SDHC_SSAR_CMD23_ARG2_Msk & (_UINT32_(value) << SDHC_SSAR_CMD23_ARG2_Pos)) 40 #define SDHC_SSAR_CMD23_Msk _UINT32_(0xFFFFFFFF) /* (SDHC_SSAR_CMD23) Register Mask */ 41 42 43 /* -------- SDHC_BSR : (SDHC Offset: 0x04) (R/W 16) Block Size -------- */ 44 #define SDHC_BSR_RESETVALUE _UINT16_(0x00) /* (SDHC_BSR) Block Size Reset Value */ 45 46 #define SDHC_BSR_BLOCKSIZE_Pos _UINT16_(0) /* (SDHC_BSR) Transfer Block Size Position */ 47 #define SDHC_BSR_BLOCKSIZE_Msk (_UINT16_(0x3FF) << SDHC_BSR_BLOCKSIZE_Pos) /* (SDHC_BSR) Transfer Block Size Mask */ 48 #define SDHC_BSR_BLOCKSIZE(value) (SDHC_BSR_BLOCKSIZE_Msk & (_UINT16_(value) << SDHC_BSR_BLOCKSIZE_Pos)) /* Assigment of value for BLOCKSIZE in the SDHC_BSR register */ 49 #define SDHC_BSR_BOUNDARY_Pos _UINT16_(12) /* (SDHC_BSR) SDMA Buffer Boundary Position */ 50 #define SDHC_BSR_BOUNDARY_Msk (_UINT16_(0x7) << SDHC_BSR_BOUNDARY_Pos) /* (SDHC_BSR) SDMA Buffer Boundary Mask */ 51 #define SDHC_BSR_BOUNDARY(value) (SDHC_BSR_BOUNDARY_Msk & (_UINT16_(value) << SDHC_BSR_BOUNDARY_Pos)) /* Assigment of value for BOUNDARY in the SDHC_BSR register */ 52 #define SDHC_BSR_BOUNDARY_4K_Val _UINT16_(0x0) /* (SDHC_BSR) 4k bytes */ 53 #define SDHC_BSR_BOUNDARY_8K_Val _UINT16_(0x1) /* (SDHC_BSR) 8k bytes */ 54 #define SDHC_BSR_BOUNDARY_16K_Val _UINT16_(0x2) /* (SDHC_BSR) 16k bytes */ 55 #define SDHC_BSR_BOUNDARY_32K_Val _UINT16_(0x3) /* (SDHC_BSR) 32k bytes */ 56 #define SDHC_BSR_BOUNDARY_64K_Val _UINT16_(0x4) /* (SDHC_BSR) 64k bytes */ 57 #define SDHC_BSR_BOUNDARY_128K_Val _UINT16_(0x5) /* (SDHC_BSR) 128k bytes */ 58 #define SDHC_BSR_BOUNDARY_256K_Val _UINT16_(0x6) /* (SDHC_BSR) 256k bytes */ 59 #define SDHC_BSR_BOUNDARY_512K_Val _UINT16_(0x7) /* (SDHC_BSR) 512k bytes */ 60 #define SDHC_BSR_BOUNDARY_4K (SDHC_BSR_BOUNDARY_4K_Val << SDHC_BSR_BOUNDARY_Pos) /* (SDHC_BSR) 4k bytes Position */ 61 #define SDHC_BSR_BOUNDARY_8K (SDHC_BSR_BOUNDARY_8K_Val << SDHC_BSR_BOUNDARY_Pos) /* (SDHC_BSR) 8k bytes Position */ 62 #define SDHC_BSR_BOUNDARY_16K (SDHC_BSR_BOUNDARY_16K_Val << SDHC_BSR_BOUNDARY_Pos) /* (SDHC_BSR) 16k bytes Position */ 63 #define SDHC_BSR_BOUNDARY_32K (SDHC_BSR_BOUNDARY_32K_Val << SDHC_BSR_BOUNDARY_Pos) /* (SDHC_BSR) 32k bytes Position */ 64 #define SDHC_BSR_BOUNDARY_64K (SDHC_BSR_BOUNDARY_64K_Val << SDHC_BSR_BOUNDARY_Pos) /* (SDHC_BSR) 64k bytes Position */ 65 #define SDHC_BSR_BOUNDARY_128K (SDHC_BSR_BOUNDARY_128K_Val << SDHC_BSR_BOUNDARY_Pos) /* (SDHC_BSR) 128k bytes Position */ 66 #define SDHC_BSR_BOUNDARY_256K (SDHC_BSR_BOUNDARY_256K_Val << SDHC_BSR_BOUNDARY_Pos) /* (SDHC_BSR) 256k bytes Position */ 67 #define SDHC_BSR_BOUNDARY_512K (SDHC_BSR_BOUNDARY_512K_Val << SDHC_BSR_BOUNDARY_Pos) /* (SDHC_BSR) 512k bytes Position */ 68 #define SDHC_BSR_Msk _UINT16_(0x73FF) /* (SDHC_BSR) Register Mask */ 69 70 71 /* -------- SDHC_BCR : (SDHC Offset: 0x06) (R/W 16) Block Count -------- */ 72 #define SDHC_BCR_RESETVALUE _UINT16_(0x00) /* (SDHC_BCR) Block Count Reset Value */ 73 74 #define SDHC_BCR_BCNT_Pos _UINT16_(0) /* (SDHC_BCR) Blocks Count for Current Transfer Position */ 75 #define SDHC_BCR_BCNT_Msk (_UINT16_(0xFFFF) << SDHC_BCR_BCNT_Pos) /* (SDHC_BCR) Blocks Count for Current Transfer Mask */ 76 #define SDHC_BCR_BCNT(value) (SDHC_BCR_BCNT_Msk & (_UINT16_(value) << SDHC_BCR_BCNT_Pos)) /* Assigment of value for BCNT in the SDHC_BCR register */ 77 #define SDHC_BCR_Msk _UINT16_(0xFFFF) /* (SDHC_BCR) Register Mask */ 78 79 80 /* -------- SDHC_ARG1R : (SDHC Offset: 0x08) (R/W 32) Argument 1 -------- */ 81 #define SDHC_ARG1R_RESETVALUE _UINT32_(0x00) /* (SDHC_ARG1R) Argument 1 Reset Value */ 82 83 #define SDHC_ARG1R_ARG_Pos _UINT32_(0) /* (SDHC_ARG1R) Argument 1 Position */ 84 #define SDHC_ARG1R_ARG_Msk (_UINT32_(0xFFFFFFFF) << SDHC_ARG1R_ARG_Pos) /* (SDHC_ARG1R) Argument 1 Mask */ 85 #define SDHC_ARG1R_ARG(value) (SDHC_ARG1R_ARG_Msk & (_UINT32_(value) << SDHC_ARG1R_ARG_Pos)) /* Assigment of value for ARG in the SDHC_ARG1R register */ 86 #define SDHC_ARG1R_Msk _UINT32_(0xFFFFFFFF) /* (SDHC_ARG1R) Register Mask */ 87 88 89 /* -------- SDHC_TMR : (SDHC Offset: 0x0C) (R/W 16) Transfer Mode -------- */ 90 #define SDHC_TMR_RESETVALUE _UINT16_(0x00) /* (SDHC_TMR) Transfer Mode Reset Value */ 91 92 #define SDHC_TMR_DMAEN_Pos _UINT16_(0) /* (SDHC_TMR) DMA Enable Position */ 93 #define SDHC_TMR_DMAEN_Msk (_UINT16_(0x1) << SDHC_TMR_DMAEN_Pos) /* (SDHC_TMR) DMA Enable Mask */ 94 #define SDHC_TMR_DMAEN(value) (SDHC_TMR_DMAEN_Msk & (_UINT16_(value) << SDHC_TMR_DMAEN_Pos)) /* Assigment of value for DMAEN in the SDHC_TMR register */ 95 #define SDHC_TMR_DMAEN_DISABLE_Val _UINT16_(0x0) /* (SDHC_TMR) No data transfer or Non DMA data transfer */ 96 #define SDHC_TMR_DMAEN_ENABLE_Val _UINT16_(0x1) /* (SDHC_TMR) DMA data transfer */ 97 #define SDHC_TMR_DMAEN_DISABLE (SDHC_TMR_DMAEN_DISABLE_Val << SDHC_TMR_DMAEN_Pos) /* (SDHC_TMR) No data transfer or Non DMA data transfer Position */ 98 #define SDHC_TMR_DMAEN_ENABLE (SDHC_TMR_DMAEN_ENABLE_Val << SDHC_TMR_DMAEN_Pos) /* (SDHC_TMR) DMA data transfer Position */ 99 #define SDHC_TMR_BCEN_Pos _UINT16_(1) /* (SDHC_TMR) Block Count Enable Position */ 100 #define SDHC_TMR_BCEN_Msk (_UINT16_(0x1) << SDHC_TMR_BCEN_Pos) /* (SDHC_TMR) Block Count Enable Mask */ 101 #define SDHC_TMR_BCEN(value) (SDHC_TMR_BCEN_Msk & (_UINT16_(value) << SDHC_TMR_BCEN_Pos)) /* Assigment of value for BCEN in the SDHC_TMR register */ 102 #define SDHC_TMR_BCEN_DISABLE_Val _UINT16_(0x0) /* (SDHC_TMR) Disable */ 103 #define SDHC_TMR_BCEN_ENABLE_Val _UINT16_(0x1) /* (SDHC_TMR) Enable */ 104 #define SDHC_TMR_BCEN_DISABLE (SDHC_TMR_BCEN_DISABLE_Val << SDHC_TMR_BCEN_Pos) /* (SDHC_TMR) Disable Position */ 105 #define SDHC_TMR_BCEN_ENABLE (SDHC_TMR_BCEN_ENABLE_Val << SDHC_TMR_BCEN_Pos) /* (SDHC_TMR) Enable Position */ 106 #define SDHC_TMR_ACMDEN_Pos _UINT16_(2) /* (SDHC_TMR) Auto Command Enable Position */ 107 #define SDHC_TMR_ACMDEN_Msk (_UINT16_(0x3) << SDHC_TMR_ACMDEN_Pos) /* (SDHC_TMR) Auto Command Enable Mask */ 108 #define SDHC_TMR_ACMDEN(value) (SDHC_TMR_ACMDEN_Msk & (_UINT16_(value) << SDHC_TMR_ACMDEN_Pos)) /* Assigment of value for ACMDEN in the SDHC_TMR register */ 109 #define SDHC_TMR_ACMDEN_DISABLED_Val _UINT16_(0x0) /* (SDHC_TMR) Auto Command Disabled */ 110 #define SDHC_TMR_ACMDEN_CMD12_Val _UINT16_(0x1) /* (SDHC_TMR) Auto CMD12 Enable */ 111 #define SDHC_TMR_ACMDEN_CMD23_Val _UINT16_(0x2) /* (SDHC_TMR) Auto CMD23 Enable */ 112 #define SDHC_TMR_ACMDEN_DISABLED (SDHC_TMR_ACMDEN_DISABLED_Val << SDHC_TMR_ACMDEN_Pos) /* (SDHC_TMR) Auto Command Disabled Position */ 113 #define SDHC_TMR_ACMDEN_CMD12 (SDHC_TMR_ACMDEN_CMD12_Val << SDHC_TMR_ACMDEN_Pos) /* (SDHC_TMR) Auto CMD12 Enable Position */ 114 #define SDHC_TMR_ACMDEN_CMD23 (SDHC_TMR_ACMDEN_CMD23_Val << SDHC_TMR_ACMDEN_Pos) /* (SDHC_TMR) Auto CMD23 Enable Position */ 115 #define SDHC_TMR_DTDSEL_Pos _UINT16_(4) /* (SDHC_TMR) Data Transfer Direction Selection Position */ 116 #define SDHC_TMR_DTDSEL_Msk (_UINT16_(0x1) << SDHC_TMR_DTDSEL_Pos) /* (SDHC_TMR) Data Transfer Direction Selection Mask */ 117 #define SDHC_TMR_DTDSEL(value) (SDHC_TMR_DTDSEL_Msk & (_UINT16_(value) << SDHC_TMR_DTDSEL_Pos)) /* Assigment of value for DTDSEL in the SDHC_TMR register */ 118 #define SDHC_TMR_DTDSEL_WRITE_Val _UINT16_(0x0) /* (SDHC_TMR) Write (Host to Card) */ 119 #define SDHC_TMR_DTDSEL_READ_Val _UINT16_(0x1) /* (SDHC_TMR) Read (Card to Host) */ 120 #define SDHC_TMR_DTDSEL_WRITE (SDHC_TMR_DTDSEL_WRITE_Val << SDHC_TMR_DTDSEL_Pos) /* (SDHC_TMR) Write (Host to Card) Position */ 121 #define SDHC_TMR_DTDSEL_READ (SDHC_TMR_DTDSEL_READ_Val << SDHC_TMR_DTDSEL_Pos) /* (SDHC_TMR) Read (Card to Host) Position */ 122 #define SDHC_TMR_MSBSEL_Pos _UINT16_(5) /* (SDHC_TMR) Multi/Single Block Selection Position */ 123 #define SDHC_TMR_MSBSEL_Msk (_UINT16_(0x1) << SDHC_TMR_MSBSEL_Pos) /* (SDHC_TMR) Multi/Single Block Selection Mask */ 124 #define SDHC_TMR_MSBSEL(value) (SDHC_TMR_MSBSEL_Msk & (_UINT16_(value) << SDHC_TMR_MSBSEL_Pos)) /* Assigment of value for MSBSEL in the SDHC_TMR register */ 125 #define SDHC_TMR_MSBSEL_SINGLE_Val _UINT16_(0x0) /* (SDHC_TMR) Single Block */ 126 #define SDHC_TMR_MSBSEL_MULTIPLE_Val _UINT16_(0x1) /* (SDHC_TMR) Multiple Block */ 127 #define SDHC_TMR_MSBSEL_SINGLE (SDHC_TMR_MSBSEL_SINGLE_Val << SDHC_TMR_MSBSEL_Pos) /* (SDHC_TMR) Single Block Position */ 128 #define SDHC_TMR_MSBSEL_MULTIPLE (SDHC_TMR_MSBSEL_MULTIPLE_Val << SDHC_TMR_MSBSEL_Pos) /* (SDHC_TMR) Multiple Block Position */ 129 #define SDHC_TMR_Msk _UINT16_(0x003F) /* (SDHC_TMR) Register Mask */ 130 131 132 /* -------- SDHC_CR : (SDHC Offset: 0x0E) (R/W 16) Command -------- */ 133 #define SDHC_CR_RESETVALUE _UINT16_(0x00) /* (SDHC_CR) Command Reset Value */ 134 135 #define SDHC_CR_RESPTYP_Pos _UINT16_(0) /* (SDHC_CR) Response Type Position */ 136 #define SDHC_CR_RESPTYP_Msk (_UINT16_(0x3) << SDHC_CR_RESPTYP_Pos) /* (SDHC_CR) Response Type Mask */ 137 #define SDHC_CR_RESPTYP(value) (SDHC_CR_RESPTYP_Msk & (_UINT16_(value) << SDHC_CR_RESPTYP_Pos)) /* Assigment of value for RESPTYP in the SDHC_CR register */ 138 #define SDHC_CR_RESPTYP_NONE_Val _UINT16_(0x0) /* (SDHC_CR) No response */ 139 #define SDHC_CR_RESPTYP_136_BIT_Val _UINT16_(0x1) /* (SDHC_CR) 136-bit response */ 140 #define SDHC_CR_RESPTYP_48_BIT_Val _UINT16_(0x2) /* (SDHC_CR) 48-bit response */ 141 #define SDHC_CR_RESPTYP_48_BIT_BUSY_Val _UINT16_(0x3) /* (SDHC_CR) 48-bit response check busy after response */ 142 #define SDHC_CR_RESPTYP_NONE (SDHC_CR_RESPTYP_NONE_Val << SDHC_CR_RESPTYP_Pos) /* (SDHC_CR) No response Position */ 143 #define SDHC_CR_RESPTYP_136_BIT (SDHC_CR_RESPTYP_136_BIT_Val << SDHC_CR_RESPTYP_Pos) /* (SDHC_CR) 136-bit response Position */ 144 #define SDHC_CR_RESPTYP_48_BIT (SDHC_CR_RESPTYP_48_BIT_Val << SDHC_CR_RESPTYP_Pos) /* (SDHC_CR) 48-bit response Position */ 145 #define SDHC_CR_RESPTYP_48_BIT_BUSY (SDHC_CR_RESPTYP_48_BIT_BUSY_Val << SDHC_CR_RESPTYP_Pos) /* (SDHC_CR) 48-bit response check busy after response Position */ 146 #define SDHC_CR_CMDCCEN_Pos _UINT16_(3) /* (SDHC_CR) Command CRC Check Enable Position */ 147 #define SDHC_CR_CMDCCEN_Msk (_UINT16_(0x1) << SDHC_CR_CMDCCEN_Pos) /* (SDHC_CR) Command CRC Check Enable Mask */ 148 #define SDHC_CR_CMDCCEN(value) (SDHC_CR_CMDCCEN_Msk & (_UINT16_(value) << SDHC_CR_CMDCCEN_Pos)) /* Assigment of value for CMDCCEN in the SDHC_CR register */ 149 #define SDHC_CR_CMDCCEN_DISABLE_Val _UINT16_(0x0) /* (SDHC_CR) Disable */ 150 #define SDHC_CR_CMDCCEN_ENABLE_Val _UINT16_(0x1) /* (SDHC_CR) Enable */ 151 #define SDHC_CR_CMDCCEN_DISABLE (SDHC_CR_CMDCCEN_DISABLE_Val << SDHC_CR_CMDCCEN_Pos) /* (SDHC_CR) Disable Position */ 152 #define SDHC_CR_CMDCCEN_ENABLE (SDHC_CR_CMDCCEN_ENABLE_Val << SDHC_CR_CMDCCEN_Pos) /* (SDHC_CR) Enable Position */ 153 #define SDHC_CR_CMDICEN_Pos _UINT16_(4) /* (SDHC_CR) Command Index Check Enable Position */ 154 #define SDHC_CR_CMDICEN_Msk (_UINT16_(0x1) << SDHC_CR_CMDICEN_Pos) /* (SDHC_CR) Command Index Check Enable Mask */ 155 #define SDHC_CR_CMDICEN(value) (SDHC_CR_CMDICEN_Msk & (_UINT16_(value) << SDHC_CR_CMDICEN_Pos)) /* Assigment of value for CMDICEN in the SDHC_CR register */ 156 #define SDHC_CR_CMDICEN_DISABLE_Val _UINT16_(0x0) /* (SDHC_CR) Disable */ 157 #define SDHC_CR_CMDICEN_ENABLE_Val _UINT16_(0x1) /* (SDHC_CR) Enable */ 158 #define SDHC_CR_CMDICEN_DISABLE (SDHC_CR_CMDICEN_DISABLE_Val << SDHC_CR_CMDICEN_Pos) /* (SDHC_CR) Disable Position */ 159 #define SDHC_CR_CMDICEN_ENABLE (SDHC_CR_CMDICEN_ENABLE_Val << SDHC_CR_CMDICEN_Pos) /* (SDHC_CR) Enable Position */ 160 #define SDHC_CR_DPSEL_Pos _UINT16_(5) /* (SDHC_CR) Data Present Select Position */ 161 #define SDHC_CR_DPSEL_Msk (_UINT16_(0x1) << SDHC_CR_DPSEL_Pos) /* (SDHC_CR) Data Present Select Mask */ 162 #define SDHC_CR_DPSEL(value) (SDHC_CR_DPSEL_Msk & (_UINT16_(value) << SDHC_CR_DPSEL_Pos)) /* Assigment of value for DPSEL in the SDHC_CR register */ 163 #define SDHC_CR_DPSEL_NO_DATA_Val _UINT16_(0x0) /* (SDHC_CR) No Data Present */ 164 #define SDHC_CR_DPSEL_DATA_Val _UINT16_(0x1) /* (SDHC_CR) Data Present */ 165 #define SDHC_CR_DPSEL_NO_DATA (SDHC_CR_DPSEL_NO_DATA_Val << SDHC_CR_DPSEL_Pos) /* (SDHC_CR) No Data Present Position */ 166 #define SDHC_CR_DPSEL_DATA (SDHC_CR_DPSEL_DATA_Val << SDHC_CR_DPSEL_Pos) /* (SDHC_CR) Data Present Position */ 167 #define SDHC_CR_CMDTYP_Pos _UINT16_(6) /* (SDHC_CR) Command Type Position */ 168 #define SDHC_CR_CMDTYP_Msk (_UINT16_(0x3) << SDHC_CR_CMDTYP_Pos) /* (SDHC_CR) Command Type Mask */ 169 #define SDHC_CR_CMDTYP(value) (SDHC_CR_CMDTYP_Msk & (_UINT16_(value) << SDHC_CR_CMDTYP_Pos)) /* Assigment of value for CMDTYP in the SDHC_CR register */ 170 #define SDHC_CR_CMDTYP_NORMAL_Val _UINT16_(0x0) /* (SDHC_CR) Other commands */ 171 #define SDHC_CR_CMDTYP_SUSPEND_Val _UINT16_(0x1) /* (SDHC_CR) CMD52 for writing Bus Suspend in CCCR */ 172 #define SDHC_CR_CMDTYP_RESUME_Val _UINT16_(0x2) /* (SDHC_CR) CMD52 for writing Function Select in CCCR */ 173 #define SDHC_CR_CMDTYP_ABORT_Val _UINT16_(0x3) /* (SDHC_CR) CMD12, CMD52 for writing I/O Abort in CCCR */ 174 #define SDHC_CR_CMDTYP_NORMAL (SDHC_CR_CMDTYP_NORMAL_Val << SDHC_CR_CMDTYP_Pos) /* (SDHC_CR) Other commands Position */ 175 #define SDHC_CR_CMDTYP_SUSPEND (SDHC_CR_CMDTYP_SUSPEND_Val << SDHC_CR_CMDTYP_Pos) /* (SDHC_CR) CMD52 for writing Bus Suspend in CCCR Position */ 176 #define SDHC_CR_CMDTYP_RESUME (SDHC_CR_CMDTYP_RESUME_Val << SDHC_CR_CMDTYP_Pos) /* (SDHC_CR) CMD52 for writing Function Select in CCCR Position */ 177 #define SDHC_CR_CMDTYP_ABORT (SDHC_CR_CMDTYP_ABORT_Val << SDHC_CR_CMDTYP_Pos) /* (SDHC_CR) CMD12, CMD52 for writing I/O Abort in CCCR Position */ 178 #define SDHC_CR_CMDIDX_Pos _UINT16_(8) /* (SDHC_CR) Command Index Position */ 179 #define SDHC_CR_CMDIDX_Msk (_UINT16_(0x3F) << SDHC_CR_CMDIDX_Pos) /* (SDHC_CR) Command Index Mask */ 180 #define SDHC_CR_CMDIDX(value) (SDHC_CR_CMDIDX_Msk & (_UINT16_(value) << SDHC_CR_CMDIDX_Pos)) /* Assigment of value for CMDIDX in the SDHC_CR register */ 181 #define SDHC_CR_Msk _UINT16_(0x3FFB) /* (SDHC_CR) Register Mask */ 182 183 184 /* -------- SDHC_RR : (SDHC Offset: 0x10) ( R/ 32) Response -------- */ 185 #define SDHC_RR_RESETVALUE _UINT32_(0x00) /* (SDHC_RR) Response Reset Value */ 186 187 #define SDHC_RR_CMDRESP_Pos _UINT32_(0) /* (SDHC_RR) Command Response Position */ 188 #define SDHC_RR_CMDRESP_Msk (_UINT32_(0xFFFFFFFF) << SDHC_RR_CMDRESP_Pos) /* (SDHC_RR) Command Response Mask */ 189 #define SDHC_RR_CMDRESP(value) (SDHC_RR_CMDRESP_Msk & (_UINT32_(value) << SDHC_RR_CMDRESP_Pos)) /* Assigment of value for CMDRESP in the SDHC_RR register */ 190 #define SDHC_RR_Msk _UINT32_(0xFFFFFFFF) /* (SDHC_RR) Register Mask */ 191 192 193 /* -------- SDHC_BDPR : (SDHC Offset: 0x20) (R/W 32) Buffer Data Port -------- */ 194 #define SDHC_BDPR_RESETVALUE _UINT32_(0x00) /* (SDHC_BDPR) Buffer Data Port Reset Value */ 195 196 #define SDHC_BDPR_BUFDATA_Pos _UINT32_(0) /* (SDHC_BDPR) Buffer Data Position */ 197 #define SDHC_BDPR_BUFDATA_Msk (_UINT32_(0xFFFFFFFF) << SDHC_BDPR_BUFDATA_Pos) /* (SDHC_BDPR) Buffer Data Mask */ 198 #define SDHC_BDPR_BUFDATA(value) (SDHC_BDPR_BUFDATA_Msk & (_UINT32_(value) << SDHC_BDPR_BUFDATA_Pos)) /* Assigment of value for BUFDATA in the SDHC_BDPR register */ 199 #define SDHC_BDPR_Msk _UINT32_(0xFFFFFFFF) /* (SDHC_BDPR) Register Mask */ 200 201 202 /* -------- SDHC_PSR : (SDHC Offset: 0x24) ( R/ 32) Present State -------- */ 203 #define SDHC_PSR_RESETVALUE _UINT32_(0xF80000) /* (SDHC_PSR) Present State Reset Value */ 204 205 #define SDHC_PSR_CMDINHC_Pos _UINT32_(0) /* (SDHC_PSR) Command Inhibit (CMD) Position */ 206 #define SDHC_PSR_CMDINHC_Msk (_UINT32_(0x1) << SDHC_PSR_CMDINHC_Pos) /* (SDHC_PSR) Command Inhibit (CMD) Mask */ 207 #define SDHC_PSR_CMDINHC(value) (SDHC_PSR_CMDINHC_Msk & (_UINT32_(value) << SDHC_PSR_CMDINHC_Pos)) /* Assigment of value for CMDINHC in the SDHC_PSR register */ 208 #define SDHC_PSR_CMDINHC_CAN_Val _UINT32_(0x0) /* (SDHC_PSR) Can issue command using only CMD line */ 209 #define SDHC_PSR_CMDINHC_CANNOT_Val _UINT32_(0x1) /* (SDHC_PSR) Cannot issue command */ 210 #define SDHC_PSR_CMDINHC_CAN (SDHC_PSR_CMDINHC_CAN_Val << SDHC_PSR_CMDINHC_Pos) /* (SDHC_PSR) Can issue command using only CMD line Position */ 211 #define SDHC_PSR_CMDINHC_CANNOT (SDHC_PSR_CMDINHC_CANNOT_Val << SDHC_PSR_CMDINHC_Pos) /* (SDHC_PSR) Cannot issue command Position */ 212 #define SDHC_PSR_CMDINHD_Pos _UINT32_(1) /* (SDHC_PSR) Command Inhibit (DAT) Position */ 213 #define SDHC_PSR_CMDINHD_Msk (_UINT32_(0x1) << SDHC_PSR_CMDINHD_Pos) /* (SDHC_PSR) Command Inhibit (DAT) Mask */ 214 #define SDHC_PSR_CMDINHD(value) (SDHC_PSR_CMDINHD_Msk & (_UINT32_(value) << SDHC_PSR_CMDINHD_Pos)) /* Assigment of value for CMDINHD in the SDHC_PSR register */ 215 #define SDHC_PSR_CMDINHD_CAN_Val _UINT32_(0x0) /* (SDHC_PSR) Can issue command which uses the DAT line */ 216 #define SDHC_PSR_CMDINHD_CANNOT_Val _UINT32_(0x1) /* (SDHC_PSR) Cannot issue command which uses the DAT line */ 217 #define SDHC_PSR_CMDINHD_CAN (SDHC_PSR_CMDINHD_CAN_Val << SDHC_PSR_CMDINHD_Pos) /* (SDHC_PSR) Can issue command which uses the DAT line Position */ 218 #define SDHC_PSR_CMDINHD_CANNOT (SDHC_PSR_CMDINHD_CANNOT_Val << SDHC_PSR_CMDINHD_Pos) /* (SDHC_PSR) Cannot issue command which uses the DAT line Position */ 219 #define SDHC_PSR_DLACT_Pos _UINT32_(2) /* (SDHC_PSR) DAT Line Active Position */ 220 #define SDHC_PSR_DLACT_Msk (_UINT32_(0x1) << SDHC_PSR_DLACT_Pos) /* (SDHC_PSR) DAT Line Active Mask */ 221 #define SDHC_PSR_DLACT(value) (SDHC_PSR_DLACT_Msk & (_UINT32_(value) << SDHC_PSR_DLACT_Pos)) /* Assigment of value for DLACT in the SDHC_PSR register */ 222 #define SDHC_PSR_DLACT_INACTIVE_Val _UINT32_(0x0) /* (SDHC_PSR) DAT Line Inactive */ 223 #define SDHC_PSR_DLACT_ACTIVE_Val _UINT32_(0x1) /* (SDHC_PSR) DAT Line Active */ 224 #define SDHC_PSR_DLACT_INACTIVE (SDHC_PSR_DLACT_INACTIVE_Val << SDHC_PSR_DLACT_Pos) /* (SDHC_PSR) DAT Line Inactive Position */ 225 #define SDHC_PSR_DLACT_ACTIVE (SDHC_PSR_DLACT_ACTIVE_Val << SDHC_PSR_DLACT_Pos) /* (SDHC_PSR) DAT Line Active Position */ 226 #define SDHC_PSR_RTREQ_Pos _UINT32_(3) /* (SDHC_PSR) Re-Tuning Request Position */ 227 #define SDHC_PSR_RTREQ_Msk (_UINT32_(0x1) << SDHC_PSR_RTREQ_Pos) /* (SDHC_PSR) Re-Tuning Request Mask */ 228 #define SDHC_PSR_RTREQ(value) (SDHC_PSR_RTREQ_Msk & (_UINT32_(value) << SDHC_PSR_RTREQ_Pos)) /* Assigment of value for RTREQ in the SDHC_PSR register */ 229 #define SDHC_PSR_RTREQ_OK_Val _UINT32_(0x0) /* (SDHC_PSR) Fixed or well-tuned sampling clock */ 230 #define SDHC_PSR_RTREQ_REQUIRED_Val _UINT32_(0x1) /* (SDHC_PSR) Sampling clock needs re-tuning */ 231 #define SDHC_PSR_RTREQ_OK (SDHC_PSR_RTREQ_OK_Val << SDHC_PSR_RTREQ_Pos) /* (SDHC_PSR) Fixed or well-tuned sampling clock Position */ 232 #define SDHC_PSR_RTREQ_REQUIRED (SDHC_PSR_RTREQ_REQUIRED_Val << SDHC_PSR_RTREQ_Pos) /* (SDHC_PSR) Sampling clock needs re-tuning Position */ 233 #define SDHC_PSR_WTACT_Pos _UINT32_(8) /* (SDHC_PSR) Write Transfer Active Position */ 234 #define SDHC_PSR_WTACT_Msk (_UINT32_(0x1) << SDHC_PSR_WTACT_Pos) /* (SDHC_PSR) Write Transfer Active Mask */ 235 #define SDHC_PSR_WTACT(value) (SDHC_PSR_WTACT_Msk & (_UINT32_(value) << SDHC_PSR_WTACT_Pos)) /* Assigment of value for WTACT in the SDHC_PSR register */ 236 #define SDHC_PSR_WTACT_NO_Val _UINT32_(0x0) /* (SDHC_PSR) No valid data */ 237 #define SDHC_PSR_WTACT_YES_Val _UINT32_(0x1) /* (SDHC_PSR) Transferring data */ 238 #define SDHC_PSR_WTACT_NO (SDHC_PSR_WTACT_NO_Val << SDHC_PSR_WTACT_Pos) /* (SDHC_PSR) No valid data Position */ 239 #define SDHC_PSR_WTACT_YES (SDHC_PSR_WTACT_YES_Val << SDHC_PSR_WTACT_Pos) /* (SDHC_PSR) Transferring data Position */ 240 #define SDHC_PSR_RTACT_Pos _UINT32_(9) /* (SDHC_PSR) Read Transfer Active Position */ 241 #define SDHC_PSR_RTACT_Msk (_UINT32_(0x1) << SDHC_PSR_RTACT_Pos) /* (SDHC_PSR) Read Transfer Active Mask */ 242 #define SDHC_PSR_RTACT(value) (SDHC_PSR_RTACT_Msk & (_UINT32_(value) << SDHC_PSR_RTACT_Pos)) /* Assigment of value for RTACT in the SDHC_PSR register */ 243 #define SDHC_PSR_RTACT_NO_Val _UINT32_(0x0) /* (SDHC_PSR) No valid data */ 244 #define SDHC_PSR_RTACT_YES_Val _UINT32_(0x1) /* (SDHC_PSR) Transferring data */ 245 #define SDHC_PSR_RTACT_NO (SDHC_PSR_RTACT_NO_Val << SDHC_PSR_RTACT_Pos) /* (SDHC_PSR) No valid data Position */ 246 #define SDHC_PSR_RTACT_YES (SDHC_PSR_RTACT_YES_Val << SDHC_PSR_RTACT_Pos) /* (SDHC_PSR) Transferring data Position */ 247 #define SDHC_PSR_BUFWREN_Pos _UINT32_(10) /* (SDHC_PSR) Buffer Write Enable Position */ 248 #define SDHC_PSR_BUFWREN_Msk (_UINT32_(0x1) << SDHC_PSR_BUFWREN_Pos) /* (SDHC_PSR) Buffer Write Enable Mask */ 249 #define SDHC_PSR_BUFWREN(value) (SDHC_PSR_BUFWREN_Msk & (_UINT32_(value) << SDHC_PSR_BUFWREN_Pos)) /* Assigment of value for BUFWREN in the SDHC_PSR register */ 250 #define SDHC_PSR_BUFWREN_DISABLE_Val _UINT32_(0x0) /* (SDHC_PSR) Write disable */ 251 #define SDHC_PSR_BUFWREN_ENABLE_Val _UINT32_(0x1) /* (SDHC_PSR) Write enable */ 252 #define SDHC_PSR_BUFWREN_DISABLE (SDHC_PSR_BUFWREN_DISABLE_Val << SDHC_PSR_BUFWREN_Pos) /* (SDHC_PSR) Write disable Position */ 253 #define SDHC_PSR_BUFWREN_ENABLE (SDHC_PSR_BUFWREN_ENABLE_Val << SDHC_PSR_BUFWREN_Pos) /* (SDHC_PSR) Write enable Position */ 254 #define SDHC_PSR_BUFRDEN_Pos _UINT32_(11) /* (SDHC_PSR) Buffer Read Enable Position */ 255 #define SDHC_PSR_BUFRDEN_Msk (_UINT32_(0x1) << SDHC_PSR_BUFRDEN_Pos) /* (SDHC_PSR) Buffer Read Enable Mask */ 256 #define SDHC_PSR_BUFRDEN(value) (SDHC_PSR_BUFRDEN_Msk & (_UINT32_(value) << SDHC_PSR_BUFRDEN_Pos)) /* Assigment of value for BUFRDEN in the SDHC_PSR register */ 257 #define SDHC_PSR_BUFRDEN_DISABLE_Val _UINT32_(0x0) /* (SDHC_PSR) Read disable */ 258 #define SDHC_PSR_BUFRDEN_ENABLE_Val _UINT32_(0x1) /* (SDHC_PSR) Read enable */ 259 #define SDHC_PSR_BUFRDEN_DISABLE (SDHC_PSR_BUFRDEN_DISABLE_Val << SDHC_PSR_BUFRDEN_Pos) /* (SDHC_PSR) Read disable Position */ 260 #define SDHC_PSR_BUFRDEN_ENABLE (SDHC_PSR_BUFRDEN_ENABLE_Val << SDHC_PSR_BUFRDEN_Pos) /* (SDHC_PSR) Read enable Position */ 261 #define SDHC_PSR_CARDINS_Pos _UINT32_(16) /* (SDHC_PSR) Card Inserted Position */ 262 #define SDHC_PSR_CARDINS_Msk (_UINT32_(0x1) << SDHC_PSR_CARDINS_Pos) /* (SDHC_PSR) Card Inserted Mask */ 263 #define SDHC_PSR_CARDINS(value) (SDHC_PSR_CARDINS_Msk & (_UINT32_(value) << SDHC_PSR_CARDINS_Pos)) /* Assigment of value for CARDINS in the SDHC_PSR register */ 264 #define SDHC_PSR_CARDINS_NO_Val _UINT32_(0x0) /* (SDHC_PSR) Reset or Debouncing or No Card */ 265 #define SDHC_PSR_CARDINS_YES_Val _UINT32_(0x1) /* (SDHC_PSR) Card inserted */ 266 #define SDHC_PSR_CARDINS_NO (SDHC_PSR_CARDINS_NO_Val << SDHC_PSR_CARDINS_Pos) /* (SDHC_PSR) Reset or Debouncing or No Card Position */ 267 #define SDHC_PSR_CARDINS_YES (SDHC_PSR_CARDINS_YES_Val << SDHC_PSR_CARDINS_Pos) /* (SDHC_PSR) Card inserted Position */ 268 #define SDHC_PSR_CARDSS_Pos _UINT32_(17) /* (SDHC_PSR) Card State Stable Position */ 269 #define SDHC_PSR_CARDSS_Msk (_UINT32_(0x1) << SDHC_PSR_CARDSS_Pos) /* (SDHC_PSR) Card State Stable Mask */ 270 #define SDHC_PSR_CARDSS(value) (SDHC_PSR_CARDSS_Msk & (_UINT32_(value) << SDHC_PSR_CARDSS_Pos)) /* Assigment of value for CARDSS in the SDHC_PSR register */ 271 #define SDHC_PSR_CARDSS_NO_Val _UINT32_(0x0) /* (SDHC_PSR) Reset or Debouncing */ 272 #define SDHC_PSR_CARDSS_YES_Val _UINT32_(0x1) /* (SDHC_PSR) No Card or Insered */ 273 #define SDHC_PSR_CARDSS_NO (SDHC_PSR_CARDSS_NO_Val << SDHC_PSR_CARDSS_Pos) /* (SDHC_PSR) Reset or Debouncing Position */ 274 #define SDHC_PSR_CARDSS_YES (SDHC_PSR_CARDSS_YES_Val << SDHC_PSR_CARDSS_Pos) /* (SDHC_PSR) No Card or Insered Position */ 275 #define SDHC_PSR_CARDDPL_Pos _UINT32_(18) /* (SDHC_PSR) Card Detect Pin Level Position */ 276 #define SDHC_PSR_CARDDPL_Msk (_UINT32_(0x1) << SDHC_PSR_CARDDPL_Pos) /* (SDHC_PSR) Card Detect Pin Level Mask */ 277 #define SDHC_PSR_CARDDPL(value) (SDHC_PSR_CARDDPL_Msk & (_UINT32_(value) << SDHC_PSR_CARDDPL_Pos)) /* Assigment of value for CARDDPL in the SDHC_PSR register */ 278 #define SDHC_PSR_CARDDPL_NO_Val _UINT32_(0x0) /* (SDHC_PSR) No card present (SDCD#=1) */ 279 #define SDHC_PSR_CARDDPL_YES_Val _UINT32_(0x1) /* (SDHC_PSR) Card present (SDCD#=0) */ 280 #define SDHC_PSR_CARDDPL_NO (SDHC_PSR_CARDDPL_NO_Val << SDHC_PSR_CARDDPL_Pos) /* (SDHC_PSR) No card present (SDCD#=1) Position */ 281 #define SDHC_PSR_CARDDPL_YES (SDHC_PSR_CARDDPL_YES_Val << SDHC_PSR_CARDDPL_Pos) /* (SDHC_PSR) Card present (SDCD#=0) Position */ 282 #define SDHC_PSR_WRPPL_Pos _UINT32_(19) /* (SDHC_PSR) Write Protect Pin Level Position */ 283 #define SDHC_PSR_WRPPL_Msk (_UINT32_(0x1) << SDHC_PSR_WRPPL_Pos) /* (SDHC_PSR) Write Protect Pin Level Mask */ 284 #define SDHC_PSR_WRPPL(value) (SDHC_PSR_WRPPL_Msk & (_UINT32_(value) << SDHC_PSR_WRPPL_Pos)) /* Assigment of value for WRPPL in the SDHC_PSR register */ 285 #define SDHC_PSR_WRPPL_PROTECTED_Val _UINT32_(0x0) /* (SDHC_PSR) Write protected (SDWP#=0) */ 286 #define SDHC_PSR_WRPPL_ENABLED_Val _UINT32_(0x1) /* (SDHC_PSR) Write enabled (SDWP#=1) */ 287 #define SDHC_PSR_WRPPL_PROTECTED (SDHC_PSR_WRPPL_PROTECTED_Val << SDHC_PSR_WRPPL_Pos) /* (SDHC_PSR) Write protected (SDWP#=0) Position */ 288 #define SDHC_PSR_WRPPL_ENABLED (SDHC_PSR_WRPPL_ENABLED_Val << SDHC_PSR_WRPPL_Pos) /* (SDHC_PSR) Write enabled (SDWP#=1) Position */ 289 #define SDHC_PSR_DATLL_Pos _UINT32_(20) /* (SDHC_PSR) DAT[3:0] Line Level Position */ 290 #define SDHC_PSR_DATLL_Msk (_UINT32_(0xF) << SDHC_PSR_DATLL_Pos) /* (SDHC_PSR) DAT[3:0] Line Level Mask */ 291 #define SDHC_PSR_DATLL(value) (SDHC_PSR_DATLL_Msk & (_UINT32_(value) << SDHC_PSR_DATLL_Pos)) /* Assigment of value for DATLL in the SDHC_PSR register */ 292 #define SDHC_PSR_CMDLL_Pos _UINT32_(24) /* (SDHC_PSR) CMD Line Level Position */ 293 #define SDHC_PSR_CMDLL_Msk (_UINT32_(0x1) << SDHC_PSR_CMDLL_Pos) /* (SDHC_PSR) CMD Line Level Mask */ 294 #define SDHC_PSR_CMDLL(value) (SDHC_PSR_CMDLL_Msk & (_UINT32_(value) << SDHC_PSR_CMDLL_Pos)) /* Assigment of value for CMDLL in the SDHC_PSR register */ 295 #define SDHC_PSR_Msk _UINT32_(0x01FF0F0F) /* (SDHC_PSR) Register Mask */ 296 297 298 /* -------- SDHC_HC1R : (SDHC Offset: 0x28) (R/W 8) Host Control 1 -------- */ 299 #define SDHC_HC1R_RESETVALUE _UINT8_(0xE00) /* (SDHC_HC1R) Host Control 1 Reset Value */ 300 301 #define SDHC_HC1R_LEDCTRL_Pos _UINT8_(0) /* (SDHC_HC1R) LED Control Position */ 302 #define SDHC_HC1R_LEDCTRL_Msk (_UINT8_(0x1) << SDHC_HC1R_LEDCTRL_Pos) /* (SDHC_HC1R) LED Control Mask */ 303 #define SDHC_HC1R_LEDCTRL(value) (SDHC_HC1R_LEDCTRL_Msk & (_UINT8_(value) << SDHC_HC1R_LEDCTRL_Pos)) /* Assigment of value for LEDCTRL in the SDHC_HC1R register */ 304 #define SDHC_HC1R_LEDCTRL_OFF_Val _UINT8_(0x0) /* (SDHC_HC1R) LED off */ 305 #define SDHC_HC1R_LEDCTRL_ON_Val _UINT8_(0x1) /* (SDHC_HC1R) LED on */ 306 #define SDHC_HC1R_LEDCTRL_OFF (SDHC_HC1R_LEDCTRL_OFF_Val << SDHC_HC1R_LEDCTRL_Pos) /* (SDHC_HC1R) LED off Position */ 307 #define SDHC_HC1R_LEDCTRL_ON (SDHC_HC1R_LEDCTRL_ON_Val << SDHC_HC1R_LEDCTRL_Pos) /* (SDHC_HC1R) LED on Position */ 308 #define SDHC_HC1R_DW_Pos _UINT8_(1) /* (SDHC_HC1R) Data Width Position */ 309 #define SDHC_HC1R_DW_Msk (_UINT8_(0x1) << SDHC_HC1R_DW_Pos) /* (SDHC_HC1R) Data Width Mask */ 310 #define SDHC_HC1R_DW(value) (SDHC_HC1R_DW_Msk & (_UINT8_(value) << SDHC_HC1R_DW_Pos)) /* Assigment of value for DW in the SDHC_HC1R register */ 311 #define SDHC_HC1R_DW_1BIT_Val _UINT8_(0x0) /* (SDHC_HC1R) 1-bit mode */ 312 #define SDHC_HC1R_DW_4BIT_Val _UINT8_(0x1) /* (SDHC_HC1R) 4-bit mode */ 313 #define SDHC_HC1R_DW_1BIT (SDHC_HC1R_DW_1BIT_Val << SDHC_HC1R_DW_Pos) /* (SDHC_HC1R) 1-bit mode Position */ 314 #define SDHC_HC1R_DW_4BIT (SDHC_HC1R_DW_4BIT_Val << SDHC_HC1R_DW_Pos) /* (SDHC_HC1R) 4-bit mode Position */ 315 #define SDHC_HC1R_HSEN_Pos _UINT8_(2) /* (SDHC_HC1R) High Speed Enable Position */ 316 #define SDHC_HC1R_HSEN_Msk (_UINT8_(0x1) << SDHC_HC1R_HSEN_Pos) /* (SDHC_HC1R) High Speed Enable Mask */ 317 #define SDHC_HC1R_HSEN(value) (SDHC_HC1R_HSEN_Msk & (_UINT8_(value) << SDHC_HC1R_HSEN_Pos)) /* Assigment of value for HSEN in the SDHC_HC1R register */ 318 #define SDHC_HC1R_HSEN_NORMAL_Val _UINT8_(0x0) /* (SDHC_HC1R) Normal Speed mode */ 319 #define SDHC_HC1R_HSEN_HIGH_Val _UINT8_(0x1) /* (SDHC_HC1R) High Speed mode */ 320 #define SDHC_HC1R_HSEN_NORMAL (SDHC_HC1R_HSEN_NORMAL_Val << SDHC_HC1R_HSEN_Pos) /* (SDHC_HC1R) Normal Speed mode Position */ 321 #define SDHC_HC1R_HSEN_HIGH (SDHC_HC1R_HSEN_HIGH_Val << SDHC_HC1R_HSEN_Pos) /* (SDHC_HC1R) High Speed mode Position */ 322 #define SDHC_HC1R_DMASEL_Pos _UINT8_(3) /* (SDHC_HC1R) DMA Select Position */ 323 #define SDHC_HC1R_DMASEL_Msk (_UINT8_(0x3) << SDHC_HC1R_DMASEL_Pos) /* (SDHC_HC1R) DMA Select Mask */ 324 #define SDHC_HC1R_DMASEL(value) (SDHC_HC1R_DMASEL_Msk & (_UINT8_(value) << SDHC_HC1R_DMASEL_Pos)) /* Assigment of value for DMASEL in the SDHC_HC1R register */ 325 #define SDHC_HC1R_DMASEL_SDMA_Val _UINT8_(0x0) /* (SDHC_HC1R) SDMA is selected */ 326 #define SDHC_HC1R_DMASEL_32BIT_Val _UINT8_(0x2) /* (SDHC_HC1R) 32-bit Address ADMA2 is selected */ 327 #define SDHC_HC1R_DMASEL_SDMA (SDHC_HC1R_DMASEL_SDMA_Val << SDHC_HC1R_DMASEL_Pos) /* (SDHC_HC1R) SDMA is selected Position */ 328 #define SDHC_HC1R_DMASEL_32BIT (SDHC_HC1R_DMASEL_32BIT_Val << SDHC_HC1R_DMASEL_Pos) /* (SDHC_HC1R) 32-bit Address ADMA2 is selected Position */ 329 #define SDHC_HC1R_CARDDTL_Pos _UINT8_(6) /* (SDHC_HC1R) Card Detect Test Level Position */ 330 #define SDHC_HC1R_CARDDTL_Msk (_UINT8_(0x1) << SDHC_HC1R_CARDDTL_Pos) /* (SDHC_HC1R) Card Detect Test Level Mask */ 331 #define SDHC_HC1R_CARDDTL(value) (SDHC_HC1R_CARDDTL_Msk & (_UINT8_(value) << SDHC_HC1R_CARDDTL_Pos)) /* Assigment of value for CARDDTL in the SDHC_HC1R register */ 332 #define SDHC_HC1R_CARDDTL_NO_Val _UINT8_(0x0) /* (SDHC_HC1R) No Card */ 333 #define SDHC_HC1R_CARDDTL_YES_Val _UINT8_(0x1) /* (SDHC_HC1R) Card Inserted */ 334 #define SDHC_HC1R_CARDDTL_NO (SDHC_HC1R_CARDDTL_NO_Val << SDHC_HC1R_CARDDTL_Pos) /* (SDHC_HC1R) No Card Position */ 335 #define SDHC_HC1R_CARDDTL_YES (SDHC_HC1R_CARDDTL_YES_Val << SDHC_HC1R_CARDDTL_Pos) /* (SDHC_HC1R) Card Inserted Position */ 336 #define SDHC_HC1R_CARDDSEL_Pos _UINT8_(7) /* (SDHC_HC1R) Card Detect Signal Selection Position */ 337 #define SDHC_HC1R_CARDDSEL_Msk (_UINT8_(0x1) << SDHC_HC1R_CARDDSEL_Pos) /* (SDHC_HC1R) Card Detect Signal Selection Mask */ 338 #define SDHC_HC1R_CARDDSEL(value) (SDHC_HC1R_CARDDSEL_Msk & (_UINT8_(value) << SDHC_HC1R_CARDDSEL_Pos)) /* Assigment of value for CARDDSEL in the SDHC_HC1R register */ 339 #define SDHC_HC1R_CARDDSEL_NORMAL_Val _UINT8_(0x0) /* (SDHC_HC1R) SDCD# is selected (for normal use) */ 340 #define SDHC_HC1R_CARDDSEL_TEST_Val _UINT8_(0x1) /* (SDHC_HC1R) The Card Select Test Level is selected (for test purpose) */ 341 #define SDHC_HC1R_CARDDSEL_NORMAL (SDHC_HC1R_CARDDSEL_NORMAL_Val << SDHC_HC1R_CARDDSEL_Pos) /* (SDHC_HC1R) SDCD# is selected (for normal use) Position */ 342 #define SDHC_HC1R_CARDDSEL_TEST (SDHC_HC1R_CARDDSEL_TEST_Val << SDHC_HC1R_CARDDSEL_Pos) /* (SDHC_HC1R) The Card Select Test Level is selected (for test purpose) Position */ 343 #define SDHC_HC1R_Msk _UINT8_(0xDF) /* (SDHC_HC1R) Register Mask */ 344 345 /* EMMC mode */ 346 #define SDHC_HC1R_EMMC_Msk _UINT8_(0x00) /* (SDHC_HC1R_EMMC) Register Mask */ 347 348 349 /* -------- SDHC_PCR : (SDHC Offset: 0x29) (R/W 8) Power Control -------- */ 350 #define SDHC_PCR_RESETVALUE _UINT8_(0x0E) /* (SDHC_PCR) Power Control Reset Value */ 351 352 #define SDHC_PCR_SDBPWR_Pos _UINT8_(0) /* (SDHC_PCR) SD Bus Power Position */ 353 #define SDHC_PCR_SDBPWR_Msk (_UINT8_(0x1) << SDHC_PCR_SDBPWR_Pos) /* (SDHC_PCR) SD Bus Power Mask */ 354 #define SDHC_PCR_SDBPWR(value) (SDHC_PCR_SDBPWR_Msk & (_UINT8_(value) << SDHC_PCR_SDBPWR_Pos)) /* Assigment of value for SDBPWR in the SDHC_PCR register */ 355 #define SDHC_PCR_SDBPWR_OFF_Val _UINT8_(0x0) /* (SDHC_PCR) Power off */ 356 #define SDHC_PCR_SDBPWR_ON_Val _UINT8_(0x1) /* (SDHC_PCR) Power on */ 357 #define SDHC_PCR_SDBPWR_OFF (SDHC_PCR_SDBPWR_OFF_Val << SDHC_PCR_SDBPWR_Pos) /* (SDHC_PCR) Power off Position */ 358 #define SDHC_PCR_SDBPWR_ON (SDHC_PCR_SDBPWR_ON_Val << SDHC_PCR_SDBPWR_Pos) /* (SDHC_PCR) Power on Position */ 359 #define SDHC_PCR_SDBVSEL_Pos _UINT8_(1) /* (SDHC_PCR) SD Bus Voltage Select Position */ 360 #define SDHC_PCR_SDBVSEL_Msk (_UINT8_(0x7) << SDHC_PCR_SDBVSEL_Pos) /* (SDHC_PCR) SD Bus Voltage Select Mask */ 361 #define SDHC_PCR_SDBVSEL(value) (SDHC_PCR_SDBVSEL_Msk & (_UINT8_(value) << SDHC_PCR_SDBVSEL_Pos)) /* Assigment of value for SDBVSEL in the SDHC_PCR register */ 362 #define SDHC_PCR_SDBVSEL_1V8_Val _UINT8_(0x5) /* (SDHC_PCR) 1.8V (Typ.) */ 363 #define SDHC_PCR_SDBVSEL_3V0_Val _UINT8_(0x6) /* (SDHC_PCR) 3.0V (Typ.) */ 364 #define SDHC_PCR_SDBVSEL_3V3_Val _UINT8_(0x7) /* (SDHC_PCR) 3.3V (Typ.) */ 365 #define SDHC_PCR_SDBVSEL_1V8 (SDHC_PCR_SDBVSEL_1V8_Val << SDHC_PCR_SDBVSEL_Pos) /* (SDHC_PCR) 1.8V (Typ.) Position */ 366 #define SDHC_PCR_SDBVSEL_3V0 (SDHC_PCR_SDBVSEL_3V0_Val << SDHC_PCR_SDBVSEL_Pos) /* (SDHC_PCR) 3.0V (Typ.) Position */ 367 #define SDHC_PCR_SDBVSEL_3V3 (SDHC_PCR_SDBVSEL_3V3_Val << SDHC_PCR_SDBVSEL_Pos) /* (SDHC_PCR) 3.3V (Typ.) Position */ 368 #define SDHC_PCR_Msk _UINT8_(0x0F) /* (SDHC_PCR) Register Mask */ 369 370 371 /* -------- SDHC_BGCR : (SDHC Offset: 0x2A) (R/W 8) Block Gap Control -------- */ 372 #define SDHC_BGCR_RESETVALUE _UINT8_(0x00) /* (SDHC_BGCR) Block Gap Control Reset Value */ 373 374 #define SDHC_BGCR_STPBGR_Pos _UINT8_(0) /* (SDHC_BGCR) Stop at Block Gap Request Position */ 375 #define SDHC_BGCR_STPBGR_Msk (_UINT8_(0x1) << SDHC_BGCR_STPBGR_Pos) /* (SDHC_BGCR) Stop at Block Gap Request Mask */ 376 #define SDHC_BGCR_STPBGR(value) (SDHC_BGCR_STPBGR_Msk & (_UINT8_(value) << SDHC_BGCR_STPBGR_Pos)) /* Assigment of value for STPBGR in the SDHC_BGCR register */ 377 #define SDHC_BGCR_STPBGR_TRANSFER_Val _UINT8_(0x0) /* (SDHC_BGCR) Transfer */ 378 #define SDHC_BGCR_STPBGR_STOP_Val _UINT8_(0x1) /* (SDHC_BGCR) Stop */ 379 #define SDHC_BGCR_STPBGR_TRANSFER (SDHC_BGCR_STPBGR_TRANSFER_Val << SDHC_BGCR_STPBGR_Pos) /* (SDHC_BGCR) Transfer Position */ 380 #define SDHC_BGCR_STPBGR_STOP (SDHC_BGCR_STPBGR_STOP_Val << SDHC_BGCR_STPBGR_Pos) /* (SDHC_BGCR) Stop Position */ 381 #define SDHC_BGCR_CONTR_Pos _UINT8_(1) /* (SDHC_BGCR) Continue Request Position */ 382 #define SDHC_BGCR_CONTR_Msk (_UINT8_(0x1) << SDHC_BGCR_CONTR_Pos) /* (SDHC_BGCR) Continue Request Mask */ 383 #define SDHC_BGCR_CONTR(value) (SDHC_BGCR_CONTR_Msk & (_UINT8_(value) << SDHC_BGCR_CONTR_Pos)) /* Assigment of value for CONTR in the SDHC_BGCR register */ 384 #define SDHC_BGCR_CONTR_GO_ON_Val _UINT8_(0x0) /* (SDHC_BGCR) Not affected */ 385 #define SDHC_BGCR_CONTR_RESTART_Val _UINT8_(0x1) /* (SDHC_BGCR) Restart */ 386 #define SDHC_BGCR_CONTR_GO_ON (SDHC_BGCR_CONTR_GO_ON_Val << SDHC_BGCR_CONTR_Pos) /* (SDHC_BGCR) Not affected Position */ 387 #define SDHC_BGCR_CONTR_RESTART (SDHC_BGCR_CONTR_RESTART_Val << SDHC_BGCR_CONTR_Pos) /* (SDHC_BGCR) Restart Position */ 388 #define SDHC_BGCR_RWCTRL_Pos _UINT8_(2) /* (SDHC_BGCR) Read Wait Control Position */ 389 #define SDHC_BGCR_RWCTRL_Msk (_UINT8_(0x1) << SDHC_BGCR_RWCTRL_Pos) /* (SDHC_BGCR) Read Wait Control Mask */ 390 #define SDHC_BGCR_RWCTRL(value) (SDHC_BGCR_RWCTRL_Msk & (_UINT8_(value) << SDHC_BGCR_RWCTRL_Pos)) /* Assigment of value for RWCTRL in the SDHC_BGCR register */ 391 #define SDHC_BGCR_RWCTRL_DISABLE_Val _UINT8_(0x0) /* (SDHC_BGCR) Disable Read Wait Control */ 392 #define SDHC_BGCR_RWCTRL_ENABLE_Val _UINT8_(0x1) /* (SDHC_BGCR) Enable Read Wait Control */ 393 #define SDHC_BGCR_RWCTRL_DISABLE (SDHC_BGCR_RWCTRL_DISABLE_Val << SDHC_BGCR_RWCTRL_Pos) /* (SDHC_BGCR) Disable Read Wait Control Position */ 394 #define SDHC_BGCR_RWCTRL_ENABLE (SDHC_BGCR_RWCTRL_ENABLE_Val << SDHC_BGCR_RWCTRL_Pos) /* (SDHC_BGCR) Enable Read Wait Control Position */ 395 #define SDHC_BGCR_INTBG_Pos _UINT8_(3) /* (SDHC_BGCR) Interrupt at Block Gap Position */ 396 #define SDHC_BGCR_INTBG_Msk (_UINT8_(0x1) << SDHC_BGCR_INTBG_Pos) /* (SDHC_BGCR) Interrupt at Block Gap Mask */ 397 #define SDHC_BGCR_INTBG(value) (SDHC_BGCR_INTBG_Msk & (_UINT8_(value) << SDHC_BGCR_INTBG_Pos)) /* Assigment of value for INTBG in the SDHC_BGCR register */ 398 #define SDHC_BGCR_INTBG_DISABLED_Val _UINT8_(0x0) /* (SDHC_BGCR) Disabled */ 399 #define SDHC_BGCR_INTBG_ENABLED_Val _UINT8_(0x1) /* (SDHC_BGCR) Enabled */ 400 #define SDHC_BGCR_INTBG_DISABLED (SDHC_BGCR_INTBG_DISABLED_Val << SDHC_BGCR_INTBG_Pos) /* (SDHC_BGCR) Disabled Position */ 401 #define SDHC_BGCR_INTBG_ENABLED (SDHC_BGCR_INTBG_ENABLED_Val << SDHC_BGCR_INTBG_Pos) /* (SDHC_BGCR) Enabled Position */ 402 #define SDHC_BGCR_Msk _UINT8_(0x0F) /* (SDHC_BGCR) Register Mask */ 403 404 /* EMMC mode */ 405 #define SDHC_BGCR_EMMC_Msk _UINT8_(0x00) /* (SDHC_BGCR_EMMC) Register Mask */ 406 407 408 /* -------- SDHC_WCR : (SDHC Offset: 0x2B) (R/W 8) Wakeup Control -------- */ 409 #define SDHC_WCR_RESETVALUE _UINT8_(0x00) /* (SDHC_WCR) Wakeup Control Reset Value */ 410 411 #define SDHC_WCR_WKENCINT_Pos _UINT8_(0) /* (SDHC_WCR) Wakeup Event Enable on Card Interrupt Position */ 412 #define SDHC_WCR_WKENCINT_Msk (_UINT8_(0x1) << SDHC_WCR_WKENCINT_Pos) /* (SDHC_WCR) Wakeup Event Enable on Card Interrupt Mask */ 413 #define SDHC_WCR_WKENCINT(value) (SDHC_WCR_WKENCINT_Msk & (_UINT8_(value) << SDHC_WCR_WKENCINT_Pos)) /* Assigment of value for WKENCINT in the SDHC_WCR register */ 414 #define SDHC_WCR_WKENCINT_DISABLE_Val _UINT8_(0x0) /* (SDHC_WCR) Disable */ 415 #define SDHC_WCR_WKENCINT_ENABLE_Val _UINT8_(0x1) /* (SDHC_WCR) Enable */ 416 #define SDHC_WCR_WKENCINT_DISABLE (SDHC_WCR_WKENCINT_DISABLE_Val << SDHC_WCR_WKENCINT_Pos) /* (SDHC_WCR) Disable Position */ 417 #define SDHC_WCR_WKENCINT_ENABLE (SDHC_WCR_WKENCINT_ENABLE_Val << SDHC_WCR_WKENCINT_Pos) /* (SDHC_WCR) Enable Position */ 418 #define SDHC_WCR_WKENCINS_Pos _UINT8_(1) /* (SDHC_WCR) Wakeup Event Enable on Card Insertion Position */ 419 #define SDHC_WCR_WKENCINS_Msk (_UINT8_(0x1) << SDHC_WCR_WKENCINS_Pos) /* (SDHC_WCR) Wakeup Event Enable on Card Insertion Mask */ 420 #define SDHC_WCR_WKENCINS(value) (SDHC_WCR_WKENCINS_Msk & (_UINT8_(value) << SDHC_WCR_WKENCINS_Pos)) /* Assigment of value for WKENCINS in the SDHC_WCR register */ 421 #define SDHC_WCR_WKENCINS_DISABLE_Val _UINT8_(0x0) /* (SDHC_WCR) Disable */ 422 #define SDHC_WCR_WKENCINS_ENABLE_Val _UINT8_(0x1) /* (SDHC_WCR) Enable */ 423 #define SDHC_WCR_WKENCINS_DISABLE (SDHC_WCR_WKENCINS_DISABLE_Val << SDHC_WCR_WKENCINS_Pos) /* (SDHC_WCR) Disable Position */ 424 #define SDHC_WCR_WKENCINS_ENABLE (SDHC_WCR_WKENCINS_ENABLE_Val << SDHC_WCR_WKENCINS_Pos) /* (SDHC_WCR) Enable Position */ 425 #define SDHC_WCR_WKENCREM_Pos _UINT8_(2) /* (SDHC_WCR) Wakeup Event Enable on Card Removal Position */ 426 #define SDHC_WCR_WKENCREM_Msk (_UINT8_(0x1) << SDHC_WCR_WKENCREM_Pos) /* (SDHC_WCR) Wakeup Event Enable on Card Removal Mask */ 427 #define SDHC_WCR_WKENCREM(value) (SDHC_WCR_WKENCREM_Msk & (_UINT8_(value) << SDHC_WCR_WKENCREM_Pos)) /* Assigment of value for WKENCREM in the SDHC_WCR register */ 428 #define SDHC_WCR_WKENCREM_DISABLE_Val _UINT8_(0x0) /* (SDHC_WCR) Disable */ 429 #define SDHC_WCR_WKENCREM_ENABLE_Val _UINT8_(0x1) /* (SDHC_WCR) Enable */ 430 #define SDHC_WCR_WKENCREM_DISABLE (SDHC_WCR_WKENCREM_DISABLE_Val << SDHC_WCR_WKENCREM_Pos) /* (SDHC_WCR) Disable Position */ 431 #define SDHC_WCR_WKENCREM_ENABLE (SDHC_WCR_WKENCREM_ENABLE_Val << SDHC_WCR_WKENCREM_Pos) /* (SDHC_WCR) Enable Position */ 432 #define SDHC_WCR_Msk _UINT8_(0x07) /* (SDHC_WCR) Register Mask */ 433 434 435 /* -------- SDHC_CCR : (SDHC Offset: 0x2C) (R/W 16) Clock Control -------- */ 436 #define SDHC_CCR_RESETVALUE _UINT16_(0x00) /* (SDHC_CCR) Clock Control Reset Value */ 437 438 #define SDHC_CCR_INTCLKEN_Pos _UINT16_(0) /* (SDHC_CCR) Internal Clock Enable Position */ 439 #define SDHC_CCR_INTCLKEN_Msk (_UINT16_(0x1) << SDHC_CCR_INTCLKEN_Pos) /* (SDHC_CCR) Internal Clock Enable Mask */ 440 #define SDHC_CCR_INTCLKEN(value) (SDHC_CCR_INTCLKEN_Msk & (_UINT16_(value) << SDHC_CCR_INTCLKEN_Pos)) /* Assigment of value for INTCLKEN in the SDHC_CCR register */ 441 #define SDHC_CCR_INTCLKEN_OFF_Val _UINT16_(0x0) /* (SDHC_CCR) Stop */ 442 #define SDHC_CCR_INTCLKEN_ON_Val _UINT16_(0x1) /* (SDHC_CCR) Oscillate */ 443 #define SDHC_CCR_INTCLKEN_OFF (SDHC_CCR_INTCLKEN_OFF_Val << SDHC_CCR_INTCLKEN_Pos) /* (SDHC_CCR) Stop Position */ 444 #define SDHC_CCR_INTCLKEN_ON (SDHC_CCR_INTCLKEN_ON_Val << SDHC_CCR_INTCLKEN_Pos) /* (SDHC_CCR) Oscillate Position */ 445 #define SDHC_CCR_INTCLKS_Pos _UINT16_(1) /* (SDHC_CCR) Internal Clock Stable Position */ 446 #define SDHC_CCR_INTCLKS_Msk (_UINT16_(0x1) << SDHC_CCR_INTCLKS_Pos) /* (SDHC_CCR) Internal Clock Stable Mask */ 447 #define SDHC_CCR_INTCLKS(value) (SDHC_CCR_INTCLKS_Msk & (_UINT16_(value) << SDHC_CCR_INTCLKS_Pos)) /* Assigment of value for INTCLKS in the SDHC_CCR register */ 448 #define SDHC_CCR_INTCLKS_NOT_READY_Val _UINT16_(0x0) /* (SDHC_CCR) Not Ready */ 449 #define SDHC_CCR_INTCLKS_READY_Val _UINT16_(0x1) /* (SDHC_CCR) Ready */ 450 #define SDHC_CCR_INTCLKS_NOT_READY (SDHC_CCR_INTCLKS_NOT_READY_Val << SDHC_CCR_INTCLKS_Pos) /* (SDHC_CCR) Not Ready Position */ 451 #define SDHC_CCR_INTCLKS_READY (SDHC_CCR_INTCLKS_READY_Val << SDHC_CCR_INTCLKS_Pos) /* (SDHC_CCR) Ready Position */ 452 #define SDHC_CCR_SDCLKEN_Pos _UINT16_(2) /* (SDHC_CCR) SD Clock Enable Position */ 453 #define SDHC_CCR_SDCLKEN_Msk (_UINT16_(0x1) << SDHC_CCR_SDCLKEN_Pos) /* (SDHC_CCR) SD Clock Enable Mask */ 454 #define SDHC_CCR_SDCLKEN(value) (SDHC_CCR_SDCLKEN_Msk & (_UINT16_(value) << SDHC_CCR_SDCLKEN_Pos)) /* Assigment of value for SDCLKEN in the SDHC_CCR register */ 455 #define SDHC_CCR_SDCLKEN_DISABLE_Val _UINT16_(0x0) /* (SDHC_CCR) Disable */ 456 #define SDHC_CCR_SDCLKEN_ENABLE_Val _UINT16_(0x1) /* (SDHC_CCR) Enable */ 457 #define SDHC_CCR_SDCLKEN_DISABLE (SDHC_CCR_SDCLKEN_DISABLE_Val << SDHC_CCR_SDCLKEN_Pos) /* (SDHC_CCR) Disable Position */ 458 #define SDHC_CCR_SDCLKEN_ENABLE (SDHC_CCR_SDCLKEN_ENABLE_Val << SDHC_CCR_SDCLKEN_Pos) /* (SDHC_CCR) Enable Position */ 459 #define SDHC_CCR_CLKGSEL_Pos _UINT16_(5) /* (SDHC_CCR) Clock Generator Select Position */ 460 #define SDHC_CCR_CLKGSEL_Msk (_UINT16_(0x1) << SDHC_CCR_CLKGSEL_Pos) /* (SDHC_CCR) Clock Generator Select Mask */ 461 #define SDHC_CCR_CLKGSEL(value) (SDHC_CCR_CLKGSEL_Msk & (_UINT16_(value) << SDHC_CCR_CLKGSEL_Pos)) /* Assigment of value for CLKGSEL in the SDHC_CCR register */ 462 #define SDHC_CCR_CLKGSEL_DIV_Val _UINT16_(0x0) /* (SDHC_CCR) Divided Clock Mode */ 463 #define SDHC_CCR_CLKGSEL_PROG_Val _UINT16_(0x1) /* (SDHC_CCR) Programmable Clock Mode */ 464 #define SDHC_CCR_CLKGSEL_DIV (SDHC_CCR_CLKGSEL_DIV_Val << SDHC_CCR_CLKGSEL_Pos) /* (SDHC_CCR) Divided Clock Mode Position */ 465 #define SDHC_CCR_CLKGSEL_PROG (SDHC_CCR_CLKGSEL_PROG_Val << SDHC_CCR_CLKGSEL_Pos) /* (SDHC_CCR) Programmable Clock Mode Position */ 466 #define SDHC_CCR_USDCLKFSEL_Pos _UINT16_(6) /* (SDHC_CCR) Upper Bits of SDCLK Frequency Select Position */ 467 #define SDHC_CCR_USDCLKFSEL_Msk (_UINT16_(0x3) << SDHC_CCR_USDCLKFSEL_Pos) /* (SDHC_CCR) Upper Bits of SDCLK Frequency Select Mask */ 468 #define SDHC_CCR_USDCLKFSEL(value) (SDHC_CCR_USDCLKFSEL_Msk & (_UINT16_(value) << SDHC_CCR_USDCLKFSEL_Pos)) /* Assigment of value for USDCLKFSEL in the SDHC_CCR register */ 469 #define SDHC_CCR_SDCLKFSEL_Pos _UINT16_(8) /* (SDHC_CCR) SDCLK Frequency Select Position */ 470 #define SDHC_CCR_SDCLKFSEL_Msk (_UINT16_(0xFF) << SDHC_CCR_SDCLKFSEL_Pos) /* (SDHC_CCR) SDCLK Frequency Select Mask */ 471 #define SDHC_CCR_SDCLKFSEL(value) (SDHC_CCR_SDCLKFSEL_Msk & (_UINT16_(value) << SDHC_CCR_SDCLKFSEL_Pos)) /* Assigment of value for SDCLKFSEL in the SDHC_CCR register */ 472 #define SDHC_CCR_Msk _UINT16_(0xFFE7) /* (SDHC_CCR) Register Mask */ 473 474 475 /* -------- SDHC_TCR : (SDHC Offset: 0x2E) (R/W 8) Timeout Control -------- */ 476 #define SDHC_TCR_RESETVALUE _UINT8_(0x00) /* (SDHC_TCR) Timeout Control Reset Value */ 477 478 #define SDHC_TCR_DTCVAL_Pos _UINT8_(0) /* (SDHC_TCR) Data Timeout Counter Value Position */ 479 #define SDHC_TCR_DTCVAL_Msk (_UINT8_(0xF) << SDHC_TCR_DTCVAL_Pos) /* (SDHC_TCR) Data Timeout Counter Value Mask */ 480 #define SDHC_TCR_DTCVAL(value) (SDHC_TCR_DTCVAL_Msk & (_UINT8_(value) << SDHC_TCR_DTCVAL_Pos)) /* Assigment of value for DTCVAL in the SDHC_TCR register */ 481 #define SDHC_TCR_Msk _UINT8_(0x0F) /* (SDHC_TCR) Register Mask */ 482 483 484 /* -------- SDHC_SRR : (SDHC Offset: 0x2F) (R/W 8) Software Reset -------- */ 485 #define SDHC_SRR_RESETVALUE _UINT8_(0x00) /* (SDHC_SRR) Software Reset Reset Value */ 486 487 #define SDHC_SRR_SWRSTALL_Pos _UINT8_(0) /* (SDHC_SRR) Software Reset For All Position */ 488 #define SDHC_SRR_SWRSTALL_Msk (_UINT8_(0x1) << SDHC_SRR_SWRSTALL_Pos) /* (SDHC_SRR) Software Reset For All Mask */ 489 #define SDHC_SRR_SWRSTALL(value) (SDHC_SRR_SWRSTALL_Msk & (_UINT8_(value) << SDHC_SRR_SWRSTALL_Pos)) /* Assigment of value for SWRSTALL in the SDHC_SRR register */ 490 #define SDHC_SRR_SWRSTALL_WORK_Val _UINT8_(0x0) /* (SDHC_SRR) Work */ 491 #define SDHC_SRR_SWRSTALL_RESET_Val _UINT8_(0x1) /* (SDHC_SRR) Reset */ 492 #define SDHC_SRR_SWRSTALL_WORK (SDHC_SRR_SWRSTALL_WORK_Val << SDHC_SRR_SWRSTALL_Pos) /* (SDHC_SRR) Work Position */ 493 #define SDHC_SRR_SWRSTALL_RESET (SDHC_SRR_SWRSTALL_RESET_Val << SDHC_SRR_SWRSTALL_Pos) /* (SDHC_SRR) Reset Position */ 494 #define SDHC_SRR_SWRSTCMD_Pos _UINT8_(1) /* (SDHC_SRR) Software Reset For CMD Line Position */ 495 #define SDHC_SRR_SWRSTCMD_Msk (_UINT8_(0x1) << SDHC_SRR_SWRSTCMD_Pos) /* (SDHC_SRR) Software Reset For CMD Line Mask */ 496 #define SDHC_SRR_SWRSTCMD(value) (SDHC_SRR_SWRSTCMD_Msk & (_UINT8_(value) << SDHC_SRR_SWRSTCMD_Pos)) /* Assigment of value for SWRSTCMD in the SDHC_SRR register */ 497 #define SDHC_SRR_SWRSTCMD_WORK_Val _UINT8_(0x0) /* (SDHC_SRR) Work */ 498 #define SDHC_SRR_SWRSTCMD_RESET_Val _UINT8_(0x1) /* (SDHC_SRR) Reset */ 499 #define SDHC_SRR_SWRSTCMD_WORK (SDHC_SRR_SWRSTCMD_WORK_Val << SDHC_SRR_SWRSTCMD_Pos) /* (SDHC_SRR) Work Position */ 500 #define SDHC_SRR_SWRSTCMD_RESET (SDHC_SRR_SWRSTCMD_RESET_Val << SDHC_SRR_SWRSTCMD_Pos) /* (SDHC_SRR) Reset Position */ 501 #define SDHC_SRR_SWRSTDAT_Pos _UINT8_(2) /* (SDHC_SRR) Software Reset For DAT Line Position */ 502 #define SDHC_SRR_SWRSTDAT_Msk (_UINT8_(0x1) << SDHC_SRR_SWRSTDAT_Pos) /* (SDHC_SRR) Software Reset For DAT Line Mask */ 503 #define SDHC_SRR_SWRSTDAT(value) (SDHC_SRR_SWRSTDAT_Msk & (_UINT8_(value) << SDHC_SRR_SWRSTDAT_Pos)) /* Assigment of value for SWRSTDAT in the SDHC_SRR register */ 504 #define SDHC_SRR_SWRSTDAT_WORK_Val _UINT8_(0x0) /* (SDHC_SRR) Work */ 505 #define SDHC_SRR_SWRSTDAT_RESET_Val _UINT8_(0x1) /* (SDHC_SRR) Reset */ 506 #define SDHC_SRR_SWRSTDAT_WORK (SDHC_SRR_SWRSTDAT_WORK_Val << SDHC_SRR_SWRSTDAT_Pos) /* (SDHC_SRR) Work Position */ 507 #define SDHC_SRR_SWRSTDAT_RESET (SDHC_SRR_SWRSTDAT_RESET_Val << SDHC_SRR_SWRSTDAT_Pos) /* (SDHC_SRR) Reset Position */ 508 #define SDHC_SRR_Msk _UINT8_(0x07) /* (SDHC_SRR) Register Mask */ 509 510 511 /* -------- SDHC_NISTR : (SDHC Offset: 0x30) (R/W 16) Normal Interrupt Status -------- */ 512 #define SDHC_NISTR_RESETVALUE _UINT16_(0x00) /* (SDHC_NISTR) Normal Interrupt Status Reset Value */ 513 514 #define SDHC_NISTR_CMDC_Pos _UINT16_(0) /* (SDHC_NISTR) Command Complete Position */ 515 #define SDHC_NISTR_CMDC_Msk (_UINT16_(0x1) << SDHC_NISTR_CMDC_Pos) /* (SDHC_NISTR) Command Complete Mask */ 516 #define SDHC_NISTR_CMDC(value) (SDHC_NISTR_CMDC_Msk & (_UINT16_(value) << SDHC_NISTR_CMDC_Pos)) /* Assigment of value for CMDC in the SDHC_NISTR register */ 517 #define SDHC_NISTR_CMDC_NO_Val _UINT16_(0x0) /* (SDHC_NISTR) No command complete */ 518 #define SDHC_NISTR_CMDC_YES_Val _UINT16_(0x1) /* (SDHC_NISTR) Command complete */ 519 #define SDHC_NISTR_CMDC_NO (SDHC_NISTR_CMDC_NO_Val << SDHC_NISTR_CMDC_Pos) /* (SDHC_NISTR) No command complete Position */ 520 #define SDHC_NISTR_CMDC_YES (SDHC_NISTR_CMDC_YES_Val << SDHC_NISTR_CMDC_Pos) /* (SDHC_NISTR) Command complete Position */ 521 #define SDHC_NISTR_TRFC_Pos _UINT16_(1) /* (SDHC_NISTR) Transfer Complete Position */ 522 #define SDHC_NISTR_TRFC_Msk (_UINT16_(0x1) << SDHC_NISTR_TRFC_Pos) /* (SDHC_NISTR) Transfer Complete Mask */ 523 #define SDHC_NISTR_TRFC(value) (SDHC_NISTR_TRFC_Msk & (_UINT16_(value) << SDHC_NISTR_TRFC_Pos)) /* Assigment of value for TRFC in the SDHC_NISTR register */ 524 #define SDHC_NISTR_TRFC_NO_Val _UINT16_(0x0) /* (SDHC_NISTR) Not complete */ 525 #define SDHC_NISTR_TRFC_YES_Val _UINT16_(0x1) /* (SDHC_NISTR) Command execution is completed */ 526 #define SDHC_NISTR_TRFC_NO (SDHC_NISTR_TRFC_NO_Val << SDHC_NISTR_TRFC_Pos) /* (SDHC_NISTR) Not complete Position */ 527 #define SDHC_NISTR_TRFC_YES (SDHC_NISTR_TRFC_YES_Val << SDHC_NISTR_TRFC_Pos) /* (SDHC_NISTR) Command execution is completed Position */ 528 #define SDHC_NISTR_BLKGE_Pos _UINT16_(2) /* (SDHC_NISTR) Block Gap Event Position */ 529 #define SDHC_NISTR_BLKGE_Msk (_UINT16_(0x1) << SDHC_NISTR_BLKGE_Pos) /* (SDHC_NISTR) Block Gap Event Mask */ 530 #define SDHC_NISTR_BLKGE(value) (SDHC_NISTR_BLKGE_Msk & (_UINT16_(value) << SDHC_NISTR_BLKGE_Pos)) /* Assigment of value for BLKGE in the SDHC_NISTR register */ 531 #define SDHC_NISTR_BLKGE_NO_Val _UINT16_(0x0) /* (SDHC_NISTR) No Block Gap Event */ 532 #define SDHC_NISTR_BLKGE_STOP_Val _UINT16_(0x1) /* (SDHC_NISTR) Transaction stopped at block gap */ 533 #define SDHC_NISTR_BLKGE_NO (SDHC_NISTR_BLKGE_NO_Val << SDHC_NISTR_BLKGE_Pos) /* (SDHC_NISTR) No Block Gap Event Position */ 534 #define SDHC_NISTR_BLKGE_STOP (SDHC_NISTR_BLKGE_STOP_Val << SDHC_NISTR_BLKGE_Pos) /* (SDHC_NISTR) Transaction stopped at block gap Position */ 535 #define SDHC_NISTR_DMAINT_Pos _UINT16_(3) /* (SDHC_NISTR) DMA Interrupt Position */ 536 #define SDHC_NISTR_DMAINT_Msk (_UINT16_(0x1) << SDHC_NISTR_DMAINT_Pos) /* (SDHC_NISTR) DMA Interrupt Mask */ 537 #define SDHC_NISTR_DMAINT(value) (SDHC_NISTR_DMAINT_Msk & (_UINT16_(value) << SDHC_NISTR_DMAINT_Pos)) /* Assigment of value for DMAINT in the SDHC_NISTR register */ 538 #define SDHC_NISTR_DMAINT_NO_Val _UINT16_(0x0) /* (SDHC_NISTR) No DMA Interrupt */ 539 #define SDHC_NISTR_DMAINT_YES_Val _UINT16_(0x1) /* (SDHC_NISTR) DMA Interrupt is generated */ 540 #define SDHC_NISTR_DMAINT_NO (SDHC_NISTR_DMAINT_NO_Val << SDHC_NISTR_DMAINT_Pos) /* (SDHC_NISTR) No DMA Interrupt Position */ 541 #define SDHC_NISTR_DMAINT_YES (SDHC_NISTR_DMAINT_YES_Val << SDHC_NISTR_DMAINT_Pos) /* (SDHC_NISTR) DMA Interrupt is generated Position */ 542 #define SDHC_NISTR_BWRRDY_Pos _UINT16_(4) /* (SDHC_NISTR) Buffer Write Ready Position */ 543 #define SDHC_NISTR_BWRRDY_Msk (_UINT16_(0x1) << SDHC_NISTR_BWRRDY_Pos) /* (SDHC_NISTR) Buffer Write Ready Mask */ 544 #define SDHC_NISTR_BWRRDY(value) (SDHC_NISTR_BWRRDY_Msk & (_UINT16_(value) << SDHC_NISTR_BWRRDY_Pos)) /* Assigment of value for BWRRDY in the SDHC_NISTR register */ 545 #define SDHC_NISTR_BWRRDY_NO_Val _UINT16_(0x0) /* (SDHC_NISTR) Not ready to write buffer */ 546 #define SDHC_NISTR_BWRRDY_YES_Val _UINT16_(0x1) /* (SDHC_NISTR) Ready to write buffer */ 547 #define SDHC_NISTR_BWRRDY_NO (SDHC_NISTR_BWRRDY_NO_Val << SDHC_NISTR_BWRRDY_Pos) /* (SDHC_NISTR) Not ready to write buffer Position */ 548 #define SDHC_NISTR_BWRRDY_YES (SDHC_NISTR_BWRRDY_YES_Val << SDHC_NISTR_BWRRDY_Pos) /* (SDHC_NISTR) Ready to write buffer Position */ 549 #define SDHC_NISTR_BRDRDY_Pos _UINT16_(5) /* (SDHC_NISTR) Buffer Read Ready Position */ 550 #define SDHC_NISTR_BRDRDY_Msk (_UINT16_(0x1) << SDHC_NISTR_BRDRDY_Pos) /* (SDHC_NISTR) Buffer Read Ready Mask */ 551 #define SDHC_NISTR_BRDRDY(value) (SDHC_NISTR_BRDRDY_Msk & (_UINT16_(value) << SDHC_NISTR_BRDRDY_Pos)) /* Assigment of value for BRDRDY in the SDHC_NISTR register */ 552 #define SDHC_NISTR_BRDRDY_NO_Val _UINT16_(0x0) /* (SDHC_NISTR) Not ready to read buffer */ 553 #define SDHC_NISTR_BRDRDY_YES_Val _UINT16_(0x1) /* (SDHC_NISTR) Ready to read buffer */ 554 #define SDHC_NISTR_BRDRDY_NO (SDHC_NISTR_BRDRDY_NO_Val << SDHC_NISTR_BRDRDY_Pos) /* (SDHC_NISTR) Not ready to read buffer Position */ 555 #define SDHC_NISTR_BRDRDY_YES (SDHC_NISTR_BRDRDY_YES_Val << SDHC_NISTR_BRDRDY_Pos) /* (SDHC_NISTR) Ready to read buffer Position */ 556 #define SDHC_NISTR_CINS_Pos _UINT16_(6) /* (SDHC_NISTR) Card Insertion Position */ 557 #define SDHC_NISTR_CINS_Msk (_UINT16_(0x1) << SDHC_NISTR_CINS_Pos) /* (SDHC_NISTR) Card Insertion Mask */ 558 #define SDHC_NISTR_CINS(value) (SDHC_NISTR_CINS_Msk & (_UINT16_(value) << SDHC_NISTR_CINS_Pos)) /* Assigment of value for CINS in the SDHC_NISTR register */ 559 #define SDHC_NISTR_CINS_NO_Val _UINT16_(0x0) /* (SDHC_NISTR) Card state stable or Debouncing */ 560 #define SDHC_NISTR_CINS_YES_Val _UINT16_(0x1) /* (SDHC_NISTR) Card inserted */ 561 #define SDHC_NISTR_CINS_NO (SDHC_NISTR_CINS_NO_Val << SDHC_NISTR_CINS_Pos) /* (SDHC_NISTR) Card state stable or Debouncing Position */ 562 #define SDHC_NISTR_CINS_YES (SDHC_NISTR_CINS_YES_Val << SDHC_NISTR_CINS_Pos) /* (SDHC_NISTR) Card inserted Position */ 563 #define SDHC_NISTR_CREM_Pos _UINT16_(7) /* (SDHC_NISTR) Card Removal Position */ 564 #define SDHC_NISTR_CREM_Msk (_UINT16_(0x1) << SDHC_NISTR_CREM_Pos) /* (SDHC_NISTR) Card Removal Mask */ 565 #define SDHC_NISTR_CREM(value) (SDHC_NISTR_CREM_Msk & (_UINT16_(value) << SDHC_NISTR_CREM_Pos)) /* Assigment of value for CREM in the SDHC_NISTR register */ 566 #define SDHC_NISTR_CREM_NO_Val _UINT16_(0x0) /* (SDHC_NISTR) Card state stable or Debouncing */ 567 #define SDHC_NISTR_CREM_YES_Val _UINT16_(0x1) /* (SDHC_NISTR) Card Removed */ 568 #define SDHC_NISTR_CREM_NO (SDHC_NISTR_CREM_NO_Val << SDHC_NISTR_CREM_Pos) /* (SDHC_NISTR) Card state stable or Debouncing Position */ 569 #define SDHC_NISTR_CREM_YES (SDHC_NISTR_CREM_YES_Val << SDHC_NISTR_CREM_Pos) /* (SDHC_NISTR) Card Removed Position */ 570 #define SDHC_NISTR_CINT_Pos _UINT16_(8) /* (SDHC_NISTR) Card Interrupt Position */ 571 #define SDHC_NISTR_CINT_Msk (_UINT16_(0x1) << SDHC_NISTR_CINT_Pos) /* (SDHC_NISTR) Card Interrupt Mask */ 572 #define SDHC_NISTR_CINT(value) (SDHC_NISTR_CINT_Msk & (_UINT16_(value) << SDHC_NISTR_CINT_Pos)) /* Assigment of value for CINT in the SDHC_NISTR register */ 573 #define SDHC_NISTR_CINT_NO_Val _UINT16_(0x0) /* (SDHC_NISTR) No Card Interrupt */ 574 #define SDHC_NISTR_CINT_YES_Val _UINT16_(0x1) /* (SDHC_NISTR) Generate Card Interrupt */ 575 #define SDHC_NISTR_CINT_NO (SDHC_NISTR_CINT_NO_Val << SDHC_NISTR_CINT_Pos) /* (SDHC_NISTR) No Card Interrupt Position */ 576 #define SDHC_NISTR_CINT_YES (SDHC_NISTR_CINT_YES_Val << SDHC_NISTR_CINT_Pos) /* (SDHC_NISTR) Generate Card Interrupt Position */ 577 #define SDHC_NISTR_ERRINT_Pos _UINT16_(15) /* (SDHC_NISTR) Error Interrupt Position */ 578 #define SDHC_NISTR_ERRINT_Msk (_UINT16_(0x1) << SDHC_NISTR_ERRINT_Pos) /* (SDHC_NISTR) Error Interrupt Mask */ 579 #define SDHC_NISTR_ERRINT(value) (SDHC_NISTR_ERRINT_Msk & (_UINT16_(value) << SDHC_NISTR_ERRINT_Pos)) /* Assigment of value for ERRINT in the SDHC_NISTR register */ 580 #define SDHC_NISTR_ERRINT_NO_Val _UINT16_(0x0) /* (SDHC_NISTR) No Error */ 581 #define SDHC_NISTR_ERRINT_YES_Val _UINT16_(0x1) /* (SDHC_NISTR) Error */ 582 #define SDHC_NISTR_ERRINT_NO (SDHC_NISTR_ERRINT_NO_Val << SDHC_NISTR_ERRINT_Pos) /* (SDHC_NISTR) No Error Position */ 583 #define SDHC_NISTR_ERRINT_YES (SDHC_NISTR_ERRINT_YES_Val << SDHC_NISTR_ERRINT_Pos) /* (SDHC_NISTR) Error Position */ 584 #define SDHC_NISTR_Msk _UINT16_(0x81FF) /* (SDHC_NISTR) Register Mask */ 585 586 /* EMMC mode */ 587 #define SDHC_NISTR_EMMC_BOOTAR_Pos _UINT16_(14) /* (SDHC_NISTR) Boot Acknowledge Received Position */ 588 #define SDHC_NISTR_EMMC_BOOTAR_Msk (_UINT16_(0x1) << SDHC_NISTR_EMMC_BOOTAR_Pos) /* (SDHC_NISTR) Boot Acknowledge Received Mask */ 589 #define SDHC_NISTR_EMMC_BOOTAR(value) (SDHC_NISTR_EMMC_BOOTAR_Msk & (_UINT16_(value) << SDHC_NISTR_EMMC_BOOTAR_Pos)) 590 #define SDHC_NISTR_EMMC_Msk _UINT16_(0x4000) /* (SDHC_NISTR_EMMC) Register Mask */ 591 592 593 /* -------- SDHC_EISTR : (SDHC Offset: 0x32) (R/W 16) Error Interrupt Status -------- */ 594 #define SDHC_EISTR_RESETVALUE _UINT16_(0x00) /* (SDHC_EISTR) Error Interrupt Status Reset Value */ 595 596 #define SDHC_EISTR_CMDTEO_Pos _UINT16_(0) /* (SDHC_EISTR) Command Timeout Error Position */ 597 #define SDHC_EISTR_CMDTEO_Msk (_UINT16_(0x1) << SDHC_EISTR_CMDTEO_Pos) /* (SDHC_EISTR) Command Timeout Error Mask */ 598 #define SDHC_EISTR_CMDTEO(value) (SDHC_EISTR_CMDTEO_Msk & (_UINT16_(value) << SDHC_EISTR_CMDTEO_Pos)) /* Assigment of value for CMDTEO in the SDHC_EISTR register */ 599 #define SDHC_EISTR_CMDTEO_NO_Val _UINT16_(0x0) /* (SDHC_EISTR) No Error */ 600 #define SDHC_EISTR_CMDTEO_YES_Val _UINT16_(0x1) /* (SDHC_EISTR) Timeout */ 601 #define SDHC_EISTR_CMDTEO_NO (SDHC_EISTR_CMDTEO_NO_Val << SDHC_EISTR_CMDTEO_Pos) /* (SDHC_EISTR) No Error Position */ 602 #define SDHC_EISTR_CMDTEO_YES (SDHC_EISTR_CMDTEO_YES_Val << SDHC_EISTR_CMDTEO_Pos) /* (SDHC_EISTR) Timeout Position */ 603 #define SDHC_EISTR_CMDCRC_Pos _UINT16_(1) /* (SDHC_EISTR) Command CRC Error Position */ 604 #define SDHC_EISTR_CMDCRC_Msk (_UINT16_(0x1) << SDHC_EISTR_CMDCRC_Pos) /* (SDHC_EISTR) Command CRC Error Mask */ 605 #define SDHC_EISTR_CMDCRC(value) (SDHC_EISTR_CMDCRC_Msk & (_UINT16_(value) << SDHC_EISTR_CMDCRC_Pos)) /* Assigment of value for CMDCRC in the SDHC_EISTR register */ 606 #define SDHC_EISTR_CMDCRC_NO_Val _UINT16_(0x0) /* (SDHC_EISTR) No Error */ 607 #define SDHC_EISTR_CMDCRC_YES_Val _UINT16_(0x1) /* (SDHC_EISTR) CRC Error Generated */ 608 #define SDHC_EISTR_CMDCRC_NO (SDHC_EISTR_CMDCRC_NO_Val << SDHC_EISTR_CMDCRC_Pos) /* (SDHC_EISTR) No Error Position */ 609 #define SDHC_EISTR_CMDCRC_YES (SDHC_EISTR_CMDCRC_YES_Val << SDHC_EISTR_CMDCRC_Pos) /* (SDHC_EISTR) CRC Error Generated Position */ 610 #define SDHC_EISTR_CMDEND_Pos _UINT16_(2) /* (SDHC_EISTR) Command End Bit Error Position */ 611 #define SDHC_EISTR_CMDEND_Msk (_UINT16_(0x1) << SDHC_EISTR_CMDEND_Pos) /* (SDHC_EISTR) Command End Bit Error Mask */ 612 #define SDHC_EISTR_CMDEND(value) (SDHC_EISTR_CMDEND_Msk & (_UINT16_(value) << SDHC_EISTR_CMDEND_Pos)) /* Assigment of value for CMDEND in the SDHC_EISTR register */ 613 #define SDHC_EISTR_CMDEND_NO_Val _UINT16_(0x0) /* (SDHC_EISTR) No error */ 614 #define SDHC_EISTR_CMDEND_YES_Val _UINT16_(0x1) /* (SDHC_EISTR) End Bit Error Generated */ 615 #define SDHC_EISTR_CMDEND_NO (SDHC_EISTR_CMDEND_NO_Val << SDHC_EISTR_CMDEND_Pos) /* (SDHC_EISTR) No error Position */ 616 #define SDHC_EISTR_CMDEND_YES (SDHC_EISTR_CMDEND_YES_Val << SDHC_EISTR_CMDEND_Pos) /* (SDHC_EISTR) End Bit Error Generated Position */ 617 #define SDHC_EISTR_CMDIDX_Pos _UINT16_(3) /* (SDHC_EISTR) Command Index Error Position */ 618 #define SDHC_EISTR_CMDIDX_Msk (_UINT16_(0x1) << SDHC_EISTR_CMDIDX_Pos) /* (SDHC_EISTR) Command Index Error Mask */ 619 #define SDHC_EISTR_CMDIDX(value) (SDHC_EISTR_CMDIDX_Msk & (_UINT16_(value) << SDHC_EISTR_CMDIDX_Pos)) /* Assigment of value for CMDIDX in the SDHC_EISTR register */ 620 #define SDHC_EISTR_CMDIDX_NO_Val _UINT16_(0x0) /* (SDHC_EISTR) No Error */ 621 #define SDHC_EISTR_CMDIDX_YES_Val _UINT16_(0x1) /* (SDHC_EISTR) Error */ 622 #define SDHC_EISTR_CMDIDX_NO (SDHC_EISTR_CMDIDX_NO_Val << SDHC_EISTR_CMDIDX_Pos) /* (SDHC_EISTR) No Error Position */ 623 #define SDHC_EISTR_CMDIDX_YES (SDHC_EISTR_CMDIDX_YES_Val << SDHC_EISTR_CMDIDX_Pos) /* (SDHC_EISTR) Error Position */ 624 #define SDHC_EISTR_DATTEO_Pos _UINT16_(4) /* (SDHC_EISTR) Data Timeout Error Position */ 625 #define SDHC_EISTR_DATTEO_Msk (_UINT16_(0x1) << SDHC_EISTR_DATTEO_Pos) /* (SDHC_EISTR) Data Timeout Error Mask */ 626 #define SDHC_EISTR_DATTEO(value) (SDHC_EISTR_DATTEO_Msk & (_UINT16_(value) << SDHC_EISTR_DATTEO_Pos)) /* Assigment of value for DATTEO in the SDHC_EISTR register */ 627 #define SDHC_EISTR_DATTEO_NO_Val _UINT16_(0x0) /* (SDHC_EISTR) No Error */ 628 #define SDHC_EISTR_DATTEO_YES_Val _UINT16_(0x1) /* (SDHC_EISTR) Timeout */ 629 #define SDHC_EISTR_DATTEO_NO (SDHC_EISTR_DATTEO_NO_Val << SDHC_EISTR_DATTEO_Pos) /* (SDHC_EISTR) No Error Position */ 630 #define SDHC_EISTR_DATTEO_YES (SDHC_EISTR_DATTEO_YES_Val << SDHC_EISTR_DATTEO_Pos) /* (SDHC_EISTR) Timeout Position */ 631 #define SDHC_EISTR_DATCRC_Pos _UINT16_(5) /* (SDHC_EISTR) Data CRC Error Position */ 632 #define SDHC_EISTR_DATCRC_Msk (_UINT16_(0x1) << SDHC_EISTR_DATCRC_Pos) /* (SDHC_EISTR) Data CRC Error Mask */ 633 #define SDHC_EISTR_DATCRC(value) (SDHC_EISTR_DATCRC_Msk & (_UINT16_(value) << SDHC_EISTR_DATCRC_Pos)) /* Assigment of value for DATCRC in the SDHC_EISTR register */ 634 #define SDHC_EISTR_DATCRC_NO_Val _UINT16_(0x0) /* (SDHC_EISTR) No Error */ 635 #define SDHC_EISTR_DATCRC_YES_Val _UINT16_(0x1) /* (SDHC_EISTR) Error */ 636 #define SDHC_EISTR_DATCRC_NO (SDHC_EISTR_DATCRC_NO_Val << SDHC_EISTR_DATCRC_Pos) /* (SDHC_EISTR) No Error Position */ 637 #define SDHC_EISTR_DATCRC_YES (SDHC_EISTR_DATCRC_YES_Val << SDHC_EISTR_DATCRC_Pos) /* (SDHC_EISTR) Error Position */ 638 #define SDHC_EISTR_DATEND_Pos _UINT16_(6) /* (SDHC_EISTR) Data End Bit Error Position */ 639 #define SDHC_EISTR_DATEND_Msk (_UINT16_(0x1) << SDHC_EISTR_DATEND_Pos) /* (SDHC_EISTR) Data End Bit Error Mask */ 640 #define SDHC_EISTR_DATEND(value) (SDHC_EISTR_DATEND_Msk & (_UINT16_(value) << SDHC_EISTR_DATEND_Pos)) /* Assigment of value for DATEND in the SDHC_EISTR register */ 641 #define SDHC_EISTR_DATEND_NO_Val _UINT16_(0x0) /* (SDHC_EISTR) No Error */ 642 #define SDHC_EISTR_DATEND_YES_Val _UINT16_(0x1) /* (SDHC_EISTR) Error */ 643 #define SDHC_EISTR_DATEND_NO (SDHC_EISTR_DATEND_NO_Val << SDHC_EISTR_DATEND_Pos) /* (SDHC_EISTR) No Error Position */ 644 #define SDHC_EISTR_DATEND_YES (SDHC_EISTR_DATEND_YES_Val << SDHC_EISTR_DATEND_Pos) /* (SDHC_EISTR) Error Position */ 645 #define SDHC_EISTR_CURLIM_Pos _UINT16_(7) /* (SDHC_EISTR) Current Limit Error Position */ 646 #define SDHC_EISTR_CURLIM_Msk (_UINT16_(0x1) << SDHC_EISTR_CURLIM_Pos) /* (SDHC_EISTR) Current Limit Error Mask */ 647 #define SDHC_EISTR_CURLIM(value) (SDHC_EISTR_CURLIM_Msk & (_UINT16_(value) << SDHC_EISTR_CURLIM_Pos)) /* Assigment of value for CURLIM in the SDHC_EISTR register */ 648 #define SDHC_EISTR_CURLIM_NO_Val _UINT16_(0x0) /* (SDHC_EISTR) No Error */ 649 #define SDHC_EISTR_CURLIM_YES_Val _UINT16_(0x1) /* (SDHC_EISTR) Power Fail */ 650 #define SDHC_EISTR_CURLIM_NO (SDHC_EISTR_CURLIM_NO_Val << SDHC_EISTR_CURLIM_Pos) /* (SDHC_EISTR) No Error Position */ 651 #define SDHC_EISTR_CURLIM_YES (SDHC_EISTR_CURLIM_YES_Val << SDHC_EISTR_CURLIM_Pos) /* (SDHC_EISTR) Power Fail Position */ 652 #define SDHC_EISTR_ACMD_Pos _UINT16_(8) /* (SDHC_EISTR) Auto CMD Error Position */ 653 #define SDHC_EISTR_ACMD_Msk (_UINT16_(0x1) << SDHC_EISTR_ACMD_Pos) /* (SDHC_EISTR) Auto CMD Error Mask */ 654 #define SDHC_EISTR_ACMD(value) (SDHC_EISTR_ACMD_Msk & (_UINT16_(value) << SDHC_EISTR_ACMD_Pos)) /* Assigment of value for ACMD in the SDHC_EISTR register */ 655 #define SDHC_EISTR_ACMD_NO_Val _UINT16_(0x0) /* (SDHC_EISTR) No Error */ 656 #define SDHC_EISTR_ACMD_YES_Val _UINT16_(0x1) /* (SDHC_EISTR) Error */ 657 #define SDHC_EISTR_ACMD_NO (SDHC_EISTR_ACMD_NO_Val << SDHC_EISTR_ACMD_Pos) /* (SDHC_EISTR) No Error Position */ 658 #define SDHC_EISTR_ACMD_YES (SDHC_EISTR_ACMD_YES_Val << SDHC_EISTR_ACMD_Pos) /* (SDHC_EISTR) Error Position */ 659 #define SDHC_EISTR_ADMA_Pos _UINT16_(9) /* (SDHC_EISTR) ADMA Error Position */ 660 #define SDHC_EISTR_ADMA_Msk (_UINT16_(0x1) << SDHC_EISTR_ADMA_Pos) /* (SDHC_EISTR) ADMA Error Mask */ 661 #define SDHC_EISTR_ADMA(value) (SDHC_EISTR_ADMA_Msk & (_UINT16_(value) << SDHC_EISTR_ADMA_Pos)) /* Assigment of value for ADMA in the SDHC_EISTR register */ 662 #define SDHC_EISTR_ADMA_NO_Val _UINT16_(0x0) /* (SDHC_EISTR) No Error */ 663 #define SDHC_EISTR_ADMA_YES_Val _UINT16_(0x1) /* (SDHC_EISTR) Error */ 664 #define SDHC_EISTR_ADMA_NO (SDHC_EISTR_ADMA_NO_Val << SDHC_EISTR_ADMA_Pos) /* (SDHC_EISTR) No Error Position */ 665 #define SDHC_EISTR_ADMA_YES (SDHC_EISTR_ADMA_YES_Val << SDHC_EISTR_ADMA_Pos) /* (SDHC_EISTR) Error Position */ 666 #define SDHC_EISTR_Msk _UINT16_(0x03FF) /* (SDHC_EISTR) Register Mask */ 667 668 /* EMMC mode */ 669 #define SDHC_EISTR_EMMC_BOOTAE_Pos _UINT16_(12) /* (SDHC_EISTR) Boot Acknowledge Error Position */ 670 #define SDHC_EISTR_EMMC_BOOTAE_Msk (_UINT16_(0x1) << SDHC_EISTR_EMMC_BOOTAE_Pos) /* (SDHC_EISTR) Boot Acknowledge Error Mask */ 671 #define SDHC_EISTR_EMMC_BOOTAE(value) (SDHC_EISTR_EMMC_BOOTAE_Msk & (_UINT16_(value) << SDHC_EISTR_EMMC_BOOTAE_Pos)) 672 #define SDHC_EISTR_EMMC_BOOTAE_FIFONOTEMPTY_Val _UINT16_(0x0) /* (SDHC_EISTR) FIFO contains at least one byte */ 673 #define SDHC_EISTR_EMMC_BOOTAE_FIFOEMPTY_Val _UINT16_(0x1) /* (SDHC_EISTR) FIFO is empty */ 674 #define SDHC_EISTR_EMMC_BOOTAE_FIFONOTEMPTY (SDHC_EISTR_EMMC_BOOTAE_FIFONOTEMPTY_Val << SDHC_EISTR_EMMC_BOOTAE_Pos) /* (SDHC_EISTR) FIFO contains at least one byte Position */ 675 #define SDHC_EISTR_EMMC_BOOTAE_FIFOEMPTY (SDHC_EISTR_EMMC_BOOTAE_FIFOEMPTY_Val << SDHC_EISTR_EMMC_BOOTAE_Pos) /* (SDHC_EISTR) FIFO is empty Position */ 676 #define SDHC_EISTR_EMMC_Msk _UINT16_(0x1000) /* (SDHC_EISTR_EMMC) Register Mask */ 677 678 679 /* -------- SDHC_NISTER : (SDHC Offset: 0x34) (R/W 16) Normal Interrupt Status Enable -------- */ 680 #define SDHC_NISTER_RESETVALUE _UINT16_(0x00) /* (SDHC_NISTER) Normal Interrupt Status Enable Reset Value */ 681 682 #define SDHC_NISTER_CMDC_Pos _UINT16_(0) /* (SDHC_NISTER) Command Complete Status Enable Position */ 683 #define SDHC_NISTER_CMDC_Msk (_UINT16_(0x1) << SDHC_NISTER_CMDC_Pos) /* (SDHC_NISTER) Command Complete Status Enable Mask */ 684 #define SDHC_NISTER_CMDC(value) (SDHC_NISTER_CMDC_Msk & (_UINT16_(value) << SDHC_NISTER_CMDC_Pos)) /* Assigment of value for CMDC in the SDHC_NISTER register */ 685 #define SDHC_NISTER_CMDC_MASKED_Val _UINT16_(0x0) /* (SDHC_NISTER) Masked */ 686 #define SDHC_NISTER_CMDC_ENABLED_Val _UINT16_(0x1) /* (SDHC_NISTER) Enabled */ 687 #define SDHC_NISTER_CMDC_MASKED (SDHC_NISTER_CMDC_MASKED_Val << SDHC_NISTER_CMDC_Pos) /* (SDHC_NISTER) Masked Position */ 688 #define SDHC_NISTER_CMDC_ENABLED (SDHC_NISTER_CMDC_ENABLED_Val << SDHC_NISTER_CMDC_Pos) /* (SDHC_NISTER) Enabled Position */ 689 #define SDHC_NISTER_TRFC_Pos _UINT16_(1) /* (SDHC_NISTER) Transfer Complete Status Enable Position */ 690 #define SDHC_NISTER_TRFC_Msk (_UINT16_(0x1) << SDHC_NISTER_TRFC_Pos) /* (SDHC_NISTER) Transfer Complete Status Enable Mask */ 691 #define SDHC_NISTER_TRFC(value) (SDHC_NISTER_TRFC_Msk & (_UINT16_(value) << SDHC_NISTER_TRFC_Pos)) /* Assigment of value for TRFC in the SDHC_NISTER register */ 692 #define SDHC_NISTER_TRFC_MASKED_Val _UINT16_(0x0) /* (SDHC_NISTER) Masked */ 693 #define SDHC_NISTER_TRFC_ENABLED_Val _UINT16_(0x1) /* (SDHC_NISTER) Enabled */ 694 #define SDHC_NISTER_TRFC_MASKED (SDHC_NISTER_TRFC_MASKED_Val << SDHC_NISTER_TRFC_Pos) /* (SDHC_NISTER) Masked Position */ 695 #define SDHC_NISTER_TRFC_ENABLED (SDHC_NISTER_TRFC_ENABLED_Val << SDHC_NISTER_TRFC_Pos) /* (SDHC_NISTER) Enabled Position */ 696 #define SDHC_NISTER_BLKGE_Pos _UINT16_(2) /* (SDHC_NISTER) Block Gap Event Status Enable Position */ 697 #define SDHC_NISTER_BLKGE_Msk (_UINT16_(0x1) << SDHC_NISTER_BLKGE_Pos) /* (SDHC_NISTER) Block Gap Event Status Enable Mask */ 698 #define SDHC_NISTER_BLKGE(value) (SDHC_NISTER_BLKGE_Msk & (_UINT16_(value) << SDHC_NISTER_BLKGE_Pos)) /* Assigment of value for BLKGE in the SDHC_NISTER register */ 699 #define SDHC_NISTER_BLKGE_MASKED_Val _UINT16_(0x0) /* (SDHC_NISTER) Masked */ 700 #define SDHC_NISTER_BLKGE_ENABLED_Val _UINT16_(0x1) /* (SDHC_NISTER) Enabled */ 701 #define SDHC_NISTER_BLKGE_MASKED (SDHC_NISTER_BLKGE_MASKED_Val << SDHC_NISTER_BLKGE_Pos) /* (SDHC_NISTER) Masked Position */ 702 #define SDHC_NISTER_BLKGE_ENABLED (SDHC_NISTER_BLKGE_ENABLED_Val << SDHC_NISTER_BLKGE_Pos) /* (SDHC_NISTER) Enabled Position */ 703 #define SDHC_NISTER_DMAINT_Pos _UINT16_(3) /* (SDHC_NISTER) DMA Interrupt Status Enable Position */ 704 #define SDHC_NISTER_DMAINT_Msk (_UINT16_(0x1) << SDHC_NISTER_DMAINT_Pos) /* (SDHC_NISTER) DMA Interrupt Status Enable Mask */ 705 #define SDHC_NISTER_DMAINT(value) (SDHC_NISTER_DMAINT_Msk & (_UINT16_(value) << SDHC_NISTER_DMAINT_Pos)) /* Assigment of value for DMAINT in the SDHC_NISTER register */ 706 #define SDHC_NISTER_DMAINT_MASKED_Val _UINT16_(0x0) /* (SDHC_NISTER) Masked */ 707 #define SDHC_NISTER_DMAINT_ENABLED_Val _UINT16_(0x1) /* (SDHC_NISTER) Enabled */ 708 #define SDHC_NISTER_DMAINT_MASKED (SDHC_NISTER_DMAINT_MASKED_Val << SDHC_NISTER_DMAINT_Pos) /* (SDHC_NISTER) Masked Position */ 709 #define SDHC_NISTER_DMAINT_ENABLED (SDHC_NISTER_DMAINT_ENABLED_Val << SDHC_NISTER_DMAINT_Pos) /* (SDHC_NISTER) Enabled Position */ 710 #define SDHC_NISTER_BWRRDY_Pos _UINT16_(4) /* (SDHC_NISTER) Buffer Write Ready Status Enable Position */ 711 #define SDHC_NISTER_BWRRDY_Msk (_UINT16_(0x1) << SDHC_NISTER_BWRRDY_Pos) /* (SDHC_NISTER) Buffer Write Ready Status Enable Mask */ 712 #define SDHC_NISTER_BWRRDY(value) (SDHC_NISTER_BWRRDY_Msk & (_UINT16_(value) << SDHC_NISTER_BWRRDY_Pos)) /* Assigment of value for BWRRDY in the SDHC_NISTER register */ 713 #define SDHC_NISTER_BWRRDY_MASKED_Val _UINT16_(0x0) /* (SDHC_NISTER) Masked */ 714 #define SDHC_NISTER_BWRRDY_ENABLED_Val _UINT16_(0x1) /* (SDHC_NISTER) Enabled */ 715 #define SDHC_NISTER_BWRRDY_MASKED (SDHC_NISTER_BWRRDY_MASKED_Val << SDHC_NISTER_BWRRDY_Pos) /* (SDHC_NISTER) Masked Position */ 716 #define SDHC_NISTER_BWRRDY_ENABLED (SDHC_NISTER_BWRRDY_ENABLED_Val << SDHC_NISTER_BWRRDY_Pos) /* (SDHC_NISTER) Enabled Position */ 717 #define SDHC_NISTER_BRDRDY_Pos _UINT16_(5) /* (SDHC_NISTER) Buffer Read Ready Status Enable Position */ 718 #define SDHC_NISTER_BRDRDY_Msk (_UINT16_(0x1) << SDHC_NISTER_BRDRDY_Pos) /* (SDHC_NISTER) Buffer Read Ready Status Enable Mask */ 719 #define SDHC_NISTER_BRDRDY(value) (SDHC_NISTER_BRDRDY_Msk & (_UINT16_(value) << SDHC_NISTER_BRDRDY_Pos)) /* Assigment of value for BRDRDY in the SDHC_NISTER register */ 720 #define SDHC_NISTER_BRDRDY_MASKED_Val _UINT16_(0x0) /* (SDHC_NISTER) Masked */ 721 #define SDHC_NISTER_BRDRDY_ENABLED_Val _UINT16_(0x1) /* (SDHC_NISTER) Enabled */ 722 #define SDHC_NISTER_BRDRDY_MASKED (SDHC_NISTER_BRDRDY_MASKED_Val << SDHC_NISTER_BRDRDY_Pos) /* (SDHC_NISTER) Masked Position */ 723 #define SDHC_NISTER_BRDRDY_ENABLED (SDHC_NISTER_BRDRDY_ENABLED_Val << SDHC_NISTER_BRDRDY_Pos) /* (SDHC_NISTER) Enabled Position */ 724 #define SDHC_NISTER_CINS_Pos _UINT16_(6) /* (SDHC_NISTER) Card Insertion Status Enable Position */ 725 #define SDHC_NISTER_CINS_Msk (_UINT16_(0x1) << SDHC_NISTER_CINS_Pos) /* (SDHC_NISTER) Card Insertion Status Enable Mask */ 726 #define SDHC_NISTER_CINS(value) (SDHC_NISTER_CINS_Msk & (_UINT16_(value) << SDHC_NISTER_CINS_Pos)) /* Assigment of value for CINS in the SDHC_NISTER register */ 727 #define SDHC_NISTER_CINS_MASKED_Val _UINT16_(0x0) /* (SDHC_NISTER) Masked */ 728 #define SDHC_NISTER_CINS_ENABLED_Val _UINT16_(0x1) /* (SDHC_NISTER) Enabled */ 729 #define SDHC_NISTER_CINS_MASKED (SDHC_NISTER_CINS_MASKED_Val << SDHC_NISTER_CINS_Pos) /* (SDHC_NISTER) Masked Position */ 730 #define SDHC_NISTER_CINS_ENABLED (SDHC_NISTER_CINS_ENABLED_Val << SDHC_NISTER_CINS_Pos) /* (SDHC_NISTER) Enabled Position */ 731 #define SDHC_NISTER_CREM_Pos _UINT16_(7) /* (SDHC_NISTER) Card Removal Status Enable Position */ 732 #define SDHC_NISTER_CREM_Msk (_UINT16_(0x1) << SDHC_NISTER_CREM_Pos) /* (SDHC_NISTER) Card Removal Status Enable Mask */ 733 #define SDHC_NISTER_CREM(value) (SDHC_NISTER_CREM_Msk & (_UINT16_(value) << SDHC_NISTER_CREM_Pos)) /* Assigment of value for CREM in the SDHC_NISTER register */ 734 #define SDHC_NISTER_CREM_MASKED_Val _UINT16_(0x0) /* (SDHC_NISTER) Masked */ 735 #define SDHC_NISTER_CREM_ENABLED_Val _UINT16_(0x1) /* (SDHC_NISTER) Enabled */ 736 #define SDHC_NISTER_CREM_MASKED (SDHC_NISTER_CREM_MASKED_Val << SDHC_NISTER_CREM_Pos) /* (SDHC_NISTER) Masked Position */ 737 #define SDHC_NISTER_CREM_ENABLED (SDHC_NISTER_CREM_ENABLED_Val << SDHC_NISTER_CREM_Pos) /* (SDHC_NISTER) Enabled Position */ 738 #define SDHC_NISTER_CINT_Pos _UINT16_(8) /* (SDHC_NISTER) Card Interrupt Status Enable Position */ 739 #define SDHC_NISTER_CINT_Msk (_UINT16_(0x1) << SDHC_NISTER_CINT_Pos) /* (SDHC_NISTER) Card Interrupt Status Enable Mask */ 740 #define SDHC_NISTER_CINT(value) (SDHC_NISTER_CINT_Msk & (_UINT16_(value) << SDHC_NISTER_CINT_Pos)) /* Assigment of value for CINT in the SDHC_NISTER register */ 741 #define SDHC_NISTER_CINT_MASKED_Val _UINT16_(0x0) /* (SDHC_NISTER) Masked */ 742 #define SDHC_NISTER_CINT_ENABLED_Val _UINT16_(0x1) /* (SDHC_NISTER) Enabled */ 743 #define SDHC_NISTER_CINT_MASKED (SDHC_NISTER_CINT_MASKED_Val << SDHC_NISTER_CINT_Pos) /* (SDHC_NISTER) Masked Position */ 744 #define SDHC_NISTER_CINT_ENABLED (SDHC_NISTER_CINT_ENABLED_Val << SDHC_NISTER_CINT_Pos) /* (SDHC_NISTER) Enabled Position */ 745 #define SDHC_NISTER_Msk _UINT16_(0x01FF) /* (SDHC_NISTER) Register Mask */ 746 747 /* EMMC mode */ 748 #define SDHC_NISTER_EMMC_BOOTAR_Pos _UINT16_(14) /* (SDHC_NISTER) Boot Acknowledge Received Status Enable Position */ 749 #define SDHC_NISTER_EMMC_BOOTAR_Msk (_UINT16_(0x1) << SDHC_NISTER_EMMC_BOOTAR_Pos) /* (SDHC_NISTER) Boot Acknowledge Received Status Enable Mask */ 750 #define SDHC_NISTER_EMMC_BOOTAR(value) (SDHC_NISTER_EMMC_BOOTAR_Msk & (_UINT16_(value) << SDHC_NISTER_EMMC_BOOTAR_Pos)) 751 #define SDHC_NISTER_EMMC_Msk _UINT16_(0x4000) /* (SDHC_NISTER_EMMC) Register Mask */ 752 753 754 /* -------- SDHC_EISTER : (SDHC Offset: 0x36) (R/W 16) Error Interrupt Status Enable -------- */ 755 #define SDHC_EISTER_RESETVALUE _UINT16_(0x00) /* (SDHC_EISTER) Error Interrupt Status Enable Reset Value */ 756 757 #define SDHC_EISTER_CMDTEO_Pos _UINT16_(0) /* (SDHC_EISTER) Command Timeout Error Status Enable Position */ 758 #define SDHC_EISTER_CMDTEO_Msk (_UINT16_(0x1) << SDHC_EISTER_CMDTEO_Pos) /* (SDHC_EISTER) Command Timeout Error Status Enable Mask */ 759 #define SDHC_EISTER_CMDTEO(value) (SDHC_EISTER_CMDTEO_Msk & (_UINT16_(value) << SDHC_EISTER_CMDTEO_Pos)) /* Assigment of value for CMDTEO in the SDHC_EISTER register */ 760 #define SDHC_EISTER_CMDTEO_MASKED_Val _UINT16_(0x0) /* (SDHC_EISTER) Masked */ 761 #define SDHC_EISTER_CMDTEO_ENABLED_Val _UINT16_(0x1) /* (SDHC_EISTER) Enabled */ 762 #define SDHC_EISTER_CMDTEO_MASKED (SDHC_EISTER_CMDTEO_MASKED_Val << SDHC_EISTER_CMDTEO_Pos) /* (SDHC_EISTER) Masked Position */ 763 #define SDHC_EISTER_CMDTEO_ENABLED (SDHC_EISTER_CMDTEO_ENABLED_Val << SDHC_EISTER_CMDTEO_Pos) /* (SDHC_EISTER) Enabled Position */ 764 #define SDHC_EISTER_CMDCRC_Pos _UINT16_(1) /* (SDHC_EISTER) Command CRC Error Status Enable Position */ 765 #define SDHC_EISTER_CMDCRC_Msk (_UINT16_(0x1) << SDHC_EISTER_CMDCRC_Pos) /* (SDHC_EISTER) Command CRC Error Status Enable Mask */ 766 #define SDHC_EISTER_CMDCRC(value) (SDHC_EISTER_CMDCRC_Msk & (_UINT16_(value) << SDHC_EISTER_CMDCRC_Pos)) /* Assigment of value for CMDCRC in the SDHC_EISTER register */ 767 #define SDHC_EISTER_CMDCRC_MASKED_Val _UINT16_(0x0) /* (SDHC_EISTER) Masked */ 768 #define SDHC_EISTER_CMDCRC_ENABLED_Val _UINT16_(0x1) /* (SDHC_EISTER) Enabled */ 769 #define SDHC_EISTER_CMDCRC_MASKED (SDHC_EISTER_CMDCRC_MASKED_Val << SDHC_EISTER_CMDCRC_Pos) /* (SDHC_EISTER) Masked Position */ 770 #define SDHC_EISTER_CMDCRC_ENABLED (SDHC_EISTER_CMDCRC_ENABLED_Val << SDHC_EISTER_CMDCRC_Pos) /* (SDHC_EISTER) Enabled Position */ 771 #define SDHC_EISTER_CMDEND_Pos _UINT16_(2) /* (SDHC_EISTER) Command End Bit Error Status Enable Position */ 772 #define SDHC_EISTER_CMDEND_Msk (_UINT16_(0x1) << SDHC_EISTER_CMDEND_Pos) /* (SDHC_EISTER) Command End Bit Error Status Enable Mask */ 773 #define SDHC_EISTER_CMDEND(value) (SDHC_EISTER_CMDEND_Msk & (_UINT16_(value) << SDHC_EISTER_CMDEND_Pos)) /* Assigment of value for CMDEND in the SDHC_EISTER register */ 774 #define SDHC_EISTER_CMDEND_MASKED_Val _UINT16_(0x0) /* (SDHC_EISTER) Masked */ 775 #define SDHC_EISTER_CMDEND_ENABLED_Val _UINT16_(0x1) /* (SDHC_EISTER) Enabled */ 776 #define SDHC_EISTER_CMDEND_MASKED (SDHC_EISTER_CMDEND_MASKED_Val << SDHC_EISTER_CMDEND_Pos) /* (SDHC_EISTER) Masked Position */ 777 #define SDHC_EISTER_CMDEND_ENABLED (SDHC_EISTER_CMDEND_ENABLED_Val << SDHC_EISTER_CMDEND_Pos) /* (SDHC_EISTER) Enabled Position */ 778 #define SDHC_EISTER_CMDIDX_Pos _UINT16_(3) /* (SDHC_EISTER) Command Index Error Status Enable Position */ 779 #define SDHC_EISTER_CMDIDX_Msk (_UINT16_(0x1) << SDHC_EISTER_CMDIDX_Pos) /* (SDHC_EISTER) Command Index Error Status Enable Mask */ 780 #define SDHC_EISTER_CMDIDX(value) (SDHC_EISTER_CMDIDX_Msk & (_UINT16_(value) << SDHC_EISTER_CMDIDX_Pos)) /* Assigment of value for CMDIDX in the SDHC_EISTER register */ 781 #define SDHC_EISTER_CMDIDX_MASKED_Val _UINT16_(0x0) /* (SDHC_EISTER) Masked */ 782 #define SDHC_EISTER_CMDIDX_ENABLED_Val _UINT16_(0x1) /* (SDHC_EISTER) Enabled */ 783 #define SDHC_EISTER_CMDIDX_MASKED (SDHC_EISTER_CMDIDX_MASKED_Val << SDHC_EISTER_CMDIDX_Pos) /* (SDHC_EISTER) Masked Position */ 784 #define SDHC_EISTER_CMDIDX_ENABLED (SDHC_EISTER_CMDIDX_ENABLED_Val << SDHC_EISTER_CMDIDX_Pos) /* (SDHC_EISTER) Enabled Position */ 785 #define SDHC_EISTER_DATTEO_Pos _UINT16_(4) /* (SDHC_EISTER) Data Timeout Error Status Enable Position */ 786 #define SDHC_EISTER_DATTEO_Msk (_UINT16_(0x1) << SDHC_EISTER_DATTEO_Pos) /* (SDHC_EISTER) Data Timeout Error Status Enable Mask */ 787 #define SDHC_EISTER_DATTEO(value) (SDHC_EISTER_DATTEO_Msk & (_UINT16_(value) << SDHC_EISTER_DATTEO_Pos)) /* Assigment of value for DATTEO in the SDHC_EISTER register */ 788 #define SDHC_EISTER_DATTEO_MASKED_Val _UINT16_(0x0) /* (SDHC_EISTER) Masked */ 789 #define SDHC_EISTER_DATTEO_ENABLED_Val _UINT16_(0x1) /* (SDHC_EISTER) Enabled */ 790 #define SDHC_EISTER_DATTEO_MASKED (SDHC_EISTER_DATTEO_MASKED_Val << SDHC_EISTER_DATTEO_Pos) /* (SDHC_EISTER) Masked Position */ 791 #define SDHC_EISTER_DATTEO_ENABLED (SDHC_EISTER_DATTEO_ENABLED_Val << SDHC_EISTER_DATTEO_Pos) /* (SDHC_EISTER) Enabled Position */ 792 #define SDHC_EISTER_DATCRC_Pos _UINT16_(5) /* (SDHC_EISTER) Data CRC Error Status Enable Position */ 793 #define SDHC_EISTER_DATCRC_Msk (_UINT16_(0x1) << SDHC_EISTER_DATCRC_Pos) /* (SDHC_EISTER) Data CRC Error Status Enable Mask */ 794 #define SDHC_EISTER_DATCRC(value) (SDHC_EISTER_DATCRC_Msk & (_UINT16_(value) << SDHC_EISTER_DATCRC_Pos)) /* Assigment of value for DATCRC in the SDHC_EISTER register */ 795 #define SDHC_EISTER_DATCRC_MASKED_Val _UINT16_(0x0) /* (SDHC_EISTER) Masked */ 796 #define SDHC_EISTER_DATCRC_ENABLED_Val _UINT16_(0x1) /* (SDHC_EISTER) Enabled */ 797 #define SDHC_EISTER_DATCRC_MASKED (SDHC_EISTER_DATCRC_MASKED_Val << SDHC_EISTER_DATCRC_Pos) /* (SDHC_EISTER) Masked Position */ 798 #define SDHC_EISTER_DATCRC_ENABLED (SDHC_EISTER_DATCRC_ENABLED_Val << SDHC_EISTER_DATCRC_Pos) /* (SDHC_EISTER) Enabled Position */ 799 #define SDHC_EISTER_DATEND_Pos _UINT16_(6) /* (SDHC_EISTER) Data End Bit Error Status Enable Position */ 800 #define SDHC_EISTER_DATEND_Msk (_UINT16_(0x1) << SDHC_EISTER_DATEND_Pos) /* (SDHC_EISTER) Data End Bit Error Status Enable Mask */ 801 #define SDHC_EISTER_DATEND(value) (SDHC_EISTER_DATEND_Msk & (_UINT16_(value) << SDHC_EISTER_DATEND_Pos)) /* Assigment of value for DATEND in the SDHC_EISTER register */ 802 #define SDHC_EISTER_DATEND_MASKED_Val _UINT16_(0x0) /* (SDHC_EISTER) Masked */ 803 #define SDHC_EISTER_DATEND_ENABLED_Val _UINT16_(0x1) /* (SDHC_EISTER) Enabled */ 804 #define SDHC_EISTER_DATEND_MASKED (SDHC_EISTER_DATEND_MASKED_Val << SDHC_EISTER_DATEND_Pos) /* (SDHC_EISTER) Masked Position */ 805 #define SDHC_EISTER_DATEND_ENABLED (SDHC_EISTER_DATEND_ENABLED_Val << SDHC_EISTER_DATEND_Pos) /* (SDHC_EISTER) Enabled Position */ 806 #define SDHC_EISTER_CURLIM_Pos _UINT16_(7) /* (SDHC_EISTER) Current Limit Error Status Enable Position */ 807 #define SDHC_EISTER_CURLIM_Msk (_UINT16_(0x1) << SDHC_EISTER_CURLIM_Pos) /* (SDHC_EISTER) Current Limit Error Status Enable Mask */ 808 #define SDHC_EISTER_CURLIM(value) (SDHC_EISTER_CURLIM_Msk & (_UINT16_(value) << SDHC_EISTER_CURLIM_Pos)) /* Assigment of value for CURLIM in the SDHC_EISTER register */ 809 #define SDHC_EISTER_CURLIM_MASKED_Val _UINT16_(0x0) /* (SDHC_EISTER) Masked */ 810 #define SDHC_EISTER_CURLIM_ENABLED_Val _UINT16_(0x1) /* (SDHC_EISTER) Enabled */ 811 #define SDHC_EISTER_CURLIM_MASKED (SDHC_EISTER_CURLIM_MASKED_Val << SDHC_EISTER_CURLIM_Pos) /* (SDHC_EISTER) Masked Position */ 812 #define SDHC_EISTER_CURLIM_ENABLED (SDHC_EISTER_CURLIM_ENABLED_Val << SDHC_EISTER_CURLIM_Pos) /* (SDHC_EISTER) Enabled Position */ 813 #define SDHC_EISTER_ACMD_Pos _UINT16_(8) /* (SDHC_EISTER) Auto CMD Error Status Enable Position */ 814 #define SDHC_EISTER_ACMD_Msk (_UINT16_(0x1) << SDHC_EISTER_ACMD_Pos) /* (SDHC_EISTER) Auto CMD Error Status Enable Mask */ 815 #define SDHC_EISTER_ACMD(value) (SDHC_EISTER_ACMD_Msk & (_UINT16_(value) << SDHC_EISTER_ACMD_Pos)) /* Assigment of value for ACMD in the SDHC_EISTER register */ 816 #define SDHC_EISTER_ACMD_MASKED_Val _UINT16_(0x0) /* (SDHC_EISTER) Masked */ 817 #define SDHC_EISTER_ACMD_ENABLED_Val _UINT16_(0x1) /* (SDHC_EISTER) Enabled */ 818 #define SDHC_EISTER_ACMD_MASKED (SDHC_EISTER_ACMD_MASKED_Val << SDHC_EISTER_ACMD_Pos) /* (SDHC_EISTER) Masked Position */ 819 #define SDHC_EISTER_ACMD_ENABLED (SDHC_EISTER_ACMD_ENABLED_Val << SDHC_EISTER_ACMD_Pos) /* (SDHC_EISTER) Enabled Position */ 820 #define SDHC_EISTER_ADMA_Pos _UINT16_(9) /* (SDHC_EISTER) ADMA Error Status Enable Position */ 821 #define SDHC_EISTER_ADMA_Msk (_UINT16_(0x1) << SDHC_EISTER_ADMA_Pos) /* (SDHC_EISTER) ADMA Error Status Enable Mask */ 822 #define SDHC_EISTER_ADMA(value) (SDHC_EISTER_ADMA_Msk & (_UINT16_(value) << SDHC_EISTER_ADMA_Pos)) /* Assigment of value for ADMA in the SDHC_EISTER register */ 823 #define SDHC_EISTER_ADMA_MASKED_Val _UINT16_(0x0) /* (SDHC_EISTER) Masked */ 824 #define SDHC_EISTER_ADMA_ENABLED_Val _UINT16_(0x1) /* (SDHC_EISTER) Enabled */ 825 #define SDHC_EISTER_ADMA_MASKED (SDHC_EISTER_ADMA_MASKED_Val << SDHC_EISTER_ADMA_Pos) /* (SDHC_EISTER) Masked Position */ 826 #define SDHC_EISTER_ADMA_ENABLED (SDHC_EISTER_ADMA_ENABLED_Val << SDHC_EISTER_ADMA_Pos) /* (SDHC_EISTER) Enabled Position */ 827 #define SDHC_EISTER_Msk _UINT16_(0x03FF) /* (SDHC_EISTER) Register Mask */ 828 829 /* EMMC mode */ 830 #define SDHC_EISTER_EMMC_BOOTAE_Pos _UINT16_(12) /* (SDHC_EISTER) Boot Acknowledge Error Status Enable Position */ 831 #define SDHC_EISTER_EMMC_BOOTAE_Msk (_UINT16_(0x1) << SDHC_EISTER_EMMC_BOOTAE_Pos) /* (SDHC_EISTER) Boot Acknowledge Error Status Enable Mask */ 832 #define SDHC_EISTER_EMMC_BOOTAE(value) (SDHC_EISTER_EMMC_BOOTAE_Msk & (_UINT16_(value) << SDHC_EISTER_EMMC_BOOTAE_Pos)) 833 #define SDHC_EISTER_EMMC_Msk _UINT16_(0x1000) /* (SDHC_EISTER_EMMC) Register Mask */ 834 835 836 /* -------- SDHC_NISIER : (SDHC Offset: 0x38) (R/W 16) Normal Interrupt Signal Enable -------- */ 837 #define SDHC_NISIER_RESETVALUE _UINT16_(0x00) /* (SDHC_NISIER) Normal Interrupt Signal Enable Reset Value */ 838 839 #define SDHC_NISIER_CMDC_Pos _UINT16_(0) /* (SDHC_NISIER) Command Complete Signal Enable Position */ 840 #define SDHC_NISIER_CMDC_Msk (_UINT16_(0x1) << SDHC_NISIER_CMDC_Pos) /* (SDHC_NISIER) Command Complete Signal Enable Mask */ 841 #define SDHC_NISIER_CMDC(value) (SDHC_NISIER_CMDC_Msk & (_UINT16_(value) << SDHC_NISIER_CMDC_Pos)) /* Assigment of value for CMDC in the SDHC_NISIER register */ 842 #define SDHC_NISIER_CMDC_MASKED_Val _UINT16_(0x0) /* (SDHC_NISIER) Masked */ 843 #define SDHC_NISIER_CMDC_ENABLED_Val _UINT16_(0x1) /* (SDHC_NISIER) Enabled */ 844 #define SDHC_NISIER_CMDC_MASKED (SDHC_NISIER_CMDC_MASKED_Val << SDHC_NISIER_CMDC_Pos) /* (SDHC_NISIER) Masked Position */ 845 #define SDHC_NISIER_CMDC_ENABLED (SDHC_NISIER_CMDC_ENABLED_Val << SDHC_NISIER_CMDC_Pos) /* (SDHC_NISIER) Enabled Position */ 846 #define SDHC_NISIER_TRFC_Pos _UINT16_(1) /* (SDHC_NISIER) Transfer Complete Signal Enable Position */ 847 #define SDHC_NISIER_TRFC_Msk (_UINT16_(0x1) << SDHC_NISIER_TRFC_Pos) /* (SDHC_NISIER) Transfer Complete Signal Enable Mask */ 848 #define SDHC_NISIER_TRFC(value) (SDHC_NISIER_TRFC_Msk & (_UINT16_(value) << SDHC_NISIER_TRFC_Pos)) /* Assigment of value for TRFC in the SDHC_NISIER register */ 849 #define SDHC_NISIER_TRFC_MASKED_Val _UINT16_(0x0) /* (SDHC_NISIER) Masked */ 850 #define SDHC_NISIER_TRFC_ENABLED_Val _UINT16_(0x1) /* (SDHC_NISIER) Enabled */ 851 #define SDHC_NISIER_TRFC_MASKED (SDHC_NISIER_TRFC_MASKED_Val << SDHC_NISIER_TRFC_Pos) /* (SDHC_NISIER) Masked Position */ 852 #define SDHC_NISIER_TRFC_ENABLED (SDHC_NISIER_TRFC_ENABLED_Val << SDHC_NISIER_TRFC_Pos) /* (SDHC_NISIER) Enabled Position */ 853 #define SDHC_NISIER_BLKGE_Pos _UINT16_(2) /* (SDHC_NISIER) Block Gap Event Signal Enable Position */ 854 #define SDHC_NISIER_BLKGE_Msk (_UINT16_(0x1) << SDHC_NISIER_BLKGE_Pos) /* (SDHC_NISIER) Block Gap Event Signal Enable Mask */ 855 #define SDHC_NISIER_BLKGE(value) (SDHC_NISIER_BLKGE_Msk & (_UINT16_(value) << SDHC_NISIER_BLKGE_Pos)) /* Assigment of value for BLKGE in the SDHC_NISIER register */ 856 #define SDHC_NISIER_BLKGE_MASKED_Val _UINT16_(0x0) /* (SDHC_NISIER) Masked */ 857 #define SDHC_NISIER_BLKGE_ENABLED_Val _UINT16_(0x1) /* (SDHC_NISIER) Enabled */ 858 #define SDHC_NISIER_BLKGE_MASKED (SDHC_NISIER_BLKGE_MASKED_Val << SDHC_NISIER_BLKGE_Pos) /* (SDHC_NISIER) Masked Position */ 859 #define SDHC_NISIER_BLKGE_ENABLED (SDHC_NISIER_BLKGE_ENABLED_Val << SDHC_NISIER_BLKGE_Pos) /* (SDHC_NISIER) Enabled Position */ 860 #define SDHC_NISIER_DMAINT_Pos _UINT16_(3) /* (SDHC_NISIER) DMA Interrupt Signal Enable Position */ 861 #define SDHC_NISIER_DMAINT_Msk (_UINT16_(0x1) << SDHC_NISIER_DMAINT_Pos) /* (SDHC_NISIER) DMA Interrupt Signal Enable Mask */ 862 #define SDHC_NISIER_DMAINT(value) (SDHC_NISIER_DMAINT_Msk & (_UINT16_(value) << SDHC_NISIER_DMAINT_Pos)) /* Assigment of value for DMAINT in the SDHC_NISIER register */ 863 #define SDHC_NISIER_DMAINT_MASKED_Val _UINT16_(0x0) /* (SDHC_NISIER) Masked */ 864 #define SDHC_NISIER_DMAINT_ENABLED_Val _UINT16_(0x1) /* (SDHC_NISIER) Enabled */ 865 #define SDHC_NISIER_DMAINT_MASKED (SDHC_NISIER_DMAINT_MASKED_Val << SDHC_NISIER_DMAINT_Pos) /* (SDHC_NISIER) Masked Position */ 866 #define SDHC_NISIER_DMAINT_ENABLED (SDHC_NISIER_DMAINT_ENABLED_Val << SDHC_NISIER_DMAINT_Pos) /* (SDHC_NISIER) Enabled Position */ 867 #define SDHC_NISIER_BWRRDY_Pos _UINT16_(4) /* (SDHC_NISIER) Buffer Write Ready Signal Enable Position */ 868 #define SDHC_NISIER_BWRRDY_Msk (_UINT16_(0x1) << SDHC_NISIER_BWRRDY_Pos) /* (SDHC_NISIER) Buffer Write Ready Signal Enable Mask */ 869 #define SDHC_NISIER_BWRRDY(value) (SDHC_NISIER_BWRRDY_Msk & (_UINT16_(value) << SDHC_NISIER_BWRRDY_Pos)) /* Assigment of value for BWRRDY in the SDHC_NISIER register */ 870 #define SDHC_NISIER_BWRRDY_MASKED_Val _UINT16_(0x0) /* (SDHC_NISIER) Masked */ 871 #define SDHC_NISIER_BWRRDY_ENABLED_Val _UINT16_(0x1) /* (SDHC_NISIER) Enabled */ 872 #define SDHC_NISIER_BWRRDY_MASKED (SDHC_NISIER_BWRRDY_MASKED_Val << SDHC_NISIER_BWRRDY_Pos) /* (SDHC_NISIER) Masked Position */ 873 #define SDHC_NISIER_BWRRDY_ENABLED (SDHC_NISIER_BWRRDY_ENABLED_Val << SDHC_NISIER_BWRRDY_Pos) /* (SDHC_NISIER) Enabled Position */ 874 #define SDHC_NISIER_BRDRDY_Pos _UINT16_(5) /* (SDHC_NISIER) Buffer Read Ready Signal Enable Position */ 875 #define SDHC_NISIER_BRDRDY_Msk (_UINT16_(0x1) << SDHC_NISIER_BRDRDY_Pos) /* (SDHC_NISIER) Buffer Read Ready Signal Enable Mask */ 876 #define SDHC_NISIER_BRDRDY(value) (SDHC_NISIER_BRDRDY_Msk & (_UINT16_(value) << SDHC_NISIER_BRDRDY_Pos)) /* Assigment of value for BRDRDY in the SDHC_NISIER register */ 877 #define SDHC_NISIER_BRDRDY_MASKED_Val _UINT16_(0x0) /* (SDHC_NISIER) Masked */ 878 #define SDHC_NISIER_BRDRDY_ENABLED_Val _UINT16_(0x1) /* (SDHC_NISIER) Enabled */ 879 #define SDHC_NISIER_BRDRDY_MASKED (SDHC_NISIER_BRDRDY_MASKED_Val << SDHC_NISIER_BRDRDY_Pos) /* (SDHC_NISIER) Masked Position */ 880 #define SDHC_NISIER_BRDRDY_ENABLED (SDHC_NISIER_BRDRDY_ENABLED_Val << SDHC_NISIER_BRDRDY_Pos) /* (SDHC_NISIER) Enabled Position */ 881 #define SDHC_NISIER_CINS_Pos _UINT16_(6) /* (SDHC_NISIER) Card Insertion Signal Enable Position */ 882 #define SDHC_NISIER_CINS_Msk (_UINT16_(0x1) << SDHC_NISIER_CINS_Pos) /* (SDHC_NISIER) Card Insertion Signal Enable Mask */ 883 #define SDHC_NISIER_CINS(value) (SDHC_NISIER_CINS_Msk & (_UINT16_(value) << SDHC_NISIER_CINS_Pos)) /* Assigment of value for CINS in the SDHC_NISIER register */ 884 #define SDHC_NISIER_CINS_MASKED_Val _UINT16_(0x0) /* (SDHC_NISIER) Masked */ 885 #define SDHC_NISIER_CINS_ENABLED_Val _UINT16_(0x1) /* (SDHC_NISIER) Enabled */ 886 #define SDHC_NISIER_CINS_MASKED (SDHC_NISIER_CINS_MASKED_Val << SDHC_NISIER_CINS_Pos) /* (SDHC_NISIER) Masked Position */ 887 #define SDHC_NISIER_CINS_ENABLED (SDHC_NISIER_CINS_ENABLED_Val << SDHC_NISIER_CINS_Pos) /* (SDHC_NISIER) Enabled Position */ 888 #define SDHC_NISIER_CREM_Pos _UINT16_(7) /* (SDHC_NISIER) Card Removal Signal Enable Position */ 889 #define SDHC_NISIER_CREM_Msk (_UINT16_(0x1) << SDHC_NISIER_CREM_Pos) /* (SDHC_NISIER) Card Removal Signal Enable Mask */ 890 #define SDHC_NISIER_CREM(value) (SDHC_NISIER_CREM_Msk & (_UINT16_(value) << SDHC_NISIER_CREM_Pos)) /* Assigment of value for CREM in the SDHC_NISIER register */ 891 #define SDHC_NISIER_CREM_MASKED_Val _UINT16_(0x0) /* (SDHC_NISIER) Masked */ 892 #define SDHC_NISIER_CREM_ENABLED_Val _UINT16_(0x1) /* (SDHC_NISIER) Enabled */ 893 #define SDHC_NISIER_CREM_MASKED (SDHC_NISIER_CREM_MASKED_Val << SDHC_NISIER_CREM_Pos) /* (SDHC_NISIER) Masked Position */ 894 #define SDHC_NISIER_CREM_ENABLED (SDHC_NISIER_CREM_ENABLED_Val << SDHC_NISIER_CREM_Pos) /* (SDHC_NISIER) Enabled Position */ 895 #define SDHC_NISIER_CINT_Pos _UINT16_(8) /* (SDHC_NISIER) Card Interrupt Signal Enable Position */ 896 #define SDHC_NISIER_CINT_Msk (_UINT16_(0x1) << SDHC_NISIER_CINT_Pos) /* (SDHC_NISIER) Card Interrupt Signal Enable Mask */ 897 #define SDHC_NISIER_CINT(value) (SDHC_NISIER_CINT_Msk & (_UINT16_(value) << SDHC_NISIER_CINT_Pos)) /* Assigment of value for CINT in the SDHC_NISIER register */ 898 #define SDHC_NISIER_CINT_MASKED_Val _UINT16_(0x0) /* (SDHC_NISIER) Masked */ 899 #define SDHC_NISIER_CINT_ENABLED_Val _UINT16_(0x1) /* (SDHC_NISIER) Enabled */ 900 #define SDHC_NISIER_CINT_MASKED (SDHC_NISIER_CINT_MASKED_Val << SDHC_NISIER_CINT_Pos) /* (SDHC_NISIER) Masked Position */ 901 #define SDHC_NISIER_CINT_ENABLED (SDHC_NISIER_CINT_ENABLED_Val << SDHC_NISIER_CINT_Pos) /* (SDHC_NISIER) Enabled Position */ 902 #define SDHC_NISIER_Msk _UINT16_(0x01FF) /* (SDHC_NISIER) Register Mask */ 903 904 /* EMMC mode */ 905 #define SDHC_NISIER_EMMC_BOOTAR_Pos _UINT16_(14) /* (SDHC_NISIER) Boot Acknowledge Received Signal Enable Position */ 906 #define SDHC_NISIER_EMMC_BOOTAR_Msk (_UINT16_(0x1) << SDHC_NISIER_EMMC_BOOTAR_Pos) /* (SDHC_NISIER) Boot Acknowledge Received Signal Enable Mask */ 907 #define SDHC_NISIER_EMMC_BOOTAR(value) (SDHC_NISIER_EMMC_BOOTAR_Msk & (_UINT16_(value) << SDHC_NISIER_EMMC_BOOTAR_Pos)) 908 #define SDHC_NISIER_EMMC_Msk _UINT16_(0x4000) /* (SDHC_NISIER_EMMC) Register Mask */ 909 910 911 /* -------- SDHC_EISIER : (SDHC Offset: 0x3A) (R/W 16) Error Interrupt Signal Enable -------- */ 912 #define SDHC_EISIER_RESETVALUE _UINT16_(0x00) /* (SDHC_EISIER) Error Interrupt Signal Enable Reset Value */ 913 914 #define SDHC_EISIER_CMDTEO_Pos _UINT16_(0) /* (SDHC_EISIER) Command Timeout Error Signal Enable Position */ 915 #define SDHC_EISIER_CMDTEO_Msk (_UINT16_(0x1) << SDHC_EISIER_CMDTEO_Pos) /* (SDHC_EISIER) Command Timeout Error Signal Enable Mask */ 916 #define SDHC_EISIER_CMDTEO(value) (SDHC_EISIER_CMDTEO_Msk & (_UINT16_(value) << SDHC_EISIER_CMDTEO_Pos)) /* Assigment of value for CMDTEO in the SDHC_EISIER register */ 917 #define SDHC_EISIER_CMDTEO_MASKED_Val _UINT16_(0x0) /* (SDHC_EISIER) Masked */ 918 #define SDHC_EISIER_CMDTEO_ENABLED_Val _UINT16_(0x1) /* (SDHC_EISIER) Enabled */ 919 #define SDHC_EISIER_CMDTEO_MASKED (SDHC_EISIER_CMDTEO_MASKED_Val << SDHC_EISIER_CMDTEO_Pos) /* (SDHC_EISIER) Masked Position */ 920 #define SDHC_EISIER_CMDTEO_ENABLED (SDHC_EISIER_CMDTEO_ENABLED_Val << SDHC_EISIER_CMDTEO_Pos) /* (SDHC_EISIER) Enabled Position */ 921 #define SDHC_EISIER_CMDCRC_Pos _UINT16_(1) /* (SDHC_EISIER) Command CRC Error Signal Enable Position */ 922 #define SDHC_EISIER_CMDCRC_Msk (_UINT16_(0x1) << SDHC_EISIER_CMDCRC_Pos) /* (SDHC_EISIER) Command CRC Error Signal Enable Mask */ 923 #define SDHC_EISIER_CMDCRC(value) (SDHC_EISIER_CMDCRC_Msk & (_UINT16_(value) << SDHC_EISIER_CMDCRC_Pos)) /* Assigment of value for CMDCRC in the SDHC_EISIER register */ 924 #define SDHC_EISIER_CMDCRC_MASKED_Val _UINT16_(0x0) /* (SDHC_EISIER) Masked */ 925 #define SDHC_EISIER_CMDCRC_ENABLED_Val _UINT16_(0x1) /* (SDHC_EISIER) Enabled */ 926 #define SDHC_EISIER_CMDCRC_MASKED (SDHC_EISIER_CMDCRC_MASKED_Val << SDHC_EISIER_CMDCRC_Pos) /* (SDHC_EISIER) Masked Position */ 927 #define SDHC_EISIER_CMDCRC_ENABLED (SDHC_EISIER_CMDCRC_ENABLED_Val << SDHC_EISIER_CMDCRC_Pos) /* (SDHC_EISIER) Enabled Position */ 928 #define SDHC_EISIER_CMDEND_Pos _UINT16_(2) /* (SDHC_EISIER) Command End Bit Error Signal Enable Position */ 929 #define SDHC_EISIER_CMDEND_Msk (_UINT16_(0x1) << SDHC_EISIER_CMDEND_Pos) /* (SDHC_EISIER) Command End Bit Error Signal Enable Mask */ 930 #define SDHC_EISIER_CMDEND(value) (SDHC_EISIER_CMDEND_Msk & (_UINT16_(value) << SDHC_EISIER_CMDEND_Pos)) /* Assigment of value for CMDEND in the SDHC_EISIER register */ 931 #define SDHC_EISIER_CMDEND_MASKED_Val _UINT16_(0x0) /* (SDHC_EISIER) Masked */ 932 #define SDHC_EISIER_CMDEND_ENABLED_Val _UINT16_(0x1) /* (SDHC_EISIER) Enabled */ 933 #define SDHC_EISIER_CMDEND_MASKED (SDHC_EISIER_CMDEND_MASKED_Val << SDHC_EISIER_CMDEND_Pos) /* (SDHC_EISIER) Masked Position */ 934 #define SDHC_EISIER_CMDEND_ENABLED (SDHC_EISIER_CMDEND_ENABLED_Val << SDHC_EISIER_CMDEND_Pos) /* (SDHC_EISIER) Enabled Position */ 935 #define SDHC_EISIER_CMDIDX_Pos _UINT16_(3) /* (SDHC_EISIER) Command Index Error Signal Enable Position */ 936 #define SDHC_EISIER_CMDIDX_Msk (_UINT16_(0x1) << SDHC_EISIER_CMDIDX_Pos) /* (SDHC_EISIER) Command Index Error Signal Enable Mask */ 937 #define SDHC_EISIER_CMDIDX(value) (SDHC_EISIER_CMDIDX_Msk & (_UINT16_(value) << SDHC_EISIER_CMDIDX_Pos)) /* Assigment of value for CMDIDX in the SDHC_EISIER register */ 938 #define SDHC_EISIER_CMDIDX_MASKED_Val _UINT16_(0x0) /* (SDHC_EISIER) Masked */ 939 #define SDHC_EISIER_CMDIDX_ENABLED_Val _UINT16_(0x1) /* (SDHC_EISIER) Enabled */ 940 #define SDHC_EISIER_CMDIDX_MASKED (SDHC_EISIER_CMDIDX_MASKED_Val << SDHC_EISIER_CMDIDX_Pos) /* (SDHC_EISIER) Masked Position */ 941 #define SDHC_EISIER_CMDIDX_ENABLED (SDHC_EISIER_CMDIDX_ENABLED_Val << SDHC_EISIER_CMDIDX_Pos) /* (SDHC_EISIER) Enabled Position */ 942 #define SDHC_EISIER_DATTEO_Pos _UINT16_(4) /* (SDHC_EISIER) Data Timeout Error Signal Enable Position */ 943 #define SDHC_EISIER_DATTEO_Msk (_UINT16_(0x1) << SDHC_EISIER_DATTEO_Pos) /* (SDHC_EISIER) Data Timeout Error Signal Enable Mask */ 944 #define SDHC_EISIER_DATTEO(value) (SDHC_EISIER_DATTEO_Msk & (_UINT16_(value) << SDHC_EISIER_DATTEO_Pos)) /* Assigment of value for DATTEO in the SDHC_EISIER register */ 945 #define SDHC_EISIER_DATTEO_MASKED_Val _UINT16_(0x0) /* (SDHC_EISIER) Masked */ 946 #define SDHC_EISIER_DATTEO_ENABLED_Val _UINT16_(0x1) /* (SDHC_EISIER) Enabled */ 947 #define SDHC_EISIER_DATTEO_MASKED (SDHC_EISIER_DATTEO_MASKED_Val << SDHC_EISIER_DATTEO_Pos) /* (SDHC_EISIER) Masked Position */ 948 #define SDHC_EISIER_DATTEO_ENABLED (SDHC_EISIER_DATTEO_ENABLED_Val << SDHC_EISIER_DATTEO_Pos) /* (SDHC_EISIER) Enabled Position */ 949 #define SDHC_EISIER_DATCRC_Pos _UINT16_(5) /* (SDHC_EISIER) Data CRC Error Signal Enable Position */ 950 #define SDHC_EISIER_DATCRC_Msk (_UINT16_(0x1) << SDHC_EISIER_DATCRC_Pos) /* (SDHC_EISIER) Data CRC Error Signal Enable Mask */ 951 #define SDHC_EISIER_DATCRC(value) (SDHC_EISIER_DATCRC_Msk & (_UINT16_(value) << SDHC_EISIER_DATCRC_Pos)) /* Assigment of value for DATCRC in the SDHC_EISIER register */ 952 #define SDHC_EISIER_DATCRC_MASKED_Val _UINT16_(0x0) /* (SDHC_EISIER) Masked */ 953 #define SDHC_EISIER_DATCRC_ENABLED_Val _UINT16_(0x1) /* (SDHC_EISIER) Enabled */ 954 #define SDHC_EISIER_DATCRC_MASKED (SDHC_EISIER_DATCRC_MASKED_Val << SDHC_EISIER_DATCRC_Pos) /* (SDHC_EISIER) Masked Position */ 955 #define SDHC_EISIER_DATCRC_ENABLED (SDHC_EISIER_DATCRC_ENABLED_Val << SDHC_EISIER_DATCRC_Pos) /* (SDHC_EISIER) Enabled Position */ 956 #define SDHC_EISIER_DATEND_Pos _UINT16_(6) /* (SDHC_EISIER) Data End Bit Error Signal Enable Position */ 957 #define SDHC_EISIER_DATEND_Msk (_UINT16_(0x1) << SDHC_EISIER_DATEND_Pos) /* (SDHC_EISIER) Data End Bit Error Signal Enable Mask */ 958 #define SDHC_EISIER_DATEND(value) (SDHC_EISIER_DATEND_Msk & (_UINT16_(value) << SDHC_EISIER_DATEND_Pos)) /* Assigment of value for DATEND in the SDHC_EISIER register */ 959 #define SDHC_EISIER_DATEND_MASKED_Val _UINT16_(0x0) /* (SDHC_EISIER) Masked */ 960 #define SDHC_EISIER_DATEND_ENABLED_Val _UINT16_(0x1) /* (SDHC_EISIER) Enabled */ 961 #define SDHC_EISIER_DATEND_MASKED (SDHC_EISIER_DATEND_MASKED_Val << SDHC_EISIER_DATEND_Pos) /* (SDHC_EISIER) Masked Position */ 962 #define SDHC_EISIER_DATEND_ENABLED (SDHC_EISIER_DATEND_ENABLED_Val << SDHC_EISIER_DATEND_Pos) /* (SDHC_EISIER) Enabled Position */ 963 #define SDHC_EISIER_CURLIM_Pos _UINT16_(7) /* (SDHC_EISIER) Current Limit Error Signal Enable Position */ 964 #define SDHC_EISIER_CURLIM_Msk (_UINT16_(0x1) << SDHC_EISIER_CURLIM_Pos) /* (SDHC_EISIER) Current Limit Error Signal Enable Mask */ 965 #define SDHC_EISIER_CURLIM(value) (SDHC_EISIER_CURLIM_Msk & (_UINT16_(value) << SDHC_EISIER_CURLIM_Pos)) /* Assigment of value for CURLIM in the SDHC_EISIER register */ 966 #define SDHC_EISIER_CURLIM_MASKED_Val _UINT16_(0x0) /* (SDHC_EISIER) Masked */ 967 #define SDHC_EISIER_CURLIM_ENABLED_Val _UINT16_(0x1) /* (SDHC_EISIER) Enabled */ 968 #define SDHC_EISIER_CURLIM_MASKED (SDHC_EISIER_CURLIM_MASKED_Val << SDHC_EISIER_CURLIM_Pos) /* (SDHC_EISIER) Masked Position */ 969 #define SDHC_EISIER_CURLIM_ENABLED (SDHC_EISIER_CURLIM_ENABLED_Val << SDHC_EISIER_CURLIM_Pos) /* (SDHC_EISIER) Enabled Position */ 970 #define SDHC_EISIER_ACMD_Pos _UINT16_(8) /* (SDHC_EISIER) Auto CMD Error Signal Enable Position */ 971 #define SDHC_EISIER_ACMD_Msk (_UINT16_(0x1) << SDHC_EISIER_ACMD_Pos) /* (SDHC_EISIER) Auto CMD Error Signal Enable Mask */ 972 #define SDHC_EISIER_ACMD(value) (SDHC_EISIER_ACMD_Msk & (_UINT16_(value) << SDHC_EISIER_ACMD_Pos)) /* Assigment of value for ACMD in the SDHC_EISIER register */ 973 #define SDHC_EISIER_ACMD_MASKED_Val _UINT16_(0x0) /* (SDHC_EISIER) Masked */ 974 #define SDHC_EISIER_ACMD_ENABLED_Val _UINT16_(0x1) /* (SDHC_EISIER) Enabled */ 975 #define SDHC_EISIER_ACMD_MASKED (SDHC_EISIER_ACMD_MASKED_Val << SDHC_EISIER_ACMD_Pos) /* (SDHC_EISIER) Masked Position */ 976 #define SDHC_EISIER_ACMD_ENABLED (SDHC_EISIER_ACMD_ENABLED_Val << SDHC_EISIER_ACMD_Pos) /* (SDHC_EISIER) Enabled Position */ 977 #define SDHC_EISIER_ADMA_Pos _UINT16_(9) /* (SDHC_EISIER) ADMA Error Signal Enable Position */ 978 #define SDHC_EISIER_ADMA_Msk (_UINT16_(0x1) << SDHC_EISIER_ADMA_Pos) /* (SDHC_EISIER) ADMA Error Signal Enable Mask */ 979 #define SDHC_EISIER_ADMA(value) (SDHC_EISIER_ADMA_Msk & (_UINT16_(value) << SDHC_EISIER_ADMA_Pos)) /* Assigment of value for ADMA in the SDHC_EISIER register */ 980 #define SDHC_EISIER_ADMA_MASKED_Val _UINT16_(0x0) /* (SDHC_EISIER) Masked */ 981 #define SDHC_EISIER_ADMA_ENABLED_Val _UINT16_(0x1) /* (SDHC_EISIER) Enabled */ 982 #define SDHC_EISIER_ADMA_MASKED (SDHC_EISIER_ADMA_MASKED_Val << SDHC_EISIER_ADMA_Pos) /* (SDHC_EISIER) Masked Position */ 983 #define SDHC_EISIER_ADMA_ENABLED (SDHC_EISIER_ADMA_ENABLED_Val << SDHC_EISIER_ADMA_Pos) /* (SDHC_EISIER) Enabled Position */ 984 #define SDHC_EISIER_Msk _UINT16_(0x03FF) /* (SDHC_EISIER) Register Mask */ 985 986 /* EMMC mode */ 987 #define SDHC_EISIER_EMMC_BOOTAE_Pos _UINT16_(12) /* (SDHC_EISIER) Boot Acknowledge Error Signal Enable Position */ 988 #define SDHC_EISIER_EMMC_BOOTAE_Msk (_UINT16_(0x1) << SDHC_EISIER_EMMC_BOOTAE_Pos) /* (SDHC_EISIER) Boot Acknowledge Error Signal Enable Mask */ 989 #define SDHC_EISIER_EMMC_BOOTAE(value) (SDHC_EISIER_EMMC_BOOTAE_Msk & (_UINT16_(value) << SDHC_EISIER_EMMC_BOOTAE_Pos)) 990 #define SDHC_EISIER_EMMC_Msk _UINT16_(0x1000) /* (SDHC_EISIER_EMMC) Register Mask */ 991 992 993 /* -------- SDHC_ACESR : (SDHC Offset: 0x3C) ( R/ 16) Auto CMD Error Status -------- */ 994 #define SDHC_ACESR_RESETVALUE _UINT16_(0x00) /* (SDHC_ACESR) Auto CMD Error Status Reset Value */ 995 996 #define SDHC_ACESR_ACMD12NE_Pos _UINT16_(0) /* (SDHC_ACESR) Auto CMD12 Not Executed Position */ 997 #define SDHC_ACESR_ACMD12NE_Msk (_UINT16_(0x1) << SDHC_ACESR_ACMD12NE_Pos) /* (SDHC_ACESR) Auto CMD12 Not Executed Mask */ 998 #define SDHC_ACESR_ACMD12NE(value) (SDHC_ACESR_ACMD12NE_Msk & (_UINT16_(value) << SDHC_ACESR_ACMD12NE_Pos)) /* Assigment of value for ACMD12NE in the SDHC_ACESR register */ 999 #define SDHC_ACESR_ACMD12NE_EXEC_Val _UINT16_(0x0) /* (SDHC_ACESR) Executed */ 1000 #define SDHC_ACESR_ACMD12NE_NOT_EXEC_Val _UINT16_(0x1) /* (SDHC_ACESR) Not executed */ 1001 #define SDHC_ACESR_ACMD12NE_EXEC (SDHC_ACESR_ACMD12NE_EXEC_Val << SDHC_ACESR_ACMD12NE_Pos) /* (SDHC_ACESR) Executed Position */ 1002 #define SDHC_ACESR_ACMD12NE_NOT_EXEC (SDHC_ACESR_ACMD12NE_NOT_EXEC_Val << SDHC_ACESR_ACMD12NE_Pos) /* (SDHC_ACESR) Not executed Position */ 1003 #define SDHC_ACESR_ACMDTEO_Pos _UINT16_(1) /* (SDHC_ACESR) Auto CMD Timeout Error Position */ 1004 #define SDHC_ACESR_ACMDTEO_Msk (_UINT16_(0x1) << SDHC_ACESR_ACMDTEO_Pos) /* (SDHC_ACESR) Auto CMD Timeout Error Mask */ 1005 #define SDHC_ACESR_ACMDTEO(value) (SDHC_ACESR_ACMDTEO_Msk & (_UINT16_(value) << SDHC_ACESR_ACMDTEO_Pos)) /* Assigment of value for ACMDTEO in the SDHC_ACESR register */ 1006 #define SDHC_ACESR_ACMDTEO_NO_Val _UINT16_(0x0) /* (SDHC_ACESR) No error */ 1007 #define SDHC_ACESR_ACMDTEO_YES_Val _UINT16_(0x1) /* (SDHC_ACESR) Timeout */ 1008 #define SDHC_ACESR_ACMDTEO_NO (SDHC_ACESR_ACMDTEO_NO_Val << SDHC_ACESR_ACMDTEO_Pos) /* (SDHC_ACESR) No error Position */ 1009 #define SDHC_ACESR_ACMDTEO_YES (SDHC_ACESR_ACMDTEO_YES_Val << SDHC_ACESR_ACMDTEO_Pos) /* (SDHC_ACESR) Timeout Position */ 1010 #define SDHC_ACESR_ACMDCRC_Pos _UINT16_(2) /* (SDHC_ACESR) Auto CMD CRC Error Position */ 1011 #define SDHC_ACESR_ACMDCRC_Msk (_UINT16_(0x1) << SDHC_ACESR_ACMDCRC_Pos) /* (SDHC_ACESR) Auto CMD CRC Error Mask */ 1012 #define SDHC_ACESR_ACMDCRC(value) (SDHC_ACESR_ACMDCRC_Msk & (_UINT16_(value) << SDHC_ACESR_ACMDCRC_Pos)) /* Assigment of value for ACMDCRC in the SDHC_ACESR register */ 1013 #define SDHC_ACESR_ACMDCRC_NO_Val _UINT16_(0x0) /* (SDHC_ACESR) No error */ 1014 #define SDHC_ACESR_ACMDCRC_YES_Val _UINT16_(0x1) /* (SDHC_ACESR) CRC Error Generated */ 1015 #define SDHC_ACESR_ACMDCRC_NO (SDHC_ACESR_ACMDCRC_NO_Val << SDHC_ACESR_ACMDCRC_Pos) /* (SDHC_ACESR) No error Position */ 1016 #define SDHC_ACESR_ACMDCRC_YES (SDHC_ACESR_ACMDCRC_YES_Val << SDHC_ACESR_ACMDCRC_Pos) /* (SDHC_ACESR) CRC Error Generated Position */ 1017 #define SDHC_ACESR_ACMDEND_Pos _UINT16_(3) /* (SDHC_ACESR) Auto CMD End Bit Error Position */ 1018 #define SDHC_ACESR_ACMDEND_Msk (_UINT16_(0x1) << SDHC_ACESR_ACMDEND_Pos) /* (SDHC_ACESR) Auto CMD End Bit Error Mask */ 1019 #define SDHC_ACESR_ACMDEND(value) (SDHC_ACESR_ACMDEND_Msk & (_UINT16_(value) << SDHC_ACESR_ACMDEND_Pos)) /* Assigment of value for ACMDEND in the SDHC_ACESR register */ 1020 #define SDHC_ACESR_ACMDEND_NO_Val _UINT16_(0x0) /* (SDHC_ACESR) No error */ 1021 #define SDHC_ACESR_ACMDEND_YES_Val _UINT16_(0x1) /* (SDHC_ACESR) End Bit Error Generated */ 1022 #define SDHC_ACESR_ACMDEND_NO (SDHC_ACESR_ACMDEND_NO_Val << SDHC_ACESR_ACMDEND_Pos) /* (SDHC_ACESR) No error Position */ 1023 #define SDHC_ACESR_ACMDEND_YES (SDHC_ACESR_ACMDEND_YES_Val << SDHC_ACESR_ACMDEND_Pos) /* (SDHC_ACESR) End Bit Error Generated Position */ 1024 #define SDHC_ACESR_ACMDIDX_Pos _UINT16_(4) /* (SDHC_ACESR) Auto CMD Index Error Position */ 1025 #define SDHC_ACESR_ACMDIDX_Msk (_UINT16_(0x1) << SDHC_ACESR_ACMDIDX_Pos) /* (SDHC_ACESR) Auto CMD Index Error Mask */ 1026 #define SDHC_ACESR_ACMDIDX(value) (SDHC_ACESR_ACMDIDX_Msk & (_UINT16_(value) << SDHC_ACESR_ACMDIDX_Pos)) /* Assigment of value for ACMDIDX in the SDHC_ACESR register */ 1027 #define SDHC_ACESR_ACMDIDX_NO_Val _UINT16_(0x0) /* (SDHC_ACESR) No error */ 1028 #define SDHC_ACESR_ACMDIDX_YES_Val _UINT16_(0x1) /* (SDHC_ACESR) Error */ 1029 #define SDHC_ACESR_ACMDIDX_NO (SDHC_ACESR_ACMDIDX_NO_Val << SDHC_ACESR_ACMDIDX_Pos) /* (SDHC_ACESR) No error Position */ 1030 #define SDHC_ACESR_ACMDIDX_YES (SDHC_ACESR_ACMDIDX_YES_Val << SDHC_ACESR_ACMDIDX_Pos) /* (SDHC_ACESR) Error Position */ 1031 #define SDHC_ACESR_CMDNI_Pos _UINT16_(7) /* (SDHC_ACESR) Command not Issued By Auto CMD12 Error Position */ 1032 #define SDHC_ACESR_CMDNI_Msk (_UINT16_(0x1) << SDHC_ACESR_CMDNI_Pos) /* (SDHC_ACESR) Command not Issued By Auto CMD12 Error Mask */ 1033 #define SDHC_ACESR_CMDNI(value) (SDHC_ACESR_CMDNI_Msk & (_UINT16_(value) << SDHC_ACESR_CMDNI_Pos)) /* Assigment of value for CMDNI in the SDHC_ACESR register */ 1034 #define SDHC_ACESR_CMDNI_OK_Val _UINT16_(0x0) /* (SDHC_ACESR) No error */ 1035 #define SDHC_ACESR_CMDNI_NOT_ISSUED_Val _UINT16_(0x1) /* (SDHC_ACESR) Not Issued */ 1036 #define SDHC_ACESR_CMDNI_OK (SDHC_ACESR_CMDNI_OK_Val << SDHC_ACESR_CMDNI_Pos) /* (SDHC_ACESR) No error Position */ 1037 #define SDHC_ACESR_CMDNI_NOT_ISSUED (SDHC_ACESR_CMDNI_NOT_ISSUED_Val << SDHC_ACESR_CMDNI_Pos) /* (SDHC_ACESR) Not Issued Position */ 1038 #define SDHC_ACESR_Msk _UINT16_(0x009F) /* (SDHC_ACESR) Register Mask */ 1039 1040 1041 /* -------- SDHC_HC2R : (SDHC Offset: 0x3E) (R/W 16) Host Control 2 -------- */ 1042 #define SDHC_HC2R_RESETVALUE _UINT16_(0x00) /* (SDHC_HC2R) Host Control 2 Reset Value */ 1043 1044 #define SDHC_HC2R_UHSMS_Pos _UINT16_(0) /* (SDHC_HC2R) UHS Mode Select Position */ 1045 #define SDHC_HC2R_UHSMS_Msk (_UINT16_(0x7) << SDHC_HC2R_UHSMS_Pos) /* (SDHC_HC2R) UHS Mode Select Mask */ 1046 #define SDHC_HC2R_UHSMS(value) (SDHC_HC2R_UHSMS_Msk & (_UINT16_(value) << SDHC_HC2R_UHSMS_Pos)) /* Assigment of value for UHSMS in the SDHC_HC2R register */ 1047 #define SDHC_HC2R_UHSMS_SDR12_Val _UINT16_(0x0) /* (SDHC_HC2R) SDR12 */ 1048 #define SDHC_HC2R_UHSMS_SDR25_Val _UINT16_(0x1) /* (SDHC_HC2R) SDR25 */ 1049 #define SDHC_HC2R_UHSMS_SDR50_Val _UINT16_(0x2) /* (SDHC_HC2R) SDR50 */ 1050 #define SDHC_HC2R_UHSMS_SDR104_Val _UINT16_(0x3) /* (SDHC_HC2R) SDR104 */ 1051 #define SDHC_HC2R_UHSMS_DDR50_Val _UINT16_(0x4) /* (SDHC_HC2R) DDR50 */ 1052 #define SDHC_HC2R_UHSMS_SDR12 (SDHC_HC2R_UHSMS_SDR12_Val << SDHC_HC2R_UHSMS_Pos) /* (SDHC_HC2R) SDR12 Position */ 1053 #define SDHC_HC2R_UHSMS_SDR25 (SDHC_HC2R_UHSMS_SDR25_Val << SDHC_HC2R_UHSMS_Pos) /* (SDHC_HC2R) SDR25 Position */ 1054 #define SDHC_HC2R_UHSMS_SDR50 (SDHC_HC2R_UHSMS_SDR50_Val << SDHC_HC2R_UHSMS_Pos) /* (SDHC_HC2R) SDR50 Position */ 1055 #define SDHC_HC2R_UHSMS_SDR104 (SDHC_HC2R_UHSMS_SDR104_Val << SDHC_HC2R_UHSMS_Pos) /* (SDHC_HC2R) SDR104 Position */ 1056 #define SDHC_HC2R_UHSMS_DDR50 (SDHC_HC2R_UHSMS_DDR50_Val << SDHC_HC2R_UHSMS_Pos) /* (SDHC_HC2R) DDR50 Position */ 1057 #define SDHC_HC2R_VS18EN_Pos _UINT16_(3) /* (SDHC_HC2R) 1.8V Signaling Enable Position */ 1058 #define SDHC_HC2R_VS18EN_Msk (_UINT16_(0x1) << SDHC_HC2R_VS18EN_Pos) /* (SDHC_HC2R) 1.8V Signaling Enable Mask */ 1059 #define SDHC_HC2R_VS18EN(value) (SDHC_HC2R_VS18EN_Msk & (_UINT16_(value) << SDHC_HC2R_VS18EN_Pos)) /* Assigment of value for VS18EN in the SDHC_HC2R register */ 1060 #define SDHC_HC2R_VS18EN_S33V_Val _UINT16_(0x0) /* (SDHC_HC2R) 3.3V Signaling */ 1061 #define SDHC_HC2R_VS18EN_S18V_Val _UINT16_(0x1) /* (SDHC_HC2R) 1.8V Signaling */ 1062 #define SDHC_HC2R_VS18EN_S33V (SDHC_HC2R_VS18EN_S33V_Val << SDHC_HC2R_VS18EN_Pos) /* (SDHC_HC2R) 3.3V Signaling Position */ 1063 #define SDHC_HC2R_VS18EN_S18V (SDHC_HC2R_VS18EN_S18V_Val << SDHC_HC2R_VS18EN_Pos) /* (SDHC_HC2R) 1.8V Signaling Position */ 1064 #define SDHC_HC2R_DRVSEL_Pos _UINT16_(4) /* (SDHC_HC2R) Driver Strength Select Position */ 1065 #define SDHC_HC2R_DRVSEL_Msk (_UINT16_(0x3) << SDHC_HC2R_DRVSEL_Pos) /* (SDHC_HC2R) Driver Strength Select Mask */ 1066 #define SDHC_HC2R_DRVSEL(value) (SDHC_HC2R_DRVSEL_Msk & (_UINT16_(value) << SDHC_HC2R_DRVSEL_Pos)) /* Assigment of value for DRVSEL in the SDHC_HC2R register */ 1067 #define SDHC_HC2R_DRVSEL_B_Val _UINT16_(0x0) /* (SDHC_HC2R) Driver Type B is Selected (Default) */ 1068 #define SDHC_HC2R_DRVSEL_A_Val _UINT16_(0x1) /* (SDHC_HC2R) Driver Type A is Selected */ 1069 #define SDHC_HC2R_DRVSEL_C_Val _UINT16_(0x2) /* (SDHC_HC2R) Driver Type C is Selected */ 1070 #define SDHC_HC2R_DRVSEL_D_Val _UINT16_(0x3) /* (SDHC_HC2R) Driver Type D is Selected */ 1071 #define SDHC_HC2R_DRVSEL_B (SDHC_HC2R_DRVSEL_B_Val << SDHC_HC2R_DRVSEL_Pos) /* (SDHC_HC2R) Driver Type B is Selected (Default) Position */ 1072 #define SDHC_HC2R_DRVSEL_A (SDHC_HC2R_DRVSEL_A_Val << SDHC_HC2R_DRVSEL_Pos) /* (SDHC_HC2R) Driver Type A is Selected Position */ 1073 #define SDHC_HC2R_DRVSEL_C (SDHC_HC2R_DRVSEL_C_Val << SDHC_HC2R_DRVSEL_Pos) /* (SDHC_HC2R) Driver Type C is Selected Position */ 1074 #define SDHC_HC2R_DRVSEL_D (SDHC_HC2R_DRVSEL_D_Val << SDHC_HC2R_DRVSEL_Pos) /* (SDHC_HC2R) Driver Type D is Selected Position */ 1075 #define SDHC_HC2R_EXTUN_Pos _UINT16_(6) /* (SDHC_HC2R) Execute Tuning Position */ 1076 #define SDHC_HC2R_EXTUN_Msk (_UINT16_(0x1) << SDHC_HC2R_EXTUN_Pos) /* (SDHC_HC2R) Execute Tuning Mask */ 1077 #define SDHC_HC2R_EXTUN(value) (SDHC_HC2R_EXTUN_Msk & (_UINT16_(value) << SDHC_HC2R_EXTUN_Pos)) /* Assigment of value for EXTUN in the SDHC_HC2R register */ 1078 #define SDHC_HC2R_EXTUN_NO_Val _UINT16_(0x0) /* (SDHC_HC2R) Not Tuned or Tuning Completed */ 1079 #define SDHC_HC2R_EXTUN_REQUESTED_Val _UINT16_(0x1) /* (SDHC_HC2R) Execute Tuning */ 1080 #define SDHC_HC2R_EXTUN_NO (SDHC_HC2R_EXTUN_NO_Val << SDHC_HC2R_EXTUN_Pos) /* (SDHC_HC2R) Not Tuned or Tuning Completed Position */ 1081 #define SDHC_HC2R_EXTUN_REQUESTED (SDHC_HC2R_EXTUN_REQUESTED_Val << SDHC_HC2R_EXTUN_Pos) /* (SDHC_HC2R) Execute Tuning Position */ 1082 #define SDHC_HC2R_SLCKSEL_Pos _UINT16_(7) /* (SDHC_HC2R) Sampling Clock Select Position */ 1083 #define SDHC_HC2R_SLCKSEL_Msk (_UINT16_(0x1) << SDHC_HC2R_SLCKSEL_Pos) /* (SDHC_HC2R) Sampling Clock Select Mask */ 1084 #define SDHC_HC2R_SLCKSEL(value) (SDHC_HC2R_SLCKSEL_Msk & (_UINT16_(value) << SDHC_HC2R_SLCKSEL_Pos)) /* Assigment of value for SLCKSEL in the SDHC_HC2R register */ 1085 #define SDHC_HC2R_SLCKSEL_FIXED_Val _UINT16_(0x0) /* (SDHC_HC2R) Fixed clock is used to sample data */ 1086 #define SDHC_HC2R_SLCKSEL_TUNED_Val _UINT16_(0x1) /* (SDHC_HC2R) Tuned clock is used to sample data */ 1087 #define SDHC_HC2R_SLCKSEL_FIXED (SDHC_HC2R_SLCKSEL_FIXED_Val << SDHC_HC2R_SLCKSEL_Pos) /* (SDHC_HC2R) Fixed clock is used to sample data Position */ 1088 #define SDHC_HC2R_SLCKSEL_TUNED (SDHC_HC2R_SLCKSEL_TUNED_Val << SDHC_HC2R_SLCKSEL_Pos) /* (SDHC_HC2R) Tuned clock is used to sample data Position */ 1089 #define SDHC_HC2R_ASINTEN_Pos _UINT16_(14) /* (SDHC_HC2R) Asynchronous Interrupt Enable Position */ 1090 #define SDHC_HC2R_ASINTEN_Msk (_UINT16_(0x1) << SDHC_HC2R_ASINTEN_Pos) /* (SDHC_HC2R) Asynchronous Interrupt Enable Mask */ 1091 #define SDHC_HC2R_ASINTEN(value) (SDHC_HC2R_ASINTEN_Msk & (_UINT16_(value) << SDHC_HC2R_ASINTEN_Pos)) /* Assigment of value for ASINTEN in the SDHC_HC2R register */ 1092 #define SDHC_HC2R_ASINTEN_DISABLED_Val _UINT16_(0x0) /* (SDHC_HC2R) Disabled */ 1093 #define SDHC_HC2R_ASINTEN_ENABLED_Val _UINT16_(0x1) /* (SDHC_HC2R) Enabled */ 1094 #define SDHC_HC2R_ASINTEN_DISABLED (SDHC_HC2R_ASINTEN_DISABLED_Val << SDHC_HC2R_ASINTEN_Pos) /* (SDHC_HC2R) Disabled Position */ 1095 #define SDHC_HC2R_ASINTEN_ENABLED (SDHC_HC2R_ASINTEN_ENABLED_Val << SDHC_HC2R_ASINTEN_Pos) /* (SDHC_HC2R) Enabled Position */ 1096 #define SDHC_HC2R_PVALEN_Pos _UINT16_(15) /* (SDHC_HC2R) Preset Value Enable Position */ 1097 #define SDHC_HC2R_PVALEN_Msk (_UINT16_(0x1) << SDHC_HC2R_PVALEN_Pos) /* (SDHC_HC2R) Preset Value Enable Mask */ 1098 #define SDHC_HC2R_PVALEN(value) (SDHC_HC2R_PVALEN_Msk & (_UINT16_(value) << SDHC_HC2R_PVALEN_Pos)) /* Assigment of value for PVALEN in the SDHC_HC2R register */ 1099 #define SDHC_HC2R_PVALEN_HOST_Val _UINT16_(0x0) /* (SDHC_HC2R) SDCLK and Driver Strength are controlled by Host Controller */ 1100 #define SDHC_HC2R_PVALEN_AUTO_Val _UINT16_(0x1) /* (SDHC_HC2R) Automatic Selection by Preset Value is Enabled */ 1101 #define SDHC_HC2R_PVALEN_HOST (SDHC_HC2R_PVALEN_HOST_Val << SDHC_HC2R_PVALEN_Pos) /* (SDHC_HC2R) SDCLK and Driver Strength are controlled by Host Controller Position */ 1102 #define SDHC_HC2R_PVALEN_AUTO (SDHC_HC2R_PVALEN_AUTO_Val << SDHC_HC2R_PVALEN_Pos) /* (SDHC_HC2R) Automatic Selection by Preset Value is Enabled Position */ 1103 #define SDHC_HC2R_Msk _UINT16_(0xC0FF) /* (SDHC_HC2R) Register Mask */ 1104 1105 /* EMMC mode */ 1106 #define SDHC_HC2R_EMMC_HS200EN_Pos _UINT16_(0) /* (SDHC_HC2R) HS200 Mode Enable Position */ 1107 #define SDHC_HC2R_EMMC_HS200EN_Msk (_UINT16_(0xF) << SDHC_HC2R_EMMC_HS200EN_Pos) /* (SDHC_HC2R) HS200 Mode Enable Mask */ 1108 #define SDHC_HC2R_EMMC_HS200EN(value) (SDHC_HC2R_EMMC_HS200EN_Msk & (_UINT16_(value) << SDHC_HC2R_EMMC_HS200EN_Pos)) 1109 #define SDHC_HC2R_EMMC_HS200EN_SDR12_Val _UINT16_(0x0) /* (SDHC_HC2R) SDR12 */ 1110 #define SDHC_HC2R_EMMC_HS200EN_SDR25_Val _UINT16_(0x1) /* (SDHC_HC2R) SDR25 */ 1111 #define SDHC_HC2R_EMMC_HS200EN_SDR50_Val _UINT16_(0x2) /* (SDHC_HC2R) SDR50 */ 1112 #define SDHC_HC2R_EMMC_HS200EN_SDR104_Val _UINT16_(0x3) /* (SDHC_HC2R) SDR104 */ 1113 #define SDHC_HC2R_EMMC_HS200EN_DDR50_Val _UINT16_(0x4) /* (SDHC_HC2R) DDR50 */ 1114 #define SDHC_HC2R_EMMC_HS200EN_SDR12 (SDHC_HC2R_EMMC_HS200EN_SDR12_Val << SDHC_HC2R_EMMC_HS200EN_Pos) /* (SDHC_HC2R) SDR12 Position */ 1115 #define SDHC_HC2R_EMMC_HS200EN_SDR25 (SDHC_HC2R_EMMC_HS200EN_SDR25_Val << SDHC_HC2R_EMMC_HS200EN_Pos) /* (SDHC_HC2R) SDR25 Position */ 1116 #define SDHC_HC2R_EMMC_HS200EN_SDR50 (SDHC_HC2R_EMMC_HS200EN_SDR50_Val << SDHC_HC2R_EMMC_HS200EN_Pos) /* (SDHC_HC2R) SDR50 Position */ 1117 #define SDHC_HC2R_EMMC_HS200EN_SDR104 (SDHC_HC2R_EMMC_HS200EN_SDR104_Val << SDHC_HC2R_EMMC_HS200EN_Pos) /* (SDHC_HC2R) SDR104 Position */ 1118 #define SDHC_HC2R_EMMC_HS200EN_DDR50 (SDHC_HC2R_EMMC_HS200EN_DDR50_Val << SDHC_HC2R_EMMC_HS200EN_Pos) /* (SDHC_HC2R) DDR50 Position */ 1119 #define SDHC_HC2R_EMMC_Msk _UINT16_(0x000F) /* (SDHC_HC2R_EMMC) Register Mask */ 1120 1121 1122 /* -------- SDHC_CA0R : (SDHC Offset: 0x40) ( R/ 32) Capabilities 0 -------- */ 1123 #define SDHC_CA0R_RESETVALUE _UINT32_(0x27E80080) /* (SDHC_CA0R) Capabilities 0 Reset Value */ 1124 1125 #define SDHC_CA0R_TEOCLKF_Pos _UINT32_(0) /* (SDHC_CA0R) Timeout Clock Frequency Position */ 1126 #define SDHC_CA0R_TEOCLKF_Msk (_UINT32_(0x3F) << SDHC_CA0R_TEOCLKF_Pos) /* (SDHC_CA0R) Timeout Clock Frequency Mask */ 1127 #define SDHC_CA0R_TEOCLKF(value) (SDHC_CA0R_TEOCLKF_Msk & (_UINT32_(value) << SDHC_CA0R_TEOCLKF_Pos)) /* Assigment of value for TEOCLKF in the SDHC_CA0R register */ 1128 #define SDHC_CA0R_TEOCLKF_OTHER_Val _UINT32_(0x0) /* (SDHC_CA0R) Get information via another method */ 1129 #define SDHC_CA0R_TEOCLKF_OTHER (SDHC_CA0R_TEOCLKF_OTHER_Val << SDHC_CA0R_TEOCLKF_Pos) /* (SDHC_CA0R) Get information via another method Position */ 1130 #define SDHC_CA0R_TEOCLKU_Pos _UINT32_(7) /* (SDHC_CA0R) Timeout Clock Unit Position */ 1131 #define SDHC_CA0R_TEOCLKU_Msk (_UINT32_(0x1) << SDHC_CA0R_TEOCLKU_Pos) /* (SDHC_CA0R) Timeout Clock Unit Mask */ 1132 #define SDHC_CA0R_TEOCLKU(value) (SDHC_CA0R_TEOCLKU_Msk & (_UINT32_(value) << SDHC_CA0R_TEOCLKU_Pos)) /* Assigment of value for TEOCLKU in the SDHC_CA0R register */ 1133 #define SDHC_CA0R_TEOCLKU_KHZ_Val _UINT32_(0x0) /* (SDHC_CA0R) KHz */ 1134 #define SDHC_CA0R_TEOCLKU_MHZ_Val _UINT32_(0x1) /* (SDHC_CA0R) MHz */ 1135 #define SDHC_CA0R_TEOCLKU_KHZ (SDHC_CA0R_TEOCLKU_KHZ_Val << SDHC_CA0R_TEOCLKU_Pos) /* (SDHC_CA0R) KHz Position */ 1136 #define SDHC_CA0R_TEOCLKU_MHZ (SDHC_CA0R_TEOCLKU_MHZ_Val << SDHC_CA0R_TEOCLKU_Pos) /* (SDHC_CA0R) MHz Position */ 1137 #define SDHC_CA0R_BASECLKF_Pos _UINT32_(8) /* (SDHC_CA0R) Base Clock Frequency Position */ 1138 #define SDHC_CA0R_BASECLKF_Msk (_UINT32_(0xFF) << SDHC_CA0R_BASECLKF_Pos) /* (SDHC_CA0R) Base Clock Frequency Mask */ 1139 #define SDHC_CA0R_BASECLKF(value) (SDHC_CA0R_BASECLKF_Msk & (_UINT32_(value) << SDHC_CA0R_BASECLKF_Pos)) /* Assigment of value for BASECLKF in the SDHC_CA0R register */ 1140 #define SDHC_CA0R_BASECLKF_OTHER_Val _UINT32_(0x0) /* (SDHC_CA0R) Get information via another method */ 1141 #define SDHC_CA0R_BASECLKF_OTHER (SDHC_CA0R_BASECLKF_OTHER_Val << SDHC_CA0R_BASECLKF_Pos) /* (SDHC_CA0R) Get information via another method Position */ 1142 #define SDHC_CA0R_MAXBLKL_Pos _UINT32_(16) /* (SDHC_CA0R) Max Block Length Position */ 1143 #define SDHC_CA0R_MAXBLKL_Msk (_UINT32_(0x3) << SDHC_CA0R_MAXBLKL_Pos) /* (SDHC_CA0R) Max Block Length Mask */ 1144 #define SDHC_CA0R_MAXBLKL(value) (SDHC_CA0R_MAXBLKL_Msk & (_UINT32_(value) << SDHC_CA0R_MAXBLKL_Pos)) /* Assigment of value for MAXBLKL in the SDHC_CA0R register */ 1145 #define SDHC_CA0R_MAXBLKL_512_Val _UINT32_(0x0) /* (SDHC_CA0R) 512 bytes */ 1146 #define SDHC_CA0R_MAXBLKL_512 (SDHC_CA0R_MAXBLKL_512_Val << SDHC_CA0R_MAXBLKL_Pos) /* (SDHC_CA0R) 512 bytes Position */ 1147 #define SDHC_CA0R_ED8SUP_Pos _UINT32_(18) /* (SDHC_CA0R) 8-bit Support for Embedded Device Position */ 1148 #define SDHC_CA0R_ED8SUP_Msk (_UINT32_(0x1) << SDHC_CA0R_ED8SUP_Pos) /* (SDHC_CA0R) 8-bit Support for Embedded Device Mask */ 1149 #define SDHC_CA0R_ED8SUP(value) (SDHC_CA0R_ED8SUP_Msk & (_UINT32_(value) << SDHC_CA0R_ED8SUP_Pos)) /* Assigment of value for ED8SUP in the SDHC_CA0R register */ 1150 #define SDHC_CA0R_ED8SUP_NO_Val _UINT32_(0x0) /* (SDHC_CA0R) 8-bit Bus Width not Supported */ 1151 #define SDHC_CA0R_ED8SUP_YES_Val _UINT32_(0x1) /* (SDHC_CA0R) 8-bit Bus Width Supported */ 1152 #define SDHC_CA0R_ED8SUP_NO (SDHC_CA0R_ED8SUP_NO_Val << SDHC_CA0R_ED8SUP_Pos) /* (SDHC_CA0R) 8-bit Bus Width not Supported Position */ 1153 #define SDHC_CA0R_ED8SUP_YES (SDHC_CA0R_ED8SUP_YES_Val << SDHC_CA0R_ED8SUP_Pos) /* (SDHC_CA0R) 8-bit Bus Width Supported Position */ 1154 #define SDHC_CA0R_ADMA2SUP_Pos _UINT32_(19) /* (SDHC_CA0R) ADMA2 Support Position */ 1155 #define SDHC_CA0R_ADMA2SUP_Msk (_UINT32_(0x1) << SDHC_CA0R_ADMA2SUP_Pos) /* (SDHC_CA0R) ADMA2 Support Mask */ 1156 #define SDHC_CA0R_ADMA2SUP(value) (SDHC_CA0R_ADMA2SUP_Msk & (_UINT32_(value) << SDHC_CA0R_ADMA2SUP_Pos)) /* Assigment of value for ADMA2SUP in the SDHC_CA0R register */ 1157 #define SDHC_CA0R_ADMA2SUP_NO_Val _UINT32_(0x0) /* (SDHC_CA0R) ADMA2 not Supported */ 1158 #define SDHC_CA0R_ADMA2SUP_YES_Val _UINT32_(0x1) /* (SDHC_CA0R) ADMA2 Supported */ 1159 #define SDHC_CA0R_ADMA2SUP_NO (SDHC_CA0R_ADMA2SUP_NO_Val << SDHC_CA0R_ADMA2SUP_Pos) /* (SDHC_CA0R) ADMA2 not Supported Position */ 1160 #define SDHC_CA0R_ADMA2SUP_YES (SDHC_CA0R_ADMA2SUP_YES_Val << SDHC_CA0R_ADMA2SUP_Pos) /* (SDHC_CA0R) ADMA2 Supported Position */ 1161 #define SDHC_CA0R_HSSUP_Pos _UINT32_(21) /* (SDHC_CA0R) High Speed Support Position */ 1162 #define SDHC_CA0R_HSSUP_Msk (_UINT32_(0x1) << SDHC_CA0R_HSSUP_Pos) /* (SDHC_CA0R) High Speed Support Mask */ 1163 #define SDHC_CA0R_HSSUP(value) (SDHC_CA0R_HSSUP_Msk & (_UINT32_(value) << SDHC_CA0R_HSSUP_Pos)) /* Assigment of value for HSSUP in the SDHC_CA0R register */ 1164 #define SDHC_CA0R_HSSUP_NO_Val _UINT32_(0x0) /* (SDHC_CA0R) High Speed not Supported */ 1165 #define SDHC_CA0R_HSSUP_YES_Val _UINT32_(0x1) /* (SDHC_CA0R) High Speed Supported */ 1166 #define SDHC_CA0R_HSSUP_NO (SDHC_CA0R_HSSUP_NO_Val << SDHC_CA0R_HSSUP_Pos) /* (SDHC_CA0R) High Speed not Supported Position */ 1167 #define SDHC_CA0R_HSSUP_YES (SDHC_CA0R_HSSUP_YES_Val << SDHC_CA0R_HSSUP_Pos) /* (SDHC_CA0R) High Speed Supported Position */ 1168 #define SDHC_CA0R_SDMASUP_Pos _UINT32_(22) /* (SDHC_CA0R) SDMA Support Position */ 1169 #define SDHC_CA0R_SDMASUP_Msk (_UINT32_(0x1) << SDHC_CA0R_SDMASUP_Pos) /* (SDHC_CA0R) SDMA Support Mask */ 1170 #define SDHC_CA0R_SDMASUP(value) (SDHC_CA0R_SDMASUP_Msk & (_UINT32_(value) << SDHC_CA0R_SDMASUP_Pos)) /* Assigment of value for SDMASUP in the SDHC_CA0R register */ 1171 #define SDHC_CA0R_SDMASUP_NO_Val _UINT32_(0x0) /* (SDHC_CA0R) SDMA not Supported */ 1172 #define SDHC_CA0R_SDMASUP_YES_Val _UINT32_(0x1) /* (SDHC_CA0R) SDMA Supported */ 1173 #define SDHC_CA0R_SDMASUP_NO (SDHC_CA0R_SDMASUP_NO_Val << SDHC_CA0R_SDMASUP_Pos) /* (SDHC_CA0R) SDMA not Supported Position */ 1174 #define SDHC_CA0R_SDMASUP_YES (SDHC_CA0R_SDMASUP_YES_Val << SDHC_CA0R_SDMASUP_Pos) /* (SDHC_CA0R) SDMA Supported Position */ 1175 #define SDHC_CA0R_SRSUP_Pos _UINT32_(23) /* (SDHC_CA0R) Suspend/Resume Support Position */ 1176 #define SDHC_CA0R_SRSUP_Msk (_UINT32_(0x1) << SDHC_CA0R_SRSUP_Pos) /* (SDHC_CA0R) Suspend/Resume Support Mask */ 1177 #define SDHC_CA0R_SRSUP(value) (SDHC_CA0R_SRSUP_Msk & (_UINT32_(value) << SDHC_CA0R_SRSUP_Pos)) /* Assigment of value for SRSUP in the SDHC_CA0R register */ 1178 #define SDHC_CA0R_SRSUP_NO_Val _UINT32_(0x0) /* (SDHC_CA0R) Suspend/Resume not Supported */ 1179 #define SDHC_CA0R_SRSUP_YES_Val _UINT32_(0x1) /* (SDHC_CA0R) Suspend/Resume Supported */ 1180 #define SDHC_CA0R_SRSUP_NO (SDHC_CA0R_SRSUP_NO_Val << SDHC_CA0R_SRSUP_Pos) /* (SDHC_CA0R) Suspend/Resume not Supported Position */ 1181 #define SDHC_CA0R_SRSUP_YES (SDHC_CA0R_SRSUP_YES_Val << SDHC_CA0R_SRSUP_Pos) /* (SDHC_CA0R) Suspend/Resume Supported Position */ 1182 #define SDHC_CA0R_V33VSUP_Pos _UINT32_(24) /* (SDHC_CA0R) Voltage Support 3.3V Position */ 1183 #define SDHC_CA0R_V33VSUP_Msk (_UINT32_(0x1) << SDHC_CA0R_V33VSUP_Pos) /* (SDHC_CA0R) Voltage Support 3.3V Mask */ 1184 #define SDHC_CA0R_V33VSUP(value) (SDHC_CA0R_V33VSUP_Msk & (_UINT32_(value) << SDHC_CA0R_V33VSUP_Pos)) /* Assigment of value for V33VSUP in the SDHC_CA0R register */ 1185 #define SDHC_CA0R_V33VSUP_NO_Val _UINT32_(0x0) /* (SDHC_CA0R) 3.3V Not Supported */ 1186 #define SDHC_CA0R_V33VSUP_YES_Val _UINT32_(0x1) /* (SDHC_CA0R) 3.3V Supported */ 1187 #define SDHC_CA0R_V33VSUP_NO (SDHC_CA0R_V33VSUP_NO_Val << SDHC_CA0R_V33VSUP_Pos) /* (SDHC_CA0R) 3.3V Not Supported Position */ 1188 #define SDHC_CA0R_V33VSUP_YES (SDHC_CA0R_V33VSUP_YES_Val << SDHC_CA0R_V33VSUP_Pos) /* (SDHC_CA0R) 3.3V Supported Position */ 1189 #define SDHC_CA0R_V30VSUP_Pos _UINT32_(25) /* (SDHC_CA0R) Voltage Support 3.0V Position */ 1190 #define SDHC_CA0R_V30VSUP_Msk (_UINT32_(0x1) << SDHC_CA0R_V30VSUP_Pos) /* (SDHC_CA0R) Voltage Support 3.0V Mask */ 1191 #define SDHC_CA0R_V30VSUP(value) (SDHC_CA0R_V30VSUP_Msk & (_UINT32_(value) << SDHC_CA0R_V30VSUP_Pos)) /* Assigment of value for V30VSUP in the SDHC_CA0R register */ 1192 #define SDHC_CA0R_V30VSUP_NO_Val _UINT32_(0x0) /* (SDHC_CA0R) 3.0V Not Supported */ 1193 #define SDHC_CA0R_V30VSUP_YES_Val _UINT32_(0x1) /* (SDHC_CA0R) 3.0V Supported */ 1194 #define SDHC_CA0R_V30VSUP_NO (SDHC_CA0R_V30VSUP_NO_Val << SDHC_CA0R_V30VSUP_Pos) /* (SDHC_CA0R) 3.0V Not Supported Position */ 1195 #define SDHC_CA0R_V30VSUP_YES (SDHC_CA0R_V30VSUP_YES_Val << SDHC_CA0R_V30VSUP_Pos) /* (SDHC_CA0R) 3.0V Supported Position */ 1196 #define SDHC_CA0R_V18VSUP_Pos _UINT32_(26) /* (SDHC_CA0R) Voltage Support 1.8V Position */ 1197 #define SDHC_CA0R_V18VSUP_Msk (_UINT32_(0x1) << SDHC_CA0R_V18VSUP_Pos) /* (SDHC_CA0R) Voltage Support 1.8V Mask */ 1198 #define SDHC_CA0R_V18VSUP(value) (SDHC_CA0R_V18VSUP_Msk & (_UINT32_(value) << SDHC_CA0R_V18VSUP_Pos)) /* Assigment of value for V18VSUP in the SDHC_CA0R register */ 1199 #define SDHC_CA0R_V18VSUP_NO_Val _UINT32_(0x0) /* (SDHC_CA0R) 1.8V Not Supported */ 1200 #define SDHC_CA0R_V18VSUP_YES_Val _UINT32_(0x1) /* (SDHC_CA0R) 1.8V Supported */ 1201 #define SDHC_CA0R_V18VSUP_NO (SDHC_CA0R_V18VSUP_NO_Val << SDHC_CA0R_V18VSUP_Pos) /* (SDHC_CA0R) 1.8V Not Supported Position */ 1202 #define SDHC_CA0R_V18VSUP_YES (SDHC_CA0R_V18VSUP_YES_Val << SDHC_CA0R_V18VSUP_Pos) /* (SDHC_CA0R) 1.8V Supported Position */ 1203 #define SDHC_CA0R_SB64SUP_Pos _UINT32_(28) /* (SDHC_CA0R) 64-Bit System Bus Support Position */ 1204 #define SDHC_CA0R_SB64SUP_Msk (_UINT32_(0x1) << SDHC_CA0R_SB64SUP_Pos) /* (SDHC_CA0R) 64-Bit System Bus Support Mask */ 1205 #define SDHC_CA0R_SB64SUP(value) (SDHC_CA0R_SB64SUP_Msk & (_UINT32_(value) << SDHC_CA0R_SB64SUP_Pos)) /* Assigment of value for SB64SUP in the SDHC_CA0R register */ 1206 #define SDHC_CA0R_SB64SUP_NO_Val _UINT32_(0x0) /* (SDHC_CA0R) 32-bit Address Descriptors and System Bus */ 1207 #define SDHC_CA0R_SB64SUP_YES_Val _UINT32_(0x1) /* (SDHC_CA0R) 64-bit Address Descriptors and System Bus */ 1208 #define SDHC_CA0R_SB64SUP_NO (SDHC_CA0R_SB64SUP_NO_Val << SDHC_CA0R_SB64SUP_Pos) /* (SDHC_CA0R) 32-bit Address Descriptors and System Bus Position */ 1209 #define SDHC_CA0R_SB64SUP_YES (SDHC_CA0R_SB64SUP_YES_Val << SDHC_CA0R_SB64SUP_Pos) /* (SDHC_CA0R) 64-bit Address Descriptors and System Bus Position */ 1210 #define SDHC_CA0R_ASINTSUP_Pos _UINT32_(29) /* (SDHC_CA0R) Asynchronous Interrupt Support Position */ 1211 #define SDHC_CA0R_ASINTSUP_Msk (_UINT32_(0x1) << SDHC_CA0R_ASINTSUP_Pos) /* (SDHC_CA0R) Asynchronous Interrupt Support Mask */ 1212 #define SDHC_CA0R_ASINTSUP(value) (SDHC_CA0R_ASINTSUP_Msk & (_UINT32_(value) << SDHC_CA0R_ASINTSUP_Pos)) /* Assigment of value for ASINTSUP in the SDHC_CA0R register */ 1213 #define SDHC_CA0R_ASINTSUP_NO_Val _UINT32_(0x0) /* (SDHC_CA0R) Asynchronous Interrupt not Supported */ 1214 #define SDHC_CA0R_ASINTSUP_YES_Val _UINT32_(0x1) /* (SDHC_CA0R) Asynchronous Interrupt supported */ 1215 #define SDHC_CA0R_ASINTSUP_NO (SDHC_CA0R_ASINTSUP_NO_Val << SDHC_CA0R_ASINTSUP_Pos) /* (SDHC_CA0R) Asynchronous Interrupt not Supported Position */ 1216 #define SDHC_CA0R_ASINTSUP_YES (SDHC_CA0R_ASINTSUP_YES_Val << SDHC_CA0R_ASINTSUP_Pos) /* (SDHC_CA0R) Asynchronous Interrupt supported Position */ 1217 #define SDHC_CA0R_SLTYPE_Pos _UINT32_(30) /* (SDHC_CA0R) Slot Type Position */ 1218 #define SDHC_CA0R_SLTYPE_Msk (_UINT32_(0x3) << SDHC_CA0R_SLTYPE_Pos) /* (SDHC_CA0R) Slot Type Mask */ 1219 #define SDHC_CA0R_SLTYPE(value) (SDHC_CA0R_SLTYPE_Msk & (_UINT32_(value) << SDHC_CA0R_SLTYPE_Pos)) /* Assigment of value for SLTYPE in the SDHC_CA0R register */ 1220 #define SDHC_CA0R_SLTYPE_REMOVABLE_Val _UINT32_(0x0) /* (SDHC_CA0R) Removable Card Slot */ 1221 #define SDHC_CA0R_SLTYPE_EMBEDDED_Val _UINT32_(0x1) /* (SDHC_CA0R) Embedded Slot for One Device */ 1222 #define SDHC_CA0R_SLTYPE_REMOVABLE (SDHC_CA0R_SLTYPE_REMOVABLE_Val << SDHC_CA0R_SLTYPE_Pos) /* (SDHC_CA0R) Removable Card Slot Position */ 1223 #define SDHC_CA0R_SLTYPE_EMBEDDED (SDHC_CA0R_SLTYPE_EMBEDDED_Val << SDHC_CA0R_SLTYPE_Pos) /* (SDHC_CA0R) Embedded Slot for One Device Position */ 1224 #define SDHC_CA0R_Msk _UINT32_(0xF7EFFFBF) /* (SDHC_CA0R) Register Mask */ 1225 1226 1227 /* -------- SDHC_CA1R : (SDHC Offset: 0x44) ( R/ 32) Capabilities 1 -------- */ 1228 #define SDHC_CA1R_RESETVALUE _UINT32_(0x70) /* (SDHC_CA1R) Capabilities 1 Reset Value */ 1229 1230 #define SDHC_CA1R_SDR50SUP_Pos _UINT32_(0) /* (SDHC_CA1R) SDR50 Support Position */ 1231 #define SDHC_CA1R_SDR50SUP_Msk (_UINT32_(0x1) << SDHC_CA1R_SDR50SUP_Pos) /* (SDHC_CA1R) SDR50 Support Mask */ 1232 #define SDHC_CA1R_SDR50SUP(value) (SDHC_CA1R_SDR50SUP_Msk & (_UINT32_(value) << SDHC_CA1R_SDR50SUP_Pos)) /* Assigment of value for SDR50SUP in the SDHC_CA1R register */ 1233 #define SDHC_CA1R_SDR50SUP_NO_Val _UINT32_(0x0) /* (SDHC_CA1R) SDR50 is Not Supported */ 1234 #define SDHC_CA1R_SDR50SUP_YES_Val _UINT32_(0x1) /* (SDHC_CA1R) SDR50 is Supported */ 1235 #define SDHC_CA1R_SDR50SUP_NO (SDHC_CA1R_SDR50SUP_NO_Val << SDHC_CA1R_SDR50SUP_Pos) /* (SDHC_CA1R) SDR50 is Not Supported Position */ 1236 #define SDHC_CA1R_SDR50SUP_YES (SDHC_CA1R_SDR50SUP_YES_Val << SDHC_CA1R_SDR50SUP_Pos) /* (SDHC_CA1R) SDR50 is Supported Position */ 1237 #define SDHC_CA1R_SDR104SUP_Pos _UINT32_(1) /* (SDHC_CA1R) SDR104 Support Position */ 1238 #define SDHC_CA1R_SDR104SUP_Msk (_UINT32_(0x1) << SDHC_CA1R_SDR104SUP_Pos) /* (SDHC_CA1R) SDR104 Support Mask */ 1239 #define SDHC_CA1R_SDR104SUP(value) (SDHC_CA1R_SDR104SUP_Msk & (_UINT32_(value) << SDHC_CA1R_SDR104SUP_Pos)) /* Assigment of value for SDR104SUP in the SDHC_CA1R register */ 1240 #define SDHC_CA1R_SDR104SUP_NO_Val _UINT32_(0x0) /* (SDHC_CA1R) SDR104 is Not Supported */ 1241 #define SDHC_CA1R_SDR104SUP_YES_Val _UINT32_(0x1) /* (SDHC_CA1R) SDR104 is Supported */ 1242 #define SDHC_CA1R_SDR104SUP_NO (SDHC_CA1R_SDR104SUP_NO_Val << SDHC_CA1R_SDR104SUP_Pos) /* (SDHC_CA1R) SDR104 is Not Supported Position */ 1243 #define SDHC_CA1R_SDR104SUP_YES (SDHC_CA1R_SDR104SUP_YES_Val << SDHC_CA1R_SDR104SUP_Pos) /* (SDHC_CA1R) SDR104 is Supported Position */ 1244 #define SDHC_CA1R_DDR50SUP_Pos _UINT32_(2) /* (SDHC_CA1R) DDR50 Support Position */ 1245 #define SDHC_CA1R_DDR50SUP_Msk (_UINT32_(0x1) << SDHC_CA1R_DDR50SUP_Pos) /* (SDHC_CA1R) DDR50 Support Mask */ 1246 #define SDHC_CA1R_DDR50SUP(value) (SDHC_CA1R_DDR50SUP_Msk & (_UINT32_(value) << SDHC_CA1R_DDR50SUP_Pos)) /* Assigment of value for DDR50SUP in the SDHC_CA1R register */ 1247 #define SDHC_CA1R_DDR50SUP_NO_Val _UINT32_(0x0) /* (SDHC_CA1R) DDR50 is Not Supported */ 1248 #define SDHC_CA1R_DDR50SUP_YES_Val _UINT32_(0x1) /* (SDHC_CA1R) DDR50 is Supported */ 1249 #define SDHC_CA1R_DDR50SUP_NO (SDHC_CA1R_DDR50SUP_NO_Val << SDHC_CA1R_DDR50SUP_Pos) /* (SDHC_CA1R) DDR50 is Not Supported Position */ 1250 #define SDHC_CA1R_DDR50SUP_YES (SDHC_CA1R_DDR50SUP_YES_Val << SDHC_CA1R_DDR50SUP_Pos) /* (SDHC_CA1R) DDR50 is Supported Position */ 1251 #define SDHC_CA1R_DRVASUP_Pos _UINT32_(4) /* (SDHC_CA1R) Driver Type A Support Position */ 1252 #define SDHC_CA1R_DRVASUP_Msk (_UINT32_(0x1) << SDHC_CA1R_DRVASUP_Pos) /* (SDHC_CA1R) Driver Type A Support Mask */ 1253 #define SDHC_CA1R_DRVASUP(value) (SDHC_CA1R_DRVASUP_Msk & (_UINT32_(value) << SDHC_CA1R_DRVASUP_Pos)) /* Assigment of value for DRVASUP in the SDHC_CA1R register */ 1254 #define SDHC_CA1R_DRVASUP_NO_Val _UINT32_(0x0) /* (SDHC_CA1R) Driver Type A is Not Supported */ 1255 #define SDHC_CA1R_DRVASUP_YES_Val _UINT32_(0x1) /* (SDHC_CA1R) Driver Type A is Supported */ 1256 #define SDHC_CA1R_DRVASUP_NO (SDHC_CA1R_DRVASUP_NO_Val << SDHC_CA1R_DRVASUP_Pos) /* (SDHC_CA1R) Driver Type A is Not Supported Position */ 1257 #define SDHC_CA1R_DRVASUP_YES (SDHC_CA1R_DRVASUP_YES_Val << SDHC_CA1R_DRVASUP_Pos) /* (SDHC_CA1R) Driver Type A is Supported Position */ 1258 #define SDHC_CA1R_DRVCSUP_Pos _UINT32_(5) /* (SDHC_CA1R) Driver Type C Support Position */ 1259 #define SDHC_CA1R_DRVCSUP_Msk (_UINT32_(0x1) << SDHC_CA1R_DRVCSUP_Pos) /* (SDHC_CA1R) Driver Type C Support Mask */ 1260 #define SDHC_CA1R_DRVCSUP(value) (SDHC_CA1R_DRVCSUP_Msk & (_UINT32_(value) << SDHC_CA1R_DRVCSUP_Pos)) /* Assigment of value for DRVCSUP in the SDHC_CA1R register */ 1261 #define SDHC_CA1R_DRVCSUP_NO_Val _UINT32_(0x0) /* (SDHC_CA1R) Driver Type C is Not Supported */ 1262 #define SDHC_CA1R_DRVCSUP_YES_Val _UINT32_(0x1) /* (SDHC_CA1R) Driver Type C is Supported */ 1263 #define SDHC_CA1R_DRVCSUP_NO (SDHC_CA1R_DRVCSUP_NO_Val << SDHC_CA1R_DRVCSUP_Pos) /* (SDHC_CA1R) Driver Type C is Not Supported Position */ 1264 #define SDHC_CA1R_DRVCSUP_YES (SDHC_CA1R_DRVCSUP_YES_Val << SDHC_CA1R_DRVCSUP_Pos) /* (SDHC_CA1R) Driver Type C is Supported Position */ 1265 #define SDHC_CA1R_DRVDSUP_Pos _UINT32_(6) /* (SDHC_CA1R) Driver Type D Support Position */ 1266 #define SDHC_CA1R_DRVDSUP_Msk (_UINT32_(0x1) << SDHC_CA1R_DRVDSUP_Pos) /* (SDHC_CA1R) Driver Type D Support Mask */ 1267 #define SDHC_CA1R_DRVDSUP(value) (SDHC_CA1R_DRVDSUP_Msk & (_UINT32_(value) << SDHC_CA1R_DRVDSUP_Pos)) /* Assigment of value for DRVDSUP in the SDHC_CA1R register */ 1268 #define SDHC_CA1R_DRVDSUP_NO_Val _UINT32_(0x0) /* (SDHC_CA1R) Driver Type D is Not Supported */ 1269 #define SDHC_CA1R_DRVDSUP_YES_Val _UINT32_(0x1) /* (SDHC_CA1R) Driver Type D is Supported */ 1270 #define SDHC_CA1R_DRVDSUP_NO (SDHC_CA1R_DRVDSUP_NO_Val << SDHC_CA1R_DRVDSUP_Pos) /* (SDHC_CA1R) Driver Type D is Not Supported Position */ 1271 #define SDHC_CA1R_DRVDSUP_YES (SDHC_CA1R_DRVDSUP_YES_Val << SDHC_CA1R_DRVDSUP_Pos) /* (SDHC_CA1R) Driver Type D is Supported Position */ 1272 #define SDHC_CA1R_TCNTRT_Pos _UINT32_(8) /* (SDHC_CA1R) Timer Count for Re-Tuning Position */ 1273 #define SDHC_CA1R_TCNTRT_Msk (_UINT32_(0xF) << SDHC_CA1R_TCNTRT_Pos) /* (SDHC_CA1R) Timer Count for Re-Tuning Mask */ 1274 #define SDHC_CA1R_TCNTRT(value) (SDHC_CA1R_TCNTRT_Msk & (_UINT32_(value) << SDHC_CA1R_TCNTRT_Pos)) /* Assigment of value for TCNTRT in the SDHC_CA1R register */ 1275 #define SDHC_CA1R_TCNTRT_DISABLED_Val _UINT32_(0x0) /* (SDHC_CA1R) Re-Tuning Timer disabled */ 1276 #define SDHC_CA1R_TCNTRT_1S_Val _UINT32_(0x1) /* (SDHC_CA1R) 1 second */ 1277 #define SDHC_CA1R_TCNTRT_2S_Val _UINT32_(0x2) /* (SDHC_CA1R) 2 seconds */ 1278 #define SDHC_CA1R_TCNTRT_4S_Val _UINT32_(0x3) /* (SDHC_CA1R) 4 seconds */ 1279 #define SDHC_CA1R_TCNTRT_8S_Val _UINT32_(0x4) /* (SDHC_CA1R) 8 seconds */ 1280 #define SDHC_CA1R_TCNTRT_16S_Val _UINT32_(0x5) /* (SDHC_CA1R) 16 seconds */ 1281 #define SDHC_CA1R_TCNTRT_32S_Val _UINT32_(0x6) /* (SDHC_CA1R) 32 seconds */ 1282 #define SDHC_CA1R_TCNTRT_64S_Val _UINT32_(0x7) /* (SDHC_CA1R) 64 seconds */ 1283 #define SDHC_CA1R_TCNTRT_128S_Val _UINT32_(0x8) /* (SDHC_CA1R) 128 seconds */ 1284 #define SDHC_CA1R_TCNTRT_256S_Val _UINT32_(0x9) /* (SDHC_CA1R) 256 seconds */ 1285 #define SDHC_CA1R_TCNTRT_512S_Val _UINT32_(0xA) /* (SDHC_CA1R) 512 seconds */ 1286 #define SDHC_CA1R_TCNTRT_1024S_Val _UINT32_(0xB) /* (SDHC_CA1R) 1024 seconds */ 1287 #define SDHC_CA1R_TCNTRT_OTHER_Val _UINT32_(0xF) /* (SDHC_CA1R) Get information from other source */ 1288 #define SDHC_CA1R_TCNTRT_DISABLED (SDHC_CA1R_TCNTRT_DISABLED_Val << SDHC_CA1R_TCNTRT_Pos) /* (SDHC_CA1R) Re-Tuning Timer disabled Position */ 1289 #define SDHC_CA1R_TCNTRT_1S (SDHC_CA1R_TCNTRT_1S_Val << SDHC_CA1R_TCNTRT_Pos) /* (SDHC_CA1R) 1 second Position */ 1290 #define SDHC_CA1R_TCNTRT_2S (SDHC_CA1R_TCNTRT_2S_Val << SDHC_CA1R_TCNTRT_Pos) /* (SDHC_CA1R) 2 seconds Position */ 1291 #define SDHC_CA1R_TCNTRT_4S (SDHC_CA1R_TCNTRT_4S_Val << SDHC_CA1R_TCNTRT_Pos) /* (SDHC_CA1R) 4 seconds Position */ 1292 #define SDHC_CA1R_TCNTRT_8S (SDHC_CA1R_TCNTRT_8S_Val << SDHC_CA1R_TCNTRT_Pos) /* (SDHC_CA1R) 8 seconds Position */ 1293 #define SDHC_CA1R_TCNTRT_16S (SDHC_CA1R_TCNTRT_16S_Val << SDHC_CA1R_TCNTRT_Pos) /* (SDHC_CA1R) 16 seconds Position */ 1294 #define SDHC_CA1R_TCNTRT_32S (SDHC_CA1R_TCNTRT_32S_Val << SDHC_CA1R_TCNTRT_Pos) /* (SDHC_CA1R) 32 seconds Position */ 1295 #define SDHC_CA1R_TCNTRT_64S (SDHC_CA1R_TCNTRT_64S_Val << SDHC_CA1R_TCNTRT_Pos) /* (SDHC_CA1R) 64 seconds Position */ 1296 #define SDHC_CA1R_TCNTRT_128S (SDHC_CA1R_TCNTRT_128S_Val << SDHC_CA1R_TCNTRT_Pos) /* (SDHC_CA1R) 128 seconds Position */ 1297 #define SDHC_CA1R_TCNTRT_256S (SDHC_CA1R_TCNTRT_256S_Val << SDHC_CA1R_TCNTRT_Pos) /* (SDHC_CA1R) 256 seconds Position */ 1298 #define SDHC_CA1R_TCNTRT_512S (SDHC_CA1R_TCNTRT_512S_Val << SDHC_CA1R_TCNTRT_Pos) /* (SDHC_CA1R) 512 seconds Position */ 1299 #define SDHC_CA1R_TCNTRT_1024S (SDHC_CA1R_TCNTRT_1024S_Val << SDHC_CA1R_TCNTRT_Pos) /* (SDHC_CA1R) 1024 seconds Position */ 1300 #define SDHC_CA1R_TCNTRT_OTHER (SDHC_CA1R_TCNTRT_OTHER_Val << SDHC_CA1R_TCNTRT_Pos) /* (SDHC_CA1R) Get information from other source Position */ 1301 #define SDHC_CA1R_TSDR50_Pos _UINT32_(13) /* (SDHC_CA1R) Use Tuning for SDR50 Position */ 1302 #define SDHC_CA1R_TSDR50_Msk (_UINT32_(0x1) << SDHC_CA1R_TSDR50_Pos) /* (SDHC_CA1R) Use Tuning for SDR50 Mask */ 1303 #define SDHC_CA1R_TSDR50(value) (SDHC_CA1R_TSDR50_Msk & (_UINT32_(value) << SDHC_CA1R_TSDR50_Pos)) /* Assigment of value for TSDR50 in the SDHC_CA1R register */ 1304 #define SDHC_CA1R_TSDR50_NO_Val _UINT32_(0x0) /* (SDHC_CA1R) SDR50 does not require tuning */ 1305 #define SDHC_CA1R_TSDR50_YES_Val _UINT32_(0x1) /* (SDHC_CA1R) SDR50 requires tuning */ 1306 #define SDHC_CA1R_TSDR50_NO (SDHC_CA1R_TSDR50_NO_Val << SDHC_CA1R_TSDR50_Pos) /* (SDHC_CA1R) SDR50 does not require tuning Position */ 1307 #define SDHC_CA1R_TSDR50_YES (SDHC_CA1R_TSDR50_YES_Val << SDHC_CA1R_TSDR50_Pos) /* (SDHC_CA1R) SDR50 requires tuning Position */ 1308 #define SDHC_CA1R_CLKMULT_Pos _UINT32_(16) /* (SDHC_CA1R) Clock Multiplier Position */ 1309 #define SDHC_CA1R_CLKMULT_Msk (_UINT32_(0xFF) << SDHC_CA1R_CLKMULT_Pos) /* (SDHC_CA1R) Clock Multiplier Mask */ 1310 #define SDHC_CA1R_CLKMULT(value) (SDHC_CA1R_CLKMULT_Msk & (_UINT32_(value) << SDHC_CA1R_CLKMULT_Pos)) /* Assigment of value for CLKMULT in the SDHC_CA1R register */ 1311 #define SDHC_CA1R_CLKMULT_NO_Val _UINT32_(0x0) /* (SDHC_CA1R) Clock Multiplier is Not Supported */ 1312 #define SDHC_CA1R_CLKMULT_NO (SDHC_CA1R_CLKMULT_NO_Val << SDHC_CA1R_CLKMULT_Pos) /* (SDHC_CA1R) Clock Multiplier is Not Supported Position */ 1313 #define SDHC_CA1R_Msk _UINT32_(0x00FF2F77) /* (SDHC_CA1R) Register Mask */ 1314 1315 #define SDHC_CA1R_TSDR_Pos _UINT32_(13) /* (SDHC_CA1R Position) Use Tuning for SDR5x */ 1316 #define SDHC_CA1R_TSDR_Msk (_UINT32_(0x1) << SDHC_CA1R_TSDR_Pos) /* (SDHC_CA1R Mask) TSDR */ 1317 #define SDHC_CA1R_TSDR(value) (SDHC_CA1R_TSDR_Msk & (_UINT32_(value) << SDHC_CA1R_TSDR_Pos)) 1318 1319 /* -------- SDHC_MCCAR : (SDHC Offset: 0x48) ( R/ 32) Maximum Current Capabilities -------- */ 1320 #define SDHC_MCCAR_RESETVALUE _UINT32_(0x00) /* (SDHC_MCCAR) Maximum Current Capabilities Reset Value */ 1321 1322 #define SDHC_MCCAR_MAXCUR33V_Pos _UINT32_(0) /* (SDHC_MCCAR) Maximum Current for 3.3V Position */ 1323 #define SDHC_MCCAR_MAXCUR33V_Msk (_UINT32_(0xFF) << SDHC_MCCAR_MAXCUR33V_Pos) /* (SDHC_MCCAR) Maximum Current for 3.3V Mask */ 1324 #define SDHC_MCCAR_MAXCUR33V(value) (SDHC_MCCAR_MAXCUR33V_Msk & (_UINT32_(value) << SDHC_MCCAR_MAXCUR33V_Pos)) /* Assigment of value for MAXCUR33V in the SDHC_MCCAR register */ 1325 #define SDHC_MCCAR_MAXCUR33V_OTHER_Val _UINT32_(0x0) /* (SDHC_MCCAR) Get information via another method */ 1326 #define SDHC_MCCAR_MAXCUR33V_4MA_Val _UINT32_(0x1) /* (SDHC_MCCAR) 4mA */ 1327 #define SDHC_MCCAR_MAXCUR33V_8MA_Val _UINT32_(0x2) /* (SDHC_MCCAR) 8mA */ 1328 #define SDHC_MCCAR_MAXCUR33V_12MA_Val _UINT32_(0x3) /* (SDHC_MCCAR) 12mA */ 1329 #define SDHC_MCCAR_MAXCUR33V_OTHER (SDHC_MCCAR_MAXCUR33V_OTHER_Val << SDHC_MCCAR_MAXCUR33V_Pos) /* (SDHC_MCCAR) Get information via another method Position */ 1330 #define SDHC_MCCAR_MAXCUR33V_4MA (SDHC_MCCAR_MAXCUR33V_4MA_Val << SDHC_MCCAR_MAXCUR33V_Pos) /* (SDHC_MCCAR) 4mA Position */ 1331 #define SDHC_MCCAR_MAXCUR33V_8MA (SDHC_MCCAR_MAXCUR33V_8MA_Val << SDHC_MCCAR_MAXCUR33V_Pos) /* (SDHC_MCCAR) 8mA Position */ 1332 #define SDHC_MCCAR_MAXCUR33V_12MA (SDHC_MCCAR_MAXCUR33V_12MA_Val << SDHC_MCCAR_MAXCUR33V_Pos) /* (SDHC_MCCAR) 12mA Position */ 1333 #define SDHC_MCCAR_MAXCUR30V_Pos _UINT32_(8) /* (SDHC_MCCAR) Maximum Current for 3.0V Position */ 1334 #define SDHC_MCCAR_MAXCUR30V_Msk (_UINT32_(0xFF) << SDHC_MCCAR_MAXCUR30V_Pos) /* (SDHC_MCCAR) Maximum Current for 3.0V Mask */ 1335 #define SDHC_MCCAR_MAXCUR30V(value) (SDHC_MCCAR_MAXCUR30V_Msk & (_UINT32_(value) << SDHC_MCCAR_MAXCUR30V_Pos)) /* Assigment of value for MAXCUR30V in the SDHC_MCCAR register */ 1336 #define SDHC_MCCAR_MAXCUR30V_OTHER_Val _UINT32_(0x0) /* (SDHC_MCCAR) Get information via another method */ 1337 #define SDHC_MCCAR_MAXCUR30V_4MA_Val _UINT32_(0x1) /* (SDHC_MCCAR) 4mA */ 1338 #define SDHC_MCCAR_MAXCUR30V_8MA_Val _UINT32_(0x2) /* (SDHC_MCCAR) 8mA */ 1339 #define SDHC_MCCAR_MAXCUR30V_12MA_Val _UINT32_(0x3) /* (SDHC_MCCAR) 12mA */ 1340 #define SDHC_MCCAR_MAXCUR30V_OTHER (SDHC_MCCAR_MAXCUR30V_OTHER_Val << SDHC_MCCAR_MAXCUR30V_Pos) /* (SDHC_MCCAR) Get information via another method Position */ 1341 #define SDHC_MCCAR_MAXCUR30V_4MA (SDHC_MCCAR_MAXCUR30V_4MA_Val << SDHC_MCCAR_MAXCUR30V_Pos) /* (SDHC_MCCAR) 4mA Position */ 1342 #define SDHC_MCCAR_MAXCUR30V_8MA (SDHC_MCCAR_MAXCUR30V_8MA_Val << SDHC_MCCAR_MAXCUR30V_Pos) /* (SDHC_MCCAR) 8mA Position */ 1343 #define SDHC_MCCAR_MAXCUR30V_12MA (SDHC_MCCAR_MAXCUR30V_12MA_Val << SDHC_MCCAR_MAXCUR30V_Pos) /* (SDHC_MCCAR) 12mA Position */ 1344 #define SDHC_MCCAR_MAXCUR18V_Pos _UINT32_(16) /* (SDHC_MCCAR) Maximum Current for 1.8V Position */ 1345 #define SDHC_MCCAR_MAXCUR18V_Msk (_UINT32_(0xFF) << SDHC_MCCAR_MAXCUR18V_Pos) /* (SDHC_MCCAR) Maximum Current for 1.8V Mask */ 1346 #define SDHC_MCCAR_MAXCUR18V(value) (SDHC_MCCAR_MAXCUR18V_Msk & (_UINT32_(value) << SDHC_MCCAR_MAXCUR18V_Pos)) /* Assigment of value for MAXCUR18V in the SDHC_MCCAR register */ 1347 #define SDHC_MCCAR_MAXCUR18V_OTHER_Val _UINT32_(0x0) /* (SDHC_MCCAR) Get information via another method */ 1348 #define SDHC_MCCAR_MAXCUR18V_4MA_Val _UINT32_(0x1) /* (SDHC_MCCAR) 4mA */ 1349 #define SDHC_MCCAR_MAXCUR18V_8MA_Val _UINT32_(0x2) /* (SDHC_MCCAR) 8mA */ 1350 #define SDHC_MCCAR_MAXCUR18V_12MA_Val _UINT32_(0x3) /* (SDHC_MCCAR) 12mA */ 1351 #define SDHC_MCCAR_MAXCUR18V_OTHER (SDHC_MCCAR_MAXCUR18V_OTHER_Val << SDHC_MCCAR_MAXCUR18V_Pos) /* (SDHC_MCCAR) Get information via another method Position */ 1352 #define SDHC_MCCAR_MAXCUR18V_4MA (SDHC_MCCAR_MAXCUR18V_4MA_Val << SDHC_MCCAR_MAXCUR18V_Pos) /* (SDHC_MCCAR) 4mA Position */ 1353 #define SDHC_MCCAR_MAXCUR18V_8MA (SDHC_MCCAR_MAXCUR18V_8MA_Val << SDHC_MCCAR_MAXCUR18V_Pos) /* (SDHC_MCCAR) 8mA Position */ 1354 #define SDHC_MCCAR_MAXCUR18V_12MA (SDHC_MCCAR_MAXCUR18V_12MA_Val << SDHC_MCCAR_MAXCUR18V_Pos) /* (SDHC_MCCAR) 12mA Position */ 1355 #define SDHC_MCCAR_Msk _UINT32_(0x00FFFFFF) /* (SDHC_MCCAR) Register Mask */ 1356 1357 1358 /* -------- SDHC_FERACES : (SDHC Offset: 0x50) ( /W 16) Force Event for Auto CMD Error Status -------- */ 1359 #define SDHC_FERACES_RESETVALUE _UINT16_(0x00) /* (SDHC_FERACES) Force Event for Auto CMD Error Status Reset Value */ 1360 1361 #define SDHC_FERACES_ACMD12NE_Pos _UINT16_(0) /* (SDHC_FERACES) Force Event for Auto CMD12 Not Executed Position */ 1362 #define SDHC_FERACES_ACMD12NE_Msk (_UINT16_(0x1) << SDHC_FERACES_ACMD12NE_Pos) /* (SDHC_FERACES) Force Event for Auto CMD12 Not Executed Mask */ 1363 #define SDHC_FERACES_ACMD12NE(value) (SDHC_FERACES_ACMD12NE_Msk & (_UINT16_(value) << SDHC_FERACES_ACMD12NE_Pos)) /* Assigment of value for ACMD12NE in the SDHC_FERACES register */ 1364 #define SDHC_FERACES_ACMD12NE_NO_Val _UINT16_(0x0) /* (SDHC_FERACES) No Interrupt */ 1365 #define SDHC_FERACES_ACMD12NE_YES_Val _UINT16_(0x1) /* (SDHC_FERACES) Interrupt is generated */ 1366 #define SDHC_FERACES_ACMD12NE_NO (SDHC_FERACES_ACMD12NE_NO_Val << SDHC_FERACES_ACMD12NE_Pos) /* (SDHC_FERACES) No Interrupt Position */ 1367 #define SDHC_FERACES_ACMD12NE_YES (SDHC_FERACES_ACMD12NE_YES_Val << SDHC_FERACES_ACMD12NE_Pos) /* (SDHC_FERACES) Interrupt is generated Position */ 1368 #define SDHC_FERACES_ACMDTEO_Pos _UINT16_(1) /* (SDHC_FERACES) Force Event for Auto CMD Timeout Error Position */ 1369 #define SDHC_FERACES_ACMDTEO_Msk (_UINT16_(0x1) << SDHC_FERACES_ACMDTEO_Pos) /* (SDHC_FERACES) Force Event for Auto CMD Timeout Error Mask */ 1370 #define SDHC_FERACES_ACMDTEO(value) (SDHC_FERACES_ACMDTEO_Msk & (_UINT16_(value) << SDHC_FERACES_ACMDTEO_Pos)) /* Assigment of value for ACMDTEO in the SDHC_FERACES register */ 1371 #define SDHC_FERACES_ACMDTEO_NO_Val _UINT16_(0x0) /* (SDHC_FERACES) No Interrupt */ 1372 #define SDHC_FERACES_ACMDTEO_YES_Val _UINT16_(0x1) /* (SDHC_FERACES) Interrupt is generated */ 1373 #define SDHC_FERACES_ACMDTEO_NO (SDHC_FERACES_ACMDTEO_NO_Val << SDHC_FERACES_ACMDTEO_Pos) /* (SDHC_FERACES) No Interrupt Position */ 1374 #define SDHC_FERACES_ACMDTEO_YES (SDHC_FERACES_ACMDTEO_YES_Val << SDHC_FERACES_ACMDTEO_Pos) /* (SDHC_FERACES) Interrupt is generated Position */ 1375 #define SDHC_FERACES_ACMDCRC_Pos _UINT16_(2) /* (SDHC_FERACES) Force Event for Auto CMD CRC Error Position */ 1376 #define SDHC_FERACES_ACMDCRC_Msk (_UINT16_(0x1) << SDHC_FERACES_ACMDCRC_Pos) /* (SDHC_FERACES) Force Event for Auto CMD CRC Error Mask */ 1377 #define SDHC_FERACES_ACMDCRC(value) (SDHC_FERACES_ACMDCRC_Msk & (_UINT16_(value) << SDHC_FERACES_ACMDCRC_Pos)) /* Assigment of value for ACMDCRC in the SDHC_FERACES register */ 1378 #define SDHC_FERACES_ACMDCRC_NO_Val _UINT16_(0x0) /* (SDHC_FERACES) No Interrupt */ 1379 #define SDHC_FERACES_ACMDCRC_YES_Val _UINT16_(0x1) /* (SDHC_FERACES) Interrupt is generated */ 1380 #define SDHC_FERACES_ACMDCRC_NO (SDHC_FERACES_ACMDCRC_NO_Val << SDHC_FERACES_ACMDCRC_Pos) /* (SDHC_FERACES) No Interrupt Position */ 1381 #define SDHC_FERACES_ACMDCRC_YES (SDHC_FERACES_ACMDCRC_YES_Val << SDHC_FERACES_ACMDCRC_Pos) /* (SDHC_FERACES) Interrupt is generated Position */ 1382 #define SDHC_FERACES_ACMDEND_Pos _UINT16_(3) /* (SDHC_FERACES) Force Event for Auto CMD End Bit Error Position */ 1383 #define SDHC_FERACES_ACMDEND_Msk (_UINT16_(0x1) << SDHC_FERACES_ACMDEND_Pos) /* (SDHC_FERACES) Force Event for Auto CMD End Bit Error Mask */ 1384 #define SDHC_FERACES_ACMDEND(value) (SDHC_FERACES_ACMDEND_Msk & (_UINT16_(value) << SDHC_FERACES_ACMDEND_Pos)) /* Assigment of value for ACMDEND in the SDHC_FERACES register */ 1385 #define SDHC_FERACES_ACMDEND_NO_Val _UINT16_(0x0) /* (SDHC_FERACES) No Interrupt */ 1386 #define SDHC_FERACES_ACMDEND_YES_Val _UINT16_(0x1) /* (SDHC_FERACES) Interrupt is generated */ 1387 #define SDHC_FERACES_ACMDEND_NO (SDHC_FERACES_ACMDEND_NO_Val << SDHC_FERACES_ACMDEND_Pos) /* (SDHC_FERACES) No Interrupt Position */ 1388 #define SDHC_FERACES_ACMDEND_YES (SDHC_FERACES_ACMDEND_YES_Val << SDHC_FERACES_ACMDEND_Pos) /* (SDHC_FERACES) Interrupt is generated Position */ 1389 #define SDHC_FERACES_ACMDIDX_Pos _UINT16_(4) /* (SDHC_FERACES) Force Event for Auto CMD Index Error Position */ 1390 #define SDHC_FERACES_ACMDIDX_Msk (_UINT16_(0x1) << SDHC_FERACES_ACMDIDX_Pos) /* (SDHC_FERACES) Force Event for Auto CMD Index Error Mask */ 1391 #define SDHC_FERACES_ACMDIDX(value) (SDHC_FERACES_ACMDIDX_Msk & (_UINT16_(value) << SDHC_FERACES_ACMDIDX_Pos)) /* Assigment of value for ACMDIDX in the SDHC_FERACES register */ 1392 #define SDHC_FERACES_ACMDIDX_NO_Val _UINT16_(0x0) /* (SDHC_FERACES) No Interrupt */ 1393 #define SDHC_FERACES_ACMDIDX_YES_Val _UINT16_(0x1) /* (SDHC_FERACES) Interrupt is generated */ 1394 #define SDHC_FERACES_ACMDIDX_NO (SDHC_FERACES_ACMDIDX_NO_Val << SDHC_FERACES_ACMDIDX_Pos) /* (SDHC_FERACES) No Interrupt Position */ 1395 #define SDHC_FERACES_ACMDIDX_YES (SDHC_FERACES_ACMDIDX_YES_Val << SDHC_FERACES_ACMDIDX_Pos) /* (SDHC_FERACES) Interrupt is generated Position */ 1396 #define SDHC_FERACES_CMDNI_Pos _UINT16_(7) /* (SDHC_FERACES) Force Event for Command Not Issued By Auto CMD12 Error Position */ 1397 #define SDHC_FERACES_CMDNI_Msk (_UINT16_(0x1) << SDHC_FERACES_CMDNI_Pos) /* (SDHC_FERACES) Force Event for Command Not Issued By Auto CMD12 Error Mask */ 1398 #define SDHC_FERACES_CMDNI(value) (SDHC_FERACES_CMDNI_Msk & (_UINT16_(value) << SDHC_FERACES_CMDNI_Pos)) /* Assigment of value for CMDNI in the SDHC_FERACES register */ 1399 #define SDHC_FERACES_CMDNI_NO_Val _UINT16_(0x0) /* (SDHC_FERACES) No Interrupt */ 1400 #define SDHC_FERACES_CMDNI_YES_Val _UINT16_(0x1) /* (SDHC_FERACES) Interrupt is generated */ 1401 #define SDHC_FERACES_CMDNI_NO (SDHC_FERACES_CMDNI_NO_Val << SDHC_FERACES_CMDNI_Pos) /* (SDHC_FERACES) No Interrupt Position */ 1402 #define SDHC_FERACES_CMDNI_YES (SDHC_FERACES_CMDNI_YES_Val << SDHC_FERACES_CMDNI_Pos) /* (SDHC_FERACES) Interrupt is generated Position */ 1403 #define SDHC_FERACES_Msk _UINT16_(0x009F) /* (SDHC_FERACES) Register Mask */ 1404 1405 1406 /* -------- SDHC_FEREIS : (SDHC Offset: 0x52) ( /W 16) Force Event for Error Interrupt Status -------- */ 1407 #define SDHC_FEREIS_RESETVALUE _UINT16_(0x00) /* (SDHC_FEREIS) Force Event for Error Interrupt Status Reset Value */ 1408 1409 #define SDHC_FEREIS_CMDTEO_Pos _UINT16_(0) /* (SDHC_FEREIS) Force Event for Command Timeout Error Position */ 1410 #define SDHC_FEREIS_CMDTEO_Msk (_UINT16_(0x1) << SDHC_FEREIS_CMDTEO_Pos) /* (SDHC_FEREIS) Force Event for Command Timeout Error Mask */ 1411 #define SDHC_FEREIS_CMDTEO(value) (SDHC_FEREIS_CMDTEO_Msk & (_UINT16_(value) << SDHC_FEREIS_CMDTEO_Pos)) /* Assigment of value for CMDTEO in the SDHC_FEREIS register */ 1412 #define SDHC_FEREIS_CMDTEO_NO_Val _UINT16_(0x0) /* (SDHC_FEREIS) No Interrupt */ 1413 #define SDHC_FEREIS_CMDTEO_YES_Val _UINT16_(0x1) /* (SDHC_FEREIS) Interrupt is generated */ 1414 #define SDHC_FEREIS_CMDTEO_NO (SDHC_FEREIS_CMDTEO_NO_Val << SDHC_FEREIS_CMDTEO_Pos) /* (SDHC_FEREIS) No Interrupt Position */ 1415 #define SDHC_FEREIS_CMDTEO_YES (SDHC_FEREIS_CMDTEO_YES_Val << SDHC_FEREIS_CMDTEO_Pos) /* (SDHC_FEREIS) Interrupt is generated Position */ 1416 #define SDHC_FEREIS_CMDCRC_Pos _UINT16_(1) /* (SDHC_FEREIS) Force Event for Command CRC Error Position */ 1417 #define SDHC_FEREIS_CMDCRC_Msk (_UINT16_(0x1) << SDHC_FEREIS_CMDCRC_Pos) /* (SDHC_FEREIS) Force Event for Command CRC Error Mask */ 1418 #define SDHC_FEREIS_CMDCRC(value) (SDHC_FEREIS_CMDCRC_Msk & (_UINT16_(value) << SDHC_FEREIS_CMDCRC_Pos)) /* Assigment of value for CMDCRC in the SDHC_FEREIS register */ 1419 #define SDHC_FEREIS_CMDCRC_NO_Val _UINT16_(0x0) /* (SDHC_FEREIS) No Interrupt */ 1420 #define SDHC_FEREIS_CMDCRC_YES_Val _UINT16_(0x1) /* (SDHC_FEREIS) Interrupt is generated */ 1421 #define SDHC_FEREIS_CMDCRC_NO (SDHC_FEREIS_CMDCRC_NO_Val << SDHC_FEREIS_CMDCRC_Pos) /* (SDHC_FEREIS) No Interrupt Position */ 1422 #define SDHC_FEREIS_CMDCRC_YES (SDHC_FEREIS_CMDCRC_YES_Val << SDHC_FEREIS_CMDCRC_Pos) /* (SDHC_FEREIS) Interrupt is generated Position */ 1423 #define SDHC_FEREIS_CMDEND_Pos _UINT16_(2) /* (SDHC_FEREIS) Force Event for Command End Bit Error Position */ 1424 #define SDHC_FEREIS_CMDEND_Msk (_UINT16_(0x1) << SDHC_FEREIS_CMDEND_Pos) /* (SDHC_FEREIS) Force Event for Command End Bit Error Mask */ 1425 #define SDHC_FEREIS_CMDEND(value) (SDHC_FEREIS_CMDEND_Msk & (_UINT16_(value) << SDHC_FEREIS_CMDEND_Pos)) /* Assigment of value for CMDEND in the SDHC_FEREIS register */ 1426 #define SDHC_FEREIS_CMDEND_NO_Val _UINT16_(0x0) /* (SDHC_FEREIS) No Interrupt */ 1427 #define SDHC_FEREIS_CMDEND_YES_Val _UINT16_(0x1) /* (SDHC_FEREIS) Interrupt is generated */ 1428 #define SDHC_FEREIS_CMDEND_NO (SDHC_FEREIS_CMDEND_NO_Val << SDHC_FEREIS_CMDEND_Pos) /* (SDHC_FEREIS) No Interrupt Position */ 1429 #define SDHC_FEREIS_CMDEND_YES (SDHC_FEREIS_CMDEND_YES_Val << SDHC_FEREIS_CMDEND_Pos) /* (SDHC_FEREIS) Interrupt is generated Position */ 1430 #define SDHC_FEREIS_CMDIDX_Pos _UINT16_(3) /* (SDHC_FEREIS) Force Event for Command Index Error Position */ 1431 #define SDHC_FEREIS_CMDIDX_Msk (_UINT16_(0x1) << SDHC_FEREIS_CMDIDX_Pos) /* (SDHC_FEREIS) Force Event for Command Index Error Mask */ 1432 #define SDHC_FEREIS_CMDIDX(value) (SDHC_FEREIS_CMDIDX_Msk & (_UINT16_(value) << SDHC_FEREIS_CMDIDX_Pos)) /* Assigment of value for CMDIDX in the SDHC_FEREIS register */ 1433 #define SDHC_FEREIS_CMDIDX_NO_Val _UINT16_(0x0) /* (SDHC_FEREIS) No Interrupt */ 1434 #define SDHC_FEREIS_CMDIDX_YES_Val _UINT16_(0x1) /* (SDHC_FEREIS) Interrupt is generated */ 1435 #define SDHC_FEREIS_CMDIDX_NO (SDHC_FEREIS_CMDIDX_NO_Val << SDHC_FEREIS_CMDIDX_Pos) /* (SDHC_FEREIS) No Interrupt Position */ 1436 #define SDHC_FEREIS_CMDIDX_YES (SDHC_FEREIS_CMDIDX_YES_Val << SDHC_FEREIS_CMDIDX_Pos) /* (SDHC_FEREIS) Interrupt is generated Position */ 1437 #define SDHC_FEREIS_DATTEO_Pos _UINT16_(4) /* (SDHC_FEREIS) Force Event for Data Timeout Error Position */ 1438 #define SDHC_FEREIS_DATTEO_Msk (_UINT16_(0x1) << SDHC_FEREIS_DATTEO_Pos) /* (SDHC_FEREIS) Force Event for Data Timeout Error Mask */ 1439 #define SDHC_FEREIS_DATTEO(value) (SDHC_FEREIS_DATTEO_Msk & (_UINT16_(value) << SDHC_FEREIS_DATTEO_Pos)) /* Assigment of value for DATTEO in the SDHC_FEREIS register */ 1440 #define SDHC_FEREIS_DATTEO_NO_Val _UINT16_(0x0) /* (SDHC_FEREIS) No Interrupt */ 1441 #define SDHC_FEREIS_DATTEO_YES_Val _UINT16_(0x1) /* (SDHC_FEREIS) Interrupt is generated */ 1442 #define SDHC_FEREIS_DATTEO_NO (SDHC_FEREIS_DATTEO_NO_Val << SDHC_FEREIS_DATTEO_Pos) /* (SDHC_FEREIS) No Interrupt Position */ 1443 #define SDHC_FEREIS_DATTEO_YES (SDHC_FEREIS_DATTEO_YES_Val << SDHC_FEREIS_DATTEO_Pos) /* (SDHC_FEREIS) Interrupt is generated Position */ 1444 #define SDHC_FEREIS_DATCRC_Pos _UINT16_(5) /* (SDHC_FEREIS) Force Event for Data CRC Error Position */ 1445 #define SDHC_FEREIS_DATCRC_Msk (_UINT16_(0x1) << SDHC_FEREIS_DATCRC_Pos) /* (SDHC_FEREIS) Force Event for Data CRC Error Mask */ 1446 #define SDHC_FEREIS_DATCRC(value) (SDHC_FEREIS_DATCRC_Msk & (_UINT16_(value) << SDHC_FEREIS_DATCRC_Pos)) /* Assigment of value for DATCRC in the SDHC_FEREIS register */ 1447 #define SDHC_FEREIS_DATCRC_NO_Val _UINT16_(0x0) /* (SDHC_FEREIS) No Interrupt */ 1448 #define SDHC_FEREIS_DATCRC_YES_Val _UINT16_(0x1) /* (SDHC_FEREIS) Interrupt is generated */ 1449 #define SDHC_FEREIS_DATCRC_NO (SDHC_FEREIS_DATCRC_NO_Val << SDHC_FEREIS_DATCRC_Pos) /* (SDHC_FEREIS) No Interrupt Position */ 1450 #define SDHC_FEREIS_DATCRC_YES (SDHC_FEREIS_DATCRC_YES_Val << SDHC_FEREIS_DATCRC_Pos) /* (SDHC_FEREIS) Interrupt is generated Position */ 1451 #define SDHC_FEREIS_DATEND_Pos _UINT16_(6) /* (SDHC_FEREIS) Force Event for Data End Bit Error Position */ 1452 #define SDHC_FEREIS_DATEND_Msk (_UINT16_(0x1) << SDHC_FEREIS_DATEND_Pos) /* (SDHC_FEREIS) Force Event for Data End Bit Error Mask */ 1453 #define SDHC_FEREIS_DATEND(value) (SDHC_FEREIS_DATEND_Msk & (_UINT16_(value) << SDHC_FEREIS_DATEND_Pos)) /* Assigment of value for DATEND in the SDHC_FEREIS register */ 1454 #define SDHC_FEREIS_DATEND_NO_Val _UINT16_(0x0) /* (SDHC_FEREIS) No Interrupt */ 1455 #define SDHC_FEREIS_DATEND_YES_Val _UINT16_(0x1) /* (SDHC_FEREIS) Interrupt is generated */ 1456 #define SDHC_FEREIS_DATEND_NO (SDHC_FEREIS_DATEND_NO_Val << SDHC_FEREIS_DATEND_Pos) /* (SDHC_FEREIS) No Interrupt Position */ 1457 #define SDHC_FEREIS_DATEND_YES (SDHC_FEREIS_DATEND_YES_Val << SDHC_FEREIS_DATEND_Pos) /* (SDHC_FEREIS) Interrupt is generated Position */ 1458 #define SDHC_FEREIS_CURLIM_Pos _UINT16_(7) /* (SDHC_FEREIS) Force Event for Current Limit Error Position */ 1459 #define SDHC_FEREIS_CURLIM_Msk (_UINT16_(0x1) << SDHC_FEREIS_CURLIM_Pos) /* (SDHC_FEREIS) Force Event for Current Limit Error Mask */ 1460 #define SDHC_FEREIS_CURLIM(value) (SDHC_FEREIS_CURLIM_Msk & (_UINT16_(value) << SDHC_FEREIS_CURLIM_Pos)) /* Assigment of value for CURLIM in the SDHC_FEREIS register */ 1461 #define SDHC_FEREIS_CURLIM_NO_Val _UINT16_(0x0) /* (SDHC_FEREIS) No Interrupt */ 1462 #define SDHC_FEREIS_CURLIM_YES_Val _UINT16_(0x1) /* (SDHC_FEREIS) Interrupt is generated */ 1463 #define SDHC_FEREIS_CURLIM_NO (SDHC_FEREIS_CURLIM_NO_Val << SDHC_FEREIS_CURLIM_Pos) /* (SDHC_FEREIS) No Interrupt Position */ 1464 #define SDHC_FEREIS_CURLIM_YES (SDHC_FEREIS_CURLIM_YES_Val << SDHC_FEREIS_CURLIM_Pos) /* (SDHC_FEREIS) Interrupt is generated Position */ 1465 #define SDHC_FEREIS_ACMD_Pos _UINT16_(8) /* (SDHC_FEREIS) Force Event for Auto CMD Error Position */ 1466 #define SDHC_FEREIS_ACMD_Msk (_UINT16_(0x1) << SDHC_FEREIS_ACMD_Pos) /* (SDHC_FEREIS) Force Event for Auto CMD Error Mask */ 1467 #define SDHC_FEREIS_ACMD(value) (SDHC_FEREIS_ACMD_Msk & (_UINT16_(value) << SDHC_FEREIS_ACMD_Pos)) /* Assigment of value for ACMD in the SDHC_FEREIS register */ 1468 #define SDHC_FEREIS_ACMD_NO_Val _UINT16_(0x0) /* (SDHC_FEREIS) No Interrupt */ 1469 #define SDHC_FEREIS_ACMD_YES_Val _UINT16_(0x1) /* (SDHC_FEREIS) Interrupt is generated */ 1470 #define SDHC_FEREIS_ACMD_NO (SDHC_FEREIS_ACMD_NO_Val << SDHC_FEREIS_ACMD_Pos) /* (SDHC_FEREIS) No Interrupt Position */ 1471 #define SDHC_FEREIS_ACMD_YES (SDHC_FEREIS_ACMD_YES_Val << SDHC_FEREIS_ACMD_Pos) /* (SDHC_FEREIS) Interrupt is generated Position */ 1472 #define SDHC_FEREIS_ADMA_Pos _UINT16_(9) /* (SDHC_FEREIS) Force Event for ADMA Error Position */ 1473 #define SDHC_FEREIS_ADMA_Msk (_UINT16_(0x1) << SDHC_FEREIS_ADMA_Pos) /* (SDHC_FEREIS) Force Event for ADMA Error Mask */ 1474 #define SDHC_FEREIS_ADMA(value) (SDHC_FEREIS_ADMA_Msk & (_UINT16_(value) << SDHC_FEREIS_ADMA_Pos)) /* Assigment of value for ADMA in the SDHC_FEREIS register */ 1475 #define SDHC_FEREIS_ADMA_NO_Val _UINT16_(0x0) /* (SDHC_FEREIS) No Interrupt */ 1476 #define SDHC_FEREIS_ADMA_YES_Val _UINT16_(0x1) /* (SDHC_FEREIS) Interrupt is generated */ 1477 #define SDHC_FEREIS_ADMA_NO (SDHC_FEREIS_ADMA_NO_Val << SDHC_FEREIS_ADMA_Pos) /* (SDHC_FEREIS) No Interrupt Position */ 1478 #define SDHC_FEREIS_ADMA_YES (SDHC_FEREIS_ADMA_YES_Val << SDHC_FEREIS_ADMA_Pos) /* (SDHC_FEREIS) Interrupt is generated Position */ 1479 #define SDHC_FEREIS_BOOTAE_Pos _UINT16_(12) /* (SDHC_FEREIS) Force Event for Boot Acknowledge Error Position */ 1480 #define SDHC_FEREIS_BOOTAE_Msk (_UINT16_(0x1) << SDHC_FEREIS_BOOTAE_Pos) /* (SDHC_FEREIS) Force Event for Boot Acknowledge Error Mask */ 1481 #define SDHC_FEREIS_BOOTAE(value) (SDHC_FEREIS_BOOTAE_Msk & (_UINT16_(value) << SDHC_FEREIS_BOOTAE_Pos)) /* Assigment of value for BOOTAE in the SDHC_FEREIS register */ 1482 #define SDHC_FEREIS_BOOTAE_NO_Val _UINT16_(0x0) /* (SDHC_FEREIS) No Interrupt */ 1483 #define SDHC_FEREIS_BOOTAE_YES_Val _UINT16_(0x1) /* (SDHC_FEREIS) Interrupt is generated */ 1484 #define SDHC_FEREIS_BOOTAE_NO (SDHC_FEREIS_BOOTAE_NO_Val << SDHC_FEREIS_BOOTAE_Pos) /* (SDHC_FEREIS) No Interrupt Position */ 1485 #define SDHC_FEREIS_BOOTAE_YES (SDHC_FEREIS_BOOTAE_YES_Val << SDHC_FEREIS_BOOTAE_Pos) /* (SDHC_FEREIS) Interrupt is generated Position */ 1486 #define SDHC_FEREIS_Msk _UINT16_(0x13FF) /* (SDHC_FEREIS) Register Mask */ 1487 1488 1489 /* -------- SDHC_AESR : (SDHC Offset: 0x54) ( R/ 8) ADMA Error Status -------- */ 1490 #define SDHC_AESR_RESETVALUE _UINT8_(0x00) /* (SDHC_AESR) ADMA Error Status Reset Value */ 1491 1492 #define SDHC_AESR_ERRST_Pos _UINT8_(0) /* (SDHC_AESR) ADMA Error State Position */ 1493 #define SDHC_AESR_ERRST_Msk (_UINT8_(0x3) << SDHC_AESR_ERRST_Pos) /* (SDHC_AESR) ADMA Error State Mask */ 1494 #define SDHC_AESR_ERRST(value) (SDHC_AESR_ERRST_Msk & (_UINT8_(value) << SDHC_AESR_ERRST_Pos)) /* Assigment of value for ERRST in the SDHC_AESR register */ 1495 #define SDHC_AESR_ERRST_STOP_Val _UINT8_(0x0) /* (SDHC_AESR) ST_STOP (Stop DMA) */ 1496 #define SDHC_AESR_ERRST_FDS_Val _UINT8_(0x1) /* (SDHC_AESR) ST_FDS (Fetch Descriptor) */ 1497 #define SDHC_AESR_ERRST_TFR_Val _UINT8_(0x3) /* (SDHC_AESR) ST_TFR (Transfer Data) */ 1498 #define SDHC_AESR_ERRST_STOP (SDHC_AESR_ERRST_STOP_Val << SDHC_AESR_ERRST_Pos) /* (SDHC_AESR) ST_STOP (Stop DMA) Position */ 1499 #define SDHC_AESR_ERRST_FDS (SDHC_AESR_ERRST_FDS_Val << SDHC_AESR_ERRST_Pos) /* (SDHC_AESR) ST_FDS (Fetch Descriptor) Position */ 1500 #define SDHC_AESR_ERRST_TFR (SDHC_AESR_ERRST_TFR_Val << SDHC_AESR_ERRST_Pos) /* (SDHC_AESR) ST_TFR (Transfer Data) Position */ 1501 #define SDHC_AESR_LMIS_Pos _UINT8_(2) /* (SDHC_AESR) ADMA Length Mismatch Error Position */ 1502 #define SDHC_AESR_LMIS_Msk (_UINT8_(0x1) << SDHC_AESR_LMIS_Pos) /* (SDHC_AESR) ADMA Length Mismatch Error Mask */ 1503 #define SDHC_AESR_LMIS(value) (SDHC_AESR_LMIS_Msk & (_UINT8_(value) << SDHC_AESR_LMIS_Pos)) /* Assigment of value for LMIS in the SDHC_AESR register */ 1504 #define SDHC_AESR_LMIS_NO_Val _UINT8_(0x0) /* (SDHC_AESR) No Error */ 1505 #define SDHC_AESR_LMIS_YES_Val _UINT8_(0x1) /* (SDHC_AESR) Error */ 1506 #define SDHC_AESR_LMIS_NO (SDHC_AESR_LMIS_NO_Val << SDHC_AESR_LMIS_Pos) /* (SDHC_AESR) No Error Position */ 1507 #define SDHC_AESR_LMIS_YES (SDHC_AESR_LMIS_YES_Val << SDHC_AESR_LMIS_Pos) /* (SDHC_AESR) Error Position */ 1508 #define SDHC_AESR_Msk _UINT8_(0x07) /* (SDHC_AESR) Register Mask */ 1509 1510 1511 /* -------- SDHC_ASAR : (SDHC Offset: 0x58) (R/W 32) ADMA System Address -------- */ 1512 #define SDHC_ASAR_RESETVALUE _UINT32_(0x00) /* (SDHC_ASAR) ADMA System Address Reset Value */ 1513 1514 #define SDHC_ASAR_ADMASA_Pos _UINT32_(0) /* (SDHC_ASAR) ADMA System Address Position */ 1515 #define SDHC_ASAR_ADMASA_Msk (_UINT32_(0xFFFFFFFF) << SDHC_ASAR_ADMASA_Pos) /* (SDHC_ASAR) ADMA System Address Mask */ 1516 #define SDHC_ASAR_ADMASA(value) (SDHC_ASAR_ADMASA_Msk & (_UINT32_(value) << SDHC_ASAR_ADMASA_Pos)) /* Assigment of value for ADMASA in the SDHC_ASAR register */ 1517 #define SDHC_ASAR_Msk _UINT32_(0xFFFFFFFF) /* (SDHC_ASAR) Register Mask */ 1518 1519 1520 /* -------- SDHC_PVR : (SDHC Offset: 0x60) (R/W 16) Preset Value n -------- */ 1521 #define SDHC_PVR_RESETVALUE _UINT16_(0x00) /* (SDHC_PVR) Preset Value n Reset Value */ 1522 1523 #define SDHC_PVR_SDCLKFSEL_Pos _UINT16_(0) /* (SDHC_PVR) SDCLK Frequency Select Value for Initialization Position */ 1524 #define SDHC_PVR_SDCLKFSEL_Msk (_UINT16_(0x3FF) << SDHC_PVR_SDCLKFSEL_Pos) /* (SDHC_PVR) SDCLK Frequency Select Value for Initialization Mask */ 1525 #define SDHC_PVR_SDCLKFSEL(value) (SDHC_PVR_SDCLKFSEL_Msk & (_UINT16_(value) << SDHC_PVR_SDCLKFSEL_Pos)) /* Assigment of value for SDCLKFSEL in the SDHC_PVR register */ 1526 #define SDHC_PVR_CLKGSEL_Pos _UINT16_(10) /* (SDHC_PVR) Clock Generator Select Value for Initialization Position */ 1527 #define SDHC_PVR_CLKGSEL_Msk (_UINT16_(0x1) << SDHC_PVR_CLKGSEL_Pos) /* (SDHC_PVR) Clock Generator Select Value for Initialization Mask */ 1528 #define SDHC_PVR_CLKGSEL(value) (SDHC_PVR_CLKGSEL_Msk & (_UINT16_(value) << SDHC_PVR_CLKGSEL_Pos)) /* Assigment of value for CLKGSEL in the SDHC_PVR register */ 1529 #define SDHC_PVR_CLKGSEL_DIV_Val _UINT16_(0x0) /* (SDHC_PVR) Host Controller Ver2.00 Compatible Clock Generator (Divider) */ 1530 #define SDHC_PVR_CLKGSEL_PROG_Val _UINT16_(0x1) /* (SDHC_PVR) Programmable Clock Generator */ 1531 #define SDHC_PVR_CLKGSEL_DIV (SDHC_PVR_CLKGSEL_DIV_Val << SDHC_PVR_CLKGSEL_Pos) /* (SDHC_PVR) Host Controller Ver2.00 Compatible Clock Generator (Divider) Position */ 1532 #define SDHC_PVR_CLKGSEL_PROG (SDHC_PVR_CLKGSEL_PROG_Val << SDHC_PVR_CLKGSEL_Pos) /* (SDHC_PVR) Programmable Clock Generator Position */ 1533 #define SDHC_PVR_DRVSEL_Pos _UINT16_(14) /* (SDHC_PVR) Driver Strength Select Value for Initialization Position */ 1534 #define SDHC_PVR_DRVSEL_Msk (_UINT16_(0x3) << SDHC_PVR_DRVSEL_Pos) /* (SDHC_PVR) Driver Strength Select Value for Initialization Mask */ 1535 #define SDHC_PVR_DRVSEL(value) (SDHC_PVR_DRVSEL_Msk & (_UINT16_(value) << SDHC_PVR_DRVSEL_Pos)) /* Assigment of value for DRVSEL in the SDHC_PVR register */ 1536 #define SDHC_PVR_DRVSEL_B_Val _UINT16_(0x0) /* (SDHC_PVR) Driver Type B is Selected */ 1537 #define SDHC_PVR_DRVSEL_A_Val _UINT16_(0x1) /* (SDHC_PVR) Driver Type A is Selected */ 1538 #define SDHC_PVR_DRVSEL_C_Val _UINT16_(0x2) /* (SDHC_PVR) Driver Type C is Selected */ 1539 #define SDHC_PVR_DRVSEL_D_Val _UINT16_(0x3) /* (SDHC_PVR) Driver Type D is Selected */ 1540 #define SDHC_PVR_DRVSEL_B (SDHC_PVR_DRVSEL_B_Val << SDHC_PVR_DRVSEL_Pos) /* (SDHC_PVR) Driver Type B is Selected Position */ 1541 #define SDHC_PVR_DRVSEL_A (SDHC_PVR_DRVSEL_A_Val << SDHC_PVR_DRVSEL_Pos) /* (SDHC_PVR) Driver Type A is Selected Position */ 1542 #define SDHC_PVR_DRVSEL_C (SDHC_PVR_DRVSEL_C_Val << SDHC_PVR_DRVSEL_Pos) /* (SDHC_PVR) Driver Type C is Selected Position */ 1543 #define SDHC_PVR_DRVSEL_D (SDHC_PVR_DRVSEL_D_Val << SDHC_PVR_DRVSEL_Pos) /* (SDHC_PVR) Driver Type D is Selected Position */ 1544 #define SDHC_PVR_Msk _UINT16_(0xC7FF) /* (SDHC_PVR) Register Mask */ 1545 1546 1547 /* -------- SDHC_SISR : (SDHC Offset: 0xFC) ( R/ 16) Slot Interrupt Status -------- */ 1548 #define SDHC_SISR_RESETVALUE _UINT16_(0x00) /* (SDHC_SISR) Slot Interrupt Status Reset Value */ 1549 1550 #define SDHC_SISR_INTSSL_Pos _UINT16_(0) /* (SDHC_SISR) Interrupt Signal for Each SDHC Slot Position */ 1551 #define SDHC_SISR_INTSSL_Msk (_UINT16_(0x3) << SDHC_SISR_INTSSL_Pos) /* (SDHC_SISR) Interrupt Signal for Each SDHC Slot Mask */ 1552 #define SDHC_SISR_INTSSL(value) (SDHC_SISR_INTSSL_Msk & (_UINT16_(value) << SDHC_SISR_INTSSL_Pos)) /* Assigment of value for INTSSL in the SDHC_SISR register */ 1553 #define SDHC_SISR_Msk _UINT16_(0x0003) /* (SDHC_SISR) Register Mask */ 1554 1555 1556 /* -------- SDHC_HCVR : (SDHC Offset: 0xFE) ( R/ 16) Host Controller Version -------- */ 1557 #define SDHC_HCVR_RESETVALUE _UINT16_(0x1802) /* (SDHC_HCVR) Host Controller Version Reset Value */ 1558 1559 #define SDHC_HCVR_SVER_Pos _UINT16_(0) /* (SDHC_HCVR) Spec Version Position */ 1560 #define SDHC_HCVR_SVER_Msk (_UINT16_(0xFF) << SDHC_HCVR_SVER_Pos) /* (SDHC_HCVR) Spec Version Mask */ 1561 #define SDHC_HCVR_SVER(value) (SDHC_HCVR_SVER_Msk & (_UINT16_(value) << SDHC_HCVR_SVER_Pos)) /* Assigment of value for SVER in the SDHC_HCVR register */ 1562 #define SDHC_HCVR_VVER_Pos _UINT16_(8) /* (SDHC_HCVR) Vendor Version Position */ 1563 #define SDHC_HCVR_VVER_Msk (_UINT16_(0xFF) << SDHC_HCVR_VVER_Pos) /* (SDHC_HCVR) Vendor Version Mask */ 1564 #define SDHC_HCVR_VVER(value) (SDHC_HCVR_VVER_Msk & (_UINT16_(value) << SDHC_HCVR_VVER_Pos)) /* Assigment of value for VVER in the SDHC_HCVR register */ 1565 #define SDHC_HCVR_Msk _UINT16_(0xFFFF) /* (SDHC_HCVR) Register Mask */ 1566 1567 1568 /* -------- SDHC_APSR : (SDHC Offset: 0x200) ( R/ 32) Additional Present State Register -------- */ 1569 #define SDHC_APSR_RESETVALUE _UINT32_(0x0F) /* (SDHC_APSR) Additional Present State Register Reset Value */ 1570 1571 #define SDHC_APSR_HDATLL_Pos _UINT32_(0) /* (SDHC_APSR) High Line Level Position */ 1572 #define SDHC_APSR_HDATLL_Msk (_UINT32_(0xF) << SDHC_APSR_HDATLL_Pos) /* (SDHC_APSR) High Line Level Mask */ 1573 #define SDHC_APSR_HDATLL(value) (SDHC_APSR_HDATLL_Msk & (_UINT32_(value) << SDHC_APSR_HDATLL_Pos)) /* Assigment of value for HDATLL in the SDHC_APSR register */ 1574 #define SDHC_APSR_Msk _UINT32_(0x0000000F) /* (SDHC_APSR) Register Mask */ 1575 1576 1577 /* -------- SDHC_MC1R : (SDHC Offset: 0x204) (R/W 8) MMC Control 1 -------- */ 1578 #define SDHC_MC1R_RESETVALUE _UINT8_(0x00) /* (SDHC_MC1R) MMC Control 1 Reset Value */ 1579 1580 #define SDHC_MC1R_CMDTYP_Pos _UINT8_(0) /* (SDHC_MC1R) e.MMC Command Type Position */ 1581 #define SDHC_MC1R_CMDTYP_Msk (_UINT8_(0x3) << SDHC_MC1R_CMDTYP_Pos) /* (SDHC_MC1R) e.MMC Command Type Mask */ 1582 #define SDHC_MC1R_CMDTYP(value) (SDHC_MC1R_CMDTYP_Msk & (_UINT8_(value) << SDHC_MC1R_CMDTYP_Pos)) /* Assigment of value for CMDTYP in the SDHC_MC1R register */ 1583 #define SDHC_MC1R_CMDTYP_NORMAL_Val _UINT8_(0x0) /* (SDHC_MC1R) Not a MMC specific command */ 1584 #define SDHC_MC1R_CMDTYP_WAITIRQ_Val _UINT8_(0x1) /* (SDHC_MC1R) Wait IRQ Command */ 1585 #define SDHC_MC1R_CMDTYP_STREAM_Val _UINT8_(0x2) /* (SDHC_MC1R) Stream Command */ 1586 #define SDHC_MC1R_CMDTYP_BOOT_Val _UINT8_(0x3) /* (SDHC_MC1R) Boot Command */ 1587 #define SDHC_MC1R_CMDTYP_NORMAL (SDHC_MC1R_CMDTYP_NORMAL_Val << SDHC_MC1R_CMDTYP_Pos) /* (SDHC_MC1R) Not a MMC specific command Position */ 1588 #define SDHC_MC1R_CMDTYP_WAITIRQ (SDHC_MC1R_CMDTYP_WAITIRQ_Val << SDHC_MC1R_CMDTYP_Pos) /* (SDHC_MC1R) Wait IRQ Command Position */ 1589 #define SDHC_MC1R_CMDTYP_STREAM (SDHC_MC1R_CMDTYP_STREAM_Val << SDHC_MC1R_CMDTYP_Pos) /* (SDHC_MC1R) Stream Command Position */ 1590 #define SDHC_MC1R_CMDTYP_BOOT (SDHC_MC1R_CMDTYP_BOOT_Val << SDHC_MC1R_CMDTYP_Pos) /* (SDHC_MC1R) Boot Command Position */ 1591 #define SDHC_MC1R_DDR_Pos _UINT8_(3) /* (SDHC_MC1R) e.MMC HSDDR Mode Position */ 1592 #define SDHC_MC1R_DDR_Msk (_UINT8_(0x1) << SDHC_MC1R_DDR_Pos) /* (SDHC_MC1R) e.MMC HSDDR Mode Mask */ 1593 #define SDHC_MC1R_DDR(value) (SDHC_MC1R_DDR_Msk & (_UINT8_(value) << SDHC_MC1R_DDR_Pos)) /* Assigment of value for DDR in the SDHC_MC1R register */ 1594 #define SDHC_MC1R_OPD_Pos _UINT8_(4) /* (SDHC_MC1R) e.MMC Open Drain Mode Position */ 1595 #define SDHC_MC1R_OPD_Msk (_UINT8_(0x1) << SDHC_MC1R_OPD_Pos) /* (SDHC_MC1R) e.MMC Open Drain Mode Mask */ 1596 #define SDHC_MC1R_OPD(value) (SDHC_MC1R_OPD_Msk & (_UINT8_(value) << SDHC_MC1R_OPD_Pos)) /* Assigment of value for OPD in the SDHC_MC1R register */ 1597 #define SDHC_MC1R_BOOTA_Pos _UINT8_(5) /* (SDHC_MC1R) e.MMC Boot Acknowledge Enable Position */ 1598 #define SDHC_MC1R_BOOTA_Msk (_UINT8_(0x1) << SDHC_MC1R_BOOTA_Pos) /* (SDHC_MC1R) e.MMC Boot Acknowledge Enable Mask */ 1599 #define SDHC_MC1R_BOOTA(value) (SDHC_MC1R_BOOTA_Msk & (_UINT8_(value) << SDHC_MC1R_BOOTA_Pos)) /* Assigment of value for BOOTA in the SDHC_MC1R register */ 1600 #define SDHC_MC1R_RSTN_Pos _UINT8_(6) /* (SDHC_MC1R) e.MMC Reset Signal Position */ 1601 #define SDHC_MC1R_RSTN_Msk (_UINT8_(0x1) << SDHC_MC1R_RSTN_Pos) /* (SDHC_MC1R) e.MMC Reset Signal Mask */ 1602 #define SDHC_MC1R_RSTN(value) (SDHC_MC1R_RSTN_Msk & (_UINT8_(value) << SDHC_MC1R_RSTN_Pos)) /* Assigment of value for RSTN in the SDHC_MC1R register */ 1603 #define SDHC_MC1R_FCD_Pos _UINT8_(7) /* (SDHC_MC1R) e.MMC Force Card Detect Position */ 1604 #define SDHC_MC1R_FCD_Msk (_UINT8_(0x1) << SDHC_MC1R_FCD_Pos) /* (SDHC_MC1R) e.MMC Force Card Detect Mask */ 1605 #define SDHC_MC1R_FCD(value) (SDHC_MC1R_FCD_Msk & (_UINT8_(value) << SDHC_MC1R_FCD_Pos)) /* Assigment of value for FCD in the SDHC_MC1R register */ 1606 #define SDHC_MC1R_Msk _UINT8_(0xFB) /* (SDHC_MC1R) Register Mask */ 1607 1608 1609 /* -------- SDHC_MC2R : (SDHC Offset: 0x205) ( /W 8) MMC Control 2 -------- */ 1610 #define SDHC_MC2R_RESETVALUE _UINT8_(0x00) /* (SDHC_MC2R) MMC Control 2 Reset Value */ 1611 1612 #define SDHC_MC2R_SRESP_Pos _UINT8_(0) /* (SDHC_MC2R) e.MMC Abort Wait IRQ Position */ 1613 #define SDHC_MC2R_SRESP_Msk (_UINT8_(0x1) << SDHC_MC2R_SRESP_Pos) /* (SDHC_MC2R) e.MMC Abort Wait IRQ Mask */ 1614 #define SDHC_MC2R_SRESP(value) (SDHC_MC2R_SRESP_Msk & (_UINT8_(value) << SDHC_MC2R_SRESP_Pos)) /* Assigment of value for SRESP in the SDHC_MC2R register */ 1615 #define SDHC_MC2R_ABOOT_Pos _UINT8_(1) /* (SDHC_MC2R) e.MMC Abort Boot Position */ 1616 #define SDHC_MC2R_ABOOT_Msk (_UINT8_(0x1) << SDHC_MC2R_ABOOT_Pos) /* (SDHC_MC2R) e.MMC Abort Boot Mask */ 1617 #define SDHC_MC2R_ABOOT(value) (SDHC_MC2R_ABOOT_Msk & (_UINT8_(value) << SDHC_MC2R_ABOOT_Pos)) /* Assigment of value for ABOOT in the SDHC_MC2R register */ 1618 #define SDHC_MC2R_Msk _UINT8_(0x03) /* (SDHC_MC2R) Register Mask */ 1619 1620 1621 /* -------- SDHC_ACR : (SDHC Offset: 0x208) (R/W 32) AHB Control -------- */ 1622 #define SDHC_ACR_RESETVALUE _UINT32_(0x00) /* (SDHC_ACR) AHB Control Reset Value */ 1623 1624 #define SDHC_ACR_BMAX_Pos _UINT32_(0) /* (SDHC_ACR) AHB Maximum Burst Position */ 1625 #define SDHC_ACR_BMAX_Msk (_UINT32_(0x3) << SDHC_ACR_BMAX_Pos) /* (SDHC_ACR) AHB Maximum Burst Mask */ 1626 #define SDHC_ACR_BMAX(value) (SDHC_ACR_BMAX_Msk & (_UINT32_(value) << SDHC_ACR_BMAX_Pos)) /* Assigment of value for BMAX in the SDHC_ACR register */ 1627 #define SDHC_ACR_BMAX_INCR16_Val _UINT32_(0x0) /* (SDHC_ACR) */ 1628 #define SDHC_ACR_BMAX_INCR8_Val _UINT32_(0x1) /* (SDHC_ACR) */ 1629 #define SDHC_ACR_BMAX_INCR4_Val _UINT32_(0x2) /* (SDHC_ACR) */ 1630 #define SDHC_ACR_BMAX_SINGLE_Val _UINT32_(0x3) /* (SDHC_ACR) */ 1631 #define SDHC_ACR_BMAX_INCR16 (SDHC_ACR_BMAX_INCR16_Val << SDHC_ACR_BMAX_Pos) /* (SDHC_ACR) Position */ 1632 #define SDHC_ACR_BMAX_INCR8 (SDHC_ACR_BMAX_INCR8_Val << SDHC_ACR_BMAX_Pos) /* (SDHC_ACR) Position */ 1633 #define SDHC_ACR_BMAX_INCR4 (SDHC_ACR_BMAX_INCR4_Val << SDHC_ACR_BMAX_Pos) /* (SDHC_ACR) Position */ 1634 #define SDHC_ACR_BMAX_SINGLE (SDHC_ACR_BMAX_SINGLE_Val << SDHC_ACR_BMAX_Pos) /* (SDHC_ACR) Position */ 1635 #define SDHC_ACR_Msk _UINT32_(0x00000003) /* (SDHC_ACR) Register Mask */ 1636 1637 1638 /* -------- SDHC_CC2R : (SDHC Offset: 0x20C) (R/W 32) Clock Control 2 -------- */ 1639 #define SDHC_CC2R_RESETVALUE _UINT32_(0x00) /* (SDHC_CC2R) Clock Control 2 Reset Value */ 1640 1641 #define SDHC_CC2R_FSDCLKD_Pos _UINT32_(0) /* (SDHC_CC2R) Force SDCK Disabled Position */ 1642 #define SDHC_CC2R_FSDCLKD_Msk (_UINT32_(0x1) << SDHC_CC2R_FSDCLKD_Pos) /* (SDHC_CC2R) Force SDCK Disabled Mask */ 1643 #define SDHC_CC2R_FSDCLKD(value) (SDHC_CC2R_FSDCLKD_Msk & (_UINT32_(value) << SDHC_CC2R_FSDCLKD_Pos)) /* Assigment of value for FSDCLKD in the SDHC_CC2R register */ 1644 #define SDHC_CC2R_FSDCLKD_NOEFFECT_Val _UINT32_(0x0) /* (SDHC_CC2R) No effect */ 1645 #define SDHC_CC2R_FSDCLKD_DISABLE_Val _UINT32_(0x1) /* (SDHC_CC2R) SDCLK can be stopped at any time after DATA transfer.SDCLK enable forcing for 8 SDCLK cycles is disabled */ 1646 #define SDHC_CC2R_FSDCLKD_NOEFFECT (SDHC_CC2R_FSDCLKD_NOEFFECT_Val << SDHC_CC2R_FSDCLKD_Pos) /* (SDHC_CC2R) No effect Position */ 1647 #define SDHC_CC2R_FSDCLKD_DISABLE (SDHC_CC2R_FSDCLKD_DISABLE_Val << SDHC_CC2R_FSDCLKD_Pos) /* (SDHC_CC2R) SDCLK can be stopped at any time after DATA transfer.SDCLK enable forcing for 8 SDCLK cycles is disabled Position */ 1648 #define SDHC_CC2R_Msk _UINT32_(0x00000001) /* (SDHC_CC2R) Register Mask */ 1649 1650 1651 /* -------- SDHC_CACR : (SDHC Offset: 0x230) (R/W 32) Capabilities Control -------- */ 1652 #define SDHC_CACR_RESETVALUE _UINT32_(0x00) /* (SDHC_CACR) Capabilities Control Reset Value */ 1653 1654 #define SDHC_CACR_CAPWREN_Pos _UINT32_(0) /* (SDHC_CACR) Capabilities Registers Write Enable (Required to write the correct frequencies in the Capabilities Registers) Position */ 1655 #define SDHC_CACR_CAPWREN_Msk (_UINT32_(0x1) << SDHC_CACR_CAPWREN_Pos) /* (SDHC_CACR) Capabilities Registers Write Enable (Required to write the correct frequencies in the Capabilities Registers) Mask */ 1656 #define SDHC_CACR_CAPWREN(value) (SDHC_CACR_CAPWREN_Msk & (_UINT32_(value) << SDHC_CACR_CAPWREN_Pos)) /* Assigment of value for CAPWREN in the SDHC_CACR register */ 1657 #define SDHC_CACR_KEY_Pos _UINT32_(8) /* (SDHC_CACR) Key (0x46) Position */ 1658 #define SDHC_CACR_KEY_Msk (_UINT32_(0xFF) << SDHC_CACR_KEY_Pos) /* (SDHC_CACR) Key (0x46) Mask */ 1659 #define SDHC_CACR_KEY(value) (SDHC_CACR_KEY_Msk & (_UINT32_(value) << SDHC_CACR_KEY_Pos)) /* Assigment of value for KEY in the SDHC_CACR register */ 1660 #define SDHC_CACR_KEY_KEY_Val _UINT32_(0x46) /* (SDHC_CACR) Key */ 1661 #define SDHC_CACR_KEY_KEY (SDHC_CACR_KEY_KEY_Val << SDHC_CACR_KEY_Pos) /* (SDHC_CACR) Key Position */ 1662 #define SDHC_CACR_Msk _UINT32_(0x0000FF01) /* (SDHC_CACR) Register Mask */ 1663 1664 1665 /* -------- SDHC_DBGR : (SDHC Offset: 0x234) (R/W 8) Debug -------- */ 1666 #define SDHC_DBGR_RESETVALUE _UINT8_(0x00) /* (SDHC_DBGR) Debug Reset Value */ 1667 1668 #define SDHC_DBGR_NIDBG_Pos _UINT8_(0) /* (SDHC_DBGR) Non-intrusive debug enable Position */ 1669 #define SDHC_DBGR_NIDBG_Msk (_UINT8_(0x1) << SDHC_DBGR_NIDBG_Pos) /* (SDHC_DBGR) Non-intrusive debug enable Mask */ 1670 #define SDHC_DBGR_NIDBG(value) (SDHC_DBGR_NIDBG_Msk & (_UINT8_(value) << SDHC_DBGR_NIDBG_Pos)) /* Assigment of value for NIDBG in the SDHC_DBGR register */ 1671 #define SDHC_DBGR_NIDBG_IDBG_Val _UINT8_(0x0) /* (SDHC_DBGR) Debugging is intrusive (reads of BDPR from debugger are considered and increment the internal buffer pointer) */ 1672 #define SDHC_DBGR_NIDBG_NIDBG_Val _UINT8_(0x1) /* (SDHC_DBGR) Debugging is not intrusive (reads of BDPR from debugger are discarded and do not increment the internal buffer pointer) */ 1673 #define SDHC_DBGR_NIDBG_IDBG (SDHC_DBGR_NIDBG_IDBG_Val << SDHC_DBGR_NIDBG_Pos) /* (SDHC_DBGR) Debugging is intrusive (reads of BDPR from debugger are considered and increment the internal buffer pointer) Position */ 1674 #define SDHC_DBGR_NIDBG_NIDBG (SDHC_DBGR_NIDBG_NIDBG_Val << SDHC_DBGR_NIDBG_Pos) /* (SDHC_DBGR) Debugging is not intrusive (reads of BDPR from debugger are discarded and do not increment the internal buffer pointer) Position */ 1675 #define SDHC_DBGR_Msk _UINT8_(0x01) /* (SDHC_DBGR) Register Mask */ 1676 1677 1678 /** \brief SDHC register offsets definitions */ 1679 #define SDHC_SSAR_REG_OFST _UINT32_(0x00) /* (SDHC_SSAR) SDMA System Address / Argument 2 Offset */ 1680 #define SDHC_BSR_REG_OFST _UINT32_(0x04) /* (SDHC_BSR) Block Size Offset */ 1681 #define SDHC_BCR_REG_OFST _UINT32_(0x06) /* (SDHC_BCR) Block Count Offset */ 1682 #define SDHC_ARG1R_REG_OFST _UINT32_(0x08) /* (SDHC_ARG1R) Argument 1 Offset */ 1683 #define SDHC_TMR_REG_OFST _UINT32_(0x0C) /* (SDHC_TMR) Transfer Mode Offset */ 1684 #define SDHC_CR_REG_OFST _UINT32_(0x0E) /* (SDHC_CR) Command Offset */ 1685 #define SDHC_RR_REG_OFST _UINT32_(0x10) /* (SDHC_RR) Response Offset */ 1686 #define SDHC_RR0_REG_OFST _UINT32_(0x10) /* (SDHC_RR0) Response Offset */ 1687 #define SDHC_RR1_REG_OFST _UINT32_(0x14) /* (SDHC_RR1) Response Offset */ 1688 #define SDHC_RR2_REG_OFST _UINT32_(0x18) /* (SDHC_RR2) Response Offset */ 1689 #define SDHC_RR3_REG_OFST _UINT32_(0x1C) /* (SDHC_RR3) Response Offset */ 1690 #define SDHC_BDPR_REG_OFST _UINT32_(0x20) /* (SDHC_BDPR) Buffer Data Port Offset */ 1691 #define SDHC_PSR_REG_OFST _UINT32_(0x24) /* (SDHC_PSR) Present State Offset */ 1692 #define SDHC_HC1R_REG_OFST _UINT32_(0x28) /* (SDHC_HC1R) Host Control 1 Offset */ 1693 #define SDHC_PCR_REG_OFST _UINT32_(0x29) /* (SDHC_PCR) Power Control Offset */ 1694 #define SDHC_BGCR_REG_OFST _UINT32_(0x2A) /* (SDHC_BGCR) Block Gap Control Offset */ 1695 #define SDHC_WCR_REG_OFST _UINT32_(0x2B) /* (SDHC_WCR) Wakeup Control Offset */ 1696 #define SDHC_CCR_REG_OFST _UINT32_(0x2C) /* (SDHC_CCR) Clock Control Offset */ 1697 #define SDHC_TCR_REG_OFST _UINT32_(0x2E) /* (SDHC_TCR) Timeout Control Offset */ 1698 #define SDHC_SRR_REG_OFST _UINT32_(0x2F) /* (SDHC_SRR) Software Reset Offset */ 1699 #define SDHC_NISTR_REG_OFST _UINT32_(0x30) /* (SDHC_NISTR) Normal Interrupt Status Offset */ 1700 #define SDHC_EISTR_REG_OFST _UINT32_(0x32) /* (SDHC_EISTR) Error Interrupt Status Offset */ 1701 #define SDHC_NISTER_REG_OFST _UINT32_(0x34) /* (SDHC_NISTER) Normal Interrupt Status Enable Offset */ 1702 #define SDHC_EISTER_REG_OFST _UINT32_(0x36) /* (SDHC_EISTER) Error Interrupt Status Enable Offset */ 1703 #define SDHC_NISIER_REG_OFST _UINT32_(0x38) /* (SDHC_NISIER) Normal Interrupt Signal Enable Offset */ 1704 #define SDHC_EISIER_REG_OFST _UINT32_(0x3A) /* (SDHC_EISIER) Error Interrupt Signal Enable Offset */ 1705 #define SDHC_ACESR_REG_OFST _UINT32_(0x3C) /* (SDHC_ACESR) Auto CMD Error Status Offset */ 1706 #define SDHC_HC2R_REG_OFST _UINT32_(0x3E) /* (SDHC_HC2R) Host Control 2 Offset */ 1707 #define SDHC_CA0R_REG_OFST _UINT32_(0x40) /* (SDHC_CA0R) Capabilities 0 Offset */ 1708 #define SDHC_CA1R_REG_OFST _UINT32_(0x44) /* (SDHC_CA1R) Capabilities 1 Offset */ 1709 #define SDHC_MCCAR_REG_OFST _UINT32_(0x48) /* (SDHC_MCCAR) Maximum Current Capabilities Offset */ 1710 #define SDHC_FERACES_REG_OFST _UINT32_(0x50) /* (SDHC_FERACES) Force Event for Auto CMD Error Status Offset */ 1711 #define SDHC_FEREIS_REG_OFST _UINT32_(0x52) /* (SDHC_FEREIS) Force Event for Error Interrupt Status Offset */ 1712 #define SDHC_AESR_REG_OFST _UINT32_(0x54) /* (SDHC_AESR) ADMA Error Status Offset */ 1713 #define SDHC_ASAR_REG_OFST _UINT32_(0x58) /* (SDHC_ASAR) ADMA System Address Offset */ 1714 #define SDHC_ASAR0_REG_OFST _UINT32_(0x58) /* (SDHC_ASAR0) ADMA System Address Offset */ 1715 #define SDHC_PVR_REG_OFST _UINT32_(0x60) /* (SDHC_PVR) Preset Value n Offset */ 1716 #define SDHC_PVR0_REG_OFST _UINT32_(0x60) /* (SDHC_PVR0) Preset Value n Offset */ 1717 #define SDHC_PVR1_REG_OFST _UINT32_(0x62) /* (SDHC_PVR1) Preset Value n Offset */ 1718 #define SDHC_PVR2_REG_OFST _UINT32_(0x64) /* (SDHC_PVR2) Preset Value n Offset */ 1719 #define SDHC_PVR3_REG_OFST _UINT32_(0x66) /* (SDHC_PVR3) Preset Value n Offset */ 1720 #define SDHC_PVR4_REG_OFST _UINT32_(0x68) /* (SDHC_PVR4) Preset Value n Offset */ 1721 #define SDHC_PVR5_REG_OFST _UINT32_(0x6A) /* (SDHC_PVR5) Preset Value n Offset */ 1722 #define SDHC_PVR6_REG_OFST _UINT32_(0x6C) /* (SDHC_PVR6) Preset Value n Offset */ 1723 #define SDHC_PVR7_REG_OFST _UINT32_(0x6E) /* (SDHC_PVR7) Preset Value n Offset */ 1724 #define SDHC_SISR_REG_OFST _UINT32_(0xFC) /* (SDHC_SISR) Slot Interrupt Status Offset */ 1725 #define SDHC_HCVR_REG_OFST _UINT32_(0xFE) /* (SDHC_HCVR) Host Controller Version Offset */ 1726 #define SDHC_APSR_REG_OFST _UINT32_(0x200) /* (SDHC_APSR) Additional Present State Register Offset */ 1727 #define SDHC_MC1R_REG_OFST _UINT32_(0x204) /* (SDHC_MC1R) MMC Control 1 Offset */ 1728 #define SDHC_MC2R_REG_OFST _UINT32_(0x205) /* (SDHC_MC2R) MMC Control 2 Offset */ 1729 #define SDHC_ACR_REG_OFST _UINT32_(0x208) /* (SDHC_ACR) AHB Control Offset */ 1730 #define SDHC_CC2R_REG_OFST _UINT32_(0x20C) /* (SDHC_CC2R) Clock Control 2 Offset */ 1731 #define SDHC_CACR_REG_OFST _UINT32_(0x230) /* (SDHC_CACR) Capabilities Control Offset */ 1732 #define SDHC_DBGR_REG_OFST _UINT32_(0x234) /* (SDHC_DBGR) Debug Offset */ 1733 1734 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1735 /** \brief SDHC register API structure */ 1736 typedef struct 1737 { /* SD/MMC Host Controller */ 1738 __IO uint32_t SDHC_SSAR; /**< Offset: 0x00 (R/W 32) SDMA System Address / Argument 2 */ 1739 __IO uint16_t SDHC_BSR; /**< Offset: 0x04 (R/W 16) Block Size */ 1740 __IO uint16_t SDHC_BCR; /**< Offset: 0x06 (R/W 16) Block Count */ 1741 __IO uint32_t SDHC_ARG1R; /**< Offset: 0x08 (R/W 32) Argument 1 */ 1742 __IO uint16_t SDHC_TMR; /**< Offset: 0x0C (R/W 16) Transfer Mode */ 1743 __IO uint16_t SDHC_CR; /**< Offset: 0x0E (R/W 16) Command */ 1744 __I uint32_t SDHC_RR[4]; /**< Offset: 0x10 (R/ 32) Response */ 1745 __IO uint32_t SDHC_BDPR; /**< Offset: 0x20 (R/W 32) Buffer Data Port */ 1746 __I uint32_t SDHC_PSR; /**< Offset: 0x24 (R/ 32) Present State */ 1747 __IO uint8_t SDHC_HC1R; /**< Offset: 0x28 (R/W 8) Host Control 1 */ 1748 __IO uint8_t SDHC_PCR; /**< Offset: 0x29 (R/W 8) Power Control */ 1749 __IO uint8_t SDHC_BGCR; /**< Offset: 0x2A (R/W 8) Block Gap Control */ 1750 __IO uint8_t SDHC_WCR; /**< Offset: 0x2B (R/W 8) Wakeup Control */ 1751 __IO uint16_t SDHC_CCR; /**< Offset: 0x2C (R/W 16) Clock Control */ 1752 __IO uint8_t SDHC_TCR; /**< Offset: 0x2E (R/W 8) Timeout Control */ 1753 __IO uint8_t SDHC_SRR; /**< Offset: 0x2F (R/W 8) Software Reset */ 1754 __IO uint16_t SDHC_NISTR; /**< Offset: 0x30 (R/W 16) Normal Interrupt Status */ 1755 __IO uint16_t SDHC_EISTR; /**< Offset: 0x32 (R/W 16) Error Interrupt Status */ 1756 __IO uint16_t SDHC_NISTER; /**< Offset: 0x34 (R/W 16) Normal Interrupt Status Enable */ 1757 __IO uint16_t SDHC_EISTER; /**< Offset: 0x36 (R/W 16) Error Interrupt Status Enable */ 1758 __IO uint16_t SDHC_NISIER; /**< Offset: 0x38 (R/W 16) Normal Interrupt Signal Enable */ 1759 __IO uint16_t SDHC_EISIER; /**< Offset: 0x3A (R/W 16) Error Interrupt Signal Enable */ 1760 __I uint16_t SDHC_ACESR; /**< Offset: 0x3C (R/ 16) Auto CMD Error Status */ 1761 __IO uint16_t SDHC_HC2R; /**< Offset: 0x3E (R/W 16) Host Control 2 */ 1762 __I uint32_t SDHC_CA0R; /**< Offset: 0x40 (R/ 32) Capabilities 0 */ 1763 __I uint32_t SDHC_CA1R; /**< Offset: 0x44 (R/ 32) Capabilities 1 */ 1764 __I uint32_t SDHC_MCCAR; /**< Offset: 0x48 (R/ 32) Maximum Current Capabilities */ 1765 __I uint8_t Reserved1[0x04]; 1766 __O uint16_t SDHC_FERACES; /**< Offset: 0x50 ( /W 16) Force Event for Auto CMD Error Status */ 1767 __O uint16_t SDHC_FEREIS; /**< Offset: 0x52 ( /W 16) Force Event for Error Interrupt Status */ 1768 __I uint8_t SDHC_AESR; /**< Offset: 0x54 (R/ 8) ADMA Error Status */ 1769 __I uint8_t Reserved2[0x03]; 1770 __IO uint32_t SDHC_ASAR[1]; /**< Offset: 0x58 (R/W 32) ADMA System Address */ 1771 __I uint8_t Reserved3[0x04]; 1772 __IO uint16_t SDHC_PVR[8]; /**< Offset: 0x60 (R/W 16) Preset Value n */ 1773 __I uint8_t Reserved4[0x8C]; 1774 __I uint16_t SDHC_SISR; /**< Offset: 0xFC (R/ 16) Slot Interrupt Status */ 1775 __I uint16_t SDHC_HCVR; /**< Offset: 0xFE (R/ 16) Host Controller Version */ 1776 __I uint8_t Reserved5[0x100]; 1777 __I uint32_t SDHC_APSR; /**< Offset: 0x200 (R/ 32) Additional Present State Register */ 1778 __IO uint8_t SDHC_MC1R; /**< Offset: 0x204 (R/W 8) MMC Control 1 */ 1779 __O uint8_t SDHC_MC2R; /**< Offset: 0x205 ( /W 8) MMC Control 2 */ 1780 __I uint8_t Reserved6[0x02]; 1781 __IO uint32_t SDHC_ACR; /**< Offset: 0x208 (R/W 32) AHB Control */ 1782 __IO uint32_t SDHC_CC2R; /**< Offset: 0x20C (R/W 32) Clock Control 2 */ 1783 __I uint8_t Reserved7[0x20]; 1784 __IO uint32_t SDHC_CACR; /**< Offset: 0x230 (R/W 32) Capabilities Control */ 1785 __IO uint8_t SDHC_DBGR; /**< Offset: 0x234 (R/W 8) Debug */ 1786 } sdhc_registers_t; 1787 1788 1789 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1790 #endif /* _PIC32CXSG61_SDHC_COMPONENT_H_ */ 1791
