1 /* 2 * Component description for RSTC 3 * 4 * Copyright (c) 2023 Microchip Technology Inc. and its subsidiaries. 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 */ 19 20 /* file generated from device description file (ATDF) version 2023-03-17T09:48:59Z */ 21 #ifndef _PIC32CXSG61_RSTC_COMPONENT_H_ 22 #define _PIC32CXSG61_RSTC_COMPONENT_H_ 23 24 /* ************************************************************************** */ 25 /* SOFTWARE API DEFINITION FOR RSTC */ 26 /* ************************************************************************** */ 27 28 /* -------- RSTC_RCAUSE : (RSTC Offset: 0x00) ( R/ 8) Reset Cause -------- */ 29 #define RSTC_RCAUSE_POR_Pos _UINT8_(0) /* (RSTC_RCAUSE) Power On Reset Position */ 30 #define RSTC_RCAUSE_POR_Msk (_UINT8_(0x1) << RSTC_RCAUSE_POR_Pos) /* (RSTC_RCAUSE) Power On Reset Mask */ 31 #define RSTC_RCAUSE_POR(value) (RSTC_RCAUSE_POR_Msk & (_UINT8_(value) << RSTC_RCAUSE_POR_Pos)) /* Assigment of value for POR in the RSTC_RCAUSE register */ 32 #define RSTC_RCAUSE_BOD12_Pos _UINT8_(1) /* (RSTC_RCAUSE) BOD12 Reset Position */ 33 #define RSTC_RCAUSE_BOD12_Msk (_UINT8_(0x1) << RSTC_RCAUSE_BOD12_Pos) /* (RSTC_RCAUSE) BOD12 Reset Mask */ 34 #define RSTC_RCAUSE_BOD12(value) (RSTC_RCAUSE_BOD12_Msk & (_UINT8_(value) << RSTC_RCAUSE_BOD12_Pos)) /* Assigment of value for BOD12 in the RSTC_RCAUSE register */ 35 #define RSTC_RCAUSE_BOD33_Pos _UINT8_(2) /* (RSTC_RCAUSE) BOD33 Reset Position */ 36 #define RSTC_RCAUSE_BOD33_Msk (_UINT8_(0x1) << RSTC_RCAUSE_BOD33_Pos) /* (RSTC_RCAUSE) BOD33 Reset Mask */ 37 #define RSTC_RCAUSE_BOD33(value) (RSTC_RCAUSE_BOD33_Msk & (_UINT8_(value) << RSTC_RCAUSE_BOD33_Pos)) /* Assigment of value for BOD33 in the RSTC_RCAUSE register */ 38 #define RSTC_RCAUSE_NVM_Pos _UINT8_(3) /* (RSTC_RCAUSE) NVM Reset Position */ 39 #define RSTC_RCAUSE_NVM_Msk (_UINT8_(0x1) << RSTC_RCAUSE_NVM_Pos) /* (RSTC_RCAUSE) NVM Reset Mask */ 40 #define RSTC_RCAUSE_NVM(value) (RSTC_RCAUSE_NVM_Msk & (_UINT8_(value) << RSTC_RCAUSE_NVM_Pos)) /* Assigment of value for NVM in the RSTC_RCAUSE register */ 41 #define RSTC_RCAUSE_EXT_Pos _UINT8_(4) /* (RSTC_RCAUSE) External Reset Position */ 42 #define RSTC_RCAUSE_EXT_Msk (_UINT8_(0x1) << RSTC_RCAUSE_EXT_Pos) /* (RSTC_RCAUSE) External Reset Mask */ 43 #define RSTC_RCAUSE_EXT(value) (RSTC_RCAUSE_EXT_Msk & (_UINT8_(value) << RSTC_RCAUSE_EXT_Pos)) /* Assigment of value for EXT in the RSTC_RCAUSE register */ 44 #define RSTC_RCAUSE_WDT_Pos _UINT8_(5) /* (RSTC_RCAUSE) Watchdog Reset Position */ 45 #define RSTC_RCAUSE_WDT_Msk (_UINT8_(0x1) << RSTC_RCAUSE_WDT_Pos) /* (RSTC_RCAUSE) Watchdog Reset Mask */ 46 #define RSTC_RCAUSE_WDT(value) (RSTC_RCAUSE_WDT_Msk & (_UINT8_(value) << RSTC_RCAUSE_WDT_Pos)) /* Assigment of value for WDT in the RSTC_RCAUSE register */ 47 #define RSTC_RCAUSE_SYST_Pos _UINT8_(6) /* (RSTC_RCAUSE) System Reset Request Position */ 48 #define RSTC_RCAUSE_SYST_Msk (_UINT8_(0x1) << RSTC_RCAUSE_SYST_Pos) /* (RSTC_RCAUSE) System Reset Request Mask */ 49 #define RSTC_RCAUSE_SYST(value) (RSTC_RCAUSE_SYST_Msk & (_UINT8_(value) << RSTC_RCAUSE_SYST_Pos)) /* Assigment of value for SYST in the RSTC_RCAUSE register */ 50 #define RSTC_RCAUSE_BACKUP_Pos _UINT8_(7) /* (RSTC_RCAUSE) Backup Reset Position */ 51 #define RSTC_RCAUSE_BACKUP_Msk (_UINT8_(0x1) << RSTC_RCAUSE_BACKUP_Pos) /* (RSTC_RCAUSE) Backup Reset Mask */ 52 #define RSTC_RCAUSE_BACKUP(value) (RSTC_RCAUSE_BACKUP_Msk & (_UINT8_(value) << RSTC_RCAUSE_BACKUP_Pos)) /* Assigment of value for BACKUP in the RSTC_RCAUSE register */ 53 #define RSTC_RCAUSE_Msk _UINT8_(0xFF) /* (RSTC_RCAUSE) Register Mask */ 54 55 #define RSTC_RCAUSE_BOD_Pos _UINT8_(1) /* (RSTC_RCAUSE Position) BODx2 Reset */ 56 #define RSTC_RCAUSE_BOD_Msk (_UINT8_(0x3) << RSTC_RCAUSE_BOD_Pos) /* (RSTC_RCAUSE Mask) BOD */ 57 #define RSTC_RCAUSE_BOD(value) (RSTC_RCAUSE_BOD_Msk & (_UINT8_(value) << RSTC_RCAUSE_BOD_Pos)) 58 59 /* -------- RSTC_BKUPEXIT : (RSTC Offset: 0x02) ( R/ 8) Backup Exit Source -------- */ 60 #define RSTC_BKUPEXIT_RESETVALUE _UINT8_(0x00) /* (RSTC_BKUPEXIT) Backup Exit Source Reset Value */ 61 62 #define RSTC_BKUPEXIT_RTC_Pos _UINT8_(1) /* (RSTC_BKUPEXIT) Real Timer Counter Interrupt Position */ 63 #define RSTC_BKUPEXIT_RTC_Msk (_UINT8_(0x1) << RSTC_BKUPEXIT_RTC_Pos) /* (RSTC_BKUPEXIT) Real Timer Counter Interrupt Mask */ 64 #define RSTC_BKUPEXIT_RTC(value) (RSTC_BKUPEXIT_RTC_Msk & (_UINT8_(value) << RSTC_BKUPEXIT_RTC_Pos)) /* Assigment of value for RTC in the RSTC_BKUPEXIT register */ 65 #define RSTC_BKUPEXIT_BBPS_Pos _UINT8_(2) /* (RSTC_BKUPEXIT) Battery Backup Power Switch Position */ 66 #define RSTC_BKUPEXIT_BBPS_Msk (_UINT8_(0x1) << RSTC_BKUPEXIT_BBPS_Pos) /* (RSTC_BKUPEXIT) Battery Backup Power Switch Mask */ 67 #define RSTC_BKUPEXIT_BBPS(value) (RSTC_BKUPEXIT_BBPS_Msk & (_UINT8_(value) << RSTC_BKUPEXIT_BBPS_Pos)) /* Assigment of value for BBPS in the RSTC_BKUPEXIT register */ 68 #define RSTC_BKUPEXIT_HIB_Pos _UINT8_(7) /* (RSTC_BKUPEXIT) Hibernate Position */ 69 #define RSTC_BKUPEXIT_HIB_Msk (_UINT8_(0x1) << RSTC_BKUPEXIT_HIB_Pos) /* (RSTC_BKUPEXIT) Hibernate Mask */ 70 #define RSTC_BKUPEXIT_HIB(value) (RSTC_BKUPEXIT_HIB_Msk & (_UINT8_(value) << RSTC_BKUPEXIT_HIB_Pos)) /* Assigment of value for HIB in the RSTC_BKUPEXIT register */ 71 #define RSTC_BKUPEXIT_Msk _UINT8_(0x86) /* (RSTC_BKUPEXIT) Register Mask */ 72 73 74 /** \brief RSTC register offsets definitions */ 75 #define RSTC_RCAUSE_REG_OFST _UINT32_(0x00) /* (RSTC_RCAUSE) Reset Cause Offset */ 76 #define RSTC_BKUPEXIT_REG_OFST _UINT32_(0x02) /* (RSTC_BKUPEXIT) Backup Exit Source Offset */ 77 78 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 79 /** \brief RSTC register API structure */ 80 typedef struct 81 { /* Reset Controller */ 82 __I uint8_t RSTC_RCAUSE; /**< Offset: 0x00 (R/ 8) Reset Cause */ 83 __I uint8_t Reserved1[0x01]; 84 __I uint8_t RSTC_BKUPEXIT; /**< Offset: 0x02 (R/ 8) Backup Exit Source */ 85 } rstc_registers_t; 86 87 88 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 89 #endif /* _PIC32CXSG61_RSTC_COMPONENT_H_ */ 90
