1 /* 2 * Component description for RAMECC 3 * 4 * Copyright (c) 2023 Microchip Technology Inc. and its subsidiaries. 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 */ 19 20 /* file generated from device description file (ATDF) version 2023-03-17T09:48:59Z */ 21 #ifndef _PIC32CXSG61_RAMECC_COMPONENT_H_ 22 #define _PIC32CXSG61_RAMECC_COMPONENT_H_ 23 24 /* ************************************************************************** */ 25 /* SOFTWARE API DEFINITION FOR RAMECC */ 26 /* ************************************************************************** */ 27 28 /* -------- RAMECC_INTENCLR : (RAMECC Offset: 0x00) (R/W 8) Interrupt Enable Clear -------- */ 29 #define RAMECC_INTENCLR_RESETVALUE _UINT8_(0x00) /* (RAMECC_INTENCLR) Interrupt Enable Clear Reset Value */ 30 31 #define RAMECC_INTENCLR_SINGLEE_Pos _UINT8_(0) /* (RAMECC_INTENCLR) Single Bit ECC Error Interrupt Enable Clear Position */ 32 #define RAMECC_INTENCLR_SINGLEE_Msk (_UINT8_(0x1) << RAMECC_INTENCLR_SINGLEE_Pos) /* (RAMECC_INTENCLR) Single Bit ECC Error Interrupt Enable Clear Mask */ 33 #define RAMECC_INTENCLR_SINGLEE(value) (RAMECC_INTENCLR_SINGLEE_Msk & (_UINT8_(value) << RAMECC_INTENCLR_SINGLEE_Pos)) /* Assigment of value for SINGLEE in the RAMECC_INTENCLR register */ 34 #define RAMECC_INTENCLR_DUALE_Pos _UINT8_(1) /* (RAMECC_INTENCLR) Dual Bit ECC Error Interrupt Enable Clear Position */ 35 #define RAMECC_INTENCLR_DUALE_Msk (_UINT8_(0x1) << RAMECC_INTENCLR_DUALE_Pos) /* (RAMECC_INTENCLR) Dual Bit ECC Error Interrupt Enable Clear Mask */ 36 #define RAMECC_INTENCLR_DUALE(value) (RAMECC_INTENCLR_DUALE_Msk & (_UINT8_(value) << RAMECC_INTENCLR_DUALE_Pos)) /* Assigment of value for DUALE in the RAMECC_INTENCLR register */ 37 #define RAMECC_INTENCLR_Msk _UINT8_(0x03) /* (RAMECC_INTENCLR) Register Mask */ 38 39 40 /* -------- RAMECC_INTENSET : (RAMECC Offset: 0x01) (R/W 8) Interrupt Enable Set -------- */ 41 #define RAMECC_INTENSET_RESETVALUE _UINT8_(0x00) /* (RAMECC_INTENSET) Interrupt Enable Set Reset Value */ 42 43 #define RAMECC_INTENSET_SINGLEE_Pos _UINT8_(0) /* (RAMECC_INTENSET) Single Bit ECC Error Interrupt Enable Set Position */ 44 #define RAMECC_INTENSET_SINGLEE_Msk (_UINT8_(0x1) << RAMECC_INTENSET_SINGLEE_Pos) /* (RAMECC_INTENSET) Single Bit ECC Error Interrupt Enable Set Mask */ 45 #define RAMECC_INTENSET_SINGLEE(value) (RAMECC_INTENSET_SINGLEE_Msk & (_UINT8_(value) << RAMECC_INTENSET_SINGLEE_Pos)) /* Assigment of value for SINGLEE in the RAMECC_INTENSET register */ 46 #define RAMECC_INTENSET_DUALE_Pos _UINT8_(1) /* (RAMECC_INTENSET) Dual Bit ECC Error Interrupt Enable Set Position */ 47 #define RAMECC_INTENSET_DUALE_Msk (_UINT8_(0x1) << RAMECC_INTENSET_DUALE_Pos) /* (RAMECC_INTENSET) Dual Bit ECC Error Interrupt Enable Set Mask */ 48 #define RAMECC_INTENSET_DUALE(value) (RAMECC_INTENSET_DUALE_Msk & (_UINT8_(value) << RAMECC_INTENSET_DUALE_Pos)) /* Assigment of value for DUALE in the RAMECC_INTENSET register */ 49 #define RAMECC_INTENSET_Msk _UINT8_(0x03) /* (RAMECC_INTENSET) Register Mask */ 50 51 52 /* -------- RAMECC_INTFLAG : (RAMECC Offset: 0x02) (R/W 8) Interrupt Flag -------- */ 53 #define RAMECC_INTFLAG_RESETVALUE _UINT8_(0x00) /* (RAMECC_INTFLAG) Interrupt Flag Reset Value */ 54 55 #define RAMECC_INTFLAG_SINGLEE_Pos _UINT8_(0) /* (RAMECC_INTFLAG) Single Bit ECC Error Interrupt Position */ 56 #define RAMECC_INTFLAG_SINGLEE_Msk (_UINT8_(0x1) << RAMECC_INTFLAG_SINGLEE_Pos) /* (RAMECC_INTFLAG) Single Bit ECC Error Interrupt Mask */ 57 #define RAMECC_INTFLAG_SINGLEE(value) (RAMECC_INTFLAG_SINGLEE_Msk & (_UINT8_(value) << RAMECC_INTFLAG_SINGLEE_Pos)) /* Assigment of value for SINGLEE in the RAMECC_INTFLAG register */ 58 #define RAMECC_INTFLAG_DUALE_Pos _UINT8_(1) /* (RAMECC_INTFLAG) Dual Bit ECC Error Interrupt Position */ 59 #define RAMECC_INTFLAG_DUALE_Msk (_UINT8_(0x1) << RAMECC_INTFLAG_DUALE_Pos) /* (RAMECC_INTFLAG) Dual Bit ECC Error Interrupt Mask */ 60 #define RAMECC_INTFLAG_DUALE(value) (RAMECC_INTFLAG_DUALE_Msk & (_UINT8_(value) << RAMECC_INTFLAG_DUALE_Pos)) /* Assigment of value for DUALE in the RAMECC_INTFLAG register */ 61 #define RAMECC_INTFLAG_Msk _UINT8_(0x03) /* (RAMECC_INTFLAG) Register Mask */ 62 63 64 /* -------- RAMECC_STATUS : (RAMECC Offset: 0x03) ( R/ 8) Status -------- */ 65 #define RAMECC_STATUS_RESETVALUE _UINT8_(0x00) /* (RAMECC_STATUS) Status Reset Value */ 66 67 #define RAMECC_STATUS_ECCDIS_Pos _UINT8_(0) /* (RAMECC_STATUS) ECC Disable Position */ 68 #define RAMECC_STATUS_ECCDIS_Msk (_UINT8_(0x1) << RAMECC_STATUS_ECCDIS_Pos) /* (RAMECC_STATUS) ECC Disable Mask */ 69 #define RAMECC_STATUS_ECCDIS(value) (RAMECC_STATUS_ECCDIS_Msk & (_UINT8_(value) << RAMECC_STATUS_ECCDIS_Pos)) /* Assigment of value for ECCDIS in the RAMECC_STATUS register */ 70 #define RAMECC_STATUS_Msk _UINT8_(0x01) /* (RAMECC_STATUS) Register Mask */ 71 72 73 /* -------- RAMECC_ERRADDR : (RAMECC Offset: 0x04) ( R/ 32) Error Address -------- */ 74 #define RAMECC_ERRADDR_RESETVALUE _UINT32_(0x00) /* (RAMECC_ERRADDR) Error Address Reset Value */ 75 76 #define RAMECC_ERRADDR_ERRADDR_Pos _UINT32_(0) /* (RAMECC_ERRADDR) Error Address Position */ 77 #define RAMECC_ERRADDR_ERRADDR_Msk (_UINT32_(0x1FFFF) << RAMECC_ERRADDR_ERRADDR_Pos) /* (RAMECC_ERRADDR) Error Address Mask */ 78 #define RAMECC_ERRADDR_ERRADDR(value) (RAMECC_ERRADDR_ERRADDR_Msk & (_UINT32_(value) << RAMECC_ERRADDR_ERRADDR_Pos)) /* Assigment of value for ERRADDR in the RAMECC_ERRADDR register */ 79 #define RAMECC_ERRADDR_Msk _UINT32_(0x0001FFFF) /* (RAMECC_ERRADDR) Register Mask */ 80 81 82 /* -------- RAMECC_DBGCTRL : (RAMECC Offset: 0x0F) (R/W 8) Debug Control -------- */ 83 #define RAMECC_DBGCTRL_RESETVALUE _UINT8_(0x00) /* (RAMECC_DBGCTRL) Debug Control Reset Value */ 84 85 #define RAMECC_DBGCTRL_ECCDIS_Pos _UINT8_(0) /* (RAMECC_DBGCTRL) ECC Disable Position */ 86 #define RAMECC_DBGCTRL_ECCDIS_Msk (_UINT8_(0x1) << RAMECC_DBGCTRL_ECCDIS_Pos) /* (RAMECC_DBGCTRL) ECC Disable Mask */ 87 #define RAMECC_DBGCTRL_ECCDIS(value) (RAMECC_DBGCTRL_ECCDIS_Msk & (_UINT8_(value) << RAMECC_DBGCTRL_ECCDIS_Pos)) /* Assigment of value for ECCDIS in the RAMECC_DBGCTRL register */ 88 #define RAMECC_DBGCTRL_ECCELOG_Pos _UINT8_(1) /* (RAMECC_DBGCTRL) ECC Error Log Position */ 89 #define RAMECC_DBGCTRL_ECCELOG_Msk (_UINT8_(0x1) << RAMECC_DBGCTRL_ECCELOG_Pos) /* (RAMECC_DBGCTRL) ECC Error Log Mask */ 90 #define RAMECC_DBGCTRL_ECCELOG(value) (RAMECC_DBGCTRL_ECCELOG_Msk & (_UINT8_(value) << RAMECC_DBGCTRL_ECCELOG_Pos)) /* Assigment of value for ECCELOG in the RAMECC_DBGCTRL register */ 91 #define RAMECC_DBGCTRL_Msk _UINT8_(0x03) /* (RAMECC_DBGCTRL) Register Mask */ 92 93 94 /** \brief RAMECC register offsets definitions */ 95 #define RAMECC_INTENCLR_REG_OFST _UINT32_(0x00) /* (RAMECC_INTENCLR) Interrupt Enable Clear Offset */ 96 #define RAMECC_INTENSET_REG_OFST _UINT32_(0x01) /* (RAMECC_INTENSET) Interrupt Enable Set Offset */ 97 #define RAMECC_INTFLAG_REG_OFST _UINT32_(0x02) /* (RAMECC_INTFLAG) Interrupt Flag Offset */ 98 #define RAMECC_STATUS_REG_OFST _UINT32_(0x03) /* (RAMECC_STATUS) Status Offset */ 99 #define RAMECC_ERRADDR_REG_OFST _UINT32_(0x04) /* (RAMECC_ERRADDR) Error Address Offset */ 100 #define RAMECC_DBGCTRL_REG_OFST _UINT32_(0x0F) /* (RAMECC_DBGCTRL) Debug Control Offset */ 101 102 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 103 /** \brief RAMECC register API structure */ 104 typedef struct 105 { /* RAM ECC */ 106 __IO uint8_t RAMECC_INTENCLR; /**< Offset: 0x00 (R/W 8) Interrupt Enable Clear */ 107 __IO uint8_t RAMECC_INTENSET; /**< Offset: 0x01 (R/W 8) Interrupt Enable Set */ 108 __IO uint8_t RAMECC_INTFLAG; /**< Offset: 0x02 (R/W 8) Interrupt Flag */ 109 __I uint8_t RAMECC_STATUS; /**< Offset: 0x03 (R/ 8) Status */ 110 __I uint32_t RAMECC_ERRADDR; /**< Offset: 0x04 (R/ 32) Error Address */ 111 __I uint8_t Reserved1[0x07]; 112 __IO uint8_t RAMECC_DBGCTRL; /**< Offset: 0x0F (R/W 8) Debug Control */ 113 } ramecc_registers_t; 114 115 116 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 117 #endif /* _PIC32CXSG61_RAMECC_COMPONENT_H_ */ 118
