1 /* 2 * Component description for PDEC 3 * 4 * Copyright (c) 2023 Microchip Technology Inc. and its subsidiaries. 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 */ 19 20 /* file generated from device description file (ATDF) version 2023-03-17T09:48:59Z */ 21 #ifndef _PIC32CXSG61_PDEC_COMPONENT_H_ 22 #define _PIC32CXSG61_PDEC_COMPONENT_H_ 23 24 /* ************************************************************************** */ 25 /* SOFTWARE API DEFINITION FOR PDEC */ 26 /* ************************************************************************** */ 27 28 /* -------- PDEC_CTRLA : (PDEC Offset: 0x00) (R/W 32) Control A -------- */ 29 #define PDEC_CTRLA_RESETVALUE _UINT32_(0x00) /* (PDEC_CTRLA) Control A Reset Value */ 30 31 #define PDEC_CTRLA_SWRST_Pos _UINT32_(0) /* (PDEC_CTRLA) Software Reset Position */ 32 #define PDEC_CTRLA_SWRST_Msk (_UINT32_(0x1) << PDEC_CTRLA_SWRST_Pos) /* (PDEC_CTRLA) Software Reset Mask */ 33 #define PDEC_CTRLA_SWRST(value) (PDEC_CTRLA_SWRST_Msk & (_UINT32_(value) << PDEC_CTRLA_SWRST_Pos)) /* Assigment of value for SWRST in the PDEC_CTRLA register */ 34 #define PDEC_CTRLA_ENABLE_Pos _UINT32_(1) /* (PDEC_CTRLA) Enable Position */ 35 #define PDEC_CTRLA_ENABLE_Msk (_UINT32_(0x1) << PDEC_CTRLA_ENABLE_Pos) /* (PDEC_CTRLA) Enable Mask */ 36 #define PDEC_CTRLA_ENABLE(value) (PDEC_CTRLA_ENABLE_Msk & (_UINT32_(value) << PDEC_CTRLA_ENABLE_Pos)) /* Assigment of value for ENABLE in the PDEC_CTRLA register */ 37 #define PDEC_CTRLA_MODE_Pos _UINT32_(2) /* (PDEC_CTRLA) Operation Mode Position */ 38 #define PDEC_CTRLA_MODE_Msk (_UINT32_(0x3) << PDEC_CTRLA_MODE_Pos) /* (PDEC_CTRLA) Operation Mode Mask */ 39 #define PDEC_CTRLA_MODE(value) (PDEC_CTRLA_MODE_Msk & (_UINT32_(value) << PDEC_CTRLA_MODE_Pos)) /* Assigment of value for MODE in the PDEC_CTRLA register */ 40 #define PDEC_CTRLA_MODE_QDEC_Val _UINT32_(0x0) /* (PDEC_CTRLA) QDEC operating mode */ 41 #define PDEC_CTRLA_MODE_HALL_Val _UINT32_(0x1) /* (PDEC_CTRLA) HALL operating mode */ 42 #define PDEC_CTRLA_MODE_COUNTER_Val _UINT32_(0x2) /* (PDEC_CTRLA) COUNTER operating mode */ 43 #define PDEC_CTRLA_MODE_QDEC (PDEC_CTRLA_MODE_QDEC_Val << PDEC_CTRLA_MODE_Pos) /* (PDEC_CTRLA) QDEC operating mode Position */ 44 #define PDEC_CTRLA_MODE_HALL (PDEC_CTRLA_MODE_HALL_Val << PDEC_CTRLA_MODE_Pos) /* (PDEC_CTRLA) HALL operating mode Position */ 45 #define PDEC_CTRLA_MODE_COUNTER (PDEC_CTRLA_MODE_COUNTER_Val << PDEC_CTRLA_MODE_Pos) /* (PDEC_CTRLA) COUNTER operating mode Position */ 46 #define PDEC_CTRLA_RUNSTDBY_Pos _UINT32_(6) /* (PDEC_CTRLA) Run in Standby Position */ 47 #define PDEC_CTRLA_RUNSTDBY_Msk (_UINT32_(0x1) << PDEC_CTRLA_RUNSTDBY_Pos) /* (PDEC_CTRLA) Run in Standby Mask */ 48 #define PDEC_CTRLA_RUNSTDBY(value) (PDEC_CTRLA_RUNSTDBY_Msk & (_UINT32_(value) << PDEC_CTRLA_RUNSTDBY_Pos)) /* Assigment of value for RUNSTDBY in the PDEC_CTRLA register */ 49 #define PDEC_CTRLA_CONF_Pos _UINT32_(8) /* (PDEC_CTRLA) PDEC Configuration Position */ 50 #define PDEC_CTRLA_CONF_Msk (_UINT32_(0x7) << PDEC_CTRLA_CONF_Pos) /* (PDEC_CTRLA) PDEC Configuration Mask */ 51 #define PDEC_CTRLA_CONF(value) (PDEC_CTRLA_CONF_Msk & (_UINT32_(value) << PDEC_CTRLA_CONF_Pos)) /* Assigment of value for CONF in the PDEC_CTRLA register */ 52 #define PDEC_CTRLA_CONF_X4_Val _UINT32_(0x0) /* (PDEC_CTRLA) Quadrature decoder direction */ 53 #define PDEC_CTRLA_CONF_X4S_Val _UINT32_(0x1) /* (PDEC_CTRLA) Secure Quadrature decoder direction */ 54 #define PDEC_CTRLA_CONF_X2_Val _UINT32_(0x2) /* (PDEC_CTRLA) Decoder direction */ 55 #define PDEC_CTRLA_CONF_X2S_Val _UINT32_(0x3) /* (PDEC_CTRLA) Secure decoder direction */ 56 #define PDEC_CTRLA_CONF_AUTOC_Val _UINT32_(0x4) /* (PDEC_CTRLA) Auto correction mode */ 57 #define PDEC_CTRLA_CONF_X4 (PDEC_CTRLA_CONF_X4_Val << PDEC_CTRLA_CONF_Pos) /* (PDEC_CTRLA) Quadrature decoder direction Position */ 58 #define PDEC_CTRLA_CONF_X4S (PDEC_CTRLA_CONF_X4S_Val << PDEC_CTRLA_CONF_Pos) /* (PDEC_CTRLA) Secure Quadrature decoder direction Position */ 59 #define PDEC_CTRLA_CONF_X2 (PDEC_CTRLA_CONF_X2_Val << PDEC_CTRLA_CONF_Pos) /* (PDEC_CTRLA) Decoder direction Position */ 60 #define PDEC_CTRLA_CONF_X2S (PDEC_CTRLA_CONF_X2S_Val << PDEC_CTRLA_CONF_Pos) /* (PDEC_CTRLA) Secure decoder direction Position */ 61 #define PDEC_CTRLA_CONF_AUTOC (PDEC_CTRLA_CONF_AUTOC_Val << PDEC_CTRLA_CONF_Pos) /* (PDEC_CTRLA) Auto correction mode Position */ 62 #define PDEC_CTRLA_ALOCK_Pos _UINT32_(11) /* (PDEC_CTRLA) Auto Lock Position */ 63 #define PDEC_CTRLA_ALOCK_Msk (_UINT32_(0x1) << PDEC_CTRLA_ALOCK_Pos) /* (PDEC_CTRLA) Auto Lock Mask */ 64 #define PDEC_CTRLA_ALOCK(value) (PDEC_CTRLA_ALOCK_Msk & (_UINT32_(value) << PDEC_CTRLA_ALOCK_Pos)) /* Assigment of value for ALOCK in the PDEC_CTRLA register */ 65 #define PDEC_CTRLA_SWAP_Pos _UINT32_(14) /* (PDEC_CTRLA) PDEC Phase A and B Swap Position */ 66 #define PDEC_CTRLA_SWAP_Msk (_UINT32_(0x1) << PDEC_CTRLA_SWAP_Pos) /* (PDEC_CTRLA) PDEC Phase A and B Swap Mask */ 67 #define PDEC_CTRLA_SWAP(value) (PDEC_CTRLA_SWAP_Msk & (_UINT32_(value) << PDEC_CTRLA_SWAP_Pos)) /* Assigment of value for SWAP in the PDEC_CTRLA register */ 68 #define PDEC_CTRLA_PEREN_Pos _UINT32_(15) /* (PDEC_CTRLA) Period Enable Position */ 69 #define PDEC_CTRLA_PEREN_Msk (_UINT32_(0x1) << PDEC_CTRLA_PEREN_Pos) /* (PDEC_CTRLA) Period Enable Mask */ 70 #define PDEC_CTRLA_PEREN(value) (PDEC_CTRLA_PEREN_Msk & (_UINT32_(value) << PDEC_CTRLA_PEREN_Pos)) /* Assigment of value for PEREN in the PDEC_CTRLA register */ 71 #define PDEC_CTRLA_PINEN0_Pos _UINT32_(16) /* (PDEC_CTRLA) PDEC Input From Pin 0 Enable Position */ 72 #define PDEC_CTRLA_PINEN0_Msk (_UINT32_(0x1) << PDEC_CTRLA_PINEN0_Pos) /* (PDEC_CTRLA) PDEC Input From Pin 0 Enable Mask */ 73 #define PDEC_CTRLA_PINEN0(value) (PDEC_CTRLA_PINEN0_Msk & (_UINT32_(value) << PDEC_CTRLA_PINEN0_Pos)) /* Assigment of value for PINEN0 in the PDEC_CTRLA register */ 74 #define PDEC_CTRLA_PINEN1_Pos _UINT32_(17) /* (PDEC_CTRLA) PDEC Input From Pin 1 Enable Position */ 75 #define PDEC_CTRLA_PINEN1_Msk (_UINT32_(0x1) << PDEC_CTRLA_PINEN1_Pos) /* (PDEC_CTRLA) PDEC Input From Pin 1 Enable Mask */ 76 #define PDEC_CTRLA_PINEN1(value) (PDEC_CTRLA_PINEN1_Msk & (_UINT32_(value) << PDEC_CTRLA_PINEN1_Pos)) /* Assigment of value for PINEN1 in the PDEC_CTRLA register */ 77 #define PDEC_CTRLA_PINEN2_Pos _UINT32_(18) /* (PDEC_CTRLA) PDEC Input From Pin 2 Enable Position */ 78 #define PDEC_CTRLA_PINEN2_Msk (_UINT32_(0x1) << PDEC_CTRLA_PINEN2_Pos) /* (PDEC_CTRLA) PDEC Input From Pin 2 Enable Mask */ 79 #define PDEC_CTRLA_PINEN2(value) (PDEC_CTRLA_PINEN2_Msk & (_UINT32_(value) << PDEC_CTRLA_PINEN2_Pos)) /* Assigment of value for PINEN2 in the PDEC_CTRLA register */ 80 #define PDEC_CTRLA_PINVEN0_Pos _UINT32_(20) /* (PDEC_CTRLA) IO Pin 0 Invert Enable Position */ 81 #define PDEC_CTRLA_PINVEN0_Msk (_UINT32_(0x1) << PDEC_CTRLA_PINVEN0_Pos) /* (PDEC_CTRLA) IO Pin 0 Invert Enable Mask */ 82 #define PDEC_CTRLA_PINVEN0(value) (PDEC_CTRLA_PINVEN0_Msk & (_UINT32_(value) << PDEC_CTRLA_PINVEN0_Pos)) /* Assigment of value for PINVEN0 in the PDEC_CTRLA register */ 83 #define PDEC_CTRLA_PINVEN1_Pos _UINT32_(21) /* (PDEC_CTRLA) IO Pin 1 Invert Enable Position */ 84 #define PDEC_CTRLA_PINVEN1_Msk (_UINT32_(0x1) << PDEC_CTRLA_PINVEN1_Pos) /* (PDEC_CTRLA) IO Pin 1 Invert Enable Mask */ 85 #define PDEC_CTRLA_PINVEN1(value) (PDEC_CTRLA_PINVEN1_Msk & (_UINT32_(value) << PDEC_CTRLA_PINVEN1_Pos)) /* Assigment of value for PINVEN1 in the PDEC_CTRLA register */ 86 #define PDEC_CTRLA_PINVEN2_Pos _UINT32_(22) /* (PDEC_CTRLA) IO Pin 2 Invert Enable Position */ 87 #define PDEC_CTRLA_PINVEN2_Msk (_UINT32_(0x1) << PDEC_CTRLA_PINVEN2_Pos) /* (PDEC_CTRLA) IO Pin 2 Invert Enable Mask */ 88 #define PDEC_CTRLA_PINVEN2(value) (PDEC_CTRLA_PINVEN2_Msk & (_UINT32_(value) << PDEC_CTRLA_PINVEN2_Pos)) /* Assigment of value for PINVEN2 in the PDEC_CTRLA register */ 89 #define PDEC_CTRLA_ANGULAR_Pos _UINT32_(24) /* (PDEC_CTRLA) Angular Counter Length Position */ 90 #define PDEC_CTRLA_ANGULAR_Msk (_UINT32_(0x7) << PDEC_CTRLA_ANGULAR_Pos) /* (PDEC_CTRLA) Angular Counter Length Mask */ 91 #define PDEC_CTRLA_ANGULAR(value) (PDEC_CTRLA_ANGULAR_Msk & (_UINT32_(value) << PDEC_CTRLA_ANGULAR_Pos)) /* Assigment of value for ANGULAR in the PDEC_CTRLA register */ 92 #define PDEC_CTRLA_MAXCMP_Pos _UINT32_(28) /* (PDEC_CTRLA) Maximum Consecutive Missing Pulses Position */ 93 #define PDEC_CTRLA_MAXCMP_Msk (_UINT32_(0xF) << PDEC_CTRLA_MAXCMP_Pos) /* (PDEC_CTRLA) Maximum Consecutive Missing Pulses Mask */ 94 #define PDEC_CTRLA_MAXCMP(value) (PDEC_CTRLA_MAXCMP_Msk & (_UINT32_(value) << PDEC_CTRLA_MAXCMP_Pos)) /* Assigment of value for MAXCMP in the PDEC_CTRLA register */ 95 #define PDEC_CTRLA_Msk _UINT32_(0xF777CF4F) /* (PDEC_CTRLA) Register Mask */ 96 97 #define PDEC_CTRLA_PINEN_Pos _UINT32_(16) /* (PDEC_CTRLA Position) PDEC Input From Pin x Enable */ 98 #define PDEC_CTRLA_PINEN_Msk (_UINT32_(0x7) << PDEC_CTRLA_PINEN_Pos) /* (PDEC_CTRLA Mask) PINEN */ 99 #define PDEC_CTRLA_PINEN(value) (PDEC_CTRLA_PINEN_Msk & (_UINT32_(value) << PDEC_CTRLA_PINEN_Pos)) 100 #define PDEC_CTRLA_PINVEN_Pos _UINT32_(20) /* (PDEC_CTRLA Position) IO Pin x Invert Enable */ 101 #define PDEC_CTRLA_PINVEN_Msk (_UINT32_(0x7) << PDEC_CTRLA_PINVEN_Pos) /* (PDEC_CTRLA Mask) PINVEN */ 102 #define PDEC_CTRLA_PINVEN(value) (PDEC_CTRLA_PINVEN_Msk & (_UINT32_(value) << PDEC_CTRLA_PINVEN_Pos)) 103 104 /* -------- PDEC_CTRLBCLR : (PDEC Offset: 0x04) (R/W 8) Control B Clear -------- */ 105 #define PDEC_CTRLBCLR_RESETVALUE _UINT8_(0x00) /* (PDEC_CTRLBCLR) Control B Clear Reset Value */ 106 107 #define PDEC_CTRLBCLR_LUPD_Pos _UINT8_(1) /* (PDEC_CTRLBCLR) Lock Update Position */ 108 #define PDEC_CTRLBCLR_LUPD_Msk (_UINT8_(0x1) << PDEC_CTRLBCLR_LUPD_Pos) /* (PDEC_CTRLBCLR) Lock Update Mask */ 109 #define PDEC_CTRLBCLR_LUPD(value) (PDEC_CTRLBCLR_LUPD_Msk & (_UINT8_(value) << PDEC_CTRLBCLR_LUPD_Pos)) /* Assigment of value for LUPD in the PDEC_CTRLBCLR register */ 110 #define PDEC_CTRLBCLR_CMD_Pos _UINT8_(5) /* (PDEC_CTRLBCLR) Command Position */ 111 #define PDEC_CTRLBCLR_CMD_Msk (_UINT8_(0x7) << PDEC_CTRLBCLR_CMD_Pos) /* (PDEC_CTRLBCLR) Command Mask */ 112 #define PDEC_CTRLBCLR_CMD(value) (PDEC_CTRLBCLR_CMD_Msk & (_UINT8_(value) << PDEC_CTRLBCLR_CMD_Pos)) /* Assigment of value for CMD in the PDEC_CTRLBCLR register */ 113 #define PDEC_CTRLBCLR_CMD_NONE_Val _UINT8_(0x0) /* (PDEC_CTRLBCLR) No action */ 114 #define PDEC_CTRLBCLR_CMD_RETRIGGER_Val _UINT8_(0x1) /* (PDEC_CTRLBCLR) Force a counter restart or retrigger */ 115 #define PDEC_CTRLBCLR_CMD_UPDATE_Val _UINT8_(0x2) /* (PDEC_CTRLBCLR) Force update of double buffered registers */ 116 #define PDEC_CTRLBCLR_CMD_READSYNC_Val _UINT8_(0x3) /* (PDEC_CTRLBCLR) Force a read synchronization of COUNT */ 117 #define PDEC_CTRLBCLR_CMD_START_Val _UINT8_(0x4) /* (PDEC_CTRLBCLR) Start QDEC/HALL */ 118 #define PDEC_CTRLBCLR_CMD_STOP_Val _UINT8_(0x5) /* (PDEC_CTRLBCLR) Stop QDEC/HALL */ 119 #define PDEC_CTRLBCLR_CMD_NONE (PDEC_CTRLBCLR_CMD_NONE_Val << PDEC_CTRLBCLR_CMD_Pos) /* (PDEC_CTRLBCLR) No action Position */ 120 #define PDEC_CTRLBCLR_CMD_RETRIGGER (PDEC_CTRLBCLR_CMD_RETRIGGER_Val << PDEC_CTRLBCLR_CMD_Pos) /* (PDEC_CTRLBCLR) Force a counter restart or retrigger Position */ 121 #define PDEC_CTRLBCLR_CMD_UPDATE (PDEC_CTRLBCLR_CMD_UPDATE_Val << PDEC_CTRLBCLR_CMD_Pos) /* (PDEC_CTRLBCLR) Force update of double buffered registers Position */ 122 #define PDEC_CTRLBCLR_CMD_READSYNC (PDEC_CTRLBCLR_CMD_READSYNC_Val << PDEC_CTRLBCLR_CMD_Pos) /* (PDEC_CTRLBCLR) Force a read synchronization of COUNT Position */ 123 #define PDEC_CTRLBCLR_CMD_START (PDEC_CTRLBCLR_CMD_START_Val << PDEC_CTRLBCLR_CMD_Pos) /* (PDEC_CTRLBCLR) Start QDEC/HALL Position */ 124 #define PDEC_CTRLBCLR_CMD_STOP (PDEC_CTRLBCLR_CMD_STOP_Val << PDEC_CTRLBCLR_CMD_Pos) /* (PDEC_CTRLBCLR) Stop QDEC/HALL Position */ 125 #define PDEC_CTRLBCLR_Msk _UINT8_(0xE2) /* (PDEC_CTRLBCLR) Register Mask */ 126 127 128 /* -------- PDEC_CTRLBSET : (PDEC Offset: 0x05) (R/W 8) Control B Set -------- */ 129 #define PDEC_CTRLBSET_RESETVALUE _UINT8_(0x00) /* (PDEC_CTRLBSET) Control B Set Reset Value */ 130 131 #define PDEC_CTRLBSET_LUPD_Pos _UINT8_(1) /* (PDEC_CTRLBSET) Lock Update Position */ 132 #define PDEC_CTRLBSET_LUPD_Msk (_UINT8_(0x1) << PDEC_CTRLBSET_LUPD_Pos) /* (PDEC_CTRLBSET) Lock Update Mask */ 133 #define PDEC_CTRLBSET_LUPD(value) (PDEC_CTRLBSET_LUPD_Msk & (_UINT8_(value) << PDEC_CTRLBSET_LUPD_Pos)) /* Assigment of value for LUPD in the PDEC_CTRLBSET register */ 134 #define PDEC_CTRLBSET_CMD_Pos _UINT8_(5) /* (PDEC_CTRLBSET) Command Position */ 135 #define PDEC_CTRLBSET_CMD_Msk (_UINT8_(0x7) << PDEC_CTRLBSET_CMD_Pos) /* (PDEC_CTRLBSET) Command Mask */ 136 #define PDEC_CTRLBSET_CMD(value) (PDEC_CTRLBSET_CMD_Msk & (_UINT8_(value) << PDEC_CTRLBSET_CMD_Pos)) /* Assigment of value for CMD in the PDEC_CTRLBSET register */ 137 #define PDEC_CTRLBSET_CMD_NONE_Val _UINT8_(0x0) /* (PDEC_CTRLBSET) No action */ 138 #define PDEC_CTRLBSET_CMD_RETRIGGER_Val _UINT8_(0x1) /* (PDEC_CTRLBSET) Force a counter restart or retrigger */ 139 #define PDEC_CTRLBSET_CMD_UPDATE_Val _UINT8_(0x2) /* (PDEC_CTRLBSET) Force update of double buffered registers */ 140 #define PDEC_CTRLBSET_CMD_READSYNC_Val _UINT8_(0x3) /* (PDEC_CTRLBSET) Force a read synchronization of COUNT */ 141 #define PDEC_CTRLBSET_CMD_START_Val _UINT8_(0x4) /* (PDEC_CTRLBSET) Start QDEC/HALL */ 142 #define PDEC_CTRLBSET_CMD_STOP_Val _UINT8_(0x5) /* (PDEC_CTRLBSET) Stop QDEC/HALL */ 143 #define PDEC_CTRLBSET_CMD_NONE (PDEC_CTRLBSET_CMD_NONE_Val << PDEC_CTRLBSET_CMD_Pos) /* (PDEC_CTRLBSET) No action Position */ 144 #define PDEC_CTRLBSET_CMD_RETRIGGER (PDEC_CTRLBSET_CMD_RETRIGGER_Val << PDEC_CTRLBSET_CMD_Pos) /* (PDEC_CTRLBSET) Force a counter restart or retrigger Position */ 145 #define PDEC_CTRLBSET_CMD_UPDATE (PDEC_CTRLBSET_CMD_UPDATE_Val << PDEC_CTRLBSET_CMD_Pos) /* (PDEC_CTRLBSET) Force update of double buffered registers Position */ 146 #define PDEC_CTRLBSET_CMD_READSYNC (PDEC_CTRLBSET_CMD_READSYNC_Val << PDEC_CTRLBSET_CMD_Pos) /* (PDEC_CTRLBSET) Force a read synchronization of COUNT Position */ 147 #define PDEC_CTRLBSET_CMD_START (PDEC_CTRLBSET_CMD_START_Val << PDEC_CTRLBSET_CMD_Pos) /* (PDEC_CTRLBSET) Start QDEC/HALL Position */ 148 #define PDEC_CTRLBSET_CMD_STOP (PDEC_CTRLBSET_CMD_STOP_Val << PDEC_CTRLBSET_CMD_Pos) /* (PDEC_CTRLBSET) Stop QDEC/HALL Position */ 149 #define PDEC_CTRLBSET_Msk _UINT8_(0xE2) /* (PDEC_CTRLBSET) Register Mask */ 150 151 152 /* -------- PDEC_EVCTRL : (PDEC Offset: 0x06) (R/W 16) Event Control -------- */ 153 #define PDEC_EVCTRL_RESETVALUE _UINT16_(0x00) /* (PDEC_EVCTRL) Event Control Reset Value */ 154 155 #define PDEC_EVCTRL_EVINV_Pos _UINT16_(2) /* (PDEC_EVCTRL) Inverted Event Input Enable Position */ 156 #define PDEC_EVCTRL_EVINV_Msk (_UINT16_(0x7) << PDEC_EVCTRL_EVINV_Pos) /* (PDEC_EVCTRL) Inverted Event Input Enable Mask */ 157 #define PDEC_EVCTRL_EVINV(value) (PDEC_EVCTRL_EVINV_Msk & (_UINT16_(value) << PDEC_EVCTRL_EVINV_Pos)) /* Assigment of value for EVINV in the PDEC_EVCTRL register */ 158 #define PDEC_EVCTRL_EVEI_Pos _UINT16_(5) /* (PDEC_EVCTRL) Event Input Enable Position */ 159 #define PDEC_EVCTRL_EVEI_Msk (_UINT16_(0x7) << PDEC_EVCTRL_EVEI_Pos) /* (PDEC_EVCTRL) Event Input Enable Mask */ 160 #define PDEC_EVCTRL_EVEI(value) (PDEC_EVCTRL_EVEI_Msk & (_UINT16_(value) << PDEC_EVCTRL_EVEI_Pos)) /* Assigment of value for EVEI in the PDEC_EVCTRL register */ 161 #define PDEC_EVCTRL_OVFEO_Pos _UINT16_(8) /* (PDEC_EVCTRL) Overflow/Underflow Output Event Enable Position */ 162 #define PDEC_EVCTRL_OVFEO_Msk (_UINT16_(0x1) << PDEC_EVCTRL_OVFEO_Pos) /* (PDEC_EVCTRL) Overflow/Underflow Output Event Enable Mask */ 163 #define PDEC_EVCTRL_OVFEO(value) (PDEC_EVCTRL_OVFEO_Msk & (_UINT16_(value) << PDEC_EVCTRL_OVFEO_Pos)) /* Assigment of value for OVFEO in the PDEC_EVCTRL register */ 164 #define PDEC_EVCTRL_ERREO_Pos _UINT16_(9) /* (PDEC_EVCTRL) Error Output Event Enable Position */ 165 #define PDEC_EVCTRL_ERREO_Msk (_UINT16_(0x1) << PDEC_EVCTRL_ERREO_Pos) /* (PDEC_EVCTRL) Error Output Event Enable Mask */ 166 #define PDEC_EVCTRL_ERREO(value) (PDEC_EVCTRL_ERREO_Msk & (_UINT16_(value) << PDEC_EVCTRL_ERREO_Pos)) /* Assigment of value for ERREO in the PDEC_EVCTRL register */ 167 #define PDEC_EVCTRL_DIREO_Pos _UINT16_(10) /* (PDEC_EVCTRL) Direction Output Event Enable Position */ 168 #define PDEC_EVCTRL_DIREO_Msk (_UINT16_(0x1) << PDEC_EVCTRL_DIREO_Pos) /* (PDEC_EVCTRL) Direction Output Event Enable Mask */ 169 #define PDEC_EVCTRL_DIREO(value) (PDEC_EVCTRL_DIREO_Msk & (_UINT16_(value) << PDEC_EVCTRL_DIREO_Pos)) /* Assigment of value for DIREO in the PDEC_EVCTRL register */ 170 #define PDEC_EVCTRL_VLCEO_Pos _UINT16_(11) /* (PDEC_EVCTRL) Velocity Output Event Enable Position */ 171 #define PDEC_EVCTRL_VLCEO_Msk (_UINT16_(0x1) << PDEC_EVCTRL_VLCEO_Pos) /* (PDEC_EVCTRL) Velocity Output Event Enable Mask */ 172 #define PDEC_EVCTRL_VLCEO(value) (PDEC_EVCTRL_VLCEO_Msk & (_UINT16_(value) << PDEC_EVCTRL_VLCEO_Pos)) /* Assigment of value for VLCEO in the PDEC_EVCTRL register */ 173 #define PDEC_EVCTRL_MCEO0_Pos _UINT16_(12) /* (PDEC_EVCTRL) Match Channel 0 Event Output Enable Position */ 174 #define PDEC_EVCTRL_MCEO0_Msk (_UINT16_(0x1) << PDEC_EVCTRL_MCEO0_Pos) /* (PDEC_EVCTRL) Match Channel 0 Event Output Enable Mask */ 175 #define PDEC_EVCTRL_MCEO0(value) (PDEC_EVCTRL_MCEO0_Msk & (_UINT16_(value) << PDEC_EVCTRL_MCEO0_Pos)) /* Assigment of value for MCEO0 in the PDEC_EVCTRL register */ 176 #define PDEC_EVCTRL_MCEO1_Pos _UINT16_(13) /* (PDEC_EVCTRL) Match Channel 1 Event Output Enable Position */ 177 #define PDEC_EVCTRL_MCEO1_Msk (_UINT16_(0x1) << PDEC_EVCTRL_MCEO1_Pos) /* (PDEC_EVCTRL) Match Channel 1 Event Output Enable Mask */ 178 #define PDEC_EVCTRL_MCEO1(value) (PDEC_EVCTRL_MCEO1_Msk & (_UINT16_(value) << PDEC_EVCTRL_MCEO1_Pos)) /* Assigment of value for MCEO1 in the PDEC_EVCTRL register */ 179 #define PDEC_EVCTRL_Msk _UINT16_(0x3FFC) /* (PDEC_EVCTRL) Register Mask */ 180 181 #define PDEC_EVCTRL_MCEO_Pos _UINT16_(12) /* (PDEC_EVCTRL Position) Match Channel x Event Output Enable */ 182 #define PDEC_EVCTRL_MCEO_Msk (_UINT16_(0x3) << PDEC_EVCTRL_MCEO_Pos) /* (PDEC_EVCTRL Mask) MCEO */ 183 #define PDEC_EVCTRL_MCEO(value) (PDEC_EVCTRL_MCEO_Msk & (_UINT16_(value) << PDEC_EVCTRL_MCEO_Pos)) 184 185 /* -------- PDEC_INTENCLR : (PDEC Offset: 0x08) (R/W 8) Interrupt Enable Clear -------- */ 186 #define PDEC_INTENCLR_RESETVALUE _UINT8_(0x00) /* (PDEC_INTENCLR) Interrupt Enable Clear Reset Value */ 187 188 #define PDEC_INTENCLR_OVF_Pos _UINT8_(0) /* (PDEC_INTENCLR) Overflow/Underflow Interrupt Disable Position */ 189 #define PDEC_INTENCLR_OVF_Msk (_UINT8_(0x1) << PDEC_INTENCLR_OVF_Pos) /* (PDEC_INTENCLR) Overflow/Underflow Interrupt Disable Mask */ 190 #define PDEC_INTENCLR_OVF(value) (PDEC_INTENCLR_OVF_Msk & (_UINT8_(value) << PDEC_INTENCLR_OVF_Pos)) /* Assigment of value for OVF in the PDEC_INTENCLR register */ 191 #define PDEC_INTENCLR_ERR_Pos _UINT8_(1) /* (PDEC_INTENCLR) Error Interrupt Disable Position */ 192 #define PDEC_INTENCLR_ERR_Msk (_UINT8_(0x1) << PDEC_INTENCLR_ERR_Pos) /* (PDEC_INTENCLR) Error Interrupt Disable Mask */ 193 #define PDEC_INTENCLR_ERR(value) (PDEC_INTENCLR_ERR_Msk & (_UINT8_(value) << PDEC_INTENCLR_ERR_Pos)) /* Assigment of value for ERR in the PDEC_INTENCLR register */ 194 #define PDEC_INTENCLR_DIR_Pos _UINT8_(2) /* (PDEC_INTENCLR) Direction Interrupt Disable Position */ 195 #define PDEC_INTENCLR_DIR_Msk (_UINT8_(0x1) << PDEC_INTENCLR_DIR_Pos) /* (PDEC_INTENCLR) Direction Interrupt Disable Mask */ 196 #define PDEC_INTENCLR_DIR(value) (PDEC_INTENCLR_DIR_Msk & (_UINT8_(value) << PDEC_INTENCLR_DIR_Pos)) /* Assigment of value for DIR in the PDEC_INTENCLR register */ 197 #define PDEC_INTENCLR_VLC_Pos _UINT8_(3) /* (PDEC_INTENCLR) Velocity Interrupt Disable Position */ 198 #define PDEC_INTENCLR_VLC_Msk (_UINT8_(0x1) << PDEC_INTENCLR_VLC_Pos) /* (PDEC_INTENCLR) Velocity Interrupt Disable Mask */ 199 #define PDEC_INTENCLR_VLC(value) (PDEC_INTENCLR_VLC_Msk & (_UINT8_(value) << PDEC_INTENCLR_VLC_Pos)) /* Assigment of value for VLC in the PDEC_INTENCLR register */ 200 #define PDEC_INTENCLR_MC0_Pos _UINT8_(4) /* (PDEC_INTENCLR) Channel 0 Compare Match Disable Position */ 201 #define PDEC_INTENCLR_MC0_Msk (_UINT8_(0x1) << PDEC_INTENCLR_MC0_Pos) /* (PDEC_INTENCLR) Channel 0 Compare Match Disable Mask */ 202 #define PDEC_INTENCLR_MC0(value) (PDEC_INTENCLR_MC0_Msk & (_UINT8_(value) << PDEC_INTENCLR_MC0_Pos)) /* Assigment of value for MC0 in the PDEC_INTENCLR register */ 203 #define PDEC_INTENCLR_MC1_Pos _UINT8_(5) /* (PDEC_INTENCLR) Channel 1 Compare Match Disable Position */ 204 #define PDEC_INTENCLR_MC1_Msk (_UINT8_(0x1) << PDEC_INTENCLR_MC1_Pos) /* (PDEC_INTENCLR) Channel 1 Compare Match Disable Mask */ 205 #define PDEC_INTENCLR_MC1(value) (PDEC_INTENCLR_MC1_Msk & (_UINT8_(value) << PDEC_INTENCLR_MC1_Pos)) /* Assigment of value for MC1 in the PDEC_INTENCLR register */ 206 #define PDEC_INTENCLR_Msk _UINT8_(0x3F) /* (PDEC_INTENCLR) Register Mask */ 207 208 #define PDEC_INTENCLR_MC_Pos _UINT8_(4) /* (PDEC_INTENCLR Position) Channel x Compare Match Disable */ 209 #define PDEC_INTENCLR_MC_Msk (_UINT8_(0x3) << PDEC_INTENCLR_MC_Pos) /* (PDEC_INTENCLR Mask) MC */ 210 #define PDEC_INTENCLR_MC(value) (PDEC_INTENCLR_MC_Msk & (_UINT8_(value) << PDEC_INTENCLR_MC_Pos)) 211 212 /* -------- PDEC_INTENSET : (PDEC Offset: 0x09) (R/W 8) Interrupt Enable Set -------- */ 213 #define PDEC_INTENSET_RESETVALUE _UINT8_(0x00) /* (PDEC_INTENSET) Interrupt Enable Set Reset Value */ 214 215 #define PDEC_INTENSET_OVF_Pos _UINT8_(0) /* (PDEC_INTENSET) Overflow/Underflow Interrupt Enable Position */ 216 #define PDEC_INTENSET_OVF_Msk (_UINT8_(0x1) << PDEC_INTENSET_OVF_Pos) /* (PDEC_INTENSET) Overflow/Underflow Interrupt Enable Mask */ 217 #define PDEC_INTENSET_OVF(value) (PDEC_INTENSET_OVF_Msk & (_UINT8_(value) << PDEC_INTENSET_OVF_Pos)) /* Assigment of value for OVF in the PDEC_INTENSET register */ 218 #define PDEC_INTENSET_ERR_Pos _UINT8_(1) /* (PDEC_INTENSET) Error Interrupt Enable Position */ 219 #define PDEC_INTENSET_ERR_Msk (_UINT8_(0x1) << PDEC_INTENSET_ERR_Pos) /* (PDEC_INTENSET) Error Interrupt Enable Mask */ 220 #define PDEC_INTENSET_ERR(value) (PDEC_INTENSET_ERR_Msk & (_UINT8_(value) << PDEC_INTENSET_ERR_Pos)) /* Assigment of value for ERR in the PDEC_INTENSET register */ 221 #define PDEC_INTENSET_DIR_Pos _UINT8_(2) /* (PDEC_INTENSET) Direction Interrupt Enable Position */ 222 #define PDEC_INTENSET_DIR_Msk (_UINT8_(0x1) << PDEC_INTENSET_DIR_Pos) /* (PDEC_INTENSET) Direction Interrupt Enable Mask */ 223 #define PDEC_INTENSET_DIR(value) (PDEC_INTENSET_DIR_Msk & (_UINT8_(value) << PDEC_INTENSET_DIR_Pos)) /* Assigment of value for DIR in the PDEC_INTENSET register */ 224 #define PDEC_INTENSET_VLC_Pos _UINT8_(3) /* (PDEC_INTENSET) Velocity Interrupt Enable Position */ 225 #define PDEC_INTENSET_VLC_Msk (_UINT8_(0x1) << PDEC_INTENSET_VLC_Pos) /* (PDEC_INTENSET) Velocity Interrupt Enable Mask */ 226 #define PDEC_INTENSET_VLC(value) (PDEC_INTENSET_VLC_Msk & (_UINT8_(value) << PDEC_INTENSET_VLC_Pos)) /* Assigment of value for VLC in the PDEC_INTENSET register */ 227 #define PDEC_INTENSET_MC0_Pos _UINT8_(4) /* (PDEC_INTENSET) Channel 0 Compare Match Enable Position */ 228 #define PDEC_INTENSET_MC0_Msk (_UINT8_(0x1) << PDEC_INTENSET_MC0_Pos) /* (PDEC_INTENSET) Channel 0 Compare Match Enable Mask */ 229 #define PDEC_INTENSET_MC0(value) (PDEC_INTENSET_MC0_Msk & (_UINT8_(value) << PDEC_INTENSET_MC0_Pos)) /* Assigment of value for MC0 in the PDEC_INTENSET register */ 230 #define PDEC_INTENSET_MC1_Pos _UINT8_(5) /* (PDEC_INTENSET) Channel 1 Compare Match Enable Position */ 231 #define PDEC_INTENSET_MC1_Msk (_UINT8_(0x1) << PDEC_INTENSET_MC1_Pos) /* (PDEC_INTENSET) Channel 1 Compare Match Enable Mask */ 232 #define PDEC_INTENSET_MC1(value) (PDEC_INTENSET_MC1_Msk & (_UINT8_(value) << PDEC_INTENSET_MC1_Pos)) /* Assigment of value for MC1 in the PDEC_INTENSET register */ 233 #define PDEC_INTENSET_Msk _UINT8_(0x3F) /* (PDEC_INTENSET) Register Mask */ 234 235 #define PDEC_INTENSET_MC_Pos _UINT8_(4) /* (PDEC_INTENSET Position) Channel x Compare Match Enable */ 236 #define PDEC_INTENSET_MC_Msk (_UINT8_(0x3) << PDEC_INTENSET_MC_Pos) /* (PDEC_INTENSET Mask) MC */ 237 #define PDEC_INTENSET_MC(value) (PDEC_INTENSET_MC_Msk & (_UINT8_(value) << PDEC_INTENSET_MC_Pos)) 238 239 /* -------- PDEC_INTFLAG : (PDEC Offset: 0x0A) (R/W 8) Interrupt Flag Status and Clear -------- */ 240 #define PDEC_INTFLAG_RESETVALUE _UINT8_(0x00) /* (PDEC_INTFLAG) Interrupt Flag Status and Clear Reset Value */ 241 242 #define PDEC_INTFLAG_OVF_Pos _UINT8_(0) /* (PDEC_INTFLAG) Overflow/Underflow Position */ 243 #define PDEC_INTFLAG_OVF_Msk (_UINT8_(0x1) << PDEC_INTFLAG_OVF_Pos) /* (PDEC_INTFLAG) Overflow/Underflow Mask */ 244 #define PDEC_INTFLAG_OVF(value) (PDEC_INTFLAG_OVF_Msk & (_UINT8_(value) << PDEC_INTFLAG_OVF_Pos)) /* Assigment of value for OVF in the PDEC_INTFLAG register */ 245 #define PDEC_INTFLAG_ERR_Pos _UINT8_(1) /* (PDEC_INTFLAG) Error Position */ 246 #define PDEC_INTFLAG_ERR_Msk (_UINT8_(0x1) << PDEC_INTFLAG_ERR_Pos) /* (PDEC_INTFLAG) Error Mask */ 247 #define PDEC_INTFLAG_ERR(value) (PDEC_INTFLAG_ERR_Msk & (_UINT8_(value) << PDEC_INTFLAG_ERR_Pos)) /* Assigment of value for ERR in the PDEC_INTFLAG register */ 248 #define PDEC_INTFLAG_DIR_Pos _UINT8_(2) /* (PDEC_INTFLAG) Direction Change Position */ 249 #define PDEC_INTFLAG_DIR_Msk (_UINT8_(0x1) << PDEC_INTFLAG_DIR_Pos) /* (PDEC_INTFLAG) Direction Change Mask */ 250 #define PDEC_INTFLAG_DIR(value) (PDEC_INTFLAG_DIR_Msk & (_UINT8_(value) << PDEC_INTFLAG_DIR_Pos)) /* Assigment of value for DIR in the PDEC_INTFLAG register */ 251 #define PDEC_INTFLAG_VLC_Pos _UINT8_(3) /* (PDEC_INTFLAG) Velocity Position */ 252 #define PDEC_INTFLAG_VLC_Msk (_UINT8_(0x1) << PDEC_INTFLAG_VLC_Pos) /* (PDEC_INTFLAG) Velocity Mask */ 253 #define PDEC_INTFLAG_VLC(value) (PDEC_INTFLAG_VLC_Msk & (_UINT8_(value) << PDEC_INTFLAG_VLC_Pos)) /* Assigment of value for VLC in the PDEC_INTFLAG register */ 254 #define PDEC_INTFLAG_MC0_Pos _UINT8_(4) /* (PDEC_INTFLAG) Channel 0 Compare Match Position */ 255 #define PDEC_INTFLAG_MC0_Msk (_UINT8_(0x1) << PDEC_INTFLAG_MC0_Pos) /* (PDEC_INTFLAG) Channel 0 Compare Match Mask */ 256 #define PDEC_INTFLAG_MC0(value) (PDEC_INTFLAG_MC0_Msk & (_UINT8_(value) << PDEC_INTFLAG_MC0_Pos)) /* Assigment of value for MC0 in the PDEC_INTFLAG register */ 257 #define PDEC_INTFLAG_MC1_Pos _UINT8_(5) /* (PDEC_INTFLAG) Channel 1 Compare Match Position */ 258 #define PDEC_INTFLAG_MC1_Msk (_UINT8_(0x1) << PDEC_INTFLAG_MC1_Pos) /* (PDEC_INTFLAG) Channel 1 Compare Match Mask */ 259 #define PDEC_INTFLAG_MC1(value) (PDEC_INTFLAG_MC1_Msk & (_UINT8_(value) << PDEC_INTFLAG_MC1_Pos)) /* Assigment of value for MC1 in the PDEC_INTFLAG register */ 260 #define PDEC_INTFLAG_Msk _UINT8_(0x3F) /* (PDEC_INTFLAG) Register Mask */ 261 262 #define PDEC_INTFLAG_MC_Pos _UINT8_(4) /* (PDEC_INTFLAG Position) Channel x Compare Match */ 263 #define PDEC_INTFLAG_MC_Msk (_UINT8_(0x3) << PDEC_INTFLAG_MC_Pos) /* (PDEC_INTFLAG Mask) MC */ 264 #define PDEC_INTFLAG_MC(value) (PDEC_INTFLAG_MC_Msk & (_UINT8_(value) << PDEC_INTFLAG_MC_Pos)) 265 266 /* -------- PDEC_STATUS : (PDEC Offset: 0x0C) (R/W 16) Status -------- */ 267 #define PDEC_STATUS_RESETVALUE _UINT16_(0x40) /* (PDEC_STATUS) Status Reset Value */ 268 269 #define PDEC_STATUS_QERR_Pos _UINT16_(0) /* (PDEC_STATUS) Quadrature Error Flag Position */ 270 #define PDEC_STATUS_QERR_Msk (_UINT16_(0x1) << PDEC_STATUS_QERR_Pos) /* (PDEC_STATUS) Quadrature Error Flag Mask */ 271 #define PDEC_STATUS_QERR(value) (PDEC_STATUS_QERR_Msk & (_UINT16_(value) << PDEC_STATUS_QERR_Pos)) /* Assigment of value for QERR in the PDEC_STATUS register */ 272 #define PDEC_STATUS_IDXERR_Pos _UINT16_(1) /* (PDEC_STATUS) Index Error Flag Position */ 273 #define PDEC_STATUS_IDXERR_Msk (_UINT16_(0x1) << PDEC_STATUS_IDXERR_Pos) /* (PDEC_STATUS) Index Error Flag Mask */ 274 #define PDEC_STATUS_IDXERR(value) (PDEC_STATUS_IDXERR_Msk & (_UINT16_(value) << PDEC_STATUS_IDXERR_Pos)) /* Assigment of value for IDXERR in the PDEC_STATUS register */ 275 #define PDEC_STATUS_MPERR_Pos _UINT16_(2) /* (PDEC_STATUS) Missing Pulse Error flag Position */ 276 #define PDEC_STATUS_MPERR_Msk (_UINT16_(0x1) << PDEC_STATUS_MPERR_Pos) /* (PDEC_STATUS) Missing Pulse Error flag Mask */ 277 #define PDEC_STATUS_MPERR(value) (PDEC_STATUS_MPERR_Msk & (_UINT16_(value) << PDEC_STATUS_MPERR_Pos)) /* Assigment of value for MPERR in the PDEC_STATUS register */ 278 #define PDEC_STATUS_WINERR_Pos _UINT16_(4) /* (PDEC_STATUS) Window Error Flag Position */ 279 #define PDEC_STATUS_WINERR_Msk (_UINT16_(0x1) << PDEC_STATUS_WINERR_Pos) /* (PDEC_STATUS) Window Error Flag Mask */ 280 #define PDEC_STATUS_WINERR(value) (PDEC_STATUS_WINERR_Msk & (_UINT16_(value) << PDEC_STATUS_WINERR_Pos)) /* Assigment of value for WINERR in the PDEC_STATUS register */ 281 #define PDEC_STATUS_HERR_Pos _UINT16_(5) /* (PDEC_STATUS) Hall Error Flag Position */ 282 #define PDEC_STATUS_HERR_Msk (_UINT16_(0x1) << PDEC_STATUS_HERR_Pos) /* (PDEC_STATUS) Hall Error Flag Mask */ 283 #define PDEC_STATUS_HERR(value) (PDEC_STATUS_HERR_Msk & (_UINT16_(value) << PDEC_STATUS_HERR_Pos)) /* Assigment of value for HERR in the PDEC_STATUS register */ 284 #define PDEC_STATUS_STOP_Pos _UINT16_(6) /* (PDEC_STATUS) Stop Position */ 285 #define PDEC_STATUS_STOP_Msk (_UINT16_(0x1) << PDEC_STATUS_STOP_Pos) /* (PDEC_STATUS) Stop Mask */ 286 #define PDEC_STATUS_STOP(value) (PDEC_STATUS_STOP_Msk & (_UINT16_(value) << PDEC_STATUS_STOP_Pos)) /* Assigment of value for STOP in the PDEC_STATUS register */ 287 #define PDEC_STATUS_DIR_Pos _UINT16_(7) /* (PDEC_STATUS) Direction Status Flag Position */ 288 #define PDEC_STATUS_DIR_Msk (_UINT16_(0x1) << PDEC_STATUS_DIR_Pos) /* (PDEC_STATUS) Direction Status Flag Mask */ 289 #define PDEC_STATUS_DIR(value) (PDEC_STATUS_DIR_Msk & (_UINT16_(value) << PDEC_STATUS_DIR_Pos)) /* Assigment of value for DIR in the PDEC_STATUS register */ 290 #define PDEC_STATUS_PRESCBUFV_Pos _UINT16_(8) /* (PDEC_STATUS) Prescaler Buffer Valid Position */ 291 #define PDEC_STATUS_PRESCBUFV_Msk (_UINT16_(0x1) << PDEC_STATUS_PRESCBUFV_Pos) /* (PDEC_STATUS) Prescaler Buffer Valid Mask */ 292 #define PDEC_STATUS_PRESCBUFV(value) (PDEC_STATUS_PRESCBUFV_Msk & (_UINT16_(value) << PDEC_STATUS_PRESCBUFV_Pos)) /* Assigment of value for PRESCBUFV in the PDEC_STATUS register */ 293 #define PDEC_STATUS_FILTERBUFV_Pos _UINT16_(9) /* (PDEC_STATUS) Filter Buffer Valid Position */ 294 #define PDEC_STATUS_FILTERBUFV_Msk (_UINT16_(0x1) << PDEC_STATUS_FILTERBUFV_Pos) /* (PDEC_STATUS) Filter Buffer Valid Mask */ 295 #define PDEC_STATUS_FILTERBUFV(value) (PDEC_STATUS_FILTERBUFV_Msk & (_UINT16_(value) << PDEC_STATUS_FILTERBUFV_Pos)) /* Assigment of value for FILTERBUFV in the PDEC_STATUS register */ 296 #define PDEC_STATUS_CCBUFV0_Pos _UINT16_(12) /* (PDEC_STATUS) Compare Channel 0 Buffer Valid Position */ 297 #define PDEC_STATUS_CCBUFV0_Msk (_UINT16_(0x1) << PDEC_STATUS_CCBUFV0_Pos) /* (PDEC_STATUS) Compare Channel 0 Buffer Valid Mask */ 298 #define PDEC_STATUS_CCBUFV0(value) (PDEC_STATUS_CCBUFV0_Msk & (_UINT16_(value) << PDEC_STATUS_CCBUFV0_Pos)) /* Assigment of value for CCBUFV0 in the PDEC_STATUS register */ 299 #define PDEC_STATUS_CCBUFV1_Pos _UINT16_(13) /* (PDEC_STATUS) Compare Channel 1 Buffer Valid Position */ 300 #define PDEC_STATUS_CCBUFV1_Msk (_UINT16_(0x1) << PDEC_STATUS_CCBUFV1_Pos) /* (PDEC_STATUS) Compare Channel 1 Buffer Valid Mask */ 301 #define PDEC_STATUS_CCBUFV1(value) (PDEC_STATUS_CCBUFV1_Msk & (_UINT16_(value) << PDEC_STATUS_CCBUFV1_Pos)) /* Assigment of value for CCBUFV1 in the PDEC_STATUS register */ 302 #define PDEC_STATUS_Msk _UINT16_(0x33F7) /* (PDEC_STATUS) Register Mask */ 303 304 #define PDEC_STATUS_CCBUFV_Pos _UINT16_(12) /* (PDEC_STATUS Position) Compare Channel x Buffer Valid */ 305 #define PDEC_STATUS_CCBUFV_Msk (_UINT16_(0x3) << PDEC_STATUS_CCBUFV_Pos) /* (PDEC_STATUS Mask) CCBUFV */ 306 #define PDEC_STATUS_CCBUFV(value) (PDEC_STATUS_CCBUFV_Msk & (_UINT16_(value) << PDEC_STATUS_CCBUFV_Pos)) 307 308 /* -------- PDEC_DBGCTRL : (PDEC Offset: 0x0F) (R/W 8) Debug Control -------- */ 309 #define PDEC_DBGCTRL_RESETVALUE _UINT8_(0x00) /* (PDEC_DBGCTRL) Debug Control Reset Value */ 310 311 #define PDEC_DBGCTRL_DBGRUN_Pos _UINT8_(0) /* (PDEC_DBGCTRL) Debug Run Mode Position */ 312 #define PDEC_DBGCTRL_DBGRUN_Msk (_UINT8_(0x1) << PDEC_DBGCTRL_DBGRUN_Pos) /* (PDEC_DBGCTRL) Debug Run Mode Mask */ 313 #define PDEC_DBGCTRL_DBGRUN(value) (PDEC_DBGCTRL_DBGRUN_Msk & (_UINT8_(value) << PDEC_DBGCTRL_DBGRUN_Pos)) /* Assigment of value for DBGRUN in the PDEC_DBGCTRL register */ 314 #define PDEC_DBGCTRL_Msk _UINT8_(0x01) /* (PDEC_DBGCTRL) Register Mask */ 315 316 317 /* -------- PDEC_SYNCBUSY : (PDEC Offset: 0x10) ( R/ 32) Synchronization Status -------- */ 318 #define PDEC_SYNCBUSY_RESETVALUE _UINT32_(0x00) /* (PDEC_SYNCBUSY) Synchronization Status Reset Value */ 319 320 #define PDEC_SYNCBUSY_SWRST_Pos _UINT32_(0) /* (PDEC_SYNCBUSY) Software Reset Synchronization Busy Position */ 321 #define PDEC_SYNCBUSY_SWRST_Msk (_UINT32_(0x1) << PDEC_SYNCBUSY_SWRST_Pos) /* (PDEC_SYNCBUSY) Software Reset Synchronization Busy Mask */ 322 #define PDEC_SYNCBUSY_SWRST(value) (PDEC_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << PDEC_SYNCBUSY_SWRST_Pos)) /* Assigment of value for SWRST in the PDEC_SYNCBUSY register */ 323 #define PDEC_SYNCBUSY_ENABLE_Pos _UINT32_(1) /* (PDEC_SYNCBUSY) Enable Synchronization Busy Position */ 324 #define PDEC_SYNCBUSY_ENABLE_Msk (_UINT32_(0x1) << PDEC_SYNCBUSY_ENABLE_Pos) /* (PDEC_SYNCBUSY) Enable Synchronization Busy Mask */ 325 #define PDEC_SYNCBUSY_ENABLE(value) (PDEC_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << PDEC_SYNCBUSY_ENABLE_Pos)) /* Assigment of value for ENABLE in the PDEC_SYNCBUSY register */ 326 #define PDEC_SYNCBUSY_CTRLB_Pos _UINT32_(2) /* (PDEC_SYNCBUSY) Control B Synchronization Busy Position */ 327 #define PDEC_SYNCBUSY_CTRLB_Msk (_UINT32_(0x1) << PDEC_SYNCBUSY_CTRLB_Pos) /* (PDEC_SYNCBUSY) Control B Synchronization Busy Mask */ 328 #define PDEC_SYNCBUSY_CTRLB(value) (PDEC_SYNCBUSY_CTRLB_Msk & (_UINT32_(value) << PDEC_SYNCBUSY_CTRLB_Pos)) /* Assigment of value for CTRLB in the PDEC_SYNCBUSY register */ 329 #define PDEC_SYNCBUSY_STATUS_Pos _UINT32_(3) /* (PDEC_SYNCBUSY) Status Synchronization Busy Position */ 330 #define PDEC_SYNCBUSY_STATUS_Msk (_UINT32_(0x1) << PDEC_SYNCBUSY_STATUS_Pos) /* (PDEC_SYNCBUSY) Status Synchronization Busy Mask */ 331 #define PDEC_SYNCBUSY_STATUS(value) (PDEC_SYNCBUSY_STATUS_Msk & (_UINT32_(value) << PDEC_SYNCBUSY_STATUS_Pos)) /* Assigment of value for STATUS in the PDEC_SYNCBUSY register */ 332 #define PDEC_SYNCBUSY_PRESC_Pos _UINT32_(4) /* (PDEC_SYNCBUSY) Prescaler Synchronization Busy Position */ 333 #define PDEC_SYNCBUSY_PRESC_Msk (_UINT32_(0x1) << PDEC_SYNCBUSY_PRESC_Pos) /* (PDEC_SYNCBUSY) Prescaler Synchronization Busy Mask */ 334 #define PDEC_SYNCBUSY_PRESC(value) (PDEC_SYNCBUSY_PRESC_Msk & (_UINT32_(value) << PDEC_SYNCBUSY_PRESC_Pos)) /* Assigment of value for PRESC in the PDEC_SYNCBUSY register */ 335 #define PDEC_SYNCBUSY_FILTER_Pos _UINT32_(5) /* (PDEC_SYNCBUSY) Filter Synchronization Busy Position */ 336 #define PDEC_SYNCBUSY_FILTER_Msk (_UINT32_(0x1) << PDEC_SYNCBUSY_FILTER_Pos) /* (PDEC_SYNCBUSY) Filter Synchronization Busy Mask */ 337 #define PDEC_SYNCBUSY_FILTER(value) (PDEC_SYNCBUSY_FILTER_Msk & (_UINT32_(value) << PDEC_SYNCBUSY_FILTER_Pos)) /* Assigment of value for FILTER in the PDEC_SYNCBUSY register */ 338 #define PDEC_SYNCBUSY_COUNT_Pos _UINT32_(6) /* (PDEC_SYNCBUSY) Count Synchronization Busy Position */ 339 #define PDEC_SYNCBUSY_COUNT_Msk (_UINT32_(0x1) << PDEC_SYNCBUSY_COUNT_Pos) /* (PDEC_SYNCBUSY) Count Synchronization Busy Mask */ 340 #define PDEC_SYNCBUSY_COUNT(value) (PDEC_SYNCBUSY_COUNT_Msk & (_UINT32_(value) << PDEC_SYNCBUSY_COUNT_Pos)) /* Assigment of value for COUNT in the PDEC_SYNCBUSY register */ 341 #define PDEC_SYNCBUSY_CC0_Pos _UINT32_(7) /* (PDEC_SYNCBUSY) Compare Channel 0 Synchronization Busy Position */ 342 #define PDEC_SYNCBUSY_CC0_Msk (_UINT32_(0x1) << PDEC_SYNCBUSY_CC0_Pos) /* (PDEC_SYNCBUSY) Compare Channel 0 Synchronization Busy Mask */ 343 #define PDEC_SYNCBUSY_CC0(value) (PDEC_SYNCBUSY_CC0_Msk & (_UINT32_(value) << PDEC_SYNCBUSY_CC0_Pos)) /* Assigment of value for CC0 in the PDEC_SYNCBUSY register */ 344 #define PDEC_SYNCBUSY_CC1_Pos _UINT32_(8) /* (PDEC_SYNCBUSY) Compare Channel 1 Synchronization Busy Position */ 345 #define PDEC_SYNCBUSY_CC1_Msk (_UINT32_(0x1) << PDEC_SYNCBUSY_CC1_Pos) /* (PDEC_SYNCBUSY) Compare Channel 1 Synchronization Busy Mask */ 346 #define PDEC_SYNCBUSY_CC1(value) (PDEC_SYNCBUSY_CC1_Msk & (_UINT32_(value) << PDEC_SYNCBUSY_CC1_Pos)) /* Assigment of value for CC1 in the PDEC_SYNCBUSY register */ 347 #define PDEC_SYNCBUSY_Msk _UINT32_(0x000001FF) /* (PDEC_SYNCBUSY) Register Mask */ 348 349 #define PDEC_SYNCBUSY_CC_Pos _UINT32_(7) /* (PDEC_SYNCBUSY Position) Compare Channel x Synchronization Busy */ 350 #define PDEC_SYNCBUSY_CC_Msk (_UINT32_(0x3) << PDEC_SYNCBUSY_CC_Pos) /* (PDEC_SYNCBUSY Mask) CC */ 351 #define PDEC_SYNCBUSY_CC(value) (PDEC_SYNCBUSY_CC_Msk & (_UINT32_(value) << PDEC_SYNCBUSY_CC_Pos)) 352 353 /* -------- PDEC_PRESC : (PDEC Offset: 0x14) (R/W 8) Prescaler Value -------- */ 354 #define PDEC_PRESC_RESETVALUE _UINT8_(0x00) /* (PDEC_PRESC) Prescaler Value Reset Value */ 355 356 #define PDEC_PRESC_PRESC_Pos _UINT8_(0) /* (PDEC_PRESC) Prescaler Value Position */ 357 #define PDEC_PRESC_PRESC_Msk (_UINT8_(0xF) << PDEC_PRESC_PRESC_Pos) /* (PDEC_PRESC) Prescaler Value Mask */ 358 #define PDEC_PRESC_PRESC(value) (PDEC_PRESC_PRESC_Msk & (_UINT8_(value) << PDEC_PRESC_PRESC_Pos)) /* Assigment of value for PRESC in the PDEC_PRESC register */ 359 #define PDEC_PRESC_PRESC_DIV1_Val _UINT8_(0x0) /* (PDEC_PRESC) No division */ 360 #define PDEC_PRESC_PRESC_DIV2_Val _UINT8_(0x1) /* (PDEC_PRESC) Divide by 2 */ 361 #define PDEC_PRESC_PRESC_DIV4_Val _UINT8_(0x2) /* (PDEC_PRESC) Divide by 4 */ 362 #define PDEC_PRESC_PRESC_DIV8_Val _UINT8_(0x3) /* (PDEC_PRESC) Divide by 8 */ 363 #define PDEC_PRESC_PRESC_DIV16_Val _UINT8_(0x4) /* (PDEC_PRESC) Divide by 16 */ 364 #define PDEC_PRESC_PRESC_DIV32_Val _UINT8_(0x5) /* (PDEC_PRESC) Divide by 32 */ 365 #define PDEC_PRESC_PRESC_DIV64_Val _UINT8_(0x6) /* (PDEC_PRESC) Divide by 64 */ 366 #define PDEC_PRESC_PRESC_DIV128_Val _UINT8_(0x7) /* (PDEC_PRESC) Divide by 128 */ 367 #define PDEC_PRESC_PRESC_DIV256_Val _UINT8_(0x8) /* (PDEC_PRESC) Divide by 256 */ 368 #define PDEC_PRESC_PRESC_DIV512_Val _UINT8_(0x9) /* (PDEC_PRESC) Divide by 512 */ 369 #define PDEC_PRESC_PRESC_DIV1024_Val _UINT8_(0xA) /* (PDEC_PRESC) Divide by 1024 */ 370 #define PDEC_PRESC_PRESC_DIV1 (PDEC_PRESC_PRESC_DIV1_Val << PDEC_PRESC_PRESC_Pos) /* (PDEC_PRESC) No division Position */ 371 #define PDEC_PRESC_PRESC_DIV2 (PDEC_PRESC_PRESC_DIV2_Val << PDEC_PRESC_PRESC_Pos) /* (PDEC_PRESC) Divide by 2 Position */ 372 #define PDEC_PRESC_PRESC_DIV4 (PDEC_PRESC_PRESC_DIV4_Val << PDEC_PRESC_PRESC_Pos) /* (PDEC_PRESC) Divide by 4 Position */ 373 #define PDEC_PRESC_PRESC_DIV8 (PDEC_PRESC_PRESC_DIV8_Val << PDEC_PRESC_PRESC_Pos) /* (PDEC_PRESC) Divide by 8 Position */ 374 #define PDEC_PRESC_PRESC_DIV16 (PDEC_PRESC_PRESC_DIV16_Val << PDEC_PRESC_PRESC_Pos) /* (PDEC_PRESC) Divide by 16 Position */ 375 #define PDEC_PRESC_PRESC_DIV32 (PDEC_PRESC_PRESC_DIV32_Val << PDEC_PRESC_PRESC_Pos) /* (PDEC_PRESC) Divide by 32 Position */ 376 #define PDEC_PRESC_PRESC_DIV64 (PDEC_PRESC_PRESC_DIV64_Val << PDEC_PRESC_PRESC_Pos) /* (PDEC_PRESC) Divide by 64 Position */ 377 #define PDEC_PRESC_PRESC_DIV128 (PDEC_PRESC_PRESC_DIV128_Val << PDEC_PRESC_PRESC_Pos) /* (PDEC_PRESC) Divide by 128 Position */ 378 #define PDEC_PRESC_PRESC_DIV256 (PDEC_PRESC_PRESC_DIV256_Val << PDEC_PRESC_PRESC_Pos) /* (PDEC_PRESC) Divide by 256 Position */ 379 #define PDEC_PRESC_PRESC_DIV512 (PDEC_PRESC_PRESC_DIV512_Val << PDEC_PRESC_PRESC_Pos) /* (PDEC_PRESC) Divide by 512 Position */ 380 #define PDEC_PRESC_PRESC_DIV1024 (PDEC_PRESC_PRESC_DIV1024_Val << PDEC_PRESC_PRESC_Pos) /* (PDEC_PRESC) Divide by 1024 Position */ 381 #define PDEC_PRESC_Msk _UINT8_(0x0F) /* (PDEC_PRESC) Register Mask */ 382 383 384 /* -------- PDEC_FILTER : (PDEC Offset: 0x15) (R/W 8) Filter Value -------- */ 385 #define PDEC_FILTER_RESETVALUE _UINT8_(0x00) /* (PDEC_FILTER) Filter Value Reset Value */ 386 387 #define PDEC_FILTER_FILTER_Pos _UINT8_(0) /* (PDEC_FILTER) Filter Value Position */ 388 #define PDEC_FILTER_FILTER_Msk (_UINT8_(0xFF) << PDEC_FILTER_FILTER_Pos) /* (PDEC_FILTER) Filter Value Mask */ 389 #define PDEC_FILTER_FILTER(value) (PDEC_FILTER_FILTER_Msk & (_UINT8_(value) << PDEC_FILTER_FILTER_Pos)) /* Assigment of value for FILTER in the PDEC_FILTER register */ 390 #define PDEC_FILTER_Msk _UINT8_(0xFF) /* (PDEC_FILTER) Register Mask */ 391 392 393 /* -------- PDEC_PRESCBUF : (PDEC Offset: 0x18) (R/W 8) Prescaler Buffer Value -------- */ 394 #define PDEC_PRESCBUF_RESETVALUE _UINT8_(0x00) /* (PDEC_PRESCBUF) Prescaler Buffer Value Reset Value */ 395 396 #define PDEC_PRESCBUF_PRESCBUF_Pos _UINT8_(0) /* (PDEC_PRESCBUF) Prescaler Buffer Value Position */ 397 #define PDEC_PRESCBUF_PRESCBUF_Msk (_UINT8_(0xF) << PDEC_PRESCBUF_PRESCBUF_Pos) /* (PDEC_PRESCBUF) Prescaler Buffer Value Mask */ 398 #define PDEC_PRESCBUF_PRESCBUF(value) (PDEC_PRESCBUF_PRESCBUF_Msk & (_UINT8_(value) << PDEC_PRESCBUF_PRESCBUF_Pos)) /* Assigment of value for PRESCBUF in the PDEC_PRESCBUF register */ 399 #define PDEC_PRESCBUF_PRESCBUF_DIV1_Val _UINT8_(0x0) /* (PDEC_PRESCBUF) No division */ 400 #define PDEC_PRESCBUF_PRESCBUF_DIV2_Val _UINT8_(0x1) /* (PDEC_PRESCBUF) Divide by 2 */ 401 #define PDEC_PRESCBUF_PRESCBUF_DIV4_Val _UINT8_(0x2) /* (PDEC_PRESCBUF) Divide by 4 */ 402 #define PDEC_PRESCBUF_PRESCBUF_DIV8_Val _UINT8_(0x3) /* (PDEC_PRESCBUF) Divide by 8 */ 403 #define PDEC_PRESCBUF_PRESCBUF_DIV16_Val _UINT8_(0x4) /* (PDEC_PRESCBUF) Divide by 16 */ 404 #define PDEC_PRESCBUF_PRESCBUF_DIV32_Val _UINT8_(0x5) /* (PDEC_PRESCBUF) Divide by 32 */ 405 #define PDEC_PRESCBUF_PRESCBUF_DIV64_Val _UINT8_(0x6) /* (PDEC_PRESCBUF) Divide by 64 */ 406 #define PDEC_PRESCBUF_PRESCBUF_DIV128_Val _UINT8_(0x7) /* (PDEC_PRESCBUF) Divide by 128 */ 407 #define PDEC_PRESCBUF_PRESCBUF_DIV256_Val _UINT8_(0x8) /* (PDEC_PRESCBUF) Divide by 256 */ 408 #define PDEC_PRESCBUF_PRESCBUF_DIV512_Val _UINT8_(0x9) /* (PDEC_PRESCBUF) Divide by 512 */ 409 #define PDEC_PRESCBUF_PRESCBUF_DIV1024_Val _UINT8_(0xA) /* (PDEC_PRESCBUF) Divide by 1024 */ 410 #define PDEC_PRESCBUF_PRESCBUF_DIV1 (PDEC_PRESCBUF_PRESCBUF_DIV1_Val << PDEC_PRESCBUF_PRESCBUF_Pos) /* (PDEC_PRESCBUF) No division Position */ 411 #define PDEC_PRESCBUF_PRESCBUF_DIV2 (PDEC_PRESCBUF_PRESCBUF_DIV2_Val << PDEC_PRESCBUF_PRESCBUF_Pos) /* (PDEC_PRESCBUF) Divide by 2 Position */ 412 #define PDEC_PRESCBUF_PRESCBUF_DIV4 (PDEC_PRESCBUF_PRESCBUF_DIV4_Val << PDEC_PRESCBUF_PRESCBUF_Pos) /* (PDEC_PRESCBUF) Divide by 4 Position */ 413 #define PDEC_PRESCBUF_PRESCBUF_DIV8 (PDEC_PRESCBUF_PRESCBUF_DIV8_Val << PDEC_PRESCBUF_PRESCBUF_Pos) /* (PDEC_PRESCBUF) Divide by 8 Position */ 414 #define PDEC_PRESCBUF_PRESCBUF_DIV16 (PDEC_PRESCBUF_PRESCBUF_DIV16_Val << PDEC_PRESCBUF_PRESCBUF_Pos) /* (PDEC_PRESCBUF) Divide by 16 Position */ 415 #define PDEC_PRESCBUF_PRESCBUF_DIV32 (PDEC_PRESCBUF_PRESCBUF_DIV32_Val << PDEC_PRESCBUF_PRESCBUF_Pos) /* (PDEC_PRESCBUF) Divide by 32 Position */ 416 #define PDEC_PRESCBUF_PRESCBUF_DIV64 (PDEC_PRESCBUF_PRESCBUF_DIV64_Val << PDEC_PRESCBUF_PRESCBUF_Pos) /* (PDEC_PRESCBUF) Divide by 64 Position */ 417 #define PDEC_PRESCBUF_PRESCBUF_DIV128 (PDEC_PRESCBUF_PRESCBUF_DIV128_Val << PDEC_PRESCBUF_PRESCBUF_Pos) /* (PDEC_PRESCBUF) Divide by 128 Position */ 418 #define PDEC_PRESCBUF_PRESCBUF_DIV256 (PDEC_PRESCBUF_PRESCBUF_DIV256_Val << PDEC_PRESCBUF_PRESCBUF_Pos) /* (PDEC_PRESCBUF) Divide by 256 Position */ 419 #define PDEC_PRESCBUF_PRESCBUF_DIV512 (PDEC_PRESCBUF_PRESCBUF_DIV512_Val << PDEC_PRESCBUF_PRESCBUF_Pos) /* (PDEC_PRESCBUF) Divide by 512 Position */ 420 #define PDEC_PRESCBUF_PRESCBUF_DIV1024 (PDEC_PRESCBUF_PRESCBUF_DIV1024_Val << PDEC_PRESCBUF_PRESCBUF_Pos) /* (PDEC_PRESCBUF) Divide by 1024 Position */ 421 #define PDEC_PRESCBUF_Msk _UINT8_(0x0F) /* (PDEC_PRESCBUF) Register Mask */ 422 423 424 /* -------- PDEC_FILTERBUF : (PDEC Offset: 0x19) (R/W 8) Filter Buffer Value -------- */ 425 #define PDEC_FILTERBUF_RESETVALUE _UINT8_(0x00) /* (PDEC_FILTERBUF) Filter Buffer Value Reset Value */ 426 427 #define PDEC_FILTERBUF_FILTERBUF_Pos _UINT8_(0) /* (PDEC_FILTERBUF) Filter Buffer Value Position */ 428 #define PDEC_FILTERBUF_FILTERBUF_Msk (_UINT8_(0xFF) << PDEC_FILTERBUF_FILTERBUF_Pos) /* (PDEC_FILTERBUF) Filter Buffer Value Mask */ 429 #define PDEC_FILTERBUF_FILTERBUF(value) (PDEC_FILTERBUF_FILTERBUF_Msk & (_UINT8_(value) << PDEC_FILTERBUF_FILTERBUF_Pos)) /* Assigment of value for FILTERBUF in the PDEC_FILTERBUF register */ 430 #define PDEC_FILTERBUF_Msk _UINT8_(0xFF) /* (PDEC_FILTERBUF) Register Mask */ 431 432 433 /* -------- PDEC_COUNT : (PDEC Offset: 0x1C) (R/W 32) Counter Value -------- */ 434 #define PDEC_COUNT_RESETVALUE _UINT32_(0x00) /* (PDEC_COUNT) Counter Value Reset Value */ 435 436 #define PDEC_COUNT_COUNT_Pos _UINT32_(0) /* (PDEC_COUNT) Counter Value Position */ 437 #define PDEC_COUNT_COUNT_Msk (_UINT32_(0xFFFF) << PDEC_COUNT_COUNT_Pos) /* (PDEC_COUNT) Counter Value Mask */ 438 #define PDEC_COUNT_COUNT(value) (PDEC_COUNT_COUNT_Msk & (_UINT32_(value) << PDEC_COUNT_COUNT_Pos)) /* Assigment of value for COUNT in the PDEC_COUNT register */ 439 #define PDEC_COUNT_Msk _UINT32_(0x0000FFFF) /* (PDEC_COUNT) Register Mask */ 440 441 442 /* -------- PDEC_CC : (PDEC Offset: 0x20) (R/W 32) Channel n Compare Value -------- */ 443 #define PDEC_CC_RESETVALUE _UINT32_(0x00) /* (PDEC_CC) Channel n Compare Value Reset Value */ 444 445 #define PDEC_CC_CC_Pos _UINT32_(0) /* (PDEC_CC) Channel Compare Value Position */ 446 #define PDEC_CC_CC_Msk (_UINT32_(0xFFFF) << PDEC_CC_CC_Pos) /* (PDEC_CC) Channel Compare Value Mask */ 447 #define PDEC_CC_CC(value) (PDEC_CC_CC_Msk & (_UINT32_(value) << PDEC_CC_CC_Pos)) /* Assigment of value for CC in the PDEC_CC register */ 448 #define PDEC_CC_Msk _UINT32_(0x0000FFFF) /* (PDEC_CC) Register Mask */ 449 450 451 /* -------- PDEC_CCBUF : (PDEC Offset: 0x30) (R/W 32) Channel Compare Buffer Value -------- */ 452 #define PDEC_CCBUF_RESETVALUE _UINT32_(0x00) /* (PDEC_CCBUF) Channel Compare Buffer Value Reset Value */ 453 454 #define PDEC_CCBUF_CCBUF_Pos _UINT32_(0) /* (PDEC_CCBUF) Channel Compare Buffer Value Position */ 455 #define PDEC_CCBUF_CCBUF_Msk (_UINT32_(0xFFFF) << PDEC_CCBUF_CCBUF_Pos) /* (PDEC_CCBUF) Channel Compare Buffer Value Mask */ 456 #define PDEC_CCBUF_CCBUF(value) (PDEC_CCBUF_CCBUF_Msk & (_UINT32_(value) << PDEC_CCBUF_CCBUF_Pos)) /* Assigment of value for CCBUF in the PDEC_CCBUF register */ 457 #define PDEC_CCBUF_Msk _UINT32_(0x0000FFFF) /* (PDEC_CCBUF) Register Mask */ 458 459 460 /** \brief PDEC register offsets definitions */ 461 #define PDEC_CTRLA_REG_OFST _UINT32_(0x00) /* (PDEC_CTRLA) Control A Offset */ 462 #define PDEC_CTRLBCLR_REG_OFST _UINT32_(0x04) /* (PDEC_CTRLBCLR) Control B Clear Offset */ 463 #define PDEC_CTRLBSET_REG_OFST _UINT32_(0x05) /* (PDEC_CTRLBSET) Control B Set Offset */ 464 #define PDEC_EVCTRL_REG_OFST _UINT32_(0x06) /* (PDEC_EVCTRL) Event Control Offset */ 465 #define PDEC_INTENCLR_REG_OFST _UINT32_(0x08) /* (PDEC_INTENCLR) Interrupt Enable Clear Offset */ 466 #define PDEC_INTENSET_REG_OFST _UINT32_(0x09) /* (PDEC_INTENSET) Interrupt Enable Set Offset */ 467 #define PDEC_INTFLAG_REG_OFST _UINT32_(0x0A) /* (PDEC_INTFLAG) Interrupt Flag Status and Clear Offset */ 468 #define PDEC_STATUS_REG_OFST _UINT32_(0x0C) /* (PDEC_STATUS) Status Offset */ 469 #define PDEC_DBGCTRL_REG_OFST _UINT32_(0x0F) /* (PDEC_DBGCTRL) Debug Control Offset */ 470 #define PDEC_SYNCBUSY_REG_OFST _UINT32_(0x10) /* (PDEC_SYNCBUSY) Synchronization Status Offset */ 471 #define PDEC_PRESC_REG_OFST _UINT32_(0x14) /* (PDEC_PRESC) Prescaler Value Offset */ 472 #define PDEC_FILTER_REG_OFST _UINT32_(0x15) /* (PDEC_FILTER) Filter Value Offset */ 473 #define PDEC_PRESCBUF_REG_OFST _UINT32_(0x18) /* (PDEC_PRESCBUF) Prescaler Buffer Value Offset */ 474 #define PDEC_FILTERBUF_REG_OFST _UINT32_(0x19) /* (PDEC_FILTERBUF) Filter Buffer Value Offset */ 475 #define PDEC_COUNT_REG_OFST _UINT32_(0x1C) /* (PDEC_COUNT) Counter Value Offset */ 476 #define PDEC_CC_REG_OFST _UINT32_(0x20) /* (PDEC_CC) Channel n Compare Value Offset */ 477 #define PDEC_CC0_REG_OFST _UINT32_(0x20) /* (PDEC_CC0) Channel n Compare Value Offset */ 478 #define PDEC_CC1_REG_OFST _UINT32_(0x24) /* (PDEC_CC1) Channel n Compare Value Offset */ 479 #define PDEC_CCBUF_REG_OFST _UINT32_(0x30) /* (PDEC_CCBUF) Channel Compare Buffer Value Offset */ 480 #define PDEC_CCBUF0_REG_OFST _UINT32_(0x30) /* (PDEC_CCBUF0) Channel Compare Buffer Value Offset */ 481 #define PDEC_CCBUF1_REG_OFST _UINT32_(0x34) /* (PDEC_CCBUF1) Channel Compare Buffer Value Offset */ 482 483 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 484 /** \brief PDEC register API structure */ 485 typedef struct 486 { /* Quadrature Decodeur */ 487 __IO uint32_t PDEC_CTRLA; /**< Offset: 0x00 (R/W 32) Control A */ 488 __IO uint8_t PDEC_CTRLBCLR; /**< Offset: 0x04 (R/W 8) Control B Clear */ 489 __IO uint8_t PDEC_CTRLBSET; /**< Offset: 0x05 (R/W 8) Control B Set */ 490 __IO uint16_t PDEC_EVCTRL; /**< Offset: 0x06 (R/W 16) Event Control */ 491 __IO uint8_t PDEC_INTENCLR; /**< Offset: 0x08 (R/W 8) Interrupt Enable Clear */ 492 __IO uint8_t PDEC_INTENSET; /**< Offset: 0x09 (R/W 8) Interrupt Enable Set */ 493 __IO uint8_t PDEC_INTFLAG; /**< Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */ 494 __I uint8_t Reserved1[0x01]; 495 __IO uint16_t PDEC_STATUS; /**< Offset: 0x0C (R/W 16) Status */ 496 __I uint8_t Reserved2[0x01]; 497 __IO uint8_t PDEC_DBGCTRL; /**< Offset: 0x0F (R/W 8) Debug Control */ 498 __I uint32_t PDEC_SYNCBUSY; /**< Offset: 0x10 (R/ 32) Synchronization Status */ 499 __IO uint8_t PDEC_PRESC; /**< Offset: 0x14 (R/W 8) Prescaler Value */ 500 __IO uint8_t PDEC_FILTER; /**< Offset: 0x15 (R/W 8) Filter Value */ 501 __I uint8_t Reserved3[0x02]; 502 __IO uint8_t PDEC_PRESCBUF; /**< Offset: 0x18 (R/W 8) Prescaler Buffer Value */ 503 __IO uint8_t PDEC_FILTERBUF; /**< Offset: 0x19 (R/W 8) Filter Buffer Value */ 504 __I uint8_t Reserved4[0x02]; 505 __IO uint32_t PDEC_COUNT; /**< Offset: 0x1C (R/W 32) Counter Value */ 506 __IO uint32_t PDEC_CC[2]; /**< Offset: 0x20 (R/W 32) Channel n Compare Value */ 507 __I uint8_t Reserved5[0x08]; 508 __IO uint32_t PDEC_CCBUF[2]; /**< Offset: 0x30 (R/W 32) Channel Compare Buffer Value */ 509 } pdec_registers_t; 510 511 512 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 513 #endif /* _PIC32CXSG61_PDEC_COMPONENT_H_ */ 514
