1 /* 2 * Component description for I2S 3 * 4 * Copyright (c) 2023 Microchip Technology Inc. and its subsidiaries. 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 */ 19 20 /* file generated from device description file (ATDF) version 2023-03-17T09:48:59Z */ 21 #ifndef _PIC32CXSG61_I2S_COMPONENT_H_ 22 #define _PIC32CXSG61_I2S_COMPONENT_H_ 23 24 /* ************************************************************************** */ 25 /* SOFTWARE API DEFINITION FOR I2S */ 26 /* ************************************************************************** */ 27 28 /* -------- I2S_CTRLA : (I2S Offset: 0x00) (R/W 8) Control A -------- */ 29 #define I2S_CTRLA_RESETVALUE _UINT8_(0x00) /* (I2S_CTRLA) Control A Reset Value */ 30 31 #define I2S_CTRLA_SWRST_Pos _UINT8_(0) /* (I2S_CTRLA) Software Reset Position */ 32 #define I2S_CTRLA_SWRST_Msk (_UINT8_(0x1) << I2S_CTRLA_SWRST_Pos) /* (I2S_CTRLA) Software Reset Mask */ 33 #define I2S_CTRLA_SWRST(value) (I2S_CTRLA_SWRST_Msk & (_UINT8_(value) << I2S_CTRLA_SWRST_Pos)) /* Assigment of value for SWRST in the I2S_CTRLA register */ 34 #define I2S_CTRLA_ENABLE_Pos _UINT8_(1) /* (I2S_CTRLA) Enable Position */ 35 #define I2S_CTRLA_ENABLE_Msk (_UINT8_(0x1) << I2S_CTRLA_ENABLE_Pos) /* (I2S_CTRLA) Enable Mask */ 36 #define I2S_CTRLA_ENABLE(value) (I2S_CTRLA_ENABLE_Msk & (_UINT8_(value) << I2S_CTRLA_ENABLE_Pos)) /* Assigment of value for ENABLE in the I2S_CTRLA register */ 37 #define I2S_CTRLA_CKEN0_Pos _UINT8_(2) /* (I2S_CTRLA) Clock Unit 0 Enable Position */ 38 #define I2S_CTRLA_CKEN0_Msk (_UINT8_(0x1) << I2S_CTRLA_CKEN0_Pos) /* (I2S_CTRLA) Clock Unit 0 Enable Mask */ 39 #define I2S_CTRLA_CKEN0(value) (I2S_CTRLA_CKEN0_Msk & (_UINT8_(value) << I2S_CTRLA_CKEN0_Pos)) /* Assigment of value for CKEN0 in the I2S_CTRLA register */ 40 #define I2S_CTRLA_CKEN1_Pos _UINT8_(3) /* (I2S_CTRLA) Clock Unit 1 Enable Position */ 41 #define I2S_CTRLA_CKEN1_Msk (_UINT8_(0x1) << I2S_CTRLA_CKEN1_Pos) /* (I2S_CTRLA) Clock Unit 1 Enable Mask */ 42 #define I2S_CTRLA_CKEN1(value) (I2S_CTRLA_CKEN1_Msk & (_UINT8_(value) << I2S_CTRLA_CKEN1_Pos)) /* Assigment of value for CKEN1 in the I2S_CTRLA register */ 43 #define I2S_CTRLA_TXEN_Pos _UINT8_(4) /* (I2S_CTRLA) Tx Serializer Enable Position */ 44 #define I2S_CTRLA_TXEN_Msk (_UINT8_(0x1) << I2S_CTRLA_TXEN_Pos) /* (I2S_CTRLA) Tx Serializer Enable Mask */ 45 #define I2S_CTRLA_TXEN(value) (I2S_CTRLA_TXEN_Msk & (_UINT8_(value) << I2S_CTRLA_TXEN_Pos)) /* Assigment of value for TXEN in the I2S_CTRLA register */ 46 #define I2S_CTRLA_RXEN_Pos _UINT8_(5) /* (I2S_CTRLA) Rx Serializer Enable Position */ 47 #define I2S_CTRLA_RXEN_Msk (_UINT8_(0x1) << I2S_CTRLA_RXEN_Pos) /* (I2S_CTRLA) Rx Serializer Enable Mask */ 48 #define I2S_CTRLA_RXEN(value) (I2S_CTRLA_RXEN_Msk & (_UINT8_(value) << I2S_CTRLA_RXEN_Pos)) /* Assigment of value for RXEN in the I2S_CTRLA register */ 49 #define I2S_CTRLA_Msk _UINT8_(0x3F) /* (I2S_CTRLA) Register Mask */ 50 51 #define I2S_CTRLA_CKEN_Pos _UINT8_(2) /* (I2S_CTRLA Position) Clock Unit x Enable */ 52 #define I2S_CTRLA_CKEN_Msk (_UINT8_(0x3) << I2S_CTRLA_CKEN_Pos) /* (I2S_CTRLA Mask) CKEN */ 53 #define I2S_CTRLA_CKEN(value) (I2S_CTRLA_CKEN_Msk & (_UINT8_(value) << I2S_CTRLA_CKEN_Pos)) 54 55 /* -------- I2S_CLKCTRL : (I2S Offset: 0x04) (R/W 32) Clock Unit n Control -------- */ 56 #define I2S_CLKCTRL_RESETVALUE _UINT32_(0x00) /* (I2S_CLKCTRL) Clock Unit n Control Reset Value */ 57 58 #define I2S_CLKCTRL_SLOTSIZE_Pos _UINT32_(0) /* (I2S_CLKCTRL) Slot Size Position */ 59 #define I2S_CLKCTRL_SLOTSIZE_Msk (_UINT32_(0x3) << I2S_CLKCTRL_SLOTSIZE_Pos) /* (I2S_CLKCTRL) Slot Size Mask */ 60 #define I2S_CLKCTRL_SLOTSIZE(value) (I2S_CLKCTRL_SLOTSIZE_Msk & (_UINT32_(value) << I2S_CLKCTRL_SLOTSIZE_Pos)) /* Assigment of value for SLOTSIZE in the I2S_CLKCTRL register */ 61 #define I2S_CLKCTRL_SLOTSIZE_8_Val _UINT32_(0x0) /* (I2S_CLKCTRL) 8-bit Slot for Clock Unit n */ 62 #define I2S_CLKCTRL_SLOTSIZE_16_Val _UINT32_(0x1) /* (I2S_CLKCTRL) 16-bit Slot for Clock Unit n */ 63 #define I2S_CLKCTRL_SLOTSIZE_24_Val _UINT32_(0x2) /* (I2S_CLKCTRL) 24-bit Slot for Clock Unit n */ 64 #define I2S_CLKCTRL_SLOTSIZE_32_Val _UINT32_(0x3) /* (I2S_CLKCTRL) 32-bit Slot for Clock Unit n */ 65 #define I2S_CLKCTRL_SLOTSIZE_8 (I2S_CLKCTRL_SLOTSIZE_8_Val << I2S_CLKCTRL_SLOTSIZE_Pos) /* (I2S_CLKCTRL) 8-bit Slot for Clock Unit n Position */ 66 #define I2S_CLKCTRL_SLOTSIZE_16 (I2S_CLKCTRL_SLOTSIZE_16_Val << I2S_CLKCTRL_SLOTSIZE_Pos) /* (I2S_CLKCTRL) 16-bit Slot for Clock Unit n Position */ 67 #define I2S_CLKCTRL_SLOTSIZE_24 (I2S_CLKCTRL_SLOTSIZE_24_Val << I2S_CLKCTRL_SLOTSIZE_Pos) /* (I2S_CLKCTRL) 24-bit Slot for Clock Unit n Position */ 68 #define I2S_CLKCTRL_SLOTSIZE_32 (I2S_CLKCTRL_SLOTSIZE_32_Val << I2S_CLKCTRL_SLOTSIZE_Pos) /* (I2S_CLKCTRL) 32-bit Slot for Clock Unit n Position */ 69 #define I2S_CLKCTRL_NBSLOTS_Pos _UINT32_(2) /* (I2S_CLKCTRL) Number of Slots in Frame Position */ 70 #define I2S_CLKCTRL_NBSLOTS_Msk (_UINT32_(0x7) << I2S_CLKCTRL_NBSLOTS_Pos) /* (I2S_CLKCTRL) Number of Slots in Frame Mask */ 71 #define I2S_CLKCTRL_NBSLOTS(value) (I2S_CLKCTRL_NBSLOTS_Msk & (_UINT32_(value) << I2S_CLKCTRL_NBSLOTS_Pos)) /* Assigment of value for NBSLOTS in the I2S_CLKCTRL register */ 72 #define I2S_CLKCTRL_FSWIDTH_Pos _UINT32_(5) /* (I2S_CLKCTRL) Frame Sync Width Position */ 73 #define I2S_CLKCTRL_FSWIDTH_Msk (_UINT32_(0x3) << I2S_CLKCTRL_FSWIDTH_Pos) /* (I2S_CLKCTRL) Frame Sync Width Mask */ 74 #define I2S_CLKCTRL_FSWIDTH(value) (I2S_CLKCTRL_FSWIDTH_Msk & (_UINT32_(value) << I2S_CLKCTRL_FSWIDTH_Pos)) /* Assigment of value for FSWIDTH in the I2S_CLKCTRL register */ 75 #define I2S_CLKCTRL_FSWIDTH_SLOT_Val _UINT32_(0x0) /* (I2S_CLKCTRL) Frame Sync Pulse is 1 Slot wide (default for I2S protocol) */ 76 #define I2S_CLKCTRL_FSWIDTH_HALF_Val _UINT32_(0x1) /* (I2S_CLKCTRL) Frame Sync Pulse is half a Frame wide */ 77 #define I2S_CLKCTRL_FSWIDTH_BIT_Val _UINT32_(0x2) /* (I2S_CLKCTRL) Frame Sync Pulse is 1 Bit wide */ 78 #define I2S_CLKCTRL_FSWIDTH_BURST_Val _UINT32_(0x3) /* (I2S_CLKCTRL) Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested */ 79 #define I2S_CLKCTRL_FSWIDTH_SLOT (I2S_CLKCTRL_FSWIDTH_SLOT_Val << I2S_CLKCTRL_FSWIDTH_Pos) /* (I2S_CLKCTRL) Frame Sync Pulse is 1 Slot wide (default for I2S protocol) Position */ 80 #define I2S_CLKCTRL_FSWIDTH_HALF (I2S_CLKCTRL_FSWIDTH_HALF_Val << I2S_CLKCTRL_FSWIDTH_Pos) /* (I2S_CLKCTRL) Frame Sync Pulse is half a Frame wide Position */ 81 #define I2S_CLKCTRL_FSWIDTH_BIT (I2S_CLKCTRL_FSWIDTH_BIT_Val << I2S_CLKCTRL_FSWIDTH_Pos) /* (I2S_CLKCTRL) Frame Sync Pulse is 1 Bit wide Position */ 82 #define I2S_CLKCTRL_FSWIDTH_BURST (I2S_CLKCTRL_FSWIDTH_BURST_Val << I2S_CLKCTRL_FSWIDTH_Pos) /* (I2S_CLKCTRL) Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested Position */ 83 #define I2S_CLKCTRL_BITDELAY_Pos _UINT32_(7) /* (I2S_CLKCTRL) Data Delay from Frame Sync Position */ 84 #define I2S_CLKCTRL_BITDELAY_Msk (_UINT32_(0x1) << I2S_CLKCTRL_BITDELAY_Pos) /* (I2S_CLKCTRL) Data Delay from Frame Sync Mask */ 85 #define I2S_CLKCTRL_BITDELAY(value) (I2S_CLKCTRL_BITDELAY_Msk & (_UINT32_(value) << I2S_CLKCTRL_BITDELAY_Pos)) /* Assigment of value for BITDELAY in the I2S_CLKCTRL register */ 86 #define I2S_CLKCTRL_BITDELAY_LJ_Val _UINT32_(0x0) /* (I2S_CLKCTRL) Left Justified (0 Bit Delay) */ 87 #define I2S_CLKCTRL_BITDELAY_I2S_Val _UINT32_(0x1) /* (I2S_CLKCTRL) I2S (1 Bit Delay) */ 88 #define I2S_CLKCTRL_BITDELAY_LJ (I2S_CLKCTRL_BITDELAY_LJ_Val << I2S_CLKCTRL_BITDELAY_Pos) /* (I2S_CLKCTRL) Left Justified (0 Bit Delay) Position */ 89 #define I2S_CLKCTRL_BITDELAY_I2S (I2S_CLKCTRL_BITDELAY_I2S_Val << I2S_CLKCTRL_BITDELAY_Pos) /* (I2S_CLKCTRL) I2S (1 Bit Delay) Position */ 90 #define I2S_CLKCTRL_FSSEL_Pos _UINT32_(8) /* (I2S_CLKCTRL) Frame Sync Select Position */ 91 #define I2S_CLKCTRL_FSSEL_Msk (_UINT32_(0x1) << I2S_CLKCTRL_FSSEL_Pos) /* (I2S_CLKCTRL) Frame Sync Select Mask */ 92 #define I2S_CLKCTRL_FSSEL(value) (I2S_CLKCTRL_FSSEL_Msk & (_UINT32_(value) << I2S_CLKCTRL_FSSEL_Pos)) /* Assigment of value for FSSEL in the I2S_CLKCTRL register */ 93 #define I2S_CLKCTRL_FSSEL_SCKDIV_Val _UINT32_(0x0) /* (I2S_CLKCTRL) Divided Serial Clock n is used as Frame Sync n source */ 94 #define I2S_CLKCTRL_FSSEL_FSPIN_Val _UINT32_(0x1) /* (I2S_CLKCTRL) FSn input pin is used as Frame Sync n source */ 95 #define I2S_CLKCTRL_FSSEL_SCKDIV (I2S_CLKCTRL_FSSEL_SCKDIV_Val << I2S_CLKCTRL_FSSEL_Pos) /* (I2S_CLKCTRL) Divided Serial Clock n is used as Frame Sync n source Position */ 96 #define I2S_CLKCTRL_FSSEL_FSPIN (I2S_CLKCTRL_FSSEL_FSPIN_Val << I2S_CLKCTRL_FSSEL_Pos) /* (I2S_CLKCTRL) FSn input pin is used as Frame Sync n source Position */ 97 #define I2S_CLKCTRL_FSINV_Pos _UINT32_(9) /* (I2S_CLKCTRL) Frame Sync Invert Position */ 98 #define I2S_CLKCTRL_FSINV_Msk (_UINT32_(0x1) << I2S_CLKCTRL_FSINV_Pos) /* (I2S_CLKCTRL) Frame Sync Invert Mask */ 99 #define I2S_CLKCTRL_FSINV(value) (I2S_CLKCTRL_FSINV_Msk & (_UINT32_(value) << I2S_CLKCTRL_FSINV_Pos)) /* Assigment of value for FSINV in the I2S_CLKCTRL register */ 100 #define I2S_CLKCTRL_FSOUTINV_Pos _UINT32_(10) /* (I2S_CLKCTRL) Frame Sync Output Invert Position */ 101 #define I2S_CLKCTRL_FSOUTINV_Msk (_UINT32_(0x1) << I2S_CLKCTRL_FSOUTINV_Pos) /* (I2S_CLKCTRL) Frame Sync Output Invert Mask */ 102 #define I2S_CLKCTRL_FSOUTINV(value) (I2S_CLKCTRL_FSOUTINV_Msk & (_UINT32_(value) << I2S_CLKCTRL_FSOUTINV_Pos)) /* Assigment of value for FSOUTINV in the I2S_CLKCTRL register */ 103 #define I2S_CLKCTRL_SCKSEL_Pos _UINT32_(11) /* (I2S_CLKCTRL) Serial Clock Select Position */ 104 #define I2S_CLKCTRL_SCKSEL_Msk (_UINT32_(0x1) << I2S_CLKCTRL_SCKSEL_Pos) /* (I2S_CLKCTRL) Serial Clock Select Mask */ 105 #define I2S_CLKCTRL_SCKSEL(value) (I2S_CLKCTRL_SCKSEL_Msk & (_UINT32_(value) << I2S_CLKCTRL_SCKSEL_Pos)) /* Assigment of value for SCKSEL in the I2S_CLKCTRL register */ 106 #define I2S_CLKCTRL_SCKSEL_MCKDIV_Val _UINT32_(0x0) /* (I2S_CLKCTRL) Divided Master Clock n is used as Serial Clock n source */ 107 #define I2S_CLKCTRL_SCKSEL_SCKPIN_Val _UINT32_(0x1) /* (I2S_CLKCTRL) SCKn input pin is used as Serial Clock n source */ 108 #define I2S_CLKCTRL_SCKSEL_MCKDIV (I2S_CLKCTRL_SCKSEL_MCKDIV_Val << I2S_CLKCTRL_SCKSEL_Pos) /* (I2S_CLKCTRL) Divided Master Clock n is used as Serial Clock n source Position */ 109 #define I2S_CLKCTRL_SCKSEL_SCKPIN (I2S_CLKCTRL_SCKSEL_SCKPIN_Val << I2S_CLKCTRL_SCKSEL_Pos) /* (I2S_CLKCTRL) SCKn input pin is used as Serial Clock n source Position */ 110 #define I2S_CLKCTRL_SCKOUTINV_Pos _UINT32_(12) /* (I2S_CLKCTRL) Serial Clock Output Invert Position */ 111 #define I2S_CLKCTRL_SCKOUTINV_Msk (_UINT32_(0x1) << I2S_CLKCTRL_SCKOUTINV_Pos) /* (I2S_CLKCTRL) Serial Clock Output Invert Mask */ 112 #define I2S_CLKCTRL_SCKOUTINV(value) (I2S_CLKCTRL_SCKOUTINV_Msk & (_UINT32_(value) << I2S_CLKCTRL_SCKOUTINV_Pos)) /* Assigment of value for SCKOUTINV in the I2S_CLKCTRL register */ 113 #define I2S_CLKCTRL_MCKSEL_Pos _UINT32_(13) /* (I2S_CLKCTRL) Master Clock Select Position */ 114 #define I2S_CLKCTRL_MCKSEL_Msk (_UINT32_(0x1) << I2S_CLKCTRL_MCKSEL_Pos) /* (I2S_CLKCTRL) Master Clock Select Mask */ 115 #define I2S_CLKCTRL_MCKSEL(value) (I2S_CLKCTRL_MCKSEL_Msk & (_UINT32_(value) << I2S_CLKCTRL_MCKSEL_Pos)) /* Assigment of value for MCKSEL in the I2S_CLKCTRL register */ 116 #define I2S_CLKCTRL_MCKSEL_GCLK_Val _UINT32_(0x0) /* (I2S_CLKCTRL) GCLK_I2S_n is used as Master Clock n source */ 117 #define I2S_CLKCTRL_MCKSEL_MCKPIN_Val _UINT32_(0x1) /* (I2S_CLKCTRL) MCKn input pin is used as Master Clock n source */ 118 #define I2S_CLKCTRL_MCKSEL_GCLK (I2S_CLKCTRL_MCKSEL_GCLK_Val << I2S_CLKCTRL_MCKSEL_Pos) /* (I2S_CLKCTRL) GCLK_I2S_n is used as Master Clock n source Position */ 119 #define I2S_CLKCTRL_MCKSEL_MCKPIN (I2S_CLKCTRL_MCKSEL_MCKPIN_Val << I2S_CLKCTRL_MCKSEL_Pos) /* (I2S_CLKCTRL) MCKn input pin is used as Master Clock n source Position */ 120 #define I2S_CLKCTRL_MCKEN_Pos _UINT32_(14) /* (I2S_CLKCTRL) Master Clock Enable Position */ 121 #define I2S_CLKCTRL_MCKEN_Msk (_UINT32_(0x1) << I2S_CLKCTRL_MCKEN_Pos) /* (I2S_CLKCTRL) Master Clock Enable Mask */ 122 #define I2S_CLKCTRL_MCKEN(value) (I2S_CLKCTRL_MCKEN_Msk & (_UINT32_(value) << I2S_CLKCTRL_MCKEN_Pos)) /* Assigment of value for MCKEN in the I2S_CLKCTRL register */ 123 #define I2S_CLKCTRL_MCKOUTINV_Pos _UINT32_(15) /* (I2S_CLKCTRL) Master Clock Output Invert Position */ 124 #define I2S_CLKCTRL_MCKOUTINV_Msk (_UINT32_(0x1) << I2S_CLKCTRL_MCKOUTINV_Pos) /* (I2S_CLKCTRL) Master Clock Output Invert Mask */ 125 #define I2S_CLKCTRL_MCKOUTINV(value) (I2S_CLKCTRL_MCKOUTINV_Msk & (_UINT32_(value) << I2S_CLKCTRL_MCKOUTINV_Pos)) /* Assigment of value for MCKOUTINV in the I2S_CLKCTRL register */ 126 #define I2S_CLKCTRL_MCKDIV_Pos _UINT32_(16) /* (I2S_CLKCTRL) Master Clock Division Factor Position */ 127 #define I2S_CLKCTRL_MCKDIV_Msk (_UINT32_(0x3F) << I2S_CLKCTRL_MCKDIV_Pos) /* (I2S_CLKCTRL) Master Clock Division Factor Mask */ 128 #define I2S_CLKCTRL_MCKDIV(value) (I2S_CLKCTRL_MCKDIV_Msk & (_UINT32_(value) << I2S_CLKCTRL_MCKDIV_Pos)) /* Assigment of value for MCKDIV in the I2S_CLKCTRL register */ 129 #define I2S_CLKCTRL_MCKOUTDIV_Pos _UINT32_(24) /* (I2S_CLKCTRL) Master Clock Output Division Factor Position */ 130 #define I2S_CLKCTRL_MCKOUTDIV_Msk (_UINT32_(0x3F) << I2S_CLKCTRL_MCKOUTDIV_Pos) /* (I2S_CLKCTRL) Master Clock Output Division Factor Mask */ 131 #define I2S_CLKCTRL_MCKOUTDIV(value) (I2S_CLKCTRL_MCKOUTDIV_Msk & (_UINT32_(value) << I2S_CLKCTRL_MCKOUTDIV_Pos)) /* Assigment of value for MCKOUTDIV in the I2S_CLKCTRL register */ 132 #define I2S_CLKCTRL_Msk _UINT32_(0x3F3FFFFF) /* (I2S_CLKCTRL) Register Mask */ 133 134 135 /* -------- I2S_INTENCLR : (I2S Offset: 0x0C) (R/W 16) Interrupt Enable Clear -------- */ 136 #define I2S_INTENCLR_RESETVALUE _UINT16_(0x00) /* (I2S_INTENCLR) Interrupt Enable Clear Reset Value */ 137 138 #define I2S_INTENCLR_RXRDY0_Pos _UINT16_(0) /* (I2S_INTENCLR) Receive Ready 0 Interrupt Enable Position */ 139 #define I2S_INTENCLR_RXRDY0_Msk (_UINT16_(0x1) << I2S_INTENCLR_RXRDY0_Pos) /* (I2S_INTENCLR) Receive Ready 0 Interrupt Enable Mask */ 140 #define I2S_INTENCLR_RXRDY0(value) (I2S_INTENCLR_RXRDY0_Msk & (_UINT16_(value) << I2S_INTENCLR_RXRDY0_Pos)) /* Assigment of value for RXRDY0 in the I2S_INTENCLR register */ 141 #define I2S_INTENCLR_RXRDY1_Pos _UINT16_(1) /* (I2S_INTENCLR) Receive Ready 1 Interrupt Enable Position */ 142 #define I2S_INTENCLR_RXRDY1_Msk (_UINT16_(0x1) << I2S_INTENCLR_RXRDY1_Pos) /* (I2S_INTENCLR) Receive Ready 1 Interrupt Enable Mask */ 143 #define I2S_INTENCLR_RXRDY1(value) (I2S_INTENCLR_RXRDY1_Msk & (_UINT16_(value) << I2S_INTENCLR_RXRDY1_Pos)) /* Assigment of value for RXRDY1 in the I2S_INTENCLR register */ 144 #define I2S_INTENCLR_RXOR0_Pos _UINT16_(4) /* (I2S_INTENCLR) Receive Overrun 0 Interrupt Enable Position */ 145 #define I2S_INTENCLR_RXOR0_Msk (_UINT16_(0x1) << I2S_INTENCLR_RXOR0_Pos) /* (I2S_INTENCLR) Receive Overrun 0 Interrupt Enable Mask */ 146 #define I2S_INTENCLR_RXOR0(value) (I2S_INTENCLR_RXOR0_Msk & (_UINT16_(value) << I2S_INTENCLR_RXOR0_Pos)) /* Assigment of value for RXOR0 in the I2S_INTENCLR register */ 147 #define I2S_INTENCLR_RXOR1_Pos _UINT16_(5) /* (I2S_INTENCLR) Receive Overrun 1 Interrupt Enable Position */ 148 #define I2S_INTENCLR_RXOR1_Msk (_UINT16_(0x1) << I2S_INTENCLR_RXOR1_Pos) /* (I2S_INTENCLR) Receive Overrun 1 Interrupt Enable Mask */ 149 #define I2S_INTENCLR_RXOR1(value) (I2S_INTENCLR_RXOR1_Msk & (_UINT16_(value) << I2S_INTENCLR_RXOR1_Pos)) /* Assigment of value for RXOR1 in the I2S_INTENCLR register */ 150 #define I2S_INTENCLR_TXRDY0_Pos _UINT16_(8) /* (I2S_INTENCLR) Transmit Ready 0 Interrupt Enable Position */ 151 #define I2S_INTENCLR_TXRDY0_Msk (_UINT16_(0x1) << I2S_INTENCLR_TXRDY0_Pos) /* (I2S_INTENCLR) Transmit Ready 0 Interrupt Enable Mask */ 152 #define I2S_INTENCLR_TXRDY0(value) (I2S_INTENCLR_TXRDY0_Msk & (_UINT16_(value) << I2S_INTENCLR_TXRDY0_Pos)) /* Assigment of value for TXRDY0 in the I2S_INTENCLR register */ 153 #define I2S_INTENCLR_TXRDY1_Pos _UINT16_(9) /* (I2S_INTENCLR) Transmit Ready 1 Interrupt Enable Position */ 154 #define I2S_INTENCLR_TXRDY1_Msk (_UINT16_(0x1) << I2S_INTENCLR_TXRDY1_Pos) /* (I2S_INTENCLR) Transmit Ready 1 Interrupt Enable Mask */ 155 #define I2S_INTENCLR_TXRDY1(value) (I2S_INTENCLR_TXRDY1_Msk & (_UINT16_(value) << I2S_INTENCLR_TXRDY1_Pos)) /* Assigment of value for TXRDY1 in the I2S_INTENCLR register */ 156 #define I2S_INTENCLR_TXUR0_Pos _UINT16_(12) /* (I2S_INTENCLR) Transmit Underrun 0 Interrupt Enable Position */ 157 #define I2S_INTENCLR_TXUR0_Msk (_UINT16_(0x1) << I2S_INTENCLR_TXUR0_Pos) /* (I2S_INTENCLR) Transmit Underrun 0 Interrupt Enable Mask */ 158 #define I2S_INTENCLR_TXUR0(value) (I2S_INTENCLR_TXUR0_Msk & (_UINT16_(value) << I2S_INTENCLR_TXUR0_Pos)) /* Assigment of value for TXUR0 in the I2S_INTENCLR register */ 159 #define I2S_INTENCLR_TXUR1_Pos _UINT16_(13) /* (I2S_INTENCLR) Transmit Underrun 1 Interrupt Enable Position */ 160 #define I2S_INTENCLR_TXUR1_Msk (_UINT16_(0x1) << I2S_INTENCLR_TXUR1_Pos) /* (I2S_INTENCLR) Transmit Underrun 1 Interrupt Enable Mask */ 161 #define I2S_INTENCLR_TXUR1(value) (I2S_INTENCLR_TXUR1_Msk & (_UINT16_(value) << I2S_INTENCLR_TXUR1_Pos)) /* Assigment of value for TXUR1 in the I2S_INTENCLR register */ 162 #define I2S_INTENCLR_Msk _UINT16_(0x3333) /* (I2S_INTENCLR) Register Mask */ 163 164 #define I2S_INTENCLR_RXRDY_Pos _UINT16_(0) /* (I2S_INTENCLR Position) Receive Ready x Interrupt Enable */ 165 #define I2S_INTENCLR_RXRDY_Msk (_UINT16_(0x3) << I2S_INTENCLR_RXRDY_Pos) /* (I2S_INTENCLR Mask) RXRDY */ 166 #define I2S_INTENCLR_RXRDY(value) (I2S_INTENCLR_RXRDY_Msk & (_UINT16_(value) << I2S_INTENCLR_RXRDY_Pos)) 167 #define I2S_INTENCLR_RXOR_Pos _UINT16_(4) /* (I2S_INTENCLR Position) Receive Overrun x Interrupt Enable */ 168 #define I2S_INTENCLR_RXOR_Msk (_UINT16_(0x3) << I2S_INTENCLR_RXOR_Pos) /* (I2S_INTENCLR Mask) RXOR */ 169 #define I2S_INTENCLR_RXOR(value) (I2S_INTENCLR_RXOR_Msk & (_UINT16_(value) << I2S_INTENCLR_RXOR_Pos)) 170 #define I2S_INTENCLR_TXRDY_Pos _UINT16_(8) /* (I2S_INTENCLR Position) Transmit Ready x Interrupt Enable */ 171 #define I2S_INTENCLR_TXRDY_Msk (_UINT16_(0x3) << I2S_INTENCLR_TXRDY_Pos) /* (I2S_INTENCLR Mask) TXRDY */ 172 #define I2S_INTENCLR_TXRDY(value) (I2S_INTENCLR_TXRDY_Msk & (_UINT16_(value) << I2S_INTENCLR_TXRDY_Pos)) 173 #define I2S_INTENCLR_TXUR_Pos _UINT16_(12) /* (I2S_INTENCLR Position) Transmit Underrun x Interrupt Enable */ 174 #define I2S_INTENCLR_TXUR_Msk (_UINT16_(0x3) << I2S_INTENCLR_TXUR_Pos) /* (I2S_INTENCLR Mask) TXUR */ 175 #define I2S_INTENCLR_TXUR(value) (I2S_INTENCLR_TXUR_Msk & (_UINT16_(value) << I2S_INTENCLR_TXUR_Pos)) 176 177 /* -------- I2S_INTENSET : (I2S Offset: 0x10) (R/W 16) Interrupt Enable Set -------- */ 178 #define I2S_INTENSET_RESETVALUE _UINT16_(0x00) /* (I2S_INTENSET) Interrupt Enable Set Reset Value */ 179 180 #define I2S_INTENSET_RXRDY0_Pos _UINT16_(0) /* (I2S_INTENSET) Receive Ready 0 Interrupt Enable Position */ 181 #define I2S_INTENSET_RXRDY0_Msk (_UINT16_(0x1) << I2S_INTENSET_RXRDY0_Pos) /* (I2S_INTENSET) Receive Ready 0 Interrupt Enable Mask */ 182 #define I2S_INTENSET_RXRDY0(value) (I2S_INTENSET_RXRDY0_Msk & (_UINT16_(value) << I2S_INTENSET_RXRDY0_Pos)) /* Assigment of value for RXRDY0 in the I2S_INTENSET register */ 183 #define I2S_INTENSET_RXRDY1_Pos _UINT16_(1) /* (I2S_INTENSET) Receive Ready 1 Interrupt Enable Position */ 184 #define I2S_INTENSET_RXRDY1_Msk (_UINT16_(0x1) << I2S_INTENSET_RXRDY1_Pos) /* (I2S_INTENSET) Receive Ready 1 Interrupt Enable Mask */ 185 #define I2S_INTENSET_RXRDY1(value) (I2S_INTENSET_RXRDY1_Msk & (_UINT16_(value) << I2S_INTENSET_RXRDY1_Pos)) /* Assigment of value for RXRDY1 in the I2S_INTENSET register */ 186 #define I2S_INTENSET_RXOR0_Pos _UINT16_(4) /* (I2S_INTENSET) Receive Overrun 0 Interrupt Enable Position */ 187 #define I2S_INTENSET_RXOR0_Msk (_UINT16_(0x1) << I2S_INTENSET_RXOR0_Pos) /* (I2S_INTENSET) Receive Overrun 0 Interrupt Enable Mask */ 188 #define I2S_INTENSET_RXOR0(value) (I2S_INTENSET_RXOR0_Msk & (_UINT16_(value) << I2S_INTENSET_RXOR0_Pos)) /* Assigment of value for RXOR0 in the I2S_INTENSET register */ 189 #define I2S_INTENSET_RXOR1_Pos _UINT16_(5) /* (I2S_INTENSET) Receive Overrun 1 Interrupt Enable Position */ 190 #define I2S_INTENSET_RXOR1_Msk (_UINT16_(0x1) << I2S_INTENSET_RXOR1_Pos) /* (I2S_INTENSET) Receive Overrun 1 Interrupt Enable Mask */ 191 #define I2S_INTENSET_RXOR1(value) (I2S_INTENSET_RXOR1_Msk & (_UINT16_(value) << I2S_INTENSET_RXOR1_Pos)) /* Assigment of value for RXOR1 in the I2S_INTENSET register */ 192 #define I2S_INTENSET_TXRDY0_Pos _UINT16_(8) /* (I2S_INTENSET) Transmit Ready 0 Interrupt Enable Position */ 193 #define I2S_INTENSET_TXRDY0_Msk (_UINT16_(0x1) << I2S_INTENSET_TXRDY0_Pos) /* (I2S_INTENSET) Transmit Ready 0 Interrupt Enable Mask */ 194 #define I2S_INTENSET_TXRDY0(value) (I2S_INTENSET_TXRDY0_Msk & (_UINT16_(value) << I2S_INTENSET_TXRDY0_Pos)) /* Assigment of value for TXRDY0 in the I2S_INTENSET register */ 195 #define I2S_INTENSET_TXRDY1_Pos _UINT16_(9) /* (I2S_INTENSET) Transmit Ready 1 Interrupt Enable Position */ 196 #define I2S_INTENSET_TXRDY1_Msk (_UINT16_(0x1) << I2S_INTENSET_TXRDY1_Pos) /* (I2S_INTENSET) Transmit Ready 1 Interrupt Enable Mask */ 197 #define I2S_INTENSET_TXRDY1(value) (I2S_INTENSET_TXRDY1_Msk & (_UINT16_(value) << I2S_INTENSET_TXRDY1_Pos)) /* Assigment of value for TXRDY1 in the I2S_INTENSET register */ 198 #define I2S_INTENSET_TXUR0_Pos _UINT16_(12) /* (I2S_INTENSET) Transmit Underrun 0 Interrupt Enable Position */ 199 #define I2S_INTENSET_TXUR0_Msk (_UINT16_(0x1) << I2S_INTENSET_TXUR0_Pos) /* (I2S_INTENSET) Transmit Underrun 0 Interrupt Enable Mask */ 200 #define I2S_INTENSET_TXUR0(value) (I2S_INTENSET_TXUR0_Msk & (_UINT16_(value) << I2S_INTENSET_TXUR0_Pos)) /* Assigment of value for TXUR0 in the I2S_INTENSET register */ 201 #define I2S_INTENSET_TXUR1_Pos _UINT16_(13) /* (I2S_INTENSET) Transmit Underrun 1 Interrupt Enable Position */ 202 #define I2S_INTENSET_TXUR1_Msk (_UINT16_(0x1) << I2S_INTENSET_TXUR1_Pos) /* (I2S_INTENSET) Transmit Underrun 1 Interrupt Enable Mask */ 203 #define I2S_INTENSET_TXUR1(value) (I2S_INTENSET_TXUR1_Msk & (_UINT16_(value) << I2S_INTENSET_TXUR1_Pos)) /* Assigment of value for TXUR1 in the I2S_INTENSET register */ 204 #define I2S_INTENSET_Msk _UINT16_(0x3333) /* (I2S_INTENSET) Register Mask */ 205 206 #define I2S_INTENSET_RXRDY_Pos _UINT16_(0) /* (I2S_INTENSET Position) Receive Ready x Interrupt Enable */ 207 #define I2S_INTENSET_RXRDY_Msk (_UINT16_(0x3) << I2S_INTENSET_RXRDY_Pos) /* (I2S_INTENSET Mask) RXRDY */ 208 #define I2S_INTENSET_RXRDY(value) (I2S_INTENSET_RXRDY_Msk & (_UINT16_(value) << I2S_INTENSET_RXRDY_Pos)) 209 #define I2S_INTENSET_RXOR_Pos _UINT16_(4) /* (I2S_INTENSET Position) Receive Overrun x Interrupt Enable */ 210 #define I2S_INTENSET_RXOR_Msk (_UINT16_(0x3) << I2S_INTENSET_RXOR_Pos) /* (I2S_INTENSET Mask) RXOR */ 211 #define I2S_INTENSET_RXOR(value) (I2S_INTENSET_RXOR_Msk & (_UINT16_(value) << I2S_INTENSET_RXOR_Pos)) 212 #define I2S_INTENSET_TXRDY_Pos _UINT16_(8) /* (I2S_INTENSET Position) Transmit Ready x Interrupt Enable */ 213 #define I2S_INTENSET_TXRDY_Msk (_UINT16_(0x3) << I2S_INTENSET_TXRDY_Pos) /* (I2S_INTENSET Mask) TXRDY */ 214 #define I2S_INTENSET_TXRDY(value) (I2S_INTENSET_TXRDY_Msk & (_UINT16_(value) << I2S_INTENSET_TXRDY_Pos)) 215 #define I2S_INTENSET_TXUR_Pos _UINT16_(12) /* (I2S_INTENSET Position) Transmit Underrun x Interrupt Enable */ 216 #define I2S_INTENSET_TXUR_Msk (_UINT16_(0x3) << I2S_INTENSET_TXUR_Pos) /* (I2S_INTENSET Mask) TXUR */ 217 #define I2S_INTENSET_TXUR(value) (I2S_INTENSET_TXUR_Msk & (_UINT16_(value) << I2S_INTENSET_TXUR_Pos)) 218 219 /* -------- I2S_INTFLAG : (I2S Offset: 0x14) (R/W 16) Interrupt Flag Status and Clear -------- */ 220 #define I2S_INTFLAG_RESETVALUE _UINT16_(0x00) /* (I2S_INTFLAG) Interrupt Flag Status and Clear Reset Value */ 221 222 #define I2S_INTFLAG_RXRDY0_Pos _UINT16_(0) /* (I2S_INTFLAG) Receive Ready 0 Position */ 223 #define I2S_INTFLAG_RXRDY0_Msk (_UINT16_(0x1) << I2S_INTFLAG_RXRDY0_Pos) /* (I2S_INTFLAG) Receive Ready 0 Mask */ 224 #define I2S_INTFLAG_RXRDY0(value) (I2S_INTFLAG_RXRDY0_Msk & (_UINT16_(value) << I2S_INTFLAG_RXRDY0_Pos)) /* Assigment of value for RXRDY0 in the I2S_INTFLAG register */ 225 #define I2S_INTFLAG_RXRDY1_Pos _UINT16_(1) /* (I2S_INTFLAG) Receive Ready 1 Position */ 226 #define I2S_INTFLAG_RXRDY1_Msk (_UINT16_(0x1) << I2S_INTFLAG_RXRDY1_Pos) /* (I2S_INTFLAG) Receive Ready 1 Mask */ 227 #define I2S_INTFLAG_RXRDY1(value) (I2S_INTFLAG_RXRDY1_Msk & (_UINT16_(value) << I2S_INTFLAG_RXRDY1_Pos)) /* Assigment of value for RXRDY1 in the I2S_INTFLAG register */ 228 #define I2S_INTFLAG_RXOR0_Pos _UINT16_(4) /* (I2S_INTFLAG) Receive Overrun 0 Position */ 229 #define I2S_INTFLAG_RXOR0_Msk (_UINT16_(0x1) << I2S_INTFLAG_RXOR0_Pos) /* (I2S_INTFLAG) Receive Overrun 0 Mask */ 230 #define I2S_INTFLAG_RXOR0(value) (I2S_INTFLAG_RXOR0_Msk & (_UINT16_(value) << I2S_INTFLAG_RXOR0_Pos)) /* Assigment of value for RXOR0 in the I2S_INTFLAG register */ 231 #define I2S_INTFLAG_RXOR1_Pos _UINT16_(5) /* (I2S_INTFLAG) Receive Overrun 1 Position */ 232 #define I2S_INTFLAG_RXOR1_Msk (_UINT16_(0x1) << I2S_INTFLAG_RXOR1_Pos) /* (I2S_INTFLAG) Receive Overrun 1 Mask */ 233 #define I2S_INTFLAG_RXOR1(value) (I2S_INTFLAG_RXOR1_Msk & (_UINT16_(value) << I2S_INTFLAG_RXOR1_Pos)) /* Assigment of value for RXOR1 in the I2S_INTFLAG register */ 234 #define I2S_INTFLAG_TXRDY0_Pos _UINT16_(8) /* (I2S_INTFLAG) Transmit Ready 0 Position */ 235 #define I2S_INTFLAG_TXRDY0_Msk (_UINT16_(0x1) << I2S_INTFLAG_TXRDY0_Pos) /* (I2S_INTFLAG) Transmit Ready 0 Mask */ 236 #define I2S_INTFLAG_TXRDY0(value) (I2S_INTFLAG_TXRDY0_Msk & (_UINT16_(value) << I2S_INTFLAG_TXRDY0_Pos)) /* Assigment of value for TXRDY0 in the I2S_INTFLAG register */ 237 #define I2S_INTFLAG_TXRDY1_Pos _UINT16_(9) /* (I2S_INTFLAG) Transmit Ready 1 Position */ 238 #define I2S_INTFLAG_TXRDY1_Msk (_UINT16_(0x1) << I2S_INTFLAG_TXRDY1_Pos) /* (I2S_INTFLAG) Transmit Ready 1 Mask */ 239 #define I2S_INTFLAG_TXRDY1(value) (I2S_INTFLAG_TXRDY1_Msk & (_UINT16_(value) << I2S_INTFLAG_TXRDY1_Pos)) /* Assigment of value for TXRDY1 in the I2S_INTFLAG register */ 240 #define I2S_INTFLAG_TXUR0_Pos _UINT16_(12) /* (I2S_INTFLAG) Transmit Underrun 0 Position */ 241 #define I2S_INTFLAG_TXUR0_Msk (_UINT16_(0x1) << I2S_INTFLAG_TXUR0_Pos) /* (I2S_INTFLAG) Transmit Underrun 0 Mask */ 242 #define I2S_INTFLAG_TXUR0(value) (I2S_INTFLAG_TXUR0_Msk & (_UINT16_(value) << I2S_INTFLAG_TXUR0_Pos)) /* Assigment of value for TXUR0 in the I2S_INTFLAG register */ 243 #define I2S_INTFLAG_TXUR1_Pos _UINT16_(13) /* (I2S_INTFLAG) Transmit Underrun 1 Position */ 244 #define I2S_INTFLAG_TXUR1_Msk (_UINT16_(0x1) << I2S_INTFLAG_TXUR1_Pos) /* (I2S_INTFLAG) Transmit Underrun 1 Mask */ 245 #define I2S_INTFLAG_TXUR1(value) (I2S_INTFLAG_TXUR1_Msk & (_UINT16_(value) << I2S_INTFLAG_TXUR1_Pos)) /* Assigment of value for TXUR1 in the I2S_INTFLAG register */ 246 #define I2S_INTFLAG_Msk _UINT16_(0x3333) /* (I2S_INTFLAG) Register Mask */ 247 248 #define I2S_INTFLAG_RXRDY_Pos _UINT16_(0) /* (I2S_INTFLAG Position) Receive Ready x */ 249 #define I2S_INTFLAG_RXRDY_Msk (_UINT16_(0x3) << I2S_INTFLAG_RXRDY_Pos) /* (I2S_INTFLAG Mask) RXRDY */ 250 #define I2S_INTFLAG_RXRDY(value) (I2S_INTFLAG_RXRDY_Msk & (_UINT16_(value) << I2S_INTFLAG_RXRDY_Pos)) 251 #define I2S_INTFLAG_RXOR_Pos _UINT16_(4) /* (I2S_INTFLAG Position) Receive Overrun x */ 252 #define I2S_INTFLAG_RXOR_Msk (_UINT16_(0x3) << I2S_INTFLAG_RXOR_Pos) /* (I2S_INTFLAG Mask) RXOR */ 253 #define I2S_INTFLAG_RXOR(value) (I2S_INTFLAG_RXOR_Msk & (_UINT16_(value) << I2S_INTFLAG_RXOR_Pos)) 254 #define I2S_INTFLAG_TXRDY_Pos _UINT16_(8) /* (I2S_INTFLAG Position) Transmit Ready x */ 255 #define I2S_INTFLAG_TXRDY_Msk (_UINT16_(0x3) << I2S_INTFLAG_TXRDY_Pos) /* (I2S_INTFLAG Mask) TXRDY */ 256 #define I2S_INTFLAG_TXRDY(value) (I2S_INTFLAG_TXRDY_Msk & (_UINT16_(value) << I2S_INTFLAG_TXRDY_Pos)) 257 #define I2S_INTFLAG_TXUR_Pos _UINT16_(12) /* (I2S_INTFLAG Position) Transmit Underrun x */ 258 #define I2S_INTFLAG_TXUR_Msk (_UINT16_(0x3) << I2S_INTFLAG_TXUR_Pos) /* (I2S_INTFLAG Mask) TXUR */ 259 #define I2S_INTFLAG_TXUR(value) (I2S_INTFLAG_TXUR_Msk & (_UINT16_(value) << I2S_INTFLAG_TXUR_Pos)) 260 261 /* -------- I2S_SYNCBUSY : (I2S Offset: 0x18) ( R/ 16) Synchronization Status -------- */ 262 #define I2S_SYNCBUSY_RESETVALUE _UINT16_(0x00) /* (I2S_SYNCBUSY) Synchronization Status Reset Value */ 263 264 #define I2S_SYNCBUSY_SWRST_Pos _UINT16_(0) /* (I2S_SYNCBUSY) Software Reset Synchronization Status Position */ 265 #define I2S_SYNCBUSY_SWRST_Msk (_UINT16_(0x1) << I2S_SYNCBUSY_SWRST_Pos) /* (I2S_SYNCBUSY) Software Reset Synchronization Status Mask */ 266 #define I2S_SYNCBUSY_SWRST(value) (I2S_SYNCBUSY_SWRST_Msk & (_UINT16_(value) << I2S_SYNCBUSY_SWRST_Pos)) /* Assigment of value for SWRST in the I2S_SYNCBUSY register */ 267 #define I2S_SYNCBUSY_ENABLE_Pos _UINT16_(1) /* (I2S_SYNCBUSY) Enable Synchronization Status Position */ 268 #define I2S_SYNCBUSY_ENABLE_Msk (_UINT16_(0x1) << I2S_SYNCBUSY_ENABLE_Pos) /* (I2S_SYNCBUSY) Enable Synchronization Status Mask */ 269 #define I2S_SYNCBUSY_ENABLE(value) (I2S_SYNCBUSY_ENABLE_Msk & (_UINT16_(value) << I2S_SYNCBUSY_ENABLE_Pos)) /* Assigment of value for ENABLE in the I2S_SYNCBUSY register */ 270 #define I2S_SYNCBUSY_CKEN0_Pos _UINT16_(2) /* (I2S_SYNCBUSY) Clock Unit 0 Enable Synchronization Status Position */ 271 #define I2S_SYNCBUSY_CKEN0_Msk (_UINT16_(0x1) << I2S_SYNCBUSY_CKEN0_Pos) /* (I2S_SYNCBUSY) Clock Unit 0 Enable Synchronization Status Mask */ 272 #define I2S_SYNCBUSY_CKEN0(value) (I2S_SYNCBUSY_CKEN0_Msk & (_UINT16_(value) << I2S_SYNCBUSY_CKEN0_Pos)) /* Assigment of value for CKEN0 in the I2S_SYNCBUSY register */ 273 #define I2S_SYNCBUSY_CKEN1_Pos _UINT16_(3) /* (I2S_SYNCBUSY) Clock Unit 1 Enable Synchronization Status Position */ 274 #define I2S_SYNCBUSY_CKEN1_Msk (_UINT16_(0x1) << I2S_SYNCBUSY_CKEN1_Pos) /* (I2S_SYNCBUSY) Clock Unit 1 Enable Synchronization Status Mask */ 275 #define I2S_SYNCBUSY_CKEN1(value) (I2S_SYNCBUSY_CKEN1_Msk & (_UINT16_(value) << I2S_SYNCBUSY_CKEN1_Pos)) /* Assigment of value for CKEN1 in the I2S_SYNCBUSY register */ 276 #define I2S_SYNCBUSY_TXEN_Pos _UINT16_(4) /* (I2S_SYNCBUSY) Tx Serializer Enable Synchronization Status Position */ 277 #define I2S_SYNCBUSY_TXEN_Msk (_UINT16_(0x1) << I2S_SYNCBUSY_TXEN_Pos) /* (I2S_SYNCBUSY) Tx Serializer Enable Synchronization Status Mask */ 278 #define I2S_SYNCBUSY_TXEN(value) (I2S_SYNCBUSY_TXEN_Msk & (_UINT16_(value) << I2S_SYNCBUSY_TXEN_Pos)) /* Assigment of value for TXEN in the I2S_SYNCBUSY register */ 279 #define I2S_SYNCBUSY_RXEN_Pos _UINT16_(5) /* (I2S_SYNCBUSY) Rx Serializer Enable Synchronization Status Position */ 280 #define I2S_SYNCBUSY_RXEN_Msk (_UINT16_(0x1) << I2S_SYNCBUSY_RXEN_Pos) /* (I2S_SYNCBUSY) Rx Serializer Enable Synchronization Status Mask */ 281 #define I2S_SYNCBUSY_RXEN(value) (I2S_SYNCBUSY_RXEN_Msk & (_UINT16_(value) << I2S_SYNCBUSY_RXEN_Pos)) /* Assigment of value for RXEN in the I2S_SYNCBUSY register */ 282 #define I2S_SYNCBUSY_TXDATA_Pos _UINT16_(8) /* (I2S_SYNCBUSY) Tx Data Synchronization Status Position */ 283 #define I2S_SYNCBUSY_TXDATA_Msk (_UINT16_(0x1) << I2S_SYNCBUSY_TXDATA_Pos) /* (I2S_SYNCBUSY) Tx Data Synchronization Status Mask */ 284 #define I2S_SYNCBUSY_TXDATA(value) (I2S_SYNCBUSY_TXDATA_Msk & (_UINT16_(value) << I2S_SYNCBUSY_TXDATA_Pos)) /* Assigment of value for TXDATA in the I2S_SYNCBUSY register */ 285 #define I2S_SYNCBUSY_RXDATA_Pos _UINT16_(9) /* (I2S_SYNCBUSY) Rx Data Synchronization Status Position */ 286 #define I2S_SYNCBUSY_RXDATA_Msk (_UINT16_(0x1) << I2S_SYNCBUSY_RXDATA_Pos) /* (I2S_SYNCBUSY) Rx Data Synchronization Status Mask */ 287 #define I2S_SYNCBUSY_RXDATA(value) (I2S_SYNCBUSY_RXDATA_Msk & (_UINT16_(value) << I2S_SYNCBUSY_RXDATA_Pos)) /* Assigment of value for RXDATA in the I2S_SYNCBUSY register */ 288 #define I2S_SYNCBUSY_Msk _UINT16_(0x033F) /* (I2S_SYNCBUSY) Register Mask */ 289 290 #define I2S_SYNCBUSY_CKEN_Pos _UINT16_(2) /* (I2S_SYNCBUSY Position) Clock Unit x Enable Synchronization Status */ 291 #define I2S_SYNCBUSY_CKEN_Msk (_UINT16_(0x3) << I2S_SYNCBUSY_CKEN_Pos) /* (I2S_SYNCBUSY Mask) CKEN */ 292 #define I2S_SYNCBUSY_CKEN(value) (I2S_SYNCBUSY_CKEN_Msk & (_UINT16_(value) << I2S_SYNCBUSY_CKEN_Pos)) 293 294 /* -------- I2S_TXCTRL : (I2S Offset: 0x20) (R/W 32) Tx Serializer Control -------- */ 295 #define I2S_TXCTRL_RESETVALUE _UINT32_(0x00) /* (I2S_TXCTRL) Tx Serializer Control Reset Value */ 296 297 #define I2S_TXCTRL_TXDEFAULT_Pos _UINT32_(2) /* (I2S_TXCTRL) Line Default Line when Slot Disabled Position */ 298 #define I2S_TXCTRL_TXDEFAULT_Msk (_UINT32_(0x3) << I2S_TXCTRL_TXDEFAULT_Pos) /* (I2S_TXCTRL) Line Default Line when Slot Disabled Mask */ 299 #define I2S_TXCTRL_TXDEFAULT(value) (I2S_TXCTRL_TXDEFAULT_Msk & (_UINT32_(value) << I2S_TXCTRL_TXDEFAULT_Pos)) /* Assigment of value for TXDEFAULT in the I2S_TXCTRL register */ 300 #define I2S_TXCTRL_TXDEFAULT_ZERO_Val _UINT32_(0x0) /* (I2S_TXCTRL) Output Default Value is 0 */ 301 #define I2S_TXCTRL_TXDEFAULT_ONE_Val _UINT32_(0x1) /* (I2S_TXCTRL) Output Default Value is 1 */ 302 #define I2S_TXCTRL_TXDEFAULT_HIZ_Val _UINT32_(0x3) /* (I2S_TXCTRL) Output Default Value is high impedance */ 303 #define I2S_TXCTRL_TXDEFAULT_ZERO (I2S_TXCTRL_TXDEFAULT_ZERO_Val << I2S_TXCTRL_TXDEFAULT_Pos) /* (I2S_TXCTRL) Output Default Value is 0 Position */ 304 #define I2S_TXCTRL_TXDEFAULT_ONE (I2S_TXCTRL_TXDEFAULT_ONE_Val << I2S_TXCTRL_TXDEFAULT_Pos) /* (I2S_TXCTRL) Output Default Value is 1 Position */ 305 #define I2S_TXCTRL_TXDEFAULT_HIZ (I2S_TXCTRL_TXDEFAULT_HIZ_Val << I2S_TXCTRL_TXDEFAULT_Pos) /* (I2S_TXCTRL) Output Default Value is high impedance Position */ 306 #define I2S_TXCTRL_TXSAME_Pos _UINT32_(4) /* (I2S_TXCTRL) Transmit Data when Underrun Position */ 307 #define I2S_TXCTRL_TXSAME_Msk (_UINT32_(0x1) << I2S_TXCTRL_TXSAME_Pos) /* (I2S_TXCTRL) Transmit Data when Underrun Mask */ 308 #define I2S_TXCTRL_TXSAME(value) (I2S_TXCTRL_TXSAME_Msk & (_UINT32_(value) << I2S_TXCTRL_TXSAME_Pos)) /* Assigment of value for TXSAME in the I2S_TXCTRL register */ 309 #define I2S_TXCTRL_TXSAME_ZERO_Val _UINT32_(0x0) /* (I2S_TXCTRL) Zero data transmitted in case of underrun */ 310 #define I2S_TXCTRL_TXSAME_SAME_Val _UINT32_(0x1) /* (I2S_TXCTRL) Last data transmitted in case of underrun */ 311 #define I2S_TXCTRL_TXSAME_ZERO (I2S_TXCTRL_TXSAME_ZERO_Val << I2S_TXCTRL_TXSAME_Pos) /* (I2S_TXCTRL) Zero data transmitted in case of underrun Position */ 312 #define I2S_TXCTRL_TXSAME_SAME (I2S_TXCTRL_TXSAME_SAME_Val << I2S_TXCTRL_TXSAME_Pos) /* (I2S_TXCTRL) Last data transmitted in case of underrun Position */ 313 #define I2S_TXCTRL_SLOTADJ_Pos _UINT32_(7) /* (I2S_TXCTRL) Data Slot Formatting Adjust Position */ 314 #define I2S_TXCTRL_SLOTADJ_Msk (_UINT32_(0x1) << I2S_TXCTRL_SLOTADJ_Pos) /* (I2S_TXCTRL) Data Slot Formatting Adjust Mask */ 315 #define I2S_TXCTRL_SLOTADJ(value) (I2S_TXCTRL_SLOTADJ_Msk & (_UINT32_(value) << I2S_TXCTRL_SLOTADJ_Pos)) /* Assigment of value for SLOTADJ in the I2S_TXCTRL register */ 316 #define I2S_TXCTRL_SLOTADJ_RIGHT_Val _UINT32_(0x0) /* (I2S_TXCTRL) Data is right adjusted in slot */ 317 #define I2S_TXCTRL_SLOTADJ_LEFT_Val _UINT32_(0x1) /* (I2S_TXCTRL) Data is left adjusted in slot */ 318 #define I2S_TXCTRL_SLOTADJ_RIGHT (I2S_TXCTRL_SLOTADJ_RIGHT_Val << I2S_TXCTRL_SLOTADJ_Pos) /* (I2S_TXCTRL) Data is right adjusted in slot Position */ 319 #define I2S_TXCTRL_SLOTADJ_LEFT (I2S_TXCTRL_SLOTADJ_LEFT_Val << I2S_TXCTRL_SLOTADJ_Pos) /* (I2S_TXCTRL) Data is left adjusted in slot Position */ 320 #define I2S_TXCTRL_DATASIZE_Pos _UINT32_(8) /* (I2S_TXCTRL) Data Word Size Position */ 321 #define I2S_TXCTRL_DATASIZE_Msk (_UINT32_(0x7) << I2S_TXCTRL_DATASIZE_Pos) /* (I2S_TXCTRL) Data Word Size Mask */ 322 #define I2S_TXCTRL_DATASIZE(value) (I2S_TXCTRL_DATASIZE_Msk & (_UINT32_(value) << I2S_TXCTRL_DATASIZE_Pos)) /* Assigment of value for DATASIZE in the I2S_TXCTRL register */ 323 #define I2S_TXCTRL_DATASIZE_32_Val _UINT32_(0x0) /* (I2S_TXCTRL) 32 bits */ 324 #define I2S_TXCTRL_DATASIZE_24_Val _UINT32_(0x1) /* (I2S_TXCTRL) 24 bits */ 325 #define I2S_TXCTRL_DATASIZE_20_Val _UINT32_(0x2) /* (I2S_TXCTRL) 20 bits */ 326 #define I2S_TXCTRL_DATASIZE_18_Val _UINT32_(0x3) /* (I2S_TXCTRL) 18 bits */ 327 #define I2S_TXCTRL_DATASIZE_16_Val _UINT32_(0x4) /* (I2S_TXCTRL) 16 bits */ 328 #define I2S_TXCTRL_DATASIZE_16C_Val _UINT32_(0x5) /* (I2S_TXCTRL) 16 bits compact stereo */ 329 #define I2S_TXCTRL_DATASIZE_8_Val _UINT32_(0x6) /* (I2S_TXCTRL) 8 bits */ 330 #define I2S_TXCTRL_DATASIZE_8C_Val _UINT32_(0x7) /* (I2S_TXCTRL) 8 bits compact stereo */ 331 #define I2S_TXCTRL_DATASIZE_32 (I2S_TXCTRL_DATASIZE_32_Val << I2S_TXCTRL_DATASIZE_Pos) /* (I2S_TXCTRL) 32 bits Position */ 332 #define I2S_TXCTRL_DATASIZE_24 (I2S_TXCTRL_DATASIZE_24_Val << I2S_TXCTRL_DATASIZE_Pos) /* (I2S_TXCTRL) 24 bits Position */ 333 #define I2S_TXCTRL_DATASIZE_20 (I2S_TXCTRL_DATASIZE_20_Val << I2S_TXCTRL_DATASIZE_Pos) /* (I2S_TXCTRL) 20 bits Position */ 334 #define I2S_TXCTRL_DATASIZE_18 (I2S_TXCTRL_DATASIZE_18_Val << I2S_TXCTRL_DATASIZE_Pos) /* (I2S_TXCTRL) 18 bits Position */ 335 #define I2S_TXCTRL_DATASIZE_16 (I2S_TXCTRL_DATASIZE_16_Val << I2S_TXCTRL_DATASIZE_Pos) /* (I2S_TXCTRL) 16 bits Position */ 336 #define I2S_TXCTRL_DATASIZE_16C (I2S_TXCTRL_DATASIZE_16C_Val << I2S_TXCTRL_DATASIZE_Pos) /* (I2S_TXCTRL) 16 bits compact stereo Position */ 337 #define I2S_TXCTRL_DATASIZE_8 (I2S_TXCTRL_DATASIZE_8_Val << I2S_TXCTRL_DATASIZE_Pos) /* (I2S_TXCTRL) 8 bits Position */ 338 #define I2S_TXCTRL_DATASIZE_8C (I2S_TXCTRL_DATASIZE_8C_Val << I2S_TXCTRL_DATASIZE_Pos) /* (I2S_TXCTRL) 8 bits compact stereo Position */ 339 #define I2S_TXCTRL_WORDADJ_Pos _UINT32_(12) /* (I2S_TXCTRL) Data Word Formatting Adjust Position */ 340 #define I2S_TXCTRL_WORDADJ_Msk (_UINT32_(0x1) << I2S_TXCTRL_WORDADJ_Pos) /* (I2S_TXCTRL) Data Word Formatting Adjust Mask */ 341 #define I2S_TXCTRL_WORDADJ(value) (I2S_TXCTRL_WORDADJ_Msk & (_UINT32_(value) << I2S_TXCTRL_WORDADJ_Pos)) /* Assigment of value for WORDADJ in the I2S_TXCTRL register */ 342 #define I2S_TXCTRL_WORDADJ_RIGHT_Val _UINT32_(0x0) /* (I2S_TXCTRL) Data is right adjusted in word */ 343 #define I2S_TXCTRL_WORDADJ_LEFT_Val _UINT32_(0x1) /* (I2S_TXCTRL) Data is left adjusted in word */ 344 #define I2S_TXCTRL_WORDADJ_RIGHT (I2S_TXCTRL_WORDADJ_RIGHT_Val << I2S_TXCTRL_WORDADJ_Pos) /* (I2S_TXCTRL) Data is right adjusted in word Position */ 345 #define I2S_TXCTRL_WORDADJ_LEFT (I2S_TXCTRL_WORDADJ_LEFT_Val << I2S_TXCTRL_WORDADJ_Pos) /* (I2S_TXCTRL) Data is left adjusted in word Position */ 346 #define I2S_TXCTRL_EXTEND_Pos _UINT32_(13) /* (I2S_TXCTRL) Data Formatting Bit Extension Position */ 347 #define I2S_TXCTRL_EXTEND_Msk (_UINT32_(0x3) << I2S_TXCTRL_EXTEND_Pos) /* (I2S_TXCTRL) Data Formatting Bit Extension Mask */ 348 #define I2S_TXCTRL_EXTEND(value) (I2S_TXCTRL_EXTEND_Msk & (_UINT32_(value) << I2S_TXCTRL_EXTEND_Pos)) /* Assigment of value for EXTEND in the I2S_TXCTRL register */ 349 #define I2S_TXCTRL_EXTEND_ZERO_Val _UINT32_(0x0) /* (I2S_TXCTRL) Extend with zeroes */ 350 #define I2S_TXCTRL_EXTEND_ONE_Val _UINT32_(0x1) /* (I2S_TXCTRL) Extend with ones */ 351 #define I2S_TXCTRL_EXTEND_MSBIT_Val _UINT32_(0x2) /* (I2S_TXCTRL) Extend with Most Significant Bit */ 352 #define I2S_TXCTRL_EXTEND_LSBIT_Val _UINT32_(0x3) /* (I2S_TXCTRL) Extend with Least Significant Bit */ 353 #define I2S_TXCTRL_EXTEND_ZERO (I2S_TXCTRL_EXTEND_ZERO_Val << I2S_TXCTRL_EXTEND_Pos) /* (I2S_TXCTRL) Extend with zeroes Position */ 354 #define I2S_TXCTRL_EXTEND_ONE (I2S_TXCTRL_EXTEND_ONE_Val << I2S_TXCTRL_EXTEND_Pos) /* (I2S_TXCTRL) Extend with ones Position */ 355 #define I2S_TXCTRL_EXTEND_MSBIT (I2S_TXCTRL_EXTEND_MSBIT_Val << I2S_TXCTRL_EXTEND_Pos) /* (I2S_TXCTRL) Extend with Most Significant Bit Position */ 356 #define I2S_TXCTRL_EXTEND_LSBIT (I2S_TXCTRL_EXTEND_LSBIT_Val << I2S_TXCTRL_EXTEND_Pos) /* (I2S_TXCTRL) Extend with Least Significant Bit Position */ 357 #define I2S_TXCTRL_BITREV_Pos _UINT32_(15) /* (I2S_TXCTRL) Data Formatting Bit Reverse Position */ 358 #define I2S_TXCTRL_BITREV_Msk (_UINT32_(0x1) << I2S_TXCTRL_BITREV_Pos) /* (I2S_TXCTRL) Data Formatting Bit Reverse Mask */ 359 #define I2S_TXCTRL_BITREV(value) (I2S_TXCTRL_BITREV_Msk & (_UINT32_(value) << I2S_TXCTRL_BITREV_Pos)) /* Assigment of value for BITREV in the I2S_TXCTRL register */ 360 #define I2S_TXCTRL_BITREV_MSBIT_Val _UINT32_(0x0) /* (I2S_TXCTRL) Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) */ 361 #define I2S_TXCTRL_BITREV_LSBIT_Val _UINT32_(0x1) /* (I2S_TXCTRL) Transfer Data Least Significant Bit (LSB) first */ 362 #define I2S_TXCTRL_BITREV_MSBIT (I2S_TXCTRL_BITREV_MSBIT_Val << I2S_TXCTRL_BITREV_Pos) /* (I2S_TXCTRL) Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) Position */ 363 #define I2S_TXCTRL_BITREV_LSBIT (I2S_TXCTRL_BITREV_LSBIT_Val << I2S_TXCTRL_BITREV_Pos) /* (I2S_TXCTRL) Transfer Data Least Significant Bit (LSB) first Position */ 364 #define I2S_TXCTRL_SLOTDIS0_Pos _UINT32_(16) /* (I2S_TXCTRL) Slot 0 Disabled for this Serializer Position */ 365 #define I2S_TXCTRL_SLOTDIS0_Msk (_UINT32_(0x1) << I2S_TXCTRL_SLOTDIS0_Pos) /* (I2S_TXCTRL) Slot 0 Disabled for this Serializer Mask */ 366 #define I2S_TXCTRL_SLOTDIS0(value) (I2S_TXCTRL_SLOTDIS0_Msk & (_UINT32_(value) << I2S_TXCTRL_SLOTDIS0_Pos)) /* Assigment of value for SLOTDIS0 in the I2S_TXCTRL register */ 367 #define I2S_TXCTRL_SLOTDIS1_Pos _UINT32_(17) /* (I2S_TXCTRL) Slot 1 Disabled for this Serializer Position */ 368 #define I2S_TXCTRL_SLOTDIS1_Msk (_UINT32_(0x1) << I2S_TXCTRL_SLOTDIS1_Pos) /* (I2S_TXCTRL) Slot 1 Disabled for this Serializer Mask */ 369 #define I2S_TXCTRL_SLOTDIS1(value) (I2S_TXCTRL_SLOTDIS1_Msk & (_UINT32_(value) << I2S_TXCTRL_SLOTDIS1_Pos)) /* Assigment of value for SLOTDIS1 in the I2S_TXCTRL register */ 370 #define I2S_TXCTRL_SLOTDIS2_Pos _UINT32_(18) /* (I2S_TXCTRL) Slot 2 Disabled for this Serializer Position */ 371 #define I2S_TXCTRL_SLOTDIS2_Msk (_UINT32_(0x1) << I2S_TXCTRL_SLOTDIS2_Pos) /* (I2S_TXCTRL) Slot 2 Disabled for this Serializer Mask */ 372 #define I2S_TXCTRL_SLOTDIS2(value) (I2S_TXCTRL_SLOTDIS2_Msk & (_UINT32_(value) << I2S_TXCTRL_SLOTDIS2_Pos)) /* Assigment of value for SLOTDIS2 in the I2S_TXCTRL register */ 373 #define I2S_TXCTRL_SLOTDIS3_Pos _UINT32_(19) /* (I2S_TXCTRL) Slot 3 Disabled for this Serializer Position */ 374 #define I2S_TXCTRL_SLOTDIS3_Msk (_UINT32_(0x1) << I2S_TXCTRL_SLOTDIS3_Pos) /* (I2S_TXCTRL) Slot 3 Disabled for this Serializer Mask */ 375 #define I2S_TXCTRL_SLOTDIS3(value) (I2S_TXCTRL_SLOTDIS3_Msk & (_UINT32_(value) << I2S_TXCTRL_SLOTDIS3_Pos)) /* Assigment of value for SLOTDIS3 in the I2S_TXCTRL register */ 376 #define I2S_TXCTRL_SLOTDIS4_Pos _UINT32_(20) /* (I2S_TXCTRL) Slot 4 Disabled for this Serializer Position */ 377 #define I2S_TXCTRL_SLOTDIS4_Msk (_UINT32_(0x1) << I2S_TXCTRL_SLOTDIS4_Pos) /* (I2S_TXCTRL) Slot 4 Disabled for this Serializer Mask */ 378 #define I2S_TXCTRL_SLOTDIS4(value) (I2S_TXCTRL_SLOTDIS4_Msk & (_UINT32_(value) << I2S_TXCTRL_SLOTDIS4_Pos)) /* Assigment of value for SLOTDIS4 in the I2S_TXCTRL register */ 379 #define I2S_TXCTRL_SLOTDIS5_Pos _UINT32_(21) /* (I2S_TXCTRL) Slot 5 Disabled for this Serializer Position */ 380 #define I2S_TXCTRL_SLOTDIS5_Msk (_UINT32_(0x1) << I2S_TXCTRL_SLOTDIS5_Pos) /* (I2S_TXCTRL) Slot 5 Disabled for this Serializer Mask */ 381 #define I2S_TXCTRL_SLOTDIS5(value) (I2S_TXCTRL_SLOTDIS5_Msk & (_UINT32_(value) << I2S_TXCTRL_SLOTDIS5_Pos)) /* Assigment of value for SLOTDIS5 in the I2S_TXCTRL register */ 382 #define I2S_TXCTRL_SLOTDIS6_Pos _UINT32_(22) /* (I2S_TXCTRL) Slot 6 Disabled for this Serializer Position */ 383 #define I2S_TXCTRL_SLOTDIS6_Msk (_UINT32_(0x1) << I2S_TXCTRL_SLOTDIS6_Pos) /* (I2S_TXCTRL) Slot 6 Disabled for this Serializer Mask */ 384 #define I2S_TXCTRL_SLOTDIS6(value) (I2S_TXCTRL_SLOTDIS6_Msk & (_UINT32_(value) << I2S_TXCTRL_SLOTDIS6_Pos)) /* Assigment of value for SLOTDIS6 in the I2S_TXCTRL register */ 385 #define I2S_TXCTRL_SLOTDIS7_Pos _UINT32_(23) /* (I2S_TXCTRL) Slot 7 Disabled for this Serializer Position */ 386 #define I2S_TXCTRL_SLOTDIS7_Msk (_UINT32_(0x1) << I2S_TXCTRL_SLOTDIS7_Pos) /* (I2S_TXCTRL) Slot 7 Disabled for this Serializer Mask */ 387 #define I2S_TXCTRL_SLOTDIS7(value) (I2S_TXCTRL_SLOTDIS7_Msk & (_UINT32_(value) << I2S_TXCTRL_SLOTDIS7_Pos)) /* Assigment of value for SLOTDIS7 in the I2S_TXCTRL register */ 388 #define I2S_TXCTRL_MONO_Pos _UINT32_(24) /* (I2S_TXCTRL) Mono Mode Position */ 389 #define I2S_TXCTRL_MONO_Msk (_UINT32_(0x1) << I2S_TXCTRL_MONO_Pos) /* (I2S_TXCTRL) Mono Mode Mask */ 390 #define I2S_TXCTRL_MONO(value) (I2S_TXCTRL_MONO_Msk & (_UINT32_(value) << I2S_TXCTRL_MONO_Pos)) /* Assigment of value for MONO in the I2S_TXCTRL register */ 391 #define I2S_TXCTRL_MONO_STEREO_Val _UINT32_(0x0) /* (I2S_TXCTRL) Normal mode */ 392 #define I2S_TXCTRL_MONO_MONO_Val _UINT32_(0x1) /* (I2S_TXCTRL) Left channel data is duplicated to right channel */ 393 #define I2S_TXCTRL_MONO_STEREO (I2S_TXCTRL_MONO_STEREO_Val << I2S_TXCTRL_MONO_Pos) /* (I2S_TXCTRL) Normal mode Position */ 394 #define I2S_TXCTRL_MONO_MONO (I2S_TXCTRL_MONO_MONO_Val << I2S_TXCTRL_MONO_Pos) /* (I2S_TXCTRL) Left channel data is duplicated to right channel Position */ 395 #define I2S_TXCTRL_DMA_Pos _UINT32_(25) /* (I2S_TXCTRL) Single or Multiple DMA Channels Position */ 396 #define I2S_TXCTRL_DMA_Msk (_UINT32_(0x1) << I2S_TXCTRL_DMA_Pos) /* (I2S_TXCTRL) Single or Multiple DMA Channels Mask */ 397 #define I2S_TXCTRL_DMA(value) (I2S_TXCTRL_DMA_Msk & (_UINT32_(value) << I2S_TXCTRL_DMA_Pos)) /* Assigment of value for DMA in the I2S_TXCTRL register */ 398 #define I2S_TXCTRL_DMA_SINGLE_Val _UINT32_(0x0) /* (I2S_TXCTRL) Single DMA channel */ 399 #define I2S_TXCTRL_DMA_MULTIPLE_Val _UINT32_(0x1) /* (I2S_TXCTRL) One DMA channel per data channel */ 400 #define I2S_TXCTRL_DMA_SINGLE (I2S_TXCTRL_DMA_SINGLE_Val << I2S_TXCTRL_DMA_Pos) /* (I2S_TXCTRL) Single DMA channel Position */ 401 #define I2S_TXCTRL_DMA_MULTIPLE (I2S_TXCTRL_DMA_MULTIPLE_Val << I2S_TXCTRL_DMA_Pos) /* (I2S_TXCTRL) One DMA channel per data channel Position */ 402 #define I2S_TXCTRL_Msk _UINT32_(0x03FFF79C) /* (I2S_TXCTRL) Register Mask */ 403 404 #define I2S_TXCTRL_SLOTDIS_Pos _UINT32_(16) /* (I2S_TXCTRL Position) Slot x Disabled for this Serializer */ 405 #define I2S_TXCTRL_SLOTDIS_Msk (_UINT32_(0xFF) << I2S_TXCTRL_SLOTDIS_Pos) /* (I2S_TXCTRL Mask) SLOTDIS */ 406 #define I2S_TXCTRL_SLOTDIS(value) (I2S_TXCTRL_SLOTDIS_Msk & (_UINT32_(value) << I2S_TXCTRL_SLOTDIS_Pos)) 407 408 /* -------- I2S_RXCTRL : (I2S Offset: 0x24) (R/W 32) Rx Serializer Control -------- */ 409 #define I2S_RXCTRL_RESETVALUE _UINT32_(0x00) /* (I2S_RXCTRL) Rx Serializer Control Reset Value */ 410 411 #define I2S_RXCTRL_SERMODE_Pos _UINT32_(0) /* (I2S_RXCTRL) Serializer Mode Position */ 412 #define I2S_RXCTRL_SERMODE_Msk (_UINT32_(0x3) << I2S_RXCTRL_SERMODE_Pos) /* (I2S_RXCTRL) Serializer Mode Mask */ 413 #define I2S_RXCTRL_SERMODE(value) (I2S_RXCTRL_SERMODE_Msk & (_UINT32_(value) << I2S_RXCTRL_SERMODE_Pos)) /* Assigment of value for SERMODE in the I2S_RXCTRL register */ 414 #define I2S_RXCTRL_SERMODE_RX_Val _UINT32_(0x0) /* (I2S_RXCTRL) Receive */ 415 #define I2S_RXCTRL_SERMODE_PDM2_Val _UINT32_(0x2) /* (I2S_RXCTRL) Receive one PDM data on each serial clock edge */ 416 #define I2S_RXCTRL_SERMODE_RX (I2S_RXCTRL_SERMODE_RX_Val << I2S_RXCTRL_SERMODE_Pos) /* (I2S_RXCTRL) Receive Position */ 417 #define I2S_RXCTRL_SERMODE_PDM2 (I2S_RXCTRL_SERMODE_PDM2_Val << I2S_RXCTRL_SERMODE_Pos) /* (I2S_RXCTRL) Receive one PDM data on each serial clock edge Position */ 418 #define I2S_RXCTRL_CLKSEL_Pos _UINT32_(5) /* (I2S_RXCTRL) Clock Unit Selection Position */ 419 #define I2S_RXCTRL_CLKSEL_Msk (_UINT32_(0x1) << I2S_RXCTRL_CLKSEL_Pos) /* (I2S_RXCTRL) Clock Unit Selection Mask */ 420 #define I2S_RXCTRL_CLKSEL(value) (I2S_RXCTRL_CLKSEL_Msk & (_UINT32_(value) << I2S_RXCTRL_CLKSEL_Pos)) /* Assigment of value for CLKSEL in the I2S_RXCTRL register */ 421 #define I2S_RXCTRL_CLKSEL_CLK0_Val _UINT32_(0x0) /* (I2S_RXCTRL) Use Clock Unit 0 */ 422 #define I2S_RXCTRL_CLKSEL_CLK1_Val _UINT32_(0x1) /* (I2S_RXCTRL) Use Clock Unit 1 */ 423 #define I2S_RXCTRL_CLKSEL_CLK0 (I2S_RXCTRL_CLKSEL_CLK0_Val << I2S_RXCTRL_CLKSEL_Pos) /* (I2S_RXCTRL) Use Clock Unit 0 Position */ 424 #define I2S_RXCTRL_CLKSEL_CLK1 (I2S_RXCTRL_CLKSEL_CLK1_Val << I2S_RXCTRL_CLKSEL_Pos) /* (I2S_RXCTRL) Use Clock Unit 1 Position */ 425 #define I2S_RXCTRL_SLOTADJ_Pos _UINT32_(7) /* (I2S_RXCTRL) Data Slot Formatting Adjust Position */ 426 #define I2S_RXCTRL_SLOTADJ_Msk (_UINT32_(0x1) << I2S_RXCTRL_SLOTADJ_Pos) /* (I2S_RXCTRL) Data Slot Formatting Adjust Mask */ 427 #define I2S_RXCTRL_SLOTADJ(value) (I2S_RXCTRL_SLOTADJ_Msk & (_UINT32_(value) << I2S_RXCTRL_SLOTADJ_Pos)) /* Assigment of value for SLOTADJ in the I2S_RXCTRL register */ 428 #define I2S_RXCTRL_SLOTADJ_RIGHT_Val _UINT32_(0x0) /* (I2S_RXCTRL) Data is right adjusted in slot */ 429 #define I2S_RXCTRL_SLOTADJ_LEFT_Val _UINT32_(0x1) /* (I2S_RXCTRL) Data is left adjusted in slot */ 430 #define I2S_RXCTRL_SLOTADJ_RIGHT (I2S_RXCTRL_SLOTADJ_RIGHT_Val << I2S_RXCTRL_SLOTADJ_Pos) /* (I2S_RXCTRL) Data is right adjusted in slot Position */ 431 #define I2S_RXCTRL_SLOTADJ_LEFT (I2S_RXCTRL_SLOTADJ_LEFT_Val << I2S_RXCTRL_SLOTADJ_Pos) /* (I2S_RXCTRL) Data is left adjusted in slot Position */ 432 #define I2S_RXCTRL_DATASIZE_Pos _UINT32_(8) /* (I2S_RXCTRL) Data Word Size Position */ 433 #define I2S_RXCTRL_DATASIZE_Msk (_UINT32_(0x7) << I2S_RXCTRL_DATASIZE_Pos) /* (I2S_RXCTRL) Data Word Size Mask */ 434 #define I2S_RXCTRL_DATASIZE(value) (I2S_RXCTRL_DATASIZE_Msk & (_UINT32_(value) << I2S_RXCTRL_DATASIZE_Pos)) /* Assigment of value for DATASIZE in the I2S_RXCTRL register */ 435 #define I2S_RXCTRL_DATASIZE_32_Val _UINT32_(0x0) /* (I2S_RXCTRL) 32 bits */ 436 #define I2S_RXCTRL_DATASIZE_24_Val _UINT32_(0x1) /* (I2S_RXCTRL) 24 bits */ 437 #define I2S_RXCTRL_DATASIZE_20_Val _UINT32_(0x2) /* (I2S_RXCTRL) 20 bits */ 438 #define I2S_RXCTRL_DATASIZE_18_Val _UINT32_(0x3) /* (I2S_RXCTRL) 18 bits */ 439 #define I2S_RXCTRL_DATASIZE_16_Val _UINT32_(0x4) /* (I2S_RXCTRL) 16 bits */ 440 #define I2S_RXCTRL_DATASIZE_16C_Val _UINT32_(0x5) /* (I2S_RXCTRL) 16 bits compact stereo */ 441 #define I2S_RXCTRL_DATASIZE_8_Val _UINT32_(0x6) /* (I2S_RXCTRL) 8 bits */ 442 #define I2S_RXCTRL_DATASIZE_8C_Val _UINT32_(0x7) /* (I2S_RXCTRL) 8 bits compact stereo */ 443 #define I2S_RXCTRL_DATASIZE_32 (I2S_RXCTRL_DATASIZE_32_Val << I2S_RXCTRL_DATASIZE_Pos) /* (I2S_RXCTRL) 32 bits Position */ 444 #define I2S_RXCTRL_DATASIZE_24 (I2S_RXCTRL_DATASIZE_24_Val << I2S_RXCTRL_DATASIZE_Pos) /* (I2S_RXCTRL) 24 bits Position */ 445 #define I2S_RXCTRL_DATASIZE_20 (I2S_RXCTRL_DATASIZE_20_Val << I2S_RXCTRL_DATASIZE_Pos) /* (I2S_RXCTRL) 20 bits Position */ 446 #define I2S_RXCTRL_DATASIZE_18 (I2S_RXCTRL_DATASIZE_18_Val << I2S_RXCTRL_DATASIZE_Pos) /* (I2S_RXCTRL) 18 bits Position */ 447 #define I2S_RXCTRL_DATASIZE_16 (I2S_RXCTRL_DATASIZE_16_Val << I2S_RXCTRL_DATASIZE_Pos) /* (I2S_RXCTRL) 16 bits Position */ 448 #define I2S_RXCTRL_DATASIZE_16C (I2S_RXCTRL_DATASIZE_16C_Val << I2S_RXCTRL_DATASIZE_Pos) /* (I2S_RXCTRL) 16 bits compact stereo Position */ 449 #define I2S_RXCTRL_DATASIZE_8 (I2S_RXCTRL_DATASIZE_8_Val << I2S_RXCTRL_DATASIZE_Pos) /* (I2S_RXCTRL) 8 bits Position */ 450 #define I2S_RXCTRL_DATASIZE_8C (I2S_RXCTRL_DATASIZE_8C_Val << I2S_RXCTRL_DATASIZE_Pos) /* (I2S_RXCTRL) 8 bits compact stereo Position */ 451 #define I2S_RXCTRL_WORDADJ_Pos _UINT32_(12) /* (I2S_RXCTRL) Data Word Formatting Adjust Position */ 452 #define I2S_RXCTRL_WORDADJ_Msk (_UINT32_(0x1) << I2S_RXCTRL_WORDADJ_Pos) /* (I2S_RXCTRL) Data Word Formatting Adjust Mask */ 453 #define I2S_RXCTRL_WORDADJ(value) (I2S_RXCTRL_WORDADJ_Msk & (_UINT32_(value) << I2S_RXCTRL_WORDADJ_Pos)) /* Assigment of value for WORDADJ in the I2S_RXCTRL register */ 454 #define I2S_RXCTRL_WORDADJ_RIGHT_Val _UINT32_(0x0) /* (I2S_RXCTRL) Data is right adjusted in word */ 455 #define I2S_RXCTRL_WORDADJ_LEFT_Val _UINT32_(0x1) /* (I2S_RXCTRL) Data is left adjusted in word */ 456 #define I2S_RXCTRL_WORDADJ_RIGHT (I2S_RXCTRL_WORDADJ_RIGHT_Val << I2S_RXCTRL_WORDADJ_Pos) /* (I2S_RXCTRL) Data is right adjusted in word Position */ 457 #define I2S_RXCTRL_WORDADJ_LEFT (I2S_RXCTRL_WORDADJ_LEFT_Val << I2S_RXCTRL_WORDADJ_Pos) /* (I2S_RXCTRL) Data is left adjusted in word Position */ 458 #define I2S_RXCTRL_EXTEND_Pos _UINT32_(13) /* (I2S_RXCTRL) Data Formatting Bit Extension Position */ 459 #define I2S_RXCTRL_EXTEND_Msk (_UINT32_(0x3) << I2S_RXCTRL_EXTEND_Pos) /* (I2S_RXCTRL) Data Formatting Bit Extension Mask */ 460 #define I2S_RXCTRL_EXTEND(value) (I2S_RXCTRL_EXTEND_Msk & (_UINT32_(value) << I2S_RXCTRL_EXTEND_Pos)) /* Assigment of value for EXTEND in the I2S_RXCTRL register */ 461 #define I2S_RXCTRL_EXTEND_ZERO_Val _UINT32_(0x0) /* (I2S_RXCTRL) Extend with zeroes */ 462 #define I2S_RXCTRL_EXTEND_ONE_Val _UINT32_(0x1) /* (I2S_RXCTRL) Extend with ones */ 463 #define I2S_RXCTRL_EXTEND_MSBIT_Val _UINT32_(0x2) /* (I2S_RXCTRL) Extend with Most Significant Bit */ 464 #define I2S_RXCTRL_EXTEND_LSBIT_Val _UINT32_(0x3) /* (I2S_RXCTRL) Extend with Least Significant Bit */ 465 #define I2S_RXCTRL_EXTEND_ZERO (I2S_RXCTRL_EXTEND_ZERO_Val << I2S_RXCTRL_EXTEND_Pos) /* (I2S_RXCTRL) Extend with zeroes Position */ 466 #define I2S_RXCTRL_EXTEND_ONE (I2S_RXCTRL_EXTEND_ONE_Val << I2S_RXCTRL_EXTEND_Pos) /* (I2S_RXCTRL) Extend with ones Position */ 467 #define I2S_RXCTRL_EXTEND_MSBIT (I2S_RXCTRL_EXTEND_MSBIT_Val << I2S_RXCTRL_EXTEND_Pos) /* (I2S_RXCTRL) Extend with Most Significant Bit Position */ 468 #define I2S_RXCTRL_EXTEND_LSBIT (I2S_RXCTRL_EXTEND_LSBIT_Val << I2S_RXCTRL_EXTEND_Pos) /* (I2S_RXCTRL) Extend with Least Significant Bit Position */ 469 #define I2S_RXCTRL_BITREV_Pos _UINT32_(15) /* (I2S_RXCTRL) Data Formatting Bit Reverse Position */ 470 #define I2S_RXCTRL_BITREV_Msk (_UINT32_(0x1) << I2S_RXCTRL_BITREV_Pos) /* (I2S_RXCTRL) Data Formatting Bit Reverse Mask */ 471 #define I2S_RXCTRL_BITREV(value) (I2S_RXCTRL_BITREV_Msk & (_UINT32_(value) << I2S_RXCTRL_BITREV_Pos)) /* Assigment of value for BITREV in the I2S_RXCTRL register */ 472 #define I2S_RXCTRL_BITREV_MSBIT_Val _UINT32_(0x0) /* (I2S_RXCTRL) Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) */ 473 #define I2S_RXCTRL_BITREV_LSBIT_Val _UINT32_(0x1) /* (I2S_RXCTRL) Transfer Data Least Significant Bit (LSB) first */ 474 #define I2S_RXCTRL_BITREV_MSBIT (I2S_RXCTRL_BITREV_MSBIT_Val << I2S_RXCTRL_BITREV_Pos) /* (I2S_RXCTRL) Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) Position */ 475 #define I2S_RXCTRL_BITREV_LSBIT (I2S_RXCTRL_BITREV_LSBIT_Val << I2S_RXCTRL_BITREV_Pos) /* (I2S_RXCTRL) Transfer Data Least Significant Bit (LSB) first Position */ 476 #define I2S_RXCTRL_SLOTDIS0_Pos _UINT32_(16) /* (I2S_RXCTRL) Slot 0 Disabled for this Serializer Position */ 477 #define I2S_RXCTRL_SLOTDIS0_Msk (_UINT32_(0x1) << I2S_RXCTRL_SLOTDIS0_Pos) /* (I2S_RXCTRL) Slot 0 Disabled for this Serializer Mask */ 478 #define I2S_RXCTRL_SLOTDIS0(value) (I2S_RXCTRL_SLOTDIS0_Msk & (_UINT32_(value) << I2S_RXCTRL_SLOTDIS0_Pos)) /* Assigment of value for SLOTDIS0 in the I2S_RXCTRL register */ 479 #define I2S_RXCTRL_SLOTDIS1_Pos _UINT32_(17) /* (I2S_RXCTRL) Slot 1 Disabled for this Serializer Position */ 480 #define I2S_RXCTRL_SLOTDIS1_Msk (_UINT32_(0x1) << I2S_RXCTRL_SLOTDIS1_Pos) /* (I2S_RXCTRL) Slot 1 Disabled for this Serializer Mask */ 481 #define I2S_RXCTRL_SLOTDIS1(value) (I2S_RXCTRL_SLOTDIS1_Msk & (_UINT32_(value) << I2S_RXCTRL_SLOTDIS1_Pos)) /* Assigment of value for SLOTDIS1 in the I2S_RXCTRL register */ 482 #define I2S_RXCTRL_SLOTDIS2_Pos _UINT32_(18) /* (I2S_RXCTRL) Slot 2 Disabled for this Serializer Position */ 483 #define I2S_RXCTRL_SLOTDIS2_Msk (_UINT32_(0x1) << I2S_RXCTRL_SLOTDIS2_Pos) /* (I2S_RXCTRL) Slot 2 Disabled for this Serializer Mask */ 484 #define I2S_RXCTRL_SLOTDIS2(value) (I2S_RXCTRL_SLOTDIS2_Msk & (_UINT32_(value) << I2S_RXCTRL_SLOTDIS2_Pos)) /* Assigment of value for SLOTDIS2 in the I2S_RXCTRL register */ 485 #define I2S_RXCTRL_SLOTDIS3_Pos _UINT32_(19) /* (I2S_RXCTRL) Slot 3 Disabled for this Serializer Position */ 486 #define I2S_RXCTRL_SLOTDIS3_Msk (_UINT32_(0x1) << I2S_RXCTRL_SLOTDIS3_Pos) /* (I2S_RXCTRL) Slot 3 Disabled for this Serializer Mask */ 487 #define I2S_RXCTRL_SLOTDIS3(value) (I2S_RXCTRL_SLOTDIS3_Msk & (_UINT32_(value) << I2S_RXCTRL_SLOTDIS3_Pos)) /* Assigment of value for SLOTDIS3 in the I2S_RXCTRL register */ 488 #define I2S_RXCTRL_SLOTDIS4_Pos _UINT32_(20) /* (I2S_RXCTRL) Slot 4 Disabled for this Serializer Position */ 489 #define I2S_RXCTRL_SLOTDIS4_Msk (_UINT32_(0x1) << I2S_RXCTRL_SLOTDIS4_Pos) /* (I2S_RXCTRL) Slot 4 Disabled for this Serializer Mask */ 490 #define I2S_RXCTRL_SLOTDIS4(value) (I2S_RXCTRL_SLOTDIS4_Msk & (_UINT32_(value) << I2S_RXCTRL_SLOTDIS4_Pos)) /* Assigment of value for SLOTDIS4 in the I2S_RXCTRL register */ 491 #define I2S_RXCTRL_SLOTDIS5_Pos _UINT32_(21) /* (I2S_RXCTRL) Slot 5 Disabled for this Serializer Position */ 492 #define I2S_RXCTRL_SLOTDIS5_Msk (_UINT32_(0x1) << I2S_RXCTRL_SLOTDIS5_Pos) /* (I2S_RXCTRL) Slot 5 Disabled for this Serializer Mask */ 493 #define I2S_RXCTRL_SLOTDIS5(value) (I2S_RXCTRL_SLOTDIS5_Msk & (_UINT32_(value) << I2S_RXCTRL_SLOTDIS5_Pos)) /* Assigment of value for SLOTDIS5 in the I2S_RXCTRL register */ 494 #define I2S_RXCTRL_SLOTDIS6_Pos _UINT32_(22) /* (I2S_RXCTRL) Slot 6 Disabled for this Serializer Position */ 495 #define I2S_RXCTRL_SLOTDIS6_Msk (_UINT32_(0x1) << I2S_RXCTRL_SLOTDIS6_Pos) /* (I2S_RXCTRL) Slot 6 Disabled for this Serializer Mask */ 496 #define I2S_RXCTRL_SLOTDIS6(value) (I2S_RXCTRL_SLOTDIS6_Msk & (_UINT32_(value) << I2S_RXCTRL_SLOTDIS6_Pos)) /* Assigment of value for SLOTDIS6 in the I2S_RXCTRL register */ 497 #define I2S_RXCTRL_SLOTDIS7_Pos _UINT32_(23) /* (I2S_RXCTRL) Slot 7 Disabled for this Serializer Position */ 498 #define I2S_RXCTRL_SLOTDIS7_Msk (_UINT32_(0x1) << I2S_RXCTRL_SLOTDIS7_Pos) /* (I2S_RXCTRL) Slot 7 Disabled for this Serializer Mask */ 499 #define I2S_RXCTRL_SLOTDIS7(value) (I2S_RXCTRL_SLOTDIS7_Msk & (_UINT32_(value) << I2S_RXCTRL_SLOTDIS7_Pos)) /* Assigment of value for SLOTDIS7 in the I2S_RXCTRL register */ 500 #define I2S_RXCTRL_MONO_Pos _UINT32_(24) /* (I2S_RXCTRL) Mono Mode Position */ 501 #define I2S_RXCTRL_MONO_Msk (_UINT32_(0x1) << I2S_RXCTRL_MONO_Pos) /* (I2S_RXCTRL) Mono Mode Mask */ 502 #define I2S_RXCTRL_MONO(value) (I2S_RXCTRL_MONO_Msk & (_UINT32_(value) << I2S_RXCTRL_MONO_Pos)) /* Assigment of value for MONO in the I2S_RXCTRL register */ 503 #define I2S_RXCTRL_MONO_STEREO_Val _UINT32_(0x0) /* (I2S_RXCTRL) Normal mode */ 504 #define I2S_RXCTRL_MONO_MONO_Val _UINT32_(0x1) /* (I2S_RXCTRL) Left channel data is duplicated to right channel */ 505 #define I2S_RXCTRL_MONO_STEREO (I2S_RXCTRL_MONO_STEREO_Val << I2S_RXCTRL_MONO_Pos) /* (I2S_RXCTRL) Normal mode Position */ 506 #define I2S_RXCTRL_MONO_MONO (I2S_RXCTRL_MONO_MONO_Val << I2S_RXCTRL_MONO_Pos) /* (I2S_RXCTRL) Left channel data is duplicated to right channel Position */ 507 #define I2S_RXCTRL_DMA_Pos _UINT32_(25) /* (I2S_RXCTRL) Single or Multiple DMA Channels Position */ 508 #define I2S_RXCTRL_DMA_Msk (_UINT32_(0x1) << I2S_RXCTRL_DMA_Pos) /* (I2S_RXCTRL) Single or Multiple DMA Channels Mask */ 509 #define I2S_RXCTRL_DMA(value) (I2S_RXCTRL_DMA_Msk & (_UINT32_(value) << I2S_RXCTRL_DMA_Pos)) /* Assigment of value for DMA in the I2S_RXCTRL register */ 510 #define I2S_RXCTRL_DMA_SINGLE_Val _UINT32_(0x0) /* (I2S_RXCTRL) Single DMA channel */ 511 #define I2S_RXCTRL_DMA_MULTIPLE_Val _UINT32_(0x1) /* (I2S_RXCTRL) One DMA channel per data channel */ 512 #define I2S_RXCTRL_DMA_SINGLE (I2S_RXCTRL_DMA_SINGLE_Val << I2S_RXCTRL_DMA_Pos) /* (I2S_RXCTRL) Single DMA channel Position */ 513 #define I2S_RXCTRL_DMA_MULTIPLE (I2S_RXCTRL_DMA_MULTIPLE_Val << I2S_RXCTRL_DMA_Pos) /* (I2S_RXCTRL) One DMA channel per data channel Position */ 514 #define I2S_RXCTRL_RXLOOP_Pos _UINT32_(26) /* (I2S_RXCTRL) Loop-back Test Mode Position */ 515 #define I2S_RXCTRL_RXLOOP_Msk (_UINT32_(0x1) << I2S_RXCTRL_RXLOOP_Pos) /* (I2S_RXCTRL) Loop-back Test Mode Mask */ 516 #define I2S_RXCTRL_RXLOOP(value) (I2S_RXCTRL_RXLOOP_Msk & (_UINT32_(value) << I2S_RXCTRL_RXLOOP_Pos)) /* Assigment of value for RXLOOP in the I2S_RXCTRL register */ 517 #define I2S_RXCTRL_Msk _UINT32_(0x07FFF7A3) /* (I2S_RXCTRL) Register Mask */ 518 519 #define I2S_RXCTRL_SLOTDIS_Pos _UINT32_(16) /* (I2S_RXCTRL Position) Slot x Disabled for this Serializer */ 520 #define I2S_RXCTRL_SLOTDIS_Msk (_UINT32_(0xFF) << I2S_RXCTRL_SLOTDIS_Pos) /* (I2S_RXCTRL Mask) SLOTDIS */ 521 #define I2S_RXCTRL_SLOTDIS(value) (I2S_RXCTRL_SLOTDIS_Msk & (_UINT32_(value) << I2S_RXCTRL_SLOTDIS_Pos)) 522 523 /* -------- I2S_TXDATA : (I2S Offset: 0x30) ( /W 32) Tx Data -------- */ 524 #define I2S_TXDATA_RESETVALUE _UINT32_(0x00) /* (I2S_TXDATA) Tx Data Reset Value */ 525 526 #define I2S_TXDATA_DATA_Pos _UINT32_(0) /* (I2S_TXDATA) Sample Data Position */ 527 #define I2S_TXDATA_DATA_Msk (_UINT32_(0xFFFFFFFF) << I2S_TXDATA_DATA_Pos) /* (I2S_TXDATA) Sample Data Mask */ 528 #define I2S_TXDATA_DATA(value) (I2S_TXDATA_DATA_Msk & (_UINT32_(value) << I2S_TXDATA_DATA_Pos)) /* Assigment of value for DATA in the I2S_TXDATA register */ 529 #define I2S_TXDATA_Msk _UINT32_(0xFFFFFFFF) /* (I2S_TXDATA) Register Mask */ 530 531 532 /* -------- I2S_RXDATA : (I2S Offset: 0x34) ( R/ 32) Rx Data -------- */ 533 #define I2S_RXDATA_RESETVALUE _UINT32_(0x00) /* (I2S_RXDATA) Rx Data Reset Value */ 534 535 #define I2S_RXDATA_DATA_Pos _UINT32_(0) /* (I2S_RXDATA) Sample Data Position */ 536 #define I2S_RXDATA_DATA_Msk (_UINT32_(0xFFFFFFFF) << I2S_RXDATA_DATA_Pos) /* (I2S_RXDATA) Sample Data Mask */ 537 #define I2S_RXDATA_DATA(value) (I2S_RXDATA_DATA_Msk & (_UINT32_(value) << I2S_RXDATA_DATA_Pos)) /* Assigment of value for DATA in the I2S_RXDATA register */ 538 #define I2S_RXDATA_Msk _UINT32_(0xFFFFFFFF) /* (I2S_RXDATA) Register Mask */ 539 540 541 /** \brief I2S register offsets definitions */ 542 #define I2S_CTRLA_REG_OFST _UINT32_(0x00) /* (I2S_CTRLA) Control A Offset */ 543 #define I2S_CLKCTRL_REG_OFST _UINT32_(0x04) /* (I2S_CLKCTRL) Clock Unit n Control Offset */ 544 #define I2S_CLKCTRL0_REG_OFST _UINT32_(0x04) /* (I2S_CLKCTRL0) Clock Unit n Control Offset */ 545 #define I2S_CLKCTRL1_REG_OFST _UINT32_(0x08) /* (I2S_CLKCTRL1) Clock Unit n Control Offset */ 546 #define I2S_INTENCLR_REG_OFST _UINT32_(0x0C) /* (I2S_INTENCLR) Interrupt Enable Clear Offset */ 547 #define I2S_INTENSET_REG_OFST _UINT32_(0x10) /* (I2S_INTENSET) Interrupt Enable Set Offset */ 548 #define I2S_INTFLAG_REG_OFST _UINT32_(0x14) /* (I2S_INTFLAG) Interrupt Flag Status and Clear Offset */ 549 #define I2S_SYNCBUSY_REG_OFST _UINT32_(0x18) /* (I2S_SYNCBUSY) Synchronization Status Offset */ 550 #define I2S_TXCTRL_REG_OFST _UINT32_(0x20) /* (I2S_TXCTRL) Tx Serializer Control Offset */ 551 #define I2S_RXCTRL_REG_OFST _UINT32_(0x24) /* (I2S_RXCTRL) Rx Serializer Control Offset */ 552 #define I2S_TXDATA_REG_OFST _UINT32_(0x30) /* (I2S_TXDATA) Tx Data Offset */ 553 #define I2S_RXDATA_REG_OFST _UINT32_(0x34) /* (I2S_RXDATA) Rx Data Offset */ 554 555 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 556 /** \brief I2S register API structure */ 557 typedef struct 558 { /* Inter-IC Sound Interface */ 559 __IO uint8_t I2S_CTRLA; /**< Offset: 0x00 (R/W 8) Control A */ 560 __I uint8_t Reserved1[0x03]; 561 __IO uint32_t I2S_CLKCTRL[2]; /**< Offset: 0x04 (R/W 32) Clock Unit n Control */ 562 __IO uint16_t I2S_INTENCLR; /**< Offset: 0x0C (R/W 16) Interrupt Enable Clear */ 563 __I uint8_t Reserved2[0x02]; 564 __IO uint16_t I2S_INTENSET; /**< Offset: 0x10 (R/W 16) Interrupt Enable Set */ 565 __I uint8_t Reserved3[0x02]; 566 __IO uint16_t I2S_INTFLAG; /**< Offset: 0x14 (R/W 16) Interrupt Flag Status and Clear */ 567 __I uint8_t Reserved4[0x02]; 568 __I uint16_t I2S_SYNCBUSY; /**< Offset: 0x18 (R/ 16) Synchronization Status */ 569 __I uint8_t Reserved5[0x06]; 570 __IO uint32_t I2S_TXCTRL; /**< Offset: 0x20 (R/W 32) Tx Serializer Control */ 571 __IO uint32_t I2S_RXCTRL; /**< Offset: 0x24 (R/W 32) Rx Serializer Control */ 572 __I uint8_t Reserved6[0x08]; 573 __O uint32_t I2S_TXDATA; /**< Offset: 0x30 ( /W 32) Tx Data */ 574 __I uint32_t I2S_RXDATA; /**< Offset: 0x34 (R/ 32) Rx Data */ 575 } i2s_registers_t; 576 577 578 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 579 #endif /* _PIC32CXSG61_I2S_COMPONENT_H_ */ 580
