1 /* 2 * Component description for FUSES 3 * 4 * Copyright (c) 2023 Microchip Technology Inc. and its subsidiaries. 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 */ 19 20 /* file generated from device description file (ATDF) version 2023-03-17T09:48:59Z */ 21 #ifndef _PIC32CXSG61_FUSES_COMPONENT_H_ 22 #define _PIC32CXSG61_FUSES_COMPONENT_H_ 23 24 /* ************************************************************************** */ 25 /* SOFTWARE API DEFINITION FOR FUSES */ 26 /* ************************************************************************** */ 27 28 /* -------- FUSES_SW0_WORD_0 : (FUSES Offset: 0x00) ( R/ 32) SW0 Page Word 0 -------- */ 29 #define FUSES_SW0_WORD_0_AC_BIAS0_Pos _UINT32_(0) /* (FUSES_SW0_WORD_0) PAIR0 Bias Calibration Position */ 30 #define FUSES_SW0_WORD_0_AC_BIAS0_Msk (_UINT32_(0x3) << FUSES_SW0_WORD_0_AC_BIAS0_Pos) /* (FUSES_SW0_WORD_0) PAIR0 Bias Calibration Mask */ 31 #define FUSES_SW0_WORD_0_AC_BIAS0(value) (FUSES_SW0_WORD_0_AC_BIAS0_Msk & (_UINT32_(value) << FUSES_SW0_WORD_0_AC_BIAS0_Pos)) /* Assigment of value for AC_BIAS0 in the FUSES_SW0_WORD_0 register */ 32 #define FUSES_SW0_WORD_0_ADC0_BIASCOMP_Pos _UINT32_(2) /* (FUSES_SW0_WORD_0) ADC Comparator Scaling Position */ 33 #define FUSES_SW0_WORD_0_ADC0_BIASCOMP_Msk (_UINT32_(0x7) << FUSES_SW0_WORD_0_ADC0_BIASCOMP_Pos) /* (FUSES_SW0_WORD_0) ADC Comparator Scaling Mask */ 34 #define FUSES_SW0_WORD_0_ADC0_BIASCOMP(value) (FUSES_SW0_WORD_0_ADC0_BIASCOMP_Msk & (_UINT32_(value) << FUSES_SW0_WORD_0_ADC0_BIASCOMP_Pos)) /* Assigment of value for ADC0_BIASCOMP in the FUSES_SW0_WORD_0 register */ 35 #define FUSES_SW0_WORD_0_ADC0_BIASREFBUF_Pos _UINT32_(5) /* (FUSES_SW0_WORD_0) ADC Bias Reference Buffer Scaling Position */ 36 #define FUSES_SW0_WORD_0_ADC0_BIASREFBUF_Msk (_UINT32_(0x7) << FUSES_SW0_WORD_0_ADC0_BIASREFBUF_Pos) /* (FUSES_SW0_WORD_0) ADC Bias Reference Buffer Scaling Mask */ 37 #define FUSES_SW0_WORD_0_ADC0_BIASREFBUF(value) (FUSES_SW0_WORD_0_ADC0_BIASREFBUF_Msk & (_UINT32_(value) << FUSES_SW0_WORD_0_ADC0_BIASREFBUF_Pos)) /* Assigment of value for ADC0_BIASREFBUF in the FUSES_SW0_WORD_0 register */ 38 #define FUSES_SW0_WORD_0_ADC0_BIASR2R_Pos _UINT32_(8) /* (FUSES_SW0_WORD_0) ADC Bias R2R ampli scaling Position */ 39 #define FUSES_SW0_WORD_0_ADC0_BIASR2R_Msk (_UINT32_(0x7) << FUSES_SW0_WORD_0_ADC0_BIASR2R_Pos) /* (FUSES_SW0_WORD_0) ADC Bias R2R ampli scaling Mask */ 40 #define FUSES_SW0_WORD_0_ADC0_BIASR2R(value) (FUSES_SW0_WORD_0_ADC0_BIASR2R_Msk & (_UINT32_(value) << FUSES_SW0_WORD_0_ADC0_BIASR2R_Pos)) /* Assigment of value for ADC0_BIASR2R in the FUSES_SW0_WORD_0 register */ 41 #define FUSES_SW0_WORD_0_ADC1_BIASCOMP_Pos _UINT32_(16) /* (FUSES_SW0_WORD_0) ADC Comparator Scaling Position */ 42 #define FUSES_SW0_WORD_0_ADC1_BIASCOMP_Msk (_UINT32_(0x7) << FUSES_SW0_WORD_0_ADC1_BIASCOMP_Pos) /* (FUSES_SW0_WORD_0) ADC Comparator Scaling Mask */ 43 #define FUSES_SW0_WORD_0_ADC1_BIASCOMP(value) (FUSES_SW0_WORD_0_ADC1_BIASCOMP_Msk & (_UINT32_(value) << FUSES_SW0_WORD_0_ADC1_BIASCOMP_Pos)) /* Assigment of value for ADC1_BIASCOMP in the FUSES_SW0_WORD_0 register */ 44 #define FUSES_SW0_WORD_0_ADC1_BIASREFBUF_Pos _UINT32_(19) /* (FUSES_SW0_WORD_0) ADC Bias Reference Buffer Scaling Position */ 45 #define FUSES_SW0_WORD_0_ADC1_BIASREFBUF_Msk (_UINT32_(0x7) << FUSES_SW0_WORD_0_ADC1_BIASREFBUF_Pos) /* (FUSES_SW0_WORD_0) ADC Bias Reference Buffer Scaling Mask */ 46 #define FUSES_SW0_WORD_0_ADC1_BIASREFBUF(value) (FUSES_SW0_WORD_0_ADC1_BIASREFBUF_Msk & (_UINT32_(value) << FUSES_SW0_WORD_0_ADC1_BIASREFBUF_Pos)) /* Assigment of value for ADC1_BIASREFBUF in the FUSES_SW0_WORD_0 register */ 47 #define FUSES_SW0_WORD_0_ADC1_BIASR2R_Pos _UINT32_(22) /* (FUSES_SW0_WORD_0) ADC Bias R2R ampli scaling Position */ 48 #define FUSES_SW0_WORD_0_ADC1_BIASR2R_Msk (_UINT32_(0x7) << FUSES_SW0_WORD_0_ADC1_BIASR2R_Pos) /* (FUSES_SW0_WORD_0) ADC Bias R2R ampli scaling Mask */ 49 #define FUSES_SW0_WORD_0_ADC1_BIASR2R(value) (FUSES_SW0_WORD_0_ADC1_BIASR2R_Msk & (_UINT32_(value) << FUSES_SW0_WORD_0_ADC1_BIASR2R_Pos)) /* Assigment of value for ADC1_BIASR2R in the FUSES_SW0_WORD_0 register */ 50 #define FUSES_SW0_WORD_0_Msk _UINT32_(0x01FF07FF) /* (FUSES_SW0_WORD_0) Register Mask */ 51 52 53 /* -------- FUSES_SW0_WORD_1 : (FUSES Offset: 0x04) ( R/ 32) SW0 Page Word 1 -------- */ 54 #define FUSES_SW0_WORD_1_USB_TRANSN_Pos _UINT32_(0) /* (FUSES_SW0_WORD_1) USB pad Transn calibration Position */ 55 #define FUSES_SW0_WORD_1_USB_TRANSN_Msk (_UINT32_(0x1F) << FUSES_SW0_WORD_1_USB_TRANSN_Pos) /* (FUSES_SW0_WORD_1) USB pad Transn calibration Mask */ 56 #define FUSES_SW0_WORD_1_USB_TRANSN(value) (FUSES_SW0_WORD_1_USB_TRANSN_Msk & (_UINT32_(value) << FUSES_SW0_WORD_1_USB_TRANSN_Pos)) /* Assigment of value for USB_TRANSN in the FUSES_SW0_WORD_1 register */ 57 #define FUSES_SW0_WORD_1_USB_TRANSP_Pos _UINT32_(5) /* (FUSES_SW0_WORD_1) USB pad Transp calibration Position */ 58 #define FUSES_SW0_WORD_1_USB_TRANSP_Msk (_UINT32_(0x1F) << FUSES_SW0_WORD_1_USB_TRANSP_Pos) /* (FUSES_SW0_WORD_1) USB pad Transp calibration Mask */ 59 #define FUSES_SW0_WORD_1_USB_TRANSP(value) (FUSES_SW0_WORD_1_USB_TRANSP_Msk & (_UINT32_(value) << FUSES_SW0_WORD_1_USB_TRANSP_Pos)) /* Assigment of value for USB_TRANSP in the FUSES_SW0_WORD_1 register */ 60 #define FUSES_SW0_WORD_1_USB_TRIM_Pos _UINT32_(10) /* (FUSES_SW0_WORD_1) USB pad Trim calibration Position */ 61 #define FUSES_SW0_WORD_1_USB_TRIM_Msk (_UINT32_(0x7) << FUSES_SW0_WORD_1_USB_TRIM_Pos) /* (FUSES_SW0_WORD_1) USB pad Trim calibration Mask */ 62 #define FUSES_SW0_WORD_1_USB_TRIM(value) (FUSES_SW0_WORD_1_USB_TRIM_Msk & (_UINT32_(value) << FUSES_SW0_WORD_1_USB_TRIM_Pos)) /* Assigment of value for USB_TRIM in the FUSES_SW0_WORD_1 register */ 63 #define FUSES_SW0_WORD_1_Msk _UINT32_(0x00001FFF) /* (FUSES_SW0_WORD_1) Register Mask */ 64 65 66 /* -------- FUSES_USER_WORD_0 : (FUSES Offset: 0x00) (R/W 32) USER Page Word 0 -------- */ 67 #define FUSES_USER_WORD_0_BOD33_DIS_Pos _UINT32_(0) /* (FUSES_USER_WORD_0) BOD33 Disable Position */ 68 #define FUSES_USER_WORD_0_BOD33_DIS_Msk (_UINT32_(0x1) << FUSES_USER_WORD_0_BOD33_DIS_Pos) /* (FUSES_USER_WORD_0) BOD33 Disable Mask */ 69 #define FUSES_USER_WORD_0_BOD33_DIS(value) (FUSES_USER_WORD_0_BOD33_DIS_Msk & (_UINT32_(value) << FUSES_USER_WORD_0_BOD33_DIS_Pos)) /* Assigment of value for BOD33_DIS in the FUSES_USER_WORD_0 register */ 70 #define FUSES_USER_WORD_0_BOD33USERLEVEL_Pos _UINT32_(1) /* (FUSES_USER_WORD_0) BOD33 User Level Position */ 71 #define FUSES_USER_WORD_0_BOD33USERLEVEL_Msk (_UINT32_(0xFF) << FUSES_USER_WORD_0_BOD33USERLEVEL_Pos) /* (FUSES_USER_WORD_0) BOD33 User Level Mask */ 72 #define FUSES_USER_WORD_0_BOD33USERLEVEL(value) (FUSES_USER_WORD_0_BOD33USERLEVEL_Msk & (_UINT32_(value) << FUSES_USER_WORD_0_BOD33USERLEVEL_Pos)) /* Assigment of value for BOD33USERLEVEL in the FUSES_USER_WORD_0 register */ 73 #define FUSES_USER_WORD_0_BOD33_ACTION_Pos _UINT32_(9) /* (FUSES_USER_WORD_0) BOD33 Action Position */ 74 #define FUSES_USER_WORD_0_BOD33_ACTION_Msk (_UINT32_(0x3) << FUSES_USER_WORD_0_BOD33_ACTION_Pos) /* (FUSES_USER_WORD_0) BOD33 Action Mask */ 75 #define FUSES_USER_WORD_0_BOD33_ACTION(value) (FUSES_USER_WORD_0_BOD33_ACTION_Msk & (_UINT32_(value) << FUSES_USER_WORD_0_BOD33_ACTION_Pos)) /* Assigment of value for BOD33_ACTION in the FUSES_USER_WORD_0 register */ 76 #define FUSES_USER_WORD_0_BOD33_ACTION_NONE_Val _UINT32_(0x0) /* (FUSES_USER_WORD_0) No action */ 77 #define FUSES_USER_WORD_0_BOD33_ACTION_RESET_Val _UINT32_(0x1) /* (FUSES_USER_WORD_0) The BOD33 generates a reset */ 78 #define FUSES_USER_WORD_0_BOD33_ACTION_INT_Val _UINT32_(0x2) /* (FUSES_USER_WORD_0) The BOD33 generates an interrupt */ 79 #define FUSES_USER_WORD_0_BOD33_ACTION_BKUP_Val _UINT32_(0x3) /* (FUSES_USER_WORD_0) The BOD33 puts the device in backup sleep mode */ 80 #define FUSES_USER_WORD_0_BOD33_ACTION_NONE (FUSES_USER_WORD_0_BOD33_ACTION_NONE_Val << FUSES_USER_WORD_0_BOD33_ACTION_Pos) /* (FUSES_USER_WORD_0) No action Position */ 81 #define FUSES_USER_WORD_0_BOD33_ACTION_RESET (FUSES_USER_WORD_0_BOD33_ACTION_RESET_Val << FUSES_USER_WORD_0_BOD33_ACTION_Pos) /* (FUSES_USER_WORD_0) The BOD33 generates a reset Position */ 82 #define FUSES_USER_WORD_0_BOD33_ACTION_INT (FUSES_USER_WORD_0_BOD33_ACTION_INT_Val << FUSES_USER_WORD_0_BOD33_ACTION_Pos) /* (FUSES_USER_WORD_0) The BOD33 generates an interrupt Position */ 83 #define FUSES_USER_WORD_0_BOD33_ACTION_BKUP (FUSES_USER_WORD_0_BOD33_ACTION_BKUP_Val << FUSES_USER_WORD_0_BOD33_ACTION_Pos) /* (FUSES_USER_WORD_0) The BOD33 puts the device in backup sleep mode Position */ 84 #define FUSES_USER_WORD_0_BOD33_HYST_Pos _UINT32_(11) /* (FUSES_USER_WORD_0) BOD33 Hysteresis Position */ 85 #define FUSES_USER_WORD_0_BOD33_HYST_Msk (_UINT32_(0xF) << FUSES_USER_WORD_0_BOD33_HYST_Pos) /* (FUSES_USER_WORD_0) BOD33 Hysteresis Mask */ 86 #define FUSES_USER_WORD_0_BOD33_HYST(value) (FUSES_USER_WORD_0_BOD33_HYST_Msk & (_UINT32_(value) << FUSES_USER_WORD_0_BOD33_HYST_Pos)) /* Assigment of value for BOD33_HYST in the FUSES_USER_WORD_0 register */ 87 #define FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_Pos _UINT32_(26) /* (FUSES_USER_WORD_0) Bootloader Size Position */ 88 #define FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_Msk (_UINT32_(0xF) << FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_Pos) /* (FUSES_USER_WORD_0) Bootloader Size Mask */ 89 #define FUSES_USER_WORD_0_NVMCTRL_BOOTPROT(value) (FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_Msk & (_UINT32_(value) << FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_Pos)) /* Assigment of value for NVMCTRL_BOOTPROT in the FUSES_USER_WORD_0 register */ 90 #define FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_0_Val _UINT32_(0xF) /* (FUSES_USER_WORD_0) 0 kbytes */ 91 #define FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_8_Val _UINT32_(0xE) /* (FUSES_USER_WORD_0) 8 kbytes */ 92 #define FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_16_Val _UINT32_(0xD) /* (FUSES_USER_WORD_0) 16 kbytes */ 93 #define FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_24_Val _UINT32_(0xC) /* (FUSES_USER_WORD_0) 24 kbytes */ 94 #define FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_32_Val _UINT32_(0xB) /* (FUSES_USER_WORD_0) 32 kbytes */ 95 #define FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_40_Val _UINT32_(0xA) /* (FUSES_USER_WORD_0) 40 kbytes */ 96 #define FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_48_Val _UINT32_(0x9) /* (FUSES_USER_WORD_0) 48 kbytes */ 97 #define FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_56_Val _UINT32_(0x8) /* (FUSES_USER_WORD_0) 56 kbytes */ 98 #define FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_64_Val _UINT32_(0x7) /* (FUSES_USER_WORD_0) 64 kbytes */ 99 #define FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_72_Val _UINT32_(0x6) /* (FUSES_USER_WORD_0) 72 kbytes */ 100 #define FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_80_Val _UINT32_(0x5) /* (FUSES_USER_WORD_0) 80 kbytes */ 101 #define FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_88_Val _UINT32_(0x4) /* (FUSES_USER_WORD_0) 88 kbytes */ 102 #define FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_96_Val _UINT32_(0x3) /* (FUSES_USER_WORD_0) 96 kbytes */ 103 #define FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_104_Val _UINT32_(0x2) /* (FUSES_USER_WORD_0) 104 kbytes */ 104 #define FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_112_Val _UINT32_(0x1) /* (FUSES_USER_WORD_0) 112 kbytes */ 105 #define FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_120_Val _UINT32_(0x0) /* (FUSES_USER_WORD_0) 120 kbytes */ 106 #define FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_0 (FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_0_Val << FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_Pos) /* (FUSES_USER_WORD_0) 0 kbytes Position */ 107 #define FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_8 (FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_8_Val << FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_Pos) /* (FUSES_USER_WORD_0) 8 kbytes Position */ 108 #define FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_16 (FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_16_Val << FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_Pos) /* (FUSES_USER_WORD_0) 16 kbytes Position */ 109 #define FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_24 (FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_24_Val << FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_Pos) /* (FUSES_USER_WORD_0) 24 kbytes Position */ 110 #define FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_32 (FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_32_Val << FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_Pos) /* (FUSES_USER_WORD_0) 32 kbytes Position */ 111 #define FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_40 (FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_40_Val << FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_Pos) /* (FUSES_USER_WORD_0) 40 kbytes Position */ 112 #define FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_48 (FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_48_Val << FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_Pos) /* (FUSES_USER_WORD_0) 48 kbytes Position */ 113 #define FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_56 (FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_56_Val << FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_Pos) /* (FUSES_USER_WORD_0) 56 kbytes Position */ 114 #define FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_64 (FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_64_Val << FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_Pos) /* (FUSES_USER_WORD_0) 64 kbytes Position */ 115 #define FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_72 (FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_72_Val << FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_Pos) /* (FUSES_USER_WORD_0) 72 kbytes Position */ 116 #define FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_80 (FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_80_Val << FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_Pos) /* (FUSES_USER_WORD_0) 80 kbytes Position */ 117 #define FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_88 (FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_88_Val << FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_Pos) /* (FUSES_USER_WORD_0) 88 kbytes Position */ 118 #define FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_96 (FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_96_Val << FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_Pos) /* (FUSES_USER_WORD_0) 96 kbytes Position */ 119 #define FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_104 (FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_104_Val << FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_Pos) /* (FUSES_USER_WORD_0) 104 kbytes Position */ 120 #define FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_112 (FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_112_Val << FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_Pos) /* (FUSES_USER_WORD_0) 112 kbytes Position */ 121 #define FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_120 (FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_120_Val << FUSES_USER_WORD_0_NVMCTRL_BOOTPROT_Pos) /* (FUSES_USER_WORD_0) 120 kbytes Position */ 122 #define FUSES_USER_WORD_0_Msk _UINT32_(0x3C007FFF) /* (FUSES_USER_WORD_0) Register Mask */ 123 124 125 /* -------- FUSES_USER_WORD_1 : (FUSES Offset: 0x04) (R/W 32) USER Page Word 1 -------- */ 126 #define FUSES_USER_WORD_1_NVMCTRL_SEESBLK_Pos _UINT32_(0) /* (FUSES_USER_WORD_1) Number Of Physical NVM Blocks Composing a SmartEEPROM Sector Position */ 127 #define FUSES_USER_WORD_1_NVMCTRL_SEESBLK_Msk (_UINT32_(0xF) << FUSES_USER_WORD_1_NVMCTRL_SEESBLK_Pos) /* (FUSES_USER_WORD_1) Number Of Physical NVM Blocks Composing a SmartEEPROM Sector Mask */ 128 #define FUSES_USER_WORD_1_NVMCTRL_SEESBLK(value) (FUSES_USER_WORD_1_NVMCTRL_SEESBLK_Msk & (_UINT32_(value) << FUSES_USER_WORD_1_NVMCTRL_SEESBLK_Pos)) /* Assigment of value for NVMCTRL_SEESBLK in the FUSES_USER_WORD_1 register */ 129 #define FUSES_USER_WORD_1_NVMCTRL_SEEPSZ_Pos _UINT32_(4) /* (FUSES_USER_WORD_1) Size Of SmartEEPROM Page Position */ 130 #define FUSES_USER_WORD_1_NVMCTRL_SEEPSZ_Msk (_UINT32_(0x7) << FUSES_USER_WORD_1_NVMCTRL_SEEPSZ_Pos) /* (FUSES_USER_WORD_1) Size Of SmartEEPROM Page Mask */ 131 #define FUSES_USER_WORD_1_NVMCTRL_SEEPSZ(value) (FUSES_USER_WORD_1_NVMCTRL_SEEPSZ_Msk & (_UINT32_(value) << FUSES_USER_WORD_1_NVMCTRL_SEEPSZ_Pos)) /* Assigment of value for NVMCTRL_SEEPSZ in the FUSES_USER_WORD_1 register */ 132 #define FUSES_USER_WORD_1_RAMECC_ECCDIS_Pos _UINT32_(7) /* (FUSES_USER_WORD_1) RAM ECC Disable fuse Position */ 133 #define FUSES_USER_WORD_1_RAMECC_ECCDIS_Msk (_UINT32_(0x1) << FUSES_USER_WORD_1_RAMECC_ECCDIS_Pos) /* (FUSES_USER_WORD_1) RAM ECC Disable fuse Mask */ 134 #define FUSES_USER_WORD_1_RAMECC_ECCDIS(value) (FUSES_USER_WORD_1_RAMECC_ECCDIS_Msk & (_UINT32_(value) << FUSES_USER_WORD_1_RAMECC_ECCDIS_Pos)) /* Assigment of value for RAMECC_ECCDIS in the FUSES_USER_WORD_1 register */ 135 #define FUSES_USER_WORD_1_WDT_ENABLE_Pos _UINT32_(16) /* (FUSES_USER_WORD_1) WDT Enable Position */ 136 #define FUSES_USER_WORD_1_WDT_ENABLE_Msk (_UINT32_(0x1) << FUSES_USER_WORD_1_WDT_ENABLE_Pos) /* (FUSES_USER_WORD_1) WDT Enable Mask */ 137 #define FUSES_USER_WORD_1_WDT_ENABLE(value) (FUSES_USER_WORD_1_WDT_ENABLE_Msk & (_UINT32_(value) << FUSES_USER_WORD_1_WDT_ENABLE_Pos)) /* Assigment of value for WDT_ENABLE in the FUSES_USER_WORD_1 register */ 138 #define FUSES_USER_WORD_1_WDT_ALWAYSON_Pos _UINT32_(17) /* (FUSES_USER_WORD_1) WDT Always On Position */ 139 #define FUSES_USER_WORD_1_WDT_ALWAYSON_Msk (_UINT32_(0x1) << FUSES_USER_WORD_1_WDT_ALWAYSON_Pos) /* (FUSES_USER_WORD_1) WDT Always On Mask */ 140 #define FUSES_USER_WORD_1_WDT_ALWAYSON(value) (FUSES_USER_WORD_1_WDT_ALWAYSON_Msk & (_UINT32_(value) << FUSES_USER_WORD_1_WDT_ALWAYSON_Pos)) /* Assigment of value for WDT_ALWAYSON in the FUSES_USER_WORD_1 register */ 141 #define FUSES_USER_WORD_1_WDT_PER_Pos _UINT32_(18) /* (FUSES_USER_WORD_1) WDT Period Position */ 142 #define FUSES_USER_WORD_1_WDT_PER_Msk (_UINT32_(0xF) << FUSES_USER_WORD_1_WDT_PER_Pos) /* (FUSES_USER_WORD_1) WDT Period Mask */ 143 #define FUSES_USER_WORD_1_WDT_PER(value) (FUSES_USER_WORD_1_WDT_PER_Msk & (_UINT32_(value) << FUSES_USER_WORD_1_WDT_PER_Pos)) /* Assigment of value for WDT_PER in the FUSES_USER_WORD_1 register */ 144 #define FUSES_USER_WORD_1_WDT_PER_CYC8_Val _UINT32_(0x0) /* (FUSES_USER_WORD_1) 8 clock cycles */ 145 #define FUSES_USER_WORD_1_WDT_PER_CYC16_Val _UINT32_(0x1) /* (FUSES_USER_WORD_1) 16 clock cycles */ 146 #define FUSES_USER_WORD_1_WDT_PER_CYC32_Val _UINT32_(0x2) /* (FUSES_USER_WORD_1) 32 clock cycles */ 147 #define FUSES_USER_WORD_1_WDT_PER_CYC64_Val _UINT32_(0x3) /* (FUSES_USER_WORD_1) 64 clock cycles */ 148 #define FUSES_USER_WORD_1_WDT_PER_CYC128_Val _UINT32_(0x4) /* (FUSES_USER_WORD_1) 128 clock cycles */ 149 #define FUSES_USER_WORD_1_WDT_PER_CYC256_Val _UINT32_(0x5) /* (FUSES_USER_WORD_1) 256 clock cycles */ 150 #define FUSES_USER_WORD_1_WDT_PER_CYC512_Val _UINT32_(0x6) /* (FUSES_USER_WORD_1) 512 clock cycles */ 151 #define FUSES_USER_WORD_1_WDT_PER_CYC1024_Val _UINT32_(0x7) /* (FUSES_USER_WORD_1) 1024 clock cycles */ 152 #define FUSES_USER_WORD_1_WDT_PER_CYC2048_Val _UINT32_(0x8) /* (FUSES_USER_WORD_1) 2048 clock cycles */ 153 #define FUSES_USER_WORD_1_WDT_PER_CYC4096_Val _UINT32_(0x9) /* (FUSES_USER_WORD_1) 4096 clock cycles */ 154 #define FUSES_USER_WORD_1_WDT_PER_CYC8192_Val _UINT32_(0xA) /* (FUSES_USER_WORD_1) 8192 clock cycles */ 155 #define FUSES_USER_WORD_1_WDT_PER_CYC16384_Val _UINT32_(0xB) /* (FUSES_USER_WORD_1) 16384 clock cycles */ 156 #define FUSES_USER_WORD_1_WDT_PER_CYC8 (FUSES_USER_WORD_1_WDT_PER_CYC8_Val << FUSES_USER_WORD_1_WDT_PER_Pos) /* (FUSES_USER_WORD_1) 8 clock cycles Position */ 157 #define FUSES_USER_WORD_1_WDT_PER_CYC16 (FUSES_USER_WORD_1_WDT_PER_CYC16_Val << FUSES_USER_WORD_1_WDT_PER_Pos) /* (FUSES_USER_WORD_1) 16 clock cycles Position */ 158 #define FUSES_USER_WORD_1_WDT_PER_CYC32 (FUSES_USER_WORD_1_WDT_PER_CYC32_Val << FUSES_USER_WORD_1_WDT_PER_Pos) /* (FUSES_USER_WORD_1) 32 clock cycles Position */ 159 #define FUSES_USER_WORD_1_WDT_PER_CYC64 (FUSES_USER_WORD_1_WDT_PER_CYC64_Val << FUSES_USER_WORD_1_WDT_PER_Pos) /* (FUSES_USER_WORD_1) 64 clock cycles Position */ 160 #define FUSES_USER_WORD_1_WDT_PER_CYC128 (FUSES_USER_WORD_1_WDT_PER_CYC128_Val << FUSES_USER_WORD_1_WDT_PER_Pos) /* (FUSES_USER_WORD_1) 128 clock cycles Position */ 161 #define FUSES_USER_WORD_1_WDT_PER_CYC256 (FUSES_USER_WORD_1_WDT_PER_CYC256_Val << FUSES_USER_WORD_1_WDT_PER_Pos) /* (FUSES_USER_WORD_1) 256 clock cycles Position */ 162 #define FUSES_USER_WORD_1_WDT_PER_CYC512 (FUSES_USER_WORD_1_WDT_PER_CYC512_Val << FUSES_USER_WORD_1_WDT_PER_Pos) /* (FUSES_USER_WORD_1) 512 clock cycles Position */ 163 #define FUSES_USER_WORD_1_WDT_PER_CYC1024 (FUSES_USER_WORD_1_WDT_PER_CYC1024_Val << FUSES_USER_WORD_1_WDT_PER_Pos) /* (FUSES_USER_WORD_1) 1024 clock cycles Position */ 164 #define FUSES_USER_WORD_1_WDT_PER_CYC2048 (FUSES_USER_WORD_1_WDT_PER_CYC2048_Val << FUSES_USER_WORD_1_WDT_PER_Pos) /* (FUSES_USER_WORD_1) 2048 clock cycles Position */ 165 #define FUSES_USER_WORD_1_WDT_PER_CYC4096 (FUSES_USER_WORD_1_WDT_PER_CYC4096_Val << FUSES_USER_WORD_1_WDT_PER_Pos) /* (FUSES_USER_WORD_1) 4096 clock cycles Position */ 166 #define FUSES_USER_WORD_1_WDT_PER_CYC8192 (FUSES_USER_WORD_1_WDT_PER_CYC8192_Val << FUSES_USER_WORD_1_WDT_PER_Pos) /* (FUSES_USER_WORD_1) 8192 clock cycles Position */ 167 #define FUSES_USER_WORD_1_WDT_PER_CYC16384 (FUSES_USER_WORD_1_WDT_PER_CYC16384_Val << FUSES_USER_WORD_1_WDT_PER_Pos) /* (FUSES_USER_WORD_1) 16384 clock cycles Position */ 168 #define FUSES_USER_WORD_1_WDT_WINDOW_Pos _UINT32_(22) /* (FUSES_USER_WORD_1) WDT Window Position */ 169 #define FUSES_USER_WORD_1_WDT_WINDOW_Msk (_UINT32_(0xF) << FUSES_USER_WORD_1_WDT_WINDOW_Pos) /* (FUSES_USER_WORD_1) WDT Window Mask */ 170 #define FUSES_USER_WORD_1_WDT_WINDOW(value) (FUSES_USER_WORD_1_WDT_WINDOW_Msk & (_UINT32_(value) << FUSES_USER_WORD_1_WDT_WINDOW_Pos)) /* Assigment of value for WDT_WINDOW in the FUSES_USER_WORD_1 register */ 171 #define FUSES_USER_WORD_1_WDT_WINDOW_CYC8_Val _UINT32_(0x0) /* (FUSES_USER_WORD_1) 8 clock cycles */ 172 #define FUSES_USER_WORD_1_WDT_WINDOW_CYC16_Val _UINT32_(0x1) /* (FUSES_USER_WORD_1) 16 clock cycles */ 173 #define FUSES_USER_WORD_1_WDT_WINDOW_CYC32_Val _UINT32_(0x2) /* (FUSES_USER_WORD_1) 32 clock cycles */ 174 #define FUSES_USER_WORD_1_WDT_WINDOW_CYC64_Val _UINT32_(0x3) /* (FUSES_USER_WORD_1) 64 clock cycles */ 175 #define FUSES_USER_WORD_1_WDT_WINDOW_CYC128_Val _UINT32_(0x4) /* (FUSES_USER_WORD_1) 128 clock cycles */ 176 #define FUSES_USER_WORD_1_WDT_WINDOW_CYC256_Val _UINT32_(0x5) /* (FUSES_USER_WORD_1) 256 clock cycles */ 177 #define FUSES_USER_WORD_1_WDT_WINDOW_CYC512_Val _UINT32_(0x6) /* (FUSES_USER_WORD_1) 512 clock cycles */ 178 #define FUSES_USER_WORD_1_WDT_WINDOW_CYC1024_Val _UINT32_(0x7) /* (FUSES_USER_WORD_1) 1024 clock cycles */ 179 #define FUSES_USER_WORD_1_WDT_WINDOW_CYC2048_Val _UINT32_(0x8) /* (FUSES_USER_WORD_1) 2048 clock cycles */ 180 #define FUSES_USER_WORD_1_WDT_WINDOW_CYC4096_Val _UINT32_(0x9) /* (FUSES_USER_WORD_1) 4096 clock cycles */ 181 #define FUSES_USER_WORD_1_WDT_WINDOW_CYC8192_Val _UINT32_(0xA) /* (FUSES_USER_WORD_1) 8192 clock cycles */ 182 #define FUSES_USER_WORD_1_WDT_WINDOW_CYC16384_Val _UINT32_(0xB) /* (FUSES_USER_WORD_1) 16384 clock cycles */ 183 #define FUSES_USER_WORD_1_WDT_WINDOW_CYC8 (FUSES_USER_WORD_1_WDT_WINDOW_CYC8_Val << FUSES_USER_WORD_1_WDT_WINDOW_Pos) /* (FUSES_USER_WORD_1) 8 clock cycles Position */ 184 #define FUSES_USER_WORD_1_WDT_WINDOW_CYC16 (FUSES_USER_WORD_1_WDT_WINDOW_CYC16_Val << FUSES_USER_WORD_1_WDT_WINDOW_Pos) /* (FUSES_USER_WORD_1) 16 clock cycles Position */ 185 #define FUSES_USER_WORD_1_WDT_WINDOW_CYC32 (FUSES_USER_WORD_1_WDT_WINDOW_CYC32_Val << FUSES_USER_WORD_1_WDT_WINDOW_Pos) /* (FUSES_USER_WORD_1) 32 clock cycles Position */ 186 #define FUSES_USER_WORD_1_WDT_WINDOW_CYC64 (FUSES_USER_WORD_1_WDT_WINDOW_CYC64_Val << FUSES_USER_WORD_1_WDT_WINDOW_Pos) /* (FUSES_USER_WORD_1) 64 clock cycles Position */ 187 #define FUSES_USER_WORD_1_WDT_WINDOW_CYC128 (FUSES_USER_WORD_1_WDT_WINDOW_CYC128_Val << FUSES_USER_WORD_1_WDT_WINDOW_Pos) /* (FUSES_USER_WORD_1) 128 clock cycles Position */ 188 #define FUSES_USER_WORD_1_WDT_WINDOW_CYC256 (FUSES_USER_WORD_1_WDT_WINDOW_CYC256_Val << FUSES_USER_WORD_1_WDT_WINDOW_Pos) /* (FUSES_USER_WORD_1) 256 clock cycles Position */ 189 #define FUSES_USER_WORD_1_WDT_WINDOW_CYC512 (FUSES_USER_WORD_1_WDT_WINDOW_CYC512_Val << FUSES_USER_WORD_1_WDT_WINDOW_Pos) /* (FUSES_USER_WORD_1) 512 clock cycles Position */ 190 #define FUSES_USER_WORD_1_WDT_WINDOW_CYC1024 (FUSES_USER_WORD_1_WDT_WINDOW_CYC1024_Val << FUSES_USER_WORD_1_WDT_WINDOW_Pos) /* (FUSES_USER_WORD_1) 1024 clock cycles Position */ 191 #define FUSES_USER_WORD_1_WDT_WINDOW_CYC2048 (FUSES_USER_WORD_1_WDT_WINDOW_CYC2048_Val << FUSES_USER_WORD_1_WDT_WINDOW_Pos) /* (FUSES_USER_WORD_1) 2048 clock cycles Position */ 192 #define FUSES_USER_WORD_1_WDT_WINDOW_CYC4096 (FUSES_USER_WORD_1_WDT_WINDOW_CYC4096_Val << FUSES_USER_WORD_1_WDT_WINDOW_Pos) /* (FUSES_USER_WORD_1) 4096 clock cycles Position */ 193 #define FUSES_USER_WORD_1_WDT_WINDOW_CYC8192 (FUSES_USER_WORD_1_WDT_WINDOW_CYC8192_Val << FUSES_USER_WORD_1_WDT_WINDOW_Pos) /* (FUSES_USER_WORD_1) 8192 clock cycles Position */ 194 #define FUSES_USER_WORD_1_WDT_WINDOW_CYC16384 (FUSES_USER_WORD_1_WDT_WINDOW_CYC16384_Val << FUSES_USER_WORD_1_WDT_WINDOW_Pos) /* (FUSES_USER_WORD_1) 16384 clock cycles Position */ 195 #define FUSES_USER_WORD_1_WDT_EWOFFSET_Pos _UINT32_(26) /* (FUSES_USER_WORD_1) WDT Early Warning Offset Position */ 196 #define FUSES_USER_WORD_1_WDT_EWOFFSET_Msk (_UINT32_(0xF) << FUSES_USER_WORD_1_WDT_EWOFFSET_Pos) /* (FUSES_USER_WORD_1) WDT Early Warning Offset Mask */ 197 #define FUSES_USER_WORD_1_WDT_EWOFFSET(value) (FUSES_USER_WORD_1_WDT_EWOFFSET_Msk & (_UINT32_(value) << FUSES_USER_WORD_1_WDT_EWOFFSET_Pos)) /* Assigment of value for WDT_EWOFFSET in the FUSES_USER_WORD_1 register */ 198 #define FUSES_USER_WORD_1_WDT_EWOFFSET_CYC8_Val _UINT32_(0x0) /* (FUSES_USER_WORD_1) 8 clock cycles */ 199 #define FUSES_USER_WORD_1_WDT_EWOFFSET_CYC16_Val _UINT32_(0x1) /* (FUSES_USER_WORD_1) 16 clock cycles */ 200 #define FUSES_USER_WORD_1_WDT_EWOFFSET_CYC32_Val _UINT32_(0x2) /* (FUSES_USER_WORD_1) 32 clock cycles */ 201 #define FUSES_USER_WORD_1_WDT_EWOFFSET_CYC64_Val _UINT32_(0x3) /* (FUSES_USER_WORD_1) 64 clock cycles */ 202 #define FUSES_USER_WORD_1_WDT_EWOFFSET_CYC128_Val _UINT32_(0x4) /* (FUSES_USER_WORD_1) 128 clock cycles */ 203 #define FUSES_USER_WORD_1_WDT_EWOFFSET_CYC256_Val _UINT32_(0x5) /* (FUSES_USER_WORD_1) 256 clock cycles */ 204 #define FUSES_USER_WORD_1_WDT_EWOFFSET_CYC512_Val _UINT32_(0x6) /* (FUSES_USER_WORD_1) 512 clock cycles */ 205 #define FUSES_USER_WORD_1_WDT_EWOFFSET_CYC1024_Val _UINT32_(0x7) /* (FUSES_USER_WORD_1) 1024 clock cycles */ 206 #define FUSES_USER_WORD_1_WDT_EWOFFSET_CYC2048_Val _UINT32_(0x8) /* (FUSES_USER_WORD_1) 2048 clock cycles */ 207 #define FUSES_USER_WORD_1_WDT_EWOFFSET_CYC4096_Val _UINT32_(0x9) /* (FUSES_USER_WORD_1) 4096 clock cycles */ 208 #define FUSES_USER_WORD_1_WDT_EWOFFSET_CYC8192_Val _UINT32_(0xA) /* (FUSES_USER_WORD_1) 8192 clock cycles */ 209 #define FUSES_USER_WORD_1_WDT_EWOFFSET_CYC8 (FUSES_USER_WORD_1_WDT_EWOFFSET_CYC8_Val << FUSES_USER_WORD_1_WDT_EWOFFSET_Pos) /* (FUSES_USER_WORD_1) 8 clock cycles Position */ 210 #define FUSES_USER_WORD_1_WDT_EWOFFSET_CYC16 (FUSES_USER_WORD_1_WDT_EWOFFSET_CYC16_Val << FUSES_USER_WORD_1_WDT_EWOFFSET_Pos) /* (FUSES_USER_WORD_1) 16 clock cycles Position */ 211 #define FUSES_USER_WORD_1_WDT_EWOFFSET_CYC32 (FUSES_USER_WORD_1_WDT_EWOFFSET_CYC32_Val << FUSES_USER_WORD_1_WDT_EWOFFSET_Pos) /* (FUSES_USER_WORD_1) 32 clock cycles Position */ 212 #define FUSES_USER_WORD_1_WDT_EWOFFSET_CYC64 (FUSES_USER_WORD_1_WDT_EWOFFSET_CYC64_Val << FUSES_USER_WORD_1_WDT_EWOFFSET_Pos) /* (FUSES_USER_WORD_1) 64 clock cycles Position */ 213 #define FUSES_USER_WORD_1_WDT_EWOFFSET_CYC128 (FUSES_USER_WORD_1_WDT_EWOFFSET_CYC128_Val << FUSES_USER_WORD_1_WDT_EWOFFSET_Pos) /* (FUSES_USER_WORD_1) 128 clock cycles Position */ 214 #define FUSES_USER_WORD_1_WDT_EWOFFSET_CYC256 (FUSES_USER_WORD_1_WDT_EWOFFSET_CYC256_Val << FUSES_USER_WORD_1_WDT_EWOFFSET_Pos) /* (FUSES_USER_WORD_1) 256 clock cycles Position */ 215 #define FUSES_USER_WORD_1_WDT_EWOFFSET_CYC512 (FUSES_USER_WORD_1_WDT_EWOFFSET_CYC512_Val << FUSES_USER_WORD_1_WDT_EWOFFSET_Pos) /* (FUSES_USER_WORD_1) 512 clock cycles Position */ 216 #define FUSES_USER_WORD_1_WDT_EWOFFSET_CYC1024 (FUSES_USER_WORD_1_WDT_EWOFFSET_CYC1024_Val << FUSES_USER_WORD_1_WDT_EWOFFSET_Pos) /* (FUSES_USER_WORD_1) 1024 clock cycles Position */ 217 #define FUSES_USER_WORD_1_WDT_EWOFFSET_CYC2048 (FUSES_USER_WORD_1_WDT_EWOFFSET_CYC2048_Val << FUSES_USER_WORD_1_WDT_EWOFFSET_Pos) /* (FUSES_USER_WORD_1) 2048 clock cycles Position */ 218 #define FUSES_USER_WORD_1_WDT_EWOFFSET_CYC4096 (FUSES_USER_WORD_1_WDT_EWOFFSET_CYC4096_Val << FUSES_USER_WORD_1_WDT_EWOFFSET_Pos) /* (FUSES_USER_WORD_1) 4096 clock cycles Position */ 219 #define FUSES_USER_WORD_1_WDT_EWOFFSET_CYC8192 (FUSES_USER_WORD_1_WDT_EWOFFSET_CYC8192_Val << FUSES_USER_WORD_1_WDT_EWOFFSET_Pos) /* (FUSES_USER_WORD_1) 8192 clock cycles Position */ 220 #define FUSES_USER_WORD_1_WDT_WEN_Pos _UINT32_(30) /* (FUSES_USER_WORD_1) WDT Window Mode Enable Position */ 221 #define FUSES_USER_WORD_1_WDT_WEN_Msk (_UINT32_(0x1) << FUSES_USER_WORD_1_WDT_WEN_Pos) /* (FUSES_USER_WORD_1) WDT Window Mode Enable Mask */ 222 #define FUSES_USER_WORD_1_WDT_WEN(value) (FUSES_USER_WORD_1_WDT_WEN_Msk & (_UINT32_(value) << FUSES_USER_WORD_1_WDT_WEN_Pos)) /* Assigment of value for WDT_WEN in the FUSES_USER_WORD_1 register */ 223 #define FUSES_USER_WORD_1_Msk _UINT32_(0x7FFF00FF) /* (FUSES_USER_WORD_1) Register Mask */ 224 225 226 /* -------- FUSES_USER_WORD_2 : (FUSES Offset: 0x08) (R/W 32) USER Page Word 2 -------- */ 227 #define FUSES_USER_WORD_2_NVMCTRL_REGION_LOCKS_Pos _UINT32_(0) /* (FUSES_USER_WORD_2) NVM Region Locks Position */ 228 #define FUSES_USER_WORD_2_NVMCTRL_REGION_LOCKS_Msk (_UINT32_(0xFFFFFFFF) << FUSES_USER_WORD_2_NVMCTRL_REGION_LOCKS_Pos) /* (FUSES_USER_WORD_2) NVM Region Locks Mask */ 229 #define FUSES_USER_WORD_2_NVMCTRL_REGION_LOCKS(value) (FUSES_USER_WORD_2_NVMCTRL_REGION_LOCKS_Msk & (_UINT32_(value) << FUSES_USER_WORD_2_NVMCTRL_REGION_LOCKS_Pos)) /* Assigment of value for NVMCTRL_REGION_LOCKS in the FUSES_USER_WORD_2 register */ 230 #define FUSES_USER_WORD_2_Msk _UINT32_(0xFFFFFFFF) /* (FUSES_USER_WORD_2) Register Mask */ 231 232 233 /** \brief FUSES register offsets definitions */ 234 #define FUSES_SW0_WORD_0_REG_OFST _UINT32_(0x00) /* (FUSES_SW0_WORD_0) SW0 Page Word 0 Offset */ 235 #define FUSES_SW0_WORD_1_REG_OFST _UINT32_(0x04) /* (FUSES_SW0_WORD_1) SW0 Page Word 1 Offset */ 236 #define FUSES_USER_WORD_0_REG_OFST _UINT32_(0x00) /* (FUSES_USER_WORD_0) USER Page Word 0 Offset */ 237 #define FUSES_USER_WORD_1_REG_OFST _UINT32_(0x04) /* (FUSES_USER_WORD_1) USER Page Word 1 Offset */ 238 #define FUSES_USER_WORD_2_REG_OFST _UINT32_(0x08) /* (FUSES_USER_WORD_2) USER Page Word 2 Offset */ 239 240 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 241 /** \brief SW0_FUSES register API structure */ 242 typedef struct 243 { 244 __I uint32_t FUSES_SW0_WORD_0; /**< Offset: 0x00 (R/ 32) SW0 Page Word 0 */ 245 __I uint32_t FUSES_SW0_WORD_1; /**< Offset: 0x04 (R/ 32) SW0 Page Word 1 */ 246 } fuses_sw0_fuses_registers_t; 247 248 /** \brief USER_FUSES register API structure */ 249 typedef struct 250 { 251 __IO uint32_t FUSES_USER_WORD_0; /**< Offset: 0x00 (R/W 32) USER Page Word 0 */ 252 __IO uint32_t FUSES_USER_WORD_1; /**< Offset: 0x04 (R/W 32) USER Page Word 1 */ 253 __IO uint32_t FUSES_USER_WORD_2; /**< Offset: 0x08 (R/W 32) USER Page Word 2 */ 254 } fuses_user_fuses_registers_t; 255 256 257 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 258 #endif /* _PIC32CXSG61_FUSES_COMPONENT_H_ */ 259
