1 /* 2 * Component description for EIC 3 * 4 * Copyright (c) 2023 Microchip Technology Inc. and its subsidiaries. 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 */ 19 20 /* file generated from device description file (ATDF) version 2023-03-17T09:48:59Z */ 21 #ifndef _PIC32CXSG61_EIC_COMPONENT_H_ 22 #define _PIC32CXSG61_EIC_COMPONENT_H_ 23 24 /* ************************************************************************** */ 25 /* SOFTWARE API DEFINITION FOR EIC */ 26 /* ************************************************************************** */ 27 28 /* -------- EIC_CTRLA : (EIC Offset: 0x00) (R/W 8) Control A -------- */ 29 #define EIC_CTRLA_RESETVALUE _UINT8_(0x00) /* (EIC_CTRLA) Control A Reset Value */ 30 31 #define EIC_CTRLA_SWRST_Pos _UINT8_(0) /* (EIC_CTRLA) Software Reset Position */ 32 #define EIC_CTRLA_SWRST_Msk (_UINT8_(0x1) << EIC_CTRLA_SWRST_Pos) /* (EIC_CTRLA) Software Reset Mask */ 33 #define EIC_CTRLA_SWRST(value) (EIC_CTRLA_SWRST_Msk & (_UINT8_(value) << EIC_CTRLA_SWRST_Pos)) /* Assigment of value for SWRST in the EIC_CTRLA register */ 34 #define EIC_CTRLA_ENABLE_Pos _UINT8_(1) /* (EIC_CTRLA) Enable Position */ 35 #define EIC_CTRLA_ENABLE_Msk (_UINT8_(0x1) << EIC_CTRLA_ENABLE_Pos) /* (EIC_CTRLA) Enable Mask */ 36 #define EIC_CTRLA_ENABLE(value) (EIC_CTRLA_ENABLE_Msk & (_UINT8_(value) << EIC_CTRLA_ENABLE_Pos)) /* Assigment of value for ENABLE in the EIC_CTRLA register */ 37 #define EIC_CTRLA_CKSEL_Pos _UINT8_(4) /* (EIC_CTRLA) Clock Selection Position */ 38 #define EIC_CTRLA_CKSEL_Msk (_UINT8_(0x1) << EIC_CTRLA_CKSEL_Pos) /* (EIC_CTRLA) Clock Selection Mask */ 39 #define EIC_CTRLA_CKSEL(value) (EIC_CTRLA_CKSEL_Msk & (_UINT8_(value) << EIC_CTRLA_CKSEL_Pos)) /* Assigment of value for CKSEL in the EIC_CTRLA register */ 40 #define EIC_CTRLA_CKSEL_CLK_GCLK_Val _UINT8_(0x0) /* (EIC_CTRLA) Clocked by GCLK */ 41 #define EIC_CTRLA_CKSEL_CLK_ULP32K_Val _UINT8_(0x1) /* (EIC_CTRLA) Clocked by ULP32K */ 42 #define EIC_CTRLA_CKSEL_CLK_GCLK (EIC_CTRLA_CKSEL_CLK_GCLK_Val << EIC_CTRLA_CKSEL_Pos) /* (EIC_CTRLA) Clocked by GCLK Position */ 43 #define EIC_CTRLA_CKSEL_CLK_ULP32K (EIC_CTRLA_CKSEL_CLK_ULP32K_Val << EIC_CTRLA_CKSEL_Pos) /* (EIC_CTRLA) Clocked by ULP32K Position */ 44 #define EIC_CTRLA_Msk _UINT8_(0x13) /* (EIC_CTRLA) Register Mask */ 45 46 47 /* -------- EIC_NMICTRL : (EIC Offset: 0x01) (R/W 8) Non-Maskable Interrupt Control -------- */ 48 #define EIC_NMICTRL_RESETVALUE _UINT8_(0x00) /* (EIC_NMICTRL) Non-Maskable Interrupt Control Reset Value */ 49 50 #define EIC_NMICTRL_NMISENSE_Pos _UINT8_(0) /* (EIC_NMICTRL) Non-Maskable Interrupt Sense Configuration Position */ 51 #define EIC_NMICTRL_NMISENSE_Msk (_UINT8_(0x7) << EIC_NMICTRL_NMISENSE_Pos) /* (EIC_NMICTRL) Non-Maskable Interrupt Sense Configuration Mask */ 52 #define EIC_NMICTRL_NMISENSE(value) (EIC_NMICTRL_NMISENSE_Msk & (_UINT8_(value) << EIC_NMICTRL_NMISENSE_Pos)) /* Assigment of value for NMISENSE in the EIC_NMICTRL register */ 53 #define EIC_NMICTRL_NMISENSE_NONE_Val _UINT8_(0x0) /* (EIC_NMICTRL) No detection */ 54 #define EIC_NMICTRL_NMISENSE_RISE_Val _UINT8_(0x1) /* (EIC_NMICTRL) Rising-edge detection */ 55 #define EIC_NMICTRL_NMISENSE_FALL_Val _UINT8_(0x2) /* (EIC_NMICTRL) Falling-edge detection */ 56 #define EIC_NMICTRL_NMISENSE_BOTH_Val _UINT8_(0x3) /* (EIC_NMICTRL) Both-edges detection */ 57 #define EIC_NMICTRL_NMISENSE_HIGH_Val _UINT8_(0x4) /* (EIC_NMICTRL) High-level detection */ 58 #define EIC_NMICTRL_NMISENSE_LOW_Val _UINT8_(0x5) /* (EIC_NMICTRL) Low-level detection */ 59 #define EIC_NMICTRL_NMISENSE_NONE (EIC_NMICTRL_NMISENSE_NONE_Val << EIC_NMICTRL_NMISENSE_Pos) /* (EIC_NMICTRL) No detection Position */ 60 #define EIC_NMICTRL_NMISENSE_RISE (EIC_NMICTRL_NMISENSE_RISE_Val << EIC_NMICTRL_NMISENSE_Pos) /* (EIC_NMICTRL) Rising-edge detection Position */ 61 #define EIC_NMICTRL_NMISENSE_FALL (EIC_NMICTRL_NMISENSE_FALL_Val << EIC_NMICTRL_NMISENSE_Pos) /* (EIC_NMICTRL) Falling-edge detection Position */ 62 #define EIC_NMICTRL_NMISENSE_BOTH (EIC_NMICTRL_NMISENSE_BOTH_Val << EIC_NMICTRL_NMISENSE_Pos) /* (EIC_NMICTRL) Both-edges detection Position */ 63 #define EIC_NMICTRL_NMISENSE_HIGH (EIC_NMICTRL_NMISENSE_HIGH_Val << EIC_NMICTRL_NMISENSE_Pos) /* (EIC_NMICTRL) High-level detection Position */ 64 #define EIC_NMICTRL_NMISENSE_LOW (EIC_NMICTRL_NMISENSE_LOW_Val << EIC_NMICTRL_NMISENSE_Pos) /* (EIC_NMICTRL) Low-level detection Position */ 65 #define EIC_NMICTRL_NMIFILTEN_Pos _UINT8_(3) /* (EIC_NMICTRL) Non-Maskable Interrupt Filter Enable Position */ 66 #define EIC_NMICTRL_NMIFILTEN_Msk (_UINT8_(0x1) << EIC_NMICTRL_NMIFILTEN_Pos) /* (EIC_NMICTRL) Non-Maskable Interrupt Filter Enable Mask */ 67 #define EIC_NMICTRL_NMIFILTEN(value) (EIC_NMICTRL_NMIFILTEN_Msk & (_UINT8_(value) << EIC_NMICTRL_NMIFILTEN_Pos)) /* Assigment of value for NMIFILTEN in the EIC_NMICTRL register */ 68 #define EIC_NMICTRL_NMIASYNCH_Pos _UINT8_(4) /* (EIC_NMICTRL) Asynchronous Edge Detection Mode Position */ 69 #define EIC_NMICTRL_NMIASYNCH_Msk (_UINT8_(0x1) << EIC_NMICTRL_NMIASYNCH_Pos) /* (EIC_NMICTRL) Asynchronous Edge Detection Mode Mask */ 70 #define EIC_NMICTRL_NMIASYNCH(value) (EIC_NMICTRL_NMIASYNCH_Msk & (_UINT8_(value) << EIC_NMICTRL_NMIASYNCH_Pos)) /* Assigment of value for NMIASYNCH in the EIC_NMICTRL register */ 71 #define EIC_NMICTRL_NMIASYNCH_SYNC_Val _UINT8_(0x0) /* (EIC_NMICTRL) Edge detection is clock synchronously operated */ 72 #define EIC_NMICTRL_NMIASYNCH_ASYNC_Val _UINT8_(0x1) /* (EIC_NMICTRL) Edge detection is clock asynchronously operated */ 73 #define EIC_NMICTRL_NMIASYNCH_SYNC (EIC_NMICTRL_NMIASYNCH_SYNC_Val << EIC_NMICTRL_NMIASYNCH_Pos) /* (EIC_NMICTRL) Edge detection is clock synchronously operated Position */ 74 #define EIC_NMICTRL_NMIASYNCH_ASYNC (EIC_NMICTRL_NMIASYNCH_ASYNC_Val << EIC_NMICTRL_NMIASYNCH_Pos) /* (EIC_NMICTRL) Edge detection is clock asynchronously operated Position */ 75 #define EIC_NMICTRL_Msk _UINT8_(0x1F) /* (EIC_NMICTRL) Register Mask */ 76 77 78 /* -------- EIC_NMIFLAG : (EIC Offset: 0x02) (R/W 16) Non-Maskable Interrupt Flag Status and Clear -------- */ 79 #define EIC_NMIFLAG_RESETVALUE _UINT16_(0x00) /* (EIC_NMIFLAG) Non-Maskable Interrupt Flag Status and Clear Reset Value */ 80 81 #define EIC_NMIFLAG_NMI_Pos _UINT16_(0) /* (EIC_NMIFLAG) Non-Maskable Interrupt Position */ 82 #define EIC_NMIFLAG_NMI_Msk (_UINT16_(0x1) << EIC_NMIFLAG_NMI_Pos) /* (EIC_NMIFLAG) Non-Maskable Interrupt Mask */ 83 #define EIC_NMIFLAG_NMI(value) (EIC_NMIFLAG_NMI_Msk & (_UINT16_(value) << EIC_NMIFLAG_NMI_Pos)) /* Assigment of value for NMI in the EIC_NMIFLAG register */ 84 #define EIC_NMIFLAG_Msk _UINT16_(0x0001) /* (EIC_NMIFLAG) Register Mask */ 85 86 87 /* -------- EIC_SYNCBUSY : (EIC Offset: 0x04) ( R/ 32) Synchronization Busy -------- */ 88 #define EIC_SYNCBUSY_RESETVALUE _UINT32_(0x00) /* (EIC_SYNCBUSY) Synchronization Busy Reset Value */ 89 90 #define EIC_SYNCBUSY_SWRST_Pos _UINT32_(0) /* (EIC_SYNCBUSY) Software Reset Synchronization Busy Status Position */ 91 #define EIC_SYNCBUSY_SWRST_Msk (_UINT32_(0x1) << EIC_SYNCBUSY_SWRST_Pos) /* (EIC_SYNCBUSY) Software Reset Synchronization Busy Status Mask */ 92 #define EIC_SYNCBUSY_SWRST(value) (EIC_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << EIC_SYNCBUSY_SWRST_Pos)) /* Assigment of value for SWRST in the EIC_SYNCBUSY register */ 93 #define EIC_SYNCBUSY_ENABLE_Pos _UINT32_(1) /* (EIC_SYNCBUSY) Enable Synchronization Busy Status Position */ 94 #define EIC_SYNCBUSY_ENABLE_Msk (_UINT32_(0x1) << EIC_SYNCBUSY_ENABLE_Pos) /* (EIC_SYNCBUSY) Enable Synchronization Busy Status Mask */ 95 #define EIC_SYNCBUSY_ENABLE(value) (EIC_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << EIC_SYNCBUSY_ENABLE_Pos)) /* Assigment of value for ENABLE in the EIC_SYNCBUSY register */ 96 #define EIC_SYNCBUSY_Msk _UINT32_(0x00000003) /* (EIC_SYNCBUSY) Register Mask */ 97 98 99 /* -------- EIC_EVCTRL : (EIC Offset: 0x08) (R/W 32) Event Control -------- */ 100 #define EIC_EVCTRL_RESETVALUE _UINT32_(0x00) /* (EIC_EVCTRL) Event Control Reset Value */ 101 102 #define EIC_EVCTRL_EXTINTEO_Pos _UINT32_(0) /* (EIC_EVCTRL) External Interrupt Event Output Enable Position */ 103 #define EIC_EVCTRL_EXTINTEO_Msk (_UINT32_(0xFFFF) << EIC_EVCTRL_EXTINTEO_Pos) /* (EIC_EVCTRL) External Interrupt Event Output Enable Mask */ 104 #define EIC_EVCTRL_EXTINTEO(value) (EIC_EVCTRL_EXTINTEO_Msk & (_UINT32_(value) << EIC_EVCTRL_EXTINTEO_Pos)) /* Assigment of value for EXTINTEO in the EIC_EVCTRL register */ 105 #define EIC_EVCTRL_Msk _UINT32_(0x0000FFFF) /* (EIC_EVCTRL) Register Mask */ 106 107 108 /* -------- EIC_INTENCLR : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Clear -------- */ 109 #define EIC_INTENCLR_RESETVALUE _UINT32_(0x00) /* (EIC_INTENCLR) Interrupt Enable Clear Reset Value */ 110 111 #define EIC_INTENCLR_EXTINT_Pos _UINT32_(0) /* (EIC_INTENCLR) External Interrupt Enable Position */ 112 #define EIC_INTENCLR_EXTINT_Msk (_UINT32_(0xFFFF) << EIC_INTENCLR_EXTINT_Pos) /* (EIC_INTENCLR) External Interrupt Enable Mask */ 113 #define EIC_INTENCLR_EXTINT(value) (EIC_INTENCLR_EXTINT_Msk & (_UINT32_(value) << EIC_INTENCLR_EXTINT_Pos)) /* Assigment of value for EXTINT in the EIC_INTENCLR register */ 114 #define EIC_INTENCLR_Msk _UINT32_(0x0000FFFF) /* (EIC_INTENCLR) Register Mask */ 115 116 117 /* -------- EIC_INTENSET : (EIC Offset: 0x10) (R/W 32) Interrupt Enable Set -------- */ 118 #define EIC_INTENSET_RESETVALUE _UINT32_(0x00) /* (EIC_INTENSET) Interrupt Enable Set Reset Value */ 119 120 #define EIC_INTENSET_EXTINT_Pos _UINT32_(0) /* (EIC_INTENSET) External Interrupt Enable Position */ 121 #define EIC_INTENSET_EXTINT_Msk (_UINT32_(0xFFFF) << EIC_INTENSET_EXTINT_Pos) /* (EIC_INTENSET) External Interrupt Enable Mask */ 122 #define EIC_INTENSET_EXTINT(value) (EIC_INTENSET_EXTINT_Msk & (_UINT32_(value) << EIC_INTENSET_EXTINT_Pos)) /* Assigment of value for EXTINT in the EIC_INTENSET register */ 123 #define EIC_INTENSET_Msk _UINT32_(0x0000FFFF) /* (EIC_INTENSET) Register Mask */ 124 125 126 /* -------- EIC_INTFLAG : (EIC Offset: 0x14) (R/W 32) Interrupt Flag Status and Clear -------- */ 127 #define EIC_INTFLAG_RESETVALUE _UINT32_(0x00) /* (EIC_INTFLAG) Interrupt Flag Status and Clear Reset Value */ 128 129 #define EIC_INTFLAG_EXTINT_Pos _UINT32_(0) /* (EIC_INTFLAG) External Interrupt Position */ 130 #define EIC_INTFLAG_EXTINT_Msk (_UINT32_(0xFFFF) << EIC_INTFLAG_EXTINT_Pos) /* (EIC_INTFLAG) External Interrupt Mask */ 131 #define EIC_INTFLAG_EXTINT(value) (EIC_INTFLAG_EXTINT_Msk & (_UINT32_(value) << EIC_INTFLAG_EXTINT_Pos)) /* Assigment of value for EXTINT in the EIC_INTFLAG register */ 132 #define EIC_INTFLAG_Msk _UINT32_(0x0000FFFF) /* (EIC_INTFLAG) Register Mask */ 133 134 135 /* -------- EIC_ASYNCH : (EIC Offset: 0x18) (R/W 32) External Interrupt Asynchronous Mode -------- */ 136 #define EIC_ASYNCH_RESETVALUE _UINT32_(0x00) /* (EIC_ASYNCH) External Interrupt Asynchronous Mode Reset Value */ 137 138 #define EIC_ASYNCH_ASYNCH_Pos _UINT32_(0) /* (EIC_ASYNCH) Asynchronous Edge Detection Mode Position */ 139 #define EIC_ASYNCH_ASYNCH_Msk (_UINT32_(0xFFFF) << EIC_ASYNCH_ASYNCH_Pos) /* (EIC_ASYNCH) Asynchronous Edge Detection Mode Mask */ 140 #define EIC_ASYNCH_ASYNCH(value) (EIC_ASYNCH_ASYNCH_Msk & (_UINT32_(value) << EIC_ASYNCH_ASYNCH_Pos)) /* Assigment of value for ASYNCH in the EIC_ASYNCH register */ 141 #define EIC_ASYNCH_ASYNCH_SYNC_Val _UINT32_(0x0) /* (EIC_ASYNCH) Edge detection is clock synchronously operated */ 142 #define EIC_ASYNCH_ASYNCH_ASYNC_Val _UINT32_(0x1) /* (EIC_ASYNCH) Edge detection is clock asynchronously operated */ 143 #define EIC_ASYNCH_ASYNCH_SYNC (EIC_ASYNCH_ASYNCH_SYNC_Val << EIC_ASYNCH_ASYNCH_Pos) /* (EIC_ASYNCH) Edge detection is clock synchronously operated Position */ 144 #define EIC_ASYNCH_ASYNCH_ASYNC (EIC_ASYNCH_ASYNCH_ASYNC_Val << EIC_ASYNCH_ASYNCH_Pos) /* (EIC_ASYNCH) Edge detection is clock asynchronously operated Position */ 145 #define EIC_ASYNCH_Msk _UINT32_(0x0000FFFF) /* (EIC_ASYNCH) Register Mask */ 146 147 148 /* -------- EIC_CONFIG0 : (EIC Offset: 0x1C) (R/W 32) External Interrupt Sense Configuration -------- */ 149 #define EIC_CONFIG0_RESETVALUE _UINT32_(0x00) /* (EIC_CONFIG0) External Interrupt Sense Configuration Reset Value */ 150 151 #define EIC_CONFIG0_SENSE0_Pos _UINT32_(0) /* (EIC_CONFIG0) Input Sense Configuration 0 Position */ 152 #define EIC_CONFIG0_SENSE0_Msk (_UINT32_(0x7) << EIC_CONFIG0_SENSE0_Pos) /* (EIC_CONFIG0) Input Sense Configuration 0 Mask */ 153 #define EIC_CONFIG0_SENSE0(value) (EIC_CONFIG0_SENSE0_Msk & (_UINT32_(value) << EIC_CONFIG0_SENSE0_Pos)) /* Assigment of value for SENSE0 in the EIC_CONFIG0 register */ 154 #define EIC_CONFIG0_SENSE0_NONE_Val _UINT32_(0x0) /* (EIC_CONFIG0) No detection */ 155 #define EIC_CONFIG0_SENSE0_RISE_Val _UINT32_(0x1) /* (EIC_CONFIG0) Rising edge detection */ 156 #define EIC_CONFIG0_SENSE0_FALL_Val _UINT32_(0x2) /* (EIC_CONFIG0) Falling edge detection */ 157 #define EIC_CONFIG0_SENSE0_BOTH_Val _UINT32_(0x3) /* (EIC_CONFIG0) Both edges detection */ 158 #define EIC_CONFIG0_SENSE0_HIGH_Val _UINT32_(0x4) /* (EIC_CONFIG0) High level detection */ 159 #define EIC_CONFIG0_SENSE0_LOW_Val _UINT32_(0x5) /* (EIC_CONFIG0) Low level detection */ 160 #define EIC_CONFIG0_SENSE0_NONE (EIC_CONFIG0_SENSE0_NONE_Val << EIC_CONFIG0_SENSE0_Pos) /* (EIC_CONFIG0) No detection Position */ 161 #define EIC_CONFIG0_SENSE0_RISE (EIC_CONFIG0_SENSE0_RISE_Val << EIC_CONFIG0_SENSE0_Pos) /* (EIC_CONFIG0) Rising edge detection Position */ 162 #define EIC_CONFIG0_SENSE0_FALL (EIC_CONFIG0_SENSE0_FALL_Val << EIC_CONFIG0_SENSE0_Pos) /* (EIC_CONFIG0) Falling edge detection Position */ 163 #define EIC_CONFIG0_SENSE0_BOTH (EIC_CONFIG0_SENSE0_BOTH_Val << EIC_CONFIG0_SENSE0_Pos) /* (EIC_CONFIG0) Both edges detection Position */ 164 #define EIC_CONFIG0_SENSE0_HIGH (EIC_CONFIG0_SENSE0_HIGH_Val << EIC_CONFIG0_SENSE0_Pos) /* (EIC_CONFIG0) High level detection Position */ 165 #define EIC_CONFIG0_SENSE0_LOW (EIC_CONFIG0_SENSE0_LOW_Val << EIC_CONFIG0_SENSE0_Pos) /* (EIC_CONFIG0) Low level detection Position */ 166 #define EIC_CONFIG0_FILTEN0_Pos _UINT32_(3) /* (EIC_CONFIG0) Filter Enable 0 Position */ 167 #define EIC_CONFIG0_FILTEN0_Msk (_UINT32_(0x1) << EIC_CONFIG0_FILTEN0_Pos) /* (EIC_CONFIG0) Filter Enable 0 Mask */ 168 #define EIC_CONFIG0_FILTEN0(value) (EIC_CONFIG0_FILTEN0_Msk & (_UINT32_(value) << EIC_CONFIG0_FILTEN0_Pos)) /* Assigment of value for FILTEN0 in the EIC_CONFIG0 register */ 169 #define EIC_CONFIG0_SENSE1_Pos _UINT32_(4) /* (EIC_CONFIG0) Input Sense Configuration 1 Position */ 170 #define EIC_CONFIG0_SENSE1_Msk (_UINT32_(0x7) << EIC_CONFIG0_SENSE1_Pos) /* (EIC_CONFIG0) Input Sense Configuration 1 Mask */ 171 #define EIC_CONFIG0_SENSE1(value) (EIC_CONFIG0_SENSE1_Msk & (_UINT32_(value) << EIC_CONFIG0_SENSE1_Pos)) /* Assigment of value for SENSE1 in the EIC_CONFIG0 register */ 172 #define EIC_CONFIG0_SENSE1_NONE_Val _UINT32_(0x0) /* (EIC_CONFIG0) No detection */ 173 #define EIC_CONFIG0_SENSE1_RISE_Val _UINT32_(0x1) /* (EIC_CONFIG0) Rising edge detection */ 174 #define EIC_CONFIG0_SENSE1_FALL_Val _UINT32_(0x2) /* (EIC_CONFIG0) Falling edge detection */ 175 #define EIC_CONFIG0_SENSE1_BOTH_Val _UINT32_(0x3) /* (EIC_CONFIG0) Both edges detection */ 176 #define EIC_CONFIG0_SENSE1_HIGH_Val _UINT32_(0x4) /* (EIC_CONFIG0) High level detection */ 177 #define EIC_CONFIG0_SENSE1_LOW_Val _UINT32_(0x5) /* (EIC_CONFIG0) Low level detection */ 178 #define EIC_CONFIG0_SENSE1_NONE (EIC_CONFIG0_SENSE1_NONE_Val << EIC_CONFIG0_SENSE1_Pos) /* (EIC_CONFIG0) No detection Position */ 179 #define EIC_CONFIG0_SENSE1_RISE (EIC_CONFIG0_SENSE1_RISE_Val << EIC_CONFIG0_SENSE1_Pos) /* (EIC_CONFIG0) Rising edge detection Position */ 180 #define EIC_CONFIG0_SENSE1_FALL (EIC_CONFIG0_SENSE1_FALL_Val << EIC_CONFIG0_SENSE1_Pos) /* (EIC_CONFIG0) Falling edge detection Position */ 181 #define EIC_CONFIG0_SENSE1_BOTH (EIC_CONFIG0_SENSE1_BOTH_Val << EIC_CONFIG0_SENSE1_Pos) /* (EIC_CONFIG0) Both edges detection Position */ 182 #define EIC_CONFIG0_SENSE1_HIGH (EIC_CONFIG0_SENSE1_HIGH_Val << EIC_CONFIG0_SENSE1_Pos) /* (EIC_CONFIG0) High level detection Position */ 183 #define EIC_CONFIG0_SENSE1_LOW (EIC_CONFIG0_SENSE1_LOW_Val << EIC_CONFIG0_SENSE1_Pos) /* (EIC_CONFIG0) Low level detection Position */ 184 #define EIC_CONFIG0_FILTEN1_Pos _UINT32_(7) /* (EIC_CONFIG0) Filter Enable 1 Position */ 185 #define EIC_CONFIG0_FILTEN1_Msk (_UINT32_(0x1) << EIC_CONFIG0_FILTEN1_Pos) /* (EIC_CONFIG0) Filter Enable 1 Mask */ 186 #define EIC_CONFIG0_FILTEN1(value) (EIC_CONFIG0_FILTEN1_Msk & (_UINT32_(value) << EIC_CONFIG0_FILTEN1_Pos)) /* Assigment of value for FILTEN1 in the EIC_CONFIG0 register */ 187 #define EIC_CONFIG0_SENSE2_Pos _UINT32_(8) /* (EIC_CONFIG0) Input Sense Configuration 2 Position */ 188 #define EIC_CONFIG0_SENSE2_Msk (_UINT32_(0x7) << EIC_CONFIG0_SENSE2_Pos) /* (EIC_CONFIG0) Input Sense Configuration 2 Mask */ 189 #define EIC_CONFIG0_SENSE2(value) (EIC_CONFIG0_SENSE2_Msk & (_UINT32_(value) << EIC_CONFIG0_SENSE2_Pos)) /* Assigment of value for SENSE2 in the EIC_CONFIG0 register */ 190 #define EIC_CONFIG0_SENSE2_NONE_Val _UINT32_(0x0) /* (EIC_CONFIG0) No detection */ 191 #define EIC_CONFIG0_SENSE2_RISE_Val _UINT32_(0x1) /* (EIC_CONFIG0) Rising edge detection */ 192 #define EIC_CONFIG0_SENSE2_FALL_Val _UINT32_(0x2) /* (EIC_CONFIG0) Falling edge detection */ 193 #define EIC_CONFIG0_SENSE2_BOTH_Val _UINT32_(0x3) /* (EIC_CONFIG0) Both edges detection */ 194 #define EIC_CONFIG0_SENSE2_HIGH_Val _UINT32_(0x4) /* (EIC_CONFIG0) High level detection */ 195 #define EIC_CONFIG0_SENSE2_LOW_Val _UINT32_(0x5) /* (EIC_CONFIG0) Low level detection */ 196 #define EIC_CONFIG0_SENSE2_NONE (EIC_CONFIG0_SENSE2_NONE_Val << EIC_CONFIG0_SENSE2_Pos) /* (EIC_CONFIG0) No detection Position */ 197 #define EIC_CONFIG0_SENSE2_RISE (EIC_CONFIG0_SENSE2_RISE_Val << EIC_CONFIG0_SENSE2_Pos) /* (EIC_CONFIG0) Rising edge detection Position */ 198 #define EIC_CONFIG0_SENSE2_FALL (EIC_CONFIG0_SENSE2_FALL_Val << EIC_CONFIG0_SENSE2_Pos) /* (EIC_CONFIG0) Falling edge detection Position */ 199 #define EIC_CONFIG0_SENSE2_BOTH (EIC_CONFIG0_SENSE2_BOTH_Val << EIC_CONFIG0_SENSE2_Pos) /* (EIC_CONFIG0) Both edges detection Position */ 200 #define EIC_CONFIG0_SENSE2_HIGH (EIC_CONFIG0_SENSE2_HIGH_Val << EIC_CONFIG0_SENSE2_Pos) /* (EIC_CONFIG0) High level detection Position */ 201 #define EIC_CONFIG0_SENSE2_LOW (EIC_CONFIG0_SENSE2_LOW_Val << EIC_CONFIG0_SENSE2_Pos) /* (EIC_CONFIG0) Low level detection Position */ 202 #define EIC_CONFIG0_FILTEN2_Pos _UINT32_(11) /* (EIC_CONFIG0) Filter Enable 2 Position */ 203 #define EIC_CONFIG0_FILTEN2_Msk (_UINT32_(0x1) << EIC_CONFIG0_FILTEN2_Pos) /* (EIC_CONFIG0) Filter Enable 2 Mask */ 204 #define EIC_CONFIG0_FILTEN2(value) (EIC_CONFIG0_FILTEN2_Msk & (_UINT32_(value) << EIC_CONFIG0_FILTEN2_Pos)) /* Assigment of value for FILTEN2 in the EIC_CONFIG0 register */ 205 #define EIC_CONFIG0_SENSE3_Pos _UINT32_(12) /* (EIC_CONFIG0) Input Sense Configuration 3 Position */ 206 #define EIC_CONFIG0_SENSE3_Msk (_UINT32_(0x7) << EIC_CONFIG0_SENSE3_Pos) /* (EIC_CONFIG0) Input Sense Configuration 3 Mask */ 207 #define EIC_CONFIG0_SENSE3(value) (EIC_CONFIG0_SENSE3_Msk & (_UINT32_(value) << EIC_CONFIG0_SENSE3_Pos)) /* Assigment of value for SENSE3 in the EIC_CONFIG0 register */ 208 #define EIC_CONFIG0_SENSE3_NONE_Val _UINT32_(0x0) /* (EIC_CONFIG0) No detection */ 209 #define EIC_CONFIG0_SENSE3_RISE_Val _UINT32_(0x1) /* (EIC_CONFIG0) Rising edge detection */ 210 #define EIC_CONFIG0_SENSE3_FALL_Val _UINT32_(0x2) /* (EIC_CONFIG0) Falling edge detection */ 211 #define EIC_CONFIG0_SENSE3_BOTH_Val _UINT32_(0x3) /* (EIC_CONFIG0) Both edges detection */ 212 #define EIC_CONFIG0_SENSE3_HIGH_Val _UINT32_(0x4) /* (EIC_CONFIG0) High level detection */ 213 #define EIC_CONFIG0_SENSE3_LOW_Val _UINT32_(0x5) /* (EIC_CONFIG0) Low level detection */ 214 #define EIC_CONFIG0_SENSE3_NONE (EIC_CONFIG0_SENSE3_NONE_Val << EIC_CONFIG0_SENSE3_Pos) /* (EIC_CONFIG0) No detection Position */ 215 #define EIC_CONFIG0_SENSE3_RISE (EIC_CONFIG0_SENSE3_RISE_Val << EIC_CONFIG0_SENSE3_Pos) /* (EIC_CONFIG0) Rising edge detection Position */ 216 #define EIC_CONFIG0_SENSE3_FALL (EIC_CONFIG0_SENSE3_FALL_Val << EIC_CONFIG0_SENSE3_Pos) /* (EIC_CONFIG0) Falling edge detection Position */ 217 #define EIC_CONFIG0_SENSE3_BOTH (EIC_CONFIG0_SENSE3_BOTH_Val << EIC_CONFIG0_SENSE3_Pos) /* (EIC_CONFIG0) Both edges detection Position */ 218 #define EIC_CONFIG0_SENSE3_HIGH (EIC_CONFIG0_SENSE3_HIGH_Val << EIC_CONFIG0_SENSE3_Pos) /* (EIC_CONFIG0) High level detection Position */ 219 #define EIC_CONFIG0_SENSE3_LOW (EIC_CONFIG0_SENSE3_LOW_Val << EIC_CONFIG0_SENSE3_Pos) /* (EIC_CONFIG0) Low level detection Position */ 220 #define EIC_CONFIG0_FILTEN3_Pos _UINT32_(15) /* (EIC_CONFIG0) Filter Enable 3 Position */ 221 #define EIC_CONFIG0_FILTEN3_Msk (_UINT32_(0x1) << EIC_CONFIG0_FILTEN3_Pos) /* (EIC_CONFIG0) Filter Enable 3 Mask */ 222 #define EIC_CONFIG0_FILTEN3(value) (EIC_CONFIG0_FILTEN3_Msk & (_UINT32_(value) << EIC_CONFIG0_FILTEN3_Pos)) /* Assigment of value for FILTEN3 in the EIC_CONFIG0 register */ 223 #define EIC_CONFIG0_SENSE4_Pos _UINT32_(16) /* (EIC_CONFIG0) Input Sense Configuration 4 Position */ 224 #define EIC_CONFIG0_SENSE4_Msk (_UINT32_(0x7) << EIC_CONFIG0_SENSE4_Pos) /* (EIC_CONFIG0) Input Sense Configuration 4 Mask */ 225 #define EIC_CONFIG0_SENSE4(value) (EIC_CONFIG0_SENSE4_Msk & (_UINT32_(value) << EIC_CONFIG0_SENSE4_Pos)) /* Assigment of value for SENSE4 in the EIC_CONFIG0 register */ 226 #define EIC_CONFIG0_SENSE4_NONE_Val _UINT32_(0x0) /* (EIC_CONFIG0) No detection */ 227 #define EIC_CONFIG0_SENSE4_RISE_Val _UINT32_(0x1) /* (EIC_CONFIG0) Rising edge detection */ 228 #define EIC_CONFIG0_SENSE4_FALL_Val _UINT32_(0x2) /* (EIC_CONFIG0) Falling edge detection */ 229 #define EIC_CONFIG0_SENSE4_BOTH_Val _UINT32_(0x3) /* (EIC_CONFIG0) Both edges detection */ 230 #define EIC_CONFIG0_SENSE4_HIGH_Val _UINT32_(0x4) /* (EIC_CONFIG0) High level detection */ 231 #define EIC_CONFIG0_SENSE4_LOW_Val _UINT32_(0x5) /* (EIC_CONFIG0) Low level detection */ 232 #define EIC_CONFIG0_SENSE4_NONE (EIC_CONFIG0_SENSE4_NONE_Val << EIC_CONFIG0_SENSE4_Pos) /* (EIC_CONFIG0) No detection Position */ 233 #define EIC_CONFIG0_SENSE4_RISE (EIC_CONFIG0_SENSE4_RISE_Val << EIC_CONFIG0_SENSE4_Pos) /* (EIC_CONFIG0) Rising edge detection Position */ 234 #define EIC_CONFIG0_SENSE4_FALL (EIC_CONFIG0_SENSE4_FALL_Val << EIC_CONFIG0_SENSE4_Pos) /* (EIC_CONFIG0) Falling edge detection Position */ 235 #define EIC_CONFIG0_SENSE4_BOTH (EIC_CONFIG0_SENSE4_BOTH_Val << EIC_CONFIG0_SENSE4_Pos) /* (EIC_CONFIG0) Both edges detection Position */ 236 #define EIC_CONFIG0_SENSE4_HIGH (EIC_CONFIG0_SENSE4_HIGH_Val << EIC_CONFIG0_SENSE4_Pos) /* (EIC_CONFIG0) High level detection Position */ 237 #define EIC_CONFIG0_SENSE4_LOW (EIC_CONFIG0_SENSE4_LOW_Val << EIC_CONFIG0_SENSE4_Pos) /* (EIC_CONFIG0) Low level detection Position */ 238 #define EIC_CONFIG0_FILTEN4_Pos _UINT32_(19) /* (EIC_CONFIG0) Filter Enable 4 Position */ 239 #define EIC_CONFIG0_FILTEN4_Msk (_UINT32_(0x1) << EIC_CONFIG0_FILTEN4_Pos) /* (EIC_CONFIG0) Filter Enable 4 Mask */ 240 #define EIC_CONFIG0_FILTEN4(value) (EIC_CONFIG0_FILTEN4_Msk & (_UINT32_(value) << EIC_CONFIG0_FILTEN4_Pos)) /* Assigment of value for FILTEN4 in the EIC_CONFIG0 register */ 241 #define EIC_CONFIG0_SENSE5_Pos _UINT32_(20) /* (EIC_CONFIG0) Input Sense Configuration 5 Position */ 242 #define EIC_CONFIG0_SENSE5_Msk (_UINT32_(0x7) << EIC_CONFIG0_SENSE5_Pos) /* (EIC_CONFIG0) Input Sense Configuration 5 Mask */ 243 #define EIC_CONFIG0_SENSE5(value) (EIC_CONFIG0_SENSE5_Msk & (_UINT32_(value) << EIC_CONFIG0_SENSE5_Pos)) /* Assigment of value for SENSE5 in the EIC_CONFIG0 register */ 244 #define EIC_CONFIG0_SENSE5_NONE_Val _UINT32_(0x0) /* (EIC_CONFIG0) No detection */ 245 #define EIC_CONFIG0_SENSE5_RISE_Val _UINT32_(0x1) /* (EIC_CONFIG0) Rising edge detection */ 246 #define EIC_CONFIG0_SENSE5_FALL_Val _UINT32_(0x2) /* (EIC_CONFIG0) Falling edge detection */ 247 #define EIC_CONFIG0_SENSE5_BOTH_Val _UINT32_(0x3) /* (EIC_CONFIG0) Both edges detection */ 248 #define EIC_CONFIG0_SENSE5_HIGH_Val _UINT32_(0x4) /* (EIC_CONFIG0) High level detection */ 249 #define EIC_CONFIG0_SENSE5_LOW_Val _UINT32_(0x5) /* (EIC_CONFIG0) Low level detection */ 250 #define EIC_CONFIG0_SENSE5_NONE (EIC_CONFIG0_SENSE5_NONE_Val << EIC_CONFIG0_SENSE5_Pos) /* (EIC_CONFIG0) No detection Position */ 251 #define EIC_CONFIG0_SENSE5_RISE (EIC_CONFIG0_SENSE5_RISE_Val << EIC_CONFIG0_SENSE5_Pos) /* (EIC_CONFIG0) Rising edge detection Position */ 252 #define EIC_CONFIG0_SENSE5_FALL (EIC_CONFIG0_SENSE5_FALL_Val << EIC_CONFIG0_SENSE5_Pos) /* (EIC_CONFIG0) Falling edge detection Position */ 253 #define EIC_CONFIG0_SENSE5_BOTH (EIC_CONFIG0_SENSE5_BOTH_Val << EIC_CONFIG0_SENSE5_Pos) /* (EIC_CONFIG0) Both edges detection Position */ 254 #define EIC_CONFIG0_SENSE5_HIGH (EIC_CONFIG0_SENSE5_HIGH_Val << EIC_CONFIG0_SENSE5_Pos) /* (EIC_CONFIG0) High level detection Position */ 255 #define EIC_CONFIG0_SENSE5_LOW (EIC_CONFIG0_SENSE5_LOW_Val << EIC_CONFIG0_SENSE5_Pos) /* (EIC_CONFIG0) Low level detection Position */ 256 #define EIC_CONFIG0_FILTEN5_Pos _UINT32_(23) /* (EIC_CONFIG0) Filter Enable 5 Position */ 257 #define EIC_CONFIG0_FILTEN5_Msk (_UINT32_(0x1) << EIC_CONFIG0_FILTEN5_Pos) /* (EIC_CONFIG0) Filter Enable 5 Mask */ 258 #define EIC_CONFIG0_FILTEN5(value) (EIC_CONFIG0_FILTEN5_Msk & (_UINT32_(value) << EIC_CONFIG0_FILTEN5_Pos)) /* Assigment of value for FILTEN5 in the EIC_CONFIG0 register */ 259 #define EIC_CONFIG0_SENSE6_Pos _UINT32_(24) /* (EIC_CONFIG0) Input Sense Configuration 6 Position */ 260 #define EIC_CONFIG0_SENSE6_Msk (_UINT32_(0x7) << EIC_CONFIG0_SENSE6_Pos) /* (EIC_CONFIG0) Input Sense Configuration 6 Mask */ 261 #define EIC_CONFIG0_SENSE6(value) (EIC_CONFIG0_SENSE6_Msk & (_UINT32_(value) << EIC_CONFIG0_SENSE6_Pos)) /* Assigment of value for SENSE6 in the EIC_CONFIG0 register */ 262 #define EIC_CONFIG0_SENSE6_NONE_Val _UINT32_(0x0) /* (EIC_CONFIG0) No detection */ 263 #define EIC_CONFIG0_SENSE6_RISE_Val _UINT32_(0x1) /* (EIC_CONFIG0) Rising edge detection */ 264 #define EIC_CONFIG0_SENSE6_FALL_Val _UINT32_(0x2) /* (EIC_CONFIG0) Falling edge detection */ 265 #define EIC_CONFIG0_SENSE6_BOTH_Val _UINT32_(0x3) /* (EIC_CONFIG0) Both edges detection */ 266 #define EIC_CONFIG0_SENSE6_HIGH_Val _UINT32_(0x4) /* (EIC_CONFIG0) High level detection */ 267 #define EIC_CONFIG0_SENSE6_LOW_Val _UINT32_(0x5) /* (EIC_CONFIG0) Low level detection */ 268 #define EIC_CONFIG0_SENSE6_NONE (EIC_CONFIG0_SENSE6_NONE_Val << EIC_CONFIG0_SENSE6_Pos) /* (EIC_CONFIG0) No detection Position */ 269 #define EIC_CONFIG0_SENSE6_RISE (EIC_CONFIG0_SENSE6_RISE_Val << EIC_CONFIG0_SENSE6_Pos) /* (EIC_CONFIG0) Rising edge detection Position */ 270 #define EIC_CONFIG0_SENSE6_FALL (EIC_CONFIG0_SENSE6_FALL_Val << EIC_CONFIG0_SENSE6_Pos) /* (EIC_CONFIG0) Falling edge detection Position */ 271 #define EIC_CONFIG0_SENSE6_BOTH (EIC_CONFIG0_SENSE6_BOTH_Val << EIC_CONFIG0_SENSE6_Pos) /* (EIC_CONFIG0) Both edges detection Position */ 272 #define EIC_CONFIG0_SENSE6_HIGH (EIC_CONFIG0_SENSE6_HIGH_Val << EIC_CONFIG0_SENSE6_Pos) /* (EIC_CONFIG0) High level detection Position */ 273 #define EIC_CONFIG0_SENSE6_LOW (EIC_CONFIG0_SENSE6_LOW_Val << EIC_CONFIG0_SENSE6_Pos) /* (EIC_CONFIG0) Low level detection Position */ 274 #define EIC_CONFIG0_FILTEN6_Pos _UINT32_(27) /* (EIC_CONFIG0) Filter Enable 6 Position */ 275 #define EIC_CONFIG0_FILTEN6_Msk (_UINT32_(0x1) << EIC_CONFIG0_FILTEN6_Pos) /* (EIC_CONFIG0) Filter Enable 6 Mask */ 276 #define EIC_CONFIG0_FILTEN6(value) (EIC_CONFIG0_FILTEN6_Msk & (_UINT32_(value) << EIC_CONFIG0_FILTEN6_Pos)) /* Assigment of value for FILTEN6 in the EIC_CONFIG0 register */ 277 #define EIC_CONFIG0_SENSE7_Pos _UINT32_(28) /* (EIC_CONFIG0) Input Sense Configuration 7 Position */ 278 #define EIC_CONFIG0_SENSE7_Msk (_UINT32_(0x7) << EIC_CONFIG0_SENSE7_Pos) /* (EIC_CONFIG0) Input Sense Configuration 7 Mask */ 279 #define EIC_CONFIG0_SENSE7(value) (EIC_CONFIG0_SENSE7_Msk & (_UINT32_(value) << EIC_CONFIG0_SENSE7_Pos)) /* Assigment of value for SENSE7 in the EIC_CONFIG0 register */ 280 #define EIC_CONFIG0_SENSE7_NONE_Val _UINT32_(0x0) /* (EIC_CONFIG0) No detection */ 281 #define EIC_CONFIG0_SENSE7_RISE_Val _UINT32_(0x1) /* (EIC_CONFIG0) Rising edge detection */ 282 #define EIC_CONFIG0_SENSE7_FALL_Val _UINT32_(0x2) /* (EIC_CONFIG0) Falling edge detection */ 283 #define EIC_CONFIG0_SENSE7_BOTH_Val _UINT32_(0x3) /* (EIC_CONFIG0) Both edges detection */ 284 #define EIC_CONFIG0_SENSE7_HIGH_Val _UINT32_(0x4) /* (EIC_CONFIG0) High level detection */ 285 #define EIC_CONFIG0_SENSE7_LOW_Val _UINT32_(0x5) /* (EIC_CONFIG0) Low level detection */ 286 #define EIC_CONFIG0_SENSE7_NONE (EIC_CONFIG0_SENSE7_NONE_Val << EIC_CONFIG0_SENSE7_Pos) /* (EIC_CONFIG0) No detection Position */ 287 #define EIC_CONFIG0_SENSE7_RISE (EIC_CONFIG0_SENSE7_RISE_Val << EIC_CONFIG0_SENSE7_Pos) /* (EIC_CONFIG0) Rising edge detection Position */ 288 #define EIC_CONFIG0_SENSE7_FALL (EIC_CONFIG0_SENSE7_FALL_Val << EIC_CONFIG0_SENSE7_Pos) /* (EIC_CONFIG0) Falling edge detection Position */ 289 #define EIC_CONFIG0_SENSE7_BOTH (EIC_CONFIG0_SENSE7_BOTH_Val << EIC_CONFIG0_SENSE7_Pos) /* (EIC_CONFIG0) Both edges detection Position */ 290 #define EIC_CONFIG0_SENSE7_HIGH (EIC_CONFIG0_SENSE7_HIGH_Val << EIC_CONFIG0_SENSE7_Pos) /* (EIC_CONFIG0) High level detection Position */ 291 #define EIC_CONFIG0_SENSE7_LOW (EIC_CONFIG0_SENSE7_LOW_Val << EIC_CONFIG0_SENSE7_Pos) /* (EIC_CONFIG0) Low level detection Position */ 292 #define EIC_CONFIG0_FILTEN7_Pos _UINT32_(31) /* (EIC_CONFIG0) Filter Enable 7 Position */ 293 #define EIC_CONFIG0_FILTEN7_Msk (_UINT32_(0x1) << EIC_CONFIG0_FILTEN7_Pos) /* (EIC_CONFIG0) Filter Enable 7 Mask */ 294 #define EIC_CONFIG0_FILTEN7(value) (EIC_CONFIG0_FILTEN7_Msk & (_UINT32_(value) << EIC_CONFIG0_FILTEN7_Pos)) /* Assigment of value for FILTEN7 in the EIC_CONFIG0 register */ 295 #define EIC_CONFIG0_Msk _UINT32_(0xFFFFFFFF) /* (EIC_CONFIG0) Register Mask */ 296 297 298 /* -------- EIC_CONFIG1 : (EIC Offset: 0x20) (R/W 32) External Interrupt Sense Configuration -------- */ 299 #define EIC_CONFIG1_RESETVALUE _UINT32_(0x00) /* (EIC_CONFIG1) External Interrupt Sense Configuration Reset Value */ 300 301 #define EIC_CONFIG1_SENSE8_Pos _UINT32_(0) /* (EIC_CONFIG1) Input Sense Configuration 8 Position */ 302 #define EIC_CONFIG1_SENSE8_Msk (_UINT32_(0x7) << EIC_CONFIG1_SENSE8_Pos) /* (EIC_CONFIG1) Input Sense Configuration 8 Mask */ 303 #define EIC_CONFIG1_SENSE8(value) (EIC_CONFIG1_SENSE8_Msk & (_UINT32_(value) << EIC_CONFIG1_SENSE8_Pos)) /* Assigment of value for SENSE8 in the EIC_CONFIG1 register */ 304 #define EIC_CONFIG1_SENSE8_NONE_Val _UINT32_(0x0) /* (EIC_CONFIG1) No detection */ 305 #define EIC_CONFIG1_SENSE8_RISE_Val _UINT32_(0x1) /* (EIC_CONFIG1) Rising edge detection */ 306 #define EIC_CONFIG1_SENSE8_FALL_Val _UINT32_(0x2) /* (EIC_CONFIG1) Falling edge detection */ 307 #define EIC_CONFIG1_SENSE8_BOTH_Val _UINT32_(0x3) /* (EIC_CONFIG1) Both edges detection */ 308 #define EIC_CONFIG1_SENSE8_HIGH_Val _UINT32_(0x4) /* (EIC_CONFIG1) High level detection */ 309 #define EIC_CONFIG1_SENSE8_LOW_Val _UINT32_(0x5) /* (EIC_CONFIG1) Low level detection */ 310 #define EIC_CONFIG1_SENSE8_NONE (EIC_CONFIG1_SENSE8_NONE_Val << EIC_CONFIG1_SENSE8_Pos) /* (EIC_CONFIG1) No detection Position */ 311 #define EIC_CONFIG1_SENSE8_RISE (EIC_CONFIG1_SENSE8_RISE_Val << EIC_CONFIG1_SENSE8_Pos) /* (EIC_CONFIG1) Rising edge detection Position */ 312 #define EIC_CONFIG1_SENSE8_FALL (EIC_CONFIG1_SENSE8_FALL_Val << EIC_CONFIG1_SENSE8_Pos) /* (EIC_CONFIG1) Falling edge detection Position */ 313 #define EIC_CONFIG1_SENSE8_BOTH (EIC_CONFIG1_SENSE8_BOTH_Val << EIC_CONFIG1_SENSE8_Pos) /* (EIC_CONFIG1) Both edges detection Position */ 314 #define EIC_CONFIG1_SENSE8_HIGH (EIC_CONFIG1_SENSE8_HIGH_Val << EIC_CONFIG1_SENSE8_Pos) /* (EIC_CONFIG1) High level detection Position */ 315 #define EIC_CONFIG1_SENSE8_LOW (EIC_CONFIG1_SENSE8_LOW_Val << EIC_CONFIG1_SENSE8_Pos) /* (EIC_CONFIG1) Low level detection Position */ 316 #define EIC_CONFIG1_FILTEN8_Pos _UINT32_(3) /* (EIC_CONFIG1) Filter Enable 8 Position */ 317 #define EIC_CONFIG1_FILTEN8_Msk (_UINT32_(0x1) << EIC_CONFIG1_FILTEN8_Pos) /* (EIC_CONFIG1) Filter Enable 8 Mask */ 318 #define EIC_CONFIG1_FILTEN8(value) (EIC_CONFIG1_FILTEN8_Msk & (_UINT32_(value) << EIC_CONFIG1_FILTEN8_Pos)) /* Assigment of value for FILTEN8 in the EIC_CONFIG1 register */ 319 #define EIC_CONFIG1_SENSE9_Pos _UINT32_(4) /* (EIC_CONFIG1) Input Sense Configuration 9 Position */ 320 #define EIC_CONFIG1_SENSE9_Msk (_UINT32_(0x7) << EIC_CONFIG1_SENSE9_Pos) /* (EIC_CONFIG1) Input Sense Configuration 9 Mask */ 321 #define EIC_CONFIG1_SENSE9(value) (EIC_CONFIG1_SENSE9_Msk & (_UINT32_(value) << EIC_CONFIG1_SENSE9_Pos)) /* Assigment of value for SENSE9 in the EIC_CONFIG1 register */ 322 #define EIC_CONFIG1_SENSE9_NONE_Val _UINT32_(0x0) /* (EIC_CONFIG1) No detection */ 323 #define EIC_CONFIG1_SENSE9_RISE_Val _UINT32_(0x1) /* (EIC_CONFIG1) Rising edge detection */ 324 #define EIC_CONFIG1_SENSE9_FALL_Val _UINT32_(0x2) /* (EIC_CONFIG1) Falling edge detection */ 325 #define EIC_CONFIG1_SENSE9_BOTH_Val _UINT32_(0x3) /* (EIC_CONFIG1) Both edges detection */ 326 #define EIC_CONFIG1_SENSE9_HIGH_Val _UINT32_(0x4) /* (EIC_CONFIG1) High level detection */ 327 #define EIC_CONFIG1_SENSE9_LOW_Val _UINT32_(0x5) /* (EIC_CONFIG1) Low level detection */ 328 #define EIC_CONFIG1_SENSE9_NONE (EIC_CONFIG1_SENSE9_NONE_Val << EIC_CONFIG1_SENSE9_Pos) /* (EIC_CONFIG1) No detection Position */ 329 #define EIC_CONFIG1_SENSE9_RISE (EIC_CONFIG1_SENSE9_RISE_Val << EIC_CONFIG1_SENSE9_Pos) /* (EIC_CONFIG1) Rising edge detection Position */ 330 #define EIC_CONFIG1_SENSE9_FALL (EIC_CONFIG1_SENSE9_FALL_Val << EIC_CONFIG1_SENSE9_Pos) /* (EIC_CONFIG1) Falling edge detection Position */ 331 #define EIC_CONFIG1_SENSE9_BOTH (EIC_CONFIG1_SENSE9_BOTH_Val << EIC_CONFIG1_SENSE9_Pos) /* (EIC_CONFIG1) Both edges detection Position */ 332 #define EIC_CONFIG1_SENSE9_HIGH (EIC_CONFIG1_SENSE9_HIGH_Val << EIC_CONFIG1_SENSE9_Pos) /* (EIC_CONFIG1) High level detection Position */ 333 #define EIC_CONFIG1_SENSE9_LOW (EIC_CONFIG1_SENSE9_LOW_Val << EIC_CONFIG1_SENSE9_Pos) /* (EIC_CONFIG1) Low level detection Position */ 334 #define EIC_CONFIG1_FILTEN9_Pos _UINT32_(7) /* (EIC_CONFIG1) Filter Enable 9 Position */ 335 #define EIC_CONFIG1_FILTEN9_Msk (_UINT32_(0x1) << EIC_CONFIG1_FILTEN9_Pos) /* (EIC_CONFIG1) Filter Enable 9 Mask */ 336 #define EIC_CONFIG1_FILTEN9(value) (EIC_CONFIG1_FILTEN9_Msk & (_UINT32_(value) << EIC_CONFIG1_FILTEN9_Pos)) /* Assigment of value for FILTEN9 in the EIC_CONFIG1 register */ 337 #define EIC_CONFIG1_SENSE10_Pos _UINT32_(8) /* (EIC_CONFIG1) Input Sense Configuration 10 Position */ 338 #define EIC_CONFIG1_SENSE10_Msk (_UINT32_(0x7) << EIC_CONFIG1_SENSE10_Pos) /* (EIC_CONFIG1) Input Sense Configuration 10 Mask */ 339 #define EIC_CONFIG1_SENSE10(value) (EIC_CONFIG1_SENSE10_Msk & (_UINT32_(value) << EIC_CONFIG1_SENSE10_Pos)) /* Assigment of value for SENSE10 in the EIC_CONFIG1 register */ 340 #define EIC_CONFIG1_SENSE10_NONE_Val _UINT32_(0x0) /* (EIC_CONFIG1) No detection */ 341 #define EIC_CONFIG1_SENSE10_RISE_Val _UINT32_(0x1) /* (EIC_CONFIG1) Rising edge detection */ 342 #define EIC_CONFIG1_SENSE10_FALL_Val _UINT32_(0x2) /* (EIC_CONFIG1) Falling edge detection */ 343 #define EIC_CONFIG1_SENSE10_BOTH_Val _UINT32_(0x3) /* (EIC_CONFIG1) Both edges detection */ 344 #define EIC_CONFIG1_SENSE10_HIGH_Val _UINT32_(0x4) /* (EIC_CONFIG1) High level detection */ 345 #define EIC_CONFIG1_SENSE10_LOW_Val _UINT32_(0x5) /* (EIC_CONFIG1) Low level detection */ 346 #define EIC_CONFIG1_SENSE10_NONE (EIC_CONFIG1_SENSE10_NONE_Val << EIC_CONFIG1_SENSE10_Pos) /* (EIC_CONFIG1) No detection Position */ 347 #define EIC_CONFIG1_SENSE10_RISE (EIC_CONFIG1_SENSE10_RISE_Val << EIC_CONFIG1_SENSE10_Pos) /* (EIC_CONFIG1) Rising edge detection Position */ 348 #define EIC_CONFIG1_SENSE10_FALL (EIC_CONFIG1_SENSE10_FALL_Val << EIC_CONFIG1_SENSE10_Pos) /* (EIC_CONFIG1) Falling edge detection Position */ 349 #define EIC_CONFIG1_SENSE10_BOTH (EIC_CONFIG1_SENSE10_BOTH_Val << EIC_CONFIG1_SENSE10_Pos) /* (EIC_CONFIG1) Both edges detection Position */ 350 #define EIC_CONFIG1_SENSE10_HIGH (EIC_CONFIG1_SENSE10_HIGH_Val << EIC_CONFIG1_SENSE10_Pos) /* (EIC_CONFIG1) High level detection Position */ 351 #define EIC_CONFIG1_SENSE10_LOW (EIC_CONFIG1_SENSE10_LOW_Val << EIC_CONFIG1_SENSE10_Pos) /* (EIC_CONFIG1) Low level detection Position */ 352 #define EIC_CONFIG1_FILTEN10_Pos _UINT32_(11) /* (EIC_CONFIG1) Filter Enable 10 Position */ 353 #define EIC_CONFIG1_FILTEN10_Msk (_UINT32_(0x1) << EIC_CONFIG1_FILTEN10_Pos) /* (EIC_CONFIG1) Filter Enable 10 Mask */ 354 #define EIC_CONFIG1_FILTEN10(value) (EIC_CONFIG1_FILTEN10_Msk & (_UINT32_(value) << EIC_CONFIG1_FILTEN10_Pos)) /* Assigment of value for FILTEN10 in the EIC_CONFIG1 register */ 355 #define EIC_CONFIG1_SENSE11_Pos _UINT32_(12) /* (EIC_CONFIG1) Input Sense Configuration 11 Position */ 356 #define EIC_CONFIG1_SENSE11_Msk (_UINT32_(0x7) << EIC_CONFIG1_SENSE11_Pos) /* (EIC_CONFIG1) Input Sense Configuration 11 Mask */ 357 #define EIC_CONFIG1_SENSE11(value) (EIC_CONFIG1_SENSE11_Msk & (_UINT32_(value) << EIC_CONFIG1_SENSE11_Pos)) /* Assigment of value for SENSE11 in the EIC_CONFIG1 register */ 358 #define EIC_CONFIG1_SENSE11_NONE_Val _UINT32_(0x0) /* (EIC_CONFIG1) No detection */ 359 #define EIC_CONFIG1_SENSE11_RISE_Val _UINT32_(0x1) /* (EIC_CONFIG1) Rising edge detection */ 360 #define EIC_CONFIG1_SENSE11_FALL_Val _UINT32_(0x2) /* (EIC_CONFIG1) Falling edge detection */ 361 #define EIC_CONFIG1_SENSE11_BOTH_Val _UINT32_(0x3) /* (EIC_CONFIG1) Both edges detection */ 362 #define EIC_CONFIG1_SENSE11_HIGH_Val _UINT32_(0x4) /* (EIC_CONFIG1) High level detection */ 363 #define EIC_CONFIG1_SENSE11_LOW_Val _UINT32_(0x5) /* (EIC_CONFIG1) Low level detection */ 364 #define EIC_CONFIG1_SENSE11_NONE (EIC_CONFIG1_SENSE11_NONE_Val << EIC_CONFIG1_SENSE11_Pos) /* (EIC_CONFIG1) No detection Position */ 365 #define EIC_CONFIG1_SENSE11_RISE (EIC_CONFIG1_SENSE11_RISE_Val << EIC_CONFIG1_SENSE11_Pos) /* (EIC_CONFIG1) Rising edge detection Position */ 366 #define EIC_CONFIG1_SENSE11_FALL (EIC_CONFIG1_SENSE11_FALL_Val << EIC_CONFIG1_SENSE11_Pos) /* (EIC_CONFIG1) Falling edge detection Position */ 367 #define EIC_CONFIG1_SENSE11_BOTH (EIC_CONFIG1_SENSE11_BOTH_Val << EIC_CONFIG1_SENSE11_Pos) /* (EIC_CONFIG1) Both edges detection Position */ 368 #define EIC_CONFIG1_SENSE11_HIGH (EIC_CONFIG1_SENSE11_HIGH_Val << EIC_CONFIG1_SENSE11_Pos) /* (EIC_CONFIG1) High level detection Position */ 369 #define EIC_CONFIG1_SENSE11_LOW (EIC_CONFIG1_SENSE11_LOW_Val << EIC_CONFIG1_SENSE11_Pos) /* (EIC_CONFIG1) Low level detection Position */ 370 #define EIC_CONFIG1_FILTEN11_Pos _UINT32_(15) /* (EIC_CONFIG1) Filter Enable 11 Position */ 371 #define EIC_CONFIG1_FILTEN11_Msk (_UINT32_(0x1) << EIC_CONFIG1_FILTEN11_Pos) /* (EIC_CONFIG1) Filter Enable 11 Mask */ 372 #define EIC_CONFIG1_FILTEN11(value) (EIC_CONFIG1_FILTEN11_Msk & (_UINT32_(value) << EIC_CONFIG1_FILTEN11_Pos)) /* Assigment of value for FILTEN11 in the EIC_CONFIG1 register */ 373 #define EIC_CONFIG1_SENSE12_Pos _UINT32_(16) /* (EIC_CONFIG1) Input Sense Configuration 12 Position */ 374 #define EIC_CONFIG1_SENSE12_Msk (_UINT32_(0x7) << EIC_CONFIG1_SENSE12_Pos) /* (EIC_CONFIG1) Input Sense Configuration 12 Mask */ 375 #define EIC_CONFIG1_SENSE12(value) (EIC_CONFIG1_SENSE12_Msk & (_UINT32_(value) << EIC_CONFIG1_SENSE12_Pos)) /* Assigment of value for SENSE12 in the EIC_CONFIG1 register */ 376 #define EIC_CONFIG1_SENSE12_NONE_Val _UINT32_(0x0) /* (EIC_CONFIG1) No detection */ 377 #define EIC_CONFIG1_SENSE12_RISE_Val _UINT32_(0x1) /* (EIC_CONFIG1) Rising edge detection */ 378 #define EIC_CONFIG1_SENSE12_FALL_Val _UINT32_(0x2) /* (EIC_CONFIG1) Falling edge detection */ 379 #define EIC_CONFIG1_SENSE12_BOTH_Val _UINT32_(0x3) /* (EIC_CONFIG1) Both edges detection */ 380 #define EIC_CONFIG1_SENSE12_HIGH_Val _UINT32_(0x4) /* (EIC_CONFIG1) High level detection */ 381 #define EIC_CONFIG1_SENSE12_LOW_Val _UINT32_(0x5) /* (EIC_CONFIG1) Low level detection */ 382 #define EIC_CONFIG1_SENSE12_NONE (EIC_CONFIG1_SENSE12_NONE_Val << EIC_CONFIG1_SENSE12_Pos) /* (EIC_CONFIG1) No detection Position */ 383 #define EIC_CONFIG1_SENSE12_RISE (EIC_CONFIG1_SENSE12_RISE_Val << EIC_CONFIG1_SENSE12_Pos) /* (EIC_CONFIG1) Rising edge detection Position */ 384 #define EIC_CONFIG1_SENSE12_FALL (EIC_CONFIG1_SENSE12_FALL_Val << EIC_CONFIG1_SENSE12_Pos) /* (EIC_CONFIG1) Falling edge detection Position */ 385 #define EIC_CONFIG1_SENSE12_BOTH (EIC_CONFIG1_SENSE12_BOTH_Val << EIC_CONFIG1_SENSE12_Pos) /* (EIC_CONFIG1) Both edges detection Position */ 386 #define EIC_CONFIG1_SENSE12_HIGH (EIC_CONFIG1_SENSE12_HIGH_Val << EIC_CONFIG1_SENSE12_Pos) /* (EIC_CONFIG1) High level detection Position */ 387 #define EIC_CONFIG1_SENSE12_LOW (EIC_CONFIG1_SENSE12_LOW_Val << EIC_CONFIG1_SENSE12_Pos) /* (EIC_CONFIG1) Low level detection Position */ 388 #define EIC_CONFIG1_FILTEN12_Pos _UINT32_(19) /* (EIC_CONFIG1) Filter Enable 12 Position */ 389 #define EIC_CONFIG1_FILTEN12_Msk (_UINT32_(0x1) << EIC_CONFIG1_FILTEN12_Pos) /* (EIC_CONFIG1) Filter Enable 12 Mask */ 390 #define EIC_CONFIG1_FILTEN12(value) (EIC_CONFIG1_FILTEN12_Msk & (_UINT32_(value) << EIC_CONFIG1_FILTEN12_Pos)) /* Assigment of value for FILTEN12 in the EIC_CONFIG1 register */ 391 #define EIC_CONFIG1_SENSE13_Pos _UINT32_(20) /* (EIC_CONFIG1) Input Sense Configuration 13 Position */ 392 #define EIC_CONFIG1_SENSE13_Msk (_UINT32_(0x7) << EIC_CONFIG1_SENSE13_Pos) /* (EIC_CONFIG1) Input Sense Configuration 13 Mask */ 393 #define EIC_CONFIG1_SENSE13(value) (EIC_CONFIG1_SENSE13_Msk & (_UINT32_(value) << EIC_CONFIG1_SENSE13_Pos)) /* Assigment of value for SENSE13 in the EIC_CONFIG1 register */ 394 #define EIC_CONFIG1_SENSE13_NONE_Val _UINT32_(0x0) /* (EIC_CONFIG1) No detection */ 395 #define EIC_CONFIG1_SENSE13_RISE_Val _UINT32_(0x1) /* (EIC_CONFIG1) Rising edge detection */ 396 #define EIC_CONFIG1_SENSE13_FALL_Val _UINT32_(0x2) /* (EIC_CONFIG1) Falling edge detection */ 397 #define EIC_CONFIG1_SENSE13_BOTH_Val _UINT32_(0x3) /* (EIC_CONFIG1) Both edges detection */ 398 #define EIC_CONFIG1_SENSE13_HIGH_Val _UINT32_(0x4) /* (EIC_CONFIG1) High level detection */ 399 #define EIC_CONFIG1_SENSE13_LOW_Val _UINT32_(0x5) /* (EIC_CONFIG1) Low level detection */ 400 #define EIC_CONFIG1_SENSE13_NONE (EIC_CONFIG1_SENSE13_NONE_Val << EIC_CONFIG1_SENSE13_Pos) /* (EIC_CONFIG1) No detection Position */ 401 #define EIC_CONFIG1_SENSE13_RISE (EIC_CONFIG1_SENSE13_RISE_Val << EIC_CONFIG1_SENSE13_Pos) /* (EIC_CONFIG1) Rising edge detection Position */ 402 #define EIC_CONFIG1_SENSE13_FALL (EIC_CONFIG1_SENSE13_FALL_Val << EIC_CONFIG1_SENSE13_Pos) /* (EIC_CONFIG1) Falling edge detection Position */ 403 #define EIC_CONFIG1_SENSE13_BOTH (EIC_CONFIG1_SENSE13_BOTH_Val << EIC_CONFIG1_SENSE13_Pos) /* (EIC_CONFIG1) Both edges detection Position */ 404 #define EIC_CONFIG1_SENSE13_HIGH (EIC_CONFIG1_SENSE13_HIGH_Val << EIC_CONFIG1_SENSE13_Pos) /* (EIC_CONFIG1) High level detection Position */ 405 #define EIC_CONFIG1_SENSE13_LOW (EIC_CONFIG1_SENSE13_LOW_Val << EIC_CONFIG1_SENSE13_Pos) /* (EIC_CONFIG1) Low level detection Position */ 406 #define EIC_CONFIG1_FILTEN13_Pos _UINT32_(23) /* (EIC_CONFIG1) Filter Enable 13 Position */ 407 #define EIC_CONFIG1_FILTEN13_Msk (_UINT32_(0x1) << EIC_CONFIG1_FILTEN13_Pos) /* (EIC_CONFIG1) Filter Enable 13 Mask */ 408 #define EIC_CONFIG1_FILTEN13(value) (EIC_CONFIG1_FILTEN13_Msk & (_UINT32_(value) << EIC_CONFIG1_FILTEN13_Pos)) /* Assigment of value for FILTEN13 in the EIC_CONFIG1 register */ 409 #define EIC_CONFIG1_SENSE14_Pos _UINT32_(24) /* (EIC_CONFIG1) Input Sense Configuration 14 Position */ 410 #define EIC_CONFIG1_SENSE14_Msk (_UINT32_(0x7) << EIC_CONFIG1_SENSE14_Pos) /* (EIC_CONFIG1) Input Sense Configuration 14 Mask */ 411 #define EIC_CONFIG1_SENSE14(value) (EIC_CONFIG1_SENSE14_Msk & (_UINT32_(value) << EIC_CONFIG1_SENSE14_Pos)) /* Assigment of value for SENSE14 in the EIC_CONFIG1 register */ 412 #define EIC_CONFIG1_SENSE14_NONE_Val _UINT32_(0x0) /* (EIC_CONFIG1) No detection */ 413 #define EIC_CONFIG1_SENSE14_RISE_Val _UINT32_(0x1) /* (EIC_CONFIG1) Rising edge detection */ 414 #define EIC_CONFIG1_SENSE14_FALL_Val _UINT32_(0x2) /* (EIC_CONFIG1) Falling edge detection */ 415 #define EIC_CONFIG1_SENSE14_BOTH_Val _UINT32_(0x3) /* (EIC_CONFIG1) Both edges detection */ 416 #define EIC_CONFIG1_SENSE14_HIGH_Val _UINT32_(0x4) /* (EIC_CONFIG1) High level detection */ 417 #define EIC_CONFIG1_SENSE14_LOW_Val _UINT32_(0x5) /* (EIC_CONFIG1) Low level detection */ 418 #define EIC_CONFIG1_SENSE14_NONE (EIC_CONFIG1_SENSE14_NONE_Val << EIC_CONFIG1_SENSE14_Pos) /* (EIC_CONFIG1) No detection Position */ 419 #define EIC_CONFIG1_SENSE14_RISE (EIC_CONFIG1_SENSE14_RISE_Val << EIC_CONFIG1_SENSE14_Pos) /* (EIC_CONFIG1) Rising edge detection Position */ 420 #define EIC_CONFIG1_SENSE14_FALL (EIC_CONFIG1_SENSE14_FALL_Val << EIC_CONFIG1_SENSE14_Pos) /* (EIC_CONFIG1) Falling edge detection Position */ 421 #define EIC_CONFIG1_SENSE14_BOTH (EIC_CONFIG1_SENSE14_BOTH_Val << EIC_CONFIG1_SENSE14_Pos) /* (EIC_CONFIG1) Both edges detection Position */ 422 #define EIC_CONFIG1_SENSE14_HIGH (EIC_CONFIG1_SENSE14_HIGH_Val << EIC_CONFIG1_SENSE14_Pos) /* (EIC_CONFIG1) High level detection Position */ 423 #define EIC_CONFIG1_SENSE14_LOW (EIC_CONFIG1_SENSE14_LOW_Val << EIC_CONFIG1_SENSE14_Pos) /* (EIC_CONFIG1) Low level detection Position */ 424 #define EIC_CONFIG1_FILTEN14_Pos _UINT32_(27) /* (EIC_CONFIG1) Filter Enable 14 Position */ 425 #define EIC_CONFIG1_FILTEN14_Msk (_UINT32_(0x1) << EIC_CONFIG1_FILTEN14_Pos) /* (EIC_CONFIG1) Filter Enable 14 Mask */ 426 #define EIC_CONFIG1_FILTEN14(value) (EIC_CONFIG1_FILTEN14_Msk & (_UINT32_(value) << EIC_CONFIG1_FILTEN14_Pos)) /* Assigment of value for FILTEN14 in the EIC_CONFIG1 register */ 427 #define EIC_CONFIG1_SENSE15_Pos _UINT32_(28) /* (EIC_CONFIG1) Input Sense Configuration 15 Position */ 428 #define EIC_CONFIG1_SENSE15_Msk (_UINT32_(0x7) << EIC_CONFIG1_SENSE15_Pos) /* (EIC_CONFIG1) Input Sense Configuration 15 Mask */ 429 #define EIC_CONFIG1_SENSE15(value) (EIC_CONFIG1_SENSE15_Msk & (_UINT32_(value) << EIC_CONFIG1_SENSE15_Pos)) /* Assigment of value for SENSE15 in the EIC_CONFIG1 register */ 430 #define EIC_CONFIG1_SENSE15_NONE_Val _UINT32_(0x0) /* (EIC_CONFIG1) No detection */ 431 #define EIC_CONFIG1_SENSE15_RISE_Val _UINT32_(0x1) /* (EIC_CONFIG1) Rising edge detection */ 432 #define EIC_CONFIG1_SENSE15_FALL_Val _UINT32_(0x2) /* (EIC_CONFIG1) Falling edge detection */ 433 #define EIC_CONFIG1_SENSE15_BOTH_Val _UINT32_(0x3) /* (EIC_CONFIG1) Both edges detection */ 434 #define EIC_CONFIG1_SENSE15_HIGH_Val _UINT32_(0x4) /* (EIC_CONFIG1) High level detection */ 435 #define EIC_CONFIG1_SENSE15_LOW_Val _UINT32_(0x5) /* (EIC_CONFIG1) Low level detection */ 436 #define EIC_CONFIG1_SENSE15_NONE (EIC_CONFIG1_SENSE15_NONE_Val << EIC_CONFIG1_SENSE15_Pos) /* (EIC_CONFIG1) No detection Position */ 437 #define EIC_CONFIG1_SENSE15_RISE (EIC_CONFIG1_SENSE15_RISE_Val << EIC_CONFIG1_SENSE15_Pos) /* (EIC_CONFIG1) Rising edge detection Position */ 438 #define EIC_CONFIG1_SENSE15_FALL (EIC_CONFIG1_SENSE15_FALL_Val << EIC_CONFIG1_SENSE15_Pos) /* (EIC_CONFIG1) Falling edge detection Position */ 439 #define EIC_CONFIG1_SENSE15_BOTH (EIC_CONFIG1_SENSE15_BOTH_Val << EIC_CONFIG1_SENSE15_Pos) /* (EIC_CONFIG1) Both edges detection Position */ 440 #define EIC_CONFIG1_SENSE15_HIGH (EIC_CONFIG1_SENSE15_HIGH_Val << EIC_CONFIG1_SENSE15_Pos) /* (EIC_CONFIG1) High level detection Position */ 441 #define EIC_CONFIG1_SENSE15_LOW (EIC_CONFIG1_SENSE15_LOW_Val << EIC_CONFIG1_SENSE15_Pos) /* (EIC_CONFIG1) Low level detection Position */ 442 #define EIC_CONFIG1_FILTEN15_Pos _UINT32_(31) /* (EIC_CONFIG1) Filter Enable 15 Position */ 443 #define EIC_CONFIG1_FILTEN15_Msk (_UINT32_(0x1) << EIC_CONFIG1_FILTEN15_Pos) /* (EIC_CONFIG1) Filter Enable 15 Mask */ 444 #define EIC_CONFIG1_FILTEN15(value) (EIC_CONFIG1_FILTEN15_Msk & (_UINT32_(value) << EIC_CONFIG1_FILTEN15_Pos)) /* Assigment of value for FILTEN15 in the EIC_CONFIG1 register */ 445 #define EIC_CONFIG1_Msk _UINT32_(0xFFFFFFFF) /* (EIC_CONFIG1) Register Mask */ 446 447 448 /* -------- EIC_DEBOUNCEN : (EIC Offset: 0x30) (R/W 32) Debouncer Enable -------- */ 449 #define EIC_DEBOUNCEN_RESETVALUE _UINT32_(0x00) /* (EIC_DEBOUNCEN) Debouncer Enable Reset Value */ 450 451 #define EIC_DEBOUNCEN_DEBOUNCEN_Pos _UINT32_(0) /* (EIC_DEBOUNCEN) Debouncer Enable Position */ 452 #define EIC_DEBOUNCEN_DEBOUNCEN_Msk (_UINT32_(0xFFFF) << EIC_DEBOUNCEN_DEBOUNCEN_Pos) /* (EIC_DEBOUNCEN) Debouncer Enable Mask */ 453 #define EIC_DEBOUNCEN_DEBOUNCEN(value) (EIC_DEBOUNCEN_DEBOUNCEN_Msk & (_UINT32_(value) << EIC_DEBOUNCEN_DEBOUNCEN_Pos)) /* Assigment of value for DEBOUNCEN in the EIC_DEBOUNCEN register */ 454 #define EIC_DEBOUNCEN_Msk _UINT32_(0x0000FFFF) /* (EIC_DEBOUNCEN) Register Mask */ 455 456 457 /* -------- EIC_DPRESCALER : (EIC Offset: 0x34) (R/W 32) Debouncer Prescaler -------- */ 458 #define EIC_DPRESCALER_RESETVALUE _UINT32_(0x00) /* (EIC_DPRESCALER) Debouncer Prescaler Reset Value */ 459 460 #define EIC_DPRESCALER_PRESCALER0_Pos _UINT32_(0) /* (EIC_DPRESCALER) Debouncer Prescaler Position */ 461 #define EIC_DPRESCALER_PRESCALER0_Msk (_UINT32_(0x7) << EIC_DPRESCALER_PRESCALER0_Pos) /* (EIC_DPRESCALER) Debouncer Prescaler Mask */ 462 #define EIC_DPRESCALER_PRESCALER0(value) (EIC_DPRESCALER_PRESCALER0_Msk & (_UINT32_(value) << EIC_DPRESCALER_PRESCALER0_Pos)) /* Assigment of value for PRESCALER0 in the EIC_DPRESCALER register */ 463 #define EIC_DPRESCALER_PRESCALER0_DIV2_Val _UINT32_(0x0) /* (EIC_DPRESCALER) EIC clock divided by 2 */ 464 #define EIC_DPRESCALER_PRESCALER0_DIV4_Val _UINT32_(0x1) /* (EIC_DPRESCALER) EIC clock divided by 4 */ 465 #define EIC_DPRESCALER_PRESCALER0_DIV8_Val _UINT32_(0x2) /* (EIC_DPRESCALER) EIC clock divided by 8 */ 466 #define EIC_DPRESCALER_PRESCALER0_DIV16_Val _UINT32_(0x3) /* (EIC_DPRESCALER) EIC clock divided by 16 */ 467 #define EIC_DPRESCALER_PRESCALER0_DIV32_Val _UINT32_(0x4) /* (EIC_DPRESCALER) EIC clock divided by 32 */ 468 #define EIC_DPRESCALER_PRESCALER0_DIV64_Val _UINT32_(0x5) /* (EIC_DPRESCALER) EIC clock divided by 64 */ 469 #define EIC_DPRESCALER_PRESCALER0_DIV128_Val _UINT32_(0x6) /* (EIC_DPRESCALER) EIC clock divided by 128 */ 470 #define EIC_DPRESCALER_PRESCALER0_DIV256_Val _UINT32_(0x7) /* (EIC_DPRESCALER) EIC clock divided by 256 */ 471 #define EIC_DPRESCALER_PRESCALER0_DIV2 (EIC_DPRESCALER_PRESCALER0_DIV2_Val << EIC_DPRESCALER_PRESCALER0_Pos) /* (EIC_DPRESCALER) EIC clock divided by 2 Position */ 472 #define EIC_DPRESCALER_PRESCALER0_DIV4 (EIC_DPRESCALER_PRESCALER0_DIV4_Val << EIC_DPRESCALER_PRESCALER0_Pos) /* (EIC_DPRESCALER) EIC clock divided by 4 Position */ 473 #define EIC_DPRESCALER_PRESCALER0_DIV8 (EIC_DPRESCALER_PRESCALER0_DIV8_Val << EIC_DPRESCALER_PRESCALER0_Pos) /* (EIC_DPRESCALER) EIC clock divided by 8 Position */ 474 #define EIC_DPRESCALER_PRESCALER0_DIV16 (EIC_DPRESCALER_PRESCALER0_DIV16_Val << EIC_DPRESCALER_PRESCALER0_Pos) /* (EIC_DPRESCALER) EIC clock divided by 16 Position */ 475 #define EIC_DPRESCALER_PRESCALER0_DIV32 (EIC_DPRESCALER_PRESCALER0_DIV32_Val << EIC_DPRESCALER_PRESCALER0_Pos) /* (EIC_DPRESCALER) EIC clock divided by 32 Position */ 476 #define EIC_DPRESCALER_PRESCALER0_DIV64 (EIC_DPRESCALER_PRESCALER0_DIV64_Val << EIC_DPRESCALER_PRESCALER0_Pos) /* (EIC_DPRESCALER) EIC clock divided by 64 Position */ 477 #define EIC_DPRESCALER_PRESCALER0_DIV128 (EIC_DPRESCALER_PRESCALER0_DIV128_Val << EIC_DPRESCALER_PRESCALER0_Pos) /* (EIC_DPRESCALER) EIC clock divided by 128 Position */ 478 #define EIC_DPRESCALER_PRESCALER0_DIV256 (EIC_DPRESCALER_PRESCALER0_DIV256_Val << EIC_DPRESCALER_PRESCALER0_Pos) /* (EIC_DPRESCALER) EIC clock divided by 256 Position */ 479 #define EIC_DPRESCALER_STATES0_Pos _UINT32_(3) /* (EIC_DPRESCALER) Debouncer number of states Position */ 480 #define EIC_DPRESCALER_STATES0_Msk (_UINT32_(0x1) << EIC_DPRESCALER_STATES0_Pos) /* (EIC_DPRESCALER) Debouncer number of states Mask */ 481 #define EIC_DPRESCALER_STATES0(value) (EIC_DPRESCALER_STATES0_Msk & (_UINT32_(value) << EIC_DPRESCALER_STATES0_Pos)) /* Assigment of value for STATES0 in the EIC_DPRESCALER register */ 482 #define EIC_DPRESCALER_STATES0_LFREQ3_Val _UINT32_(0x0) /* (EIC_DPRESCALER) 3 low frequency samples */ 483 #define EIC_DPRESCALER_STATES0_LFREQ7_Val _UINT32_(0x1) /* (EIC_DPRESCALER) 7 low frequency samples */ 484 #define EIC_DPRESCALER_STATES0_LFREQ3 (EIC_DPRESCALER_STATES0_LFREQ3_Val << EIC_DPRESCALER_STATES0_Pos) /* (EIC_DPRESCALER) 3 low frequency samples Position */ 485 #define EIC_DPRESCALER_STATES0_LFREQ7 (EIC_DPRESCALER_STATES0_LFREQ7_Val << EIC_DPRESCALER_STATES0_Pos) /* (EIC_DPRESCALER) 7 low frequency samples Position */ 486 #define EIC_DPRESCALER_PRESCALER1_Pos _UINT32_(4) /* (EIC_DPRESCALER) Debouncer Prescaler Position */ 487 #define EIC_DPRESCALER_PRESCALER1_Msk (_UINT32_(0x7) << EIC_DPRESCALER_PRESCALER1_Pos) /* (EIC_DPRESCALER) Debouncer Prescaler Mask */ 488 #define EIC_DPRESCALER_PRESCALER1(value) (EIC_DPRESCALER_PRESCALER1_Msk & (_UINT32_(value) << EIC_DPRESCALER_PRESCALER1_Pos)) /* Assigment of value for PRESCALER1 in the EIC_DPRESCALER register */ 489 #define EIC_DPRESCALER_PRESCALER1_DIV2_Val _UINT32_(0x0) /* (EIC_DPRESCALER) EIC clock divided by 2 */ 490 #define EIC_DPRESCALER_PRESCALER1_DIV4_Val _UINT32_(0x1) /* (EIC_DPRESCALER) EIC clock divided by 4 */ 491 #define EIC_DPRESCALER_PRESCALER1_DIV8_Val _UINT32_(0x2) /* (EIC_DPRESCALER) EIC clock divided by 8 */ 492 #define EIC_DPRESCALER_PRESCALER1_DIV16_Val _UINT32_(0x3) /* (EIC_DPRESCALER) EIC clock divided by 16 */ 493 #define EIC_DPRESCALER_PRESCALER1_DIV32_Val _UINT32_(0x4) /* (EIC_DPRESCALER) EIC clock divided by 32 */ 494 #define EIC_DPRESCALER_PRESCALER1_DIV64_Val _UINT32_(0x5) /* (EIC_DPRESCALER) EIC clock divided by 64 */ 495 #define EIC_DPRESCALER_PRESCALER1_DIV128_Val _UINT32_(0x6) /* (EIC_DPRESCALER) EIC clock divided by 128 */ 496 #define EIC_DPRESCALER_PRESCALER1_DIV256_Val _UINT32_(0x7) /* (EIC_DPRESCALER) EIC clock divided by 256 */ 497 #define EIC_DPRESCALER_PRESCALER1_DIV2 (EIC_DPRESCALER_PRESCALER1_DIV2_Val << EIC_DPRESCALER_PRESCALER1_Pos) /* (EIC_DPRESCALER) EIC clock divided by 2 Position */ 498 #define EIC_DPRESCALER_PRESCALER1_DIV4 (EIC_DPRESCALER_PRESCALER1_DIV4_Val << EIC_DPRESCALER_PRESCALER1_Pos) /* (EIC_DPRESCALER) EIC clock divided by 4 Position */ 499 #define EIC_DPRESCALER_PRESCALER1_DIV8 (EIC_DPRESCALER_PRESCALER1_DIV8_Val << EIC_DPRESCALER_PRESCALER1_Pos) /* (EIC_DPRESCALER) EIC clock divided by 8 Position */ 500 #define EIC_DPRESCALER_PRESCALER1_DIV16 (EIC_DPRESCALER_PRESCALER1_DIV16_Val << EIC_DPRESCALER_PRESCALER1_Pos) /* (EIC_DPRESCALER) EIC clock divided by 16 Position */ 501 #define EIC_DPRESCALER_PRESCALER1_DIV32 (EIC_DPRESCALER_PRESCALER1_DIV32_Val << EIC_DPRESCALER_PRESCALER1_Pos) /* (EIC_DPRESCALER) EIC clock divided by 32 Position */ 502 #define EIC_DPRESCALER_PRESCALER1_DIV64 (EIC_DPRESCALER_PRESCALER1_DIV64_Val << EIC_DPRESCALER_PRESCALER1_Pos) /* (EIC_DPRESCALER) EIC clock divided by 64 Position */ 503 #define EIC_DPRESCALER_PRESCALER1_DIV128 (EIC_DPRESCALER_PRESCALER1_DIV128_Val << EIC_DPRESCALER_PRESCALER1_Pos) /* (EIC_DPRESCALER) EIC clock divided by 128 Position */ 504 #define EIC_DPRESCALER_PRESCALER1_DIV256 (EIC_DPRESCALER_PRESCALER1_DIV256_Val << EIC_DPRESCALER_PRESCALER1_Pos) /* (EIC_DPRESCALER) EIC clock divided by 256 Position */ 505 #define EIC_DPRESCALER_STATES1_Pos _UINT32_(7) /* (EIC_DPRESCALER) Debouncer number of states Position */ 506 #define EIC_DPRESCALER_STATES1_Msk (_UINT32_(0x1) << EIC_DPRESCALER_STATES1_Pos) /* (EIC_DPRESCALER) Debouncer number of states Mask */ 507 #define EIC_DPRESCALER_STATES1(value) (EIC_DPRESCALER_STATES1_Msk & (_UINT32_(value) << EIC_DPRESCALER_STATES1_Pos)) /* Assigment of value for STATES1 in the EIC_DPRESCALER register */ 508 #define EIC_DPRESCALER_STATES1_LFREQ3_Val _UINT32_(0x0) /* (EIC_DPRESCALER) 3 low frequency samples */ 509 #define EIC_DPRESCALER_STATES1_LFREQ7_Val _UINT32_(0x1) /* (EIC_DPRESCALER) 7 low frequency samples */ 510 #define EIC_DPRESCALER_STATES1_LFREQ3 (EIC_DPRESCALER_STATES1_LFREQ3_Val << EIC_DPRESCALER_STATES1_Pos) /* (EIC_DPRESCALER) 3 low frequency samples Position */ 511 #define EIC_DPRESCALER_STATES1_LFREQ7 (EIC_DPRESCALER_STATES1_LFREQ7_Val << EIC_DPRESCALER_STATES1_Pos) /* (EIC_DPRESCALER) 7 low frequency samples Position */ 512 #define EIC_DPRESCALER_TICKON_Pos _UINT32_(16) /* (EIC_DPRESCALER) Pin Sampler frequency selection Position */ 513 #define EIC_DPRESCALER_TICKON_Msk (_UINT32_(0x1) << EIC_DPRESCALER_TICKON_Pos) /* (EIC_DPRESCALER) Pin Sampler frequency selection Mask */ 514 #define EIC_DPRESCALER_TICKON(value) (EIC_DPRESCALER_TICKON_Msk & (_UINT32_(value) << EIC_DPRESCALER_TICKON_Pos)) /* Assigment of value for TICKON in the EIC_DPRESCALER register */ 515 #define EIC_DPRESCALER_TICKON_CLK_GCLK_EIC_Val _UINT32_(0x0) /* (EIC_DPRESCALER) Clocked by GCLK */ 516 #define EIC_DPRESCALER_TICKON_CLK_LFREQ_Val _UINT32_(0x1) /* (EIC_DPRESCALER) Clocked by Low Frequency Clock */ 517 #define EIC_DPRESCALER_TICKON_CLK_GCLK_EIC (EIC_DPRESCALER_TICKON_CLK_GCLK_EIC_Val << EIC_DPRESCALER_TICKON_Pos) /* (EIC_DPRESCALER) Clocked by GCLK Position */ 518 #define EIC_DPRESCALER_TICKON_CLK_LFREQ (EIC_DPRESCALER_TICKON_CLK_LFREQ_Val << EIC_DPRESCALER_TICKON_Pos) /* (EIC_DPRESCALER) Clocked by Low Frequency Clock Position */ 519 #define EIC_DPRESCALER_Msk _UINT32_(0x000100FF) /* (EIC_DPRESCALER) Register Mask */ 520 521 522 /* -------- EIC_PINSTATE : (EIC Offset: 0x38) ( R/ 32) Pin State -------- */ 523 #define EIC_PINSTATE_RESETVALUE _UINT32_(0x00) /* (EIC_PINSTATE) Pin State Reset Value */ 524 525 #define EIC_PINSTATE_PINSTATE_Pos _UINT32_(0) /* (EIC_PINSTATE) Pin State Position */ 526 #define EIC_PINSTATE_PINSTATE_Msk (_UINT32_(0xFFFF) << EIC_PINSTATE_PINSTATE_Pos) /* (EIC_PINSTATE) Pin State Mask */ 527 #define EIC_PINSTATE_PINSTATE(value) (EIC_PINSTATE_PINSTATE_Msk & (_UINT32_(value) << EIC_PINSTATE_PINSTATE_Pos)) /* Assigment of value for PINSTATE in the EIC_PINSTATE register */ 528 #define EIC_PINSTATE_Msk _UINT32_(0x0000FFFF) /* (EIC_PINSTATE) Register Mask */ 529 530 531 /** \brief EIC register offsets definitions */ 532 #define EIC_CTRLA_REG_OFST _UINT32_(0x00) /* (EIC_CTRLA) Control A Offset */ 533 #define EIC_NMICTRL_REG_OFST _UINT32_(0x01) /* (EIC_NMICTRL) Non-Maskable Interrupt Control Offset */ 534 #define EIC_NMIFLAG_REG_OFST _UINT32_(0x02) /* (EIC_NMIFLAG) Non-Maskable Interrupt Flag Status and Clear Offset */ 535 #define EIC_SYNCBUSY_REG_OFST _UINT32_(0x04) /* (EIC_SYNCBUSY) Synchronization Busy Offset */ 536 #define EIC_EVCTRL_REG_OFST _UINT32_(0x08) /* (EIC_EVCTRL) Event Control Offset */ 537 #define EIC_INTENCLR_REG_OFST _UINT32_(0x0C) /* (EIC_INTENCLR) Interrupt Enable Clear Offset */ 538 #define EIC_INTENSET_REG_OFST _UINT32_(0x10) /* (EIC_INTENSET) Interrupt Enable Set Offset */ 539 #define EIC_INTFLAG_REG_OFST _UINT32_(0x14) /* (EIC_INTFLAG) Interrupt Flag Status and Clear Offset */ 540 #define EIC_ASYNCH_REG_OFST _UINT32_(0x18) /* (EIC_ASYNCH) External Interrupt Asynchronous Mode Offset */ 541 #define EIC_CONFIG0_REG_OFST _UINT32_(0x1C) /* (EIC_CONFIG0) External Interrupt Sense Configuration Offset */ 542 #define EIC_CONFIG1_REG_OFST _UINT32_(0x20) /* (EIC_CONFIG1) External Interrupt Sense Configuration Offset */ 543 #define EIC_DEBOUNCEN_REG_OFST _UINT32_(0x30) /* (EIC_DEBOUNCEN) Debouncer Enable Offset */ 544 #define EIC_DPRESCALER_REG_OFST _UINT32_(0x34) /* (EIC_DPRESCALER) Debouncer Prescaler Offset */ 545 #define EIC_PINSTATE_REG_OFST _UINT32_(0x38) /* (EIC_PINSTATE) Pin State Offset */ 546 547 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 548 /** \brief EIC register API structure */ 549 typedef struct 550 { /* External Interrupt Controller */ 551 __IO uint8_t EIC_CTRLA; /**< Offset: 0x00 (R/W 8) Control A */ 552 __IO uint8_t EIC_NMICTRL; /**< Offset: 0x01 (R/W 8) Non-Maskable Interrupt Control */ 553 __IO uint16_t EIC_NMIFLAG; /**< Offset: 0x02 (R/W 16) Non-Maskable Interrupt Flag Status and Clear */ 554 __I uint32_t EIC_SYNCBUSY; /**< Offset: 0x04 (R/ 32) Synchronization Busy */ 555 __IO uint32_t EIC_EVCTRL; /**< Offset: 0x08 (R/W 32) Event Control */ 556 __IO uint32_t EIC_INTENCLR; /**< Offset: 0x0C (R/W 32) Interrupt Enable Clear */ 557 __IO uint32_t EIC_INTENSET; /**< Offset: 0x10 (R/W 32) Interrupt Enable Set */ 558 __IO uint32_t EIC_INTFLAG; /**< Offset: 0x14 (R/W 32) Interrupt Flag Status and Clear */ 559 __IO uint32_t EIC_ASYNCH; /**< Offset: 0x18 (R/W 32) External Interrupt Asynchronous Mode */ 560 __IO uint32_t EIC_CONFIG0; /**< Offset: 0x1C (R/W 32) External Interrupt Sense Configuration */ 561 __IO uint32_t EIC_CONFIG1; /**< Offset: 0x20 (R/W 32) External Interrupt Sense Configuration */ 562 __I uint8_t Reserved1[0x0C]; 563 __IO uint32_t EIC_DEBOUNCEN; /**< Offset: 0x30 (R/W 32) Debouncer Enable */ 564 __IO uint32_t EIC_DPRESCALER; /**< Offset: 0x34 (R/W 32) Debouncer Prescaler */ 565 __I uint32_t EIC_PINSTATE; /**< Offset: 0x38 (R/ 32) Pin State */ 566 } eic_registers_t; 567 568 569 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 570 #endif /* _PIC32CXSG61_EIC_COMPONENT_H_ */ 571
