1 /* 2 * Component description for AES 3 * 4 * Copyright (c) 2023 Microchip Technology Inc. and its subsidiaries. 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 */ 19 20 /* file generated from device description file (ATDF) version 2023-03-17T09:48:59Z */ 21 #ifndef _PIC32CXSG61_AES_COMPONENT_H_ 22 #define _PIC32CXSG61_AES_COMPONENT_H_ 23 24 /* ************************************************************************** */ 25 /* SOFTWARE API DEFINITION FOR AES */ 26 /* ************************************************************************** */ 27 28 /* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */ 29 #define AES_CTRLA_RESETVALUE _UINT32_(0x00) /* (AES_CTRLA) Control A Reset Value */ 30 31 #define AES_CTRLA_SWRST_Pos _UINT32_(0) /* (AES_CTRLA) Software Reset Position */ 32 #define AES_CTRLA_SWRST_Msk (_UINT32_(0x1) << AES_CTRLA_SWRST_Pos) /* (AES_CTRLA) Software Reset Mask */ 33 #define AES_CTRLA_SWRST(value) (AES_CTRLA_SWRST_Msk & (_UINT32_(value) << AES_CTRLA_SWRST_Pos)) /* Assigment of value for SWRST in the AES_CTRLA register */ 34 #define AES_CTRLA_ENABLE_Pos _UINT32_(1) /* (AES_CTRLA) Enable Position */ 35 #define AES_CTRLA_ENABLE_Msk (_UINT32_(0x1) << AES_CTRLA_ENABLE_Pos) /* (AES_CTRLA) Enable Mask */ 36 #define AES_CTRLA_ENABLE(value) (AES_CTRLA_ENABLE_Msk & (_UINT32_(value) << AES_CTRLA_ENABLE_Pos)) /* Assigment of value for ENABLE in the AES_CTRLA register */ 37 #define AES_CTRLA_AESMODE_Pos _UINT32_(2) /* (AES_CTRLA) AES Modes of operation Position */ 38 #define AES_CTRLA_AESMODE_Msk (_UINT32_(0x7) << AES_CTRLA_AESMODE_Pos) /* (AES_CTRLA) AES Modes of operation Mask */ 39 #define AES_CTRLA_AESMODE(value) (AES_CTRLA_AESMODE_Msk & (_UINT32_(value) << AES_CTRLA_AESMODE_Pos)) /* Assigment of value for AESMODE in the AES_CTRLA register */ 40 #define AES_CTRLA_AESMODE_ECB_Val _UINT32_(0x0) /* (AES_CTRLA) Electronic code book mode */ 41 #define AES_CTRLA_AESMODE_CBC_Val _UINT32_(0x1) /* (AES_CTRLA) Cipher block chaining mode */ 42 #define AES_CTRLA_AESMODE_OFB_Val _UINT32_(0x2) /* (AES_CTRLA) Output feedback mode */ 43 #define AES_CTRLA_AESMODE_CFB_Val _UINT32_(0x3) /* (AES_CTRLA) Cipher feedback mode */ 44 #define AES_CTRLA_AESMODE_COUNTER_Val _UINT32_(0x4) /* (AES_CTRLA) Counter mode */ 45 #define AES_CTRLA_AESMODE_CCM_Val _UINT32_(0x5) /* (AES_CTRLA) CCM mode */ 46 #define AES_CTRLA_AESMODE_GCM_Val _UINT32_(0x6) /* (AES_CTRLA) Galois counter mode */ 47 #define AES_CTRLA_AESMODE_ECB (AES_CTRLA_AESMODE_ECB_Val << AES_CTRLA_AESMODE_Pos) /* (AES_CTRLA) Electronic code book mode Position */ 48 #define AES_CTRLA_AESMODE_CBC (AES_CTRLA_AESMODE_CBC_Val << AES_CTRLA_AESMODE_Pos) /* (AES_CTRLA) Cipher block chaining mode Position */ 49 #define AES_CTRLA_AESMODE_OFB (AES_CTRLA_AESMODE_OFB_Val << AES_CTRLA_AESMODE_Pos) /* (AES_CTRLA) Output feedback mode Position */ 50 #define AES_CTRLA_AESMODE_CFB (AES_CTRLA_AESMODE_CFB_Val << AES_CTRLA_AESMODE_Pos) /* (AES_CTRLA) Cipher feedback mode Position */ 51 #define AES_CTRLA_AESMODE_COUNTER (AES_CTRLA_AESMODE_COUNTER_Val << AES_CTRLA_AESMODE_Pos) /* (AES_CTRLA) Counter mode Position */ 52 #define AES_CTRLA_AESMODE_CCM (AES_CTRLA_AESMODE_CCM_Val << AES_CTRLA_AESMODE_Pos) /* (AES_CTRLA) CCM mode Position */ 53 #define AES_CTRLA_AESMODE_GCM (AES_CTRLA_AESMODE_GCM_Val << AES_CTRLA_AESMODE_Pos) /* (AES_CTRLA) Galois counter mode Position */ 54 #define AES_CTRLA_CFBS_Pos _UINT32_(5) /* (AES_CTRLA) Cipher Feedback Block Size Position */ 55 #define AES_CTRLA_CFBS_Msk (_UINT32_(0x7) << AES_CTRLA_CFBS_Pos) /* (AES_CTRLA) Cipher Feedback Block Size Mask */ 56 #define AES_CTRLA_CFBS(value) (AES_CTRLA_CFBS_Msk & (_UINT32_(value) << AES_CTRLA_CFBS_Pos)) /* Assigment of value for CFBS in the AES_CTRLA register */ 57 #define AES_CTRLA_CFBS_128BIT_Val _UINT32_(0x0) /* (AES_CTRLA) 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ 58 #define AES_CTRLA_CFBS_64BIT_Val _UINT32_(0x1) /* (AES_CTRLA) 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ 59 #define AES_CTRLA_CFBS_32BIT_Val _UINT32_(0x2) /* (AES_CTRLA) 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ 60 #define AES_CTRLA_CFBS_16BIT_Val _UINT32_(0x3) /* (AES_CTRLA) 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ 61 #define AES_CTRLA_CFBS_8BIT_Val _UINT32_(0x4) /* (AES_CTRLA) 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ 62 #define AES_CTRLA_CFBS_128BIT (AES_CTRLA_CFBS_128BIT_Val << AES_CTRLA_CFBS_Pos) /* (AES_CTRLA) 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */ 63 #define AES_CTRLA_CFBS_64BIT (AES_CTRLA_CFBS_64BIT_Val << AES_CTRLA_CFBS_Pos) /* (AES_CTRLA) 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */ 64 #define AES_CTRLA_CFBS_32BIT (AES_CTRLA_CFBS_32BIT_Val << AES_CTRLA_CFBS_Pos) /* (AES_CTRLA) 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */ 65 #define AES_CTRLA_CFBS_16BIT (AES_CTRLA_CFBS_16BIT_Val << AES_CTRLA_CFBS_Pos) /* (AES_CTRLA) 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */ 66 #define AES_CTRLA_CFBS_8BIT (AES_CTRLA_CFBS_8BIT_Val << AES_CTRLA_CFBS_Pos) /* (AES_CTRLA) 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */ 67 #define AES_CTRLA_KEYSIZE_Pos _UINT32_(8) /* (AES_CTRLA) Encryption Key Size Position */ 68 #define AES_CTRLA_KEYSIZE_Msk (_UINT32_(0x3) << AES_CTRLA_KEYSIZE_Pos) /* (AES_CTRLA) Encryption Key Size Mask */ 69 #define AES_CTRLA_KEYSIZE(value) (AES_CTRLA_KEYSIZE_Msk & (_UINT32_(value) << AES_CTRLA_KEYSIZE_Pos)) /* Assigment of value for KEYSIZE in the AES_CTRLA register */ 70 #define AES_CTRLA_KEYSIZE_128BIT_Val _UINT32_(0x0) /* (AES_CTRLA) 128-bit Key for Encryption / Decryption */ 71 #define AES_CTRLA_KEYSIZE_192BIT_Val _UINT32_(0x1) /* (AES_CTRLA) 192-bit Key for Encryption / Decryption */ 72 #define AES_CTRLA_KEYSIZE_256BIT_Val _UINT32_(0x2) /* (AES_CTRLA) 256-bit Key for Encryption / Decryption */ 73 #define AES_CTRLA_KEYSIZE_128BIT (AES_CTRLA_KEYSIZE_128BIT_Val << AES_CTRLA_KEYSIZE_Pos) /* (AES_CTRLA) 128-bit Key for Encryption / Decryption Position */ 74 #define AES_CTRLA_KEYSIZE_192BIT (AES_CTRLA_KEYSIZE_192BIT_Val << AES_CTRLA_KEYSIZE_Pos) /* (AES_CTRLA) 192-bit Key for Encryption / Decryption Position */ 75 #define AES_CTRLA_KEYSIZE_256BIT (AES_CTRLA_KEYSIZE_256BIT_Val << AES_CTRLA_KEYSIZE_Pos) /* (AES_CTRLA) 256-bit Key for Encryption / Decryption Position */ 76 #define AES_CTRLA_CIPHER_Pos _UINT32_(10) /* (AES_CTRLA) Cipher Mode Position */ 77 #define AES_CTRLA_CIPHER_Msk (_UINT32_(0x1) << AES_CTRLA_CIPHER_Pos) /* (AES_CTRLA) Cipher Mode Mask */ 78 #define AES_CTRLA_CIPHER(value) (AES_CTRLA_CIPHER_Msk & (_UINT32_(value) << AES_CTRLA_CIPHER_Pos)) /* Assigment of value for CIPHER in the AES_CTRLA register */ 79 #define AES_CTRLA_CIPHER_DEC_Val _UINT32_(0x0) /* (AES_CTRLA) Decryption */ 80 #define AES_CTRLA_CIPHER_ENC_Val _UINT32_(0x1) /* (AES_CTRLA) Encryption */ 81 #define AES_CTRLA_CIPHER_DEC (AES_CTRLA_CIPHER_DEC_Val << AES_CTRLA_CIPHER_Pos) /* (AES_CTRLA) Decryption Position */ 82 #define AES_CTRLA_CIPHER_ENC (AES_CTRLA_CIPHER_ENC_Val << AES_CTRLA_CIPHER_Pos) /* (AES_CTRLA) Encryption Position */ 83 #define AES_CTRLA_STARTMODE_Pos _UINT32_(11) /* (AES_CTRLA) Start Mode Select Position */ 84 #define AES_CTRLA_STARTMODE_Msk (_UINT32_(0x1) << AES_CTRLA_STARTMODE_Pos) /* (AES_CTRLA) Start Mode Select Mask */ 85 #define AES_CTRLA_STARTMODE(value) (AES_CTRLA_STARTMODE_Msk & (_UINT32_(value) << AES_CTRLA_STARTMODE_Pos)) /* Assigment of value for STARTMODE in the AES_CTRLA register */ 86 #define AES_CTRLA_STARTMODE_MANUAL_Val _UINT32_(0x0) /* (AES_CTRLA) Start Encryption / Decryption in Manual mode */ 87 #define AES_CTRLA_STARTMODE_AUTO_Val _UINT32_(0x1) /* (AES_CTRLA) Start Encryption / Decryption in Auto mode */ 88 #define AES_CTRLA_STARTMODE_MANUAL (AES_CTRLA_STARTMODE_MANUAL_Val << AES_CTRLA_STARTMODE_Pos) /* (AES_CTRLA) Start Encryption / Decryption in Manual mode Position */ 89 #define AES_CTRLA_STARTMODE_AUTO (AES_CTRLA_STARTMODE_AUTO_Val << AES_CTRLA_STARTMODE_Pos) /* (AES_CTRLA) Start Encryption / Decryption in Auto mode Position */ 90 #define AES_CTRLA_LOD_Pos _UINT32_(12) /* (AES_CTRLA) Last Output Data Mode Position */ 91 #define AES_CTRLA_LOD_Msk (_UINT32_(0x1) << AES_CTRLA_LOD_Pos) /* (AES_CTRLA) Last Output Data Mode Mask */ 92 #define AES_CTRLA_LOD(value) (AES_CTRLA_LOD_Msk & (_UINT32_(value) << AES_CTRLA_LOD_Pos)) /* Assigment of value for LOD in the AES_CTRLA register */ 93 #define AES_CTRLA_LOD_NONE_Val _UINT32_(0x0) /* (AES_CTRLA) No effect */ 94 #define AES_CTRLA_LOD_LAST_Val _UINT32_(0x1) /* (AES_CTRLA) Start encryption in Last Output Data mode */ 95 #define AES_CTRLA_LOD_NONE (AES_CTRLA_LOD_NONE_Val << AES_CTRLA_LOD_Pos) /* (AES_CTRLA) No effect Position */ 96 #define AES_CTRLA_LOD_LAST (AES_CTRLA_LOD_LAST_Val << AES_CTRLA_LOD_Pos) /* (AES_CTRLA) Start encryption in Last Output Data mode Position */ 97 #define AES_CTRLA_KEYGEN_Pos _UINT32_(13) /* (AES_CTRLA) Last Key Generation Position */ 98 #define AES_CTRLA_KEYGEN_Msk (_UINT32_(0x1) << AES_CTRLA_KEYGEN_Pos) /* (AES_CTRLA) Last Key Generation Mask */ 99 #define AES_CTRLA_KEYGEN(value) (AES_CTRLA_KEYGEN_Msk & (_UINT32_(value) << AES_CTRLA_KEYGEN_Pos)) /* Assigment of value for KEYGEN in the AES_CTRLA register */ 100 #define AES_CTRLA_KEYGEN_NONE_Val _UINT32_(0x0) /* (AES_CTRLA) No effect */ 101 #define AES_CTRLA_KEYGEN_LAST_Val _UINT32_(0x1) /* (AES_CTRLA) Start Computation of the last NK words of the expanded key */ 102 #define AES_CTRLA_KEYGEN_NONE (AES_CTRLA_KEYGEN_NONE_Val << AES_CTRLA_KEYGEN_Pos) /* (AES_CTRLA) No effect Position */ 103 #define AES_CTRLA_KEYGEN_LAST (AES_CTRLA_KEYGEN_LAST_Val << AES_CTRLA_KEYGEN_Pos) /* (AES_CTRLA) Start Computation of the last NK words of the expanded key Position */ 104 #define AES_CTRLA_XORKEY_Pos _UINT32_(14) /* (AES_CTRLA) XOR Key Operation Position */ 105 #define AES_CTRLA_XORKEY_Msk (_UINT32_(0x1) << AES_CTRLA_XORKEY_Pos) /* (AES_CTRLA) XOR Key Operation Mask */ 106 #define AES_CTRLA_XORKEY(value) (AES_CTRLA_XORKEY_Msk & (_UINT32_(value) << AES_CTRLA_XORKEY_Pos)) /* Assigment of value for XORKEY in the AES_CTRLA register */ 107 #define AES_CTRLA_XORKEY_NONE_Val _UINT32_(0x0) /* (AES_CTRLA) No effect */ 108 #define AES_CTRLA_XORKEY_XOR_Val _UINT32_(0x1) /* (AES_CTRLA) The user keyword gets XORed with the previous keyword register content. */ 109 #define AES_CTRLA_XORKEY_NONE (AES_CTRLA_XORKEY_NONE_Val << AES_CTRLA_XORKEY_Pos) /* (AES_CTRLA) No effect Position */ 110 #define AES_CTRLA_XORKEY_XOR (AES_CTRLA_XORKEY_XOR_Val << AES_CTRLA_XORKEY_Pos) /* (AES_CTRLA) The user keyword gets XORed with the previous keyword register content. Position */ 111 #define AES_CTRLA_CTYPE_Pos _UINT32_(16) /* (AES_CTRLA) Counter Measure Type Position */ 112 #define AES_CTRLA_CTYPE_Msk (_UINT32_(0xF) << AES_CTRLA_CTYPE_Pos) /* (AES_CTRLA) Counter Measure Type Mask */ 113 #define AES_CTRLA_CTYPE(value) (AES_CTRLA_CTYPE_Msk & (_UINT32_(value) << AES_CTRLA_CTYPE_Pos)) /* Assigment of value for CTYPE in the AES_CTRLA register */ 114 #define AES_CTRLA_Msk _UINT32_(0x000F7FFF) /* (AES_CTRLA) Register Mask */ 115 116 117 /* -------- AES_CTRLB : (AES Offset: 0x04) (R/W 8) Control B -------- */ 118 #define AES_CTRLB_RESETVALUE _UINT8_(0x00) /* (AES_CTRLB) Control B Reset Value */ 119 120 #define AES_CTRLB_START_Pos _UINT8_(0) /* (AES_CTRLB) Start Encryption/Decryption Position */ 121 #define AES_CTRLB_START_Msk (_UINT8_(0x1) << AES_CTRLB_START_Pos) /* (AES_CTRLB) Start Encryption/Decryption Mask */ 122 #define AES_CTRLB_START(value) (AES_CTRLB_START_Msk & (_UINT8_(value) << AES_CTRLB_START_Pos)) /* Assigment of value for START in the AES_CTRLB register */ 123 #define AES_CTRLB_NEWMSG_Pos _UINT8_(1) /* (AES_CTRLB) New message Position */ 124 #define AES_CTRLB_NEWMSG_Msk (_UINT8_(0x1) << AES_CTRLB_NEWMSG_Pos) /* (AES_CTRLB) New message Mask */ 125 #define AES_CTRLB_NEWMSG(value) (AES_CTRLB_NEWMSG_Msk & (_UINT8_(value) << AES_CTRLB_NEWMSG_Pos)) /* Assigment of value for NEWMSG in the AES_CTRLB register */ 126 #define AES_CTRLB_EOM_Pos _UINT8_(2) /* (AES_CTRLB) End of message Position */ 127 #define AES_CTRLB_EOM_Msk (_UINT8_(0x1) << AES_CTRLB_EOM_Pos) /* (AES_CTRLB) End of message Mask */ 128 #define AES_CTRLB_EOM(value) (AES_CTRLB_EOM_Msk & (_UINT8_(value) << AES_CTRLB_EOM_Pos)) /* Assigment of value for EOM in the AES_CTRLB register */ 129 #define AES_CTRLB_GFMUL_Pos _UINT8_(3) /* (AES_CTRLB) GF Multiplication Position */ 130 #define AES_CTRLB_GFMUL_Msk (_UINT8_(0x1) << AES_CTRLB_GFMUL_Pos) /* (AES_CTRLB) GF Multiplication Mask */ 131 #define AES_CTRLB_GFMUL(value) (AES_CTRLB_GFMUL_Msk & (_UINT8_(value) << AES_CTRLB_GFMUL_Pos)) /* Assigment of value for GFMUL in the AES_CTRLB register */ 132 #define AES_CTRLB_Msk _UINT8_(0x0F) /* (AES_CTRLB) Register Mask */ 133 134 135 /* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */ 136 #define AES_INTENCLR_RESETVALUE _UINT8_(0x00) /* (AES_INTENCLR) Interrupt Enable Clear Reset Value */ 137 138 #define AES_INTENCLR_ENCCMP_Pos _UINT8_(0) /* (AES_INTENCLR) Encryption Complete Interrupt Enable Position */ 139 #define AES_INTENCLR_ENCCMP_Msk (_UINT8_(0x1) << AES_INTENCLR_ENCCMP_Pos) /* (AES_INTENCLR) Encryption Complete Interrupt Enable Mask */ 140 #define AES_INTENCLR_ENCCMP(value) (AES_INTENCLR_ENCCMP_Msk & (_UINT8_(value) << AES_INTENCLR_ENCCMP_Pos)) /* Assigment of value for ENCCMP in the AES_INTENCLR register */ 141 #define AES_INTENCLR_GFMCMP_Pos _UINT8_(1) /* (AES_INTENCLR) GF Multiplication Complete Interrupt Enable Position */ 142 #define AES_INTENCLR_GFMCMP_Msk (_UINT8_(0x1) << AES_INTENCLR_GFMCMP_Pos) /* (AES_INTENCLR) GF Multiplication Complete Interrupt Enable Mask */ 143 #define AES_INTENCLR_GFMCMP(value) (AES_INTENCLR_GFMCMP_Msk & (_UINT8_(value) << AES_INTENCLR_GFMCMP_Pos)) /* Assigment of value for GFMCMP in the AES_INTENCLR register */ 144 #define AES_INTENCLR_Msk _UINT8_(0x03) /* (AES_INTENCLR) Register Mask */ 145 146 147 /* -------- AES_INTENSET : (AES Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */ 148 #define AES_INTENSET_RESETVALUE _UINT8_(0x00) /* (AES_INTENSET) Interrupt Enable Set Reset Value */ 149 150 #define AES_INTENSET_ENCCMP_Pos _UINT8_(0) /* (AES_INTENSET) Encryption Complete Interrupt Enable Position */ 151 #define AES_INTENSET_ENCCMP_Msk (_UINT8_(0x1) << AES_INTENSET_ENCCMP_Pos) /* (AES_INTENSET) Encryption Complete Interrupt Enable Mask */ 152 #define AES_INTENSET_ENCCMP(value) (AES_INTENSET_ENCCMP_Msk & (_UINT8_(value) << AES_INTENSET_ENCCMP_Pos)) /* Assigment of value for ENCCMP in the AES_INTENSET register */ 153 #define AES_INTENSET_GFMCMP_Pos _UINT8_(1) /* (AES_INTENSET) GF Multiplication Complete Interrupt Enable Position */ 154 #define AES_INTENSET_GFMCMP_Msk (_UINT8_(0x1) << AES_INTENSET_GFMCMP_Pos) /* (AES_INTENSET) GF Multiplication Complete Interrupt Enable Mask */ 155 #define AES_INTENSET_GFMCMP(value) (AES_INTENSET_GFMCMP_Msk & (_UINT8_(value) << AES_INTENSET_GFMCMP_Pos)) /* Assigment of value for GFMCMP in the AES_INTENSET register */ 156 #define AES_INTENSET_Msk _UINT8_(0x03) /* (AES_INTENSET) Register Mask */ 157 158 159 /* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W 8) Interrupt Flag Status -------- */ 160 #define AES_INTFLAG_RESETVALUE _UINT8_(0x00) /* (AES_INTFLAG) Interrupt Flag Status Reset Value */ 161 162 #define AES_INTFLAG_ENCCMP_Pos _UINT8_(0) /* (AES_INTFLAG) Encryption Complete Position */ 163 #define AES_INTFLAG_ENCCMP_Msk (_UINT8_(0x1) << AES_INTFLAG_ENCCMP_Pos) /* (AES_INTFLAG) Encryption Complete Mask */ 164 #define AES_INTFLAG_ENCCMP(value) (AES_INTFLAG_ENCCMP_Msk & (_UINT8_(value) << AES_INTFLAG_ENCCMP_Pos)) /* Assigment of value for ENCCMP in the AES_INTFLAG register */ 165 #define AES_INTFLAG_GFMCMP_Pos _UINT8_(1) /* (AES_INTFLAG) GF Multiplication Complete Position */ 166 #define AES_INTFLAG_GFMCMP_Msk (_UINT8_(0x1) << AES_INTFLAG_GFMCMP_Pos) /* (AES_INTFLAG) GF Multiplication Complete Mask */ 167 #define AES_INTFLAG_GFMCMP(value) (AES_INTFLAG_GFMCMP_Msk & (_UINT8_(value) << AES_INTFLAG_GFMCMP_Pos)) /* Assigment of value for GFMCMP in the AES_INTFLAG register */ 168 #define AES_INTFLAG_Msk _UINT8_(0x03) /* (AES_INTFLAG) Register Mask */ 169 170 171 /* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W 8) Data buffer pointer -------- */ 172 #define AES_DATABUFPTR_RESETVALUE _UINT8_(0x00) /* (AES_DATABUFPTR) Data buffer pointer Reset Value */ 173 174 #define AES_DATABUFPTR_INDATAPTR_Pos _UINT8_(0) /* (AES_DATABUFPTR) Input Data Pointer Position */ 175 #define AES_DATABUFPTR_INDATAPTR_Msk (_UINT8_(0x3) << AES_DATABUFPTR_INDATAPTR_Pos) /* (AES_DATABUFPTR) Input Data Pointer Mask */ 176 #define AES_DATABUFPTR_INDATAPTR(value) (AES_DATABUFPTR_INDATAPTR_Msk & (_UINT8_(value) << AES_DATABUFPTR_INDATAPTR_Pos)) /* Assigment of value for INDATAPTR in the AES_DATABUFPTR register */ 177 #define AES_DATABUFPTR_Msk _UINT8_(0x03) /* (AES_DATABUFPTR) Register Mask */ 178 179 180 /* -------- AES_DBGCTRL : (AES Offset: 0x09) (R/W 8) Debug control -------- */ 181 #define AES_DBGCTRL_RESETVALUE _UINT8_(0x00) /* (AES_DBGCTRL) Debug control Reset Value */ 182 183 #define AES_DBGCTRL_DBGRUN_Pos _UINT8_(0) /* (AES_DBGCTRL) Debug Run Position */ 184 #define AES_DBGCTRL_DBGRUN_Msk (_UINT8_(0x1) << AES_DBGCTRL_DBGRUN_Pos) /* (AES_DBGCTRL) Debug Run Mask */ 185 #define AES_DBGCTRL_DBGRUN(value) (AES_DBGCTRL_DBGRUN_Msk & (_UINT8_(value) << AES_DBGCTRL_DBGRUN_Pos)) /* Assigment of value for DBGRUN in the AES_DBGCTRL register */ 186 #define AES_DBGCTRL_Msk _UINT8_(0x01) /* (AES_DBGCTRL) Register Mask */ 187 188 189 /* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */ 190 #define AES_KEYWORD_RESETVALUE _UINT32_(0x00) /* (AES_KEYWORD) Keyword n Reset Value */ 191 192 #define AES_KEYWORD_KEYWORD_Pos _UINT32_(0) /* (AES_KEYWORD) Key Word Value Position */ 193 #define AES_KEYWORD_KEYWORD_Msk (_UINT32_(0xFFFFFFFF) << AES_KEYWORD_KEYWORD_Pos) /* (AES_KEYWORD) Key Word Value Mask */ 194 #define AES_KEYWORD_KEYWORD(value) (AES_KEYWORD_KEYWORD_Msk & (_UINT32_(value) << AES_KEYWORD_KEYWORD_Pos)) /* Assigment of value for KEYWORD in the AES_KEYWORD register */ 195 #define AES_KEYWORD_Msk _UINT32_(0xFFFFFFFF) /* (AES_KEYWORD) Register Mask */ 196 197 198 /* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */ 199 #define AES_INDATA_RESETVALUE _UINT32_(0x00) /* (AES_INDATA) Indata Reset Value */ 200 201 #define AES_INDATA_INDATA_Pos _UINT32_(0) /* (AES_INDATA) Data Value Position */ 202 #define AES_INDATA_INDATA_Msk (_UINT32_(0xFFFFFFFF) << AES_INDATA_INDATA_Pos) /* (AES_INDATA) Data Value Mask */ 203 #define AES_INDATA_INDATA(value) (AES_INDATA_INDATA_Msk & (_UINT32_(value) << AES_INDATA_INDATA_Pos)) /* Assigment of value for INDATA in the AES_INDATA register */ 204 #define AES_INDATA_Msk _UINT32_(0xFFFFFFFF) /* (AES_INDATA) Register Mask */ 205 206 207 /* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */ 208 #define AES_INTVECTV_RESETVALUE _UINT32_(0x00) /* (AES_INTVECTV) Initialisation Vector n Reset Value */ 209 210 #define AES_INTVECTV_INTVECTV_Pos _UINT32_(0) /* (AES_INTVECTV) Initialization Vector Value Position */ 211 #define AES_INTVECTV_INTVECTV_Msk (_UINT32_(0xFFFFFFFF) << AES_INTVECTV_INTVECTV_Pos) /* (AES_INTVECTV) Initialization Vector Value Mask */ 212 #define AES_INTVECTV_INTVECTV(value) (AES_INTVECTV_INTVECTV_Msk & (_UINT32_(value) << AES_INTVECTV_INTVECTV_Pos)) /* Assigment of value for INTVECTV in the AES_INTVECTV register */ 213 #define AES_INTVECTV_Msk _UINT32_(0xFFFFFFFF) /* (AES_INTVECTV) Register Mask */ 214 215 216 /* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */ 217 #define AES_HASHKEY_RESETVALUE _UINT32_(0x00) /* (AES_HASHKEY) Hash key n Reset Value */ 218 219 #define AES_HASHKEY_HASHKEY_Pos _UINT32_(0) /* (AES_HASHKEY) Hash Key Value Position */ 220 #define AES_HASHKEY_HASHKEY_Msk (_UINT32_(0xFFFFFFFF) << AES_HASHKEY_HASHKEY_Pos) /* (AES_HASHKEY) Hash Key Value Mask */ 221 #define AES_HASHKEY_HASHKEY(value) (AES_HASHKEY_HASHKEY_Msk & (_UINT32_(value) << AES_HASHKEY_HASHKEY_Pos)) /* Assigment of value for HASHKEY in the AES_HASHKEY register */ 222 #define AES_HASHKEY_Msk _UINT32_(0xFFFFFFFF) /* (AES_HASHKEY) Register Mask */ 223 224 225 /* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */ 226 #define AES_GHASH_RESETVALUE _UINT32_(0x00) /* (AES_GHASH) Galois Hash n Reset Value */ 227 228 #define AES_GHASH_GHASH_Pos _UINT32_(0) /* (AES_GHASH) Galois Hash Value Position */ 229 #define AES_GHASH_GHASH_Msk (_UINT32_(0xFFFFFFFF) << AES_GHASH_GHASH_Pos) /* (AES_GHASH) Galois Hash Value Mask */ 230 #define AES_GHASH_GHASH(value) (AES_GHASH_GHASH_Msk & (_UINT32_(value) << AES_GHASH_GHASH_Pos)) /* Assigment of value for GHASH in the AES_GHASH register */ 231 #define AES_GHASH_Msk _UINT32_(0xFFFFFFFF) /* (AES_GHASH) Register Mask */ 232 233 234 /* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */ 235 #define AES_CIPLEN_RESETVALUE _UINT32_(0x00) /* (AES_CIPLEN) Cipher Length Reset Value */ 236 237 #define AES_CIPLEN_CIPLEN_Pos _UINT32_(0) /* (AES_CIPLEN) Cipher Length Position */ 238 #define AES_CIPLEN_CIPLEN_Msk (_UINT32_(0xFFFFFFFF) << AES_CIPLEN_CIPLEN_Pos) /* (AES_CIPLEN) Cipher Length Mask */ 239 #define AES_CIPLEN_CIPLEN(value) (AES_CIPLEN_CIPLEN_Msk & (_UINT32_(value) << AES_CIPLEN_CIPLEN_Pos)) /* Assigment of value for CIPLEN in the AES_CIPLEN register */ 240 #define AES_CIPLEN_Msk _UINT32_(0xFFFFFFFF) /* (AES_CIPLEN) Register Mask */ 241 242 243 /* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */ 244 #define AES_RANDSEED_RESETVALUE _UINT32_(0x00) /* (AES_RANDSEED) Random Seed Reset Value */ 245 246 #define AES_RANDSEED_RANDSEED_Pos _UINT32_(0) /* (AES_RANDSEED) Random Seed Position */ 247 #define AES_RANDSEED_RANDSEED_Msk (_UINT32_(0xFFFFFFFF) << AES_RANDSEED_RANDSEED_Pos) /* (AES_RANDSEED) Random Seed Mask */ 248 #define AES_RANDSEED_RANDSEED(value) (AES_RANDSEED_RANDSEED_Msk & (_UINT32_(value) << AES_RANDSEED_RANDSEED_Pos)) /* Assigment of value for RANDSEED in the AES_RANDSEED register */ 249 #define AES_RANDSEED_Msk _UINT32_(0xFFFFFFFF) /* (AES_RANDSEED) Register Mask */ 250 251 252 /** \brief AES register offsets definitions */ 253 #define AES_CTRLA_REG_OFST _UINT32_(0x00) /* (AES_CTRLA) Control A Offset */ 254 #define AES_CTRLB_REG_OFST _UINT32_(0x04) /* (AES_CTRLB) Control B Offset */ 255 #define AES_INTENCLR_REG_OFST _UINT32_(0x05) /* (AES_INTENCLR) Interrupt Enable Clear Offset */ 256 #define AES_INTENSET_REG_OFST _UINT32_(0x06) /* (AES_INTENSET) Interrupt Enable Set Offset */ 257 #define AES_INTFLAG_REG_OFST _UINT32_(0x07) /* (AES_INTFLAG) Interrupt Flag Status Offset */ 258 #define AES_DATABUFPTR_REG_OFST _UINT32_(0x08) /* (AES_DATABUFPTR) Data buffer pointer Offset */ 259 #define AES_DBGCTRL_REG_OFST _UINT32_(0x09) /* (AES_DBGCTRL) Debug control Offset */ 260 #define AES_KEYWORD_REG_OFST _UINT32_(0x0C) /* (AES_KEYWORD) Keyword n Offset */ 261 #define AES_KEYWORD0_REG_OFST _UINT32_(0x0C) /* (AES_KEYWORD0) Keyword n Offset */ 262 #define AES_KEYWORD1_REG_OFST _UINT32_(0x10) /* (AES_KEYWORD1) Keyword n Offset */ 263 #define AES_KEYWORD2_REG_OFST _UINT32_(0x14) /* (AES_KEYWORD2) Keyword n Offset */ 264 #define AES_KEYWORD3_REG_OFST _UINT32_(0x18) /* (AES_KEYWORD3) Keyword n Offset */ 265 #define AES_KEYWORD4_REG_OFST _UINT32_(0x1C) /* (AES_KEYWORD4) Keyword n Offset */ 266 #define AES_KEYWORD5_REG_OFST _UINT32_(0x20) /* (AES_KEYWORD5) Keyword n Offset */ 267 #define AES_KEYWORD6_REG_OFST _UINT32_(0x24) /* (AES_KEYWORD6) Keyword n Offset */ 268 #define AES_KEYWORD7_REG_OFST _UINT32_(0x28) /* (AES_KEYWORD7) Keyword n Offset */ 269 #define AES_INDATA_REG_OFST _UINT32_(0x38) /* (AES_INDATA) Indata Offset */ 270 #define AES_INTVECTV_REG_OFST _UINT32_(0x3C) /* (AES_INTVECTV) Initialisation Vector n Offset */ 271 #define AES_INTVECTV0_REG_OFST _UINT32_(0x3C) /* (AES_INTVECTV0) Initialisation Vector n Offset */ 272 #define AES_INTVECTV1_REG_OFST _UINT32_(0x40) /* (AES_INTVECTV1) Initialisation Vector n Offset */ 273 #define AES_INTVECTV2_REG_OFST _UINT32_(0x44) /* (AES_INTVECTV2) Initialisation Vector n Offset */ 274 #define AES_INTVECTV3_REG_OFST _UINT32_(0x48) /* (AES_INTVECTV3) Initialisation Vector n Offset */ 275 #define AES_HASHKEY_REG_OFST _UINT32_(0x5C) /* (AES_HASHKEY) Hash key n Offset */ 276 #define AES_HASHKEY0_REG_OFST _UINT32_(0x5C) /* (AES_HASHKEY0) Hash key n Offset */ 277 #define AES_HASHKEY1_REG_OFST _UINT32_(0x60) /* (AES_HASHKEY1) Hash key n Offset */ 278 #define AES_HASHKEY2_REG_OFST _UINT32_(0x64) /* (AES_HASHKEY2) Hash key n Offset */ 279 #define AES_HASHKEY3_REG_OFST _UINT32_(0x68) /* (AES_HASHKEY3) Hash key n Offset */ 280 #define AES_GHASH_REG_OFST _UINT32_(0x6C) /* (AES_GHASH) Galois Hash n Offset */ 281 #define AES_GHASH0_REG_OFST _UINT32_(0x6C) /* (AES_GHASH0) Galois Hash n Offset */ 282 #define AES_GHASH1_REG_OFST _UINT32_(0x70) /* (AES_GHASH1) Galois Hash n Offset */ 283 #define AES_GHASH2_REG_OFST _UINT32_(0x74) /* (AES_GHASH2) Galois Hash n Offset */ 284 #define AES_GHASH3_REG_OFST _UINT32_(0x78) /* (AES_GHASH3) Galois Hash n Offset */ 285 #define AES_CIPLEN_REG_OFST _UINT32_(0x80) /* (AES_CIPLEN) Cipher Length Offset */ 286 #define AES_RANDSEED_REG_OFST _UINT32_(0x84) /* (AES_RANDSEED) Random Seed Offset */ 287 288 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 289 /** \brief AES register API structure */ 290 typedef struct 291 { /* Advanced Encryption Standard */ 292 __IO uint32_t AES_CTRLA; /**< Offset: 0x00 (R/W 32) Control A */ 293 __IO uint8_t AES_CTRLB; /**< Offset: 0x04 (R/W 8) Control B */ 294 __IO uint8_t AES_INTENCLR; /**< Offset: 0x05 (R/W 8) Interrupt Enable Clear */ 295 __IO uint8_t AES_INTENSET; /**< Offset: 0x06 (R/W 8) Interrupt Enable Set */ 296 __IO uint8_t AES_INTFLAG; /**< Offset: 0x07 (R/W 8) Interrupt Flag Status */ 297 __IO uint8_t AES_DATABUFPTR; /**< Offset: 0x08 (R/W 8) Data buffer pointer */ 298 __IO uint8_t AES_DBGCTRL; /**< Offset: 0x09 (R/W 8) Debug control */ 299 __I uint8_t Reserved1[0x02]; 300 __O uint32_t AES_KEYWORD[8]; /**< Offset: 0x0C ( /W 32) Keyword n */ 301 __I uint8_t Reserved2[0x0C]; 302 __IO uint32_t AES_INDATA; /**< Offset: 0x38 (R/W 32) Indata */ 303 __O uint32_t AES_INTVECTV[4]; /**< Offset: 0x3C ( /W 32) Initialisation Vector n */ 304 __I uint8_t Reserved3[0x10]; 305 __IO uint32_t AES_HASHKEY[4]; /**< Offset: 0x5C (R/W 32) Hash key n */ 306 __IO uint32_t AES_GHASH[4]; /**< Offset: 0x6C (R/W 32) Galois Hash n */ 307 __I uint8_t Reserved4[0x04]; 308 __IO uint32_t AES_CIPLEN; /**< Offset: 0x80 (R/W 32) Cipher Length */ 309 __IO uint32_t AES_RANDSEED; /**< Offset: 0x84 (R/W 32) Random Seed */ 310 } aes_registers_t; 311 312 313 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 314 #endif /* _PIC32CXSG61_AES_COMPONENT_H_ */ 315
