1 /* 2 * Component description for USB 3 * 4 * Copyright (c) 2023 Microchip Technology Inc. and its subsidiaries. 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 */ 19 20 /* file generated from device description file (ATDF) version 2023-03-17T09:48:46Z */ 21 #ifndef _PIC32CXSG60_USB_COMPONENT_H_ 22 #define _PIC32CXSG60_USB_COMPONENT_H_ 23 24 /* ************************************************************************** */ 25 /* SOFTWARE API DEFINITION FOR USB */ 26 /* ************************************************************************** */ 27 28 /* -------- USB_DEVICE_ADDR : (USB Offset: 0x00) (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer -------- */ 29 #define USB_DEVICE_ADDR_ADDR_Pos _UINT32_(0) /* (USB_DEVICE_ADDR) Adress of data buffer Position */ 30 #define USB_DEVICE_ADDR_ADDR_Msk (_UINT32_(0xFFFFFFFF) << USB_DEVICE_ADDR_ADDR_Pos) /* (USB_DEVICE_ADDR) Adress of data buffer Mask */ 31 #define USB_DEVICE_ADDR_ADDR(value) (USB_DEVICE_ADDR_ADDR_Msk & (_UINT32_(value) << USB_DEVICE_ADDR_ADDR_Pos)) /* Assigment of value for ADDR in the USB_DEVICE_ADDR register */ 32 #define USB_DEVICE_ADDR_Msk _UINT32_(0xFFFFFFFF) /* (USB_DEVICE_ADDR) Register Mask */ 33 34 35 /* -------- USB_DEVICE_PCKSIZE : (USB Offset: 0x04) (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Packet Size -------- */ 36 #define USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos _UINT32_(0) /* (USB_DEVICE_PCKSIZE) Byte Count Position */ 37 #define USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk (_UINT32_(0x3FFF) << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos) /* (USB_DEVICE_PCKSIZE) Byte Count Mask */ 38 #define USB_DEVICE_PCKSIZE_BYTE_COUNT(value) (USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk & (_UINT32_(value) << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos)) /* Assigment of value for BYTE_COUNT in the USB_DEVICE_PCKSIZE register */ 39 #define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos _UINT32_(14) /* (USB_DEVICE_PCKSIZE) Multi Packet In or Out size Position */ 40 #define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk (_UINT32_(0x3FFF) << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos) /* (USB_DEVICE_PCKSIZE) Multi Packet In or Out size Mask */ 41 #define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(value) (USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk & (_UINT32_(value) << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos)) /* Assigment of value for MULTI_PACKET_SIZE in the USB_DEVICE_PCKSIZE register */ 42 #define USB_DEVICE_PCKSIZE_SIZE_Pos _UINT32_(28) /* (USB_DEVICE_PCKSIZE) Enpoint size Position */ 43 #define USB_DEVICE_PCKSIZE_SIZE_Msk (_UINT32_(0x7) << USB_DEVICE_PCKSIZE_SIZE_Pos) /* (USB_DEVICE_PCKSIZE) Enpoint size Mask */ 44 #define USB_DEVICE_PCKSIZE_SIZE(value) (USB_DEVICE_PCKSIZE_SIZE_Msk & (_UINT32_(value) << USB_DEVICE_PCKSIZE_SIZE_Pos)) /* Assigment of value for SIZE in the USB_DEVICE_PCKSIZE register */ 45 #define USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos _UINT32_(31) /* (USB_DEVICE_PCKSIZE) Automatic Zero Length Packet Position */ 46 #define USB_DEVICE_PCKSIZE_AUTO_ZLP_Msk (_UINT32_(0x1) << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos) /* (USB_DEVICE_PCKSIZE) Automatic Zero Length Packet Mask */ 47 #define USB_DEVICE_PCKSIZE_AUTO_ZLP(value) (USB_DEVICE_PCKSIZE_AUTO_ZLP_Msk & (_UINT32_(value) << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos)) /* Assigment of value for AUTO_ZLP in the USB_DEVICE_PCKSIZE register */ 48 #define USB_DEVICE_PCKSIZE_Msk _UINT32_(0xFFFFFFFF) /* (USB_DEVICE_PCKSIZE) Register Mask */ 49 50 51 /* -------- USB_DEVICE_EXTREG : (USB Offset: 0x08) (R/W 16) DEVICE_DESC_BANK Endpoint Bank, Extended -------- */ 52 #define USB_DEVICE_EXTREG_SUBPID_Pos _UINT16_(0) /* (USB_DEVICE_EXTREG) SUBPID field send with extended token Position */ 53 #define USB_DEVICE_EXTREG_SUBPID_Msk (_UINT16_(0xF) << USB_DEVICE_EXTREG_SUBPID_Pos) /* (USB_DEVICE_EXTREG) SUBPID field send with extended token Mask */ 54 #define USB_DEVICE_EXTREG_SUBPID(value) (USB_DEVICE_EXTREG_SUBPID_Msk & (_UINT16_(value) << USB_DEVICE_EXTREG_SUBPID_Pos)) /* Assigment of value for SUBPID in the USB_DEVICE_EXTREG register */ 55 #define USB_DEVICE_EXTREG_VARIABLE_Pos _UINT16_(4) /* (USB_DEVICE_EXTREG) Variable field send with extended token Position */ 56 #define USB_DEVICE_EXTREG_VARIABLE_Msk (_UINT16_(0x7FF) << USB_DEVICE_EXTREG_VARIABLE_Pos) /* (USB_DEVICE_EXTREG) Variable field send with extended token Mask */ 57 #define USB_DEVICE_EXTREG_VARIABLE(value) (USB_DEVICE_EXTREG_VARIABLE_Msk & (_UINT16_(value) << USB_DEVICE_EXTREG_VARIABLE_Pos)) /* Assigment of value for VARIABLE in the USB_DEVICE_EXTREG register */ 58 #define USB_DEVICE_EXTREG_Msk _UINT16_(0x7FFF) /* (USB_DEVICE_EXTREG) Register Mask */ 59 60 61 /* -------- USB_DEVICE_STATUS_BK : (USB Offset: 0x0A) (R/W 8) DEVICE_DESC_BANK Enpoint Bank, Status of Bank -------- */ 62 #define USB_DEVICE_STATUS_BK_CRCERR_Pos _UINT8_(0) /* (USB_DEVICE_STATUS_BK) CRC Error Status Position */ 63 #define USB_DEVICE_STATUS_BK_CRCERR_Msk (_UINT8_(0x1) << USB_DEVICE_STATUS_BK_CRCERR_Pos) /* (USB_DEVICE_STATUS_BK) CRC Error Status Mask */ 64 #define USB_DEVICE_STATUS_BK_CRCERR(value) (USB_DEVICE_STATUS_BK_CRCERR_Msk & (_UINT8_(value) << USB_DEVICE_STATUS_BK_CRCERR_Pos)) /* Assigment of value for CRCERR in the USB_DEVICE_STATUS_BK register */ 65 #define USB_DEVICE_STATUS_BK_ERRORFLOW_Pos _UINT8_(1) /* (USB_DEVICE_STATUS_BK) Error Flow Status Position */ 66 #define USB_DEVICE_STATUS_BK_ERRORFLOW_Msk (_UINT8_(0x1) << USB_DEVICE_STATUS_BK_ERRORFLOW_Pos) /* (USB_DEVICE_STATUS_BK) Error Flow Status Mask */ 67 #define USB_DEVICE_STATUS_BK_ERRORFLOW(value) (USB_DEVICE_STATUS_BK_ERRORFLOW_Msk & (_UINT8_(value) << USB_DEVICE_STATUS_BK_ERRORFLOW_Pos)) /* Assigment of value for ERRORFLOW in the USB_DEVICE_STATUS_BK register */ 68 #define USB_DEVICE_STATUS_BK_Msk _UINT8_(0x03) /* (USB_DEVICE_STATUS_BK) Register Mask */ 69 70 71 /* -------- USB_HOST_ADDR : (USB Offset: 0x00) (R/W 32) HOST_DESC_BANK Host Bank, Adress of Data Buffer -------- */ 72 #define USB_HOST_ADDR_ADDR_Pos _UINT32_(0) /* (USB_HOST_ADDR) Adress of data buffer Position */ 73 #define USB_HOST_ADDR_ADDR_Msk (_UINT32_(0xFFFFFFFF) << USB_HOST_ADDR_ADDR_Pos) /* (USB_HOST_ADDR) Adress of data buffer Mask */ 74 #define USB_HOST_ADDR_ADDR(value) (USB_HOST_ADDR_ADDR_Msk & (_UINT32_(value) << USB_HOST_ADDR_ADDR_Pos)) /* Assigment of value for ADDR in the USB_HOST_ADDR register */ 75 #define USB_HOST_ADDR_Msk _UINT32_(0xFFFFFFFF) /* (USB_HOST_ADDR) Register Mask */ 76 77 78 /* -------- USB_HOST_PCKSIZE : (USB Offset: 0x04) (R/W 32) HOST_DESC_BANK Host Bank, Packet Size -------- */ 79 #define USB_HOST_PCKSIZE_BYTE_COUNT_Pos _UINT32_(0) /* (USB_HOST_PCKSIZE) Byte Count Position */ 80 #define USB_HOST_PCKSIZE_BYTE_COUNT_Msk (_UINT32_(0x3FFF) << USB_HOST_PCKSIZE_BYTE_COUNT_Pos) /* (USB_HOST_PCKSIZE) Byte Count Mask */ 81 #define USB_HOST_PCKSIZE_BYTE_COUNT(value) (USB_HOST_PCKSIZE_BYTE_COUNT_Msk & (_UINT32_(value) << USB_HOST_PCKSIZE_BYTE_COUNT_Pos)) /* Assigment of value for BYTE_COUNT in the USB_HOST_PCKSIZE register */ 82 #define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos _UINT32_(14) /* (USB_HOST_PCKSIZE) Multi Packet In or Out size Position */ 83 #define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk (_UINT32_(0x3FFF) << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos) /* (USB_HOST_PCKSIZE) Multi Packet In or Out size Mask */ 84 #define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(value) (USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk & (_UINT32_(value) << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos)) /* Assigment of value for MULTI_PACKET_SIZE in the USB_HOST_PCKSIZE register */ 85 #define USB_HOST_PCKSIZE_SIZE_Pos _UINT32_(28) /* (USB_HOST_PCKSIZE) Pipe size Position */ 86 #define USB_HOST_PCKSIZE_SIZE_Msk (_UINT32_(0x7) << USB_HOST_PCKSIZE_SIZE_Pos) /* (USB_HOST_PCKSIZE) Pipe size Mask */ 87 #define USB_HOST_PCKSIZE_SIZE(value) (USB_HOST_PCKSIZE_SIZE_Msk & (_UINT32_(value) << USB_HOST_PCKSIZE_SIZE_Pos)) /* Assigment of value for SIZE in the USB_HOST_PCKSIZE register */ 88 #define USB_HOST_PCKSIZE_AUTO_ZLP_Pos _UINT32_(31) /* (USB_HOST_PCKSIZE) Automatic Zero Length Packet Position */ 89 #define USB_HOST_PCKSIZE_AUTO_ZLP_Msk (_UINT32_(0x1) << USB_HOST_PCKSIZE_AUTO_ZLP_Pos) /* (USB_HOST_PCKSIZE) Automatic Zero Length Packet Mask */ 90 #define USB_HOST_PCKSIZE_AUTO_ZLP(value) (USB_HOST_PCKSIZE_AUTO_ZLP_Msk & (_UINT32_(value) << USB_HOST_PCKSIZE_AUTO_ZLP_Pos)) /* Assigment of value for AUTO_ZLP in the USB_HOST_PCKSIZE register */ 91 #define USB_HOST_PCKSIZE_Msk _UINT32_(0xFFFFFFFF) /* (USB_HOST_PCKSIZE) Register Mask */ 92 93 94 /* -------- USB_HOST_EXTREG : (USB Offset: 0x08) (R/W 16) HOST_DESC_BANK Host Bank, Extended -------- */ 95 #define USB_HOST_EXTREG_SUBPID_Pos _UINT16_(0) /* (USB_HOST_EXTREG) SUBPID field send with extended token Position */ 96 #define USB_HOST_EXTREG_SUBPID_Msk (_UINT16_(0xF) << USB_HOST_EXTREG_SUBPID_Pos) /* (USB_HOST_EXTREG) SUBPID field send with extended token Mask */ 97 #define USB_HOST_EXTREG_SUBPID(value) (USB_HOST_EXTREG_SUBPID_Msk & (_UINT16_(value) << USB_HOST_EXTREG_SUBPID_Pos)) /* Assigment of value for SUBPID in the USB_HOST_EXTREG register */ 98 #define USB_HOST_EXTREG_VARIABLE_Pos _UINT16_(4) /* (USB_HOST_EXTREG) Variable field send with extended token Position */ 99 #define USB_HOST_EXTREG_VARIABLE_Msk (_UINT16_(0x7FF) << USB_HOST_EXTREG_VARIABLE_Pos) /* (USB_HOST_EXTREG) Variable field send with extended token Mask */ 100 #define USB_HOST_EXTREG_VARIABLE(value) (USB_HOST_EXTREG_VARIABLE_Msk & (_UINT16_(value) << USB_HOST_EXTREG_VARIABLE_Pos)) /* Assigment of value for VARIABLE in the USB_HOST_EXTREG register */ 101 #define USB_HOST_EXTREG_Msk _UINT16_(0x7FFF) /* (USB_HOST_EXTREG) Register Mask */ 102 103 104 /* -------- USB_HOST_STATUS_BK : (USB Offset: 0x0A) (R/W 8) HOST_DESC_BANK Host Bank, Status of Bank -------- */ 105 #define USB_HOST_STATUS_BK_CRCERR_Pos _UINT8_(0) /* (USB_HOST_STATUS_BK) CRC Error Status Position */ 106 #define USB_HOST_STATUS_BK_CRCERR_Msk (_UINT8_(0x1) << USB_HOST_STATUS_BK_CRCERR_Pos) /* (USB_HOST_STATUS_BK) CRC Error Status Mask */ 107 #define USB_HOST_STATUS_BK_CRCERR(value) (USB_HOST_STATUS_BK_CRCERR_Msk & (_UINT8_(value) << USB_HOST_STATUS_BK_CRCERR_Pos)) /* Assigment of value for CRCERR in the USB_HOST_STATUS_BK register */ 108 #define USB_HOST_STATUS_BK_ERRORFLOW_Pos _UINT8_(1) /* (USB_HOST_STATUS_BK) Error Flow Status Position */ 109 #define USB_HOST_STATUS_BK_ERRORFLOW_Msk (_UINT8_(0x1) << USB_HOST_STATUS_BK_ERRORFLOW_Pos) /* (USB_HOST_STATUS_BK) Error Flow Status Mask */ 110 #define USB_HOST_STATUS_BK_ERRORFLOW(value) (USB_HOST_STATUS_BK_ERRORFLOW_Msk & (_UINT8_(value) << USB_HOST_STATUS_BK_ERRORFLOW_Pos)) /* Assigment of value for ERRORFLOW in the USB_HOST_STATUS_BK register */ 111 #define USB_HOST_STATUS_BK_Msk _UINT8_(0x03) /* (USB_HOST_STATUS_BK) Register Mask */ 112 113 114 /* -------- USB_HOST_CTRL_PIPE : (USB Offset: 0x0C) (R/W 16) HOST_DESC_BANK Host Bank, Host Control Pipe -------- */ 115 #define USB_HOST_CTRL_PIPE_RESETVALUE _UINT16_(0x00) /* (USB_HOST_CTRL_PIPE) HOST_DESC_BANK Host Bank, Host Control Pipe Reset Value */ 116 117 #define USB_HOST_CTRL_PIPE_PDADDR_Pos _UINT16_(0) /* (USB_HOST_CTRL_PIPE) Pipe Device Adress Position */ 118 #define USB_HOST_CTRL_PIPE_PDADDR_Msk (_UINT16_(0x7F) << USB_HOST_CTRL_PIPE_PDADDR_Pos) /* (USB_HOST_CTRL_PIPE) Pipe Device Adress Mask */ 119 #define USB_HOST_CTRL_PIPE_PDADDR(value) (USB_HOST_CTRL_PIPE_PDADDR_Msk & (_UINT16_(value) << USB_HOST_CTRL_PIPE_PDADDR_Pos)) /* Assigment of value for PDADDR in the USB_HOST_CTRL_PIPE register */ 120 #define USB_HOST_CTRL_PIPE_PEPNUM_Pos _UINT16_(8) /* (USB_HOST_CTRL_PIPE) Pipe Endpoint Number Position */ 121 #define USB_HOST_CTRL_PIPE_PEPNUM_Msk (_UINT16_(0xF) << USB_HOST_CTRL_PIPE_PEPNUM_Pos) /* (USB_HOST_CTRL_PIPE) Pipe Endpoint Number Mask */ 122 #define USB_HOST_CTRL_PIPE_PEPNUM(value) (USB_HOST_CTRL_PIPE_PEPNUM_Msk & (_UINT16_(value) << USB_HOST_CTRL_PIPE_PEPNUM_Pos)) /* Assigment of value for PEPNUM in the USB_HOST_CTRL_PIPE register */ 123 #define USB_HOST_CTRL_PIPE_PERMAX_Pos _UINT16_(12) /* (USB_HOST_CTRL_PIPE) Pipe Error Max Number Position */ 124 #define USB_HOST_CTRL_PIPE_PERMAX_Msk (_UINT16_(0xF) << USB_HOST_CTRL_PIPE_PERMAX_Pos) /* (USB_HOST_CTRL_PIPE) Pipe Error Max Number Mask */ 125 #define USB_HOST_CTRL_PIPE_PERMAX(value) (USB_HOST_CTRL_PIPE_PERMAX_Msk & (_UINT16_(value) << USB_HOST_CTRL_PIPE_PERMAX_Pos)) /* Assigment of value for PERMAX in the USB_HOST_CTRL_PIPE register */ 126 #define USB_HOST_CTRL_PIPE_Msk _UINT16_(0xFF7F) /* (USB_HOST_CTRL_PIPE) Register Mask */ 127 128 129 /* -------- USB_HOST_STATUS_PIPE : (USB Offset: 0x0E) (R/W 16) HOST_DESC_BANK Host Bank, Host Status Pipe -------- */ 130 #define USB_HOST_STATUS_PIPE_DTGLER_Pos _UINT16_(0) /* (USB_HOST_STATUS_PIPE) Data Toggle Error Position */ 131 #define USB_HOST_STATUS_PIPE_DTGLER_Msk (_UINT16_(0x1) << USB_HOST_STATUS_PIPE_DTGLER_Pos) /* (USB_HOST_STATUS_PIPE) Data Toggle Error Mask */ 132 #define USB_HOST_STATUS_PIPE_DTGLER(value) (USB_HOST_STATUS_PIPE_DTGLER_Msk & (_UINT16_(value) << USB_HOST_STATUS_PIPE_DTGLER_Pos)) /* Assigment of value for DTGLER in the USB_HOST_STATUS_PIPE register */ 133 #define USB_HOST_STATUS_PIPE_DAPIDER_Pos _UINT16_(1) /* (USB_HOST_STATUS_PIPE) Data PID Error Position */ 134 #define USB_HOST_STATUS_PIPE_DAPIDER_Msk (_UINT16_(0x1) << USB_HOST_STATUS_PIPE_DAPIDER_Pos) /* (USB_HOST_STATUS_PIPE) Data PID Error Mask */ 135 #define USB_HOST_STATUS_PIPE_DAPIDER(value) (USB_HOST_STATUS_PIPE_DAPIDER_Msk & (_UINT16_(value) << USB_HOST_STATUS_PIPE_DAPIDER_Pos)) /* Assigment of value for DAPIDER in the USB_HOST_STATUS_PIPE register */ 136 #define USB_HOST_STATUS_PIPE_PIDER_Pos _UINT16_(2) /* (USB_HOST_STATUS_PIPE) PID Error Position */ 137 #define USB_HOST_STATUS_PIPE_PIDER_Msk (_UINT16_(0x1) << USB_HOST_STATUS_PIPE_PIDER_Pos) /* (USB_HOST_STATUS_PIPE) PID Error Mask */ 138 #define USB_HOST_STATUS_PIPE_PIDER(value) (USB_HOST_STATUS_PIPE_PIDER_Msk & (_UINT16_(value) << USB_HOST_STATUS_PIPE_PIDER_Pos)) /* Assigment of value for PIDER in the USB_HOST_STATUS_PIPE register */ 139 #define USB_HOST_STATUS_PIPE_TOUTER_Pos _UINT16_(3) /* (USB_HOST_STATUS_PIPE) Time Out Error Position */ 140 #define USB_HOST_STATUS_PIPE_TOUTER_Msk (_UINT16_(0x1) << USB_HOST_STATUS_PIPE_TOUTER_Pos) /* (USB_HOST_STATUS_PIPE) Time Out Error Mask */ 141 #define USB_HOST_STATUS_PIPE_TOUTER(value) (USB_HOST_STATUS_PIPE_TOUTER_Msk & (_UINT16_(value) << USB_HOST_STATUS_PIPE_TOUTER_Pos)) /* Assigment of value for TOUTER in the USB_HOST_STATUS_PIPE register */ 142 #define USB_HOST_STATUS_PIPE_CRC16ER_Pos _UINT16_(4) /* (USB_HOST_STATUS_PIPE) CRC16 Error Position */ 143 #define USB_HOST_STATUS_PIPE_CRC16ER_Msk (_UINT16_(0x1) << USB_HOST_STATUS_PIPE_CRC16ER_Pos) /* (USB_HOST_STATUS_PIPE) CRC16 Error Mask */ 144 #define USB_HOST_STATUS_PIPE_CRC16ER(value) (USB_HOST_STATUS_PIPE_CRC16ER_Msk & (_UINT16_(value) << USB_HOST_STATUS_PIPE_CRC16ER_Pos)) /* Assigment of value for CRC16ER in the USB_HOST_STATUS_PIPE register */ 145 #define USB_HOST_STATUS_PIPE_ERCNT_Pos _UINT16_(5) /* (USB_HOST_STATUS_PIPE) Pipe Error Count Position */ 146 #define USB_HOST_STATUS_PIPE_ERCNT_Msk (_UINT16_(0x7) << USB_HOST_STATUS_PIPE_ERCNT_Pos) /* (USB_HOST_STATUS_PIPE) Pipe Error Count Mask */ 147 #define USB_HOST_STATUS_PIPE_ERCNT(value) (USB_HOST_STATUS_PIPE_ERCNT_Msk & (_UINT16_(value) << USB_HOST_STATUS_PIPE_ERCNT_Pos)) /* Assigment of value for ERCNT in the USB_HOST_STATUS_PIPE register */ 148 #define USB_HOST_STATUS_PIPE_Msk _UINT16_(0x00FF) /* (USB_HOST_STATUS_PIPE) Register Mask */ 149 150 151 /* -------- USB_DEVICE_EPCFG : (USB Offset: 0x00) (R/W 8) DEVICE_ENDPOINT End Point Configuration -------- */ 152 #define USB_DEVICE_EPCFG_RESETVALUE _UINT8_(0x00) /* (USB_DEVICE_EPCFG) DEVICE_ENDPOINT End Point Configuration Reset Value */ 153 154 #define USB_DEVICE_EPCFG_EPTYPE0_Pos _UINT8_(0) /* (USB_DEVICE_EPCFG) End Point Type0 Position */ 155 #define USB_DEVICE_EPCFG_EPTYPE0_Msk (_UINT8_(0x7) << USB_DEVICE_EPCFG_EPTYPE0_Pos) /* (USB_DEVICE_EPCFG) End Point Type0 Mask */ 156 #define USB_DEVICE_EPCFG_EPTYPE0(value) (USB_DEVICE_EPCFG_EPTYPE0_Msk & (_UINT8_(value) << USB_DEVICE_EPCFG_EPTYPE0_Pos)) /* Assigment of value for EPTYPE0 in the USB_DEVICE_EPCFG register */ 157 #define USB_DEVICE_EPCFG_EPTYPE1_Pos _UINT8_(4) /* (USB_DEVICE_EPCFG) End Point Type1 Position */ 158 #define USB_DEVICE_EPCFG_EPTYPE1_Msk (_UINT8_(0x7) << USB_DEVICE_EPCFG_EPTYPE1_Pos) /* (USB_DEVICE_EPCFG) End Point Type1 Mask */ 159 #define USB_DEVICE_EPCFG_EPTYPE1(value) (USB_DEVICE_EPCFG_EPTYPE1_Msk & (_UINT8_(value) << USB_DEVICE_EPCFG_EPTYPE1_Pos)) /* Assigment of value for EPTYPE1 in the USB_DEVICE_EPCFG register */ 160 #define USB_DEVICE_EPCFG_Msk _UINT8_(0x77) /* (USB_DEVICE_EPCFG) Register Mask */ 161 162 163 /* -------- USB_DEVICE_EPSTATUSCLR : (USB Offset: 0x04) ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Clear -------- */ 164 #define USB_DEVICE_EPSTATUSCLR_RESETVALUE _UINT8_(0x00) /* (USB_DEVICE_EPSTATUSCLR) DEVICE_ENDPOINT End Point Pipe Status Clear Reset Value */ 165 166 #define USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos _UINT8_(0) /* (USB_DEVICE_EPSTATUSCLR) Data Toggle OUT Clear Position */ 167 #define USB_DEVICE_EPSTATUSCLR_DTGLOUT_Msk (_UINT8_(0x1) << USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos) /* (USB_DEVICE_EPSTATUSCLR) Data Toggle OUT Clear Mask */ 168 #define USB_DEVICE_EPSTATUSCLR_DTGLOUT(value) (USB_DEVICE_EPSTATUSCLR_DTGLOUT_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos)) /* Assigment of value for DTGLOUT in the USB_DEVICE_EPSTATUSCLR register */ 169 #define USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos _UINT8_(1) /* (USB_DEVICE_EPSTATUSCLR) Data Toggle IN Clear Position */ 170 #define USB_DEVICE_EPSTATUSCLR_DTGLIN_Msk (_UINT8_(0x1) << USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos) /* (USB_DEVICE_EPSTATUSCLR) Data Toggle IN Clear Mask */ 171 #define USB_DEVICE_EPSTATUSCLR_DTGLIN(value) (USB_DEVICE_EPSTATUSCLR_DTGLIN_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos)) /* Assigment of value for DTGLIN in the USB_DEVICE_EPSTATUSCLR register */ 172 #define USB_DEVICE_EPSTATUSCLR_CURBK_Pos _UINT8_(2) /* (USB_DEVICE_EPSTATUSCLR) Current Bank Clear Position */ 173 #define USB_DEVICE_EPSTATUSCLR_CURBK_Msk (_UINT8_(0x1) << USB_DEVICE_EPSTATUSCLR_CURBK_Pos) /* (USB_DEVICE_EPSTATUSCLR) Current Bank Clear Mask */ 174 #define USB_DEVICE_EPSTATUSCLR_CURBK(value) (USB_DEVICE_EPSTATUSCLR_CURBK_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUSCLR_CURBK_Pos)) /* Assigment of value for CURBK in the USB_DEVICE_EPSTATUSCLR register */ 175 #define USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos _UINT8_(4) /* (USB_DEVICE_EPSTATUSCLR) Stall 0 Request Clear Position */ 176 #define USB_DEVICE_EPSTATUSCLR_STALLRQ0_Msk (_UINT8_(0x1) << USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos) /* (USB_DEVICE_EPSTATUSCLR) Stall 0 Request Clear Mask */ 177 #define USB_DEVICE_EPSTATUSCLR_STALLRQ0(value) (USB_DEVICE_EPSTATUSCLR_STALLRQ0_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos)) /* Assigment of value for STALLRQ0 in the USB_DEVICE_EPSTATUSCLR register */ 178 #define USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos _UINT8_(5) /* (USB_DEVICE_EPSTATUSCLR) Stall 1 Request Clear Position */ 179 #define USB_DEVICE_EPSTATUSCLR_STALLRQ1_Msk (_UINT8_(0x1) << USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos) /* (USB_DEVICE_EPSTATUSCLR) Stall 1 Request Clear Mask */ 180 #define USB_DEVICE_EPSTATUSCLR_STALLRQ1(value) (USB_DEVICE_EPSTATUSCLR_STALLRQ1_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos)) /* Assigment of value for STALLRQ1 in the USB_DEVICE_EPSTATUSCLR register */ 181 #define USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos _UINT8_(6) /* (USB_DEVICE_EPSTATUSCLR) Bank 0 Ready Clear Position */ 182 #define USB_DEVICE_EPSTATUSCLR_BK0RDY_Msk (_UINT8_(0x1) << USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos) /* (USB_DEVICE_EPSTATUSCLR) Bank 0 Ready Clear Mask */ 183 #define USB_DEVICE_EPSTATUSCLR_BK0RDY(value) (USB_DEVICE_EPSTATUSCLR_BK0RDY_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos)) /* Assigment of value for BK0RDY in the USB_DEVICE_EPSTATUSCLR register */ 184 #define USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos _UINT8_(7) /* (USB_DEVICE_EPSTATUSCLR) Bank 1 Ready Clear Position */ 185 #define USB_DEVICE_EPSTATUSCLR_BK1RDY_Msk (_UINT8_(0x1) << USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos) /* (USB_DEVICE_EPSTATUSCLR) Bank 1 Ready Clear Mask */ 186 #define USB_DEVICE_EPSTATUSCLR_BK1RDY(value) (USB_DEVICE_EPSTATUSCLR_BK1RDY_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos)) /* Assigment of value for BK1RDY in the USB_DEVICE_EPSTATUSCLR register */ 187 #define USB_DEVICE_EPSTATUSCLR_Msk _UINT8_(0xF7) /* (USB_DEVICE_EPSTATUSCLR) Register Mask */ 188 189 #define USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos _UINT8_(4) /* (USB_DEVICE_EPSTATUSCLR Position) Stall x Request Clear */ 190 #define USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk (_UINT8_(0x3) << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos) /* (USB_DEVICE_EPSTATUSCLR Mask) STALLRQ */ 191 #define USB_DEVICE_EPSTATUSCLR_STALLRQ(value) (USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos)) 192 193 /* -------- USB_DEVICE_EPSTATUSSET : (USB Offset: 0x05) ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Set -------- */ 194 #define USB_DEVICE_EPSTATUSSET_RESETVALUE _UINT8_(0x00) /* (USB_DEVICE_EPSTATUSSET) DEVICE_ENDPOINT End Point Pipe Status Set Reset Value */ 195 196 #define USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos _UINT8_(0) /* (USB_DEVICE_EPSTATUSSET) Data Toggle OUT Set Position */ 197 #define USB_DEVICE_EPSTATUSSET_DTGLOUT_Msk (_UINT8_(0x1) << USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos) /* (USB_DEVICE_EPSTATUSSET) Data Toggle OUT Set Mask */ 198 #define USB_DEVICE_EPSTATUSSET_DTGLOUT(value) (USB_DEVICE_EPSTATUSSET_DTGLOUT_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos)) /* Assigment of value for DTGLOUT in the USB_DEVICE_EPSTATUSSET register */ 199 #define USB_DEVICE_EPSTATUSSET_DTGLIN_Pos _UINT8_(1) /* (USB_DEVICE_EPSTATUSSET) Data Toggle IN Set Position */ 200 #define USB_DEVICE_EPSTATUSSET_DTGLIN_Msk (_UINT8_(0x1) << USB_DEVICE_EPSTATUSSET_DTGLIN_Pos) /* (USB_DEVICE_EPSTATUSSET) Data Toggle IN Set Mask */ 201 #define USB_DEVICE_EPSTATUSSET_DTGLIN(value) (USB_DEVICE_EPSTATUSSET_DTGLIN_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUSSET_DTGLIN_Pos)) /* Assigment of value for DTGLIN in the USB_DEVICE_EPSTATUSSET register */ 202 #define USB_DEVICE_EPSTATUSSET_CURBK_Pos _UINT8_(2) /* (USB_DEVICE_EPSTATUSSET) Current Bank Set Position */ 203 #define USB_DEVICE_EPSTATUSSET_CURBK_Msk (_UINT8_(0x1) << USB_DEVICE_EPSTATUSSET_CURBK_Pos) /* (USB_DEVICE_EPSTATUSSET) Current Bank Set Mask */ 204 #define USB_DEVICE_EPSTATUSSET_CURBK(value) (USB_DEVICE_EPSTATUSSET_CURBK_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUSSET_CURBK_Pos)) /* Assigment of value for CURBK in the USB_DEVICE_EPSTATUSSET register */ 205 #define USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos _UINT8_(4) /* (USB_DEVICE_EPSTATUSSET) Stall 0 Request Set Position */ 206 #define USB_DEVICE_EPSTATUSSET_STALLRQ0_Msk (_UINT8_(0x1) << USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos) /* (USB_DEVICE_EPSTATUSSET) Stall 0 Request Set Mask */ 207 #define USB_DEVICE_EPSTATUSSET_STALLRQ0(value) (USB_DEVICE_EPSTATUSSET_STALLRQ0_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos)) /* Assigment of value for STALLRQ0 in the USB_DEVICE_EPSTATUSSET register */ 208 #define USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos _UINT8_(5) /* (USB_DEVICE_EPSTATUSSET) Stall 1 Request Set Position */ 209 #define USB_DEVICE_EPSTATUSSET_STALLRQ1_Msk (_UINT8_(0x1) << USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos) /* (USB_DEVICE_EPSTATUSSET) Stall 1 Request Set Mask */ 210 #define USB_DEVICE_EPSTATUSSET_STALLRQ1(value) (USB_DEVICE_EPSTATUSSET_STALLRQ1_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos)) /* Assigment of value for STALLRQ1 in the USB_DEVICE_EPSTATUSSET register */ 211 #define USB_DEVICE_EPSTATUSSET_BK0RDY_Pos _UINT8_(6) /* (USB_DEVICE_EPSTATUSSET) Bank 0 Ready Set Position */ 212 #define USB_DEVICE_EPSTATUSSET_BK0RDY_Msk (_UINT8_(0x1) << USB_DEVICE_EPSTATUSSET_BK0RDY_Pos) /* (USB_DEVICE_EPSTATUSSET) Bank 0 Ready Set Mask */ 213 #define USB_DEVICE_EPSTATUSSET_BK0RDY(value) (USB_DEVICE_EPSTATUSSET_BK0RDY_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUSSET_BK0RDY_Pos)) /* Assigment of value for BK0RDY in the USB_DEVICE_EPSTATUSSET register */ 214 #define USB_DEVICE_EPSTATUSSET_BK1RDY_Pos _UINT8_(7) /* (USB_DEVICE_EPSTATUSSET) Bank 1 Ready Set Position */ 215 #define USB_DEVICE_EPSTATUSSET_BK1RDY_Msk (_UINT8_(0x1) << USB_DEVICE_EPSTATUSSET_BK1RDY_Pos) /* (USB_DEVICE_EPSTATUSSET) Bank 1 Ready Set Mask */ 216 #define USB_DEVICE_EPSTATUSSET_BK1RDY(value) (USB_DEVICE_EPSTATUSSET_BK1RDY_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUSSET_BK1RDY_Pos)) /* Assigment of value for BK1RDY in the USB_DEVICE_EPSTATUSSET register */ 217 #define USB_DEVICE_EPSTATUSSET_Msk _UINT8_(0xF7) /* (USB_DEVICE_EPSTATUSSET) Register Mask */ 218 219 #define USB_DEVICE_EPSTATUSSET_STALLRQ_Pos _UINT8_(4) /* (USB_DEVICE_EPSTATUSSET Position) Stall x Request Set */ 220 #define USB_DEVICE_EPSTATUSSET_STALLRQ_Msk (_UINT8_(0x3) << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos) /* (USB_DEVICE_EPSTATUSSET Mask) STALLRQ */ 221 #define USB_DEVICE_EPSTATUSSET_STALLRQ(value) (USB_DEVICE_EPSTATUSSET_STALLRQ_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos)) 222 223 /* -------- USB_DEVICE_EPSTATUS : (USB Offset: 0x06) ( R/ 8) DEVICE_ENDPOINT End Point Pipe Status -------- */ 224 #define USB_DEVICE_EPSTATUS_RESETVALUE _UINT8_(0x00) /* (USB_DEVICE_EPSTATUS) DEVICE_ENDPOINT End Point Pipe Status Reset Value */ 225 226 #define USB_DEVICE_EPSTATUS_DTGLOUT_Pos _UINT8_(0) /* (USB_DEVICE_EPSTATUS) Data Toggle Out Position */ 227 #define USB_DEVICE_EPSTATUS_DTGLOUT_Msk (_UINT8_(0x1) << USB_DEVICE_EPSTATUS_DTGLOUT_Pos) /* (USB_DEVICE_EPSTATUS) Data Toggle Out Mask */ 228 #define USB_DEVICE_EPSTATUS_DTGLOUT(value) (USB_DEVICE_EPSTATUS_DTGLOUT_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUS_DTGLOUT_Pos)) /* Assigment of value for DTGLOUT in the USB_DEVICE_EPSTATUS register */ 229 #define USB_DEVICE_EPSTATUS_DTGLIN_Pos _UINT8_(1) /* (USB_DEVICE_EPSTATUS) Data Toggle In Position */ 230 #define USB_DEVICE_EPSTATUS_DTGLIN_Msk (_UINT8_(0x1) << USB_DEVICE_EPSTATUS_DTGLIN_Pos) /* (USB_DEVICE_EPSTATUS) Data Toggle In Mask */ 231 #define USB_DEVICE_EPSTATUS_DTGLIN(value) (USB_DEVICE_EPSTATUS_DTGLIN_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUS_DTGLIN_Pos)) /* Assigment of value for DTGLIN in the USB_DEVICE_EPSTATUS register */ 232 #define USB_DEVICE_EPSTATUS_CURBK_Pos _UINT8_(2) /* (USB_DEVICE_EPSTATUS) Current Bank Position */ 233 #define USB_DEVICE_EPSTATUS_CURBK_Msk (_UINT8_(0x1) << USB_DEVICE_EPSTATUS_CURBK_Pos) /* (USB_DEVICE_EPSTATUS) Current Bank Mask */ 234 #define USB_DEVICE_EPSTATUS_CURBK(value) (USB_DEVICE_EPSTATUS_CURBK_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUS_CURBK_Pos)) /* Assigment of value for CURBK in the USB_DEVICE_EPSTATUS register */ 235 #define USB_DEVICE_EPSTATUS_STALLRQ0_Pos _UINT8_(4) /* (USB_DEVICE_EPSTATUS) Stall 0 Request Position */ 236 #define USB_DEVICE_EPSTATUS_STALLRQ0_Msk (_UINT8_(0x1) << USB_DEVICE_EPSTATUS_STALLRQ0_Pos) /* (USB_DEVICE_EPSTATUS) Stall 0 Request Mask */ 237 #define USB_DEVICE_EPSTATUS_STALLRQ0(value) (USB_DEVICE_EPSTATUS_STALLRQ0_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUS_STALLRQ0_Pos)) /* Assigment of value for STALLRQ0 in the USB_DEVICE_EPSTATUS register */ 238 #define USB_DEVICE_EPSTATUS_STALLRQ1_Pos _UINT8_(5) /* (USB_DEVICE_EPSTATUS) Stall 1 Request Position */ 239 #define USB_DEVICE_EPSTATUS_STALLRQ1_Msk (_UINT8_(0x1) << USB_DEVICE_EPSTATUS_STALLRQ1_Pos) /* (USB_DEVICE_EPSTATUS) Stall 1 Request Mask */ 240 #define USB_DEVICE_EPSTATUS_STALLRQ1(value) (USB_DEVICE_EPSTATUS_STALLRQ1_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUS_STALLRQ1_Pos)) /* Assigment of value for STALLRQ1 in the USB_DEVICE_EPSTATUS register */ 241 #define USB_DEVICE_EPSTATUS_BK0RDY_Pos _UINT8_(6) /* (USB_DEVICE_EPSTATUS) Bank 0 ready Position */ 242 #define USB_DEVICE_EPSTATUS_BK0RDY_Msk (_UINT8_(0x1) << USB_DEVICE_EPSTATUS_BK0RDY_Pos) /* (USB_DEVICE_EPSTATUS) Bank 0 ready Mask */ 243 #define USB_DEVICE_EPSTATUS_BK0RDY(value) (USB_DEVICE_EPSTATUS_BK0RDY_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUS_BK0RDY_Pos)) /* Assigment of value for BK0RDY in the USB_DEVICE_EPSTATUS register */ 244 #define USB_DEVICE_EPSTATUS_BK1RDY_Pos _UINT8_(7) /* (USB_DEVICE_EPSTATUS) Bank 1 ready Position */ 245 #define USB_DEVICE_EPSTATUS_BK1RDY_Msk (_UINT8_(0x1) << USB_DEVICE_EPSTATUS_BK1RDY_Pos) /* (USB_DEVICE_EPSTATUS) Bank 1 ready Mask */ 246 #define USB_DEVICE_EPSTATUS_BK1RDY(value) (USB_DEVICE_EPSTATUS_BK1RDY_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUS_BK1RDY_Pos)) /* Assigment of value for BK1RDY in the USB_DEVICE_EPSTATUS register */ 247 #define USB_DEVICE_EPSTATUS_Msk _UINT8_(0xF7) /* (USB_DEVICE_EPSTATUS) Register Mask */ 248 249 #define USB_DEVICE_EPSTATUS_STALLRQ_Pos _UINT8_(4) /* (USB_DEVICE_EPSTATUS Position) Stall x Request */ 250 #define USB_DEVICE_EPSTATUS_STALLRQ_Msk (_UINT8_(0x3) << USB_DEVICE_EPSTATUS_STALLRQ_Pos) /* (USB_DEVICE_EPSTATUS Mask) STALLRQ */ 251 #define USB_DEVICE_EPSTATUS_STALLRQ(value) (USB_DEVICE_EPSTATUS_STALLRQ_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUS_STALLRQ_Pos)) 252 253 /* -------- USB_DEVICE_EPINTFLAG : (USB Offset: 0x07) (R/W 8) DEVICE_ENDPOINT End Point Interrupt Flag -------- */ 254 #define USB_DEVICE_EPINTFLAG_RESETVALUE _UINT8_(0x00) /* (USB_DEVICE_EPINTFLAG) DEVICE_ENDPOINT End Point Interrupt Flag Reset Value */ 255 256 #define USB_DEVICE_EPINTFLAG_TRCPT0_Pos _UINT8_(0) /* (USB_DEVICE_EPINTFLAG) Transfer Complete 0 Position */ 257 #define USB_DEVICE_EPINTFLAG_TRCPT0_Msk (_UINT8_(0x1) << USB_DEVICE_EPINTFLAG_TRCPT0_Pos) /* (USB_DEVICE_EPINTFLAG) Transfer Complete 0 Mask */ 258 #define USB_DEVICE_EPINTFLAG_TRCPT0(value) (USB_DEVICE_EPINTFLAG_TRCPT0_Msk & (_UINT8_(value) << USB_DEVICE_EPINTFLAG_TRCPT0_Pos)) /* Assigment of value for TRCPT0 in the USB_DEVICE_EPINTFLAG register */ 259 #define USB_DEVICE_EPINTFLAG_TRCPT1_Pos _UINT8_(1) /* (USB_DEVICE_EPINTFLAG) Transfer Complete 1 Position */ 260 #define USB_DEVICE_EPINTFLAG_TRCPT1_Msk (_UINT8_(0x1) << USB_DEVICE_EPINTFLAG_TRCPT1_Pos) /* (USB_DEVICE_EPINTFLAG) Transfer Complete 1 Mask */ 261 #define USB_DEVICE_EPINTFLAG_TRCPT1(value) (USB_DEVICE_EPINTFLAG_TRCPT1_Msk & (_UINT8_(value) << USB_DEVICE_EPINTFLAG_TRCPT1_Pos)) /* Assigment of value for TRCPT1 in the USB_DEVICE_EPINTFLAG register */ 262 #define USB_DEVICE_EPINTFLAG_TRFAIL0_Pos _UINT8_(2) /* (USB_DEVICE_EPINTFLAG) Error Flow 0 Position */ 263 #define USB_DEVICE_EPINTFLAG_TRFAIL0_Msk (_UINT8_(0x1) << USB_DEVICE_EPINTFLAG_TRFAIL0_Pos) /* (USB_DEVICE_EPINTFLAG) Error Flow 0 Mask */ 264 #define USB_DEVICE_EPINTFLAG_TRFAIL0(value) (USB_DEVICE_EPINTFLAG_TRFAIL0_Msk & (_UINT8_(value) << USB_DEVICE_EPINTFLAG_TRFAIL0_Pos)) /* Assigment of value for TRFAIL0 in the USB_DEVICE_EPINTFLAG register */ 265 #define USB_DEVICE_EPINTFLAG_TRFAIL1_Pos _UINT8_(3) /* (USB_DEVICE_EPINTFLAG) Error Flow 1 Position */ 266 #define USB_DEVICE_EPINTFLAG_TRFAIL1_Msk (_UINT8_(0x1) << USB_DEVICE_EPINTFLAG_TRFAIL1_Pos) /* (USB_DEVICE_EPINTFLAG) Error Flow 1 Mask */ 267 #define USB_DEVICE_EPINTFLAG_TRFAIL1(value) (USB_DEVICE_EPINTFLAG_TRFAIL1_Msk & (_UINT8_(value) << USB_DEVICE_EPINTFLAG_TRFAIL1_Pos)) /* Assigment of value for TRFAIL1 in the USB_DEVICE_EPINTFLAG register */ 268 #define USB_DEVICE_EPINTFLAG_RXSTP_Pos _UINT8_(4) /* (USB_DEVICE_EPINTFLAG) Received Setup Position */ 269 #define USB_DEVICE_EPINTFLAG_RXSTP_Msk (_UINT8_(0x1) << USB_DEVICE_EPINTFLAG_RXSTP_Pos) /* (USB_DEVICE_EPINTFLAG) Received Setup Mask */ 270 #define USB_DEVICE_EPINTFLAG_RXSTP(value) (USB_DEVICE_EPINTFLAG_RXSTP_Msk & (_UINT8_(value) << USB_DEVICE_EPINTFLAG_RXSTP_Pos)) /* Assigment of value for RXSTP in the USB_DEVICE_EPINTFLAG register */ 271 #define USB_DEVICE_EPINTFLAG_STALL0_Pos _UINT8_(5) /* (USB_DEVICE_EPINTFLAG) Stall 0 In/out Position */ 272 #define USB_DEVICE_EPINTFLAG_STALL0_Msk (_UINT8_(0x1) << USB_DEVICE_EPINTFLAG_STALL0_Pos) /* (USB_DEVICE_EPINTFLAG) Stall 0 In/out Mask */ 273 #define USB_DEVICE_EPINTFLAG_STALL0(value) (USB_DEVICE_EPINTFLAG_STALL0_Msk & (_UINT8_(value) << USB_DEVICE_EPINTFLAG_STALL0_Pos)) /* Assigment of value for STALL0 in the USB_DEVICE_EPINTFLAG register */ 274 #define USB_DEVICE_EPINTFLAG_STALL1_Pos _UINT8_(6) /* (USB_DEVICE_EPINTFLAG) Stall 1 In/out Position */ 275 #define USB_DEVICE_EPINTFLAG_STALL1_Msk (_UINT8_(0x1) << USB_DEVICE_EPINTFLAG_STALL1_Pos) /* (USB_DEVICE_EPINTFLAG) Stall 1 In/out Mask */ 276 #define USB_DEVICE_EPINTFLAG_STALL1(value) (USB_DEVICE_EPINTFLAG_STALL1_Msk & (_UINT8_(value) << USB_DEVICE_EPINTFLAG_STALL1_Pos)) /* Assigment of value for STALL1 in the USB_DEVICE_EPINTFLAG register */ 277 #define USB_DEVICE_EPINTFLAG_Msk _UINT8_(0x7F) /* (USB_DEVICE_EPINTFLAG) Register Mask */ 278 279 #define USB_DEVICE_EPINTFLAG_TRCPT_Pos _UINT8_(0) /* (USB_DEVICE_EPINTFLAG Position) Transfer Complete x */ 280 #define USB_DEVICE_EPINTFLAG_TRCPT_Msk (_UINT8_(0x3) << USB_DEVICE_EPINTFLAG_TRCPT_Pos) /* (USB_DEVICE_EPINTFLAG Mask) TRCPT */ 281 #define USB_DEVICE_EPINTFLAG_TRCPT(value) (USB_DEVICE_EPINTFLAG_TRCPT_Msk & (_UINT8_(value) << USB_DEVICE_EPINTFLAG_TRCPT_Pos)) 282 #define USB_DEVICE_EPINTFLAG_TRFAIL_Pos _UINT8_(2) /* (USB_DEVICE_EPINTFLAG Position) Error Flow x */ 283 #define USB_DEVICE_EPINTFLAG_TRFAIL_Msk (_UINT8_(0x3) << USB_DEVICE_EPINTFLAG_TRFAIL_Pos) /* (USB_DEVICE_EPINTFLAG Mask) TRFAIL */ 284 #define USB_DEVICE_EPINTFLAG_TRFAIL(value) (USB_DEVICE_EPINTFLAG_TRFAIL_Msk & (_UINT8_(value) << USB_DEVICE_EPINTFLAG_TRFAIL_Pos)) 285 #define USB_DEVICE_EPINTFLAG_STALL_Pos _UINT8_(5) /* (USB_DEVICE_EPINTFLAG Position) Stall x In/out */ 286 #define USB_DEVICE_EPINTFLAG_STALL_Msk (_UINT8_(0x3) << USB_DEVICE_EPINTFLAG_STALL_Pos) /* (USB_DEVICE_EPINTFLAG Mask) STALL */ 287 #define USB_DEVICE_EPINTFLAG_STALL(value) (USB_DEVICE_EPINTFLAG_STALL_Msk & (_UINT8_(value) << USB_DEVICE_EPINTFLAG_STALL_Pos)) 288 289 /* -------- USB_DEVICE_EPINTENCLR : (USB Offset: 0x08) (R/W 8) DEVICE_ENDPOINT End Point Interrupt Clear Flag -------- */ 290 #define USB_DEVICE_EPINTENCLR_RESETVALUE _UINT8_(0x00) /* (USB_DEVICE_EPINTENCLR) DEVICE_ENDPOINT End Point Interrupt Clear Flag Reset Value */ 291 292 #define USB_DEVICE_EPINTENCLR_TRCPT0_Pos _UINT8_(0) /* (USB_DEVICE_EPINTENCLR) Transfer Complete 0 Interrupt Disable Position */ 293 #define USB_DEVICE_EPINTENCLR_TRCPT0_Msk (_UINT8_(0x1) << USB_DEVICE_EPINTENCLR_TRCPT0_Pos) /* (USB_DEVICE_EPINTENCLR) Transfer Complete 0 Interrupt Disable Mask */ 294 #define USB_DEVICE_EPINTENCLR_TRCPT0(value) (USB_DEVICE_EPINTENCLR_TRCPT0_Msk & (_UINT8_(value) << USB_DEVICE_EPINTENCLR_TRCPT0_Pos)) /* Assigment of value for TRCPT0 in the USB_DEVICE_EPINTENCLR register */ 295 #define USB_DEVICE_EPINTENCLR_TRCPT1_Pos _UINT8_(1) /* (USB_DEVICE_EPINTENCLR) Transfer Complete 1 Interrupt Disable Position */ 296 #define USB_DEVICE_EPINTENCLR_TRCPT1_Msk (_UINT8_(0x1) << USB_DEVICE_EPINTENCLR_TRCPT1_Pos) /* (USB_DEVICE_EPINTENCLR) Transfer Complete 1 Interrupt Disable Mask */ 297 #define USB_DEVICE_EPINTENCLR_TRCPT1(value) (USB_DEVICE_EPINTENCLR_TRCPT1_Msk & (_UINT8_(value) << USB_DEVICE_EPINTENCLR_TRCPT1_Pos)) /* Assigment of value for TRCPT1 in the USB_DEVICE_EPINTENCLR register */ 298 #define USB_DEVICE_EPINTENCLR_TRFAIL0_Pos _UINT8_(2) /* (USB_DEVICE_EPINTENCLR) Error Flow 0 Interrupt Disable Position */ 299 #define USB_DEVICE_EPINTENCLR_TRFAIL0_Msk (_UINT8_(0x1) << USB_DEVICE_EPINTENCLR_TRFAIL0_Pos) /* (USB_DEVICE_EPINTENCLR) Error Flow 0 Interrupt Disable Mask */ 300 #define USB_DEVICE_EPINTENCLR_TRFAIL0(value) (USB_DEVICE_EPINTENCLR_TRFAIL0_Msk & (_UINT8_(value) << USB_DEVICE_EPINTENCLR_TRFAIL0_Pos)) /* Assigment of value for TRFAIL0 in the USB_DEVICE_EPINTENCLR register */ 301 #define USB_DEVICE_EPINTENCLR_TRFAIL1_Pos _UINT8_(3) /* (USB_DEVICE_EPINTENCLR) Error Flow 1 Interrupt Disable Position */ 302 #define USB_DEVICE_EPINTENCLR_TRFAIL1_Msk (_UINT8_(0x1) << USB_DEVICE_EPINTENCLR_TRFAIL1_Pos) /* (USB_DEVICE_EPINTENCLR) Error Flow 1 Interrupt Disable Mask */ 303 #define USB_DEVICE_EPINTENCLR_TRFAIL1(value) (USB_DEVICE_EPINTENCLR_TRFAIL1_Msk & (_UINT8_(value) << USB_DEVICE_EPINTENCLR_TRFAIL1_Pos)) /* Assigment of value for TRFAIL1 in the USB_DEVICE_EPINTENCLR register */ 304 #define USB_DEVICE_EPINTENCLR_RXSTP_Pos _UINT8_(4) /* (USB_DEVICE_EPINTENCLR) Received Setup Interrupt Disable Position */ 305 #define USB_DEVICE_EPINTENCLR_RXSTP_Msk (_UINT8_(0x1) << USB_DEVICE_EPINTENCLR_RXSTP_Pos) /* (USB_DEVICE_EPINTENCLR) Received Setup Interrupt Disable Mask */ 306 #define USB_DEVICE_EPINTENCLR_RXSTP(value) (USB_DEVICE_EPINTENCLR_RXSTP_Msk & (_UINT8_(value) << USB_DEVICE_EPINTENCLR_RXSTP_Pos)) /* Assigment of value for RXSTP in the USB_DEVICE_EPINTENCLR register */ 307 #define USB_DEVICE_EPINTENCLR_STALL0_Pos _UINT8_(5) /* (USB_DEVICE_EPINTENCLR) Stall 0 In/Out Interrupt Disable Position */ 308 #define USB_DEVICE_EPINTENCLR_STALL0_Msk (_UINT8_(0x1) << USB_DEVICE_EPINTENCLR_STALL0_Pos) /* (USB_DEVICE_EPINTENCLR) Stall 0 In/Out Interrupt Disable Mask */ 309 #define USB_DEVICE_EPINTENCLR_STALL0(value) (USB_DEVICE_EPINTENCLR_STALL0_Msk & (_UINT8_(value) << USB_DEVICE_EPINTENCLR_STALL0_Pos)) /* Assigment of value for STALL0 in the USB_DEVICE_EPINTENCLR register */ 310 #define USB_DEVICE_EPINTENCLR_STALL1_Pos _UINT8_(6) /* (USB_DEVICE_EPINTENCLR) Stall 1 In/Out Interrupt Disable Position */ 311 #define USB_DEVICE_EPINTENCLR_STALL1_Msk (_UINT8_(0x1) << USB_DEVICE_EPINTENCLR_STALL1_Pos) /* (USB_DEVICE_EPINTENCLR) Stall 1 In/Out Interrupt Disable Mask */ 312 #define USB_DEVICE_EPINTENCLR_STALL1(value) (USB_DEVICE_EPINTENCLR_STALL1_Msk & (_UINT8_(value) << USB_DEVICE_EPINTENCLR_STALL1_Pos)) /* Assigment of value for STALL1 in the USB_DEVICE_EPINTENCLR register */ 313 #define USB_DEVICE_EPINTENCLR_Msk _UINT8_(0x7F) /* (USB_DEVICE_EPINTENCLR) Register Mask */ 314 315 #define USB_DEVICE_EPINTENCLR_TRCPT_Pos _UINT8_(0) /* (USB_DEVICE_EPINTENCLR Position) Transfer Complete x Interrupt Disable */ 316 #define USB_DEVICE_EPINTENCLR_TRCPT_Msk (_UINT8_(0x3) << USB_DEVICE_EPINTENCLR_TRCPT_Pos) /* (USB_DEVICE_EPINTENCLR Mask) TRCPT */ 317 #define USB_DEVICE_EPINTENCLR_TRCPT(value) (USB_DEVICE_EPINTENCLR_TRCPT_Msk & (_UINT8_(value) << USB_DEVICE_EPINTENCLR_TRCPT_Pos)) 318 #define USB_DEVICE_EPINTENCLR_TRFAIL_Pos _UINT8_(2) /* (USB_DEVICE_EPINTENCLR Position) Error Flow x Interrupt Disable */ 319 #define USB_DEVICE_EPINTENCLR_TRFAIL_Msk (_UINT8_(0x3) << USB_DEVICE_EPINTENCLR_TRFAIL_Pos) /* (USB_DEVICE_EPINTENCLR Mask) TRFAIL */ 320 #define USB_DEVICE_EPINTENCLR_TRFAIL(value) (USB_DEVICE_EPINTENCLR_TRFAIL_Msk & (_UINT8_(value) << USB_DEVICE_EPINTENCLR_TRFAIL_Pos)) 321 #define USB_DEVICE_EPINTENCLR_STALL_Pos _UINT8_(5) /* (USB_DEVICE_EPINTENCLR Position) Stall x In/Out Interrupt Disable */ 322 #define USB_DEVICE_EPINTENCLR_STALL_Msk (_UINT8_(0x3) << USB_DEVICE_EPINTENCLR_STALL_Pos) /* (USB_DEVICE_EPINTENCLR Mask) STALL */ 323 #define USB_DEVICE_EPINTENCLR_STALL(value) (USB_DEVICE_EPINTENCLR_STALL_Msk & (_UINT8_(value) << USB_DEVICE_EPINTENCLR_STALL_Pos)) 324 325 /* -------- USB_DEVICE_EPINTENSET : (USB Offset: 0x09) (R/W 8) DEVICE_ENDPOINT End Point Interrupt Set Flag -------- */ 326 #define USB_DEVICE_EPINTENSET_RESETVALUE _UINT8_(0x00) /* (USB_DEVICE_EPINTENSET) DEVICE_ENDPOINT End Point Interrupt Set Flag Reset Value */ 327 328 #define USB_DEVICE_EPINTENSET_TRCPT0_Pos _UINT8_(0) /* (USB_DEVICE_EPINTENSET) Transfer Complete 0 Interrupt Enable Position */ 329 #define USB_DEVICE_EPINTENSET_TRCPT0_Msk (_UINT8_(0x1) << USB_DEVICE_EPINTENSET_TRCPT0_Pos) /* (USB_DEVICE_EPINTENSET) Transfer Complete 0 Interrupt Enable Mask */ 330 #define USB_DEVICE_EPINTENSET_TRCPT0(value) (USB_DEVICE_EPINTENSET_TRCPT0_Msk & (_UINT8_(value) << USB_DEVICE_EPINTENSET_TRCPT0_Pos)) /* Assigment of value for TRCPT0 in the USB_DEVICE_EPINTENSET register */ 331 #define USB_DEVICE_EPINTENSET_TRCPT1_Pos _UINT8_(1) /* (USB_DEVICE_EPINTENSET) Transfer Complete 1 Interrupt Enable Position */ 332 #define USB_DEVICE_EPINTENSET_TRCPT1_Msk (_UINT8_(0x1) << USB_DEVICE_EPINTENSET_TRCPT1_Pos) /* (USB_DEVICE_EPINTENSET) Transfer Complete 1 Interrupt Enable Mask */ 333 #define USB_DEVICE_EPINTENSET_TRCPT1(value) (USB_DEVICE_EPINTENSET_TRCPT1_Msk & (_UINT8_(value) << USB_DEVICE_EPINTENSET_TRCPT1_Pos)) /* Assigment of value for TRCPT1 in the USB_DEVICE_EPINTENSET register */ 334 #define USB_DEVICE_EPINTENSET_TRFAIL0_Pos _UINT8_(2) /* (USB_DEVICE_EPINTENSET) Error Flow 0 Interrupt Enable Position */ 335 #define USB_DEVICE_EPINTENSET_TRFAIL0_Msk (_UINT8_(0x1) << USB_DEVICE_EPINTENSET_TRFAIL0_Pos) /* (USB_DEVICE_EPINTENSET) Error Flow 0 Interrupt Enable Mask */ 336 #define USB_DEVICE_EPINTENSET_TRFAIL0(value) (USB_DEVICE_EPINTENSET_TRFAIL0_Msk & (_UINT8_(value) << USB_DEVICE_EPINTENSET_TRFAIL0_Pos)) /* Assigment of value for TRFAIL0 in the USB_DEVICE_EPINTENSET register */ 337 #define USB_DEVICE_EPINTENSET_TRFAIL1_Pos _UINT8_(3) /* (USB_DEVICE_EPINTENSET) Error Flow 1 Interrupt Enable Position */ 338 #define USB_DEVICE_EPINTENSET_TRFAIL1_Msk (_UINT8_(0x1) << USB_DEVICE_EPINTENSET_TRFAIL1_Pos) /* (USB_DEVICE_EPINTENSET) Error Flow 1 Interrupt Enable Mask */ 339 #define USB_DEVICE_EPINTENSET_TRFAIL1(value) (USB_DEVICE_EPINTENSET_TRFAIL1_Msk & (_UINT8_(value) << USB_DEVICE_EPINTENSET_TRFAIL1_Pos)) /* Assigment of value for TRFAIL1 in the USB_DEVICE_EPINTENSET register */ 340 #define USB_DEVICE_EPINTENSET_RXSTP_Pos _UINT8_(4) /* (USB_DEVICE_EPINTENSET) Received Setup Interrupt Enable Position */ 341 #define USB_DEVICE_EPINTENSET_RXSTP_Msk (_UINT8_(0x1) << USB_DEVICE_EPINTENSET_RXSTP_Pos) /* (USB_DEVICE_EPINTENSET) Received Setup Interrupt Enable Mask */ 342 #define USB_DEVICE_EPINTENSET_RXSTP(value) (USB_DEVICE_EPINTENSET_RXSTP_Msk & (_UINT8_(value) << USB_DEVICE_EPINTENSET_RXSTP_Pos)) /* Assigment of value for RXSTP in the USB_DEVICE_EPINTENSET register */ 343 #define USB_DEVICE_EPINTENSET_STALL0_Pos _UINT8_(5) /* (USB_DEVICE_EPINTENSET) Stall 0 In/out Interrupt enable Position */ 344 #define USB_DEVICE_EPINTENSET_STALL0_Msk (_UINT8_(0x1) << USB_DEVICE_EPINTENSET_STALL0_Pos) /* (USB_DEVICE_EPINTENSET) Stall 0 In/out Interrupt enable Mask */ 345 #define USB_DEVICE_EPINTENSET_STALL0(value) (USB_DEVICE_EPINTENSET_STALL0_Msk & (_UINT8_(value) << USB_DEVICE_EPINTENSET_STALL0_Pos)) /* Assigment of value for STALL0 in the USB_DEVICE_EPINTENSET register */ 346 #define USB_DEVICE_EPINTENSET_STALL1_Pos _UINT8_(6) /* (USB_DEVICE_EPINTENSET) Stall 1 In/out Interrupt enable Position */ 347 #define USB_DEVICE_EPINTENSET_STALL1_Msk (_UINT8_(0x1) << USB_DEVICE_EPINTENSET_STALL1_Pos) /* (USB_DEVICE_EPINTENSET) Stall 1 In/out Interrupt enable Mask */ 348 #define USB_DEVICE_EPINTENSET_STALL1(value) (USB_DEVICE_EPINTENSET_STALL1_Msk & (_UINT8_(value) << USB_DEVICE_EPINTENSET_STALL1_Pos)) /* Assigment of value for STALL1 in the USB_DEVICE_EPINTENSET register */ 349 #define USB_DEVICE_EPINTENSET_Msk _UINT8_(0x7F) /* (USB_DEVICE_EPINTENSET) Register Mask */ 350 351 #define USB_DEVICE_EPINTENSET_TRCPT_Pos _UINT8_(0) /* (USB_DEVICE_EPINTENSET Position) Transfer Complete x Interrupt Enable */ 352 #define USB_DEVICE_EPINTENSET_TRCPT_Msk (_UINT8_(0x3) << USB_DEVICE_EPINTENSET_TRCPT_Pos) /* (USB_DEVICE_EPINTENSET Mask) TRCPT */ 353 #define USB_DEVICE_EPINTENSET_TRCPT(value) (USB_DEVICE_EPINTENSET_TRCPT_Msk & (_UINT8_(value) << USB_DEVICE_EPINTENSET_TRCPT_Pos)) 354 #define USB_DEVICE_EPINTENSET_TRFAIL_Pos _UINT8_(2) /* (USB_DEVICE_EPINTENSET Position) Error Flow x Interrupt Enable */ 355 #define USB_DEVICE_EPINTENSET_TRFAIL_Msk (_UINT8_(0x3) << USB_DEVICE_EPINTENSET_TRFAIL_Pos) /* (USB_DEVICE_EPINTENSET Mask) TRFAIL */ 356 #define USB_DEVICE_EPINTENSET_TRFAIL(value) (USB_DEVICE_EPINTENSET_TRFAIL_Msk & (_UINT8_(value) << USB_DEVICE_EPINTENSET_TRFAIL_Pos)) 357 #define USB_DEVICE_EPINTENSET_STALL_Pos _UINT8_(5) /* (USB_DEVICE_EPINTENSET Position) Stall x In/out Interrupt enable */ 358 #define USB_DEVICE_EPINTENSET_STALL_Msk (_UINT8_(0x3) << USB_DEVICE_EPINTENSET_STALL_Pos) /* (USB_DEVICE_EPINTENSET Mask) STALL */ 359 #define USB_DEVICE_EPINTENSET_STALL(value) (USB_DEVICE_EPINTENSET_STALL_Msk & (_UINT8_(value) << USB_DEVICE_EPINTENSET_STALL_Pos)) 360 361 /* -------- USB_HOST_PCFG : (USB Offset: 0x00) (R/W 8) HOST_PIPE End Point Configuration -------- */ 362 #define USB_HOST_PCFG_RESETVALUE _UINT8_(0x00) /* (USB_HOST_PCFG) HOST_PIPE End Point Configuration Reset Value */ 363 364 #define USB_HOST_PCFG_PTOKEN_Pos _UINT8_(0) /* (USB_HOST_PCFG) Pipe Token Position */ 365 #define USB_HOST_PCFG_PTOKEN_Msk (_UINT8_(0x3) << USB_HOST_PCFG_PTOKEN_Pos) /* (USB_HOST_PCFG) Pipe Token Mask */ 366 #define USB_HOST_PCFG_PTOKEN(value) (USB_HOST_PCFG_PTOKEN_Msk & (_UINT8_(value) << USB_HOST_PCFG_PTOKEN_Pos)) /* Assigment of value for PTOKEN in the USB_HOST_PCFG register */ 367 #define USB_HOST_PCFG_BK_Pos _UINT8_(2) /* (USB_HOST_PCFG) Pipe Bank Position */ 368 #define USB_HOST_PCFG_BK_Msk (_UINT8_(0x1) << USB_HOST_PCFG_BK_Pos) /* (USB_HOST_PCFG) Pipe Bank Mask */ 369 #define USB_HOST_PCFG_BK(value) (USB_HOST_PCFG_BK_Msk & (_UINT8_(value) << USB_HOST_PCFG_BK_Pos)) /* Assigment of value for BK in the USB_HOST_PCFG register */ 370 #define USB_HOST_PCFG_PTYPE_Pos _UINT8_(3) /* (USB_HOST_PCFG) Pipe Type Position */ 371 #define USB_HOST_PCFG_PTYPE_Msk (_UINT8_(0x7) << USB_HOST_PCFG_PTYPE_Pos) /* (USB_HOST_PCFG) Pipe Type Mask */ 372 #define USB_HOST_PCFG_PTYPE(value) (USB_HOST_PCFG_PTYPE_Msk & (_UINT8_(value) << USB_HOST_PCFG_PTYPE_Pos)) /* Assigment of value for PTYPE in the USB_HOST_PCFG register */ 373 #define USB_HOST_PCFG_Msk _UINT8_(0x3F) /* (USB_HOST_PCFG) Register Mask */ 374 375 376 /* -------- USB_HOST_BINTERVAL : (USB Offset: 0x03) (R/W 8) HOST_PIPE Bus Access Period of Pipe -------- */ 377 #define USB_HOST_BINTERVAL_RESETVALUE _UINT8_(0x00) /* (USB_HOST_BINTERVAL) HOST_PIPE Bus Access Period of Pipe Reset Value */ 378 379 #define USB_HOST_BINTERVAL_BITINTERVAL_Pos _UINT8_(0) /* (USB_HOST_BINTERVAL) Bit Interval Position */ 380 #define USB_HOST_BINTERVAL_BITINTERVAL_Msk (_UINT8_(0xFF) << USB_HOST_BINTERVAL_BITINTERVAL_Pos) /* (USB_HOST_BINTERVAL) Bit Interval Mask */ 381 #define USB_HOST_BINTERVAL_BITINTERVAL(value) (USB_HOST_BINTERVAL_BITINTERVAL_Msk & (_UINT8_(value) << USB_HOST_BINTERVAL_BITINTERVAL_Pos)) /* Assigment of value for BITINTERVAL in the USB_HOST_BINTERVAL register */ 382 #define USB_HOST_BINTERVAL_Msk _UINT8_(0xFF) /* (USB_HOST_BINTERVAL) Register Mask */ 383 384 385 /* -------- USB_HOST_PSTATUSCLR : (USB Offset: 0x04) ( /W 8) HOST_PIPE End Point Pipe Status Clear -------- */ 386 #define USB_HOST_PSTATUSCLR_RESETVALUE _UINT8_(0x00) /* (USB_HOST_PSTATUSCLR) HOST_PIPE End Point Pipe Status Clear Reset Value */ 387 388 #define USB_HOST_PSTATUSCLR_DTGL_Pos _UINT8_(0) /* (USB_HOST_PSTATUSCLR) Data Toggle clear Position */ 389 #define USB_HOST_PSTATUSCLR_DTGL_Msk (_UINT8_(0x1) << USB_HOST_PSTATUSCLR_DTGL_Pos) /* (USB_HOST_PSTATUSCLR) Data Toggle clear Mask */ 390 #define USB_HOST_PSTATUSCLR_DTGL(value) (USB_HOST_PSTATUSCLR_DTGL_Msk & (_UINT8_(value) << USB_HOST_PSTATUSCLR_DTGL_Pos)) /* Assigment of value for DTGL in the USB_HOST_PSTATUSCLR register */ 391 #define USB_HOST_PSTATUSCLR_CURBK_Pos _UINT8_(2) /* (USB_HOST_PSTATUSCLR) Curren Bank clear Position */ 392 #define USB_HOST_PSTATUSCLR_CURBK_Msk (_UINT8_(0x1) << USB_HOST_PSTATUSCLR_CURBK_Pos) /* (USB_HOST_PSTATUSCLR) Curren Bank clear Mask */ 393 #define USB_HOST_PSTATUSCLR_CURBK(value) (USB_HOST_PSTATUSCLR_CURBK_Msk & (_UINT8_(value) << USB_HOST_PSTATUSCLR_CURBK_Pos)) /* Assigment of value for CURBK in the USB_HOST_PSTATUSCLR register */ 394 #define USB_HOST_PSTATUSCLR_PFREEZE_Pos _UINT8_(4) /* (USB_HOST_PSTATUSCLR) Pipe Freeze Clear Position */ 395 #define USB_HOST_PSTATUSCLR_PFREEZE_Msk (_UINT8_(0x1) << USB_HOST_PSTATUSCLR_PFREEZE_Pos) /* (USB_HOST_PSTATUSCLR) Pipe Freeze Clear Mask */ 396 #define USB_HOST_PSTATUSCLR_PFREEZE(value) (USB_HOST_PSTATUSCLR_PFREEZE_Msk & (_UINT8_(value) << USB_HOST_PSTATUSCLR_PFREEZE_Pos)) /* Assigment of value for PFREEZE in the USB_HOST_PSTATUSCLR register */ 397 #define USB_HOST_PSTATUSCLR_BK0RDY_Pos _UINT8_(6) /* (USB_HOST_PSTATUSCLR) Bank 0 Ready Clear Position */ 398 #define USB_HOST_PSTATUSCLR_BK0RDY_Msk (_UINT8_(0x1) << USB_HOST_PSTATUSCLR_BK0RDY_Pos) /* (USB_HOST_PSTATUSCLR) Bank 0 Ready Clear Mask */ 399 #define USB_HOST_PSTATUSCLR_BK0RDY(value) (USB_HOST_PSTATUSCLR_BK0RDY_Msk & (_UINT8_(value) << USB_HOST_PSTATUSCLR_BK0RDY_Pos)) /* Assigment of value for BK0RDY in the USB_HOST_PSTATUSCLR register */ 400 #define USB_HOST_PSTATUSCLR_BK1RDY_Pos _UINT8_(7) /* (USB_HOST_PSTATUSCLR) Bank 1 Ready Clear Position */ 401 #define USB_HOST_PSTATUSCLR_BK1RDY_Msk (_UINT8_(0x1) << USB_HOST_PSTATUSCLR_BK1RDY_Pos) /* (USB_HOST_PSTATUSCLR) Bank 1 Ready Clear Mask */ 402 #define USB_HOST_PSTATUSCLR_BK1RDY(value) (USB_HOST_PSTATUSCLR_BK1RDY_Msk & (_UINT8_(value) << USB_HOST_PSTATUSCLR_BK1RDY_Pos)) /* Assigment of value for BK1RDY in the USB_HOST_PSTATUSCLR register */ 403 #define USB_HOST_PSTATUSCLR_Msk _UINT8_(0xD5) /* (USB_HOST_PSTATUSCLR) Register Mask */ 404 405 406 /* -------- USB_HOST_PSTATUSSET : (USB Offset: 0x05) ( /W 8) HOST_PIPE End Point Pipe Status Set -------- */ 407 #define USB_HOST_PSTATUSSET_RESETVALUE _UINT8_(0x00) /* (USB_HOST_PSTATUSSET) HOST_PIPE End Point Pipe Status Set Reset Value */ 408 409 #define USB_HOST_PSTATUSSET_DTGL_Pos _UINT8_(0) /* (USB_HOST_PSTATUSSET) Data Toggle Set Position */ 410 #define USB_HOST_PSTATUSSET_DTGL_Msk (_UINT8_(0x1) << USB_HOST_PSTATUSSET_DTGL_Pos) /* (USB_HOST_PSTATUSSET) Data Toggle Set Mask */ 411 #define USB_HOST_PSTATUSSET_DTGL(value) (USB_HOST_PSTATUSSET_DTGL_Msk & (_UINT8_(value) << USB_HOST_PSTATUSSET_DTGL_Pos)) /* Assigment of value for DTGL in the USB_HOST_PSTATUSSET register */ 412 #define USB_HOST_PSTATUSSET_CURBK_Pos _UINT8_(2) /* (USB_HOST_PSTATUSSET) Current Bank Set Position */ 413 #define USB_HOST_PSTATUSSET_CURBK_Msk (_UINT8_(0x1) << USB_HOST_PSTATUSSET_CURBK_Pos) /* (USB_HOST_PSTATUSSET) Current Bank Set Mask */ 414 #define USB_HOST_PSTATUSSET_CURBK(value) (USB_HOST_PSTATUSSET_CURBK_Msk & (_UINT8_(value) << USB_HOST_PSTATUSSET_CURBK_Pos)) /* Assigment of value for CURBK in the USB_HOST_PSTATUSSET register */ 415 #define USB_HOST_PSTATUSSET_PFREEZE_Pos _UINT8_(4) /* (USB_HOST_PSTATUSSET) Pipe Freeze Set Position */ 416 #define USB_HOST_PSTATUSSET_PFREEZE_Msk (_UINT8_(0x1) << USB_HOST_PSTATUSSET_PFREEZE_Pos) /* (USB_HOST_PSTATUSSET) Pipe Freeze Set Mask */ 417 #define USB_HOST_PSTATUSSET_PFREEZE(value) (USB_HOST_PSTATUSSET_PFREEZE_Msk & (_UINT8_(value) << USB_HOST_PSTATUSSET_PFREEZE_Pos)) /* Assigment of value for PFREEZE in the USB_HOST_PSTATUSSET register */ 418 #define USB_HOST_PSTATUSSET_BK0RDY_Pos _UINT8_(6) /* (USB_HOST_PSTATUSSET) Bank 0 Ready Set Position */ 419 #define USB_HOST_PSTATUSSET_BK0RDY_Msk (_UINT8_(0x1) << USB_HOST_PSTATUSSET_BK0RDY_Pos) /* (USB_HOST_PSTATUSSET) Bank 0 Ready Set Mask */ 420 #define USB_HOST_PSTATUSSET_BK0RDY(value) (USB_HOST_PSTATUSSET_BK0RDY_Msk & (_UINT8_(value) << USB_HOST_PSTATUSSET_BK0RDY_Pos)) /* Assigment of value for BK0RDY in the USB_HOST_PSTATUSSET register */ 421 #define USB_HOST_PSTATUSSET_BK1RDY_Pos _UINT8_(7) /* (USB_HOST_PSTATUSSET) Bank 1 Ready Set Position */ 422 #define USB_HOST_PSTATUSSET_BK1RDY_Msk (_UINT8_(0x1) << USB_HOST_PSTATUSSET_BK1RDY_Pos) /* (USB_HOST_PSTATUSSET) Bank 1 Ready Set Mask */ 423 #define USB_HOST_PSTATUSSET_BK1RDY(value) (USB_HOST_PSTATUSSET_BK1RDY_Msk & (_UINT8_(value) << USB_HOST_PSTATUSSET_BK1RDY_Pos)) /* Assigment of value for BK1RDY in the USB_HOST_PSTATUSSET register */ 424 #define USB_HOST_PSTATUSSET_Msk _UINT8_(0xD5) /* (USB_HOST_PSTATUSSET) Register Mask */ 425 426 427 /* -------- USB_HOST_PSTATUS : (USB Offset: 0x06) ( R/ 8) HOST_PIPE End Point Pipe Status -------- */ 428 #define USB_HOST_PSTATUS_RESETVALUE _UINT8_(0x00) /* (USB_HOST_PSTATUS) HOST_PIPE End Point Pipe Status Reset Value */ 429 430 #define USB_HOST_PSTATUS_DTGL_Pos _UINT8_(0) /* (USB_HOST_PSTATUS) Data Toggle Position */ 431 #define USB_HOST_PSTATUS_DTGL_Msk (_UINT8_(0x1) << USB_HOST_PSTATUS_DTGL_Pos) /* (USB_HOST_PSTATUS) Data Toggle Mask */ 432 #define USB_HOST_PSTATUS_DTGL(value) (USB_HOST_PSTATUS_DTGL_Msk & (_UINT8_(value) << USB_HOST_PSTATUS_DTGL_Pos)) /* Assigment of value for DTGL in the USB_HOST_PSTATUS register */ 433 #define USB_HOST_PSTATUS_CURBK_Pos _UINT8_(2) /* (USB_HOST_PSTATUS) Current Bank Position */ 434 #define USB_HOST_PSTATUS_CURBK_Msk (_UINT8_(0x1) << USB_HOST_PSTATUS_CURBK_Pos) /* (USB_HOST_PSTATUS) Current Bank Mask */ 435 #define USB_HOST_PSTATUS_CURBK(value) (USB_HOST_PSTATUS_CURBK_Msk & (_UINT8_(value) << USB_HOST_PSTATUS_CURBK_Pos)) /* Assigment of value for CURBK in the USB_HOST_PSTATUS register */ 436 #define USB_HOST_PSTATUS_PFREEZE_Pos _UINT8_(4) /* (USB_HOST_PSTATUS) Pipe Freeze Position */ 437 #define USB_HOST_PSTATUS_PFREEZE_Msk (_UINT8_(0x1) << USB_HOST_PSTATUS_PFREEZE_Pos) /* (USB_HOST_PSTATUS) Pipe Freeze Mask */ 438 #define USB_HOST_PSTATUS_PFREEZE(value) (USB_HOST_PSTATUS_PFREEZE_Msk & (_UINT8_(value) << USB_HOST_PSTATUS_PFREEZE_Pos)) /* Assigment of value for PFREEZE in the USB_HOST_PSTATUS register */ 439 #define USB_HOST_PSTATUS_BK0RDY_Pos _UINT8_(6) /* (USB_HOST_PSTATUS) Bank 0 ready Position */ 440 #define USB_HOST_PSTATUS_BK0RDY_Msk (_UINT8_(0x1) << USB_HOST_PSTATUS_BK0RDY_Pos) /* (USB_HOST_PSTATUS) Bank 0 ready Mask */ 441 #define USB_HOST_PSTATUS_BK0RDY(value) (USB_HOST_PSTATUS_BK0RDY_Msk & (_UINT8_(value) << USB_HOST_PSTATUS_BK0RDY_Pos)) /* Assigment of value for BK0RDY in the USB_HOST_PSTATUS register */ 442 #define USB_HOST_PSTATUS_BK1RDY_Pos _UINT8_(7) /* (USB_HOST_PSTATUS) Bank 1 ready Position */ 443 #define USB_HOST_PSTATUS_BK1RDY_Msk (_UINT8_(0x1) << USB_HOST_PSTATUS_BK1RDY_Pos) /* (USB_HOST_PSTATUS) Bank 1 ready Mask */ 444 #define USB_HOST_PSTATUS_BK1RDY(value) (USB_HOST_PSTATUS_BK1RDY_Msk & (_UINT8_(value) << USB_HOST_PSTATUS_BK1RDY_Pos)) /* Assigment of value for BK1RDY in the USB_HOST_PSTATUS register */ 445 #define USB_HOST_PSTATUS_Msk _UINT8_(0xD5) /* (USB_HOST_PSTATUS) Register Mask */ 446 447 448 /* -------- USB_HOST_PINTFLAG : (USB Offset: 0x07) (R/W 8) HOST_PIPE Pipe Interrupt Flag -------- */ 449 #define USB_HOST_PINTFLAG_RESETVALUE _UINT8_(0x00) /* (USB_HOST_PINTFLAG) HOST_PIPE Pipe Interrupt Flag Reset Value */ 450 451 #define USB_HOST_PINTFLAG_TRCPT0_Pos _UINT8_(0) /* (USB_HOST_PINTFLAG) Transfer Complete 0 Interrupt Flag Position */ 452 #define USB_HOST_PINTFLAG_TRCPT0_Msk (_UINT8_(0x1) << USB_HOST_PINTFLAG_TRCPT0_Pos) /* (USB_HOST_PINTFLAG) Transfer Complete 0 Interrupt Flag Mask */ 453 #define USB_HOST_PINTFLAG_TRCPT0(value) (USB_HOST_PINTFLAG_TRCPT0_Msk & (_UINT8_(value) << USB_HOST_PINTFLAG_TRCPT0_Pos)) /* Assigment of value for TRCPT0 in the USB_HOST_PINTFLAG register */ 454 #define USB_HOST_PINTFLAG_TRCPT1_Pos _UINT8_(1) /* (USB_HOST_PINTFLAG) Transfer Complete 1 Interrupt Flag Position */ 455 #define USB_HOST_PINTFLAG_TRCPT1_Msk (_UINT8_(0x1) << USB_HOST_PINTFLAG_TRCPT1_Pos) /* (USB_HOST_PINTFLAG) Transfer Complete 1 Interrupt Flag Mask */ 456 #define USB_HOST_PINTFLAG_TRCPT1(value) (USB_HOST_PINTFLAG_TRCPT1_Msk & (_UINT8_(value) << USB_HOST_PINTFLAG_TRCPT1_Pos)) /* Assigment of value for TRCPT1 in the USB_HOST_PINTFLAG register */ 457 #define USB_HOST_PINTFLAG_TRFAIL_Pos _UINT8_(2) /* (USB_HOST_PINTFLAG) Error Flow Interrupt Flag Position */ 458 #define USB_HOST_PINTFLAG_TRFAIL_Msk (_UINT8_(0x1) << USB_HOST_PINTFLAG_TRFAIL_Pos) /* (USB_HOST_PINTFLAG) Error Flow Interrupt Flag Mask */ 459 #define USB_HOST_PINTFLAG_TRFAIL(value) (USB_HOST_PINTFLAG_TRFAIL_Msk & (_UINT8_(value) << USB_HOST_PINTFLAG_TRFAIL_Pos)) /* Assigment of value for TRFAIL in the USB_HOST_PINTFLAG register */ 460 #define USB_HOST_PINTFLAG_PERR_Pos _UINT8_(3) /* (USB_HOST_PINTFLAG) Pipe Error Interrupt Flag Position */ 461 #define USB_HOST_PINTFLAG_PERR_Msk (_UINT8_(0x1) << USB_HOST_PINTFLAG_PERR_Pos) /* (USB_HOST_PINTFLAG) Pipe Error Interrupt Flag Mask */ 462 #define USB_HOST_PINTFLAG_PERR(value) (USB_HOST_PINTFLAG_PERR_Msk & (_UINT8_(value) << USB_HOST_PINTFLAG_PERR_Pos)) /* Assigment of value for PERR in the USB_HOST_PINTFLAG register */ 463 #define USB_HOST_PINTFLAG_TXSTP_Pos _UINT8_(4) /* (USB_HOST_PINTFLAG) Transmit Setup Interrupt Flag Position */ 464 #define USB_HOST_PINTFLAG_TXSTP_Msk (_UINT8_(0x1) << USB_HOST_PINTFLAG_TXSTP_Pos) /* (USB_HOST_PINTFLAG) Transmit Setup Interrupt Flag Mask */ 465 #define USB_HOST_PINTFLAG_TXSTP(value) (USB_HOST_PINTFLAG_TXSTP_Msk & (_UINT8_(value) << USB_HOST_PINTFLAG_TXSTP_Pos)) /* Assigment of value for TXSTP in the USB_HOST_PINTFLAG register */ 466 #define USB_HOST_PINTFLAG_STALL_Pos _UINT8_(5) /* (USB_HOST_PINTFLAG) Stall Interrupt Flag Position */ 467 #define USB_HOST_PINTFLAG_STALL_Msk (_UINT8_(0x1) << USB_HOST_PINTFLAG_STALL_Pos) /* (USB_HOST_PINTFLAG) Stall Interrupt Flag Mask */ 468 #define USB_HOST_PINTFLAG_STALL(value) (USB_HOST_PINTFLAG_STALL_Msk & (_UINT8_(value) << USB_HOST_PINTFLAG_STALL_Pos)) /* Assigment of value for STALL in the USB_HOST_PINTFLAG register */ 469 #define USB_HOST_PINTFLAG_Msk _UINT8_(0x3F) /* (USB_HOST_PINTFLAG) Register Mask */ 470 471 #define USB_HOST_PINTFLAG_TRCPT_Pos _UINT8_(0) /* (USB_HOST_PINTFLAG Position) Transfer Complete x Interrupt Flag */ 472 #define USB_HOST_PINTFLAG_TRCPT_Msk (_UINT8_(0x3) << USB_HOST_PINTFLAG_TRCPT_Pos) /* (USB_HOST_PINTFLAG Mask) TRCPT */ 473 #define USB_HOST_PINTFLAG_TRCPT(value) (USB_HOST_PINTFLAG_TRCPT_Msk & (_UINT8_(value) << USB_HOST_PINTFLAG_TRCPT_Pos)) 474 475 /* -------- USB_HOST_PINTENCLR : (USB Offset: 0x08) (R/W 8) HOST_PIPE Pipe Interrupt Flag Clear -------- */ 476 #define USB_HOST_PINTENCLR_RESETVALUE _UINT8_(0x00) /* (USB_HOST_PINTENCLR) HOST_PIPE Pipe Interrupt Flag Clear Reset Value */ 477 478 #define USB_HOST_PINTENCLR_TRCPT0_Pos _UINT8_(0) /* (USB_HOST_PINTENCLR) Transfer Complete 0 Disable Position */ 479 #define USB_HOST_PINTENCLR_TRCPT0_Msk (_UINT8_(0x1) << USB_HOST_PINTENCLR_TRCPT0_Pos) /* (USB_HOST_PINTENCLR) Transfer Complete 0 Disable Mask */ 480 #define USB_HOST_PINTENCLR_TRCPT0(value) (USB_HOST_PINTENCLR_TRCPT0_Msk & (_UINT8_(value) << USB_HOST_PINTENCLR_TRCPT0_Pos)) /* Assigment of value for TRCPT0 in the USB_HOST_PINTENCLR register */ 481 #define USB_HOST_PINTENCLR_TRCPT1_Pos _UINT8_(1) /* (USB_HOST_PINTENCLR) Transfer Complete 1 Disable Position */ 482 #define USB_HOST_PINTENCLR_TRCPT1_Msk (_UINT8_(0x1) << USB_HOST_PINTENCLR_TRCPT1_Pos) /* (USB_HOST_PINTENCLR) Transfer Complete 1 Disable Mask */ 483 #define USB_HOST_PINTENCLR_TRCPT1(value) (USB_HOST_PINTENCLR_TRCPT1_Msk & (_UINT8_(value) << USB_HOST_PINTENCLR_TRCPT1_Pos)) /* Assigment of value for TRCPT1 in the USB_HOST_PINTENCLR register */ 484 #define USB_HOST_PINTENCLR_TRFAIL_Pos _UINT8_(2) /* (USB_HOST_PINTENCLR) Error Flow Interrupt Disable Position */ 485 #define USB_HOST_PINTENCLR_TRFAIL_Msk (_UINT8_(0x1) << USB_HOST_PINTENCLR_TRFAIL_Pos) /* (USB_HOST_PINTENCLR) Error Flow Interrupt Disable Mask */ 486 #define USB_HOST_PINTENCLR_TRFAIL(value) (USB_HOST_PINTENCLR_TRFAIL_Msk & (_UINT8_(value) << USB_HOST_PINTENCLR_TRFAIL_Pos)) /* Assigment of value for TRFAIL in the USB_HOST_PINTENCLR register */ 487 #define USB_HOST_PINTENCLR_PERR_Pos _UINT8_(3) /* (USB_HOST_PINTENCLR) Pipe Error Interrupt Disable Position */ 488 #define USB_HOST_PINTENCLR_PERR_Msk (_UINT8_(0x1) << USB_HOST_PINTENCLR_PERR_Pos) /* (USB_HOST_PINTENCLR) Pipe Error Interrupt Disable Mask */ 489 #define USB_HOST_PINTENCLR_PERR(value) (USB_HOST_PINTENCLR_PERR_Msk & (_UINT8_(value) << USB_HOST_PINTENCLR_PERR_Pos)) /* Assigment of value for PERR in the USB_HOST_PINTENCLR register */ 490 #define USB_HOST_PINTENCLR_TXSTP_Pos _UINT8_(4) /* (USB_HOST_PINTENCLR) Transmit Setup Interrupt Disable Position */ 491 #define USB_HOST_PINTENCLR_TXSTP_Msk (_UINT8_(0x1) << USB_HOST_PINTENCLR_TXSTP_Pos) /* (USB_HOST_PINTENCLR) Transmit Setup Interrupt Disable Mask */ 492 #define USB_HOST_PINTENCLR_TXSTP(value) (USB_HOST_PINTENCLR_TXSTP_Msk & (_UINT8_(value) << USB_HOST_PINTENCLR_TXSTP_Pos)) /* Assigment of value for TXSTP in the USB_HOST_PINTENCLR register */ 493 #define USB_HOST_PINTENCLR_STALL_Pos _UINT8_(5) /* (USB_HOST_PINTENCLR) Stall Inetrrupt Disable Position */ 494 #define USB_HOST_PINTENCLR_STALL_Msk (_UINT8_(0x1) << USB_HOST_PINTENCLR_STALL_Pos) /* (USB_HOST_PINTENCLR) Stall Inetrrupt Disable Mask */ 495 #define USB_HOST_PINTENCLR_STALL(value) (USB_HOST_PINTENCLR_STALL_Msk & (_UINT8_(value) << USB_HOST_PINTENCLR_STALL_Pos)) /* Assigment of value for STALL in the USB_HOST_PINTENCLR register */ 496 #define USB_HOST_PINTENCLR_Msk _UINT8_(0x3F) /* (USB_HOST_PINTENCLR) Register Mask */ 497 498 #define USB_HOST_PINTENCLR_TRCPT_Pos _UINT8_(0) /* (USB_HOST_PINTENCLR Position) Transfer Complete x Disable */ 499 #define USB_HOST_PINTENCLR_TRCPT_Msk (_UINT8_(0x3) << USB_HOST_PINTENCLR_TRCPT_Pos) /* (USB_HOST_PINTENCLR Mask) TRCPT */ 500 #define USB_HOST_PINTENCLR_TRCPT(value) (USB_HOST_PINTENCLR_TRCPT_Msk & (_UINT8_(value) << USB_HOST_PINTENCLR_TRCPT_Pos)) 501 502 /* -------- USB_HOST_PINTENSET : (USB Offset: 0x09) (R/W 8) HOST_PIPE Pipe Interrupt Flag Set -------- */ 503 #define USB_HOST_PINTENSET_RESETVALUE _UINT8_(0x00) /* (USB_HOST_PINTENSET) HOST_PIPE Pipe Interrupt Flag Set Reset Value */ 504 505 #define USB_HOST_PINTENSET_TRCPT0_Pos _UINT8_(0) /* (USB_HOST_PINTENSET) Transfer Complete 0 Interrupt Enable Position */ 506 #define USB_HOST_PINTENSET_TRCPT0_Msk (_UINT8_(0x1) << USB_HOST_PINTENSET_TRCPT0_Pos) /* (USB_HOST_PINTENSET) Transfer Complete 0 Interrupt Enable Mask */ 507 #define USB_HOST_PINTENSET_TRCPT0(value) (USB_HOST_PINTENSET_TRCPT0_Msk & (_UINT8_(value) << USB_HOST_PINTENSET_TRCPT0_Pos)) /* Assigment of value for TRCPT0 in the USB_HOST_PINTENSET register */ 508 #define USB_HOST_PINTENSET_TRCPT1_Pos _UINT8_(1) /* (USB_HOST_PINTENSET) Transfer Complete 1 Interrupt Enable Position */ 509 #define USB_HOST_PINTENSET_TRCPT1_Msk (_UINT8_(0x1) << USB_HOST_PINTENSET_TRCPT1_Pos) /* (USB_HOST_PINTENSET) Transfer Complete 1 Interrupt Enable Mask */ 510 #define USB_HOST_PINTENSET_TRCPT1(value) (USB_HOST_PINTENSET_TRCPT1_Msk & (_UINT8_(value) << USB_HOST_PINTENSET_TRCPT1_Pos)) /* Assigment of value for TRCPT1 in the USB_HOST_PINTENSET register */ 511 #define USB_HOST_PINTENSET_TRFAIL_Pos _UINT8_(2) /* (USB_HOST_PINTENSET) Error Flow Interrupt Enable Position */ 512 #define USB_HOST_PINTENSET_TRFAIL_Msk (_UINT8_(0x1) << USB_HOST_PINTENSET_TRFAIL_Pos) /* (USB_HOST_PINTENSET) Error Flow Interrupt Enable Mask */ 513 #define USB_HOST_PINTENSET_TRFAIL(value) (USB_HOST_PINTENSET_TRFAIL_Msk & (_UINT8_(value) << USB_HOST_PINTENSET_TRFAIL_Pos)) /* Assigment of value for TRFAIL in the USB_HOST_PINTENSET register */ 514 #define USB_HOST_PINTENSET_PERR_Pos _UINT8_(3) /* (USB_HOST_PINTENSET) Pipe Error Interrupt Enable Position */ 515 #define USB_HOST_PINTENSET_PERR_Msk (_UINT8_(0x1) << USB_HOST_PINTENSET_PERR_Pos) /* (USB_HOST_PINTENSET) Pipe Error Interrupt Enable Mask */ 516 #define USB_HOST_PINTENSET_PERR(value) (USB_HOST_PINTENSET_PERR_Msk & (_UINT8_(value) << USB_HOST_PINTENSET_PERR_Pos)) /* Assigment of value for PERR in the USB_HOST_PINTENSET register */ 517 #define USB_HOST_PINTENSET_TXSTP_Pos _UINT8_(4) /* (USB_HOST_PINTENSET) Transmit Setup Interrupt Enable Position */ 518 #define USB_HOST_PINTENSET_TXSTP_Msk (_UINT8_(0x1) << USB_HOST_PINTENSET_TXSTP_Pos) /* (USB_HOST_PINTENSET) Transmit Setup Interrupt Enable Mask */ 519 #define USB_HOST_PINTENSET_TXSTP(value) (USB_HOST_PINTENSET_TXSTP_Msk & (_UINT8_(value) << USB_HOST_PINTENSET_TXSTP_Pos)) /* Assigment of value for TXSTP in the USB_HOST_PINTENSET register */ 520 #define USB_HOST_PINTENSET_STALL_Pos _UINT8_(5) /* (USB_HOST_PINTENSET) Stall Interrupt Enable Position */ 521 #define USB_HOST_PINTENSET_STALL_Msk (_UINT8_(0x1) << USB_HOST_PINTENSET_STALL_Pos) /* (USB_HOST_PINTENSET) Stall Interrupt Enable Mask */ 522 #define USB_HOST_PINTENSET_STALL(value) (USB_HOST_PINTENSET_STALL_Msk & (_UINT8_(value) << USB_HOST_PINTENSET_STALL_Pos)) /* Assigment of value for STALL in the USB_HOST_PINTENSET register */ 523 #define USB_HOST_PINTENSET_Msk _UINT8_(0x3F) /* (USB_HOST_PINTENSET) Register Mask */ 524 525 #define USB_HOST_PINTENSET_TRCPT_Pos _UINT8_(0) /* (USB_HOST_PINTENSET Position) Transfer Complete x Interrupt Enable */ 526 #define USB_HOST_PINTENSET_TRCPT_Msk (_UINT8_(0x3) << USB_HOST_PINTENSET_TRCPT_Pos) /* (USB_HOST_PINTENSET Mask) TRCPT */ 527 #define USB_HOST_PINTENSET_TRCPT(value) (USB_HOST_PINTENSET_TRCPT_Msk & (_UINT8_(value) << USB_HOST_PINTENSET_TRCPT_Pos)) 528 529 /* -------- USB_CTRLA : (USB Offset: 0x00) (R/W 8) Control A -------- */ 530 #define USB_CTRLA_RESETVALUE _UINT8_(0x00) /* (USB_CTRLA) Control A Reset Value */ 531 532 #define USB_CTRLA_SWRST_Pos _UINT8_(0) /* (USB_CTRLA) Software Reset Position */ 533 #define USB_CTRLA_SWRST_Msk (_UINT8_(0x1) << USB_CTRLA_SWRST_Pos) /* (USB_CTRLA) Software Reset Mask */ 534 #define USB_CTRLA_SWRST(value) (USB_CTRLA_SWRST_Msk & (_UINT8_(value) << USB_CTRLA_SWRST_Pos)) /* Assigment of value for SWRST in the USB_CTRLA register */ 535 #define USB_CTRLA_ENABLE_Pos _UINT8_(1) /* (USB_CTRLA) Enable Position */ 536 #define USB_CTRLA_ENABLE_Msk (_UINT8_(0x1) << USB_CTRLA_ENABLE_Pos) /* (USB_CTRLA) Enable Mask */ 537 #define USB_CTRLA_ENABLE(value) (USB_CTRLA_ENABLE_Msk & (_UINT8_(value) << USB_CTRLA_ENABLE_Pos)) /* Assigment of value for ENABLE in the USB_CTRLA register */ 538 #define USB_CTRLA_RUNSTDBY_Pos _UINT8_(2) /* (USB_CTRLA) Run in Standby Mode Position */ 539 #define USB_CTRLA_RUNSTDBY_Msk (_UINT8_(0x1) << USB_CTRLA_RUNSTDBY_Pos) /* (USB_CTRLA) Run in Standby Mode Mask */ 540 #define USB_CTRLA_RUNSTDBY(value) (USB_CTRLA_RUNSTDBY_Msk & (_UINT8_(value) << USB_CTRLA_RUNSTDBY_Pos)) /* Assigment of value for RUNSTDBY in the USB_CTRLA register */ 541 #define USB_CTRLA_MODE_Pos _UINT8_(7) /* (USB_CTRLA) Operating Mode Position */ 542 #define USB_CTRLA_MODE_Msk (_UINT8_(0x1) << USB_CTRLA_MODE_Pos) /* (USB_CTRLA) Operating Mode Mask */ 543 #define USB_CTRLA_MODE(value) (USB_CTRLA_MODE_Msk & (_UINT8_(value) << USB_CTRLA_MODE_Pos)) /* Assigment of value for MODE in the USB_CTRLA register */ 544 #define USB_CTRLA_MODE_DEVICE_Val _UINT8_(0x0) /* (USB_CTRLA) Device Mode */ 545 #define USB_CTRLA_MODE_HOST_Val _UINT8_(0x1) /* (USB_CTRLA) Host Mode */ 546 #define USB_CTRLA_MODE_DEVICE (USB_CTRLA_MODE_DEVICE_Val << USB_CTRLA_MODE_Pos) /* (USB_CTRLA) Device Mode Position */ 547 #define USB_CTRLA_MODE_HOST (USB_CTRLA_MODE_HOST_Val << USB_CTRLA_MODE_Pos) /* (USB_CTRLA) Host Mode Position */ 548 #define USB_CTRLA_Msk _UINT8_(0x87) /* (USB_CTRLA) Register Mask */ 549 550 551 /* -------- USB_SYNCBUSY : (USB Offset: 0x02) ( R/ 8) Synchronization Busy -------- */ 552 #define USB_SYNCBUSY_RESETVALUE _UINT8_(0x00) /* (USB_SYNCBUSY) Synchronization Busy Reset Value */ 553 554 #define USB_SYNCBUSY_SWRST_Pos _UINT8_(0) /* (USB_SYNCBUSY) Software Reset Synchronization Busy Position */ 555 #define USB_SYNCBUSY_SWRST_Msk (_UINT8_(0x1) << USB_SYNCBUSY_SWRST_Pos) /* (USB_SYNCBUSY) Software Reset Synchronization Busy Mask */ 556 #define USB_SYNCBUSY_SWRST(value) (USB_SYNCBUSY_SWRST_Msk & (_UINT8_(value) << USB_SYNCBUSY_SWRST_Pos)) /* Assigment of value for SWRST in the USB_SYNCBUSY register */ 557 #define USB_SYNCBUSY_ENABLE_Pos _UINT8_(1) /* (USB_SYNCBUSY) Enable Synchronization Busy Position */ 558 #define USB_SYNCBUSY_ENABLE_Msk (_UINT8_(0x1) << USB_SYNCBUSY_ENABLE_Pos) /* (USB_SYNCBUSY) Enable Synchronization Busy Mask */ 559 #define USB_SYNCBUSY_ENABLE(value) (USB_SYNCBUSY_ENABLE_Msk & (_UINT8_(value) << USB_SYNCBUSY_ENABLE_Pos)) /* Assigment of value for ENABLE in the USB_SYNCBUSY register */ 560 #define USB_SYNCBUSY_Msk _UINT8_(0x03) /* (USB_SYNCBUSY) Register Mask */ 561 562 563 /* -------- USB_QOSCTRL : (USB Offset: 0x03) (R/W 8) USB Quality Of Service -------- */ 564 #define USB_QOSCTRL_RESETVALUE _UINT8_(0x0F) /* (USB_QOSCTRL) USB Quality Of Service Reset Value */ 565 566 #define USB_QOSCTRL_CQOS_Pos _UINT8_(0) /* (USB_QOSCTRL) Configuration Quality of Service Position */ 567 #define USB_QOSCTRL_CQOS_Msk (_UINT8_(0x3) << USB_QOSCTRL_CQOS_Pos) /* (USB_QOSCTRL) Configuration Quality of Service Mask */ 568 #define USB_QOSCTRL_CQOS(value) (USB_QOSCTRL_CQOS_Msk & (_UINT8_(value) << USB_QOSCTRL_CQOS_Pos)) /* Assigment of value for CQOS in the USB_QOSCTRL register */ 569 #define USB_QOSCTRL_DQOS_Pos _UINT8_(2) /* (USB_QOSCTRL) Data Quality of Service Position */ 570 #define USB_QOSCTRL_DQOS_Msk (_UINT8_(0x3) << USB_QOSCTRL_DQOS_Pos) /* (USB_QOSCTRL) Data Quality of Service Mask */ 571 #define USB_QOSCTRL_DQOS(value) (USB_QOSCTRL_DQOS_Msk & (_UINT8_(value) << USB_QOSCTRL_DQOS_Pos)) /* Assigment of value for DQOS in the USB_QOSCTRL register */ 572 #define USB_QOSCTRL_Msk _UINT8_(0x0F) /* (USB_QOSCTRL) Register Mask */ 573 574 575 /* -------- USB_DEVICE_CTRLB : (USB Offset: 0x08) (R/W 16) DEVICE Control B -------- */ 576 #define USB_DEVICE_CTRLB_RESETVALUE _UINT16_(0x01) /* (USB_DEVICE_CTRLB) DEVICE Control B Reset Value */ 577 578 #define USB_DEVICE_CTRLB_DETACH_Pos _UINT16_(0) /* (USB_DEVICE_CTRLB) Detach Position */ 579 #define USB_DEVICE_CTRLB_DETACH_Msk (_UINT16_(0x1) << USB_DEVICE_CTRLB_DETACH_Pos) /* (USB_DEVICE_CTRLB) Detach Mask */ 580 #define USB_DEVICE_CTRLB_DETACH(value) (USB_DEVICE_CTRLB_DETACH_Msk & (_UINT16_(value) << USB_DEVICE_CTRLB_DETACH_Pos)) /* Assigment of value for DETACH in the USB_DEVICE_CTRLB register */ 581 #define USB_DEVICE_CTRLB_UPRSM_Pos _UINT16_(1) /* (USB_DEVICE_CTRLB) Upstream Resume Position */ 582 #define USB_DEVICE_CTRLB_UPRSM_Msk (_UINT16_(0x1) << USB_DEVICE_CTRLB_UPRSM_Pos) /* (USB_DEVICE_CTRLB) Upstream Resume Mask */ 583 #define USB_DEVICE_CTRLB_UPRSM(value) (USB_DEVICE_CTRLB_UPRSM_Msk & (_UINT16_(value) << USB_DEVICE_CTRLB_UPRSM_Pos)) /* Assigment of value for UPRSM in the USB_DEVICE_CTRLB register */ 584 #define USB_DEVICE_CTRLB_SPDCONF_Pos _UINT16_(2) /* (USB_DEVICE_CTRLB) Speed Configuration Position */ 585 #define USB_DEVICE_CTRLB_SPDCONF_Msk (_UINT16_(0x3) << USB_DEVICE_CTRLB_SPDCONF_Pos) /* (USB_DEVICE_CTRLB) Speed Configuration Mask */ 586 #define USB_DEVICE_CTRLB_SPDCONF(value) (USB_DEVICE_CTRLB_SPDCONF_Msk & (_UINT16_(value) << USB_DEVICE_CTRLB_SPDCONF_Pos)) /* Assigment of value for SPDCONF in the USB_DEVICE_CTRLB register */ 587 #define USB_DEVICE_CTRLB_SPDCONF_FS_Val _UINT16_(0x0) /* (USB_DEVICE_CTRLB) FS : Full Speed */ 588 #define USB_DEVICE_CTRLB_SPDCONF_LS_Val _UINT16_(0x1) /* (USB_DEVICE_CTRLB) LS : Low Speed */ 589 #define USB_DEVICE_CTRLB_SPDCONF_FS (USB_DEVICE_CTRLB_SPDCONF_FS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos) /* (USB_DEVICE_CTRLB) FS : Full Speed Position */ 590 #define USB_DEVICE_CTRLB_SPDCONF_LS (USB_DEVICE_CTRLB_SPDCONF_LS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos) /* (USB_DEVICE_CTRLB) LS : Low Speed Position */ 591 #define USB_DEVICE_CTRLB_NREPLY_Pos _UINT16_(4) /* (USB_DEVICE_CTRLB) No Reply Position */ 592 #define USB_DEVICE_CTRLB_NREPLY_Msk (_UINT16_(0x1) << USB_DEVICE_CTRLB_NREPLY_Pos) /* (USB_DEVICE_CTRLB) No Reply Mask */ 593 #define USB_DEVICE_CTRLB_NREPLY(value) (USB_DEVICE_CTRLB_NREPLY_Msk & (_UINT16_(value) << USB_DEVICE_CTRLB_NREPLY_Pos)) /* Assigment of value for NREPLY in the USB_DEVICE_CTRLB register */ 594 #define USB_DEVICE_CTRLB_GNAK_Pos _UINT16_(9) /* (USB_DEVICE_CTRLB) Global NAK Position */ 595 #define USB_DEVICE_CTRLB_GNAK_Msk (_UINT16_(0x1) << USB_DEVICE_CTRLB_GNAK_Pos) /* (USB_DEVICE_CTRLB) Global NAK Mask */ 596 #define USB_DEVICE_CTRLB_GNAK(value) (USB_DEVICE_CTRLB_GNAK_Msk & (_UINT16_(value) << USB_DEVICE_CTRLB_GNAK_Pos)) /* Assigment of value for GNAK in the USB_DEVICE_CTRLB register */ 597 #define USB_DEVICE_CTRLB_LPMHDSK_Pos _UINT16_(10) /* (USB_DEVICE_CTRLB) Link Power Management Handshake Position */ 598 #define USB_DEVICE_CTRLB_LPMHDSK_Msk (_UINT16_(0x3) << USB_DEVICE_CTRLB_LPMHDSK_Pos) /* (USB_DEVICE_CTRLB) Link Power Management Handshake Mask */ 599 #define USB_DEVICE_CTRLB_LPMHDSK(value) (USB_DEVICE_CTRLB_LPMHDSK_Msk & (_UINT16_(value) << USB_DEVICE_CTRLB_LPMHDSK_Pos)) /* Assigment of value for LPMHDSK in the USB_DEVICE_CTRLB register */ 600 #define USB_DEVICE_CTRLB_LPMHDSK_NO_Val _UINT16_(0x0) /* (USB_DEVICE_CTRLB) No handshake. LPM is not supported */ 601 #define USB_DEVICE_CTRLB_LPMHDSK_ACK_Val _UINT16_(0x1) /* (USB_DEVICE_CTRLB) ACK */ 602 #define USB_DEVICE_CTRLB_LPMHDSK_NYET_Val _UINT16_(0x2) /* (USB_DEVICE_CTRLB) NYET */ 603 #define USB_DEVICE_CTRLB_LPMHDSK_NO (USB_DEVICE_CTRLB_LPMHDSK_NO_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos) /* (USB_DEVICE_CTRLB) No handshake. LPM is not supported Position */ 604 #define USB_DEVICE_CTRLB_LPMHDSK_ACK (USB_DEVICE_CTRLB_LPMHDSK_ACK_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos) /* (USB_DEVICE_CTRLB) ACK Position */ 605 #define USB_DEVICE_CTRLB_LPMHDSK_NYET (USB_DEVICE_CTRLB_LPMHDSK_NYET_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos) /* (USB_DEVICE_CTRLB) NYET Position */ 606 #define USB_DEVICE_CTRLB_Msk _UINT16_(0x0E1F) /* (USB_DEVICE_CTRLB) Register Mask */ 607 608 609 /* -------- USB_HOST_CTRLB : (USB Offset: 0x08) (R/W 16) HOST Control B -------- */ 610 #define USB_HOST_CTRLB_RESETVALUE _UINT16_(0x00) /* (USB_HOST_CTRLB) HOST Control B Reset Value */ 611 612 #define USB_HOST_CTRLB_RESUME_Pos _UINT16_(1) /* (USB_HOST_CTRLB) Send USB Resume Position */ 613 #define USB_HOST_CTRLB_RESUME_Msk (_UINT16_(0x1) << USB_HOST_CTRLB_RESUME_Pos) /* (USB_HOST_CTRLB) Send USB Resume Mask */ 614 #define USB_HOST_CTRLB_RESUME(value) (USB_HOST_CTRLB_RESUME_Msk & (_UINT16_(value) << USB_HOST_CTRLB_RESUME_Pos)) /* Assigment of value for RESUME in the USB_HOST_CTRLB register */ 615 #define USB_HOST_CTRLB_SPDCONF_Pos _UINT16_(2) /* (USB_HOST_CTRLB) Speed Configuration for Host Position */ 616 #define USB_HOST_CTRLB_SPDCONF_Msk (_UINT16_(0x3) << USB_HOST_CTRLB_SPDCONF_Pos) /* (USB_HOST_CTRLB) Speed Configuration for Host Mask */ 617 #define USB_HOST_CTRLB_SPDCONF(value) (USB_HOST_CTRLB_SPDCONF_Msk & (_UINT16_(value) << USB_HOST_CTRLB_SPDCONF_Pos)) /* Assigment of value for SPDCONF in the USB_HOST_CTRLB register */ 618 #define USB_HOST_CTRLB_SPDCONF_NORMAL_Val _UINT16_(0x0) /* (USB_HOST_CTRLB) Low and Full Speed capable */ 619 #define USB_HOST_CTRLB_SPDCONF_NORMAL (USB_HOST_CTRLB_SPDCONF_NORMAL_Val << USB_HOST_CTRLB_SPDCONF_Pos) /* (USB_HOST_CTRLB) Low and Full Speed capable Position */ 620 #define USB_HOST_CTRLB_AUTORESUME_Pos _UINT16_(4) /* (USB_HOST_CTRLB) Auto Resume Enable Position */ 621 #define USB_HOST_CTRLB_AUTORESUME_Msk (_UINT16_(0x1) << USB_HOST_CTRLB_AUTORESUME_Pos) /* (USB_HOST_CTRLB) Auto Resume Enable Mask */ 622 #define USB_HOST_CTRLB_AUTORESUME(value) (USB_HOST_CTRLB_AUTORESUME_Msk & (_UINT16_(value) << USB_HOST_CTRLB_AUTORESUME_Pos)) /* Assigment of value for AUTORESUME in the USB_HOST_CTRLB register */ 623 #define USB_HOST_CTRLB_SOFE_Pos _UINT16_(8) /* (USB_HOST_CTRLB) Start of Frame Generation Enable Position */ 624 #define USB_HOST_CTRLB_SOFE_Msk (_UINT16_(0x1) << USB_HOST_CTRLB_SOFE_Pos) /* (USB_HOST_CTRLB) Start of Frame Generation Enable Mask */ 625 #define USB_HOST_CTRLB_SOFE(value) (USB_HOST_CTRLB_SOFE_Msk & (_UINT16_(value) << USB_HOST_CTRLB_SOFE_Pos)) /* Assigment of value for SOFE in the USB_HOST_CTRLB register */ 626 #define USB_HOST_CTRLB_BUSRESET_Pos _UINT16_(9) /* (USB_HOST_CTRLB) Send USB Reset Position */ 627 #define USB_HOST_CTRLB_BUSRESET_Msk (_UINT16_(0x1) << USB_HOST_CTRLB_BUSRESET_Pos) /* (USB_HOST_CTRLB) Send USB Reset Mask */ 628 #define USB_HOST_CTRLB_BUSRESET(value) (USB_HOST_CTRLB_BUSRESET_Msk & (_UINT16_(value) << USB_HOST_CTRLB_BUSRESET_Pos)) /* Assigment of value for BUSRESET in the USB_HOST_CTRLB register */ 629 #define USB_HOST_CTRLB_VBUSOK_Pos _UINT16_(10) /* (USB_HOST_CTRLB) VBUS is OK Position */ 630 #define USB_HOST_CTRLB_VBUSOK_Msk (_UINT16_(0x1) << USB_HOST_CTRLB_VBUSOK_Pos) /* (USB_HOST_CTRLB) VBUS is OK Mask */ 631 #define USB_HOST_CTRLB_VBUSOK(value) (USB_HOST_CTRLB_VBUSOK_Msk & (_UINT16_(value) << USB_HOST_CTRLB_VBUSOK_Pos)) /* Assigment of value for VBUSOK in the USB_HOST_CTRLB register */ 632 #define USB_HOST_CTRLB_L1RESUME_Pos _UINT16_(11) /* (USB_HOST_CTRLB) Send L1 Resume Position */ 633 #define USB_HOST_CTRLB_L1RESUME_Msk (_UINT16_(0x1) << USB_HOST_CTRLB_L1RESUME_Pos) /* (USB_HOST_CTRLB) Send L1 Resume Mask */ 634 #define USB_HOST_CTRLB_L1RESUME(value) (USB_HOST_CTRLB_L1RESUME_Msk & (_UINT16_(value) << USB_HOST_CTRLB_L1RESUME_Pos)) /* Assigment of value for L1RESUME in the USB_HOST_CTRLB register */ 635 #define USB_HOST_CTRLB_Msk _UINT16_(0x0F1E) /* (USB_HOST_CTRLB) Register Mask */ 636 637 638 /* -------- USB_DEVICE_DADD : (USB Offset: 0x0A) (R/W 8) DEVICE Device Address -------- */ 639 #define USB_DEVICE_DADD_RESETVALUE _UINT8_(0x00) /* (USB_DEVICE_DADD) DEVICE Device Address Reset Value */ 640 641 #define USB_DEVICE_DADD_DADD_Pos _UINT8_(0) /* (USB_DEVICE_DADD) Device Address Position */ 642 #define USB_DEVICE_DADD_DADD_Msk (_UINT8_(0x7F) << USB_DEVICE_DADD_DADD_Pos) /* (USB_DEVICE_DADD) Device Address Mask */ 643 #define USB_DEVICE_DADD_DADD(value) (USB_DEVICE_DADD_DADD_Msk & (_UINT8_(value) << USB_DEVICE_DADD_DADD_Pos)) /* Assigment of value for DADD in the USB_DEVICE_DADD register */ 644 #define USB_DEVICE_DADD_ADDEN_Pos _UINT8_(7) /* (USB_DEVICE_DADD) Device Address Enable Position */ 645 #define USB_DEVICE_DADD_ADDEN_Msk (_UINT8_(0x1) << USB_DEVICE_DADD_ADDEN_Pos) /* (USB_DEVICE_DADD) Device Address Enable Mask */ 646 #define USB_DEVICE_DADD_ADDEN(value) (USB_DEVICE_DADD_ADDEN_Msk & (_UINT8_(value) << USB_DEVICE_DADD_ADDEN_Pos)) /* Assigment of value for ADDEN in the USB_DEVICE_DADD register */ 647 #define USB_DEVICE_DADD_Msk _UINT8_(0xFF) /* (USB_DEVICE_DADD) Register Mask */ 648 649 650 /* -------- USB_HOST_HSOFC : (USB Offset: 0x0A) (R/W 8) HOST Host Start Of Frame Control -------- */ 651 #define USB_HOST_HSOFC_RESETVALUE _UINT8_(0x00) /* (USB_HOST_HSOFC) HOST Host Start Of Frame Control Reset Value */ 652 653 #define USB_HOST_HSOFC_FLENC_Pos _UINT8_(0) /* (USB_HOST_HSOFC) Frame Length Control Position */ 654 #define USB_HOST_HSOFC_FLENC_Msk (_UINT8_(0xF) << USB_HOST_HSOFC_FLENC_Pos) /* (USB_HOST_HSOFC) Frame Length Control Mask */ 655 #define USB_HOST_HSOFC_FLENC(value) (USB_HOST_HSOFC_FLENC_Msk & (_UINT8_(value) << USB_HOST_HSOFC_FLENC_Pos)) /* Assigment of value for FLENC in the USB_HOST_HSOFC register */ 656 #define USB_HOST_HSOFC_FLENCE_Pos _UINT8_(7) /* (USB_HOST_HSOFC) Frame Length Control Enable Position */ 657 #define USB_HOST_HSOFC_FLENCE_Msk (_UINT8_(0x1) << USB_HOST_HSOFC_FLENCE_Pos) /* (USB_HOST_HSOFC) Frame Length Control Enable Mask */ 658 #define USB_HOST_HSOFC_FLENCE(value) (USB_HOST_HSOFC_FLENCE_Msk & (_UINT8_(value) << USB_HOST_HSOFC_FLENCE_Pos)) /* Assigment of value for FLENCE in the USB_HOST_HSOFC register */ 659 #define USB_HOST_HSOFC_Msk _UINT8_(0x8F) /* (USB_HOST_HSOFC) Register Mask */ 660 661 662 /* -------- USB_DEVICE_STATUS : (USB Offset: 0x0C) ( R/ 8) DEVICE Status -------- */ 663 #define USB_DEVICE_STATUS_RESETVALUE _UINT8_(0x40) /* (USB_DEVICE_STATUS) DEVICE Status Reset Value */ 664 665 #define USB_DEVICE_STATUS_SPEED_Pos _UINT8_(2) /* (USB_DEVICE_STATUS) Speed Status Position */ 666 #define USB_DEVICE_STATUS_SPEED_Msk (_UINT8_(0x3) << USB_DEVICE_STATUS_SPEED_Pos) /* (USB_DEVICE_STATUS) Speed Status Mask */ 667 #define USB_DEVICE_STATUS_SPEED(value) (USB_DEVICE_STATUS_SPEED_Msk & (_UINT8_(value) << USB_DEVICE_STATUS_SPEED_Pos)) /* Assigment of value for SPEED in the USB_DEVICE_STATUS register */ 668 #define USB_DEVICE_STATUS_SPEED_FS_Val _UINT8_(0x0) /* (USB_DEVICE_STATUS) Full-speed mode */ 669 #define USB_DEVICE_STATUS_SPEED_LS_Val _UINT8_(0x1) /* (USB_DEVICE_STATUS) Low-speed mode */ 670 #define USB_DEVICE_STATUS_SPEED_FS (USB_DEVICE_STATUS_SPEED_FS_Val << USB_DEVICE_STATUS_SPEED_Pos) /* (USB_DEVICE_STATUS) Full-speed mode Position */ 671 #define USB_DEVICE_STATUS_SPEED_LS (USB_DEVICE_STATUS_SPEED_LS_Val << USB_DEVICE_STATUS_SPEED_Pos) /* (USB_DEVICE_STATUS) Low-speed mode Position */ 672 #define USB_DEVICE_STATUS_LINESTATE_Pos _UINT8_(6) /* (USB_DEVICE_STATUS) USB Line State Status Position */ 673 #define USB_DEVICE_STATUS_LINESTATE_Msk (_UINT8_(0x3) << USB_DEVICE_STATUS_LINESTATE_Pos) /* (USB_DEVICE_STATUS) USB Line State Status Mask */ 674 #define USB_DEVICE_STATUS_LINESTATE(value) (USB_DEVICE_STATUS_LINESTATE_Msk & (_UINT8_(value) << USB_DEVICE_STATUS_LINESTATE_Pos)) /* Assigment of value for LINESTATE in the USB_DEVICE_STATUS register */ 675 #define USB_DEVICE_STATUS_LINESTATE_SE0RESET_Val _UINT8_(0x0) /* (USB_DEVICE_STATUS) SE0/RESET */ 676 #define USB_DEVICE_STATUS_LINESTATE_FSJLSK_Val _UINT8_(0x1) /* (USB_DEVICE_STATUS) FS-J or LS-K State */ 677 #define USB_DEVICE_STATUS_LINESTATE_FSKLSJ_Val _UINT8_(0x2) /* (USB_DEVICE_STATUS) FS-K or LS-J State */ 678 #define USB_DEVICE_STATUS_LINESTATE_SE0RESET (USB_DEVICE_STATUS_LINESTATE_SE0RESET_Val << USB_DEVICE_STATUS_LINESTATE_Pos) /* (USB_DEVICE_STATUS) SE0/RESET Position */ 679 #define USB_DEVICE_STATUS_LINESTATE_FSJLSK (USB_DEVICE_STATUS_LINESTATE_FSJLSK_Val << USB_DEVICE_STATUS_LINESTATE_Pos) /* (USB_DEVICE_STATUS) FS-J or LS-K State Position */ 680 #define USB_DEVICE_STATUS_LINESTATE_FSKLSJ (USB_DEVICE_STATUS_LINESTATE_FSKLSJ_Val << USB_DEVICE_STATUS_LINESTATE_Pos) /* (USB_DEVICE_STATUS) FS-K or LS-J State Position */ 681 #define USB_DEVICE_STATUS_Msk _UINT8_(0xCC) /* (USB_DEVICE_STATUS) Register Mask */ 682 683 684 /* -------- USB_HOST_STATUS : (USB Offset: 0x0C) (R/W 8) HOST Status -------- */ 685 #define USB_HOST_STATUS_RESETVALUE _UINT8_(0x00) /* (USB_HOST_STATUS) HOST Status Reset Value */ 686 687 #define USB_HOST_STATUS_SPEED_Pos _UINT8_(2) /* (USB_HOST_STATUS) Speed Status Position */ 688 #define USB_HOST_STATUS_SPEED_Msk (_UINT8_(0x3) << USB_HOST_STATUS_SPEED_Pos) /* (USB_HOST_STATUS) Speed Status Mask */ 689 #define USB_HOST_STATUS_SPEED(value) (USB_HOST_STATUS_SPEED_Msk & (_UINT8_(value) << USB_HOST_STATUS_SPEED_Pos)) /* Assigment of value for SPEED in the USB_HOST_STATUS register */ 690 #define USB_HOST_STATUS_LINESTATE_Pos _UINT8_(6) /* (USB_HOST_STATUS) USB Line State Status Position */ 691 #define USB_HOST_STATUS_LINESTATE_Msk (_UINT8_(0x3) << USB_HOST_STATUS_LINESTATE_Pos) /* (USB_HOST_STATUS) USB Line State Status Mask */ 692 #define USB_HOST_STATUS_LINESTATE(value) (USB_HOST_STATUS_LINESTATE_Msk & (_UINT8_(value) << USB_HOST_STATUS_LINESTATE_Pos)) /* Assigment of value for LINESTATE in the USB_HOST_STATUS register */ 693 #define USB_HOST_STATUS_Msk _UINT8_(0xCC) /* (USB_HOST_STATUS) Register Mask */ 694 695 696 /* -------- USB_FSMSTATUS : (USB Offset: 0x0D) ( R/ 8) Finite State Machine Status -------- */ 697 #define USB_FSMSTATUS_RESETVALUE _UINT8_(0x01) /* (USB_FSMSTATUS) Finite State Machine Status Reset Value */ 698 699 #define USB_FSMSTATUS_FSMSTATE_Pos _UINT8_(0) /* (USB_FSMSTATUS) Fine State Machine Status Position */ 700 #define USB_FSMSTATUS_FSMSTATE_Msk (_UINT8_(0x7F) << USB_FSMSTATUS_FSMSTATE_Pos) /* (USB_FSMSTATUS) Fine State Machine Status Mask */ 701 #define USB_FSMSTATUS_FSMSTATE(value) (USB_FSMSTATUS_FSMSTATE_Msk & (_UINT8_(value) << USB_FSMSTATUS_FSMSTATE_Pos)) /* Assigment of value for FSMSTATE in the USB_FSMSTATUS register */ 702 #define USB_FSMSTATUS_FSMSTATE_OFF_Val _UINT8_(0x1) /* (USB_FSMSTATUS) OFF (L3). It corresponds to the powered-off, disconnected, and disabled state */ 703 #define USB_FSMSTATUS_FSMSTATE_ON_Val _UINT8_(0x2) /* (USB_FSMSTATUS) ON (L0). It corresponds to the Idle and Active states */ 704 #define USB_FSMSTATUS_FSMSTATE_SUSPEND_Val _UINT8_(0x4) /* (USB_FSMSTATUS) SUSPEND (L2) */ 705 #define USB_FSMSTATUS_FSMSTATE_SLEEP_Val _UINT8_(0x8) /* (USB_FSMSTATUS) SLEEP (L1) */ 706 #define USB_FSMSTATUS_FSMSTATE_DNRESUME_Val _UINT8_(0x10) /* (USB_FSMSTATUS) DNRESUME. Down Stream Resume. */ 707 #define USB_FSMSTATUS_FSMSTATE_UPRESUME_Val _UINT8_(0x20) /* (USB_FSMSTATUS) UPRESUME. Up Stream Resume. */ 708 #define USB_FSMSTATUS_FSMSTATE_RESET_Val _UINT8_(0x40) /* (USB_FSMSTATUS) RESET. USB lines Reset. */ 709 #define USB_FSMSTATUS_FSMSTATE_OFF (USB_FSMSTATUS_FSMSTATE_OFF_Val << USB_FSMSTATUS_FSMSTATE_Pos) /* (USB_FSMSTATUS) OFF (L3). It corresponds to the powered-off, disconnected, and disabled state Position */ 710 #define USB_FSMSTATUS_FSMSTATE_ON (USB_FSMSTATUS_FSMSTATE_ON_Val << USB_FSMSTATUS_FSMSTATE_Pos) /* (USB_FSMSTATUS) ON (L0). It corresponds to the Idle and Active states Position */ 711 #define USB_FSMSTATUS_FSMSTATE_SUSPEND (USB_FSMSTATUS_FSMSTATE_SUSPEND_Val << USB_FSMSTATUS_FSMSTATE_Pos) /* (USB_FSMSTATUS) SUSPEND (L2) Position */ 712 #define USB_FSMSTATUS_FSMSTATE_SLEEP (USB_FSMSTATUS_FSMSTATE_SLEEP_Val << USB_FSMSTATUS_FSMSTATE_Pos) /* (USB_FSMSTATUS) SLEEP (L1) Position */ 713 #define USB_FSMSTATUS_FSMSTATE_DNRESUME (USB_FSMSTATUS_FSMSTATE_DNRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos) /* (USB_FSMSTATUS) DNRESUME. Down Stream Resume. Position */ 714 #define USB_FSMSTATUS_FSMSTATE_UPRESUME (USB_FSMSTATUS_FSMSTATE_UPRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos) /* (USB_FSMSTATUS) UPRESUME. Up Stream Resume. Position */ 715 #define USB_FSMSTATUS_FSMSTATE_RESET (USB_FSMSTATUS_FSMSTATE_RESET_Val << USB_FSMSTATUS_FSMSTATE_Pos) /* (USB_FSMSTATUS) RESET. USB lines Reset. Position */ 716 #define USB_FSMSTATUS_Msk _UINT8_(0x7F) /* (USB_FSMSTATUS) Register Mask */ 717 718 719 /* -------- USB_DEVICE_FNUM : (USB Offset: 0x10) ( R/ 16) DEVICE Device Frame Number -------- */ 720 #define USB_DEVICE_FNUM_RESETVALUE _UINT16_(0x00) /* (USB_DEVICE_FNUM) DEVICE Device Frame Number Reset Value */ 721 722 #define USB_DEVICE_FNUM_FNUM_Pos _UINT16_(3) /* (USB_DEVICE_FNUM) Frame Number Position */ 723 #define USB_DEVICE_FNUM_FNUM_Msk (_UINT16_(0x7FF) << USB_DEVICE_FNUM_FNUM_Pos) /* (USB_DEVICE_FNUM) Frame Number Mask */ 724 #define USB_DEVICE_FNUM_FNUM(value) (USB_DEVICE_FNUM_FNUM_Msk & (_UINT16_(value) << USB_DEVICE_FNUM_FNUM_Pos)) /* Assigment of value for FNUM in the USB_DEVICE_FNUM register */ 725 #define USB_DEVICE_FNUM_FNCERR_Pos _UINT16_(15) /* (USB_DEVICE_FNUM) Frame Number CRC Error Position */ 726 #define USB_DEVICE_FNUM_FNCERR_Msk (_UINT16_(0x1) << USB_DEVICE_FNUM_FNCERR_Pos) /* (USB_DEVICE_FNUM) Frame Number CRC Error Mask */ 727 #define USB_DEVICE_FNUM_FNCERR(value) (USB_DEVICE_FNUM_FNCERR_Msk & (_UINT16_(value) << USB_DEVICE_FNUM_FNCERR_Pos)) /* Assigment of value for FNCERR in the USB_DEVICE_FNUM register */ 728 #define USB_DEVICE_FNUM_Msk _UINT16_(0xBFF8) /* (USB_DEVICE_FNUM) Register Mask */ 729 730 731 /* -------- USB_HOST_FNUM : (USB Offset: 0x10) (R/W 16) HOST Host Frame Number -------- */ 732 #define USB_HOST_FNUM_RESETVALUE _UINT16_(0x00) /* (USB_HOST_FNUM) HOST Host Frame Number Reset Value */ 733 734 #define USB_HOST_FNUM_FNUM_Pos _UINT16_(3) /* (USB_HOST_FNUM) Frame Number Position */ 735 #define USB_HOST_FNUM_FNUM_Msk (_UINT16_(0x7FF) << USB_HOST_FNUM_FNUM_Pos) /* (USB_HOST_FNUM) Frame Number Mask */ 736 #define USB_HOST_FNUM_FNUM(value) (USB_HOST_FNUM_FNUM_Msk & (_UINT16_(value) << USB_HOST_FNUM_FNUM_Pos)) /* Assigment of value for FNUM in the USB_HOST_FNUM register */ 737 #define USB_HOST_FNUM_Msk _UINT16_(0x3FF8) /* (USB_HOST_FNUM) Register Mask */ 738 739 740 /* -------- USB_HOST_FLENHIGH : (USB Offset: 0x12) ( R/ 8) HOST Host Frame Length -------- */ 741 #define USB_HOST_FLENHIGH_RESETVALUE _UINT8_(0x00) /* (USB_HOST_FLENHIGH) HOST Host Frame Length Reset Value */ 742 743 #define USB_HOST_FLENHIGH_FLENHIGH_Pos _UINT8_(0) /* (USB_HOST_FLENHIGH) Frame Length Position */ 744 #define USB_HOST_FLENHIGH_FLENHIGH_Msk (_UINT8_(0xFF) << USB_HOST_FLENHIGH_FLENHIGH_Pos) /* (USB_HOST_FLENHIGH) Frame Length Mask */ 745 #define USB_HOST_FLENHIGH_FLENHIGH(value) (USB_HOST_FLENHIGH_FLENHIGH_Msk & (_UINT8_(value) << USB_HOST_FLENHIGH_FLENHIGH_Pos)) /* Assigment of value for FLENHIGH in the USB_HOST_FLENHIGH register */ 746 #define USB_HOST_FLENHIGH_Msk _UINT8_(0xFF) /* (USB_HOST_FLENHIGH) Register Mask */ 747 748 749 /* -------- USB_DEVICE_INTENCLR : (USB Offset: 0x14) (R/W 16) DEVICE Device Interrupt Enable Clear -------- */ 750 #define USB_DEVICE_INTENCLR_RESETVALUE _UINT16_(0x00) /* (USB_DEVICE_INTENCLR) DEVICE Device Interrupt Enable Clear Reset Value */ 751 752 #define USB_DEVICE_INTENCLR_SUSPEND_Pos _UINT16_(0) /* (USB_DEVICE_INTENCLR) Suspend Interrupt Enable Position */ 753 #define USB_DEVICE_INTENCLR_SUSPEND_Msk (_UINT16_(0x1) << USB_DEVICE_INTENCLR_SUSPEND_Pos) /* (USB_DEVICE_INTENCLR) Suspend Interrupt Enable Mask */ 754 #define USB_DEVICE_INTENCLR_SUSPEND(value) (USB_DEVICE_INTENCLR_SUSPEND_Msk & (_UINT16_(value) << USB_DEVICE_INTENCLR_SUSPEND_Pos)) /* Assigment of value for SUSPEND in the USB_DEVICE_INTENCLR register */ 755 #define USB_DEVICE_INTENCLR_SOF_Pos _UINT16_(2) /* (USB_DEVICE_INTENCLR) Start Of Frame Interrupt Enable Position */ 756 #define USB_DEVICE_INTENCLR_SOF_Msk (_UINT16_(0x1) << USB_DEVICE_INTENCLR_SOF_Pos) /* (USB_DEVICE_INTENCLR) Start Of Frame Interrupt Enable Mask */ 757 #define USB_DEVICE_INTENCLR_SOF(value) (USB_DEVICE_INTENCLR_SOF_Msk & (_UINT16_(value) << USB_DEVICE_INTENCLR_SOF_Pos)) /* Assigment of value for SOF in the USB_DEVICE_INTENCLR register */ 758 #define USB_DEVICE_INTENCLR_EORST_Pos _UINT16_(3) /* (USB_DEVICE_INTENCLR) End of Reset Interrupt Enable Position */ 759 #define USB_DEVICE_INTENCLR_EORST_Msk (_UINT16_(0x1) << USB_DEVICE_INTENCLR_EORST_Pos) /* (USB_DEVICE_INTENCLR) End of Reset Interrupt Enable Mask */ 760 #define USB_DEVICE_INTENCLR_EORST(value) (USB_DEVICE_INTENCLR_EORST_Msk & (_UINT16_(value) << USB_DEVICE_INTENCLR_EORST_Pos)) /* Assigment of value for EORST in the USB_DEVICE_INTENCLR register */ 761 #define USB_DEVICE_INTENCLR_WAKEUP_Pos _UINT16_(4) /* (USB_DEVICE_INTENCLR) Wake Up Interrupt Enable Position */ 762 #define USB_DEVICE_INTENCLR_WAKEUP_Msk (_UINT16_(0x1) << USB_DEVICE_INTENCLR_WAKEUP_Pos) /* (USB_DEVICE_INTENCLR) Wake Up Interrupt Enable Mask */ 763 #define USB_DEVICE_INTENCLR_WAKEUP(value) (USB_DEVICE_INTENCLR_WAKEUP_Msk & (_UINT16_(value) << USB_DEVICE_INTENCLR_WAKEUP_Pos)) /* Assigment of value for WAKEUP in the USB_DEVICE_INTENCLR register */ 764 #define USB_DEVICE_INTENCLR_EORSM_Pos _UINT16_(5) /* (USB_DEVICE_INTENCLR) End Of Resume Interrupt Enable Position */ 765 #define USB_DEVICE_INTENCLR_EORSM_Msk (_UINT16_(0x1) << USB_DEVICE_INTENCLR_EORSM_Pos) /* (USB_DEVICE_INTENCLR) End Of Resume Interrupt Enable Mask */ 766 #define USB_DEVICE_INTENCLR_EORSM(value) (USB_DEVICE_INTENCLR_EORSM_Msk & (_UINT16_(value) << USB_DEVICE_INTENCLR_EORSM_Pos)) /* Assigment of value for EORSM in the USB_DEVICE_INTENCLR register */ 767 #define USB_DEVICE_INTENCLR_UPRSM_Pos _UINT16_(6) /* (USB_DEVICE_INTENCLR) Upstream Resume Interrupt Enable Position */ 768 #define USB_DEVICE_INTENCLR_UPRSM_Msk (_UINT16_(0x1) << USB_DEVICE_INTENCLR_UPRSM_Pos) /* (USB_DEVICE_INTENCLR) Upstream Resume Interrupt Enable Mask */ 769 #define USB_DEVICE_INTENCLR_UPRSM(value) (USB_DEVICE_INTENCLR_UPRSM_Msk & (_UINT16_(value) << USB_DEVICE_INTENCLR_UPRSM_Pos)) /* Assigment of value for UPRSM in the USB_DEVICE_INTENCLR register */ 770 #define USB_DEVICE_INTENCLR_RAMACER_Pos _UINT16_(7) /* (USB_DEVICE_INTENCLR) Ram Access Interrupt Enable Position */ 771 #define USB_DEVICE_INTENCLR_RAMACER_Msk (_UINT16_(0x1) << USB_DEVICE_INTENCLR_RAMACER_Pos) /* (USB_DEVICE_INTENCLR) Ram Access Interrupt Enable Mask */ 772 #define USB_DEVICE_INTENCLR_RAMACER(value) (USB_DEVICE_INTENCLR_RAMACER_Msk & (_UINT16_(value) << USB_DEVICE_INTENCLR_RAMACER_Pos)) /* Assigment of value for RAMACER in the USB_DEVICE_INTENCLR register */ 773 #define USB_DEVICE_INTENCLR_LPMNYET_Pos _UINT16_(8) /* (USB_DEVICE_INTENCLR) Link Power Management Not Yet Interrupt Enable Position */ 774 #define USB_DEVICE_INTENCLR_LPMNYET_Msk (_UINT16_(0x1) << USB_DEVICE_INTENCLR_LPMNYET_Pos) /* (USB_DEVICE_INTENCLR) Link Power Management Not Yet Interrupt Enable Mask */ 775 #define USB_DEVICE_INTENCLR_LPMNYET(value) (USB_DEVICE_INTENCLR_LPMNYET_Msk & (_UINT16_(value) << USB_DEVICE_INTENCLR_LPMNYET_Pos)) /* Assigment of value for LPMNYET in the USB_DEVICE_INTENCLR register */ 776 #define USB_DEVICE_INTENCLR_LPMSUSP_Pos _UINT16_(9) /* (USB_DEVICE_INTENCLR) Link Power Management Suspend Interrupt Enable Position */ 777 #define USB_DEVICE_INTENCLR_LPMSUSP_Msk (_UINT16_(0x1) << USB_DEVICE_INTENCLR_LPMSUSP_Pos) /* (USB_DEVICE_INTENCLR) Link Power Management Suspend Interrupt Enable Mask */ 778 #define USB_DEVICE_INTENCLR_LPMSUSP(value) (USB_DEVICE_INTENCLR_LPMSUSP_Msk & (_UINT16_(value) << USB_DEVICE_INTENCLR_LPMSUSP_Pos)) /* Assigment of value for LPMSUSP in the USB_DEVICE_INTENCLR register */ 779 #define USB_DEVICE_INTENCLR_Msk _UINT16_(0x03FD) /* (USB_DEVICE_INTENCLR) Register Mask */ 780 781 782 /* -------- USB_HOST_INTENCLR : (USB Offset: 0x14) (R/W 16) HOST Host Interrupt Enable Clear -------- */ 783 #define USB_HOST_INTENCLR_RESETVALUE _UINT16_(0x00) /* (USB_HOST_INTENCLR) HOST Host Interrupt Enable Clear Reset Value */ 784 785 #define USB_HOST_INTENCLR_HSOF_Pos _UINT16_(2) /* (USB_HOST_INTENCLR) Host Start Of Frame Interrupt Disable Position */ 786 #define USB_HOST_INTENCLR_HSOF_Msk (_UINT16_(0x1) << USB_HOST_INTENCLR_HSOF_Pos) /* (USB_HOST_INTENCLR) Host Start Of Frame Interrupt Disable Mask */ 787 #define USB_HOST_INTENCLR_HSOF(value) (USB_HOST_INTENCLR_HSOF_Msk & (_UINT16_(value) << USB_HOST_INTENCLR_HSOF_Pos)) /* Assigment of value for HSOF in the USB_HOST_INTENCLR register */ 788 #define USB_HOST_INTENCLR_RST_Pos _UINT16_(3) /* (USB_HOST_INTENCLR) BUS Reset Interrupt Disable Position */ 789 #define USB_HOST_INTENCLR_RST_Msk (_UINT16_(0x1) << USB_HOST_INTENCLR_RST_Pos) /* (USB_HOST_INTENCLR) BUS Reset Interrupt Disable Mask */ 790 #define USB_HOST_INTENCLR_RST(value) (USB_HOST_INTENCLR_RST_Msk & (_UINT16_(value) << USB_HOST_INTENCLR_RST_Pos)) /* Assigment of value for RST in the USB_HOST_INTENCLR register */ 791 #define USB_HOST_INTENCLR_WAKEUP_Pos _UINT16_(4) /* (USB_HOST_INTENCLR) Wake Up Interrupt Disable Position */ 792 #define USB_HOST_INTENCLR_WAKEUP_Msk (_UINT16_(0x1) << USB_HOST_INTENCLR_WAKEUP_Pos) /* (USB_HOST_INTENCLR) Wake Up Interrupt Disable Mask */ 793 #define USB_HOST_INTENCLR_WAKEUP(value) (USB_HOST_INTENCLR_WAKEUP_Msk & (_UINT16_(value) << USB_HOST_INTENCLR_WAKEUP_Pos)) /* Assigment of value for WAKEUP in the USB_HOST_INTENCLR register */ 794 #define USB_HOST_INTENCLR_DNRSM_Pos _UINT16_(5) /* (USB_HOST_INTENCLR) DownStream to Device Interrupt Disable Position */ 795 #define USB_HOST_INTENCLR_DNRSM_Msk (_UINT16_(0x1) << USB_HOST_INTENCLR_DNRSM_Pos) /* (USB_HOST_INTENCLR) DownStream to Device Interrupt Disable Mask */ 796 #define USB_HOST_INTENCLR_DNRSM(value) (USB_HOST_INTENCLR_DNRSM_Msk & (_UINT16_(value) << USB_HOST_INTENCLR_DNRSM_Pos)) /* Assigment of value for DNRSM in the USB_HOST_INTENCLR register */ 797 #define USB_HOST_INTENCLR_UPRSM_Pos _UINT16_(6) /* (USB_HOST_INTENCLR) Upstream Resume from Device Interrupt Disable Position */ 798 #define USB_HOST_INTENCLR_UPRSM_Msk (_UINT16_(0x1) << USB_HOST_INTENCLR_UPRSM_Pos) /* (USB_HOST_INTENCLR) Upstream Resume from Device Interrupt Disable Mask */ 799 #define USB_HOST_INTENCLR_UPRSM(value) (USB_HOST_INTENCLR_UPRSM_Msk & (_UINT16_(value) << USB_HOST_INTENCLR_UPRSM_Pos)) /* Assigment of value for UPRSM in the USB_HOST_INTENCLR register */ 800 #define USB_HOST_INTENCLR_RAMACER_Pos _UINT16_(7) /* (USB_HOST_INTENCLR) Ram Access Interrupt Disable Position */ 801 #define USB_HOST_INTENCLR_RAMACER_Msk (_UINT16_(0x1) << USB_HOST_INTENCLR_RAMACER_Pos) /* (USB_HOST_INTENCLR) Ram Access Interrupt Disable Mask */ 802 #define USB_HOST_INTENCLR_RAMACER(value) (USB_HOST_INTENCLR_RAMACER_Msk & (_UINT16_(value) << USB_HOST_INTENCLR_RAMACER_Pos)) /* Assigment of value for RAMACER in the USB_HOST_INTENCLR register */ 803 #define USB_HOST_INTENCLR_DCONN_Pos _UINT16_(8) /* (USB_HOST_INTENCLR) Device Connection Interrupt Disable Position */ 804 #define USB_HOST_INTENCLR_DCONN_Msk (_UINT16_(0x1) << USB_HOST_INTENCLR_DCONN_Pos) /* (USB_HOST_INTENCLR) Device Connection Interrupt Disable Mask */ 805 #define USB_HOST_INTENCLR_DCONN(value) (USB_HOST_INTENCLR_DCONN_Msk & (_UINT16_(value) << USB_HOST_INTENCLR_DCONN_Pos)) /* Assigment of value for DCONN in the USB_HOST_INTENCLR register */ 806 #define USB_HOST_INTENCLR_DDISC_Pos _UINT16_(9) /* (USB_HOST_INTENCLR) Device Disconnection Interrupt Disable Position */ 807 #define USB_HOST_INTENCLR_DDISC_Msk (_UINT16_(0x1) << USB_HOST_INTENCLR_DDISC_Pos) /* (USB_HOST_INTENCLR) Device Disconnection Interrupt Disable Mask */ 808 #define USB_HOST_INTENCLR_DDISC(value) (USB_HOST_INTENCLR_DDISC_Msk & (_UINT16_(value) << USB_HOST_INTENCLR_DDISC_Pos)) /* Assigment of value for DDISC in the USB_HOST_INTENCLR register */ 809 #define USB_HOST_INTENCLR_Msk _UINT16_(0x03FC) /* (USB_HOST_INTENCLR) Register Mask */ 810 811 812 /* -------- USB_DEVICE_INTENSET : (USB Offset: 0x18) (R/W 16) DEVICE Device Interrupt Enable Set -------- */ 813 #define USB_DEVICE_INTENSET_RESETVALUE _UINT16_(0x00) /* (USB_DEVICE_INTENSET) DEVICE Device Interrupt Enable Set Reset Value */ 814 815 #define USB_DEVICE_INTENSET_SUSPEND_Pos _UINT16_(0) /* (USB_DEVICE_INTENSET) Suspend Interrupt Enable Position */ 816 #define USB_DEVICE_INTENSET_SUSPEND_Msk (_UINT16_(0x1) << USB_DEVICE_INTENSET_SUSPEND_Pos) /* (USB_DEVICE_INTENSET) Suspend Interrupt Enable Mask */ 817 #define USB_DEVICE_INTENSET_SUSPEND(value) (USB_DEVICE_INTENSET_SUSPEND_Msk & (_UINT16_(value) << USB_DEVICE_INTENSET_SUSPEND_Pos)) /* Assigment of value for SUSPEND in the USB_DEVICE_INTENSET register */ 818 #define USB_DEVICE_INTENSET_SOF_Pos _UINT16_(2) /* (USB_DEVICE_INTENSET) Start Of Frame Interrupt Enable Position */ 819 #define USB_DEVICE_INTENSET_SOF_Msk (_UINT16_(0x1) << USB_DEVICE_INTENSET_SOF_Pos) /* (USB_DEVICE_INTENSET) Start Of Frame Interrupt Enable Mask */ 820 #define USB_DEVICE_INTENSET_SOF(value) (USB_DEVICE_INTENSET_SOF_Msk & (_UINT16_(value) << USB_DEVICE_INTENSET_SOF_Pos)) /* Assigment of value for SOF in the USB_DEVICE_INTENSET register */ 821 #define USB_DEVICE_INTENSET_EORST_Pos _UINT16_(3) /* (USB_DEVICE_INTENSET) End of Reset Interrupt Enable Position */ 822 #define USB_DEVICE_INTENSET_EORST_Msk (_UINT16_(0x1) << USB_DEVICE_INTENSET_EORST_Pos) /* (USB_DEVICE_INTENSET) End of Reset Interrupt Enable Mask */ 823 #define USB_DEVICE_INTENSET_EORST(value) (USB_DEVICE_INTENSET_EORST_Msk & (_UINT16_(value) << USB_DEVICE_INTENSET_EORST_Pos)) /* Assigment of value for EORST in the USB_DEVICE_INTENSET register */ 824 #define USB_DEVICE_INTENSET_WAKEUP_Pos _UINT16_(4) /* (USB_DEVICE_INTENSET) Wake Up Interrupt Enable Position */ 825 #define USB_DEVICE_INTENSET_WAKEUP_Msk (_UINT16_(0x1) << USB_DEVICE_INTENSET_WAKEUP_Pos) /* (USB_DEVICE_INTENSET) Wake Up Interrupt Enable Mask */ 826 #define USB_DEVICE_INTENSET_WAKEUP(value) (USB_DEVICE_INTENSET_WAKEUP_Msk & (_UINT16_(value) << USB_DEVICE_INTENSET_WAKEUP_Pos)) /* Assigment of value for WAKEUP in the USB_DEVICE_INTENSET register */ 827 #define USB_DEVICE_INTENSET_EORSM_Pos _UINT16_(5) /* (USB_DEVICE_INTENSET) End Of Resume Interrupt Enable Position */ 828 #define USB_DEVICE_INTENSET_EORSM_Msk (_UINT16_(0x1) << USB_DEVICE_INTENSET_EORSM_Pos) /* (USB_DEVICE_INTENSET) End Of Resume Interrupt Enable Mask */ 829 #define USB_DEVICE_INTENSET_EORSM(value) (USB_DEVICE_INTENSET_EORSM_Msk & (_UINT16_(value) << USB_DEVICE_INTENSET_EORSM_Pos)) /* Assigment of value for EORSM in the USB_DEVICE_INTENSET register */ 830 #define USB_DEVICE_INTENSET_UPRSM_Pos _UINT16_(6) /* (USB_DEVICE_INTENSET) Upstream Resume Interrupt Enable Position */ 831 #define USB_DEVICE_INTENSET_UPRSM_Msk (_UINT16_(0x1) << USB_DEVICE_INTENSET_UPRSM_Pos) /* (USB_DEVICE_INTENSET) Upstream Resume Interrupt Enable Mask */ 832 #define USB_DEVICE_INTENSET_UPRSM(value) (USB_DEVICE_INTENSET_UPRSM_Msk & (_UINT16_(value) << USB_DEVICE_INTENSET_UPRSM_Pos)) /* Assigment of value for UPRSM in the USB_DEVICE_INTENSET register */ 833 #define USB_DEVICE_INTENSET_RAMACER_Pos _UINT16_(7) /* (USB_DEVICE_INTENSET) Ram Access Interrupt Enable Position */ 834 #define USB_DEVICE_INTENSET_RAMACER_Msk (_UINT16_(0x1) << USB_DEVICE_INTENSET_RAMACER_Pos) /* (USB_DEVICE_INTENSET) Ram Access Interrupt Enable Mask */ 835 #define USB_DEVICE_INTENSET_RAMACER(value) (USB_DEVICE_INTENSET_RAMACER_Msk & (_UINT16_(value) << USB_DEVICE_INTENSET_RAMACER_Pos)) /* Assigment of value for RAMACER in the USB_DEVICE_INTENSET register */ 836 #define USB_DEVICE_INTENSET_LPMNYET_Pos _UINT16_(8) /* (USB_DEVICE_INTENSET) Link Power Management Not Yet Interrupt Enable Position */ 837 #define USB_DEVICE_INTENSET_LPMNYET_Msk (_UINT16_(0x1) << USB_DEVICE_INTENSET_LPMNYET_Pos) /* (USB_DEVICE_INTENSET) Link Power Management Not Yet Interrupt Enable Mask */ 838 #define USB_DEVICE_INTENSET_LPMNYET(value) (USB_DEVICE_INTENSET_LPMNYET_Msk & (_UINT16_(value) << USB_DEVICE_INTENSET_LPMNYET_Pos)) /* Assigment of value for LPMNYET in the USB_DEVICE_INTENSET register */ 839 #define USB_DEVICE_INTENSET_LPMSUSP_Pos _UINT16_(9) /* (USB_DEVICE_INTENSET) Link Power Management Suspend Interrupt Enable Position */ 840 #define USB_DEVICE_INTENSET_LPMSUSP_Msk (_UINT16_(0x1) << USB_DEVICE_INTENSET_LPMSUSP_Pos) /* (USB_DEVICE_INTENSET) Link Power Management Suspend Interrupt Enable Mask */ 841 #define USB_DEVICE_INTENSET_LPMSUSP(value) (USB_DEVICE_INTENSET_LPMSUSP_Msk & (_UINT16_(value) << USB_DEVICE_INTENSET_LPMSUSP_Pos)) /* Assigment of value for LPMSUSP in the USB_DEVICE_INTENSET register */ 842 #define USB_DEVICE_INTENSET_Msk _UINT16_(0x03FD) /* (USB_DEVICE_INTENSET) Register Mask */ 843 844 845 /* -------- USB_HOST_INTENSET : (USB Offset: 0x18) (R/W 16) HOST Host Interrupt Enable Set -------- */ 846 #define USB_HOST_INTENSET_RESETVALUE _UINT16_(0x00) /* (USB_HOST_INTENSET) HOST Host Interrupt Enable Set Reset Value */ 847 848 #define USB_HOST_INTENSET_HSOF_Pos _UINT16_(2) /* (USB_HOST_INTENSET) Host Start Of Frame Interrupt Enable Position */ 849 #define USB_HOST_INTENSET_HSOF_Msk (_UINT16_(0x1) << USB_HOST_INTENSET_HSOF_Pos) /* (USB_HOST_INTENSET) Host Start Of Frame Interrupt Enable Mask */ 850 #define USB_HOST_INTENSET_HSOF(value) (USB_HOST_INTENSET_HSOF_Msk & (_UINT16_(value) << USB_HOST_INTENSET_HSOF_Pos)) /* Assigment of value for HSOF in the USB_HOST_INTENSET register */ 851 #define USB_HOST_INTENSET_RST_Pos _UINT16_(3) /* (USB_HOST_INTENSET) Bus Reset Interrupt Enable Position */ 852 #define USB_HOST_INTENSET_RST_Msk (_UINT16_(0x1) << USB_HOST_INTENSET_RST_Pos) /* (USB_HOST_INTENSET) Bus Reset Interrupt Enable Mask */ 853 #define USB_HOST_INTENSET_RST(value) (USB_HOST_INTENSET_RST_Msk & (_UINT16_(value) << USB_HOST_INTENSET_RST_Pos)) /* Assigment of value for RST in the USB_HOST_INTENSET register */ 854 #define USB_HOST_INTENSET_WAKEUP_Pos _UINT16_(4) /* (USB_HOST_INTENSET) Wake Up Interrupt Enable Position */ 855 #define USB_HOST_INTENSET_WAKEUP_Msk (_UINT16_(0x1) << USB_HOST_INTENSET_WAKEUP_Pos) /* (USB_HOST_INTENSET) Wake Up Interrupt Enable Mask */ 856 #define USB_HOST_INTENSET_WAKEUP(value) (USB_HOST_INTENSET_WAKEUP_Msk & (_UINT16_(value) << USB_HOST_INTENSET_WAKEUP_Pos)) /* Assigment of value for WAKEUP in the USB_HOST_INTENSET register */ 857 #define USB_HOST_INTENSET_DNRSM_Pos _UINT16_(5) /* (USB_HOST_INTENSET) DownStream to the Device Interrupt Enable Position */ 858 #define USB_HOST_INTENSET_DNRSM_Msk (_UINT16_(0x1) << USB_HOST_INTENSET_DNRSM_Pos) /* (USB_HOST_INTENSET) DownStream to the Device Interrupt Enable Mask */ 859 #define USB_HOST_INTENSET_DNRSM(value) (USB_HOST_INTENSET_DNRSM_Msk & (_UINT16_(value) << USB_HOST_INTENSET_DNRSM_Pos)) /* Assigment of value for DNRSM in the USB_HOST_INTENSET register */ 860 #define USB_HOST_INTENSET_UPRSM_Pos _UINT16_(6) /* (USB_HOST_INTENSET) Upstream Resume fromthe device Interrupt Enable Position */ 861 #define USB_HOST_INTENSET_UPRSM_Msk (_UINT16_(0x1) << USB_HOST_INTENSET_UPRSM_Pos) /* (USB_HOST_INTENSET) Upstream Resume fromthe device Interrupt Enable Mask */ 862 #define USB_HOST_INTENSET_UPRSM(value) (USB_HOST_INTENSET_UPRSM_Msk & (_UINT16_(value) << USB_HOST_INTENSET_UPRSM_Pos)) /* Assigment of value for UPRSM in the USB_HOST_INTENSET register */ 863 #define USB_HOST_INTENSET_RAMACER_Pos _UINT16_(7) /* (USB_HOST_INTENSET) Ram Access Interrupt Enable Position */ 864 #define USB_HOST_INTENSET_RAMACER_Msk (_UINT16_(0x1) << USB_HOST_INTENSET_RAMACER_Pos) /* (USB_HOST_INTENSET) Ram Access Interrupt Enable Mask */ 865 #define USB_HOST_INTENSET_RAMACER(value) (USB_HOST_INTENSET_RAMACER_Msk & (_UINT16_(value) << USB_HOST_INTENSET_RAMACER_Pos)) /* Assigment of value for RAMACER in the USB_HOST_INTENSET register */ 866 #define USB_HOST_INTENSET_DCONN_Pos _UINT16_(8) /* (USB_HOST_INTENSET) Link Power Management Interrupt Enable Position */ 867 #define USB_HOST_INTENSET_DCONN_Msk (_UINT16_(0x1) << USB_HOST_INTENSET_DCONN_Pos) /* (USB_HOST_INTENSET) Link Power Management Interrupt Enable Mask */ 868 #define USB_HOST_INTENSET_DCONN(value) (USB_HOST_INTENSET_DCONN_Msk & (_UINT16_(value) << USB_HOST_INTENSET_DCONN_Pos)) /* Assigment of value for DCONN in the USB_HOST_INTENSET register */ 869 #define USB_HOST_INTENSET_DDISC_Pos _UINT16_(9) /* (USB_HOST_INTENSET) Device Disconnection Interrupt Enable Position */ 870 #define USB_HOST_INTENSET_DDISC_Msk (_UINT16_(0x1) << USB_HOST_INTENSET_DDISC_Pos) /* (USB_HOST_INTENSET) Device Disconnection Interrupt Enable Mask */ 871 #define USB_HOST_INTENSET_DDISC(value) (USB_HOST_INTENSET_DDISC_Msk & (_UINT16_(value) << USB_HOST_INTENSET_DDISC_Pos)) /* Assigment of value for DDISC in the USB_HOST_INTENSET register */ 872 #define USB_HOST_INTENSET_Msk _UINT16_(0x03FC) /* (USB_HOST_INTENSET) Register Mask */ 873 874 875 /* -------- USB_DEVICE_INTFLAG : (USB Offset: 0x1C) (R/W 16) DEVICE Device Interrupt Flag -------- */ 876 #define USB_DEVICE_INTFLAG_RESETVALUE _UINT16_(0x00) /* (USB_DEVICE_INTFLAG) DEVICE Device Interrupt Flag Reset Value */ 877 878 #define USB_DEVICE_INTFLAG_SUSPEND_Pos _UINT16_(0) /* (USB_DEVICE_INTFLAG) Suspend Position */ 879 #define USB_DEVICE_INTFLAG_SUSPEND_Msk (_UINT16_(0x1) << USB_DEVICE_INTFLAG_SUSPEND_Pos) /* (USB_DEVICE_INTFLAG) Suspend Mask */ 880 #define USB_DEVICE_INTFLAG_SUSPEND(value) (USB_DEVICE_INTFLAG_SUSPEND_Msk & (_UINT16_(value) << USB_DEVICE_INTFLAG_SUSPEND_Pos)) /* Assigment of value for SUSPEND in the USB_DEVICE_INTFLAG register */ 881 #define USB_DEVICE_INTFLAG_SOF_Pos _UINT16_(2) /* (USB_DEVICE_INTFLAG) Start Of Frame Position */ 882 #define USB_DEVICE_INTFLAG_SOF_Msk (_UINT16_(0x1) << USB_DEVICE_INTFLAG_SOF_Pos) /* (USB_DEVICE_INTFLAG) Start Of Frame Mask */ 883 #define USB_DEVICE_INTFLAG_SOF(value) (USB_DEVICE_INTFLAG_SOF_Msk & (_UINT16_(value) << USB_DEVICE_INTFLAG_SOF_Pos)) /* Assigment of value for SOF in the USB_DEVICE_INTFLAG register */ 884 #define USB_DEVICE_INTFLAG_EORST_Pos _UINT16_(3) /* (USB_DEVICE_INTFLAG) End of Reset Position */ 885 #define USB_DEVICE_INTFLAG_EORST_Msk (_UINT16_(0x1) << USB_DEVICE_INTFLAG_EORST_Pos) /* (USB_DEVICE_INTFLAG) End of Reset Mask */ 886 #define USB_DEVICE_INTFLAG_EORST(value) (USB_DEVICE_INTFLAG_EORST_Msk & (_UINT16_(value) << USB_DEVICE_INTFLAG_EORST_Pos)) /* Assigment of value for EORST in the USB_DEVICE_INTFLAG register */ 887 #define USB_DEVICE_INTFLAG_WAKEUP_Pos _UINT16_(4) /* (USB_DEVICE_INTFLAG) Wake Up Position */ 888 #define USB_DEVICE_INTFLAG_WAKEUP_Msk (_UINT16_(0x1) << USB_DEVICE_INTFLAG_WAKEUP_Pos) /* (USB_DEVICE_INTFLAG) Wake Up Mask */ 889 #define USB_DEVICE_INTFLAG_WAKEUP(value) (USB_DEVICE_INTFLAG_WAKEUP_Msk & (_UINT16_(value) << USB_DEVICE_INTFLAG_WAKEUP_Pos)) /* Assigment of value for WAKEUP in the USB_DEVICE_INTFLAG register */ 890 #define USB_DEVICE_INTFLAG_EORSM_Pos _UINT16_(5) /* (USB_DEVICE_INTFLAG) End Of Resume Position */ 891 #define USB_DEVICE_INTFLAG_EORSM_Msk (_UINT16_(0x1) << USB_DEVICE_INTFLAG_EORSM_Pos) /* (USB_DEVICE_INTFLAG) End Of Resume Mask */ 892 #define USB_DEVICE_INTFLAG_EORSM(value) (USB_DEVICE_INTFLAG_EORSM_Msk & (_UINT16_(value) << USB_DEVICE_INTFLAG_EORSM_Pos)) /* Assigment of value for EORSM in the USB_DEVICE_INTFLAG register */ 893 #define USB_DEVICE_INTFLAG_UPRSM_Pos _UINT16_(6) /* (USB_DEVICE_INTFLAG) Upstream Resume Position */ 894 #define USB_DEVICE_INTFLAG_UPRSM_Msk (_UINT16_(0x1) << USB_DEVICE_INTFLAG_UPRSM_Pos) /* (USB_DEVICE_INTFLAG) Upstream Resume Mask */ 895 #define USB_DEVICE_INTFLAG_UPRSM(value) (USB_DEVICE_INTFLAG_UPRSM_Msk & (_UINT16_(value) << USB_DEVICE_INTFLAG_UPRSM_Pos)) /* Assigment of value for UPRSM in the USB_DEVICE_INTFLAG register */ 896 #define USB_DEVICE_INTFLAG_RAMACER_Pos _UINT16_(7) /* (USB_DEVICE_INTFLAG) Ram Access Position */ 897 #define USB_DEVICE_INTFLAG_RAMACER_Msk (_UINT16_(0x1) << USB_DEVICE_INTFLAG_RAMACER_Pos) /* (USB_DEVICE_INTFLAG) Ram Access Mask */ 898 #define USB_DEVICE_INTFLAG_RAMACER(value) (USB_DEVICE_INTFLAG_RAMACER_Msk & (_UINT16_(value) << USB_DEVICE_INTFLAG_RAMACER_Pos)) /* Assigment of value for RAMACER in the USB_DEVICE_INTFLAG register */ 899 #define USB_DEVICE_INTFLAG_LPMNYET_Pos _UINT16_(8) /* (USB_DEVICE_INTFLAG) Link Power Management Not Yet Position */ 900 #define USB_DEVICE_INTFLAG_LPMNYET_Msk (_UINT16_(0x1) << USB_DEVICE_INTFLAG_LPMNYET_Pos) /* (USB_DEVICE_INTFLAG) Link Power Management Not Yet Mask */ 901 #define USB_DEVICE_INTFLAG_LPMNYET(value) (USB_DEVICE_INTFLAG_LPMNYET_Msk & (_UINT16_(value) << USB_DEVICE_INTFLAG_LPMNYET_Pos)) /* Assigment of value for LPMNYET in the USB_DEVICE_INTFLAG register */ 902 #define USB_DEVICE_INTFLAG_LPMSUSP_Pos _UINT16_(9) /* (USB_DEVICE_INTFLAG) Link Power Management Suspend Position */ 903 #define USB_DEVICE_INTFLAG_LPMSUSP_Msk (_UINT16_(0x1) << USB_DEVICE_INTFLAG_LPMSUSP_Pos) /* (USB_DEVICE_INTFLAG) Link Power Management Suspend Mask */ 904 #define USB_DEVICE_INTFLAG_LPMSUSP(value) (USB_DEVICE_INTFLAG_LPMSUSP_Msk & (_UINT16_(value) << USB_DEVICE_INTFLAG_LPMSUSP_Pos)) /* Assigment of value for LPMSUSP in the USB_DEVICE_INTFLAG register */ 905 #define USB_DEVICE_INTFLAG_Msk _UINT16_(0x03FD) /* (USB_DEVICE_INTFLAG) Register Mask */ 906 907 908 /* -------- USB_HOST_INTFLAG : (USB Offset: 0x1C) (R/W 16) HOST Host Interrupt Flag -------- */ 909 #define USB_HOST_INTFLAG_RESETVALUE _UINT16_(0x00) /* (USB_HOST_INTFLAG) HOST Host Interrupt Flag Reset Value */ 910 911 #define USB_HOST_INTFLAG_HSOF_Pos _UINT16_(2) /* (USB_HOST_INTFLAG) Host Start Of Frame Position */ 912 #define USB_HOST_INTFLAG_HSOF_Msk (_UINT16_(0x1) << USB_HOST_INTFLAG_HSOF_Pos) /* (USB_HOST_INTFLAG) Host Start Of Frame Mask */ 913 #define USB_HOST_INTFLAG_HSOF(value) (USB_HOST_INTFLAG_HSOF_Msk & (_UINT16_(value) << USB_HOST_INTFLAG_HSOF_Pos)) /* Assigment of value for HSOF in the USB_HOST_INTFLAG register */ 914 #define USB_HOST_INTFLAG_RST_Pos _UINT16_(3) /* (USB_HOST_INTFLAG) Bus Reset Position */ 915 #define USB_HOST_INTFLAG_RST_Msk (_UINT16_(0x1) << USB_HOST_INTFLAG_RST_Pos) /* (USB_HOST_INTFLAG) Bus Reset Mask */ 916 #define USB_HOST_INTFLAG_RST(value) (USB_HOST_INTFLAG_RST_Msk & (_UINT16_(value) << USB_HOST_INTFLAG_RST_Pos)) /* Assigment of value for RST in the USB_HOST_INTFLAG register */ 917 #define USB_HOST_INTFLAG_WAKEUP_Pos _UINT16_(4) /* (USB_HOST_INTFLAG) Wake Up Position */ 918 #define USB_HOST_INTFLAG_WAKEUP_Msk (_UINT16_(0x1) << USB_HOST_INTFLAG_WAKEUP_Pos) /* (USB_HOST_INTFLAG) Wake Up Mask */ 919 #define USB_HOST_INTFLAG_WAKEUP(value) (USB_HOST_INTFLAG_WAKEUP_Msk & (_UINT16_(value) << USB_HOST_INTFLAG_WAKEUP_Pos)) /* Assigment of value for WAKEUP in the USB_HOST_INTFLAG register */ 920 #define USB_HOST_INTFLAG_DNRSM_Pos _UINT16_(5) /* (USB_HOST_INTFLAG) Downstream Position */ 921 #define USB_HOST_INTFLAG_DNRSM_Msk (_UINT16_(0x1) << USB_HOST_INTFLAG_DNRSM_Pos) /* (USB_HOST_INTFLAG) Downstream Mask */ 922 #define USB_HOST_INTFLAG_DNRSM(value) (USB_HOST_INTFLAG_DNRSM_Msk & (_UINT16_(value) << USB_HOST_INTFLAG_DNRSM_Pos)) /* Assigment of value for DNRSM in the USB_HOST_INTFLAG register */ 923 #define USB_HOST_INTFLAG_UPRSM_Pos _UINT16_(6) /* (USB_HOST_INTFLAG) Upstream Resume from the Device Position */ 924 #define USB_HOST_INTFLAG_UPRSM_Msk (_UINT16_(0x1) << USB_HOST_INTFLAG_UPRSM_Pos) /* (USB_HOST_INTFLAG) Upstream Resume from the Device Mask */ 925 #define USB_HOST_INTFLAG_UPRSM(value) (USB_HOST_INTFLAG_UPRSM_Msk & (_UINT16_(value) << USB_HOST_INTFLAG_UPRSM_Pos)) /* Assigment of value for UPRSM in the USB_HOST_INTFLAG register */ 926 #define USB_HOST_INTFLAG_RAMACER_Pos _UINT16_(7) /* (USB_HOST_INTFLAG) Ram Access Position */ 927 #define USB_HOST_INTFLAG_RAMACER_Msk (_UINT16_(0x1) << USB_HOST_INTFLAG_RAMACER_Pos) /* (USB_HOST_INTFLAG) Ram Access Mask */ 928 #define USB_HOST_INTFLAG_RAMACER(value) (USB_HOST_INTFLAG_RAMACER_Msk & (_UINT16_(value) << USB_HOST_INTFLAG_RAMACER_Pos)) /* Assigment of value for RAMACER in the USB_HOST_INTFLAG register */ 929 #define USB_HOST_INTFLAG_DCONN_Pos _UINT16_(8) /* (USB_HOST_INTFLAG) Device Connection Position */ 930 #define USB_HOST_INTFLAG_DCONN_Msk (_UINT16_(0x1) << USB_HOST_INTFLAG_DCONN_Pos) /* (USB_HOST_INTFLAG) Device Connection Mask */ 931 #define USB_HOST_INTFLAG_DCONN(value) (USB_HOST_INTFLAG_DCONN_Msk & (_UINT16_(value) << USB_HOST_INTFLAG_DCONN_Pos)) /* Assigment of value for DCONN in the USB_HOST_INTFLAG register */ 932 #define USB_HOST_INTFLAG_DDISC_Pos _UINT16_(9) /* (USB_HOST_INTFLAG) Device Disconnection Position */ 933 #define USB_HOST_INTFLAG_DDISC_Msk (_UINT16_(0x1) << USB_HOST_INTFLAG_DDISC_Pos) /* (USB_HOST_INTFLAG) Device Disconnection Mask */ 934 #define USB_HOST_INTFLAG_DDISC(value) (USB_HOST_INTFLAG_DDISC_Msk & (_UINT16_(value) << USB_HOST_INTFLAG_DDISC_Pos)) /* Assigment of value for DDISC in the USB_HOST_INTFLAG register */ 935 #define USB_HOST_INTFLAG_Msk _UINT16_(0x03FC) /* (USB_HOST_INTFLAG) Register Mask */ 936 937 938 /* -------- USB_DEVICE_EPINTSMRY : (USB Offset: 0x20) ( R/ 16) DEVICE End Point Interrupt Summary -------- */ 939 #define USB_DEVICE_EPINTSMRY_RESETVALUE _UINT16_(0x00) /* (USB_DEVICE_EPINTSMRY) DEVICE End Point Interrupt Summary Reset Value */ 940 941 #define USB_DEVICE_EPINTSMRY_EPINT0_Pos _UINT16_(0) /* (USB_DEVICE_EPINTSMRY) End Point 0 Interrupt Position */ 942 #define USB_DEVICE_EPINTSMRY_EPINT0_Msk (_UINT16_(0x1) << USB_DEVICE_EPINTSMRY_EPINT0_Pos) /* (USB_DEVICE_EPINTSMRY) End Point 0 Interrupt Mask */ 943 #define USB_DEVICE_EPINTSMRY_EPINT0(value) (USB_DEVICE_EPINTSMRY_EPINT0_Msk & (_UINT16_(value) << USB_DEVICE_EPINTSMRY_EPINT0_Pos)) /* Assigment of value for EPINT0 in the USB_DEVICE_EPINTSMRY register */ 944 #define USB_DEVICE_EPINTSMRY_EPINT1_Pos _UINT16_(1) /* (USB_DEVICE_EPINTSMRY) End Point 1 Interrupt Position */ 945 #define USB_DEVICE_EPINTSMRY_EPINT1_Msk (_UINT16_(0x1) << USB_DEVICE_EPINTSMRY_EPINT1_Pos) /* (USB_DEVICE_EPINTSMRY) End Point 1 Interrupt Mask */ 946 #define USB_DEVICE_EPINTSMRY_EPINT1(value) (USB_DEVICE_EPINTSMRY_EPINT1_Msk & (_UINT16_(value) << USB_DEVICE_EPINTSMRY_EPINT1_Pos)) /* Assigment of value for EPINT1 in the USB_DEVICE_EPINTSMRY register */ 947 #define USB_DEVICE_EPINTSMRY_EPINT2_Pos _UINT16_(2) /* (USB_DEVICE_EPINTSMRY) End Point 2 Interrupt Position */ 948 #define USB_DEVICE_EPINTSMRY_EPINT2_Msk (_UINT16_(0x1) << USB_DEVICE_EPINTSMRY_EPINT2_Pos) /* (USB_DEVICE_EPINTSMRY) End Point 2 Interrupt Mask */ 949 #define USB_DEVICE_EPINTSMRY_EPINT2(value) (USB_DEVICE_EPINTSMRY_EPINT2_Msk & (_UINT16_(value) << USB_DEVICE_EPINTSMRY_EPINT2_Pos)) /* Assigment of value for EPINT2 in the USB_DEVICE_EPINTSMRY register */ 950 #define USB_DEVICE_EPINTSMRY_EPINT3_Pos _UINT16_(3) /* (USB_DEVICE_EPINTSMRY) End Point 3 Interrupt Position */ 951 #define USB_DEVICE_EPINTSMRY_EPINT3_Msk (_UINT16_(0x1) << USB_DEVICE_EPINTSMRY_EPINT3_Pos) /* (USB_DEVICE_EPINTSMRY) End Point 3 Interrupt Mask */ 952 #define USB_DEVICE_EPINTSMRY_EPINT3(value) (USB_DEVICE_EPINTSMRY_EPINT3_Msk & (_UINT16_(value) << USB_DEVICE_EPINTSMRY_EPINT3_Pos)) /* Assigment of value for EPINT3 in the USB_DEVICE_EPINTSMRY register */ 953 #define USB_DEVICE_EPINTSMRY_EPINT4_Pos _UINT16_(4) /* (USB_DEVICE_EPINTSMRY) End Point 4 Interrupt Position */ 954 #define USB_DEVICE_EPINTSMRY_EPINT4_Msk (_UINT16_(0x1) << USB_DEVICE_EPINTSMRY_EPINT4_Pos) /* (USB_DEVICE_EPINTSMRY) End Point 4 Interrupt Mask */ 955 #define USB_DEVICE_EPINTSMRY_EPINT4(value) (USB_DEVICE_EPINTSMRY_EPINT4_Msk & (_UINT16_(value) << USB_DEVICE_EPINTSMRY_EPINT4_Pos)) /* Assigment of value for EPINT4 in the USB_DEVICE_EPINTSMRY register */ 956 #define USB_DEVICE_EPINTSMRY_EPINT5_Pos _UINT16_(5) /* (USB_DEVICE_EPINTSMRY) End Point 5 Interrupt Position */ 957 #define USB_DEVICE_EPINTSMRY_EPINT5_Msk (_UINT16_(0x1) << USB_DEVICE_EPINTSMRY_EPINT5_Pos) /* (USB_DEVICE_EPINTSMRY) End Point 5 Interrupt Mask */ 958 #define USB_DEVICE_EPINTSMRY_EPINT5(value) (USB_DEVICE_EPINTSMRY_EPINT5_Msk & (_UINT16_(value) << USB_DEVICE_EPINTSMRY_EPINT5_Pos)) /* Assigment of value for EPINT5 in the USB_DEVICE_EPINTSMRY register */ 959 #define USB_DEVICE_EPINTSMRY_EPINT6_Pos _UINT16_(6) /* (USB_DEVICE_EPINTSMRY) End Point 6 Interrupt Position */ 960 #define USB_DEVICE_EPINTSMRY_EPINT6_Msk (_UINT16_(0x1) << USB_DEVICE_EPINTSMRY_EPINT6_Pos) /* (USB_DEVICE_EPINTSMRY) End Point 6 Interrupt Mask */ 961 #define USB_DEVICE_EPINTSMRY_EPINT6(value) (USB_DEVICE_EPINTSMRY_EPINT6_Msk & (_UINT16_(value) << USB_DEVICE_EPINTSMRY_EPINT6_Pos)) /* Assigment of value for EPINT6 in the USB_DEVICE_EPINTSMRY register */ 962 #define USB_DEVICE_EPINTSMRY_EPINT7_Pos _UINT16_(7) /* (USB_DEVICE_EPINTSMRY) End Point 7 Interrupt Position */ 963 #define USB_DEVICE_EPINTSMRY_EPINT7_Msk (_UINT16_(0x1) << USB_DEVICE_EPINTSMRY_EPINT7_Pos) /* (USB_DEVICE_EPINTSMRY) End Point 7 Interrupt Mask */ 964 #define USB_DEVICE_EPINTSMRY_EPINT7(value) (USB_DEVICE_EPINTSMRY_EPINT7_Msk & (_UINT16_(value) << USB_DEVICE_EPINTSMRY_EPINT7_Pos)) /* Assigment of value for EPINT7 in the USB_DEVICE_EPINTSMRY register */ 965 #define USB_DEVICE_EPINTSMRY_Msk _UINT16_(0x00FF) /* (USB_DEVICE_EPINTSMRY) Register Mask */ 966 967 #define USB_DEVICE_EPINTSMRY_EPINT_Pos _UINT16_(0) /* (USB_DEVICE_EPINTSMRY Position) End Point 7 Interrupt */ 968 #define USB_DEVICE_EPINTSMRY_EPINT_Msk (_UINT16_(0xFF) << USB_DEVICE_EPINTSMRY_EPINT_Pos) /* (USB_DEVICE_EPINTSMRY Mask) EPINT */ 969 #define USB_DEVICE_EPINTSMRY_EPINT(value) (USB_DEVICE_EPINTSMRY_EPINT_Msk & (_UINT16_(value) << USB_DEVICE_EPINTSMRY_EPINT_Pos)) 970 971 /* -------- USB_HOST_PINTSMRY : (USB Offset: 0x20) ( R/ 16) HOST Pipe Interrupt Summary -------- */ 972 #define USB_HOST_PINTSMRY_RESETVALUE _UINT16_(0x00) /* (USB_HOST_PINTSMRY) HOST Pipe Interrupt Summary Reset Value */ 973 974 #define USB_HOST_PINTSMRY_EPINT0_Pos _UINT16_(0) /* (USB_HOST_PINTSMRY) Pipe 0 Interrupt Position */ 975 #define USB_HOST_PINTSMRY_EPINT0_Msk (_UINT16_(0x1) << USB_HOST_PINTSMRY_EPINT0_Pos) /* (USB_HOST_PINTSMRY) Pipe 0 Interrupt Mask */ 976 #define USB_HOST_PINTSMRY_EPINT0(value) (USB_HOST_PINTSMRY_EPINT0_Msk & (_UINT16_(value) << USB_HOST_PINTSMRY_EPINT0_Pos)) /* Assigment of value for EPINT0 in the USB_HOST_PINTSMRY register */ 977 #define USB_HOST_PINTSMRY_EPINT1_Pos _UINT16_(1) /* (USB_HOST_PINTSMRY) Pipe 1 Interrupt Position */ 978 #define USB_HOST_PINTSMRY_EPINT1_Msk (_UINT16_(0x1) << USB_HOST_PINTSMRY_EPINT1_Pos) /* (USB_HOST_PINTSMRY) Pipe 1 Interrupt Mask */ 979 #define USB_HOST_PINTSMRY_EPINT1(value) (USB_HOST_PINTSMRY_EPINT1_Msk & (_UINT16_(value) << USB_HOST_PINTSMRY_EPINT1_Pos)) /* Assigment of value for EPINT1 in the USB_HOST_PINTSMRY register */ 980 #define USB_HOST_PINTSMRY_EPINT2_Pos _UINT16_(2) /* (USB_HOST_PINTSMRY) Pipe 2 Interrupt Position */ 981 #define USB_HOST_PINTSMRY_EPINT2_Msk (_UINT16_(0x1) << USB_HOST_PINTSMRY_EPINT2_Pos) /* (USB_HOST_PINTSMRY) Pipe 2 Interrupt Mask */ 982 #define USB_HOST_PINTSMRY_EPINT2(value) (USB_HOST_PINTSMRY_EPINT2_Msk & (_UINT16_(value) << USB_HOST_PINTSMRY_EPINT2_Pos)) /* Assigment of value for EPINT2 in the USB_HOST_PINTSMRY register */ 983 #define USB_HOST_PINTSMRY_EPINT3_Pos _UINT16_(3) /* (USB_HOST_PINTSMRY) Pipe 3 Interrupt Position */ 984 #define USB_HOST_PINTSMRY_EPINT3_Msk (_UINT16_(0x1) << USB_HOST_PINTSMRY_EPINT3_Pos) /* (USB_HOST_PINTSMRY) Pipe 3 Interrupt Mask */ 985 #define USB_HOST_PINTSMRY_EPINT3(value) (USB_HOST_PINTSMRY_EPINT3_Msk & (_UINT16_(value) << USB_HOST_PINTSMRY_EPINT3_Pos)) /* Assigment of value for EPINT3 in the USB_HOST_PINTSMRY register */ 986 #define USB_HOST_PINTSMRY_EPINT4_Pos _UINT16_(4) /* (USB_HOST_PINTSMRY) Pipe 4 Interrupt Position */ 987 #define USB_HOST_PINTSMRY_EPINT4_Msk (_UINT16_(0x1) << USB_HOST_PINTSMRY_EPINT4_Pos) /* (USB_HOST_PINTSMRY) Pipe 4 Interrupt Mask */ 988 #define USB_HOST_PINTSMRY_EPINT4(value) (USB_HOST_PINTSMRY_EPINT4_Msk & (_UINT16_(value) << USB_HOST_PINTSMRY_EPINT4_Pos)) /* Assigment of value for EPINT4 in the USB_HOST_PINTSMRY register */ 989 #define USB_HOST_PINTSMRY_EPINT5_Pos _UINT16_(5) /* (USB_HOST_PINTSMRY) Pipe 5 Interrupt Position */ 990 #define USB_HOST_PINTSMRY_EPINT5_Msk (_UINT16_(0x1) << USB_HOST_PINTSMRY_EPINT5_Pos) /* (USB_HOST_PINTSMRY) Pipe 5 Interrupt Mask */ 991 #define USB_HOST_PINTSMRY_EPINT5(value) (USB_HOST_PINTSMRY_EPINT5_Msk & (_UINT16_(value) << USB_HOST_PINTSMRY_EPINT5_Pos)) /* Assigment of value for EPINT5 in the USB_HOST_PINTSMRY register */ 992 #define USB_HOST_PINTSMRY_EPINT6_Pos _UINT16_(6) /* (USB_HOST_PINTSMRY) Pipe 6 Interrupt Position */ 993 #define USB_HOST_PINTSMRY_EPINT6_Msk (_UINT16_(0x1) << USB_HOST_PINTSMRY_EPINT6_Pos) /* (USB_HOST_PINTSMRY) Pipe 6 Interrupt Mask */ 994 #define USB_HOST_PINTSMRY_EPINT6(value) (USB_HOST_PINTSMRY_EPINT6_Msk & (_UINT16_(value) << USB_HOST_PINTSMRY_EPINT6_Pos)) /* Assigment of value for EPINT6 in the USB_HOST_PINTSMRY register */ 995 #define USB_HOST_PINTSMRY_EPINT7_Pos _UINT16_(7) /* (USB_HOST_PINTSMRY) Pipe 7 Interrupt Position */ 996 #define USB_HOST_PINTSMRY_EPINT7_Msk (_UINT16_(0x1) << USB_HOST_PINTSMRY_EPINT7_Pos) /* (USB_HOST_PINTSMRY) Pipe 7 Interrupt Mask */ 997 #define USB_HOST_PINTSMRY_EPINT7(value) (USB_HOST_PINTSMRY_EPINT7_Msk & (_UINT16_(value) << USB_HOST_PINTSMRY_EPINT7_Pos)) /* Assigment of value for EPINT7 in the USB_HOST_PINTSMRY register */ 998 #define USB_HOST_PINTSMRY_Msk _UINT16_(0x00FF) /* (USB_HOST_PINTSMRY) Register Mask */ 999 1000 #define USB_HOST_PINTSMRY_EPINT_Pos _UINT16_(0) /* (USB_HOST_PINTSMRY Position) Pipe 7 Interrupt */ 1001 #define USB_HOST_PINTSMRY_EPINT_Msk (_UINT16_(0xFF) << USB_HOST_PINTSMRY_EPINT_Pos) /* (USB_HOST_PINTSMRY Mask) EPINT */ 1002 #define USB_HOST_PINTSMRY_EPINT(value) (USB_HOST_PINTSMRY_EPINT_Msk & (_UINT16_(value) << USB_HOST_PINTSMRY_EPINT_Pos)) 1003 1004 /* -------- USB_DESCADD : (USB Offset: 0x24) (R/W 32) Descriptor Address -------- */ 1005 #define USB_DESCADD_RESETVALUE _UINT32_(0x00) /* (USB_DESCADD) Descriptor Address Reset Value */ 1006 1007 #define USB_DESCADD_DESCADD_Pos _UINT32_(0) /* (USB_DESCADD) Descriptor Address Value Position */ 1008 #define USB_DESCADD_DESCADD_Msk (_UINT32_(0xFFFFFFFF) << USB_DESCADD_DESCADD_Pos) /* (USB_DESCADD) Descriptor Address Value Mask */ 1009 #define USB_DESCADD_DESCADD(value) (USB_DESCADD_DESCADD_Msk & (_UINT32_(value) << USB_DESCADD_DESCADD_Pos)) /* Assigment of value for DESCADD in the USB_DESCADD register */ 1010 #define USB_DESCADD_Msk _UINT32_(0xFFFFFFFF) /* (USB_DESCADD) Register Mask */ 1011 1012 1013 /* -------- USB_PADCAL : (USB Offset: 0x28) (R/W 16) USB PAD Calibration -------- */ 1014 #define USB_PADCAL_RESETVALUE _UINT16_(0x00) /* (USB_PADCAL) USB PAD Calibration Reset Value */ 1015 1016 #define USB_PADCAL_TRANSP_Pos _UINT16_(0) /* (USB_PADCAL) USB Pad Transp calibration Position */ 1017 #define USB_PADCAL_TRANSP_Msk (_UINT16_(0x1F) << USB_PADCAL_TRANSP_Pos) /* (USB_PADCAL) USB Pad Transp calibration Mask */ 1018 #define USB_PADCAL_TRANSP(value) (USB_PADCAL_TRANSP_Msk & (_UINT16_(value) << USB_PADCAL_TRANSP_Pos)) /* Assigment of value for TRANSP in the USB_PADCAL register */ 1019 #define USB_PADCAL_TRANSN_Pos _UINT16_(6) /* (USB_PADCAL) USB Pad Transn calibration Position */ 1020 #define USB_PADCAL_TRANSN_Msk (_UINT16_(0x1F) << USB_PADCAL_TRANSN_Pos) /* (USB_PADCAL) USB Pad Transn calibration Mask */ 1021 #define USB_PADCAL_TRANSN(value) (USB_PADCAL_TRANSN_Msk & (_UINT16_(value) << USB_PADCAL_TRANSN_Pos)) /* Assigment of value for TRANSN in the USB_PADCAL register */ 1022 #define USB_PADCAL_TRIM_Pos _UINT16_(12) /* (USB_PADCAL) USB Pad Trim calibration Position */ 1023 #define USB_PADCAL_TRIM_Msk (_UINT16_(0x7) << USB_PADCAL_TRIM_Pos) /* (USB_PADCAL) USB Pad Trim calibration Mask */ 1024 #define USB_PADCAL_TRIM(value) (USB_PADCAL_TRIM_Msk & (_UINT16_(value) << USB_PADCAL_TRIM_Pos)) /* Assigment of value for TRIM in the USB_PADCAL register */ 1025 #define USB_PADCAL_Msk _UINT16_(0x77DF) /* (USB_PADCAL) Register Mask */ 1026 1027 1028 /** \brief USB register offsets definitions */ 1029 #define USB_DEVICE_ADDR_REG_OFST _UINT32_(0x00) /* (USB_DEVICE_ADDR) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer Offset */ 1030 #define USB_DEVICE_PCKSIZE_REG_OFST _UINT32_(0x04) /* (USB_DEVICE_PCKSIZE) DEVICE_DESC_BANK Endpoint Bank, Packet Size Offset */ 1031 #define USB_DEVICE_EXTREG_REG_OFST _UINT32_(0x08) /* (USB_DEVICE_EXTREG) DEVICE_DESC_BANK Endpoint Bank, Extended Offset */ 1032 #define USB_DEVICE_STATUS_BK_REG_OFST _UINT32_(0x0A) /* (USB_DEVICE_STATUS_BK) DEVICE_DESC_BANK Enpoint Bank, Status of Bank Offset */ 1033 #define USB_HOST_ADDR_REG_OFST _UINT32_(0x00) /* (USB_HOST_ADDR) HOST_DESC_BANK Host Bank, Adress of Data Buffer Offset */ 1034 #define USB_HOST_PCKSIZE_REG_OFST _UINT32_(0x04) /* (USB_HOST_PCKSIZE) HOST_DESC_BANK Host Bank, Packet Size Offset */ 1035 #define USB_HOST_EXTREG_REG_OFST _UINT32_(0x08) /* (USB_HOST_EXTREG) HOST_DESC_BANK Host Bank, Extended Offset */ 1036 #define USB_HOST_STATUS_BK_REG_OFST _UINT32_(0x0A) /* (USB_HOST_STATUS_BK) HOST_DESC_BANK Host Bank, Status of Bank Offset */ 1037 #define USB_HOST_CTRL_PIPE_REG_OFST _UINT32_(0x0C) /* (USB_HOST_CTRL_PIPE) HOST_DESC_BANK Host Bank, Host Control Pipe Offset */ 1038 #define USB_HOST_STATUS_PIPE_REG_OFST _UINT32_(0x0E) /* (USB_HOST_STATUS_PIPE) HOST_DESC_BANK Host Bank, Host Status Pipe Offset */ 1039 #define USB_DEVICE_EPCFG_REG_OFST _UINT32_(0x00) /* (USB_DEVICE_EPCFG) DEVICE_ENDPOINT End Point Configuration Offset */ 1040 #define USB_DEVICE_EPSTATUSCLR_REG_OFST _UINT32_(0x04) /* (USB_DEVICE_EPSTATUSCLR) DEVICE_ENDPOINT End Point Pipe Status Clear Offset */ 1041 #define USB_DEVICE_EPSTATUSSET_REG_OFST _UINT32_(0x05) /* (USB_DEVICE_EPSTATUSSET) DEVICE_ENDPOINT End Point Pipe Status Set Offset */ 1042 #define USB_DEVICE_EPSTATUS_REG_OFST _UINT32_(0x06) /* (USB_DEVICE_EPSTATUS) DEVICE_ENDPOINT End Point Pipe Status Offset */ 1043 #define USB_DEVICE_EPINTFLAG_REG_OFST _UINT32_(0x07) /* (USB_DEVICE_EPINTFLAG) DEVICE_ENDPOINT End Point Interrupt Flag Offset */ 1044 #define USB_DEVICE_EPINTENCLR_REG_OFST _UINT32_(0x08) /* (USB_DEVICE_EPINTENCLR) DEVICE_ENDPOINT End Point Interrupt Clear Flag Offset */ 1045 #define USB_DEVICE_EPINTENSET_REG_OFST _UINT32_(0x09) /* (USB_DEVICE_EPINTENSET) DEVICE_ENDPOINT End Point Interrupt Set Flag Offset */ 1046 #define USB_HOST_PCFG_REG_OFST _UINT32_(0x00) /* (USB_HOST_PCFG) HOST_PIPE End Point Configuration Offset */ 1047 #define USB_HOST_BINTERVAL_REG_OFST _UINT32_(0x03) /* (USB_HOST_BINTERVAL) HOST_PIPE Bus Access Period of Pipe Offset */ 1048 #define USB_HOST_PSTATUSCLR_REG_OFST _UINT32_(0x04) /* (USB_HOST_PSTATUSCLR) HOST_PIPE End Point Pipe Status Clear Offset */ 1049 #define USB_HOST_PSTATUSSET_REG_OFST _UINT32_(0x05) /* (USB_HOST_PSTATUSSET) HOST_PIPE End Point Pipe Status Set Offset */ 1050 #define USB_HOST_PSTATUS_REG_OFST _UINT32_(0x06) /* (USB_HOST_PSTATUS) HOST_PIPE End Point Pipe Status Offset */ 1051 #define USB_HOST_PINTFLAG_REG_OFST _UINT32_(0x07) /* (USB_HOST_PINTFLAG) HOST_PIPE Pipe Interrupt Flag Offset */ 1052 #define USB_HOST_PINTENCLR_REG_OFST _UINT32_(0x08) /* (USB_HOST_PINTENCLR) HOST_PIPE Pipe Interrupt Flag Clear Offset */ 1053 #define USB_HOST_PINTENSET_REG_OFST _UINT32_(0x09) /* (USB_HOST_PINTENSET) HOST_PIPE Pipe Interrupt Flag Set Offset */ 1054 #define USB_CTRLA_REG_OFST _UINT32_(0x00) /* (USB_CTRLA) Control A Offset */ 1055 #define USB_SYNCBUSY_REG_OFST _UINT32_(0x02) /* (USB_SYNCBUSY) Synchronization Busy Offset */ 1056 #define USB_QOSCTRL_REG_OFST _UINT32_(0x03) /* (USB_QOSCTRL) USB Quality Of Service Offset */ 1057 #define USB_DEVICE_CTRLB_REG_OFST _UINT32_(0x08) /* (USB_DEVICE_CTRLB) DEVICE Control B Offset */ 1058 #define USB_HOST_CTRLB_REG_OFST _UINT32_(0x08) /* (USB_HOST_CTRLB) HOST Control B Offset */ 1059 #define USB_DEVICE_DADD_REG_OFST _UINT32_(0x0A) /* (USB_DEVICE_DADD) DEVICE Device Address Offset */ 1060 #define USB_HOST_HSOFC_REG_OFST _UINT32_(0x0A) /* (USB_HOST_HSOFC) HOST Host Start Of Frame Control Offset */ 1061 #define USB_DEVICE_STATUS_REG_OFST _UINT32_(0x0C) /* (USB_DEVICE_STATUS) DEVICE Status Offset */ 1062 #define USB_HOST_STATUS_REG_OFST _UINT32_(0x0C) /* (USB_HOST_STATUS) HOST Status Offset */ 1063 #define USB_FSMSTATUS_REG_OFST _UINT32_(0x0D) /* (USB_FSMSTATUS) Finite State Machine Status Offset */ 1064 #define USB_DEVICE_FNUM_REG_OFST _UINT32_(0x10) /* (USB_DEVICE_FNUM) DEVICE Device Frame Number Offset */ 1065 #define USB_HOST_FNUM_REG_OFST _UINT32_(0x10) /* (USB_HOST_FNUM) HOST Host Frame Number Offset */ 1066 #define USB_HOST_FLENHIGH_REG_OFST _UINT32_(0x12) /* (USB_HOST_FLENHIGH) HOST Host Frame Length Offset */ 1067 #define USB_DEVICE_INTENCLR_REG_OFST _UINT32_(0x14) /* (USB_DEVICE_INTENCLR) DEVICE Device Interrupt Enable Clear Offset */ 1068 #define USB_HOST_INTENCLR_REG_OFST _UINT32_(0x14) /* (USB_HOST_INTENCLR) HOST Host Interrupt Enable Clear Offset */ 1069 #define USB_DEVICE_INTENSET_REG_OFST _UINT32_(0x18) /* (USB_DEVICE_INTENSET) DEVICE Device Interrupt Enable Set Offset */ 1070 #define USB_HOST_INTENSET_REG_OFST _UINT32_(0x18) /* (USB_HOST_INTENSET) HOST Host Interrupt Enable Set Offset */ 1071 #define USB_DEVICE_INTFLAG_REG_OFST _UINT32_(0x1C) /* (USB_DEVICE_INTFLAG) DEVICE Device Interrupt Flag Offset */ 1072 #define USB_HOST_INTFLAG_REG_OFST _UINT32_(0x1C) /* (USB_HOST_INTFLAG) HOST Host Interrupt Flag Offset */ 1073 #define USB_DEVICE_EPINTSMRY_REG_OFST _UINT32_(0x20) /* (USB_DEVICE_EPINTSMRY) DEVICE End Point Interrupt Summary Offset */ 1074 #define USB_HOST_PINTSMRY_REG_OFST _UINT32_(0x20) /* (USB_HOST_PINTSMRY) HOST Pipe Interrupt Summary Offset */ 1075 #define USB_DESCADD_REG_OFST _UINT32_(0x24) /* (USB_DESCADD) Descriptor Address Offset */ 1076 #define USB_PADCAL_REG_OFST _UINT32_(0x28) /* (USB_PADCAL) USB PAD Calibration Offset */ 1077 1078 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1079 /** \brief DEVICE_DESC_BANK register API structure */ 1080 typedef struct 1081 { 1082 __IO uint32_t USB_ADDR; /**< Offset: 0x00 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */ 1083 __IO uint32_t USB_PCKSIZE; /**< Offset: 0x04 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Packet Size */ 1084 __IO uint16_t USB_EXTREG; /**< Offset: 0x08 (R/W 16) DEVICE_DESC_BANK Endpoint Bank, Extended */ 1085 __IO uint8_t USB_STATUS_BK; /**< Offset: 0x0A (R/W 8) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */ 1086 __I uint8_t Reserved1[0x05]; 1087 } usb_device_desc_bank_registers_t; 1088 1089 /** \brief HOST_DESC_BANK register API structure */ 1090 typedef struct 1091 { 1092 __IO uint32_t USB_ADDR; /**< Offset: 0x00 (R/W 32) HOST_DESC_BANK Host Bank, Adress of Data Buffer */ 1093 __IO uint32_t USB_PCKSIZE; /**< Offset: 0x04 (R/W 32) HOST_DESC_BANK Host Bank, Packet Size */ 1094 __IO uint16_t USB_EXTREG; /**< Offset: 0x08 (R/W 16) HOST_DESC_BANK Host Bank, Extended */ 1095 __IO uint8_t USB_STATUS_BK; /**< Offset: 0x0A (R/W 8) HOST_DESC_BANK Host Bank, Status of Bank */ 1096 __I uint8_t Reserved1[0x01]; 1097 __IO uint16_t USB_CTRL_PIPE; /**< Offset: 0x0C (R/W 16) HOST_DESC_BANK Host Bank, Host Control Pipe */ 1098 __IO uint16_t USB_STATUS_PIPE; /**< Offset: 0x0E (R/W 16) HOST_DESC_BANK Host Bank, Host Status Pipe */ 1099 } usb_host_desc_bank_registers_t; 1100 1101 /** \brief DEVICE_ENDPOINT register API structure */ 1102 typedef struct 1103 { 1104 __IO uint8_t USB_EPCFG; /**< Offset: 0x00 (R/W 8) DEVICE_ENDPOINT End Point Configuration */ 1105 __I uint8_t Reserved1[0x03]; 1106 __O uint8_t USB_EPSTATUSCLR; /**< Offset: 0x04 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Clear */ 1107 __O uint8_t USB_EPSTATUSSET; /**< Offset: 0x05 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Set */ 1108 __I uint8_t USB_EPSTATUS; /**< Offset: 0x06 (R/ 8) DEVICE_ENDPOINT End Point Pipe Status */ 1109 __IO uint8_t USB_EPINTFLAG; /**< Offset: 0x07 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Flag */ 1110 __IO uint8_t USB_EPINTENCLR; /**< Offset: 0x08 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Clear Flag */ 1111 __IO uint8_t USB_EPINTENSET; /**< Offset: 0x09 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Set Flag */ 1112 __I uint8_t Reserved2[0x16]; 1113 } usb_device_endpoint_registers_t; 1114 1115 /** \brief HOST_PIPE register API structure */ 1116 typedef struct 1117 { 1118 __IO uint8_t USB_PCFG; /**< Offset: 0x00 (R/W 8) HOST_PIPE End Point Configuration */ 1119 __I uint8_t Reserved1[0x02]; 1120 __IO uint8_t USB_BINTERVAL; /**< Offset: 0x03 (R/W 8) HOST_PIPE Bus Access Period of Pipe */ 1121 __O uint8_t USB_PSTATUSCLR; /**< Offset: 0x04 ( /W 8) HOST_PIPE End Point Pipe Status Clear */ 1122 __O uint8_t USB_PSTATUSSET; /**< Offset: 0x05 ( /W 8) HOST_PIPE End Point Pipe Status Set */ 1123 __I uint8_t USB_PSTATUS; /**< Offset: 0x06 (R/ 8) HOST_PIPE End Point Pipe Status */ 1124 __IO uint8_t USB_PINTFLAG; /**< Offset: 0x07 (R/W 8) HOST_PIPE Pipe Interrupt Flag */ 1125 __IO uint8_t USB_PINTENCLR; /**< Offset: 0x08 (R/W 8) HOST_PIPE Pipe Interrupt Flag Clear */ 1126 __IO uint8_t USB_PINTENSET; /**< Offset: 0x09 (R/W 8) HOST_PIPE Pipe Interrupt Flag Set */ 1127 __I uint8_t Reserved2[0x16]; 1128 } usb_host_pipe_registers_t; 1129 1130 #define USB_DEVICE_DESC_BANK_NUMBER 2 1131 1132 /** \brief USB_DESCRIPTOR register API structure */ 1133 typedef struct 1134 { /* Universal Serial Bus */ 1135 usb_device_desc_bank_registers_t DEVICE_DESC_BANK[USB_DEVICE_DESC_BANK_NUMBER]; /**< Offset: 0x00 */ 1136 } usb_descriptor_device_registers_t; 1137 1138 #define USB_HOST_DESC_BANK_NUMBER 2 1139 1140 /** \brief USB_DESCRIPTOR register API structure */ 1141 typedef struct 1142 { /* Universal Serial Bus */ 1143 usb_host_desc_bank_registers_t HOST_DESC_BANK[USB_HOST_DESC_BANK_NUMBER]; /**< Offset: 0x00 */ 1144 } usb_descriptor_host_registers_t; 1145 1146 /** \brief USB_DESCRIPTOR hardware registers */ 1147 typedef union 1148 { /* Universal Serial Bus */ 1149 usb_descriptor_device_registers_t DEVICE; /**< USB is Device */ 1150 usb_descriptor_host_registers_t HOST; /**< USB is Host */ 1151 } usb_descriptor_registers_t; 1152 1153 #define USB_DEVICE_ENDPOINT_NUMBER 8 1154 1155 /** \brief USB register API structure */ 1156 typedef struct 1157 { /* Universal Serial Bus */ 1158 __IO uint8_t USB_CTRLA; /**< Offset: 0x00 (R/W 8) Control A */ 1159 __I uint8_t Reserved1[0x01]; 1160 __I uint8_t USB_SYNCBUSY; /**< Offset: 0x02 (R/ 8) Synchronization Busy */ 1161 __IO uint8_t USB_QOSCTRL; /**< Offset: 0x03 (R/W 8) USB Quality Of Service */ 1162 __I uint8_t Reserved2[0x04]; 1163 __IO uint16_t USB_CTRLB; /**< Offset: 0x08 (R/W 16) DEVICE Control B */ 1164 __IO uint8_t USB_DADD; /**< Offset: 0x0A (R/W 8) DEVICE Device Address */ 1165 __I uint8_t Reserved3[0x01]; 1166 __I uint8_t USB_STATUS; /**< Offset: 0x0C (R/ 8) DEVICE Status */ 1167 __I uint8_t USB_FSMSTATUS; /**< Offset: 0x0D (R/ 8) Finite State Machine Status */ 1168 __I uint8_t Reserved4[0x02]; 1169 __I uint16_t USB_FNUM; /**< Offset: 0x10 (R/ 16) DEVICE Device Frame Number */ 1170 __I uint8_t Reserved5[0x02]; 1171 __IO uint16_t USB_INTENCLR; /**< Offset: 0x14 (R/W 16) DEVICE Device Interrupt Enable Clear */ 1172 __I uint8_t Reserved6[0x02]; 1173 __IO uint16_t USB_INTENSET; /**< Offset: 0x18 (R/W 16) DEVICE Device Interrupt Enable Set */ 1174 __I uint8_t Reserved7[0x02]; 1175 __IO uint16_t USB_INTFLAG; /**< Offset: 0x1C (R/W 16) DEVICE Device Interrupt Flag */ 1176 __I uint8_t Reserved8[0x02]; 1177 __I uint16_t USB_EPINTSMRY; /**< Offset: 0x20 (R/ 16) DEVICE End Point Interrupt Summary */ 1178 __I uint8_t Reserved9[0x02]; 1179 __IO uint32_t USB_DESCADD; /**< Offset: 0x24 (R/W 32) Descriptor Address */ 1180 __IO uint16_t USB_PADCAL; /**< Offset: 0x28 (R/W 16) USB PAD Calibration */ 1181 __I uint8_t Reserved10[0xD6]; 1182 usb_device_endpoint_registers_t DEVICE_ENDPOINT[USB_DEVICE_ENDPOINT_NUMBER]; /**< Offset: 0x100 */ 1183 } usb_device_registers_t; 1184 1185 #define USB_HOST_PIPE_NUMBER 8 1186 1187 /** \brief USB register API structure */ 1188 typedef struct 1189 { /* Universal Serial Bus */ 1190 __IO uint8_t USB_CTRLA; /**< Offset: 0x00 (R/W 8) Control A */ 1191 __I uint8_t Reserved1[0x01]; 1192 __I uint8_t USB_SYNCBUSY; /**< Offset: 0x02 (R/ 8) Synchronization Busy */ 1193 __IO uint8_t USB_QOSCTRL; /**< Offset: 0x03 (R/W 8) USB Quality Of Service */ 1194 __I uint8_t Reserved2[0x04]; 1195 __IO uint16_t USB_CTRLB; /**< Offset: 0x08 (R/W 16) HOST Control B */ 1196 __IO uint8_t USB_HSOFC; /**< Offset: 0x0A (R/W 8) HOST Host Start Of Frame Control */ 1197 __I uint8_t Reserved3[0x01]; 1198 __IO uint8_t USB_STATUS; /**< Offset: 0x0C (R/W 8) HOST Status */ 1199 __I uint8_t USB_FSMSTATUS; /**< Offset: 0x0D (R/ 8) Finite State Machine Status */ 1200 __I uint8_t Reserved4[0x02]; 1201 __IO uint16_t USB_FNUM; /**< Offset: 0x10 (R/W 16) HOST Host Frame Number */ 1202 __I uint8_t USB_FLENHIGH; /**< Offset: 0x12 (R/ 8) HOST Host Frame Length */ 1203 __I uint8_t Reserved5[0x01]; 1204 __IO uint16_t USB_INTENCLR; /**< Offset: 0x14 (R/W 16) HOST Host Interrupt Enable Clear */ 1205 __I uint8_t Reserved6[0x02]; 1206 __IO uint16_t USB_INTENSET; /**< Offset: 0x18 (R/W 16) HOST Host Interrupt Enable Set */ 1207 __I uint8_t Reserved7[0x02]; 1208 __IO uint16_t USB_INTFLAG; /**< Offset: 0x1C (R/W 16) HOST Host Interrupt Flag */ 1209 __I uint8_t Reserved8[0x02]; 1210 __I uint16_t USB_PINTSMRY; /**< Offset: 0x20 (R/ 16) HOST Pipe Interrupt Summary */ 1211 __I uint8_t Reserved9[0x02]; 1212 __IO uint32_t USB_DESCADD; /**< Offset: 0x24 (R/W 32) Descriptor Address */ 1213 __IO uint16_t USB_PADCAL; /**< Offset: 0x28 (R/W 16) USB PAD Calibration */ 1214 __I uint8_t Reserved10[0xD6]; 1215 usb_host_pipe_registers_t HOST_PIPE[USB_HOST_PIPE_NUMBER]; /**< Offset: 0x100 */ 1216 } usb_host_registers_t; 1217 1218 /** \brief USB hardware registers */ 1219 typedef union 1220 { /* Universal Serial Bus */ 1221 usb_device_registers_t DEVICE; /**< USB is Device */ 1222 usb_host_registers_t HOST; /**< USB is Host */ 1223 } usb_registers_t; 1224 1225 1226 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1227 /** \brief USB_DESCRIPTOR memory section attribute */ 1228 #define SECTION_USB_DESCRIPTOR 1229 1230 #endif /* _PIC32CXSG60_USB_COMPONENT_H_ */ 1231
