1 /* 2 * Component description for SUPC 3 * 4 * Copyright (c) 2023 Microchip Technology Inc. and its subsidiaries. 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 */ 19 20 /* file generated from device description file (ATDF) version 2023-03-17T09:48:46Z */ 21 #ifndef _PIC32CXSG60_SUPC_COMPONENT_H_ 22 #define _PIC32CXSG60_SUPC_COMPONENT_H_ 23 24 /* ************************************************************************** */ 25 /* SOFTWARE API DEFINITION FOR SUPC */ 26 /* ************************************************************************** */ 27 28 /* -------- SUPC_INTENCLR : (SUPC Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */ 29 #define SUPC_INTENCLR_RESETVALUE _UINT32_(0x00) /* (SUPC_INTENCLR) Interrupt Enable Clear Reset Value */ 30 31 #define SUPC_INTENCLR_BOD33RDY_Pos _UINT32_(0) /* (SUPC_INTENCLR) BOD33 Ready Position */ 32 #define SUPC_INTENCLR_BOD33RDY_Msk (_UINT32_(0x1) << SUPC_INTENCLR_BOD33RDY_Pos) /* (SUPC_INTENCLR) BOD33 Ready Mask */ 33 #define SUPC_INTENCLR_BOD33RDY(value) (SUPC_INTENCLR_BOD33RDY_Msk & (_UINT32_(value) << SUPC_INTENCLR_BOD33RDY_Pos)) /* Assigment of value for BOD33RDY in the SUPC_INTENCLR register */ 34 #define SUPC_INTENCLR_BOD33DET_Pos _UINT32_(1) /* (SUPC_INTENCLR) BOD33 Detection Position */ 35 #define SUPC_INTENCLR_BOD33DET_Msk (_UINT32_(0x1) << SUPC_INTENCLR_BOD33DET_Pos) /* (SUPC_INTENCLR) BOD33 Detection Mask */ 36 #define SUPC_INTENCLR_BOD33DET(value) (SUPC_INTENCLR_BOD33DET_Msk & (_UINT32_(value) << SUPC_INTENCLR_BOD33DET_Pos)) /* Assigment of value for BOD33DET in the SUPC_INTENCLR register */ 37 #define SUPC_INTENCLR_B33SRDY_Pos _UINT32_(2) /* (SUPC_INTENCLR) BOD33 Synchronization Ready Position */ 38 #define SUPC_INTENCLR_B33SRDY_Msk (_UINT32_(0x1) << SUPC_INTENCLR_B33SRDY_Pos) /* (SUPC_INTENCLR) BOD33 Synchronization Ready Mask */ 39 #define SUPC_INTENCLR_B33SRDY(value) (SUPC_INTENCLR_B33SRDY_Msk & (_UINT32_(value) << SUPC_INTENCLR_B33SRDY_Pos)) /* Assigment of value for B33SRDY in the SUPC_INTENCLR register */ 40 #define SUPC_INTENCLR_VREGRDY_Pos _UINT32_(8) /* (SUPC_INTENCLR) Voltage Regulator Ready Position */ 41 #define SUPC_INTENCLR_VREGRDY_Msk (_UINT32_(0x1) << SUPC_INTENCLR_VREGRDY_Pos) /* (SUPC_INTENCLR) Voltage Regulator Ready Mask */ 42 #define SUPC_INTENCLR_VREGRDY(value) (SUPC_INTENCLR_VREGRDY_Msk & (_UINT32_(value) << SUPC_INTENCLR_VREGRDY_Pos)) /* Assigment of value for VREGRDY in the SUPC_INTENCLR register */ 43 #define SUPC_INTENCLR_VCORERDY_Pos _UINT32_(10) /* (SUPC_INTENCLR) VDDCORE Ready Position */ 44 #define SUPC_INTENCLR_VCORERDY_Msk (_UINT32_(0x1) << SUPC_INTENCLR_VCORERDY_Pos) /* (SUPC_INTENCLR) VDDCORE Ready Mask */ 45 #define SUPC_INTENCLR_VCORERDY(value) (SUPC_INTENCLR_VCORERDY_Msk & (_UINT32_(value) << SUPC_INTENCLR_VCORERDY_Pos)) /* Assigment of value for VCORERDY in the SUPC_INTENCLR register */ 46 #define SUPC_INTENCLR_Msk _UINT32_(0x00000507) /* (SUPC_INTENCLR) Register Mask */ 47 48 49 /* -------- SUPC_INTENSET : (SUPC Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */ 50 #define SUPC_INTENSET_RESETVALUE _UINT32_(0x00) /* (SUPC_INTENSET) Interrupt Enable Set Reset Value */ 51 52 #define SUPC_INTENSET_BOD33RDY_Pos _UINT32_(0) /* (SUPC_INTENSET) BOD33 Ready Position */ 53 #define SUPC_INTENSET_BOD33RDY_Msk (_UINT32_(0x1) << SUPC_INTENSET_BOD33RDY_Pos) /* (SUPC_INTENSET) BOD33 Ready Mask */ 54 #define SUPC_INTENSET_BOD33RDY(value) (SUPC_INTENSET_BOD33RDY_Msk & (_UINT32_(value) << SUPC_INTENSET_BOD33RDY_Pos)) /* Assigment of value for BOD33RDY in the SUPC_INTENSET register */ 55 #define SUPC_INTENSET_BOD33DET_Pos _UINT32_(1) /* (SUPC_INTENSET) BOD33 Detection Position */ 56 #define SUPC_INTENSET_BOD33DET_Msk (_UINT32_(0x1) << SUPC_INTENSET_BOD33DET_Pos) /* (SUPC_INTENSET) BOD33 Detection Mask */ 57 #define SUPC_INTENSET_BOD33DET(value) (SUPC_INTENSET_BOD33DET_Msk & (_UINT32_(value) << SUPC_INTENSET_BOD33DET_Pos)) /* Assigment of value for BOD33DET in the SUPC_INTENSET register */ 58 #define SUPC_INTENSET_B33SRDY_Pos _UINT32_(2) /* (SUPC_INTENSET) BOD33 Synchronization Ready Position */ 59 #define SUPC_INTENSET_B33SRDY_Msk (_UINT32_(0x1) << SUPC_INTENSET_B33SRDY_Pos) /* (SUPC_INTENSET) BOD33 Synchronization Ready Mask */ 60 #define SUPC_INTENSET_B33SRDY(value) (SUPC_INTENSET_B33SRDY_Msk & (_UINT32_(value) << SUPC_INTENSET_B33SRDY_Pos)) /* Assigment of value for B33SRDY in the SUPC_INTENSET register */ 61 #define SUPC_INTENSET_VREGRDY_Pos _UINT32_(8) /* (SUPC_INTENSET) Voltage Regulator Ready Position */ 62 #define SUPC_INTENSET_VREGRDY_Msk (_UINT32_(0x1) << SUPC_INTENSET_VREGRDY_Pos) /* (SUPC_INTENSET) Voltage Regulator Ready Mask */ 63 #define SUPC_INTENSET_VREGRDY(value) (SUPC_INTENSET_VREGRDY_Msk & (_UINT32_(value) << SUPC_INTENSET_VREGRDY_Pos)) /* Assigment of value for VREGRDY in the SUPC_INTENSET register */ 64 #define SUPC_INTENSET_VCORERDY_Pos _UINT32_(10) /* (SUPC_INTENSET) VDDCORE Ready Position */ 65 #define SUPC_INTENSET_VCORERDY_Msk (_UINT32_(0x1) << SUPC_INTENSET_VCORERDY_Pos) /* (SUPC_INTENSET) VDDCORE Ready Mask */ 66 #define SUPC_INTENSET_VCORERDY(value) (SUPC_INTENSET_VCORERDY_Msk & (_UINT32_(value) << SUPC_INTENSET_VCORERDY_Pos)) /* Assigment of value for VCORERDY in the SUPC_INTENSET register */ 67 #define SUPC_INTENSET_Msk _UINT32_(0x00000507) /* (SUPC_INTENSET) Register Mask */ 68 69 70 /* -------- SUPC_INTFLAG : (SUPC Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */ 71 #define SUPC_INTFLAG_RESETVALUE _UINT32_(0x00) /* (SUPC_INTFLAG) Interrupt Flag Status and Clear Reset Value */ 72 73 #define SUPC_INTFLAG_BOD33RDY_Pos _UINT32_(0) /* (SUPC_INTFLAG) BOD33 Ready Position */ 74 #define SUPC_INTFLAG_BOD33RDY_Msk (_UINT32_(0x1) << SUPC_INTFLAG_BOD33RDY_Pos) /* (SUPC_INTFLAG) BOD33 Ready Mask */ 75 #define SUPC_INTFLAG_BOD33RDY(value) (SUPC_INTFLAG_BOD33RDY_Msk & (_UINT32_(value) << SUPC_INTFLAG_BOD33RDY_Pos)) /* Assigment of value for BOD33RDY in the SUPC_INTFLAG register */ 76 #define SUPC_INTFLAG_BOD33DET_Pos _UINT32_(1) /* (SUPC_INTFLAG) BOD33 Detection Position */ 77 #define SUPC_INTFLAG_BOD33DET_Msk (_UINT32_(0x1) << SUPC_INTFLAG_BOD33DET_Pos) /* (SUPC_INTFLAG) BOD33 Detection Mask */ 78 #define SUPC_INTFLAG_BOD33DET(value) (SUPC_INTFLAG_BOD33DET_Msk & (_UINT32_(value) << SUPC_INTFLAG_BOD33DET_Pos)) /* Assigment of value for BOD33DET in the SUPC_INTFLAG register */ 79 #define SUPC_INTFLAG_B33SRDY_Pos _UINT32_(2) /* (SUPC_INTFLAG) BOD33 Synchronization Ready Position */ 80 #define SUPC_INTFLAG_B33SRDY_Msk (_UINT32_(0x1) << SUPC_INTFLAG_B33SRDY_Pos) /* (SUPC_INTFLAG) BOD33 Synchronization Ready Mask */ 81 #define SUPC_INTFLAG_B33SRDY(value) (SUPC_INTFLAG_B33SRDY_Msk & (_UINT32_(value) << SUPC_INTFLAG_B33SRDY_Pos)) /* Assigment of value for B33SRDY in the SUPC_INTFLAG register */ 82 #define SUPC_INTFLAG_VREGRDY_Pos _UINT32_(8) /* (SUPC_INTFLAG) Voltage Regulator Ready Position */ 83 #define SUPC_INTFLAG_VREGRDY_Msk (_UINT32_(0x1) << SUPC_INTFLAG_VREGRDY_Pos) /* (SUPC_INTFLAG) Voltage Regulator Ready Mask */ 84 #define SUPC_INTFLAG_VREGRDY(value) (SUPC_INTFLAG_VREGRDY_Msk & (_UINT32_(value) << SUPC_INTFLAG_VREGRDY_Pos)) /* Assigment of value for VREGRDY in the SUPC_INTFLAG register */ 85 #define SUPC_INTFLAG_VCORERDY_Pos _UINT32_(10) /* (SUPC_INTFLAG) VDDCORE Ready Position */ 86 #define SUPC_INTFLAG_VCORERDY_Msk (_UINT32_(0x1) << SUPC_INTFLAG_VCORERDY_Pos) /* (SUPC_INTFLAG) VDDCORE Ready Mask */ 87 #define SUPC_INTFLAG_VCORERDY(value) (SUPC_INTFLAG_VCORERDY_Msk & (_UINT32_(value) << SUPC_INTFLAG_VCORERDY_Pos)) /* Assigment of value for VCORERDY in the SUPC_INTFLAG register */ 88 #define SUPC_INTFLAG_Msk _UINT32_(0x00000507) /* (SUPC_INTFLAG) Register Mask */ 89 90 91 /* -------- SUPC_STATUS : (SUPC Offset: 0x0C) ( R/ 32) Power and Clocks Status -------- */ 92 #define SUPC_STATUS_RESETVALUE _UINT32_(0x00) /* (SUPC_STATUS) Power and Clocks Status Reset Value */ 93 94 #define SUPC_STATUS_BOD33RDY_Pos _UINT32_(0) /* (SUPC_STATUS) BOD33 Ready Position */ 95 #define SUPC_STATUS_BOD33RDY_Msk (_UINT32_(0x1) << SUPC_STATUS_BOD33RDY_Pos) /* (SUPC_STATUS) BOD33 Ready Mask */ 96 #define SUPC_STATUS_BOD33RDY(value) (SUPC_STATUS_BOD33RDY_Msk & (_UINT32_(value) << SUPC_STATUS_BOD33RDY_Pos)) /* Assigment of value for BOD33RDY in the SUPC_STATUS register */ 97 #define SUPC_STATUS_BOD33DET_Pos _UINT32_(1) /* (SUPC_STATUS) BOD33 Detection Position */ 98 #define SUPC_STATUS_BOD33DET_Msk (_UINT32_(0x1) << SUPC_STATUS_BOD33DET_Pos) /* (SUPC_STATUS) BOD33 Detection Mask */ 99 #define SUPC_STATUS_BOD33DET(value) (SUPC_STATUS_BOD33DET_Msk & (_UINT32_(value) << SUPC_STATUS_BOD33DET_Pos)) /* Assigment of value for BOD33DET in the SUPC_STATUS register */ 100 #define SUPC_STATUS_B33SRDY_Pos _UINT32_(2) /* (SUPC_STATUS) BOD33 Synchronization Ready Position */ 101 #define SUPC_STATUS_B33SRDY_Msk (_UINT32_(0x1) << SUPC_STATUS_B33SRDY_Pos) /* (SUPC_STATUS) BOD33 Synchronization Ready Mask */ 102 #define SUPC_STATUS_B33SRDY(value) (SUPC_STATUS_B33SRDY_Msk & (_UINT32_(value) << SUPC_STATUS_B33SRDY_Pos)) /* Assigment of value for B33SRDY in the SUPC_STATUS register */ 103 #define SUPC_STATUS_VREGRDY_Pos _UINT32_(8) /* (SUPC_STATUS) Voltage Regulator Ready Position */ 104 #define SUPC_STATUS_VREGRDY_Msk (_UINT32_(0x1) << SUPC_STATUS_VREGRDY_Pos) /* (SUPC_STATUS) Voltage Regulator Ready Mask */ 105 #define SUPC_STATUS_VREGRDY(value) (SUPC_STATUS_VREGRDY_Msk & (_UINT32_(value) << SUPC_STATUS_VREGRDY_Pos)) /* Assigment of value for VREGRDY in the SUPC_STATUS register */ 106 #define SUPC_STATUS_VCORERDY_Pos _UINT32_(10) /* (SUPC_STATUS) VDDCORE Ready Position */ 107 #define SUPC_STATUS_VCORERDY_Msk (_UINT32_(0x1) << SUPC_STATUS_VCORERDY_Pos) /* (SUPC_STATUS) VDDCORE Ready Mask */ 108 #define SUPC_STATUS_VCORERDY(value) (SUPC_STATUS_VCORERDY_Msk & (_UINT32_(value) << SUPC_STATUS_VCORERDY_Pos)) /* Assigment of value for VCORERDY in the SUPC_STATUS register */ 109 #define SUPC_STATUS_Msk _UINT32_(0x00000507) /* (SUPC_STATUS) Register Mask */ 110 111 112 /* -------- SUPC_BOD33 : (SUPC Offset: 0x10) (R/W 32) BOD33 Control -------- */ 113 #define SUPC_BOD33_RESETVALUE _UINT32_(0x00) /* (SUPC_BOD33) BOD33 Control Reset Value */ 114 115 #define SUPC_BOD33_ENABLE_Pos _UINT32_(1) /* (SUPC_BOD33) Enable Position */ 116 #define SUPC_BOD33_ENABLE_Msk (_UINT32_(0x1) << SUPC_BOD33_ENABLE_Pos) /* (SUPC_BOD33) Enable Mask */ 117 #define SUPC_BOD33_ENABLE(value) (SUPC_BOD33_ENABLE_Msk & (_UINT32_(value) << SUPC_BOD33_ENABLE_Pos)) /* Assigment of value for ENABLE in the SUPC_BOD33 register */ 118 #define SUPC_BOD33_ACTION_Pos _UINT32_(2) /* (SUPC_BOD33) Action when Threshold Crossed Position */ 119 #define SUPC_BOD33_ACTION_Msk (_UINT32_(0x3) << SUPC_BOD33_ACTION_Pos) /* (SUPC_BOD33) Action when Threshold Crossed Mask */ 120 #define SUPC_BOD33_ACTION(value) (SUPC_BOD33_ACTION_Msk & (_UINT32_(value) << SUPC_BOD33_ACTION_Pos)) /* Assigment of value for ACTION in the SUPC_BOD33 register */ 121 #define SUPC_BOD33_ACTION_NONE_Val _UINT32_(0x0) /* (SUPC_BOD33) No action */ 122 #define SUPC_BOD33_ACTION_RESET_Val _UINT32_(0x1) /* (SUPC_BOD33) The BOD33 generates a reset */ 123 #define SUPC_BOD33_ACTION_INT_Val _UINT32_(0x2) /* (SUPC_BOD33) The BOD33 generates an interrupt */ 124 #define SUPC_BOD33_ACTION_BKUP_Val _UINT32_(0x3) /* (SUPC_BOD33) The BOD33 puts the device in backup sleep mode */ 125 #define SUPC_BOD33_ACTION_NONE (SUPC_BOD33_ACTION_NONE_Val << SUPC_BOD33_ACTION_Pos) /* (SUPC_BOD33) No action Position */ 126 #define SUPC_BOD33_ACTION_RESET (SUPC_BOD33_ACTION_RESET_Val << SUPC_BOD33_ACTION_Pos) /* (SUPC_BOD33) The BOD33 generates a reset Position */ 127 #define SUPC_BOD33_ACTION_INT (SUPC_BOD33_ACTION_INT_Val << SUPC_BOD33_ACTION_Pos) /* (SUPC_BOD33) The BOD33 generates an interrupt Position */ 128 #define SUPC_BOD33_ACTION_BKUP (SUPC_BOD33_ACTION_BKUP_Val << SUPC_BOD33_ACTION_Pos) /* (SUPC_BOD33) The BOD33 puts the device in backup sleep mode Position */ 129 #define SUPC_BOD33_STDBYCFG_Pos _UINT32_(4) /* (SUPC_BOD33) Configuration in Standby mode Position */ 130 #define SUPC_BOD33_STDBYCFG_Msk (_UINT32_(0x1) << SUPC_BOD33_STDBYCFG_Pos) /* (SUPC_BOD33) Configuration in Standby mode Mask */ 131 #define SUPC_BOD33_STDBYCFG(value) (SUPC_BOD33_STDBYCFG_Msk & (_UINT32_(value) << SUPC_BOD33_STDBYCFG_Pos)) /* Assigment of value for STDBYCFG in the SUPC_BOD33 register */ 132 #define SUPC_BOD33_RUNSTDBY_Pos _UINT32_(5) /* (SUPC_BOD33) Run in Standby mode Position */ 133 #define SUPC_BOD33_RUNSTDBY_Msk (_UINT32_(0x1) << SUPC_BOD33_RUNSTDBY_Pos) /* (SUPC_BOD33) Run in Standby mode Mask */ 134 #define SUPC_BOD33_RUNSTDBY(value) (SUPC_BOD33_RUNSTDBY_Msk & (_UINT32_(value) << SUPC_BOD33_RUNSTDBY_Pos)) /* Assigment of value for RUNSTDBY in the SUPC_BOD33 register */ 135 #define SUPC_BOD33_RUNHIB_Pos _UINT32_(6) /* (SUPC_BOD33) Run in Hibernate mode Position */ 136 #define SUPC_BOD33_RUNHIB_Msk (_UINT32_(0x1) << SUPC_BOD33_RUNHIB_Pos) /* (SUPC_BOD33) Run in Hibernate mode Mask */ 137 #define SUPC_BOD33_RUNHIB(value) (SUPC_BOD33_RUNHIB_Msk & (_UINT32_(value) << SUPC_BOD33_RUNHIB_Pos)) /* Assigment of value for RUNHIB in the SUPC_BOD33 register */ 138 #define SUPC_BOD33_RUNBKUP_Pos _UINT32_(7) /* (SUPC_BOD33) Run in Backup mode Position */ 139 #define SUPC_BOD33_RUNBKUP_Msk (_UINT32_(0x1) << SUPC_BOD33_RUNBKUP_Pos) /* (SUPC_BOD33) Run in Backup mode Mask */ 140 #define SUPC_BOD33_RUNBKUP(value) (SUPC_BOD33_RUNBKUP_Msk & (_UINT32_(value) << SUPC_BOD33_RUNBKUP_Pos)) /* Assigment of value for RUNBKUP in the SUPC_BOD33 register */ 141 #define SUPC_BOD33_HYST_Pos _UINT32_(8) /* (SUPC_BOD33) Hysteresis value Position */ 142 #define SUPC_BOD33_HYST_Msk (_UINT32_(0xF) << SUPC_BOD33_HYST_Pos) /* (SUPC_BOD33) Hysteresis value Mask */ 143 #define SUPC_BOD33_HYST(value) (SUPC_BOD33_HYST_Msk & (_UINT32_(value) << SUPC_BOD33_HYST_Pos)) /* Assigment of value for HYST in the SUPC_BOD33 register */ 144 #define SUPC_BOD33_PSEL_Pos _UINT32_(12) /* (SUPC_BOD33) Prescaler Select Position */ 145 #define SUPC_BOD33_PSEL_Msk (_UINT32_(0x7) << SUPC_BOD33_PSEL_Pos) /* (SUPC_BOD33) Prescaler Select Mask */ 146 #define SUPC_BOD33_PSEL(value) (SUPC_BOD33_PSEL_Msk & (_UINT32_(value) << SUPC_BOD33_PSEL_Pos)) /* Assigment of value for PSEL in the SUPC_BOD33 register */ 147 #define SUPC_BOD33_PSEL_NODIV_Val _UINT32_(0x0) /* (SUPC_BOD33) Not divided */ 148 #define SUPC_BOD33_PSEL_DIV4_Val _UINT32_(0x1) /* (SUPC_BOD33) Divide clock by 4 */ 149 #define SUPC_BOD33_PSEL_DIV8_Val _UINT32_(0x2) /* (SUPC_BOD33) Divide clock by 8 */ 150 #define SUPC_BOD33_PSEL_DIV16_Val _UINT32_(0x3) /* (SUPC_BOD33) Divide clock by 16 */ 151 #define SUPC_BOD33_PSEL_DIV32_Val _UINT32_(0x4) /* (SUPC_BOD33) Divide clock by 32 */ 152 #define SUPC_BOD33_PSEL_DIV64_Val _UINT32_(0x5) /* (SUPC_BOD33) Divide clock by 64 */ 153 #define SUPC_BOD33_PSEL_DIV128_Val _UINT32_(0x6) /* (SUPC_BOD33) Divide clock by 128 */ 154 #define SUPC_BOD33_PSEL_DIV256_Val _UINT32_(0x7) /* (SUPC_BOD33) Divide clock by 256 */ 155 #define SUPC_BOD33_PSEL_NODIV (SUPC_BOD33_PSEL_NODIV_Val << SUPC_BOD33_PSEL_Pos) /* (SUPC_BOD33) Not divided Position */ 156 #define SUPC_BOD33_PSEL_DIV4 (SUPC_BOD33_PSEL_DIV4_Val << SUPC_BOD33_PSEL_Pos) /* (SUPC_BOD33) Divide clock by 4 Position */ 157 #define SUPC_BOD33_PSEL_DIV8 (SUPC_BOD33_PSEL_DIV8_Val << SUPC_BOD33_PSEL_Pos) /* (SUPC_BOD33) Divide clock by 8 Position */ 158 #define SUPC_BOD33_PSEL_DIV16 (SUPC_BOD33_PSEL_DIV16_Val << SUPC_BOD33_PSEL_Pos) /* (SUPC_BOD33) Divide clock by 16 Position */ 159 #define SUPC_BOD33_PSEL_DIV32 (SUPC_BOD33_PSEL_DIV32_Val << SUPC_BOD33_PSEL_Pos) /* (SUPC_BOD33) Divide clock by 32 Position */ 160 #define SUPC_BOD33_PSEL_DIV64 (SUPC_BOD33_PSEL_DIV64_Val << SUPC_BOD33_PSEL_Pos) /* (SUPC_BOD33) Divide clock by 64 Position */ 161 #define SUPC_BOD33_PSEL_DIV128 (SUPC_BOD33_PSEL_DIV128_Val << SUPC_BOD33_PSEL_Pos) /* (SUPC_BOD33) Divide clock by 128 Position */ 162 #define SUPC_BOD33_PSEL_DIV256 (SUPC_BOD33_PSEL_DIV256_Val << SUPC_BOD33_PSEL_Pos) /* (SUPC_BOD33) Divide clock by 256 Position */ 163 #define SUPC_BOD33_LEVEL_Pos _UINT32_(16) /* (SUPC_BOD33) Threshold Level for VDD/AVDD Position */ 164 #define SUPC_BOD33_LEVEL_Msk (_UINT32_(0xFF) << SUPC_BOD33_LEVEL_Pos) /* (SUPC_BOD33) Threshold Level for VDD/AVDD Mask */ 165 #define SUPC_BOD33_LEVEL(value) (SUPC_BOD33_LEVEL_Msk & (_UINT32_(value) << SUPC_BOD33_LEVEL_Pos)) /* Assigment of value for LEVEL in the SUPC_BOD33 register */ 166 #define SUPC_BOD33_VBATLEVEL_Pos _UINT32_(24) /* (SUPC_BOD33) Threshold Level in battery backup sleep mode for VBAT Position */ 167 #define SUPC_BOD33_VBATLEVEL_Msk (_UINT32_(0xFF) << SUPC_BOD33_VBATLEVEL_Pos) /* (SUPC_BOD33) Threshold Level in battery backup sleep mode for VBAT Mask */ 168 #define SUPC_BOD33_VBATLEVEL(value) (SUPC_BOD33_VBATLEVEL_Msk & (_UINT32_(value) << SUPC_BOD33_VBATLEVEL_Pos)) /* Assigment of value for VBATLEVEL in the SUPC_BOD33 register */ 169 #define SUPC_BOD33_Msk _UINT32_(0xFFFF7FFE) /* (SUPC_BOD33) Register Mask */ 170 171 172 /* -------- SUPC_VREG : (SUPC Offset: 0x18) (R/W 32) VREG Control -------- */ 173 #define SUPC_VREG_RESETVALUE _UINT32_(0x02) /* (SUPC_VREG) VREG Control Reset Value */ 174 175 #define SUPC_VREG_ENABLE_Pos _UINT32_(1) /* (SUPC_VREG) Enable Position */ 176 #define SUPC_VREG_ENABLE_Msk (_UINT32_(0x1) << SUPC_VREG_ENABLE_Pos) /* (SUPC_VREG) Enable Mask */ 177 #define SUPC_VREG_ENABLE(value) (SUPC_VREG_ENABLE_Msk & (_UINT32_(value) << SUPC_VREG_ENABLE_Pos)) /* Assigment of value for ENABLE in the SUPC_VREG register */ 178 #define SUPC_VREG_SEL_Pos _UINT32_(2) /* (SUPC_VREG) Voltage Regulator Selection Position */ 179 #define SUPC_VREG_SEL_Msk (_UINT32_(0x1) << SUPC_VREG_SEL_Pos) /* (SUPC_VREG) Voltage Regulator Selection Mask */ 180 #define SUPC_VREG_SEL(value) (SUPC_VREG_SEL_Msk & (_UINT32_(value) << SUPC_VREG_SEL_Pos)) /* Assigment of value for SEL in the SUPC_VREG register */ 181 #define SUPC_VREG_SEL_LDO_Val _UINT32_(0x0) /* (SUPC_VREG) LDO selection */ 182 #define SUPC_VREG_SEL_BUCK_Val _UINT32_(0x1) /* (SUPC_VREG) Buck selection */ 183 #define SUPC_VREG_SEL_LDO (SUPC_VREG_SEL_LDO_Val << SUPC_VREG_SEL_Pos) /* (SUPC_VREG) LDO selection Position */ 184 #define SUPC_VREG_SEL_BUCK (SUPC_VREG_SEL_BUCK_Val << SUPC_VREG_SEL_Pos) /* (SUPC_VREG) Buck selection Position */ 185 #define SUPC_VREG_RUNBKUP_Pos _UINT32_(7) /* (SUPC_VREG) Run in Backup mode Position */ 186 #define SUPC_VREG_RUNBKUP_Msk (_UINT32_(0x1) << SUPC_VREG_RUNBKUP_Pos) /* (SUPC_VREG) Run in Backup mode Mask */ 187 #define SUPC_VREG_RUNBKUP(value) (SUPC_VREG_RUNBKUP_Msk & (_UINT32_(value) << SUPC_VREG_RUNBKUP_Pos)) /* Assigment of value for RUNBKUP in the SUPC_VREG register */ 188 #define SUPC_VREG_VSEN_Pos _UINT32_(16) /* (SUPC_VREG) Voltage Scaling Enable Position */ 189 #define SUPC_VREG_VSEN_Msk (_UINT32_(0x1) << SUPC_VREG_VSEN_Pos) /* (SUPC_VREG) Voltage Scaling Enable Mask */ 190 #define SUPC_VREG_VSEN(value) (SUPC_VREG_VSEN_Msk & (_UINT32_(value) << SUPC_VREG_VSEN_Pos)) /* Assigment of value for VSEN in the SUPC_VREG register */ 191 #define SUPC_VREG_VSPER_Pos _UINT32_(24) /* (SUPC_VREG) Voltage Scaling Period Position */ 192 #define SUPC_VREG_VSPER_Msk (_UINT32_(0x7) << SUPC_VREG_VSPER_Pos) /* (SUPC_VREG) Voltage Scaling Period Mask */ 193 #define SUPC_VREG_VSPER(value) (SUPC_VREG_VSPER_Msk & (_UINT32_(value) << SUPC_VREG_VSPER_Pos)) /* Assigment of value for VSPER in the SUPC_VREG register */ 194 #define SUPC_VREG_Msk _UINT32_(0x07010086) /* (SUPC_VREG) Register Mask */ 195 196 197 /* -------- SUPC_VREF : (SUPC Offset: 0x1C) (R/W 32) VREF Control -------- */ 198 #define SUPC_VREF_RESETVALUE _UINT32_(0x00) /* (SUPC_VREF) VREF Control Reset Value */ 199 200 #define SUPC_VREF_VREFOE_Pos _UINT32_(2) /* (SUPC_VREF) Voltage Reference Output Enable Position */ 201 #define SUPC_VREF_VREFOE_Msk (_UINT32_(0x1) << SUPC_VREF_VREFOE_Pos) /* (SUPC_VREF) Voltage Reference Output Enable Mask */ 202 #define SUPC_VREF_VREFOE(value) (SUPC_VREF_VREFOE_Msk & (_UINT32_(value) << SUPC_VREF_VREFOE_Pos)) /* Assigment of value for VREFOE in the SUPC_VREF register */ 203 #define SUPC_VREF_RUNSTDBY_Pos _UINT32_(6) /* (SUPC_VREF) Run during Standby Position */ 204 #define SUPC_VREF_RUNSTDBY_Msk (_UINT32_(0x1) << SUPC_VREF_RUNSTDBY_Pos) /* (SUPC_VREF) Run during Standby Mask */ 205 #define SUPC_VREF_RUNSTDBY(value) (SUPC_VREF_RUNSTDBY_Msk & (_UINT32_(value) << SUPC_VREF_RUNSTDBY_Pos)) /* Assigment of value for RUNSTDBY in the SUPC_VREF register */ 206 #define SUPC_VREF_ONDEMAND_Pos _UINT32_(7) /* (SUPC_VREF) On Demand Contrl Position */ 207 #define SUPC_VREF_ONDEMAND_Msk (_UINT32_(0x1) << SUPC_VREF_ONDEMAND_Pos) /* (SUPC_VREF) On Demand Contrl Mask */ 208 #define SUPC_VREF_ONDEMAND(value) (SUPC_VREF_ONDEMAND_Msk & (_UINT32_(value) << SUPC_VREF_ONDEMAND_Pos)) /* Assigment of value for ONDEMAND in the SUPC_VREF register */ 209 #define SUPC_VREF_SEL_Pos _UINT32_(16) /* (SUPC_VREF) Voltage Reference Selection Position */ 210 #define SUPC_VREF_SEL_Msk (_UINT32_(0xF) << SUPC_VREF_SEL_Pos) /* (SUPC_VREF) Voltage Reference Selection Mask */ 211 #define SUPC_VREF_SEL(value) (SUPC_VREF_SEL_Msk & (_UINT32_(value) << SUPC_VREF_SEL_Pos)) /* Assigment of value for SEL in the SUPC_VREF register */ 212 #define SUPC_VREF_SEL_2V4_Val _UINT32_(0x6) /* (SUPC_VREF) 2.4V voltage reference typical value */ 213 #define SUPC_VREF_SEL_2V5_Val _UINT32_(0x7) /* (SUPC_VREF) 2.5V voltage reference typical value */ 214 #define SUPC_VREF_SEL_2V4 (SUPC_VREF_SEL_2V4_Val << SUPC_VREF_SEL_Pos) /* (SUPC_VREF) 2.4V voltage reference typical value Position */ 215 #define SUPC_VREF_SEL_2V5 (SUPC_VREF_SEL_2V5_Val << SUPC_VREF_SEL_Pos) /* (SUPC_VREF) 2.5V voltage reference typical value Position */ 216 #define SUPC_VREF_Msk _UINT32_(0x000F00C4) /* (SUPC_VREF) Register Mask */ 217 218 219 /* -------- SUPC_BBPS : (SUPC Offset: 0x20) (R/W 32) Battery Backup Power Switch -------- */ 220 #define SUPC_BBPS_RESETVALUE _UINT32_(0x00) /* (SUPC_BBPS) Battery Backup Power Switch Reset Value */ 221 222 #define SUPC_BBPS_CONF_Pos _UINT32_(0) /* (SUPC_BBPS) Battery Backup Configuration Position */ 223 #define SUPC_BBPS_CONF_Msk (_UINT32_(0x1) << SUPC_BBPS_CONF_Pos) /* (SUPC_BBPS) Battery Backup Configuration Mask */ 224 #define SUPC_BBPS_CONF(value) (SUPC_BBPS_CONF_Msk & (_UINT32_(value) << SUPC_BBPS_CONF_Pos)) /* Assigment of value for CONF in the SUPC_BBPS register */ 225 #define SUPC_BBPS_CONF_BOD33_Val _UINT32_(0x0) /* (SUPC_BBPS) The power switch is handled by the BOD33 */ 226 #define SUPC_BBPS_CONF_FORCED_Val _UINT32_(0x1) /* (SUPC_BBPS) In Backup Domain, the backup domain is always supplied by battery backup power */ 227 #define SUPC_BBPS_CONF_BOD33 (SUPC_BBPS_CONF_BOD33_Val << SUPC_BBPS_CONF_Pos) /* (SUPC_BBPS) The power switch is handled by the BOD33 Position */ 228 #define SUPC_BBPS_CONF_FORCED (SUPC_BBPS_CONF_FORCED_Val << SUPC_BBPS_CONF_Pos) /* (SUPC_BBPS) In Backup Domain, the backup domain is always supplied by battery backup power Position */ 229 #define SUPC_BBPS_WAKEEN_Pos _UINT32_(2) /* (SUPC_BBPS) Wake Enable Position */ 230 #define SUPC_BBPS_WAKEEN_Msk (_UINT32_(0x1) << SUPC_BBPS_WAKEEN_Pos) /* (SUPC_BBPS) Wake Enable Mask */ 231 #define SUPC_BBPS_WAKEEN(value) (SUPC_BBPS_WAKEEN_Msk & (_UINT32_(value) << SUPC_BBPS_WAKEEN_Pos)) /* Assigment of value for WAKEEN in the SUPC_BBPS register */ 232 #define SUPC_BBPS_Msk _UINT32_(0x00000005) /* (SUPC_BBPS) Register Mask */ 233 234 235 /* -------- SUPC_BKOUT : (SUPC Offset: 0x24) (R/W 32) Backup Output Control -------- */ 236 #define SUPC_BKOUT_RESETVALUE _UINT32_(0x00) /* (SUPC_BKOUT) Backup Output Control Reset Value */ 237 238 #define SUPC_BKOUT_ENOUT0_Pos _UINT32_(0) /* (SUPC_BKOUT) Enable OUT0 Position */ 239 #define SUPC_BKOUT_ENOUT0_Msk (_UINT32_(0x1) << SUPC_BKOUT_ENOUT0_Pos) /* (SUPC_BKOUT) Enable OUT0 Mask */ 240 #define SUPC_BKOUT_ENOUT0(value) (SUPC_BKOUT_ENOUT0_Msk & (_UINT32_(value) << SUPC_BKOUT_ENOUT0_Pos)) /* Assigment of value for ENOUT0 in the SUPC_BKOUT register */ 241 #define SUPC_BKOUT_ENOUT1_Pos _UINT32_(1) /* (SUPC_BKOUT) Enable OUT1 Position */ 242 #define SUPC_BKOUT_ENOUT1_Msk (_UINT32_(0x1) << SUPC_BKOUT_ENOUT1_Pos) /* (SUPC_BKOUT) Enable OUT1 Mask */ 243 #define SUPC_BKOUT_ENOUT1(value) (SUPC_BKOUT_ENOUT1_Msk & (_UINT32_(value) << SUPC_BKOUT_ENOUT1_Pos)) /* Assigment of value for ENOUT1 in the SUPC_BKOUT register */ 244 #define SUPC_BKOUT_CLROUT0_Pos _UINT32_(8) /* (SUPC_BKOUT) Clear OUT0 Position */ 245 #define SUPC_BKOUT_CLROUT0_Msk (_UINT32_(0x1) << SUPC_BKOUT_CLROUT0_Pos) /* (SUPC_BKOUT) Clear OUT0 Mask */ 246 #define SUPC_BKOUT_CLROUT0(value) (SUPC_BKOUT_CLROUT0_Msk & (_UINT32_(value) << SUPC_BKOUT_CLROUT0_Pos)) /* Assigment of value for CLROUT0 in the SUPC_BKOUT register */ 247 #define SUPC_BKOUT_CLROUT1_Pos _UINT32_(9) /* (SUPC_BKOUT) Clear OUT1 Position */ 248 #define SUPC_BKOUT_CLROUT1_Msk (_UINT32_(0x1) << SUPC_BKOUT_CLROUT1_Pos) /* (SUPC_BKOUT) Clear OUT1 Mask */ 249 #define SUPC_BKOUT_CLROUT1(value) (SUPC_BKOUT_CLROUT1_Msk & (_UINT32_(value) << SUPC_BKOUT_CLROUT1_Pos)) /* Assigment of value for CLROUT1 in the SUPC_BKOUT register */ 250 #define SUPC_BKOUT_SETOUT0_Pos _UINT32_(16) /* (SUPC_BKOUT) Set OUT0 Position */ 251 #define SUPC_BKOUT_SETOUT0_Msk (_UINT32_(0x1) << SUPC_BKOUT_SETOUT0_Pos) /* (SUPC_BKOUT) Set OUT0 Mask */ 252 #define SUPC_BKOUT_SETOUT0(value) (SUPC_BKOUT_SETOUT0_Msk & (_UINT32_(value) << SUPC_BKOUT_SETOUT0_Pos)) /* Assigment of value for SETOUT0 in the SUPC_BKOUT register */ 253 #define SUPC_BKOUT_SETOUT1_Pos _UINT32_(17) /* (SUPC_BKOUT) Set OUT1 Position */ 254 #define SUPC_BKOUT_SETOUT1_Msk (_UINT32_(0x1) << SUPC_BKOUT_SETOUT1_Pos) /* (SUPC_BKOUT) Set OUT1 Mask */ 255 #define SUPC_BKOUT_SETOUT1(value) (SUPC_BKOUT_SETOUT1_Msk & (_UINT32_(value) << SUPC_BKOUT_SETOUT1_Pos)) /* Assigment of value for SETOUT1 in the SUPC_BKOUT register */ 256 #define SUPC_BKOUT_RTCTGLOUT0_Pos _UINT32_(24) /* (SUPC_BKOUT) RTC Toggle OUT0 Position */ 257 #define SUPC_BKOUT_RTCTGLOUT0_Msk (_UINT32_(0x1) << SUPC_BKOUT_RTCTGLOUT0_Pos) /* (SUPC_BKOUT) RTC Toggle OUT0 Mask */ 258 #define SUPC_BKOUT_RTCTGLOUT0(value) (SUPC_BKOUT_RTCTGLOUT0_Msk & (_UINT32_(value) << SUPC_BKOUT_RTCTGLOUT0_Pos)) /* Assigment of value for RTCTGLOUT0 in the SUPC_BKOUT register */ 259 #define SUPC_BKOUT_RTCTGLOUT1_Pos _UINT32_(25) /* (SUPC_BKOUT) RTC Toggle OUT1 Position */ 260 #define SUPC_BKOUT_RTCTGLOUT1_Msk (_UINT32_(0x1) << SUPC_BKOUT_RTCTGLOUT1_Pos) /* (SUPC_BKOUT) RTC Toggle OUT1 Mask */ 261 #define SUPC_BKOUT_RTCTGLOUT1(value) (SUPC_BKOUT_RTCTGLOUT1_Msk & (_UINT32_(value) << SUPC_BKOUT_RTCTGLOUT1_Pos)) /* Assigment of value for RTCTGLOUT1 in the SUPC_BKOUT register */ 262 #define SUPC_BKOUT_Msk _UINT32_(0x03030303) /* (SUPC_BKOUT) Register Mask */ 263 264 #define SUPC_BKOUT_ENOUT_Pos _UINT32_(0) /* (SUPC_BKOUT Position) Enable OUTx */ 265 #define SUPC_BKOUT_ENOUT_Msk (_UINT32_(0x3) << SUPC_BKOUT_ENOUT_Pos) /* (SUPC_BKOUT Mask) ENOUT */ 266 #define SUPC_BKOUT_ENOUT(value) (SUPC_BKOUT_ENOUT_Msk & (_UINT32_(value) << SUPC_BKOUT_ENOUT_Pos)) 267 #define SUPC_BKOUT_CLROUT_Pos _UINT32_(8) /* (SUPC_BKOUT Position) Clear OUTx */ 268 #define SUPC_BKOUT_CLROUT_Msk (_UINT32_(0x3) << SUPC_BKOUT_CLROUT_Pos) /* (SUPC_BKOUT Mask) CLROUT */ 269 #define SUPC_BKOUT_CLROUT(value) (SUPC_BKOUT_CLROUT_Msk & (_UINT32_(value) << SUPC_BKOUT_CLROUT_Pos)) 270 #define SUPC_BKOUT_SETOUT_Pos _UINT32_(16) /* (SUPC_BKOUT Position) Set OUTx */ 271 #define SUPC_BKOUT_SETOUT_Msk (_UINT32_(0x3) << SUPC_BKOUT_SETOUT_Pos) /* (SUPC_BKOUT Mask) SETOUT */ 272 #define SUPC_BKOUT_SETOUT(value) (SUPC_BKOUT_SETOUT_Msk & (_UINT32_(value) << SUPC_BKOUT_SETOUT_Pos)) 273 #define SUPC_BKOUT_RTCTGLOUT_Pos _UINT32_(24) /* (SUPC_BKOUT Position) RTC Toggle OUTx */ 274 #define SUPC_BKOUT_RTCTGLOUT_Msk (_UINT32_(0x3) << SUPC_BKOUT_RTCTGLOUT_Pos) /* (SUPC_BKOUT Mask) RTCTGLOUT */ 275 #define SUPC_BKOUT_RTCTGLOUT(value) (SUPC_BKOUT_RTCTGLOUT_Msk & (_UINT32_(value) << SUPC_BKOUT_RTCTGLOUT_Pos)) 276 277 /* -------- SUPC_BKIN : (SUPC Offset: 0x28) ( R/ 32) Backup Input Control -------- */ 278 #define SUPC_BKIN_RESETVALUE _UINT32_(0x00) /* (SUPC_BKIN) Backup Input Control Reset Value */ 279 280 #define SUPC_BKIN_BKIN0_Pos _UINT32_(0) /* (SUPC_BKIN) Backup Input 0 Position */ 281 #define SUPC_BKIN_BKIN0_Msk (_UINT32_(0x1) << SUPC_BKIN_BKIN0_Pos) /* (SUPC_BKIN) Backup Input 0 Mask */ 282 #define SUPC_BKIN_BKIN0(value) (SUPC_BKIN_BKIN0_Msk & (_UINT32_(value) << SUPC_BKIN_BKIN0_Pos)) /* Assigment of value for BKIN0 in the SUPC_BKIN register */ 283 #define SUPC_BKIN_BKIN1_Pos _UINT32_(1) /* (SUPC_BKIN) Backup Input 1 Position */ 284 #define SUPC_BKIN_BKIN1_Msk (_UINT32_(0x1) << SUPC_BKIN_BKIN1_Pos) /* (SUPC_BKIN) Backup Input 1 Mask */ 285 #define SUPC_BKIN_BKIN1(value) (SUPC_BKIN_BKIN1_Msk & (_UINT32_(value) << SUPC_BKIN_BKIN1_Pos)) /* Assigment of value for BKIN1 in the SUPC_BKIN register */ 286 #define SUPC_BKIN_Msk _UINT32_(0x00000003) /* (SUPC_BKIN) Register Mask */ 287 288 #define SUPC_BKIN_BKIN_Pos _UINT32_(0) /* (SUPC_BKIN Position) Backup Input x */ 289 #define SUPC_BKIN_BKIN_Msk (_UINT32_(0x3) << SUPC_BKIN_BKIN_Pos) /* (SUPC_BKIN Mask) BKIN */ 290 #define SUPC_BKIN_BKIN(value) (SUPC_BKIN_BKIN_Msk & (_UINT32_(value) << SUPC_BKIN_BKIN_Pos)) 291 292 /** \brief SUPC register offsets definitions */ 293 #define SUPC_INTENCLR_REG_OFST _UINT32_(0x00) /* (SUPC_INTENCLR) Interrupt Enable Clear Offset */ 294 #define SUPC_INTENSET_REG_OFST _UINT32_(0x04) /* (SUPC_INTENSET) Interrupt Enable Set Offset */ 295 #define SUPC_INTFLAG_REG_OFST _UINT32_(0x08) /* (SUPC_INTFLAG) Interrupt Flag Status and Clear Offset */ 296 #define SUPC_STATUS_REG_OFST _UINT32_(0x0C) /* (SUPC_STATUS) Power and Clocks Status Offset */ 297 #define SUPC_BOD33_REG_OFST _UINT32_(0x10) /* (SUPC_BOD33) BOD33 Control Offset */ 298 #define SUPC_VREG_REG_OFST _UINT32_(0x18) /* (SUPC_VREG) VREG Control Offset */ 299 #define SUPC_VREF_REG_OFST _UINT32_(0x1C) /* (SUPC_VREF) VREF Control Offset */ 300 #define SUPC_BBPS_REG_OFST _UINT32_(0x20) /* (SUPC_BBPS) Battery Backup Power Switch Offset */ 301 #define SUPC_BKOUT_REG_OFST _UINT32_(0x24) /* (SUPC_BKOUT) Backup Output Control Offset */ 302 #define SUPC_BKIN_REG_OFST _UINT32_(0x28) /* (SUPC_BKIN) Backup Input Control Offset */ 303 304 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 305 /** \brief SUPC register API structure */ 306 typedef struct 307 { /* Supply Controller */ 308 __IO uint32_t SUPC_INTENCLR; /**< Offset: 0x00 (R/W 32) Interrupt Enable Clear */ 309 __IO uint32_t SUPC_INTENSET; /**< Offset: 0x04 (R/W 32) Interrupt Enable Set */ 310 __IO uint32_t SUPC_INTFLAG; /**< Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */ 311 __I uint32_t SUPC_STATUS; /**< Offset: 0x0C (R/ 32) Power and Clocks Status */ 312 __IO uint32_t SUPC_BOD33; /**< Offset: 0x10 (R/W 32) BOD33 Control */ 313 __I uint8_t Reserved1[0x04]; 314 __IO uint32_t SUPC_VREG; /**< Offset: 0x18 (R/W 32) VREG Control */ 315 __IO uint32_t SUPC_VREF; /**< Offset: 0x1C (R/W 32) VREF Control */ 316 __IO uint32_t SUPC_BBPS; /**< Offset: 0x20 (R/W 32) Battery Backup Power Switch */ 317 __IO uint32_t SUPC_BKOUT; /**< Offset: 0x24 (R/W 32) Backup Output Control */ 318 __I uint32_t SUPC_BKIN; /**< Offset: 0x28 (R/ 32) Backup Input Control */ 319 } supc_registers_t; 320 321 322 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 323 #endif /* _PIC32CXSG60_SUPC_COMPONENT_H_ */ 324
