1 /*
2  * Component description for SERCOM
3  *
4  * Copyright (c) 2023 Microchip Technology Inc. and its subsidiaries.
5  *
6  * Licensed under the Apache License, Version 2.0 (the "License");
7  * you may not use this file except in compliance with the License.
8  * You may obtain a copy of the License at
9  *
10  *   http://www.apache.org/licenses/LICENSE-2.0
11  *
12  * Unless required by applicable law or agreed to in writing, software
13  * distributed under the License is distributed on an "AS IS" BASIS,
14  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15  * See the License for the specific language governing permissions and
16  * limitations under the License.
17  *
18  */
19 
20 /* file generated from device description file (ATDF) version 2023-03-17T09:48:46Z */
21 #ifndef _PIC32CXSG60_SERCOM_COMPONENT_H_
22 #define _PIC32CXSG60_SERCOM_COMPONENT_H_
23 
24 /* ************************************************************************** */
25 /*   SOFTWARE API DEFINITION FOR SERCOM                                       */
26 /* ************************************************************************** */
27 
28 /* -------- SERCOM_I2CM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CM Control A -------- */
29 #define SERCOM_I2CM_CTRLA_RESETVALUE          _UINT32_(0x00)                                       /*  (SERCOM_I2CM_CTRLA) I2CM Control A  Reset Value */
30 
31 #define SERCOM_I2CM_CTRLA_SWRST_Pos           _UINT32_(0)                                          /* (SERCOM_I2CM_CTRLA) Software Reset Position */
32 #define SERCOM_I2CM_CTRLA_SWRST_Msk           (_UINT32_(0x1) << SERCOM_I2CM_CTRLA_SWRST_Pos)       /* (SERCOM_I2CM_CTRLA) Software Reset Mask */
33 #define SERCOM_I2CM_CTRLA_SWRST(value)        (SERCOM_I2CM_CTRLA_SWRST_Msk & (_UINT32_(value) << SERCOM_I2CM_CTRLA_SWRST_Pos)) /* Assigment of value for SWRST in the SERCOM_I2CM_CTRLA register */
34 #define SERCOM_I2CM_CTRLA_ENABLE_Pos          _UINT32_(1)                                          /* (SERCOM_I2CM_CTRLA) Enable Position */
35 #define SERCOM_I2CM_CTRLA_ENABLE_Msk          (_UINT32_(0x1) << SERCOM_I2CM_CTRLA_ENABLE_Pos)      /* (SERCOM_I2CM_CTRLA) Enable Mask */
36 #define SERCOM_I2CM_CTRLA_ENABLE(value)       (SERCOM_I2CM_CTRLA_ENABLE_Msk & (_UINT32_(value) << SERCOM_I2CM_CTRLA_ENABLE_Pos)) /* Assigment of value for ENABLE in the SERCOM_I2CM_CTRLA register */
37 #define SERCOM_I2CM_CTRLA_MODE_Pos            _UINT32_(2)                                          /* (SERCOM_I2CM_CTRLA) Operating Mode Position */
38 #define SERCOM_I2CM_CTRLA_MODE_Msk            (_UINT32_(0x7) << SERCOM_I2CM_CTRLA_MODE_Pos)        /* (SERCOM_I2CM_CTRLA) Operating Mode Mask */
39 #define SERCOM_I2CM_CTRLA_MODE(value)         (SERCOM_I2CM_CTRLA_MODE_Msk & (_UINT32_(value) << SERCOM_I2CM_CTRLA_MODE_Pos)) /* Assigment of value for MODE in the SERCOM_I2CM_CTRLA register */
40 #define   SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val _UINT32_(0x0)                                        /* (SERCOM_I2CM_CTRLA) USART with external clock  */
41 #define   SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val _UINT32_(0x1)                                        /* (SERCOM_I2CM_CTRLA) USART with internal clock  */
42 #define   SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val _UINT32_(0x2)                                        /* (SERCOM_I2CM_CTRLA) SPI in slave operation  */
43 #define   SERCOM_I2CM_CTRLA_MODE_SPI_MASTER_Val _UINT32_(0x3)                                        /* (SERCOM_I2CM_CTRLA) SPI in master operation  */
44 #define   SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE_Val _UINT32_(0x4)                                        /* (SERCOM_I2CM_CTRLA) I2C slave operation  */
45 #define   SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val _UINT32_(0x5)                                        /* (SERCOM_I2CM_CTRLA) I2C master operation  */
46 #define SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK  (SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_I2CM_CTRLA_MODE_Pos) /* (SERCOM_I2CM_CTRLA) USART with external clock Position  */
47 #define SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK  (SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_I2CM_CTRLA_MODE_Pos) /* (SERCOM_I2CM_CTRLA) USART with internal clock Position  */
48 #define SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE      (SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_I2CM_CTRLA_MODE_Pos) /* (SERCOM_I2CM_CTRLA) SPI in slave operation Position  */
49 #define SERCOM_I2CM_CTRLA_MODE_SPI_MASTER     (SERCOM_I2CM_CTRLA_MODE_SPI_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos) /* (SERCOM_I2CM_CTRLA) SPI in master operation Position  */
50 #define SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE      (SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CM_CTRLA_MODE_Pos) /* (SERCOM_I2CM_CTRLA) I2C slave operation Position  */
51 #define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER     (SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos) /* (SERCOM_I2CM_CTRLA) I2C master operation Position  */
52 #define SERCOM_I2CM_CTRLA_RUNSTDBY_Pos        _UINT32_(7)                                          /* (SERCOM_I2CM_CTRLA) Run in Standby Position */
53 #define SERCOM_I2CM_CTRLA_RUNSTDBY_Msk        (_UINT32_(0x1) << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos)    /* (SERCOM_I2CM_CTRLA) Run in Standby Mask */
54 #define SERCOM_I2CM_CTRLA_RUNSTDBY(value)     (SERCOM_I2CM_CTRLA_RUNSTDBY_Msk & (_UINT32_(value) << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos)) /* Assigment of value for RUNSTDBY in the SERCOM_I2CM_CTRLA register */
55 #define SERCOM_I2CM_CTRLA_PINOUT_Pos          _UINT32_(16)                                         /* (SERCOM_I2CM_CTRLA) Pin Usage Position */
56 #define SERCOM_I2CM_CTRLA_PINOUT_Msk          (_UINT32_(0x1) << SERCOM_I2CM_CTRLA_PINOUT_Pos)      /* (SERCOM_I2CM_CTRLA) Pin Usage Mask */
57 #define SERCOM_I2CM_CTRLA_PINOUT(value)       (SERCOM_I2CM_CTRLA_PINOUT_Msk & (_UINT32_(value) << SERCOM_I2CM_CTRLA_PINOUT_Pos)) /* Assigment of value for PINOUT in the SERCOM_I2CM_CTRLA register */
58 #define SERCOM_I2CM_CTRLA_SDAHOLD_Pos         _UINT32_(20)                                         /* (SERCOM_I2CM_CTRLA) SDA Hold Time Position */
59 #define SERCOM_I2CM_CTRLA_SDAHOLD_Msk         (_UINT32_(0x3) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos)     /* (SERCOM_I2CM_CTRLA) SDA Hold Time Mask */
60 #define SERCOM_I2CM_CTRLA_SDAHOLD(value)      (SERCOM_I2CM_CTRLA_SDAHOLD_Msk & (_UINT32_(value) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos)) /* Assigment of value for SDAHOLD in the SERCOM_I2CM_CTRLA register */
61 #define   SERCOM_I2CM_CTRLA_SDAHOLD_DISABLE_Val _UINT32_(0x0)                                        /* (SERCOM_I2CM_CTRLA) Disabled  */
62 #define   SERCOM_I2CM_CTRLA_SDAHOLD_75NS_Val  _UINT32_(0x1)                                        /* (SERCOM_I2CM_CTRLA) 50-100ns hold time  */
63 #define   SERCOM_I2CM_CTRLA_SDAHOLD_450NS_Val _UINT32_(0x2)                                        /* (SERCOM_I2CM_CTRLA) 300-600ns hold time  */
64 #define   SERCOM_I2CM_CTRLA_SDAHOLD_600NS_Val _UINT32_(0x3)                                        /* (SERCOM_I2CM_CTRLA) 400-800ns hold time  */
65 #define SERCOM_I2CM_CTRLA_SDAHOLD_DISABLE     (SERCOM_I2CM_CTRLA_SDAHOLD_DISABLE_Val << SERCOM_I2CM_CTRLA_SDAHOLD_Pos) /* (SERCOM_I2CM_CTRLA) Disabled Position  */
66 #define SERCOM_I2CM_CTRLA_SDAHOLD_75NS        (SERCOM_I2CM_CTRLA_SDAHOLD_75NS_Val << SERCOM_I2CM_CTRLA_SDAHOLD_Pos) /* (SERCOM_I2CM_CTRLA) 50-100ns hold time Position  */
67 #define SERCOM_I2CM_CTRLA_SDAHOLD_450NS       (SERCOM_I2CM_CTRLA_SDAHOLD_450NS_Val << SERCOM_I2CM_CTRLA_SDAHOLD_Pos) /* (SERCOM_I2CM_CTRLA) 300-600ns hold time Position  */
68 #define SERCOM_I2CM_CTRLA_SDAHOLD_600NS       (SERCOM_I2CM_CTRLA_SDAHOLD_600NS_Val << SERCOM_I2CM_CTRLA_SDAHOLD_Pos) /* (SERCOM_I2CM_CTRLA) 400-800ns hold time Position  */
69 #define SERCOM_I2CM_CTRLA_MEXTTOEN_Pos        _UINT32_(22)                                         /* (SERCOM_I2CM_CTRLA) Master SCL Low Extend Timeout Position */
70 #define SERCOM_I2CM_CTRLA_MEXTTOEN_Msk        (_UINT32_(0x1) << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos)    /* (SERCOM_I2CM_CTRLA) Master SCL Low Extend Timeout Mask */
71 #define SERCOM_I2CM_CTRLA_MEXTTOEN(value)     (SERCOM_I2CM_CTRLA_MEXTTOEN_Msk & (_UINT32_(value) << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos)) /* Assigment of value for MEXTTOEN in the SERCOM_I2CM_CTRLA register */
72 #define SERCOM_I2CM_CTRLA_SEXTTOEN_Pos        _UINT32_(23)                                         /* (SERCOM_I2CM_CTRLA) Slave SCL Low Extend Timeout Position */
73 #define SERCOM_I2CM_CTRLA_SEXTTOEN_Msk        (_UINT32_(0x1) << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos)    /* (SERCOM_I2CM_CTRLA) Slave SCL Low Extend Timeout Mask */
74 #define SERCOM_I2CM_CTRLA_SEXTTOEN(value)     (SERCOM_I2CM_CTRLA_SEXTTOEN_Msk & (_UINT32_(value) << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos)) /* Assigment of value for SEXTTOEN in the SERCOM_I2CM_CTRLA register */
75 #define SERCOM_I2CM_CTRLA_SPEED_Pos           _UINT32_(24)                                         /* (SERCOM_I2CM_CTRLA) Transfer Speed Position */
76 #define SERCOM_I2CM_CTRLA_SPEED_Msk           (_UINT32_(0x3) << SERCOM_I2CM_CTRLA_SPEED_Pos)       /* (SERCOM_I2CM_CTRLA) Transfer Speed Mask */
77 #define SERCOM_I2CM_CTRLA_SPEED(value)        (SERCOM_I2CM_CTRLA_SPEED_Msk & (_UINT32_(value) << SERCOM_I2CM_CTRLA_SPEED_Pos)) /* Assigment of value for SPEED in the SERCOM_I2CM_CTRLA register */
78 #define   SERCOM_I2CM_CTRLA_SPEED_STANDARD_AND_FAST_MODE_Val _UINT32_(0x0)                                        /* (SERCOM_I2CM_CTRLA) Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz   */
79 #define   SERCOM_I2CM_CTRLA_SPEED_FASTPLUS_MODE_Val _UINT32_(0x1)                                        /* (SERCOM_I2CM_CTRLA) Fast-mode Plus Upto 1MHz  */
80 #define   SERCOM_I2CM_CTRLA_SPEED_HIGH_SPEED_MODE_Val _UINT32_(0x2)                                        /* (SERCOM_I2CM_CTRLA) High-speed mode Upto 3.4MHz  */
81 #define SERCOM_I2CM_CTRLA_SPEED_STANDARD_AND_FAST_MODE (SERCOM_I2CM_CTRLA_SPEED_STANDARD_AND_FAST_MODE_Val << SERCOM_I2CM_CTRLA_SPEED_Pos) /* (SERCOM_I2CM_CTRLA) Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz  Position  */
82 #define SERCOM_I2CM_CTRLA_SPEED_FASTPLUS_MODE (SERCOM_I2CM_CTRLA_SPEED_FASTPLUS_MODE_Val << SERCOM_I2CM_CTRLA_SPEED_Pos) /* (SERCOM_I2CM_CTRLA) Fast-mode Plus Upto 1MHz Position  */
83 #define SERCOM_I2CM_CTRLA_SPEED_HIGH_SPEED_MODE (SERCOM_I2CM_CTRLA_SPEED_HIGH_SPEED_MODE_Val << SERCOM_I2CM_CTRLA_SPEED_Pos) /* (SERCOM_I2CM_CTRLA) High-speed mode Upto 3.4MHz Position  */
84 #define SERCOM_I2CM_CTRLA_SCLSM_Pos           _UINT32_(27)                                         /* (SERCOM_I2CM_CTRLA) SCL Clock Stretch Mode Position */
85 #define SERCOM_I2CM_CTRLA_SCLSM_Msk           (_UINT32_(0x1) << SERCOM_I2CM_CTRLA_SCLSM_Pos)       /* (SERCOM_I2CM_CTRLA) SCL Clock Stretch Mode Mask */
86 #define SERCOM_I2CM_CTRLA_SCLSM(value)        (SERCOM_I2CM_CTRLA_SCLSM_Msk & (_UINT32_(value) << SERCOM_I2CM_CTRLA_SCLSM_Pos)) /* Assigment of value for SCLSM in the SERCOM_I2CM_CTRLA register */
87 #define SERCOM_I2CM_CTRLA_INACTOUT_Pos        _UINT32_(28)                                         /* (SERCOM_I2CM_CTRLA) Inactive Time-Out Position */
88 #define SERCOM_I2CM_CTRLA_INACTOUT_Msk        (_UINT32_(0x3) << SERCOM_I2CM_CTRLA_INACTOUT_Pos)    /* (SERCOM_I2CM_CTRLA) Inactive Time-Out Mask */
89 #define SERCOM_I2CM_CTRLA_INACTOUT(value)     (SERCOM_I2CM_CTRLA_INACTOUT_Msk & (_UINT32_(value) << SERCOM_I2CM_CTRLA_INACTOUT_Pos)) /* Assigment of value for INACTOUT in the SERCOM_I2CM_CTRLA register */
90 #define   SERCOM_I2CM_CTRLA_INACTOUT_DISABLE_Val _UINT32_(0x0)                                        /* (SERCOM_I2CM_CTRLA) Disabled  */
91 #define   SERCOM_I2CM_CTRLA_INACTOUT_55US_Val _UINT32_(0x1)                                        /* (SERCOM_I2CM_CTRLA) 5-6 SCL Time-Out(50-60us)  */
92 #define   SERCOM_I2CM_CTRLA_INACTOUT_105US_Val _UINT32_(0x2)                                        /* (SERCOM_I2CM_CTRLA) 10-11 SCL Time-Out(100-110us)  */
93 #define   SERCOM_I2CM_CTRLA_INACTOUT_205US_Val _UINT32_(0x3)                                        /* (SERCOM_I2CM_CTRLA) 20-21 SCL Time-Out(200-210us)  */
94 #define SERCOM_I2CM_CTRLA_INACTOUT_DISABLE    (SERCOM_I2CM_CTRLA_INACTOUT_DISABLE_Val << SERCOM_I2CM_CTRLA_INACTOUT_Pos) /* (SERCOM_I2CM_CTRLA) Disabled Position  */
95 #define SERCOM_I2CM_CTRLA_INACTOUT_55US       (SERCOM_I2CM_CTRLA_INACTOUT_55US_Val << SERCOM_I2CM_CTRLA_INACTOUT_Pos) /* (SERCOM_I2CM_CTRLA) 5-6 SCL Time-Out(50-60us) Position  */
96 #define SERCOM_I2CM_CTRLA_INACTOUT_105US      (SERCOM_I2CM_CTRLA_INACTOUT_105US_Val << SERCOM_I2CM_CTRLA_INACTOUT_Pos) /* (SERCOM_I2CM_CTRLA) 10-11 SCL Time-Out(100-110us) Position  */
97 #define SERCOM_I2CM_CTRLA_INACTOUT_205US      (SERCOM_I2CM_CTRLA_INACTOUT_205US_Val << SERCOM_I2CM_CTRLA_INACTOUT_Pos) /* (SERCOM_I2CM_CTRLA) 20-21 SCL Time-Out(200-210us) Position  */
98 #define SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos       _UINT32_(30)                                         /* (SERCOM_I2CM_CTRLA) SCL Low Timeout Enable Position */
99 #define SERCOM_I2CM_CTRLA_LOWTOUTEN_Msk       (_UINT32_(0x1) << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos)   /* (SERCOM_I2CM_CTRLA) SCL Low Timeout Enable Mask */
100 #define SERCOM_I2CM_CTRLA_LOWTOUTEN(value)    (SERCOM_I2CM_CTRLA_LOWTOUTEN_Msk & (_UINT32_(value) << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos)) /* Assigment of value for LOWTOUTEN in the SERCOM_I2CM_CTRLA register */
101 #define SERCOM_I2CM_CTRLA_Msk                 _UINT32_(0x7BF1009F)                                 /* (SERCOM_I2CM_CTRLA) Register Mask  */
102 
103 
104 /* -------- SERCOM_I2CS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CS Control A -------- */
105 #define SERCOM_I2CS_CTRLA_RESETVALUE          _UINT32_(0x00)                                       /*  (SERCOM_I2CS_CTRLA) I2CS Control A  Reset Value */
106 
107 #define SERCOM_I2CS_CTRLA_SWRST_Pos           _UINT32_(0)                                          /* (SERCOM_I2CS_CTRLA) Software Reset Position */
108 #define SERCOM_I2CS_CTRLA_SWRST_Msk           (_UINT32_(0x1) << SERCOM_I2CS_CTRLA_SWRST_Pos)       /* (SERCOM_I2CS_CTRLA) Software Reset Mask */
109 #define SERCOM_I2CS_CTRLA_SWRST(value)        (SERCOM_I2CS_CTRLA_SWRST_Msk & (_UINT32_(value) << SERCOM_I2CS_CTRLA_SWRST_Pos)) /* Assigment of value for SWRST in the SERCOM_I2CS_CTRLA register */
110 #define SERCOM_I2CS_CTRLA_ENABLE_Pos          _UINT32_(1)                                          /* (SERCOM_I2CS_CTRLA) Enable Position */
111 #define SERCOM_I2CS_CTRLA_ENABLE_Msk          (_UINT32_(0x1) << SERCOM_I2CS_CTRLA_ENABLE_Pos)      /* (SERCOM_I2CS_CTRLA) Enable Mask */
112 #define SERCOM_I2CS_CTRLA_ENABLE(value)       (SERCOM_I2CS_CTRLA_ENABLE_Msk & (_UINT32_(value) << SERCOM_I2CS_CTRLA_ENABLE_Pos)) /* Assigment of value for ENABLE in the SERCOM_I2CS_CTRLA register */
113 #define SERCOM_I2CS_CTRLA_MODE_Pos            _UINT32_(2)                                          /* (SERCOM_I2CS_CTRLA) Operating Mode Position */
114 #define SERCOM_I2CS_CTRLA_MODE_Msk            (_UINT32_(0x7) << SERCOM_I2CS_CTRLA_MODE_Pos)        /* (SERCOM_I2CS_CTRLA) Operating Mode Mask */
115 #define SERCOM_I2CS_CTRLA_MODE(value)         (SERCOM_I2CS_CTRLA_MODE_Msk & (_UINT32_(value) << SERCOM_I2CS_CTRLA_MODE_Pos)) /* Assigment of value for MODE in the SERCOM_I2CS_CTRLA register */
116 #define   SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val _UINT32_(0x0)                                        /* (SERCOM_I2CS_CTRLA) USART with external clock  */
117 #define   SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val _UINT32_(0x1)                                        /* (SERCOM_I2CS_CTRLA) USART with internal clock  */
118 #define   SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val _UINT32_(0x2)                                        /* (SERCOM_I2CS_CTRLA) SPI in slave operation  */
119 #define   SERCOM_I2CS_CTRLA_MODE_SPI_MASTER_Val _UINT32_(0x3)                                        /* (SERCOM_I2CS_CTRLA) SPI in master operation  */
120 #define   SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val _UINT32_(0x4)                                        /* (SERCOM_I2CS_CTRLA) I2C slave operation  */
121 #define   SERCOM_I2CS_CTRLA_MODE_I2C_MASTER_Val _UINT32_(0x5)                                        /* (SERCOM_I2CS_CTRLA) I2C master operation  */
122 #define SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK  (SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_I2CS_CTRLA_MODE_Pos) /* (SERCOM_I2CS_CTRLA) USART with external clock Position  */
123 #define SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK  (SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_I2CS_CTRLA_MODE_Pos) /* (SERCOM_I2CS_CTRLA) USART with internal clock Position  */
124 #define SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE      (SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos) /* (SERCOM_I2CS_CTRLA) SPI in slave operation Position  */
125 #define SERCOM_I2CS_CTRLA_MODE_SPI_MASTER     (SERCOM_I2CS_CTRLA_MODE_SPI_MASTER_Val << SERCOM_I2CS_CTRLA_MODE_Pos) /* (SERCOM_I2CS_CTRLA) SPI in master operation Position  */
126 #define SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE      (SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos) /* (SERCOM_I2CS_CTRLA) I2C slave operation Position  */
127 #define SERCOM_I2CS_CTRLA_MODE_I2C_MASTER     (SERCOM_I2CS_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CS_CTRLA_MODE_Pos) /* (SERCOM_I2CS_CTRLA) I2C master operation Position  */
128 #define SERCOM_I2CS_CTRLA_RUNSTDBY_Pos        _UINT32_(7)                                          /* (SERCOM_I2CS_CTRLA) Run during Standby Position */
129 #define SERCOM_I2CS_CTRLA_RUNSTDBY_Msk        (_UINT32_(0x1) << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos)    /* (SERCOM_I2CS_CTRLA) Run during Standby Mask */
130 #define SERCOM_I2CS_CTRLA_RUNSTDBY(value)     (SERCOM_I2CS_CTRLA_RUNSTDBY_Msk & (_UINT32_(value) << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos)) /* Assigment of value for RUNSTDBY in the SERCOM_I2CS_CTRLA register */
131 #define SERCOM_I2CS_CTRLA_PINOUT_Pos          _UINT32_(16)                                         /* (SERCOM_I2CS_CTRLA) Pin Usage Position */
132 #define SERCOM_I2CS_CTRLA_PINOUT_Msk          (_UINT32_(0x1) << SERCOM_I2CS_CTRLA_PINOUT_Pos)      /* (SERCOM_I2CS_CTRLA) Pin Usage Mask */
133 #define SERCOM_I2CS_CTRLA_PINOUT(value)       (SERCOM_I2CS_CTRLA_PINOUT_Msk & (_UINT32_(value) << SERCOM_I2CS_CTRLA_PINOUT_Pos)) /* Assigment of value for PINOUT in the SERCOM_I2CS_CTRLA register */
134 #define SERCOM_I2CS_CTRLA_SDAHOLD_Pos         _UINT32_(20)                                         /* (SERCOM_I2CS_CTRLA) SDA Hold Time Position */
135 #define SERCOM_I2CS_CTRLA_SDAHOLD_Msk         (_UINT32_(0x3) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)     /* (SERCOM_I2CS_CTRLA) SDA Hold Time Mask */
136 #define SERCOM_I2CS_CTRLA_SDAHOLD(value)      (SERCOM_I2CS_CTRLA_SDAHOLD_Msk & (_UINT32_(value) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)) /* Assigment of value for SDAHOLD in the SERCOM_I2CS_CTRLA register */
137 #define   SERCOM_I2CS_CTRLA_SDAHOLD_DISABLE_Val _UINT32_(0x0)                                        /* (SERCOM_I2CS_CTRLA) Disabled  */
138 #define   SERCOM_I2CS_CTRLA_SDAHOLD_75NS_Val  _UINT32_(0x1)                                        /* (SERCOM_I2CS_CTRLA) 50-100ns hold time  */
139 #define   SERCOM_I2CS_CTRLA_SDAHOLD_450NS_Val _UINT32_(0x2)                                        /* (SERCOM_I2CS_CTRLA) 300-600ns hold time  */
140 #define   SERCOM_I2CS_CTRLA_SDAHOLD_600NS_Val _UINT32_(0x3)                                        /* (SERCOM_I2CS_CTRLA) 400-800ns hold time  */
141 #define SERCOM_I2CS_CTRLA_SDAHOLD_DISABLE     (SERCOM_I2CS_CTRLA_SDAHOLD_DISABLE_Val << SERCOM_I2CS_CTRLA_SDAHOLD_Pos) /* (SERCOM_I2CS_CTRLA) Disabled Position  */
142 #define SERCOM_I2CS_CTRLA_SDAHOLD_75NS        (SERCOM_I2CS_CTRLA_SDAHOLD_75NS_Val << SERCOM_I2CS_CTRLA_SDAHOLD_Pos) /* (SERCOM_I2CS_CTRLA) 50-100ns hold time Position  */
143 #define SERCOM_I2CS_CTRLA_SDAHOLD_450NS       (SERCOM_I2CS_CTRLA_SDAHOLD_450NS_Val << SERCOM_I2CS_CTRLA_SDAHOLD_Pos) /* (SERCOM_I2CS_CTRLA) 300-600ns hold time Position  */
144 #define SERCOM_I2CS_CTRLA_SDAHOLD_600NS       (SERCOM_I2CS_CTRLA_SDAHOLD_600NS_Val << SERCOM_I2CS_CTRLA_SDAHOLD_Pos) /* (SERCOM_I2CS_CTRLA) 400-800ns hold time Position  */
145 #define SERCOM_I2CS_CTRLA_SEXTTOEN_Pos        _UINT32_(23)                                         /* (SERCOM_I2CS_CTRLA) Slave SCL Low Extend Timeout Position */
146 #define SERCOM_I2CS_CTRLA_SEXTTOEN_Msk        (_UINT32_(0x1) << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos)    /* (SERCOM_I2CS_CTRLA) Slave SCL Low Extend Timeout Mask */
147 #define SERCOM_I2CS_CTRLA_SEXTTOEN(value)     (SERCOM_I2CS_CTRLA_SEXTTOEN_Msk & (_UINT32_(value) << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos)) /* Assigment of value for SEXTTOEN in the SERCOM_I2CS_CTRLA register */
148 #define SERCOM_I2CS_CTRLA_SPEED_Pos           _UINT32_(24)                                         /* (SERCOM_I2CS_CTRLA) Transfer Speed Position */
149 #define SERCOM_I2CS_CTRLA_SPEED_Msk           (_UINT32_(0x3) << SERCOM_I2CS_CTRLA_SPEED_Pos)       /* (SERCOM_I2CS_CTRLA) Transfer Speed Mask */
150 #define SERCOM_I2CS_CTRLA_SPEED(value)        (SERCOM_I2CS_CTRLA_SPEED_Msk & (_UINT32_(value) << SERCOM_I2CS_CTRLA_SPEED_Pos)) /* Assigment of value for SPEED in the SERCOM_I2CS_CTRLA register */
151 #define   SERCOM_I2CS_CTRLA_SPEED_STANDARD_AND_FAST_MODE_Val _UINT32_(0x0)                                        /* (SERCOM_I2CS_CTRLA) Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz   */
152 #define   SERCOM_I2CS_CTRLA_SPEED_FASTPLUS_MODE_Val _UINT32_(0x1)                                        /* (SERCOM_I2CS_CTRLA) Fast-mode Plus Upto 1MHz  */
153 #define   SERCOM_I2CS_CTRLA_SPEED_HIGH_SPEED_MODE_Val _UINT32_(0x2)                                        /* (SERCOM_I2CS_CTRLA) High-speed mode Upto 3.4MHz  */
154 #define SERCOM_I2CS_CTRLA_SPEED_STANDARD_AND_FAST_MODE (SERCOM_I2CS_CTRLA_SPEED_STANDARD_AND_FAST_MODE_Val << SERCOM_I2CS_CTRLA_SPEED_Pos) /* (SERCOM_I2CS_CTRLA) Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz  Position  */
155 #define SERCOM_I2CS_CTRLA_SPEED_FASTPLUS_MODE (SERCOM_I2CS_CTRLA_SPEED_FASTPLUS_MODE_Val << SERCOM_I2CS_CTRLA_SPEED_Pos) /* (SERCOM_I2CS_CTRLA) Fast-mode Plus Upto 1MHz Position  */
156 #define SERCOM_I2CS_CTRLA_SPEED_HIGH_SPEED_MODE (SERCOM_I2CS_CTRLA_SPEED_HIGH_SPEED_MODE_Val << SERCOM_I2CS_CTRLA_SPEED_Pos) /* (SERCOM_I2CS_CTRLA) High-speed mode Upto 3.4MHz Position  */
157 #define SERCOM_I2CS_CTRLA_SCLSM_Pos           _UINT32_(27)                                         /* (SERCOM_I2CS_CTRLA) SCL Clock Stretch Mode Position */
158 #define SERCOM_I2CS_CTRLA_SCLSM_Msk           (_UINT32_(0x1) << SERCOM_I2CS_CTRLA_SCLSM_Pos)       /* (SERCOM_I2CS_CTRLA) SCL Clock Stretch Mode Mask */
159 #define SERCOM_I2CS_CTRLA_SCLSM(value)        (SERCOM_I2CS_CTRLA_SCLSM_Msk & (_UINT32_(value) << SERCOM_I2CS_CTRLA_SCLSM_Pos)) /* Assigment of value for SCLSM in the SERCOM_I2CS_CTRLA register */
160 #define SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos       _UINT32_(30)                                         /* (SERCOM_I2CS_CTRLA) SCL Low Timeout Enable Position */
161 #define SERCOM_I2CS_CTRLA_LOWTOUTEN_Msk       (_UINT32_(0x1) << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos)   /* (SERCOM_I2CS_CTRLA) SCL Low Timeout Enable Mask */
162 #define SERCOM_I2CS_CTRLA_LOWTOUTEN(value)    (SERCOM_I2CS_CTRLA_LOWTOUTEN_Msk & (_UINT32_(value) << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos)) /* Assigment of value for LOWTOUTEN in the SERCOM_I2CS_CTRLA register */
163 #define SERCOM_I2CS_CTRLA_Msk                 _UINT32_(0x4BB1009F)                                 /* (SERCOM_I2CS_CTRLA) Register Mask  */
164 
165 
166 /* -------- SERCOM_SPIM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPIM Control A -------- */
167 #define SERCOM_SPIM_CTRLA_RESETVALUE          _UINT32_(0x00)                                       /*  (SERCOM_SPIM_CTRLA) SPIM Control A  Reset Value */
168 
169 #define SERCOM_SPIM_CTRLA_SWRST_Pos           _UINT32_(0)                                          /* (SERCOM_SPIM_CTRLA) Software Reset Position */
170 #define SERCOM_SPIM_CTRLA_SWRST_Msk           (_UINT32_(0x1) << SERCOM_SPIM_CTRLA_SWRST_Pos)       /* (SERCOM_SPIM_CTRLA) Software Reset Mask */
171 #define SERCOM_SPIM_CTRLA_SWRST(value)        (SERCOM_SPIM_CTRLA_SWRST_Msk & (_UINT32_(value) << SERCOM_SPIM_CTRLA_SWRST_Pos)) /* Assigment of value for SWRST in the SERCOM_SPIM_CTRLA register */
172 #define SERCOM_SPIM_CTRLA_ENABLE_Pos          _UINT32_(1)                                          /* (SERCOM_SPIM_CTRLA) Enable Position */
173 #define SERCOM_SPIM_CTRLA_ENABLE_Msk          (_UINT32_(0x1) << SERCOM_SPIM_CTRLA_ENABLE_Pos)      /* (SERCOM_SPIM_CTRLA) Enable Mask */
174 #define SERCOM_SPIM_CTRLA_ENABLE(value)       (SERCOM_SPIM_CTRLA_ENABLE_Msk & (_UINT32_(value) << SERCOM_SPIM_CTRLA_ENABLE_Pos)) /* Assigment of value for ENABLE in the SERCOM_SPIM_CTRLA register */
175 #define SERCOM_SPIM_CTRLA_MODE_Pos            _UINT32_(2)                                          /* (SERCOM_SPIM_CTRLA) Operating Mode Position */
176 #define SERCOM_SPIM_CTRLA_MODE_Msk            (_UINT32_(0x7) << SERCOM_SPIM_CTRLA_MODE_Pos)        /* (SERCOM_SPIM_CTRLA) Operating Mode Mask */
177 #define SERCOM_SPIM_CTRLA_MODE(value)         (SERCOM_SPIM_CTRLA_MODE_Msk & (_UINT32_(value) << SERCOM_SPIM_CTRLA_MODE_Pos)) /* Assigment of value for MODE in the SERCOM_SPIM_CTRLA register */
178 #define   SERCOM_SPIM_CTRLA_MODE_USART_EXT_CLK_Val _UINT32_(0x0)                                        /* (SERCOM_SPIM_CTRLA) USART with external clock  */
179 #define   SERCOM_SPIM_CTRLA_MODE_USART_INT_CLK_Val _UINT32_(0x1)                                        /* (SERCOM_SPIM_CTRLA) USART with internal clock  */
180 #define   SERCOM_SPIM_CTRLA_MODE_SPI_SLAVE_Val _UINT32_(0x2)                                        /* (SERCOM_SPIM_CTRLA) SPI in slave operation  */
181 #define   SERCOM_SPIM_CTRLA_MODE_SPI_MASTER_Val _UINT32_(0x3)                                        /* (SERCOM_SPIM_CTRLA) SPI in master operation  */
182 #define   SERCOM_SPIM_CTRLA_MODE_I2C_SLAVE_Val _UINT32_(0x4)                                        /* (SERCOM_SPIM_CTRLA) I2C slave operation  */
183 #define   SERCOM_SPIM_CTRLA_MODE_I2C_MASTER_Val _UINT32_(0x5)                                        /* (SERCOM_SPIM_CTRLA) I2C master operation  */
184 #define SERCOM_SPIM_CTRLA_MODE_USART_EXT_CLK  (SERCOM_SPIM_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_SPIM_CTRLA_MODE_Pos) /* (SERCOM_SPIM_CTRLA) USART with external clock Position  */
185 #define SERCOM_SPIM_CTRLA_MODE_USART_INT_CLK  (SERCOM_SPIM_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_SPIM_CTRLA_MODE_Pos) /* (SERCOM_SPIM_CTRLA) USART with internal clock Position  */
186 #define SERCOM_SPIM_CTRLA_MODE_SPI_SLAVE      (SERCOM_SPIM_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_SPIM_CTRLA_MODE_Pos) /* (SERCOM_SPIM_CTRLA) SPI in slave operation Position  */
187 #define SERCOM_SPIM_CTRLA_MODE_SPI_MASTER     (SERCOM_SPIM_CTRLA_MODE_SPI_MASTER_Val << SERCOM_SPIM_CTRLA_MODE_Pos) /* (SERCOM_SPIM_CTRLA) SPI in master operation Position  */
188 #define SERCOM_SPIM_CTRLA_MODE_I2C_SLAVE      (SERCOM_SPIM_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_SPIM_CTRLA_MODE_Pos) /* (SERCOM_SPIM_CTRLA) I2C slave operation Position  */
189 #define SERCOM_SPIM_CTRLA_MODE_I2C_MASTER     (SERCOM_SPIM_CTRLA_MODE_I2C_MASTER_Val << SERCOM_SPIM_CTRLA_MODE_Pos) /* (SERCOM_SPIM_CTRLA) I2C master operation Position  */
190 #define SERCOM_SPIM_CTRLA_RUNSTDBY_Pos        _UINT32_(7)                                          /* (SERCOM_SPIM_CTRLA) Run during Standby Position */
191 #define SERCOM_SPIM_CTRLA_RUNSTDBY_Msk        (_UINT32_(0x1) << SERCOM_SPIM_CTRLA_RUNSTDBY_Pos)    /* (SERCOM_SPIM_CTRLA) Run during Standby Mask */
192 #define SERCOM_SPIM_CTRLA_RUNSTDBY(value)     (SERCOM_SPIM_CTRLA_RUNSTDBY_Msk & (_UINT32_(value) << SERCOM_SPIM_CTRLA_RUNSTDBY_Pos)) /* Assigment of value for RUNSTDBY in the SERCOM_SPIM_CTRLA register */
193 #define SERCOM_SPIM_CTRLA_IBON_Pos            _UINT32_(8)                                          /* (SERCOM_SPIM_CTRLA) Immediate Buffer Overflow Notification Position */
194 #define SERCOM_SPIM_CTRLA_IBON_Msk            (_UINT32_(0x1) << SERCOM_SPIM_CTRLA_IBON_Pos)        /* (SERCOM_SPIM_CTRLA) Immediate Buffer Overflow Notification Mask */
195 #define SERCOM_SPIM_CTRLA_IBON(value)         (SERCOM_SPIM_CTRLA_IBON_Msk & (_UINT32_(value) << SERCOM_SPIM_CTRLA_IBON_Pos)) /* Assigment of value for IBON in the SERCOM_SPIM_CTRLA register */
196 #define SERCOM_SPIM_CTRLA_DOPO_Pos            _UINT32_(16)                                         /* (SERCOM_SPIM_CTRLA) Data Out Pinout Position */
197 #define SERCOM_SPIM_CTRLA_DOPO_Msk            (_UINT32_(0x3) << SERCOM_SPIM_CTRLA_DOPO_Pos)        /* (SERCOM_SPIM_CTRLA) Data Out Pinout Mask */
198 #define SERCOM_SPIM_CTRLA_DOPO(value)         (SERCOM_SPIM_CTRLA_DOPO_Msk & (_UINT32_(value) << SERCOM_SPIM_CTRLA_DOPO_Pos)) /* Assigment of value for DOPO in the SERCOM_SPIM_CTRLA register */
199 #define   SERCOM_SPIM_CTRLA_DOPO_PAD0_Val     _UINT32_(0x0)                                        /* (SERCOM_SPIM_CTRLA) DO on PAD[0], SCK on PAD[1] and SS on PAD[2]  */
200 #define   SERCOM_SPIM_CTRLA_DOPO_PAD2_Val     _UINT32_(0x2)                                        /* (SERCOM_SPIM_CTRLA) DO on PAD[3], SCK on PAD[1] and SS on PAD[2]  */
201 #define SERCOM_SPIM_CTRLA_DOPO_PAD0           (SERCOM_SPIM_CTRLA_DOPO_PAD0_Val << SERCOM_SPIM_CTRLA_DOPO_Pos) /* (SERCOM_SPIM_CTRLA) DO on PAD[0], SCK on PAD[1] and SS on PAD[2] Position  */
202 #define SERCOM_SPIM_CTRLA_DOPO_PAD2           (SERCOM_SPIM_CTRLA_DOPO_PAD2_Val << SERCOM_SPIM_CTRLA_DOPO_Pos) /* (SERCOM_SPIM_CTRLA) DO on PAD[3], SCK on PAD[1] and SS on PAD[2] Position  */
203 #define SERCOM_SPIM_CTRLA_DIPO_Pos            _UINT32_(20)                                         /* (SERCOM_SPIM_CTRLA) Data In Pinout Position */
204 #define SERCOM_SPIM_CTRLA_DIPO_Msk            (_UINT32_(0x3) << SERCOM_SPIM_CTRLA_DIPO_Pos)        /* (SERCOM_SPIM_CTRLA) Data In Pinout Mask */
205 #define SERCOM_SPIM_CTRLA_DIPO(value)         (SERCOM_SPIM_CTRLA_DIPO_Msk & (_UINT32_(value) << SERCOM_SPIM_CTRLA_DIPO_Pos)) /* Assigment of value for DIPO in the SERCOM_SPIM_CTRLA register */
206 #define   SERCOM_SPIM_CTRLA_DIPO_PAD0_Val     _UINT32_(0x0)                                        /* (SERCOM_SPIM_CTRLA) SERCOM PAD[0] is used as data input  */
207 #define   SERCOM_SPIM_CTRLA_DIPO_PAD1_Val     _UINT32_(0x1)                                        /* (SERCOM_SPIM_CTRLA) SERCOM PAD[1] is used as data input  */
208 #define   SERCOM_SPIM_CTRLA_DIPO_PAD2_Val     _UINT32_(0x2)                                        /* (SERCOM_SPIM_CTRLA) SERCOM PAD[2] is used as data input  */
209 #define   SERCOM_SPIM_CTRLA_DIPO_PAD3_Val     _UINT32_(0x3)                                        /* (SERCOM_SPIM_CTRLA) SERCOM PAD[3] is used as data input  */
210 #define SERCOM_SPIM_CTRLA_DIPO_PAD0           (SERCOM_SPIM_CTRLA_DIPO_PAD0_Val << SERCOM_SPIM_CTRLA_DIPO_Pos) /* (SERCOM_SPIM_CTRLA) SERCOM PAD[0] is used as data input Position  */
211 #define SERCOM_SPIM_CTRLA_DIPO_PAD1           (SERCOM_SPIM_CTRLA_DIPO_PAD1_Val << SERCOM_SPIM_CTRLA_DIPO_Pos) /* (SERCOM_SPIM_CTRLA) SERCOM PAD[1] is used as data input Position  */
212 #define SERCOM_SPIM_CTRLA_DIPO_PAD2           (SERCOM_SPIM_CTRLA_DIPO_PAD2_Val << SERCOM_SPIM_CTRLA_DIPO_Pos) /* (SERCOM_SPIM_CTRLA) SERCOM PAD[2] is used as data input Position  */
213 #define SERCOM_SPIM_CTRLA_DIPO_PAD3           (SERCOM_SPIM_CTRLA_DIPO_PAD3_Val << SERCOM_SPIM_CTRLA_DIPO_Pos) /* (SERCOM_SPIM_CTRLA) SERCOM PAD[3] is used as data input Position  */
214 #define SERCOM_SPIM_CTRLA_FORM_Pos            _UINT32_(24)                                         /* (SERCOM_SPIM_CTRLA) Frame Format Position */
215 #define SERCOM_SPIM_CTRLA_FORM_Msk            (_UINT32_(0xF) << SERCOM_SPIM_CTRLA_FORM_Pos)        /* (SERCOM_SPIM_CTRLA) Frame Format Mask */
216 #define SERCOM_SPIM_CTRLA_FORM(value)         (SERCOM_SPIM_CTRLA_FORM_Msk & (_UINT32_(value) << SERCOM_SPIM_CTRLA_FORM_Pos)) /* Assigment of value for FORM in the SERCOM_SPIM_CTRLA register */
217 #define   SERCOM_SPIM_CTRLA_FORM_SPI_FRAME_Val _UINT32_(0x0)                                        /* (SERCOM_SPIM_CTRLA) SPI Frame  */
218 #define   SERCOM_SPIM_CTRLA_FORM_SPI_FRAME_WITH_ADDR_Val _UINT32_(0x2)                                        /* (SERCOM_SPIM_CTRLA) SPI Frame with Addr  */
219 #define SERCOM_SPIM_CTRLA_FORM_SPI_FRAME      (SERCOM_SPIM_CTRLA_FORM_SPI_FRAME_Val << SERCOM_SPIM_CTRLA_FORM_Pos) /* (SERCOM_SPIM_CTRLA) SPI Frame Position  */
220 #define SERCOM_SPIM_CTRLA_FORM_SPI_FRAME_WITH_ADDR (SERCOM_SPIM_CTRLA_FORM_SPI_FRAME_WITH_ADDR_Val << SERCOM_SPIM_CTRLA_FORM_Pos) /* (SERCOM_SPIM_CTRLA) SPI Frame with Addr Position  */
221 #define SERCOM_SPIM_CTRLA_CPHA_Pos            _UINT32_(28)                                         /* (SERCOM_SPIM_CTRLA) Clock Phase Position */
222 #define SERCOM_SPIM_CTRLA_CPHA_Msk            (_UINT32_(0x1) << SERCOM_SPIM_CTRLA_CPHA_Pos)        /* (SERCOM_SPIM_CTRLA) Clock Phase Mask */
223 #define SERCOM_SPIM_CTRLA_CPHA(value)         (SERCOM_SPIM_CTRLA_CPHA_Msk & (_UINT32_(value) << SERCOM_SPIM_CTRLA_CPHA_Pos)) /* Assigment of value for CPHA in the SERCOM_SPIM_CTRLA register */
224 #define   SERCOM_SPIM_CTRLA_CPHA_LEADING_EDGE_Val _UINT32_(0x0)                                        /* (SERCOM_SPIM_CTRLA) The data is sampled on a leading SCK edge and changed on a trailing SCK edge  */
225 #define   SERCOM_SPIM_CTRLA_CPHA_TRAILING_EDGE_Val _UINT32_(0x1)                                        /* (SERCOM_SPIM_CTRLA) The data is sampled on a trailing SCK edge and changed on a leading SCK edge  */
226 #define SERCOM_SPIM_CTRLA_CPHA_LEADING_EDGE   (SERCOM_SPIM_CTRLA_CPHA_LEADING_EDGE_Val << SERCOM_SPIM_CTRLA_CPHA_Pos) /* (SERCOM_SPIM_CTRLA) The data is sampled on a leading SCK edge and changed on a trailing SCK edge Position  */
227 #define SERCOM_SPIM_CTRLA_CPHA_TRAILING_EDGE  (SERCOM_SPIM_CTRLA_CPHA_TRAILING_EDGE_Val << SERCOM_SPIM_CTRLA_CPHA_Pos) /* (SERCOM_SPIM_CTRLA) The data is sampled on a trailing SCK edge and changed on a leading SCK edge Position  */
228 #define SERCOM_SPIM_CTRLA_CPOL_Pos            _UINT32_(29)                                         /* (SERCOM_SPIM_CTRLA) Clock Polarity Position */
229 #define SERCOM_SPIM_CTRLA_CPOL_Msk            (_UINT32_(0x1) << SERCOM_SPIM_CTRLA_CPOL_Pos)        /* (SERCOM_SPIM_CTRLA) Clock Polarity Mask */
230 #define SERCOM_SPIM_CTRLA_CPOL(value)         (SERCOM_SPIM_CTRLA_CPOL_Msk & (_UINT32_(value) << SERCOM_SPIM_CTRLA_CPOL_Pos)) /* Assigment of value for CPOL in the SERCOM_SPIM_CTRLA register */
231 #define   SERCOM_SPIM_CTRLA_CPOL_IDLE_LOW_Val _UINT32_(0x0)                                        /* (SERCOM_SPIM_CTRLA) SCK is low when idle  */
232 #define   SERCOM_SPIM_CTRLA_CPOL_IDLE_HIGH_Val _UINT32_(0x1)                                        /* (SERCOM_SPIM_CTRLA) SCK is high when idle  */
233 #define SERCOM_SPIM_CTRLA_CPOL_IDLE_LOW       (SERCOM_SPIM_CTRLA_CPOL_IDLE_LOW_Val << SERCOM_SPIM_CTRLA_CPOL_Pos) /* (SERCOM_SPIM_CTRLA) SCK is low when idle Position  */
234 #define SERCOM_SPIM_CTRLA_CPOL_IDLE_HIGH      (SERCOM_SPIM_CTRLA_CPOL_IDLE_HIGH_Val << SERCOM_SPIM_CTRLA_CPOL_Pos) /* (SERCOM_SPIM_CTRLA) SCK is high when idle Position  */
235 #define SERCOM_SPIM_CTRLA_DORD_Pos            _UINT32_(30)                                         /* (SERCOM_SPIM_CTRLA) Data Order Position */
236 #define SERCOM_SPIM_CTRLA_DORD_Msk            (_UINT32_(0x1) << SERCOM_SPIM_CTRLA_DORD_Pos)        /* (SERCOM_SPIM_CTRLA) Data Order Mask */
237 #define SERCOM_SPIM_CTRLA_DORD(value)         (SERCOM_SPIM_CTRLA_DORD_Msk & (_UINT32_(value) << SERCOM_SPIM_CTRLA_DORD_Pos)) /* Assigment of value for DORD in the SERCOM_SPIM_CTRLA register */
238 #define   SERCOM_SPIM_CTRLA_DORD_MSB_Val      _UINT32_(0x0)                                        /* (SERCOM_SPIM_CTRLA) MSB is transferred first  */
239 #define   SERCOM_SPIM_CTRLA_DORD_LSB_Val      _UINT32_(0x1)                                        /* (SERCOM_SPIM_CTRLA) LSB is transferred first  */
240 #define SERCOM_SPIM_CTRLA_DORD_MSB            (SERCOM_SPIM_CTRLA_DORD_MSB_Val << SERCOM_SPIM_CTRLA_DORD_Pos) /* (SERCOM_SPIM_CTRLA) MSB is transferred first Position  */
241 #define SERCOM_SPIM_CTRLA_DORD_LSB            (SERCOM_SPIM_CTRLA_DORD_LSB_Val << SERCOM_SPIM_CTRLA_DORD_Pos) /* (SERCOM_SPIM_CTRLA) LSB is transferred first Position  */
242 #define SERCOM_SPIM_CTRLA_Msk                 _UINT32_(0x7F33019F)                                 /* (SERCOM_SPIM_CTRLA) Register Mask  */
243 
244 
245 /* -------- SERCOM_SPIS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPIS Control A -------- */
246 #define SERCOM_SPIS_CTRLA_RESETVALUE          _UINT32_(0x00)                                       /*  (SERCOM_SPIS_CTRLA) SPIS Control A  Reset Value */
247 
248 #define SERCOM_SPIS_CTRLA_SWRST_Pos           _UINT32_(0)                                          /* (SERCOM_SPIS_CTRLA) Software Reset Position */
249 #define SERCOM_SPIS_CTRLA_SWRST_Msk           (_UINT32_(0x1) << SERCOM_SPIS_CTRLA_SWRST_Pos)       /* (SERCOM_SPIS_CTRLA) Software Reset Mask */
250 #define SERCOM_SPIS_CTRLA_SWRST(value)        (SERCOM_SPIS_CTRLA_SWRST_Msk & (_UINT32_(value) << SERCOM_SPIS_CTRLA_SWRST_Pos)) /* Assigment of value for SWRST in the SERCOM_SPIS_CTRLA register */
251 #define SERCOM_SPIS_CTRLA_ENABLE_Pos          _UINT32_(1)                                          /* (SERCOM_SPIS_CTRLA) Enable Position */
252 #define SERCOM_SPIS_CTRLA_ENABLE_Msk          (_UINT32_(0x1) << SERCOM_SPIS_CTRLA_ENABLE_Pos)      /* (SERCOM_SPIS_CTRLA) Enable Mask */
253 #define SERCOM_SPIS_CTRLA_ENABLE(value)       (SERCOM_SPIS_CTRLA_ENABLE_Msk & (_UINT32_(value) << SERCOM_SPIS_CTRLA_ENABLE_Pos)) /* Assigment of value for ENABLE in the SERCOM_SPIS_CTRLA register */
254 #define SERCOM_SPIS_CTRLA_MODE_Pos            _UINT32_(2)                                          /* (SERCOM_SPIS_CTRLA) Operating Mode Position */
255 #define SERCOM_SPIS_CTRLA_MODE_Msk            (_UINT32_(0x7) << SERCOM_SPIS_CTRLA_MODE_Pos)        /* (SERCOM_SPIS_CTRLA) Operating Mode Mask */
256 #define SERCOM_SPIS_CTRLA_MODE(value)         (SERCOM_SPIS_CTRLA_MODE_Msk & (_UINT32_(value) << SERCOM_SPIS_CTRLA_MODE_Pos)) /* Assigment of value for MODE in the SERCOM_SPIS_CTRLA register */
257 #define   SERCOM_SPIS_CTRLA_MODE_USART_EXT_CLK_Val _UINT32_(0x0)                                        /* (SERCOM_SPIS_CTRLA) USART with external clock  */
258 #define   SERCOM_SPIS_CTRLA_MODE_USART_INT_CLK_Val _UINT32_(0x1)                                        /* (SERCOM_SPIS_CTRLA) USART with internal clock  */
259 #define   SERCOM_SPIS_CTRLA_MODE_SPI_SLAVE_Val _UINT32_(0x2)                                        /* (SERCOM_SPIS_CTRLA) SPI in slave operation  */
260 #define   SERCOM_SPIS_CTRLA_MODE_SPI_MASTER_Val _UINT32_(0x3)                                        /* (SERCOM_SPIS_CTRLA) SPI in master operation  */
261 #define   SERCOM_SPIS_CTRLA_MODE_I2C_SLAVE_Val _UINT32_(0x4)                                        /* (SERCOM_SPIS_CTRLA) I2C slave operation  */
262 #define   SERCOM_SPIS_CTRLA_MODE_I2C_MASTER_Val _UINT32_(0x5)                                        /* (SERCOM_SPIS_CTRLA) I2C master operation  */
263 #define SERCOM_SPIS_CTRLA_MODE_USART_EXT_CLK  (SERCOM_SPIS_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_SPIS_CTRLA_MODE_Pos) /* (SERCOM_SPIS_CTRLA) USART with external clock Position  */
264 #define SERCOM_SPIS_CTRLA_MODE_USART_INT_CLK  (SERCOM_SPIS_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_SPIS_CTRLA_MODE_Pos) /* (SERCOM_SPIS_CTRLA) USART with internal clock Position  */
265 #define SERCOM_SPIS_CTRLA_MODE_SPI_SLAVE      (SERCOM_SPIS_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_SPIS_CTRLA_MODE_Pos) /* (SERCOM_SPIS_CTRLA) SPI in slave operation Position  */
266 #define SERCOM_SPIS_CTRLA_MODE_SPI_MASTER     (SERCOM_SPIS_CTRLA_MODE_SPI_MASTER_Val << SERCOM_SPIS_CTRLA_MODE_Pos) /* (SERCOM_SPIS_CTRLA) SPI in master operation Position  */
267 #define SERCOM_SPIS_CTRLA_MODE_I2C_SLAVE      (SERCOM_SPIS_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_SPIS_CTRLA_MODE_Pos) /* (SERCOM_SPIS_CTRLA) I2C slave operation Position  */
268 #define SERCOM_SPIS_CTRLA_MODE_I2C_MASTER     (SERCOM_SPIS_CTRLA_MODE_I2C_MASTER_Val << SERCOM_SPIS_CTRLA_MODE_Pos) /* (SERCOM_SPIS_CTRLA) I2C master operation Position  */
269 #define SERCOM_SPIS_CTRLA_RUNSTDBY_Pos        _UINT32_(7)                                          /* (SERCOM_SPIS_CTRLA) Run during Standby Position */
270 #define SERCOM_SPIS_CTRLA_RUNSTDBY_Msk        (_UINT32_(0x1) << SERCOM_SPIS_CTRLA_RUNSTDBY_Pos)    /* (SERCOM_SPIS_CTRLA) Run during Standby Mask */
271 #define SERCOM_SPIS_CTRLA_RUNSTDBY(value)     (SERCOM_SPIS_CTRLA_RUNSTDBY_Msk & (_UINT32_(value) << SERCOM_SPIS_CTRLA_RUNSTDBY_Pos)) /* Assigment of value for RUNSTDBY in the SERCOM_SPIS_CTRLA register */
272 #define SERCOM_SPIS_CTRLA_IBON_Pos            _UINT32_(8)                                          /* (SERCOM_SPIS_CTRLA) Immediate Buffer Overflow Notification Position */
273 #define SERCOM_SPIS_CTRLA_IBON_Msk            (_UINT32_(0x1) << SERCOM_SPIS_CTRLA_IBON_Pos)        /* (SERCOM_SPIS_CTRLA) Immediate Buffer Overflow Notification Mask */
274 #define SERCOM_SPIS_CTRLA_IBON(value)         (SERCOM_SPIS_CTRLA_IBON_Msk & (_UINT32_(value) << SERCOM_SPIS_CTRLA_IBON_Pos)) /* Assigment of value for IBON in the SERCOM_SPIS_CTRLA register */
275 #define SERCOM_SPIS_CTRLA_DOPO_Pos            _UINT32_(16)                                         /* (SERCOM_SPIS_CTRLA) Data Out Pinout Position */
276 #define SERCOM_SPIS_CTRLA_DOPO_Msk            (_UINT32_(0x3) << SERCOM_SPIS_CTRLA_DOPO_Pos)        /* (SERCOM_SPIS_CTRLA) Data Out Pinout Mask */
277 #define SERCOM_SPIS_CTRLA_DOPO(value)         (SERCOM_SPIS_CTRLA_DOPO_Msk & (_UINT32_(value) << SERCOM_SPIS_CTRLA_DOPO_Pos)) /* Assigment of value for DOPO in the SERCOM_SPIS_CTRLA register */
278 #define   SERCOM_SPIS_CTRLA_DOPO_PAD0_Val     _UINT32_(0x0)                                        /* (SERCOM_SPIS_CTRLA) DO on PAD[0], SCK on PAD[1] and SS on PAD[2]  */
279 #define   SERCOM_SPIS_CTRLA_DOPO_PAD2_Val     _UINT32_(0x2)                                        /* (SERCOM_SPIS_CTRLA) DO on PAD[3], SCK on PAD[1] and SS on PAD[2]  */
280 #define SERCOM_SPIS_CTRLA_DOPO_PAD0           (SERCOM_SPIS_CTRLA_DOPO_PAD0_Val << SERCOM_SPIS_CTRLA_DOPO_Pos) /* (SERCOM_SPIS_CTRLA) DO on PAD[0], SCK on PAD[1] and SS on PAD[2] Position  */
281 #define SERCOM_SPIS_CTRLA_DOPO_PAD2           (SERCOM_SPIS_CTRLA_DOPO_PAD2_Val << SERCOM_SPIS_CTRLA_DOPO_Pos) /* (SERCOM_SPIS_CTRLA) DO on PAD[3], SCK on PAD[1] and SS on PAD[2] Position  */
282 #define SERCOM_SPIS_CTRLA_DIPO_Pos            _UINT32_(20)                                         /* (SERCOM_SPIS_CTRLA) Data In Pinout Position */
283 #define SERCOM_SPIS_CTRLA_DIPO_Msk            (_UINT32_(0x3) << SERCOM_SPIS_CTRLA_DIPO_Pos)        /* (SERCOM_SPIS_CTRLA) Data In Pinout Mask */
284 #define SERCOM_SPIS_CTRLA_DIPO(value)         (SERCOM_SPIS_CTRLA_DIPO_Msk & (_UINT32_(value) << SERCOM_SPIS_CTRLA_DIPO_Pos)) /* Assigment of value for DIPO in the SERCOM_SPIS_CTRLA register */
285 #define   SERCOM_SPIS_CTRLA_DIPO_PAD0_Val     _UINT32_(0x0)                                        /* (SERCOM_SPIS_CTRLA) SERCOM PAD[0] is used as data input  */
286 #define   SERCOM_SPIS_CTRLA_DIPO_PAD1_Val     _UINT32_(0x1)                                        /* (SERCOM_SPIS_CTRLA) SERCOM PAD[1] is used as data input  */
287 #define   SERCOM_SPIS_CTRLA_DIPO_PAD2_Val     _UINT32_(0x2)                                        /* (SERCOM_SPIS_CTRLA) SERCOM PAD[2] is used as data input  */
288 #define   SERCOM_SPIS_CTRLA_DIPO_PAD3_Val     _UINT32_(0x3)                                        /* (SERCOM_SPIS_CTRLA) SERCOM PAD[3] is used as data input  */
289 #define SERCOM_SPIS_CTRLA_DIPO_PAD0           (SERCOM_SPIS_CTRLA_DIPO_PAD0_Val << SERCOM_SPIS_CTRLA_DIPO_Pos) /* (SERCOM_SPIS_CTRLA) SERCOM PAD[0] is used as data input Position  */
290 #define SERCOM_SPIS_CTRLA_DIPO_PAD1           (SERCOM_SPIS_CTRLA_DIPO_PAD1_Val << SERCOM_SPIS_CTRLA_DIPO_Pos) /* (SERCOM_SPIS_CTRLA) SERCOM PAD[1] is used as data input Position  */
291 #define SERCOM_SPIS_CTRLA_DIPO_PAD2           (SERCOM_SPIS_CTRLA_DIPO_PAD2_Val << SERCOM_SPIS_CTRLA_DIPO_Pos) /* (SERCOM_SPIS_CTRLA) SERCOM PAD[2] is used as data input Position  */
292 #define SERCOM_SPIS_CTRLA_DIPO_PAD3           (SERCOM_SPIS_CTRLA_DIPO_PAD3_Val << SERCOM_SPIS_CTRLA_DIPO_Pos) /* (SERCOM_SPIS_CTRLA) SERCOM PAD[3] is used as data input Position  */
293 #define SERCOM_SPIS_CTRLA_FORM_Pos            _UINT32_(24)                                         /* (SERCOM_SPIS_CTRLA) Frame Format Position */
294 #define SERCOM_SPIS_CTRLA_FORM_Msk            (_UINT32_(0xF) << SERCOM_SPIS_CTRLA_FORM_Pos)        /* (SERCOM_SPIS_CTRLA) Frame Format Mask */
295 #define SERCOM_SPIS_CTRLA_FORM(value)         (SERCOM_SPIS_CTRLA_FORM_Msk & (_UINT32_(value) << SERCOM_SPIS_CTRLA_FORM_Pos)) /* Assigment of value for FORM in the SERCOM_SPIS_CTRLA register */
296 #define   SERCOM_SPIS_CTRLA_FORM_SPI_FRAME_Val _UINT32_(0x0)                                        /* (SERCOM_SPIS_CTRLA) SPI Frame  */
297 #define   SERCOM_SPIS_CTRLA_FORM_SPI_FRAME_WITH_ADDR_Val _UINT32_(0x2)                                        /* (SERCOM_SPIS_CTRLA) SPI Frame with Addr  */
298 #define SERCOM_SPIS_CTRLA_FORM_SPI_FRAME      (SERCOM_SPIS_CTRLA_FORM_SPI_FRAME_Val << SERCOM_SPIS_CTRLA_FORM_Pos) /* (SERCOM_SPIS_CTRLA) SPI Frame Position  */
299 #define SERCOM_SPIS_CTRLA_FORM_SPI_FRAME_WITH_ADDR (SERCOM_SPIS_CTRLA_FORM_SPI_FRAME_WITH_ADDR_Val << SERCOM_SPIS_CTRLA_FORM_Pos) /* (SERCOM_SPIS_CTRLA) SPI Frame with Addr Position  */
300 #define SERCOM_SPIS_CTRLA_CPHA_Pos            _UINT32_(28)                                         /* (SERCOM_SPIS_CTRLA) Clock Phase Position */
301 #define SERCOM_SPIS_CTRLA_CPHA_Msk            (_UINT32_(0x1) << SERCOM_SPIS_CTRLA_CPHA_Pos)        /* (SERCOM_SPIS_CTRLA) Clock Phase Mask */
302 #define SERCOM_SPIS_CTRLA_CPHA(value)         (SERCOM_SPIS_CTRLA_CPHA_Msk & (_UINT32_(value) << SERCOM_SPIS_CTRLA_CPHA_Pos)) /* Assigment of value for CPHA in the SERCOM_SPIS_CTRLA register */
303 #define   SERCOM_SPIS_CTRLA_CPHA_LEADING_EDGE_Val _UINT32_(0x0)                                        /* (SERCOM_SPIS_CTRLA) The data is sampled on a leading SCK edge and changed on a trailing SCK edge  */
304 #define   SERCOM_SPIS_CTRLA_CPHA_TRAILING_EDGE_Val _UINT32_(0x1)                                        /* (SERCOM_SPIS_CTRLA) The data is sampled on a trailing SCK edge and changed on a leading SCK edge  */
305 #define SERCOM_SPIS_CTRLA_CPHA_LEADING_EDGE   (SERCOM_SPIS_CTRLA_CPHA_LEADING_EDGE_Val << SERCOM_SPIS_CTRLA_CPHA_Pos) /* (SERCOM_SPIS_CTRLA) The data is sampled on a leading SCK edge and changed on a trailing SCK edge Position  */
306 #define SERCOM_SPIS_CTRLA_CPHA_TRAILING_EDGE  (SERCOM_SPIS_CTRLA_CPHA_TRAILING_EDGE_Val << SERCOM_SPIS_CTRLA_CPHA_Pos) /* (SERCOM_SPIS_CTRLA) The data is sampled on a trailing SCK edge and changed on a leading SCK edge Position  */
307 #define SERCOM_SPIS_CTRLA_CPOL_Pos            _UINT32_(29)                                         /* (SERCOM_SPIS_CTRLA) Clock Polarity Position */
308 #define SERCOM_SPIS_CTRLA_CPOL_Msk            (_UINT32_(0x1) << SERCOM_SPIS_CTRLA_CPOL_Pos)        /* (SERCOM_SPIS_CTRLA) Clock Polarity Mask */
309 #define SERCOM_SPIS_CTRLA_CPOL(value)         (SERCOM_SPIS_CTRLA_CPOL_Msk & (_UINT32_(value) << SERCOM_SPIS_CTRLA_CPOL_Pos)) /* Assigment of value for CPOL in the SERCOM_SPIS_CTRLA register */
310 #define   SERCOM_SPIS_CTRLA_CPOL_IDLE_LOW_Val _UINT32_(0x0)                                        /* (SERCOM_SPIS_CTRLA) SCK is low when idle  */
311 #define   SERCOM_SPIS_CTRLA_CPOL_IDLE_HIGH_Val _UINT32_(0x1)                                        /* (SERCOM_SPIS_CTRLA) SCK is high when idle  */
312 #define SERCOM_SPIS_CTRLA_CPOL_IDLE_LOW       (SERCOM_SPIS_CTRLA_CPOL_IDLE_LOW_Val << SERCOM_SPIS_CTRLA_CPOL_Pos) /* (SERCOM_SPIS_CTRLA) SCK is low when idle Position  */
313 #define SERCOM_SPIS_CTRLA_CPOL_IDLE_HIGH      (SERCOM_SPIS_CTRLA_CPOL_IDLE_HIGH_Val << SERCOM_SPIS_CTRLA_CPOL_Pos) /* (SERCOM_SPIS_CTRLA) SCK is high when idle Position  */
314 #define SERCOM_SPIS_CTRLA_DORD_Pos            _UINT32_(30)                                         /* (SERCOM_SPIS_CTRLA) Data Order Position */
315 #define SERCOM_SPIS_CTRLA_DORD_Msk            (_UINT32_(0x1) << SERCOM_SPIS_CTRLA_DORD_Pos)        /* (SERCOM_SPIS_CTRLA) Data Order Mask */
316 #define SERCOM_SPIS_CTRLA_DORD(value)         (SERCOM_SPIS_CTRLA_DORD_Msk & (_UINT32_(value) << SERCOM_SPIS_CTRLA_DORD_Pos)) /* Assigment of value for DORD in the SERCOM_SPIS_CTRLA register */
317 #define   SERCOM_SPIS_CTRLA_DORD_MSB_Val      _UINT32_(0x0)                                        /* (SERCOM_SPIS_CTRLA) MSB is transferred first  */
318 #define   SERCOM_SPIS_CTRLA_DORD_LSB_Val      _UINT32_(0x1)                                        /* (SERCOM_SPIS_CTRLA) LSB is transferred first  */
319 #define SERCOM_SPIS_CTRLA_DORD_MSB            (SERCOM_SPIS_CTRLA_DORD_MSB_Val << SERCOM_SPIS_CTRLA_DORD_Pos) /* (SERCOM_SPIS_CTRLA) MSB is transferred first Position  */
320 #define SERCOM_SPIS_CTRLA_DORD_LSB            (SERCOM_SPIS_CTRLA_DORD_LSB_Val << SERCOM_SPIS_CTRLA_DORD_Pos) /* (SERCOM_SPIS_CTRLA) LSB is transferred first Position  */
321 #define SERCOM_SPIS_CTRLA_Msk                 _UINT32_(0x7F33019F)                                 /* (SERCOM_SPIS_CTRLA) Register Mask  */
322 
323 
324 /* -------- SERCOM_USART_EXT_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART_EXT Control A -------- */
325 #define SERCOM_USART_EXT_CTRLA_RESETVALUE     _UINT32_(0x00)                                       /*  (SERCOM_USART_EXT_CTRLA) USART_EXT Control A  Reset Value */
326 
327 #define SERCOM_USART_EXT_CTRLA_SWRST_Pos      _UINT32_(0)                                          /* (SERCOM_USART_EXT_CTRLA) Software Reset Position */
328 #define SERCOM_USART_EXT_CTRLA_SWRST_Msk      (_UINT32_(0x1) << SERCOM_USART_EXT_CTRLA_SWRST_Pos)  /* (SERCOM_USART_EXT_CTRLA) Software Reset Mask */
329 #define SERCOM_USART_EXT_CTRLA_SWRST(value)   (SERCOM_USART_EXT_CTRLA_SWRST_Msk & (_UINT32_(value) << SERCOM_USART_EXT_CTRLA_SWRST_Pos)) /* Assigment of value for SWRST in the SERCOM_USART_EXT_CTRLA register */
330 #define SERCOM_USART_EXT_CTRLA_ENABLE_Pos     _UINT32_(1)                                          /* (SERCOM_USART_EXT_CTRLA) Enable Position */
331 #define SERCOM_USART_EXT_CTRLA_ENABLE_Msk     (_UINT32_(0x1) << SERCOM_USART_EXT_CTRLA_ENABLE_Pos) /* (SERCOM_USART_EXT_CTRLA) Enable Mask */
332 #define SERCOM_USART_EXT_CTRLA_ENABLE(value)  (SERCOM_USART_EXT_CTRLA_ENABLE_Msk & (_UINT32_(value) << SERCOM_USART_EXT_CTRLA_ENABLE_Pos)) /* Assigment of value for ENABLE in the SERCOM_USART_EXT_CTRLA register */
333 #define SERCOM_USART_EXT_CTRLA_MODE_Pos       _UINT32_(2)                                          /* (SERCOM_USART_EXT_CTRLA) Operating Mode Position */
334 #define SERCOM_USART_EXT_CTRLA_MODE_Msk       (_UINT32_(0x7) << SERCOM_USART_EXT_CTRLA_MODE_Pos)   /* (SERCOM_USART_EXT_CTRLA) Operating Mode Mask */
335 #define SERCOM_USART_EXT_CTRLA_MODE(value)    (SERCOM_USART_EXT_CTRLA_MODE_Msk & (_UINT32_(value) << SERCOM_USART_EXT_CTRLA_MODE_Pos)) /* Assigment of value for MODE in the SERCOM_USART_EXT_CTRLA register */
336 #define   SERCOM_USART_EXT_CTRLA_MODE_USART_EXT_CLK_Val _UINT32_(0x0)                                        /* (SERCOM_USART_EXT_CTRLA) USART with external clock  */
337 #define   SERCOM_USART_EXT_CTRLA_MODE_USART_INT_CLK_Val _UINT32_(0x1)                                        /* (SERCOM_USART_EXT_CTRLA) USART with internal clock  */
338 #define   SERCOM_USART_EXT_CTRLA_MODE_SPI_SLAVE_Val _UINT32_(0x2)                                        /* (SERCOM_USART_EXT_CTRLA) SPI in slave operation  */
339 #define   SERCOM_USART_EXT_CTRLA_MODE_SPI_MASTER_Val _UINT32_(0x3)                                        /* (SERCOM_USART_EXT_CTRLA) SPI in master operation  */
340 #define   SERCOM_USART_EXT_CTRLA_MODE_I2C_SLAVE_Val _UINT32_(0x4)                                        /* (SERCOM_USART_EXT_CTRLA) I2C slave operation  */
341 #define   SERCOM_USART_EXT_CTRLA_MODE_I2C_MASTER_Val _UINT32_(0x5)                                        /* (SERCOM_USART_EXT_CTRLA) I2C master operation  */
342 #define SERCOM_USART_EXT_CTRLA_MODE_USART_EXT_CLK (SERCOM_USART_EXT_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_USART_EXT_CTRLA_MODE_Pos) /* (SERCOM_USART_EXT_CTRLA) USART with external clock Position  */
343 #define SERCOM_USART_EXT_CTRLA_MODE_USART_INT_CLK (SERCOM_USART_EXT_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_USART_EXT_CTRLA_MODE_Pos) /* (SERCOM_USART_EXT_CTRLA) USART with internal clock Position  */
344 #define SERCOM_USART_EXT_CTRLA_MODE_SPI_SLAVE (SERCOM_USART_EXT_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_USART_EXT_CTRLA_MODE_Pos) /* (SERCOM_USART_EXT_CTRLA) SPI in slave operation Position  */
345 #define SERCOM_USART_EXT_CTRLA_MODE_SPI_MASTER (SERCOM_USART_EXT_CTRLA_MODE_SPI_MASTER_Val << SERCOM_USART_EXT_CTRLA_MODE_Pos) /* (SERCOM_USART_EXT_CTRLA) SPI in master operation Position  */
346 #define SERCOM_USART_EXT_CTRLA_MODE_I2C_SLAVE (SERCOM_USART_EXT_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_USART_EXT_CTRLA_MODE_Pos) /* (SERCOM_USART_EXT_CTRLA) I2C slave operation Position  */
347 #define SERCOM_USART_EXT_CTRLA_MODE_I2C_MASTER (SERCOM_USART_EXT_CTRLA_MODE_I2C_MASTER_Val << SERCOM_USART_EXT_CTRLA_MODE_Pos) /* (SERCOM_USART_EXT_CTRLA) I2C master operation Position  */
348 #define SERCOM_USART_EXT_CTRLA_RUNSTDBY_Pos   _UINT32_(7)                                          /* (SERCOM_USART_EXT_CTRLA) Run during Standby Position */
349 #define SERCOM_USART_EXT_CTRLA_RUNSTDBY_Msk   (_UINT32_(0x1) << SERCOM_USART_EXT_CTRLA_RUNSTDBY_Pos) /* (SERCOM_USART_EXT_CTRLA) Run during Standby Mask */
350 #define SERCOM_USART_EXT_CTRLA_RUNSTDBY(value) (SERCOM_USART_EXT_CTRLA_RUNSTDBY_Msk & (_UINT32_(value) << SERCOM_USART_EXT_CTRLA_RUNSTDBY_Pos)) /* Assigment of value for RUNSTDBY in the SERCOM_USART_EXT_CTRLA register */
351 #define SERCOM_USART_EXT_CTRLA_IBON_Pos       _UINT32_(8)                                          /* (SERCOM_USART_EXT_CTRLA) Immediate Buffer Overflow Notification Position */
352 #define SERCOM_USART_EXT_CTRLA_IBON_Msk       (_UINT32_(0x1) << SERCOM_USART_EXT_CTRLA_IBON_Pos)   /* (SERCOM_USART_EXT_CTRLA) Immediate Buffer Overflow Notification Mask */
353 #define SERCOM_USART_EXT_CTRLA_IBON(value)    (SERCOM_USART_EXT_CTRLA_IBON_Msk & (_UINT32_(value) << SERCOM_USART_EXT_CTRLA_IBON_Pos)) /* Assigment of value for IBON in the SERCOM_USART_EXT_CTRLA register */
354 #define SERCOM_USART_EXT_CTRLA_TXINV_Pos      _UINT32_(9)                                          /* (SERCOM_USART_EXT_CTRLA) Transmit Data Invert Position */
355 #define SERCOM_USART_EXT_CTRLA_TXINV_Msk      (_UINT32_(0x1) << SERCOM_USART_EXT_CTRLA_TXINV_Pos)  /* (SERCOM_USART_EXT_CTRLA) Transmit Data Invert Mask */
356 #define SERCOM_USART_EXT_CTRLA_TXINV(value)   (SERCOM_USART_EXT_CTRLA_TXINV_Msk & (_UINT32_(value) << SERCOM_USART_EXT_CTRLA_TXINV_Pos)) /* Assigment of value for TXINV in the SERCOM_USART_EXT_CTRLA register */
357 #define SERCOM_USART_EXT_CTRLA_RXINV_Pos      _UINT32_(10)                                         /* (SERCOM_USART_EXT_CTRLA) Receive Data Invert Position */
358 #define SERCOM_USART_EXT_CTRLA_RXINV_Msk      (_UINT32_(0x1) << SERCOM_USART_EXT_CTRLA_RXINV_Pos)  /* (SERCOM_USART_EXT_CTRLA) Receive Data Invert Mask */
359 #define SERCOM_USART_EXT_CTRLA_RXINV(value)   (SERCOM_USART_EXT_CTRLA_RXINV_Msk & (_UINT32_(value) << SERCOM_USART_EXT_CTRLA_RXINV_Pos)) /* Assigment of value for RXINV in the SERCOM_USART_EXT_CTRLA register */
360 #define SERCOM_USART_EXT_CTRLA_SAMPR_Pos      _UINT32_(13)                                         /* (SERCOM_USART_EXT_CTRLA) Sample Position */
361 #define SERCOM_USART_EXT_CTRLA_SAMPR_Msk      (_UINT32_(0x7) << SERCOM_USART_EXT_CTRLA_SAMPR_Pos)  /* (SERCOM_USART_EXT_CTRLA) Sample Mask */
362 #define SERCOM_USART_EXT_CTRLA_SAMPR(value)   (SERCOM_USART_EXT_CTRLA_SAMPR_Msk & (_UINT32_(value) << SERCOM_USART_EXT_CTRLA_SAMPR_Pos)) /* Assigment of value for SAMPR in the SERCOM_USART_EXT_CTRLA register */
363 #define   SERCOM_USART_EXT_CTRLA_SAMPR_16X_ARITHMETIC_Val _UINT32_(0x0)                                        /* (SERCOM_USART_EXT_CTRLA) 16x over-sampling using arithmetic baudrate generation  */
364 #define   SERCOM_USART_EXT_CTRLA_SAMPR_16X_FRACTIONAL_Val _UINT32_(0x1)                                        /* (SERCOM_USART_EXT_CTRLA) 16x over-sampling using fractional baudrate generation  */
365 #define   SERCOM_USART_EXT_CTRLA_SAMPR_8X_ARITHMETIC_Val _UINT32_(0x2)                                        /* (SERCOM_USART_EXT_CTRLA) 8x over-sampling using arithmetic baudrate generation  */
366 #define   SERCOM_USART_EXT_CTRLA_SAMPR_8X_FRACTIONAL_Val _UINT32_(0x3)                                        /* (SERCOM_USART_EXT_CTRLA) 8x over-sampling using fractional baudrate generation  */
367 #define   SERCOM_USART_EXT_CTRLA_SAMPR_3X_ARITHMETIC_Val _UINT32_(0x4)                                        /* (SERCOM_USART_EXT_CTRLA) 3x over-sampling using arithmetic baudrate generation  */
368 #define SERCOM_USART_EXT_CTRLA_SAMPR_16X_ARITHMETIC (SERCOM_USART_EXT_CTRLA_SAMPR_16X_ARITHMETIC_Val << SERCOM_USART_EXT_CTRLA_SAMPR_Pos) /* (SERCOM_USART_EXT_CTRLA) 16x over-sampling using arithmetic baudrate generation Position  */
369 #define SERCOM_USART_EXT_CTRLA_SAMPR_16X_FRACTIONAL (SERCOM_USART_EXT_CTRLA_SAMPR_16X_FRACTIONAL_Val << SERCOM_USART_EXT_CTRLA_SAMPR_Pos) /* (SERCOM_USART_EXT_CTRLA) 16x over-sampling using fractional baudrate generation Position  */
370 #define SERCOM_USART_EXT_CTRLA_SAMPR_8X_ARITHMETIC (SERCOM_USART_EXT_CTRLA_SAMPR_8X_ARITHMETIC_Val << SERCOM_USART_EXT_CTRLA_SAMPR_Pos) /* (SERCOM_USART_EXT_CTRLA) 8x over-sampling using arithmetic baudrate generation Position  */
371 #define SERCOM_USART_EXT_CTRLA_SAMPR_8X_FRACTIONAL (SERCOM_USART_EXT_CTRLA_SAMPR_8X_FRACTIONAL_Val << SERCOM_USART_EXT_CTRLA_SAMPR_Pos) /* (SERCOM_USART_EXT_CTRLA) 8x over-sampling using fractional baudrate generation Position  */
372 #define SERCOM_USART_EXT_CTRLA_SAMPR_3X_ARITHMETIC (SERCOM_USART_EXT_CTRLA_SAMPR_3X_ARITHMETIC_Val << SERCOM_USART_EXT_CTRLA_SAMPR_Pos) /* (SERCOM_USART_EXT_CTRLA) 3x over-sampling using arithmetic baudrate generation Position  */
373 #define SERCOM_USART_EXT_CTRLA_TXPO_Pos       _UINT32_(16)                                         /* (SERCOM_USART_EXT_CTRLA) Transmit Data Pinout Position */
374 #define SERCOM_USART_EXT_CTRLA_TXPO_Msk       (_UINT32_(0x3) << SERCOM_USART_EXT_CTRLA_TXPO_Pos)   /* (SERCOM_USART_EXT_CTRLA) Transmit Data Pinout Mask */
375 #define SERCOM_USART_EXT_CTRLA_TXPO(value)    (SERCOM_USART_EXT_CTRLA_TXPO_Msk & (_UINT32_(value) << SERCOM_USART_EXT_CTRLA_TXPO_Pos)) /* Assigment of value for TXPO in the SERCOM_USART_EXT_CTRLA register */
376 #define   SERCOM_USART_EXT_CTRLA_TXPO_PAD0_Val _UINT32_(0x0)                                        /* (SERCOM_USART_EXT_CTRLA) PAD[0] = TxD; PAD[1] = XCK  */
377 #define   SERCOM_USART_EXT_CTRLA_TXPO_PAD2_Val _UINT32_(0x2)                                        /* (SERCOM_USART_EXT_CTRLA) PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS  */
378 #define   SERCOM_USART_EXT_CTRLA_TXPO_PAD3_Val _UINT32_(0x3)                                        /* (SERCOM_USART_EXT_CTRLA) PAD[0] = TxD; PAD[1] = XCK; PAD[2] = TE  */
379 #define SERCOM_USART_EXT_CTRLA_TXPO_PAD0      (SERCOM_USART_EXT_CTRLA_TXPO_PAD0_Val << SERCOM_USART_EXT_CTRLA_TXPO_Pos) /* (SERCOM_USART_EXT_CTRLA) PAD[0] = TxD; PAD[1] = XCK Position  */
380 #define SERCOM_USART_EXT_CTRLA_TXPO_PAD2      (SERCOM_USART_EXT_CTRLA_TXPO_PAD2_Val << SERCOM_USART_EXT_CTRLA_TXPO_Pos) /* (SERCOM_USART_EXT_CTRLA) PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS Position  */
381 #define SERCOM_USART_EXT_CTRLA_TXPO_PAD3      (SERCOM_USART_EXT_CTRLA_TXPO_PAD3_Val << SERCOM_USART_EXT_CTRLA_TXPO_Pos) /* (SERCOM_USART_EXT_CTRLA) PAD[0] = TxD; PAD[1] = XCK; PAD[2] = TE Position  */
382 #define SERCOM_USART_EXT_CTRLA_RXPO_Pos       _UINT32_(20)                                         /* (SERCOM_USART_EXT_CTRLA) Receive Data Pinout Position */
383 #define SERCOM_USART_EXT_CTRLA_RXPO_Msk       (_UINT32_(0x3) << SERCOM_USART_EXT_CTRLA_RXPO_Pos)   /* (SERCOM_USART_EXT_CTRLA) Receive Data Pinout Mask */
384 #define SERCOM_USART_EXT_CTRLA_RXPO(value)    (SERCOM_USART_EXT_CTRLA_RXPO_Msk & (_UINT32_(value) << SERCOM_USART_EXT_CTRLA_RXPO_Pos)) /* Assigment of value for RXPO in the SERCOM_USART_EXT_CTRLA register */
385 #define   SERCOM_USART_EXT_CTRLA_RXPO_PAD0_Val _UINT32_(0x0)                                        /* (SERCOM_USART_EXT_CTRLA) SERCOM PAD[0] is used for data reception  */
386 #define   SERCOM_USART_EXT_CTRLA_RXPO_PAD1_Val _UINT32_(0x1)                                        /* (SERCOM_USART_EXT_CTRLA) SERCOM PAD[1] is used for data reception  */
387 #define   SERCOM_USART_EXT_CTRLA_RXPO_PAD2_Val _UINT32_(0x2)                                        /* (SERCOM_USART_EXT_CTRLA) SERCOM PAD[2] is used for data reception  */
388 #define   SERCOM_USART_EXT_CTRLA_RXPO_PAD3_Val _UINT32_(0x3)                                        /* (SERCOM_USART_EXT_CTRLA) SERCOM PAD[3] is used for data reception  */
389 #define SERCOM_USART_EXT_CTRLA_RXPO_PAD0      (SERCOM_USART_EXT_CTRLA_RXPO_PAD0_Val << SERCOM_USART_EXT_CTRLA_RXPO_Pos) /* (SERCOM_USART_EXT_CTRLA) SERCOM PAD[0] is used for data reception Position  */
390 #define SERCOM_USART_EXT_CTRLA_RXPO_PAD1      (SERCOM_USART_EXT_CTRLA_RXPO_PAD1_Val << SERCOM_USART_EXT_CTRLA_RXPO_Pos) /* (SERCOM_USART_EXT_CTRLA) SERCOM PAD[1] is used for data reception Position  */
391 #define SERCOM_USART_EXT_CTRLA_RXPO_PAD2      (SERCOM_USART_EXT_CTRLA_RXPO_PAD2_Val << SERCOM_USART_EXT_CTRLA_RXPO_Pos) /* (SERCOM_USART_EXT_CTRLA) SERCOM PAD[2] is used for data reception Position  */
392 #define SERCOM_USART_EXT_CTRLA_RXPO_PAD3      (SERCOM_USART_EXT_CTRLA_RXPO_PAD3_Val << SERCOM_USART_EXT_CTRLA_RXPO_Pos) /* (SERCOM_USART_EXT_CTRLA) SERCOM PAD[3] is used for data reception Position  */
393 #define SERCOM_USART_EXT_CTRLA_SAMPA_Pos      _UINT32_(22)                                         /* (SERCOM_USART_EXT_CTRLA) Sample Adjustment Position */
394 #define SERCOM_USART_EXT_CTRLA_SAMPA_Msk      (_UINT32_(0x3) << SERCOM_USART_EXT_CTRLA_SAMPA_Pos)  /* (SERCOM_USART_EXT_CTRLA) Sample Adjustment Mask */
395 #define SERCOM_USART_EXT_CTRLA_SAMPA(value)   (SERCOM_USART_EXT_CTRLA_SAMPA_Msk & (_UINT32_(value) << SERCOM_USART_EXT_CTRLA_SAMPA_Pos)) /* Assigment of value for SAMPA in the SERCOM_USART_EXT_CTRLA register */
396 #define   SERCOM_USART_EXT_CTRLA_SAMPA_ADJ0_Val _UINT32_(0x0)                                        /* (SERCOM_USART_EXT_CTRLA) 16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-5  */
397 #define   SERCOM_USART_EXT_CTRLA_SAMPA_ADJ1_Val _UINT32_(0x1)                                        /* (SERCOM_USART_EXT_CTRLA) 16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-6  */
398 #define   SERCOM_USART_EXT_CTRLA_SAMPA_ADJ2_Val _UINT32_(0x2)                                        /* (SERCOM_USART_EXT_CTRLA) 16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-7  */
399 #define   SERCOM_USART_EXT_CTRLA_SAMPA_ADJ3_Val _UINT32_(0x3)                                        /* (SERCOM_USART_EXT_CTRLA) 16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8  */
400 #define SERCOM_USART_EXT_CTRLA_SAMPA_ADJ0     (SERCOM_USART_EXT_CTRLA_SAMPA_ADJ0_Val << SERCOM_USART_EXT_CTRLA_SAMPA_Pos) /* (SERCOM_USART_EXT_CTRLA) 16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-5 Position  */
401 #define SERCOM_USART_EXT_CTRLA_SAMPA_ADJ1     (SERCOM_USART_EXT_CTRLA_SAMPA_ADJ1_Val << SERCOM_USART_EXT_CTRLA_SAMPA_Pos) /* (SERCOM_USART_EXT_CTRLA) 16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-6 Position  */
402 #define SERCOM_USART_EXT_CTRLA_SAMPA_ADJ2     (SERCOM_USART_EXT_CTRLA_SAMPA_ADJ2_Val << SERCOM_USART_EXT_CTRLA_SAMPA_Pos) /* (SERCOM_USART_EXT_CTRLA) 16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-7 Position  */
403 #define SERCOM_USART_EXT_CTRLA_SAMPA_ADJ3     (SERCOM_USART_EXT_CTRLA_SAMPA_ADJ3_Val << SERCOM_USART_EXT_CTRLA_SAMPA_Pos) /* (SERCOM_USART_EXT_CTRLA) 16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8 Position  */
404 #define SERCOM_USART_EXT_CTRLA_FORM_Pos       _UINT32_(24)                                         /* (SERCOM_USART_EXT_CTRLA) Frame Format Position */
405 #define SERCOM_USART_EXT_CTRLA_FORM_Msk       (_UINT32_(0xF) << SERCOM_USART_EXT_CTRLA_FORM_Pos)   /* (SERCOM_USART_EXT_CTRLA) Frame Format Mask */
406 #define SERCOM_USART_EXT_CTRLA_FORM(value)    (SERCOM_USART_EXT_CTRLA_FORM_Msk & (_UINT32_(value) << SERCOM_USART_EXT_CTRLA_FORM_Pos)) /* Assigment of value for FORM in the SERCOM_USART_EXT_CTRLA register */
407 #define   SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_NO_PARITY_Val _UINT32_(0x0)                                        /* (SERCOM_USART_EXT_CTRLA) USART frame  */
408 #define   SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_WITH_PARITY_Val _UINT32_(0x1)                                        /* (SERCOM_USART_EXT_CTRLA) USART frame with parity  */
409 #define   SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_LIN_MASTER_MODE_Val _UINT32_(0x2)                                        /* (SERCOM_USART_EXT_CTRLA) LIN Master - Break and sync generation  */
410 #define   SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_AUTO_BAUD_NO_PARITY_Val _UINT32_(0x4)                                        /* (SERCOM_USART_EXT_CTRLA) Auto-baud (LIN Slave) - break detection and auto-baud  */
411 #define   SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_AUTO_BAUD_WITH_PARITY_Val _UINT32_(0x5)                                        /* (SERCOM_USART_EXT_CTRLA) Auto-baud - break detection and auto-baud with parity  */
412 #define   SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_ISO_7816_Val _UINT32_(0x7)                                        /* (SERCOM_USART_EXT_CTRLA) ISO 7816  */
413 #define SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_NO_PARITY (SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_NO_PARITY_Val << SERCOM_USART_EXT_CTRLA_FORM_Pos) /* (SERCOM_USART_EXT_CTRLA) USART frame Position  */
414 #define SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_WITH_PARITY (SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_WITH_PARITY_Val << SERCOM_USART_EXT_CTRLA_FORM_Pos) /* (SERCOM_USART_EXT_CTRLA) USART frame with parity Position  */
415 #define SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_LIN_MASTER_MODE (SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_LIN_MASTER_MODE_Val << SERCOM_USART_EXT_CTRLA_FORM_Pos) /* (SERCOM_USART_EXT_CTRLA) LIN Master - Break and sync generation Position  */
416 #define SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_AUTO_BAUD_NO_PARITY (SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_AUTO_BAUD_NO_PARITY_Val << SERCOM_USART_EXT_CTRLA_FORM_Pos) /* (SERCOM_USART_EXT_CTRLA) Auto-baud (LIN Slave) - break detection and auto-baud Position  */
417 #define SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_AUTO_BAUD_WITH_PARITY (SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_AUTO_BAUD_WITH_PARITY_Val << SERCOM_USART_EXT_CTRLA_FORM_Pos) /* (SERCOM_USART_EXT_CTRLA) Auto-baud - break detection and auto-baud with parity Position  */
418 #define SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_ISO_7816 (SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_ISO_7816_Val << SERCOM_USART_EXT_CTRLA_FORM_Pos) /* (SERCOM_USART_EXT_CTRLA) ISO 7816 Position  */
419 #define SERCOM_USART_EXT_CTRLA_CMODE_Pos      _UINT32_(28)                                         /* (SERCOM_USART_EXT_CTRLA) Communication Mode Position */
420 #define SERCOM_USART_EXT_CTRLA_CMODE_Msk      (_UINT32_(0x1) << SERCOM_USART_EXT_CTRLA_CMODE_Pos)  /* (SERCOM_USART_EXT_CTRLA) Communication Mode Mask */
421 #define SERCOM_USART_EXT_CTRLA_CMODE(value)   (SERCOM_USART_EXT_CTRLA_CMODE_Msk & (_UINT32_(value) << SERCOM_USART_EXT_CTRLA_CMODE_Pos)) /* Assigment of value for CMODE in the SERCOM_USART_EXT_CTRLA register */
422 #define   SERCOM_USART_EXT_CTRLA_CMODE_ASYNC_Val _UINT32_(0x0)                                        /* (SERCOM_USART_EXT_CTRLA) Asynchronous Communication  */
423 #define   SERCOM_USART_EXT_CTRLA_CMODE_SYNC_Val _UINT32_(0x1)                                        /* (SERCOM_USART_EXT_CTRLA) Synchronous Communication  */
424 #define SERCOM_USART_EXT_CTRLA_CMODE_ASYNC    (SERCOM_USART_EXT_CTRLA_CMODE_ASYNC_Val << SERCOM_USART_EXT_CTRLA_CMODE_Pos) /* (SERCOM_USART_EXT_CTRLA) Asynchronous Communication Position  */
425 #define SERCOM_USART_EXT_CTRLA_CMODE_SYNC     (SERCOM_USART_EXT_CTRLA_CMODE_SYNC_Val << SERCOM_USART_EXT_CTRLA_CMODE_Pos) /* (SERCOM_USART_EXT_CTRLA) Synchronous Communication Position  */
426 #define SERCOM_USART_EXT_CTRLA_CPOL_Pos       _UINT32_(29)                                         /* (SERCOM_USART_EXT_CTRLA) Clock Polarity Position */
427 #define SERCOM_USART_EXT_CTRLA_CPOL_Msk       (_UINT32_(0x1) << SERCOM_USART_EXT_CTRLA_CPOL_Pos)   /* (SERCOM_USART_EXT_CTRLA) Clock Polarity Mask */
428 #define SERCOM_USART_EXT_CTRLA_CPOL(value)    (SERCOM_USART_EXT_CTRLA_CPOL_Msk & (_UINT32_(value) << SERCOM_USART_EXT_CTRLA_CPOL_Pos)) /* Assigment of value for CPOL in the SERCOM_USART_EXT_CTRLA register */
429 #define   SERCOM_USART_EXT_CTRLA_CPOL_IDLE_LOW_Val _UINT32_(0x0)                                        /* (SERCOM_USART_EXT_CTRLA) TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge  */
430 #define   SERCOM_USART_EXT_CTRLA_CPOL_IDLE_HIGH_Val _UINT32_(0x1)                                        /* (SERCOM_USART_EXT_CTRLA) TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge  */
431 #define SERCOM_USART_EXT_CTRLA_CPOL_IDLE_LOW  (SERCOM_USART_EXT_CTRLA_CPOL_IDLE_LOW_Val << SERCOM_USART_EXT_CTRLA_CPOL_Pos) /* (SERCOM_USART_EXT_CTRLA) TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge Position  */
432 #define SERCOM_USART_EXT_CTRLA_CPOL_IDLE_HIGH (SERCOM_USART_EXT_CTRLA_CPOL_IDLE_HIGH_Val << SERCOM_USART_EXT_CTRLA_CPOL_Pos) /* (SERCOM_USART_EXT_CTRLA) TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge Position  */
433 #define SERCOM_USART_EXT_CTRLA_DORD_Pos       _UINT32_(30)                                         /* (SERCOM_USART_EXT_CTRLA) Data Order Position */
434 #define SERCOM_USART_EXT_CTRLA_DORD_Msk       (_UINT32_(0x1) << SERCOM_USART_EXT_CTRLA_DORD_Pos)   /* (SERCOM_USART_EXT_CTRLA) Data Order Mask */
435 #define SERCOM_USART_EXT_CTRLA_DORD(value)    (SERCOM_USART_EXT_CTRLA_DORD_Msk & (_UINT32_(value) << SERCOM_USART_EXT_CTRLA_DORD_Pos)) /* Assigment of value for DORD in the SERCOM_USART_EXT_CTRLA register */
436 #define   SERCOM_USART_EXT_CTRLA_DORD_MSB_Val _UINT32_(0x0)                                        /* (SERCOM_USART_EXT_CTRLA) MSB is transmitted first  */
437 #define   SERCOM_USART_EXT_CTRLA_DORD_LSB_Val _UINT32_(0x1)                                        /* (SERCOM_USART_EXT_CTRLA) LSB is transmitted first  */
438 #define SERCOM_USART_EXT_CTRLA_DORD_MSB       (SERCOM_USART_EXT_CTRLA_DORD_MSB_Val << SERCOM_USART_EXT_CTRLA_DORD_Pos) /* (SERCOM_USART_EXT_CTRLA) MSB is transmitted first Position  */
439 #define SERCOM_USART_EXT_CTRLA_DORD_LSB       (SERCOM_USART_EXT_CTRLA_DORD_LSB_Val << SERCOM_USART_EXT_CTRLA_DORD_Pos) /* (SERCOM_USART_EXT_CTRLA) LSB is transmitted first Position  */
440 #define SERCOM_USART_EXT_CTRLA_Msk            _UINT32_(0x7FF3E79F)                                 /* (SERCOM_USART_EXT_CTRLA) Register Mask  */
441 
442 
443 /* -------- SERCOM_USART_INT_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART_INT Control A -------- */
444 #define SERCOM_USART_INT_CTRLA_RESETVALUE     _UINT32_(0x00)                                       /*  (SERCOM_USART_INT_CTRLA) USART_INT Control A  Reset Value */
445 
446 #define SERCOM_USART_INT_CTRLA_SWRST_Pos      _UINT32_(0)                                          /* (SERCOM_USART_INT_CTRLA) Software Reset Position */
447 #define SERCOM_USART_INT_CTRLA_SWRST_Msk      (_UINT32_(0x1) << SERCOM_USART_INT_CTRLA_SWRST_Pos)  /* (SERCOM_USART_INT_CTRLA) Software Reset Mask */
448 #define SERCOM_USART_INT_CTRLA_SWRST(value)   (SERCOM_USART_INT_CTRLA_SWRST_Msk & (_UINT32_(value) << SERCOM_USART_INT_CTRLA_SWRST_Pos)) /* Assigment of value for SWRST in the SERCOM_USART_INT_CTRLA register */
449 #define SERCOM_USART_INT_CTRLA_ENABLE_Pos     _UINT32_(1)                                          /* (SERCOM_USART_INT_CTRLA) Enable Position */
450 #define SERCOM_USART_INT_CTRLA_ENABLE_Msk     (_UINT32_(0x1) << SERCOM_USART_INT_CTRLA_ENABLE_Pos) /* (SERCOM_USART_INT_CTRLA) Enable Mask */
451 #define SERCOM_USART_INT_CTRLA_ENABLE(value)  (SERCOM_USART_INT_CTRLA_ENABLE_Msk & (_UINT32_(value) << SERCOM_USART_INT_CTRLA_ENABLE_Pos)) /* Assigment of value for ENABLE in the SERCOM_USART_INT_CTRLA register */
452 #define SERCOM_USART_INT_CTRLA_MODE_Pos       _UINT32_(2)                                          /* (SERCOM_USART_INT_CTRLA) Operating Mode Position */
453 #define SERCOM_USART_INT_CTRLA_MODE_Msk       (_UINT32_(0x7) << SERCOM_USART_INT_CTRLA_MODE_Pos)   /* (SERCOM_USART_INT_CTRLA) Operating Mode Mask */
454 #define SERCOM_USART_INT_CTRLA_MODE(value)    (SERCOM_USART_INT_CTRLA_MODE_Msk & (_UINT32_(value) << SERCOM_USART_INT_CTRLA_MODE_Pos)) /* Assigment of value for MODE in the SERCOM_USART_INT_CTRLA register */
455 #define   SERCOM_USART_INT_CTRLA_MODE_USART_EXT_CLK_Val _UINT32_(0x0)                                        /* (SERCOM_USART_INT_CTRLA) USART with external clock  */
456 #define   SERCOM_USART_INT_CTRLA_MODE_USART_INT_CLK_Val _UINT32_(0x1)                                        /* (SERCOM_USART_INT_CTRLA) USART with internal clock  */
457 #define   SERCOM_USART_INT_CTRLA_MODE_SPI_SLAVE_Val _UINT32_(0x2)                                        /* (SERCOM_USART_INT_CTRLA) SPI in slave operation  */
458 #define   SERCOM_USART_INT_CTRLA_MODE_SPI_MASTER_Val _UINT32_(0x3)                                        /* (SERCOM_USART_INT_CTRLA) SPI in master operation  */
459 #define   SERCOM_USART_INT_CTRLA_MODE_I2C_SLAVE_Val _UINT32_(0x4)                                        /* (SERCOM_USART_INT_CTRLA) I2C slave operation  */
460 #define   SERCOM_USART_INT_CTRLA_MODE_I2C_MASTER_Val _UINT32_(0x5)                                        /* (SERCOM_USART_INT_CTRLA) I2C master operation  */
461 #define SERCOM_USART_INT_CTRLA_MODE_USART_EXT_CLK (SERCOM_USART_INT_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_USART_INT_CTRLA_MODE_Pos) /* (SERCOM_USART_INT_CTRLA) USART with external clock Position  */
462 #define SERCOM_USART_INT_CTRLA_MODE_USART_INT_CLK (SERCOM_USART_INT_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_USART_INT_CTRLA_MODE_Pos) /* (SERCOM_USART_INT_CTRLA) USART with internal clock Position  */
463 #define SERCOM_USART_INT_CTRLA_MODE_SPI_SLAVE (SERCOM_USART_INT_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_USART_INT_CTRLA_MODE_Pos) /* (SERCOM_USART_INT_CTRLA) SPI in slave operation Position  */
464 #define SERCOM_USART_INT_CTRLA_MODE_SPI_MASTER (SERCOM_USART_INT_CTRLA_MODE_SPI_MASTER_Val << SERCOM_USART_INT_CTRLA_MODE_Pos) /* (SERCOM_USART_INT_CTRLA) SPI in master operation Position  */
465 #define SERCOM_USART_INT_CTRLA_MODE_I2C_SLAVE (SERCOM_USART_INT_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_USART_INT_CTRLA_MODE_Pos) /* (SERCOM_USART_INT_CTRLA) I2C slave operation Position  */
466 #define SERCOM_USART_INT_CTRLA_MODE_I2C_MASTER (SERCOM_USART_INT_CTRLA_MODE_I2C_MASTER_Val << SERCOM_USART_INT_CTRLA_MODE_Pos) /* (SERCOM_USART_INT_CTRLA) I2C master operation Position  */
467 #define SERCOM_USART_INT_CTRLA_RUNSTDBY_Pos   _UINT32_(7)                                          /* (SERCOM_USART_INT_CTRLA) Run during Standby Position */
468 #define SERCOM_USART_INT_CTRLA_RUNSTDBY_Msk   (_UINT32_(0x1) << SERCOM_USART_INT_CTRLA_RUNSTDBY_Pos) /* (SERCOM_USART_INT_CTRLA) Run during Standby Mask */
469 #define SERCOM_USART_INT_CTRLA_RUNSTDBY(value) (SERCOM_USART_INT_CTRLA_RUNSTDBY_Msk & (_UINT32_(value) << SERCOM_USART_INT_CTRLA_RUNSTDBY_Pos)) /* Assigment of value for RUNSTDBY in the SERCOM_USART_INT_CTRLA register */
470 #define SERCOM_USART_INT_CTRLA_IBON_Pos       _UINT32_(8)                                          /* (SERCOM_USART_INT_CTRLA) Immediate Buffer Overflow Notification Position */
471 #define SERCOM_USART_INT_CTRLA_IBON_Msk       (_UINT32_(0x1) << SERCOM_USART_INT_CTRLA_IBON_Pos)   /* (SERCOM_USART_INT_CTRLA) Immediate Buffer Overflow Notification Mask */
472 #define SERCOM_USART_INT_CTRLA_IBON(value)    (SERCOM_USART_INT_CTRLA_IBON_Msk & (_UINT32_(value) << SERCOM_USART_INT_CTRLA_IBON_Pos)) /* Assigment of value for IBON in the SERCOM_USART_INT_CTRLA register */
473 #define SERCOM_USART_INT_CTRLA_TXINV_Pos      _UINT32_(9)                                          /* (SERCOM_USART_INT_CTRLA) Transmit Data Invert Position */
474 #define SERCOM_USART_INT_CTRLA_TXINV_Msk      (_UINT32_(0x1) << SERCOM_USART_INT_CTRLA_TXINV_Pos)  /* (SERCOM_USART_INT_CTRLA) Transmit Data Invert Mask */
475 #define SERCOM_USART_INT_CTRLA_TXINV(value)   (SERCOM_USART_INT_CTRLA_TXINV_Msk & (_UINT32_(value) << SERCOM_USART_INT_CTRLA_TXINV_Pos)) /* Assigment of value for TXINV in the SERCOM_USART_INT_CTRLA register */
476 #define SERCOM_USART_INT_CTRLA_RXINV_Pos      _UINT32_(10)                                         /* (SERCOM_USART_INT_CTRLA) Receive Data Invert Position */
477 #define SERCOM_USART_INT_CTRLA_RXINV_Msk      (_UINT32_(0x1) << SERCOM_USART_INT_CTRLA_RXINV_Pos)  /* (SERCOM_USART_INT_CTRLA) Receive Data Invert Mask */
478 #define SERCOM_USART_INT_CTRLA_RXINV(value)   (SERCOM_USART_INT_CTRLA_RXINV_Msk & (_UINT32_(value) << SERCOM_USART_INT_CTRLA_RXINV_Pos)) /* Assigment of value for RXINV in the SERCOM_USART_INT_CTRLA register */
479 #define SERCOM_USART_INT_CTRLA_SAMPR_Pos      _UINT32_(13)                                         /* (SERCOM_USART_INT_CTRLA) Sample Position */
480 #define SERCOM_USART_INT_CTRLA_SAMPR_Msk      (_UINT32_(0x7) << SERCOM_USART_INT_CTRLA_SAMPR_Pos)  /* (SERCOM_USART_INT_CTRLA) Sample Mask */
481 #define SERCOM_USART_INT_CTRLA_SAMPR(value)   (SERCOM_USART_INT_CTRLA_SAMPR_Msk & (_UINT32_(value) << SERCOM_USART_INT_CTRLA_SAMPR_Pos)) /* Assigment of value for SAMPR in the SERCOM_USART_INT_CTRLA register */
482 #define   SERCOM_USART_INT_CTRLA_SAMPR_16X_ARITHMETIC_Val _UINT32_(0x0)                                        /* (SERCOM_USART_INT_CTRLA) 16x over-sampling using arithmetic baudrate generation  */
483 #define   SERCOM_USART_INT_CTRLA_SAMPR_16X_FRACTIONAL_Val _UINT32_(0x1)                                        /* (SERCOM_USART_INT_CTRLA) 16x over-sampling using fractional baudrate generation  */
484 #define   SERCOM_USART_INT_CTRLA_SAMPR_8X_ARITHMETIC_Val _UINT32_(0x2)                                        /* (SERCOM_USART_INT_CTRLA) 8x over-sampling using arithmetic baudrate generation  */
485 #define   SERCOM_USART_INT_CTRLA_SAMPR_8X_FRACTIONAL_Val _UINT32_(0x3)                                        /* (SERCOM_USART_INT_CTRLA) 8x over-sampling using fractional baudrate generation  */
486 #define   SERCOM_USART_INT_CTRLA_SAMPR_3X_ARITHMETIC_Val _UINT32_(0x4)                                        /* (SERCOM_USART_INT_CTRLA) 3x over-sampling using arithmetic baudrate generation  */
487 #define SERCOM_USART_INT_CTRLA_SAMPR_16X_ARITHMETIC (SERCOM_USART_INT_CTRLA_SAMPR_16X_ARITHMETIC_Val << SERCOM_USART_INT_CTRLA_SAMPR_Pos) /* (SERCOM_USART_INT_CTRLA) 16x over-sampling using arithmetic baudrate generation Position  */
488 #define SERCOM_USART_INT_CTRLA_SAMPR_16X_FRACTIONAL (SERCOM_USART_INT_CTRLA_SAMPR_16X_FRACTIONAL_Val << SERCOM_USART_INT_CTRLA_SAMPR_Pos) /* (SERCOM_USART_INT_CTRLA) 16x over-sampling using fractional baudrate generation Position  */
489 #define SERCOM_USART_INT_CTRLA_SAMPR_8X_ARITHMETIC (SERCOM_USART_INT_CTRLA_SAMPR_8X_ARITHMETIC_Val << SERCOM_USART_INT_CTRLA_SAMPR_Pos) /* (SERCOM_USART_INT_CTRLA) 8x over-sampling using arithmetic baudrate generation Position  */
490 #define SERCOM_USART_INT_CTRLA_SAMPR_8X_FRACTIONAL (SERCOM_USART_INT_CTRLA_SAMPR_8X_FRACTIONAL_Val << SERCOM_USART_INT_CTRLA_SAMPR_Pos) /* (SERCOM_USART_INT_CTRLA) 8x over-sampling using fractional baudrate generation Position  */
491 #define SERCOM_USART_INT_CTRLA_SAMPR_3X_ARITHMETIC (SERCOM_USART_INT_CTRLA_SAMPR_3X_ARITHMETIC_Val << SERCOM_USART_INT_CTRLA_SAMPR_Pos) /* (SERCOM_USART_INT_CTRLA) 3x over-sampling using arithmetic baudrate generation Position  */
492 #define SERCOM_USART_INT_CTRLA_TXPO_Pos       _UINT32_(16)                                         /* (SERCOM_USART_INT_CTRLA) Transmit Data Pinout Position */
493 #define SERCOM_USART_INT_CTRLA_TXPO_Msk       (_UINT32_(0x3) << SERCOM_USART_INT_CTRLA_TXPO_Pos)   /* (SERCOM_USART_INT_CTRLA) Transmit Data Pinout Mask */
494 #define SERCOM_USART_INT_CTRLA_TXPO(value)    (SERCOM_USART_INT_CTRLA_TXPO_Msk & (_UINT32_(value) << SERCOM_USART_INT_CTRLA_TXPO_Pos)) /* Assigment of value for TXPO in the SERCOM_USART_INT_CTRLA register */
495 #define   SERCOM_USART_INT_CTRLA_TXPO_PAD0_Val _UINT32_(0x0)                                        /* (SERCOM_USART_INT_CTRLA) PAD[0] = TxD; PAD[1] = XCK  */
496 #define   SERCOM_USART_INT_CTRLA_TXPO_PAD2_Val _UINT32_(0x2)                                        /* (SERCOM_USART_INT_CTRLA) PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS  */
497 #define   SERCOM_USART_INT_CTRLA_TXPO_PAD3_Val _UINT32_(0x3)                                        /* (SERCOM_USART_INT_CTRLA) PAD[0] = TxD; PAD[1] = XCK; PAD[2] = TE  */
498 #define SERCOM_USART_INT_CTRLA_TXPO_PAD0      (SERCOM_USART_INT_CTRLA_TXPO_PAD0_Val << SERCOM_USART_INT_CTRLA_TXPO_Pos) /* (SERCOM_USART_INT_CTRLA) PAD[0] = TxD; PAD[1] = XCK Position  */
499 #define SERCOM_USART_INT_CTRLA_TXPO_PAD2      (SERCOM_USART_INT_CTRLA_TXPO_PAD2_Val << SERCOM_USART_INT_CTRLA_TXPO_Pos) /* (SERCOM_USART_INT_CTRLA) PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS Position  */
500 #define SERCOM_USART_INT_CTRLA_TXPO_PAD3      (SERCOM_USART_INT_CTRLA_TXPO_PAD3_Val << SERCOM_USART_INT_CTRLA_TXPO_Pos) /* (SERCOM_USART_INT_CTRLA) PAD[0] = TxD; PAD[1] = XCK; PAD[2] = TE Position  */
501 #define SERCOM_USART_INT_CTRLA_RXPO_Pos       _UINT32_(20)                                         /* (SERCOM_USART_INT_CTRLA) Receive Data Pinout Position */
502 #define SERCOM_USART_INT_CTRLA_RXPO_Msk       (_UINT32_(0x3) << SERCOM_USART_INT_CTRLA_RXPO_Pos)   /* (SERCOM_USART_INT_CTRLA) Receive Data Pinout Mask */
503 #define SERCOM_USART_INT_CTRLA_RXPO(value)    (SERCOM_USART_INT_CTRLA_RXPO_Msk & (_UINT32_(value) << SERCOM_USART_INT_CTRLA_RXPO_Pos)) /* Assigment of value for RXPO in the SERCOM_USART_INT_CTRLA register */
504 #define   SERCOM_USART_INT_CTRLA_RXPO_PAD0_Val _UINT32_(0x0)                                        /* (SERCOM_USART_INT_CTRLA) SERCOM PAD[0] is used for data reception  */
505 #define   SERCOM_USART_INT_CTRLA_RXPO_PAD1_Val _UINT32_(0x1)                                        /* (SERCOM_USART_INT_CTRLA) SERCOM PAD[1] is used for data reception  */
506 #define   SERCOM_USART_INT_CTRLA_RXPO_PAD2_Val _UINT32_(0x2)                                        /* (SERCOM_USART_INT_CTRLA) SERCOM PAD[2] is used for data reception  */
507 #define   SERCOM_USART_INT_CTRLA_RXPO_PAD3_Val _UINT32_(0x3)                                        /* (SERCOM_USART_INT_CTRLA) SERCOM PAD[3] is used for data reception  */
508 #define SERCOM_USART_INT_CTRLA_RXPO_PAD0      (SERCOM_USART_INT_CTRLA_RXPO_PAD0_Val << SERCOM_USART_INT_CTRLA_RXPO_Pos) /* (SERCOM_USART_INT_CTRLA) SERCOM PAD[0] is used for data reception Position  */
509 #define SERCOM_USART_INT_CTRLA_RXPO_PAD1      (SERCOM_USART_INT_CTRLA_RXPO_PAD1_Val << SERCOM_USART_INT_CTRLA_RXPO_Pos) /* (SERCOM_USART_INT_CTRLA) SERCOM PAD[1] is used for data reception Position  */
510 #define SERCOM_USART_INT_CTRLA_RXPO_PAD2      (SERCOM_USART_INT_CTRLA_RXPO_PAD2_Val << SERCOM_USART_INT_CTRLA_RXPO_Pos) /* (SERCOM_USART_INT_CTRLA) SERCOM PAD[2] is used for data reception Position  */
511 #define SERCOM_USART_INT_CTRLA_RXPO_PAD3      (SERCOM_USART_INT_CTRLA_RXPO_PAD3_Val << SERCOM_USART_INT_CTRLA_RXPO_Pos) /* (SERCOM_USART_INT_CTRLA) SERCOM PAD[3] is used for data reception Position  */
512 #define SERCOM_USART_INT_CTRLA_SAMPA_Pos      _UINT32_(22)                                         /* (SERCOM_USART_INT_CTRLA) Sample Adjustment Position */
513 #define SERCOM_USART_INT_CTRLA_SAMPA_Msk      (_UINT32_(0x3) << SERCOM_USART_INT_CTRLA_SAMPA_Pos)  /* (SERCOM_USART_INT_CTRLA) Sample Adjustment Mask */
514 #define SERCOM_USART_INT_CTRLA_SAMPA(value)   (SERCOM_USART_INT_CTRLA_SAMPA_Msk & (_UINT32_(value) << SERCOM_USART_INT_CTRLA_SAMPA_Pos)) /* Assigment of value for SAMPA in the SERCOM_USART_INT_CTRLA register */
515 #define   SERCOM_USART_INT_CTRLA_SAMPA_ADJ0_Val _UINT32_(0x0)                                        /* (SERCOM_USART_INT_CTRLA) 16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-5  */
516 #define   SERCOM_USART_INT_CTRLA_SAMPA_ADJ1_Val _UINT32_(0x1)                                        /* (SERCOM_USART_INT_CTRLA) 16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-6  */
517 #define   SERCOM_USART_INT_CTRLA_SAMPA_ADJ2_Val _UINT32_(0x2)                                        /* (SERCOM_USART_INT_CTRLA) 16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-7  */
518 #define   SERCOM_USART_INT_CTRLA_SAMPA_ADJ3_Val _UINT32_(0x3)                                        /* (SERCOM_USART_INT_CTRLA) 16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8  */
519 #define SERCOM_USART_INT_CTRLA_SAMPA_ADJ0     (SERCOM_USART_INT_CTRLA_SAMPA_ADJ0_Val << SERCOM_USART_INT_CTRLA_SAMPA_Pos) /* (SERCOM_USART_INT_CTRLA) 16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-5 Position  */
520 #define SERCOM_USART_INT_CTRLA_SAMPA_ADJ1     (SERCOM_USART_INT_CTRLA_SAMPA_ADJ1_Val << SERCOM_USART_INT_CTRLA_SAMPA_Pos) /* (SERCOM_USART_INT_CTRLA) 16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-6 Position  */
521 #define SERCOM_USART_INT_CTRLA_SAMPA_ADJ2     (SERCOM_USART_INT_CTRLA_SAMPA_ADJ2_Val << SERCOM_USART_INT_CTRLA_SAMPA_Pos) /* (SERCOM_USART_INT_CTRLA) 16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-7 Position  */
522 #define SERCOM_USART_INT_CTRLA_SAMPA_ADJ3     (SERCOM_USART_INT_CTRLA_SAMPA_ADJ3_Val << SERCOM_USART_INT_CTRLA_SAMPA_Pos) /* (SERCOM_USART_INT_CTRLA) 16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8 Position  */
523 #define SERCOM_USART_INT_CTRLA_FORM_Pos       _UINT32_(24)                                         /* (SERCOM_USART_INT_CTRLA) Frame Format Position */
524 #define SERCOM_USART_INT_CTRLA_FORM_Msk       (_UINT32_(0xF) << SERCOM_USART_INT_CTRLA_FORM_Pos)   /* (SERCOM_USART_INT_CTRLA) Frame Format Mask */
525 #define SERCOM_USART_INT_CTRLA_FORM(value)    (SERCOM_USART_INT_CTRLA_FORM_Msk & (_UINT32_(value) << SERCOM_USART_INT_CTRLA_FORM_Pos)) /* Assigment of value for FORM in the SERCOM_USART_INT_CTRLA register */
526 #define   SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_NO_PARITY_Val _UINT32_(0x0)                                        /* (SERCOM_USART_INT_CTRLA) USART frame  */
527 #define   SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_WITH_PARITY_Val _UINT32_(0x1)                                        /* (SERCOM_USART_INT_CTRLA) USART frame with parity  */
528 #define   SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_LIN_MASTER_MODE_Val _UINT32_(0x2)                                        /* (SERCOM_USART_INT_CTRLA) LIN Master - Break and sync generation  */
529 #define   SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_AUTO_BAUD_NO_PARITY_Val _UINT32_(0x4)                                        /* (SERCOM_USART_INT_CTRLA) Auto-baud (LIN Slave) - break detection and auto-baud  */
530 #define   SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_AUTO_BAUD_WITH_PARITY_Val _UINT32_(0x5)                                        /* (SERCOM_USART_INT_CTRLA) Auto-baud - break detection and auto-baud with parity  */
531 #define   SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_ISO_7816_Val _UINT32_(0x7)                                        /* (SERCOM_USART_INT_CTRLA) ISO 7816  */
532 #define SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_NO_PARITY (SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_NO_PARITY_Val << SERCOM_USART_INT_CTRLA_FORM_Pos) /* (SERCOM_USART_INT_CTRLA) USART frame Position  */
533 #define SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_WITH_PARITY (SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_WITH_PARITY_Val << SERCOM_USART_INT_CTRLA_FORM_Pos) /* (SERCOM_USART_INT_CTRLA) USART frame with parity Position  */
534 #define SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_LIN_MASTER_MODE (SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_LIN_MASTER_MODE_Val << SERCOM_USART_INT_CTRLA_FORM_Pos) /* (SERCOM_USART_INT_CTRLA) LIN Master - Break and sync generation Position  */
535 #define SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_AUTO_BAUD_NO_PARITY (SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_AUTO_BAUD_NO_PARITY_Val << SERCOM_USART_INT_CTRLA_FORM_Pos) /* (SERCOM_USART_INT_CTRLA) Auto-baud (LIN Slave) - break detection and auto-baud Position  */
536 #define SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_AUTO_BAUD_WITH_PARITY (SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_AUTO_BAUD_WITH_PARITY_Val << SERCOM_USART_INT_CTRLA_FORM_Pos) /* (SERCOM_USART_INT_CTRLA) Auto-baud - break detection and auto-baud with parity Position  */
537 #define SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_ISO_7816 (SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_ISO_7816_Val << SERCOM_USART_INT_CTRLA_FORM_Pos) /* (SERCOM_USART_INT_CTRLA) ISO 7816 Position  */
538 #define SERCOM_USART_INT_CTRLA_CMODE_Pos      _UINT32_(28)                                         /* (SERCOM_USART_INT_CTRLA) Communication Mode Position */
539 #define SERCOM_USART_INT_CTRLA_CMODE_Msk      (_UINT32_(0x1) << SERCOM_USART_INT_CTRLA_CMODE_Pos)  /* (SERCOM_USART_INT_CTRLA) Communication Mode Mask */
540 #define SERCOM_USART_INT_CTRLA_CMODE(value)   (SERCOM_USART_INT_CTRLA_CMODE_Msk & (_UINT32_(value) << SERCOM_USART_INT_CTRLA_CMODE_Pos)) /* Assigment of value for CMODE in the SERCOM_USART_INT_CTRLA register */
541 #define   SERCOM_USART_INT_CTRLA_CMODE_ASYNC_Val _UINT32_(0x0)                                        /* (SERCOM_USART_INT_CTRLA) Asynchronous Communication  */
542 #define   SERCOM_USART_INT_CTRLA_CMODE_SYNC_Val _UINT32_(0x1)                                        /* (SERCOM_USART_INT_CTRLA) Synchronous Communication  */
543 #define SERCOM_USART_INT_CTRLA_CMODE_ASYNC    (SERCOM_USART_INT_CTRLA_CMODE_ASYNC_Val << SERCOM_USART_INT_CTRLA_CMODE_Pos) /* (SERCOM_USART_INT_CTRLA) Asynchronous Communication Position  */
544 #define SERCOM_USART_INT_CTRLA_CMODE_SYNC     (SERCOM_USART_INT_CTRLA_CMODE_SYNC_Val << SERCOM_USART_INT_CTRLA_CMODE_Pos) /* (SERCOM_USART_INT_CTRLA) Synchronous Communication Position  */
545 #define SERCOM_USART_INT_CTRLA_CPOL_Pos       _UINT32_(29)                                         /* (SERCOM_USART_INT_CTRLA) Clock Polarity Position */
546 #define SERCOM_USART_INT_CTRLA_CPOL_Msk       (_UINT32_(0x1) << SERCOM_USART_INT_CTRLA_CPOL_Pos)   /* (SERCOM_USART_INT_CTRLA) Clock Polarity Mask */
547 #define SERCOM_USART_INT_CTRLA_CPOL(value)    (SERCOM_USART_INT_CTRLA_CPOL_Msk & (_UINT32_(value) << SERCOM_USART_INT_CTRLA_CPOL_Pos)) /* Assigment of value for CPOL in the SERCOM_USART_INT_CTRLA register */
548 #define   SERCOM_USART_INT_CTRLA_CPOL_IDLE_LOW_Val _UINT32_(0x0)                                        /* (SERCOM_USART_INT_CTRLA) TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge  */
549 #define   SERCOM_USART_INT_CTRLA_CPOL_IDLE_HIGH_Val _UINT32_(0x1)                                        /* (SERCOM_USART_INT_CTRLA) TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge  */
550 #define SERCOM_USART_INT_CTRLA_CPOL_IDLE_LOW  (SERCOM_USART_INT_CTRLA_CPOL_IDLE_LOW_Val << SERCOM_USART_INT_CTRLA_CPOL_Pos) /* (SERCOM_USART_INT_CTRLA) TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge Position  */
551 #define SERCOM_USART_INT_CTRLA_CPOL_IDLE_HIGH (SERCOM_USART_INT_CTRLA_CPOL_IDLE_HIGH_Val << SERCOM_USART_INT_CTRLA_CPOL_Pos) /* (SERCOM_USART_INT_CTRLA) TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge Position  */
552 #define SERCOM_USART_INT_CTRLA_DORD_Pos       _UINT32_(30)                                         /* (SERCOM_USART_INT_CTRLA) Data Order Position */
553 #define SERCOM_USART_INT_CTRLA_DORD_Msk       (_UINT32_(0x1) << SERCOM_USART_INT_CTRLA_DORD_Pos)   /* (SERCOM_USART_INT_CTRLA) Data Order Mask */
554 #define SERCOM_USART_INT_CTRLA_DORD(value)    (SERCOM_USART_INT_CTRLA_DORD_Msk & (_UINT32_(value) << SERCOM_USART_INT_CTRLA_DORD_Pos)) /* Assigment of value for DORD in the SERCOM_USART_INT_CTRLA register */
555 #define   SERCOM_USART_INT_CTRLA_DORD_MSB_Val _UINT32_(0x0)                                        /* (SERCOM_USART_INT_CTRLA) MSB is transmitted first  */
556 #define   SERCOM_USART_INT_CTRLA_DORD_LSB_Val _UINT32_(0x1)                                        /* (SERCOM_USART_INT_CTRLA) LSB is transmitted first  */
557 #define SERCOM_USART_INT_CTRLA_DORD_MSB       (SERCOM_USART_INT_CTRLA_DORD_MSB_Val << SERCOM_USART_INT_CTRLA_DORD_Pos) /* (SERCOM_USART_INT_CTRLA) MSB is transmitted first Position  */
558 #define SERCOM_USART_INT_CTRLA_DORD_LSB       (SERCOM_USART_INT_CTRLA_DORD_LSB_Val << SERCOM_USART_INT_CTRLA_DORD_Pos) /* (SERCOM_USART_INT_CTRLA) LSB is transmitted first Position  */
559 #define SERCOM_USART_INT_CTRLA_Msk            _UINT32_(0x7FF3E79F)                                 /* (SERCOM_USART_INT_CTRLA) Register Mask  */
560 
561 
562 /* -------- SERCOM_I2CM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CM Control B -------- */
563 #define SERCOM_I2CM_CTRLB_RESETVALUE          _UINT32_(0x00)                                       /*  (SERCOM_I2CM_CTRLB) I2CM Control B  Reset Value */
564 
565 #define SERCOM_I2CM_CTRLB_SMEN_Pos            _UINT32_(8)                                          /* (SERCOM_I2CM_CTRLB) Smart Mode Enable Position */
566 #define SERCOM_I2CM_CTRLB_SMEN_Msk            (_UINT32_(0x1) << SERCOM_I2CM_CTRLB_SMEN_Pos)        /* (SERCOM_I2CM_CTRLB) Smart Mode Enable Mask */
567 #define SERCOM_I2CM_CTRLB_SMEN(value)         (SERCOM_I2CM_CTRLB_SMEN_Msk & (_UINT32_(value) << SERCOM_I2CM_CTRLB_SMEN_Pos)) /* Assigment of value for SMEN in the SERCOM_I2CM_CTRLB register */
568 #define SERCOM_I2CM_CTRLB_QCEN_Pos            _UINT32_(9)                                          /* (SERCOM_I2CM_CTRLB) Quick Command Enable Position */
569 #define SERCOM_I2CM_CTRLB_QCEN_Msk            (_UINT32_(0x1) << SERCOM_I2CM_CTRLB_QCEN_Pos)        /* (SERCOM_I2CM_CTRLB) Quick Command Enable Mask */
570 #define SERCOM_I2CM_CTRLB_QCEN(value)         (SERCOM_I2CM_CTRLB_QCEN_Msk & (_UINT32_(value) << SERCOM_I2CM_CTRLB_QCEN_Pos)) /* Assigment of value for QCEN in the SERCOM_I2CM_CTRLB register */
571 #define SERCOM_I2CM_CTRLB_CMD_Pos             _UINT32_(16)                                         /* (SERCOM_I2CM_CTRLB) Command Position */
572 #define SERCOM_I2CM_CTRLB_CMD_Msk             (_UINT32_(0x3) << SERCOM_I2CM_CTRLB_CMD_Pos)         /* (SERCOM_I2CM_CTRLB) Command Mask */
573 #define SERCOM_I2CM_CTRLB_CMD(value)          (SERCOM_I2CM_CTRLB_CMD_Msk & (_UINT32_(value) << SERCOM_I2CM_CTRLB_CMD_Pos)) /* Assigment of value for CMD in the SERCOM_I2CM_CTRLB register */
574 #define SERCOM_I2CM_CTRLB_ACKACT_Pos          _UINT32_(18)                                         /* (SERCOM_I2CM_CTRLB) Acknowledge Action Position */
575 #define SERCOM_I2CM_CTRLB_ACKACT_Msk          (_UINT32_(0x1) << SERCOM_I2CM_CTRLB_ACKACT_Pos)      /* (SERCOM_I2CM_CTRLB) Acknowledge Action Mask */
576 #define SERCOM_I2CM_CTRLB_ACKACT(value)       (SERCOM_I2CM_CTRLB_ACKACT_Msk & (_UINT32_(value) << SERCOM_I2CM_CTRLB_ACKACT_Pos)) /* Assigment of value for ACKACT in the SERCOM_I2CM_CTRLB register */
577 #define SERCOM_I2CM_CTRLB_Msk                 _UINT32_(0x00070300)                                 /* (SERCOM_I2CM_CTRLB) Register Mask  */
578 
579 
580 /* -------- SERCOM_I2CS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CS Control B -------- */
581 #define SERCOM_I2CS_CTRLB_RESETVALUE          _UINT32_(0x00)                                       /*  (SERCOM_I2CS_CTRLB) I2CS Control B  Reset Value */
582 
583 #define SERCOM_I2CS_CTRLB_SMEN_Pos            _UINT32_(8)                                          /* (SERCOM_I2CS_CTRLB) Smart Mode Enable Position */
584 #define SERCOM_I2CS_CTRLB_SMEN_Msk            (_UINT32_(0x1) << SERCOM_I2CS_CTRLB_SMEN_Pos)        /* (SERCOM_I2CS_CTRLB) Smart Mode Enable Mask */
585 #define SERCOM_I2CS_CTRLB_SMEN(value)         (SERCOM_I2CS_CTRLB_SMEN_Msk & (_UINT32_(value) << SERCOM_I2CS_CTRLB_SMEN_Pos)) /* Assigment of value for SMEN in the SERCOM_I2CS_CTRLB register */
586 #define SERCOM_I2CS_CTRLB_GCMD_Pos            _UINT32_(9)                                          /* (SERCOM_I2CS_CTRLB) PMBus Group Command Position */
587 #define SERCOM_I2CS_CTRLB_GCMD_Msk            (_UINT32_(0x1) << SERCOM_I2CS_CTRLB_GCMD_Pos)        /* (SERCOM_I2CS_CTRLB) PMBus Group Command Mask */
588 #define SERCOM_I2CS_CTRLB_GCMD(value)         (SERCOM_I2CS_CTRLB_GCMD_Msk & (_UINT32_(value) << SERCOM_I2CS_CTRLB_GCMD_Pos)) /* Assigment of value for GCMD in the SERCOM_I2CS_CTRLB register */
589 #define SERCOM_I2CS_CTRLB_AMODE_Pos           _UINT32_(14)                                         /* (SERCOM_I2CS_CTRLB) Address Mode Position */
590 #define SERCOM_I2CS_CTRLB_AMODE_Msk           (_UINT32_(0x3) << SERCOM_I2CS_CTRLB_AMODE_Pos)       /* (SERCOM_I2CS_CTRLB) Address Mode Mask */
591 #define SERCOM_I2CS_CTRLB_AMODE(value)        (SERCOM_I2CS_CTRLB_AMODE_Msk & (_UINT32_(value) << SERCOM_I2CS_CTRLB_AMODE_Pos)) /* Assigment of value for AMODE in the SERCOM_I2CS_CTRLB register */
592 #define   SERCOM_I2CS_CTRLB_AMODE_MASK_Val    _UINT32_(0x0)                                        /* (SERCOM_I2CS_CTRLB) I2C Address mask   */
593 #define   SERCOM_I2CS_CTRLB_AMODE_2_ADDRESSES_Val _UINT32_(0x1)                                        /* (SERCOM_I2CS_CTRLB) Two unique Addressess  */
594 #define   SERCOM_I2CS_CTRLB_AMODE_RANGE_Val   _UINT32_(0x2)                                        /* (SERCOM_I2CS_CTRLB) Address Range  */
595 #define SERCOM_I2CS_CTRLB_AMODE_MASK          (SERCOM_I2CS_CTRLB_AMODE_MASK_Val << SERCOM_I2CS_CTRLB_AMODE_Pos) /* (SERCOM_I2CS_CTRLB) I2C Address mask  Position  */
596 #define SERCOM_I2CS_CTRLB_AMODE_2_ADDRESSES   (SERCOM_I2CS_CTRLB_AMODE_2_ADDRESSES_Val << SERCOM_I2CS_CTRLB_AMODE_Pos) /* (SERCOM_I2CS_CTRLB) Two unique Addressess Position  */
597 #define SERCOM_I2CS_CTRLB_AMODE_RANGE         (SERCOM_I2CS_CTRLB_AMODE_RANGE_Val << SERCOM_I2CS_CTRLB_AMODE_Pos) /* (SERCOM_I2CS_CTRLB) Address Range Position  */
598 #define SERCOM_I2CS_CTRLB_CMD_Pos             _UINT32_(16)                                         /* (SERCOM_I2CS_CTRLB) Command Position */
599 #define SERCOM_I2CS_CTRLB_CMD_Msk             (_UINT32_(0x3) << SERCOM_I2CS_CTRLB_CMD_Pos)         /* (SERCOM_I2CS_CTRLB) Command Mask */
600 #define SERCOM_I2CS_CTRLB_CMD(value)          (SERCOM_I2CS_CTRLB_CMD_Msk & (_UINT32_(value) << SERCOM_I2CS_CTRLB_CMD_Pos)) /* Assigment of value for CMD in the SERCOM_I2CS_CTRLB register */
601 #define SERCOM_I2CS_CTRLB_ACKACT_Pos          _UINT32_(18)                                         /* (SERCOM_I2CS_CTRLB) Acknowledge Action Position */
602 #define SERCOM_I2CS_CTRLB_ACKACT_Msk          (_UINT32_(0x1) << SERCOM_I2CS_CTRLB_ACKACT_Pos)      /* (SERCOM_I2CS_CTRLB) Acknowledge Action Mask */
603 #define SERCOM_I2CS_CTRLB_ACKACT(value)       (SERCOM_I2CS_CTRLB_ACKACT_Msk & (_UINT32_(value) << SERCOM_I2CS_CTRLB_ACKACT_Pos)) /* Assigment of value for ACKACT in the SERCOM_I2CS_CTRLB register */
604 #define SERCOM_I2CS_CTRLB_Msk                 _UINT32_(0x0007C300)                                 /* (SERCOM_I2CS_CTRLB) Register Mask  */
605 
606 
607 /* -------- SERCOM_SPIM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPIM Control B -------- */
608 #define SERCOM_SPIM_CTRLB_RESETVALUE          _UINT32_(0x00)                                       /*  (SERCOM_SPIM_CTRLB) SPIM Control B  Reset Value */
609 
610 #define SERCOM_SPIM_CTRLB_CHSIZE_Pos          _UINT32_(0)                                          /* (SERCOM_SPIM_CTRLB) Character Size Position */
611 #define SERCOM_SPIM_CTRLB_CHSIZE_Msk          (_UINT32_(0x7) << SERCOM_SPIM_CTRLB_CHSIZE_Pos)      /* (SERCOM_SPIM_CTRLB) Character Size Mask */
612 #define SERCOM_SPIM_CTRLB_CHSIZE(value)       (SERCOM_SPIM_CTRLB_CHSIZE_Msk & (_UINT32_(value) << SERCOM_SPIM_CTRLB_CHSIZE_Pos)) /* Assigment of value for CHSIZE in the SERCOM_SPIM_CTRLB register */
613 #define   SERCOM_SPIM_CTRLB_CHSIZE_8_BIT_Val  _UINT32_(0x0)                                        /* (SERCOM_SPIM_CTRLB) 8 bits  */
614 #define   SERCOM_SPIM_CTRLB_CHSIZE_9_BIT_Val  _UINT32_(0x1)                                        /* (SERCOM_SPIM_CTRLB) 9 bits  */
615 #define SERCOM_SPIM_CTRLB_CHSIZE_8_BIT        (SERCOM_SPIM_CTRLB_CHSIZE_8_BIT_Val << SERCOM_SPIM_CTRLB_CHSIZE_Pos) /* (SERCOM_SPIM_CTRLB) 8 bits Position  */
616 #define SERCOM_SPIM_CTRLB_CHSIZE_9_BIT        (SERCOM_SPIM_CTRLB_CHSIZE_9_BIT_Val << SERCOM_SPIM_CTRLB_CHSIZE_Pos) /* (SERCOM_SPIM_CTRLB) 9 bits Position  */
617 #define SERCOM_SPIM_CTRLB_PLOADEN_Pos         _UINT32_(6)                                          /* (SERCOM_SPIM_CTRLB) Data Preload Enable Position */
618 #define SERCOM_SPIM_CTRLB_PLOADEN_Msk         (_UINT32_(0x1) << SERCOM_SPIM_CTRLB_PLOADEN_Pos)     /* (SERCOM_SPIM_CTRLB) Data Preload Enable Mask */
619 #define SERCOM_SPIM_CTRLB_PLOADEN(value)      (SERCOM_SPIM_CTRLB_PLOADEN_Msk & (_UINT32_(value) << SERCOM_SPIM_CTRLB_PLOADEN_Pos)) /* Assigment of value for PLOADEN in the SERCOM_SPIM_CTRLB register */
620 #define SERCOM_SPIM_CTRLB_SSDE_Pos            _UINT32_(9)                                          /* (SERCOM_SPIM_CTRLB) Slave Select Low Detect Enable Position */
621 #define SERCOM_SPIM_CTRLB_SSDE_Msk            (_UINT32_(0x1) << SERCOM_SPIM_CTRLB_SSDE_Pos)        /* (SERCOM_SPIM_CTRLB) Slave Select Low Detect Enable Mask */
622 #define SERCOM_SPIM_CTRLB_SSDE(value)         (SERCOM_SPIM_CTRLB_SSDE_Msk & (_UINT32_(value) << SERCOM_SPIM_CTRLB_SSDE_Pos)) /* Assigment of value for SSDE in the SERCOM_SPIM_CTRLB register */
623 #define SERCOM_SPIM_CTRLB_AMODE_Pos           _UINT32_(14)                                         /* (SERCOM_SPIM_CTRLB) Address Mode Position */
624 #define SERCOM_SPIM_CTRLB_AMODE_Msk           (_UINT32_(0x3) << SERCOM_SPIM_CTRLB_AMODE_Pos)       /* (SERCOM_SPIM_CTRLB) Address Mode Mask */
625 #define SERCOM_SPIM_CTRLB_AMODE(value)        (SERCOM_SPIM_CTRLB_AMODE_Msk & (_UINT32_(value) << SERCOM_SPIM_CTRLB_AMODE_Pos)) /* Assigment of value for AMODE in the SERCOM_SPIM_CTRLB register */
626 #define   SERCOM_SPIM_CTRLB_AMODE_MASK_Val    _UINT32_(0x0)                                        /* (SERCOM_SPIM_CTRLB) SPI Address mask   */
627 #define   SERCOM_SPIM_CTRLB_AMODE_2_ADDRESSES_Val _UINT32_(0x1)                                        /* (SERCOM_SPIM_CTRLB) Two unique Addressess  */
628 #define   SERCOM_SPIM_CTRLB_AMODE_RANGE_Val   _UINT32_(0x2)                                        /* (SERCOM_SPIM_CTRLB) Address Range  */
629 #define SERCOM_SPIM_CTRLB_AMODE_MASK          (SERCOM_SPIM_CTRLB_AMODE_MASK_Val << SERCOM_SPIM_CTRLB_AMODE_Pos) /* (SERCOM_SPIM_CTRLB) SPI Address mask  Position  */
630 #define SERCOM_SPIM_CTRLB_AMODE_2_ADDRESSES   (SERCOM_SPIM_CTRLB_AMODE_2_ADDRESSES_Val << SERCOM_SPIM_CTRLB_AMODE_Pos) /* (SERCOM_SPIM_CTRLB) Two unique Addressess Position  */
631 #define SERCOM_SPIM_CTRLB_AMODE_RANGE         (SERCOM_SPIM_CTRLB_AMODE_RANGE_Val << SERCOM_SPIM_CTRLB_AMODE_Pos) /* (SERCOM_SPIM_CTRLB) Address Range Position  */
632 #define SERCOM_SPIM_CTRLB_RXEN_Pos            _UINT32_(17)                                         /* (SERCOM_SPIM_CTRLB) Receiver Enable Position */
633 #define SERCOM_SPIM_CTRLB_RXEN_Msk            (_UINT32_(0x1) << SERCOM_SPIM_CTRLB_RXEN_Pos)        /* (SERCOM_SPIM_CTRLB) Receiver Enable Mask */
634 #define SERCOM_SPIM_CTRLB_RXEN(value)         (SERCOM_SPIM_CTRLB_RXEN_Msk & (_UINT32_(value) << SERCOM_SPIM_CTRLB_RXEN_Pos)) /* Assigment of value for RXEN in the SERCOM_SPIM_CTRLB register */
635 #define SERCOM_SPIM_CTRLB_Msk                 _UINT32_(0x0002C247)                                 /* (SERCOM_SPIM_CTRLB) Register Mask  */
636 
637 
638 /* -------- SERCOM_SPIS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPIS Control B -------- */
639 #define SERCOM_SPIS_CTRLB_RESETVALUE          _UINT32_(0x00)                                       /*  (SERCOM_SPIS_CTRLB) SPIS Control B  Reset Value */
640 
641 #define SERCOM_SPIS_CTRLB_CHSIZE_Pos          _UINT32_(0)                                          /* (SERCOM_SPIS_CTRLB) Character Size Position */
642 #define SERCOM_SPIS_CTRLB_CHSIZE_Msk          (_UINT32_(0x7) << SERCOM_SPIS_CTRLB_CHSIZE_Pos)      /* (SERCOM_SPIS_CTRLB) Character Size Mask */
643 #define SERCOM_SPIS_CTRLB_CHSIZE(value)       (SERCOM_SPIS_CTRLB_CHSIZE_Msk & (_UINT32_(value) << SERCOM_SPIS_CTRLB_CHSIZE_Pos)) /* Assigment of value for CHSIZE in the SERCOM_SPIS_CTRLB register */
644 #define   SERCOM_SPIS_CTRLB_CHSIZE_8_BIT_Val  _UINT32_(0x0)                                        /* (SERCOM_SPIS_CTRLB) 8 bits  */
645 #define   SERCOM_SPIS_CTRLB_CHSIZE_9_BIT_Val  _UINT32_(0x1)                                        /* (SERCOM_SPIS_CTRLB) 9 bits  */
646 #define SERCOM_SPIS_CTRLB_CHSIZE_8_BIT        (SERCOM_SPIS_CTRLB_CHSIZE_8_BIT_Val << SERCOM_SPIS_CTRLB_CHSIZE_Pos) /* (SERCOM_SPIS_CTRLB) 8 bits Position  */
647 #define SERCOM_SPIS_CTRLB_CHSIZE_9_BIT        (SERCOM_SPIS_CTRLB_CHSIZE_9_BIT_Val << SERCOM_SPIS_CTRLB_CHSIZE_Pos) /* (SERCOM_SPIS_CTRLB) 9 bits Position  */
648 #define SERCOM_SPIS_CTRLB_PLOADEN_Pos         _UINT32_(6)                                          /* (SERCOM_SPIS_CTRLB) Data Preload Enable Position */
649 #define SERCOM_SPIS_CTRLB_PLOADEN_Msk         (_UINT32_(0x1) << SERCOM_SPIS_CTRLB_PLOADEN_Pos)     /* (SERCOM_SPIS_CTRLB) Data Preload Enable Mask */
650 #define SERCOM_SPIS_CTRLB_PLOADEN(value)      (SERCOM_SPIS_CTRLB_PLOADEN_Msk & (_UINT32_(value) << SERCOM_SPIS_CTRLB_PLOADEN_Pos)) /* Assigment of value for PLOADEN in the SERCOM_SPIS_CTRLB register */
651 #define SERCOM_SPIS_CTRLB_SSDE_Pos            _UINT32_(9)                                          /* (SERCOM_SPIS_CTRLB) Slave Select Low Detect Enable Position */
652 #define SERCOM_SPIS_CTRLB_SSDE_Msk            (_UINT32_(0x1) << SERCOM_SPIS_CTRLB_SSDE_Pos)        /* (SERCOM_SPIS_CTRLB) Slave Select Low Detect Enable Mask */
653 #define SERCOM_SPIS_CTRLB_SSDE(value)         (SERCOM_SPIS_CTRLB_SSDE_Msk & (_UINT32_(value) << SERCOM_SPIS_CTRLB_SSDE_Pos)) /* Assigment of value for SSDE in the SERCOM_SPIS_CTRLB register */
654 #define SERCOM_SPIS_CTRLB_AMODE_Pos           _UINT32_(14)                                         /* (SERCOM_SPIS_CTRLB) Address Mode Position */
655 #define SERCOM_SPIS_CTRLB_AMODE_Msk           (_UINT32_(0x3) << SERCOM_SPIS_CTRLB_AMODE_Pos)       /* (SERCOM_SPIS_CTRLB) Address Mode Mask */
656 #define SERCOM_SPIS_CTRLB_AMODE(value)        (SERCOM_SPIS_CTRLB_AMODE_Msk & (_UINT32_(value) << SERCOM_SPIS_CTRLB_AMODE_Pos)) /* Assigment of value for AMODE in the SERCOM_SPIS_CTRLB register */
657 #define   SERCOM_SPIS_CTRLB_AMODE_MASK_Val    _UINT32_(0x0)                                        /* (SERCOM_SPIS_CTRLB) SPI Address mask   */
658 #define   SERCOM_SPIS_CTRLB_AMODE_2_ADDRESSES_Val _UINT32_(0x1)                                        /* (SERCOM_SPIS_CTRLB) Two unique Addressess  */
659 #define   SERCOM_SPIS_CTRLB_AMODE_RANGE_Val   _UINT32_(0x2)                                        /* (SERCOM_SPIS_CTRLB) Address Range  */
660 #define SERCOM_SPIS_CTRLB_AMODE_MASK          (SERCOM_SPIS_CTRLB_AMODE_MASK_Val << SERCOM_SPIS_CTRLB_AMODE_Pos) /* (SERCOM_SPIS_CTRLB) SPI Address mask  Position  */
661 #define SERCOM_SPIS_CTRLB_AMODE_2_ADDRESSES   (SERCOM_SPIS_CTRLB_AMODE_2_ADDRESSES_Val << SERCOM_SPIS_CTRLB_AMODE_Pos) /* (SERCOM_SPIS_CTRLB) Two unique Addressess Position  */
662 #define SERCOM_SPIS_CTRLB_AMODE_RANGE         (SERCOM_SPIS_CTRLB_AMODE_RANGE_Val << SERCOM_SPIS_CTRLB_AMODE_Pos) /* (SERCOM_SPIS_CTRLB) Address Range Position  */
663 #define SERCOM_SPIS_CTRLB_RXEN_Pos            _UINT32_(17)                                         /* (SERCOM_SPIS_CTRLB) Receiver Enable Position */
664 #define SERCOM_SPIS_CTRLB_RXEN_Msk            (_UINT32_(0x1) << SERCOM_SPIS_CTRLB_RXEN_Pos)        /* (SERCOM_SPIS_CTRLB) Receiver Enable Mask */
665 #define SERCOM_SPIS_CTRLB_RXEN(value)         (SERCOM_SPIS_CTRLB_RXEN_Msk & (_UINT32_(value) << SERCOM_SPIS_CTRLB_RXEN_Pos)) /* Assigment of value for RXEN in the SERCOM_SPIS_CTRLB register */
666 #define SERCOM_SPIS_CTRLB_Msk                 _UINT32_(0x0002C247)                                 /* (SERCOM_SPIS_CTRLB) Register Mask  */
667 
668 
669 /* -------- SERCOM_USART_EXT_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART_EXT Control B -------- */
670 #define SERCOM_USART_EXT_CTRLB_RESETVALUE     _UINT32_(0x00)                                       /*  (SERCOM_USART_EXT_CTRLB) USART_EXT Control B  Reset Value */
671 
672 #define SERCOM_USART_EXT_CTRLB_CHSIZE_Pos     _UINT32_(0)                                          /* (SERCOM_USART_EXT_CTRLB) Character Size Position */
673 #define SERCOM_USART_EXT_CTRLB_CHSIZE_Msk     (_UINT32_(0x7) << SERCOM_USART_EXT_CTRLB_CHSIZE_Pos) /* (SERCOM_USART_EXT_CTRLB) Character Size Mask */
674 #define SERCOM_USART_EXT_CTRLB_CHSIZE(value)  (SERCOM_USART_EXT_CTRLB_CHSIZE_Msk & (_UINT32_(value) << SERCOM_USART_EXT_CTRLB_CHSIZE_Pos)) /* Assigment of value for CHSIZE in the SERCOM_USART_EXT_CTRLB register */
675 #define   SERCOM_USART_EXT_CTRLB_CHSIZE_8_BIT_Val _UINT32_(0x0)                                        /* (SERCOM_USART_EXT_CTRLB) 8 Bits  */
676 #define   SERCOM_USART_EXT_CTRLB_CHSIZE_9_BIT_Val _UINT32_(0x1)                                        /* (SERCOM_USART_EXT_CTRLB) 9 Bits  */
677 #define   SERCOM_USART_EXT_CTRLB_CHSIZE_5_BIT_Val _UINT32_(0x5)                                        /* (SERCOM_USART_EXT_CTRLB) 5 Bits  */
678 #define   SERCOM_USART_EXT_CTRLB_CHSIZE_6_BIT_Val _UINT32_(0x6)                                        /* (SERCOM_USART_EXT_CTRLB) 6 Bits  */
679 #define   SERCOM_USART_EXT_CTRLB_CHSIZE_7_BIT_Val _UINT32_(0x7)                                        /* (SERCOM_USART_EXT_CTRLB) 7 Bits  */
680 #define SERCOM_USART_EXT_CTRLB_CHSIZE_8_BIT   (SERCOM_USART_EXT_CTRLB_CHSIZE_8_BIT_Val << SERCOM_USART_EXT_CTRLB_CHSIZE_Pos) /* (SERCOM_USART_EXT_CTRLB) 8 Bits Position  */
681 #define SERCOM_USART_EXT_CTRLB_CHSIZE_9_BIT   (SERCOM_USART_EXT_CTRLB_CHSIZE_9_BIT_Val << SERCOM_USART_EXT_CTRLB_CHSIZE_Pos) /* (SERCOM_USART_EXT_CTRLB) 9 Bits Position  */
682 #define SERCOM_USART_EXT_CTRLB_CHSIZE_5_BIT   (SERCOM_USART_EXT_CTRLB_CHSIZE_5_BIT_Val << SERCOM_USART_EXT_CTRLB_CHSIZE_Pos) /* (SERCOM_USART_EXT_CTRLB) 5 Bits Position  */
683 #define SERCOM_USART_EXT_CTRLB_CHSIZE_6_BIT   (SERCOM_USART_EXT_CTRLB_CHSIZE_6_BIT_Val << SERCOM_USART_EXT_CTRLB_CHSIZE_Pos) /* (SERCOM_USART_EXT_CTRLB) 6 Bits Position  */
684 #define SERCOM_USART_EXT_CTRLB_CHSIZE_7_BIT   (SERCOM_USART_EXT_CTRLB_CHSIZE_7_BIT_Val << SERCOM_USART_EXT_CTRLB_CHSIZE_Pos) /* (SERCOM_USART_EXT_CTRLB) 7 Bits Position  */
685 #define SERCOM_USART_EXT_CTRLB_SBMODE_Pos     _UINT32_(6)                                          /* (SERCOM_USART_EXT_CTRLB) Stop Bit Mode Position */
686 #define SERCOM_USART_EXT_CTRLB_SBMODE_Msk     (_UINT32_(0x1) << SERCOM_USART_EXT_CTRLB_SBMODE_Pos) /* (SERCOM_USART_EXT_CTRLB) Stop Bit Mode Mask */
687 #define SERCOM_USART_EXT_CTRLB_SBMODE(value)  (SERCOM_USART_EXT_CTRLB_SBMODE_Msk & (_UINT32_(value) << SERCOM_USART_EXT_CTRLB_SBMODE_Pos)) /* Assigment of value for SBMODE in the SERCOM_USART_EXT_CTRLB register */
688 #define   SERCOM_USART_EXT_CTRLB_SBMODE_1_BIT_Val _UINT32_(0x0)                                        /* (SERCOM_USART_EXT_CTRLB) One Stop Bit  */
689 #define   SERCOM_USART_EXT_CTRLB_SBMODE_2_BIT_Val _UINT32_(0x1)                                        /* (SERCOM_USART_EXT_CTRLB) Two Stop Bits  */
690 #define SERCOM_USART_EXT_CTRLB_SBMODE_1_BIT   (SERCOM_USART_EXT_CTRLB_SBMODE_1_BIT_Val << SERCOM_USART_EXT_CTRLB_SBMODE_Pos) /* (SERCOM_USART_EXT_CTRLB) One Stop Bit Position  */
691 #define SERCOM_USART_EXT_CTRLB_SBMODE_2_BIT   (SERCOM_USART_EXT_CTRLB_SBMODE_2_BIT_Val << SERCOM_USART_EXT_CTRLB_SBMODE_Pos) /* (SERCOM_USART_EXT_CTRLB) Two Stop Bits Position  */
692 #define SERCOM_USART_EXT_CTRLB_COLDEN_Pos     _UINT32_(8)                                          /* (SERCOM_USART_EXT_CTRLB) Collision Detection Enable Position */
693 #define SERCOM_USART_EXT_CTRLB_COLDEN_Msk     (_UINT32_(0x1) << SERCOM_USART_EXT_CTRLB_COLDEN_Pos) /* (SERCOM_USART_EXT_CTRLB) Collision Detection Enable Mask */
694 #define SERCOM_USART_EXT_CTRLB_COLDEN(value)  (SERCOM_USART_EXT_CTRLB_COLDEN_Msk & (_UINT32_(value) << SERCOM_USART_EXT_CTRLB_COLDEN_Pos)) /* Assigment of value for COLDEN in the SERCOM_USART_EXT_CTRLB register */
695 #define SERCOM_USART_EXT_CTRLB_SFDE_Pos       _UINT32_(9)                                          /* (SERCOM_USART_EXT_CTRLB) Start of Frame Detection Enable Position */
696 #define SERCOM_USART_EXT_CTRLB_SFDE_Msk       (_UINT32_(0x1) << SERCOM_USART_EXT_CTRLB_SFDE_Pos)   /* (SERCOM_USART_EXT_CTRLB) Start of Frame Detection Enable Mask */
697 #define SERCOM_USART_EXT_CTRLB_SFDE(value)    (SERCOM_USART_EXT_CTRLB_SFDE_Msk & (_UINT32_(value) << SERCOM_USART_EXT_CTRLB_SFDE_Pos)) /* Assigment of value for SFDE in the SERCOM_USART_EXT_CTRLB register */
698 #define SERCOM_USART_EXT_CTRLB_ENC_Pos        _UINT32_(10)                                         /* (SERCOM_USART_EXT_CTRLB) Encoding Format Position */
699 #define SERCOM_USART_EXT_CTRLB_ENC_Msk        (_UINT32_(0x1) << SERCOM_USART_EXT_CTRLB_ENC_Pos)    /* (SERCOM_USART_EXT_CTRLB) Encoding Format Mask */
700 #define SERCOM_USART_EXT_CTRLB_ENC(value)     (SERCOM_USART_EXT_CTRLB_ENC_Msk & (_UINT32_(value) << SERCOM_USART_EXT_CTRLB_ENC_Pos)) /* Assigment of value for ENC in the SERCOM_USART_EXT_CTRLB register */
701 #define SERCOM_USART_EXT_CTRLB_PMODE_Pos      _UINT32_(13)                                         /* (SERCOM_USART_EXT_CTRLB) Parity Mode Position */
702 #define SERCOM_USART_EXT_CTRLB_PMODE_Msk      (_UINT32_(0x1) << SERCOM_USART_EXT_CTRLB_PMODE_Pos)  /* (SERCOM_USART_EXT_CTRLB) Parity Mode Mask */
703 #define SERCOM_USART_EXT_CTRLB_PMODE(value)   (SERCOM_USART_EXT_CTRLB_PMODE_Msk & (_UINT32_(value) << SERCOM_USART_EXT_CTRLB_PMODE_Pos)) /* Assigment of value for PMODE in the SERCOM_USART_EXT_CTRLB register */
704 #define   SERCOM_USART_EXT_CTRLB_PMODE_EVEN_Val _UINT32_(0x0)                                        /* (SERCOM_USART_EXT_CTRLB) Even Parity  */
705 #define   SERCOM_USART_EXT_CTRLB_PMODE_ODD_Val _UINT32_(0x1)                                        /* (SERCOM_USART_EXT_CTRLB) Odd Parity  */
706 #define SERCOM_USART_EXT_CTRLB_PMODE_EVEN     (SERCOM_USART_EXT_CTRLB_PMODE_EVEN_Val << SERCOM_USART_EXT_CTRLB_PMODE_Pos) /* (SERCOM_USART_EXT_CTRLB) Even Parity Position  */
707 #define SERCOM_USART_EXT_CTRLB_PMODE_ODD      (SERCOM_USART_EXT_CTRLB_PMODE_ODD_Val << SERCOM_USART_EXT_CTRLB_PMODE_Pos) /* (SERCOM_USART_EXT_CTRLB) Odd Parity Position  */
708 #define SERCOM_USART_EXT_CTRLB_TXEN_Pos       _UINT32_(16)                                         /* (SERCOM_USART_EXT_CTRLB) Transmitter Enable Position */
709 #define SERCOM_USART_EXT_CTRLB_TXEN_Msk       (_UINT32_(0x1) << SERCOM_USART_EXT_CTRLB_TXEN_Pos)   /* (SERCOM_USART_EXT_CTRLB) Transmitter Enable Mask */
710 #define SERCOM_USART_EXT_CTRLB_TXEN(value)    (SERCOM_USART_EXT_CTRLB_TXEN_Msk & (_UINT32_(value) << SERCOM_USART_EXT_CTRLB_TXEN_Pos)) /* Assigment of value for TXEN in the SERCOM_USART_EXT_CTRLB register */
711 #define SERCOM_USART_EXT_CTRLB_RXEN_Pos       _UINT32_(17)                                         /* (SERCOM_USART_EXT_CTRLB) Receiver Enable Position */
712 #define SERCOM_USART_EXT_CTRLB_RXEN_Msk       (_UINT32_(0x1) << SERCOM_USART_EXT_CTRLB_RXEN_Pos)   /* (SERCOM_USART_EXT_CTRLB) Receiver Enable Mask */
713 #define SERCOM_USART_EXT_CTRLB_RXEN(value)    (SERCOM_USART_EXT_CTRLB_RXEN_Msk & (_UINT32_(value) << SERCOM_USART_EXT_CTRLB_RXEN_Pos)) /* Assigment of value for RXEN in the SERCOM_USART_EXT_CTRLB register */
714 #define SERCOM_USART_EXT_CTRLB_LINCMD_Pos     _UINT32_(24)                                         /* (SERCOM_USART_EXT_CTRLB) LIN Command Position */
715 #define SERCOM_USART_EXT_CTRLB_LINCMD_Msk     (_UINT32_(0x3) << SERCOM_USART_EXT_CTRLB_LINCMD_Pos) /* (SERCOM_USART_EXT_CTRLB) LIN Command Mask */
716 #define SERCOM_USART_EXT_CTRLB_LINCMD(value)  (SERCOM_USART_EXT_CTRLB_LINCMD_Msk & (_UINT32_(value) << SERCOM_USART_EXT_CTRLB_LINCMD_Pos)) /* Assigment of value for LINCMD in the SERCOM_USART_EXT_CTRLB register */
717 #define   SERCOM_USART_EXT_CTRLB_LINCMD_NONE_Val _UINT32_(0x0)                                        /* (SERCOM_USART_EXT_CTRLB) Normal USART transmission  */
718 #define   SERCOM_USART_EXT_CTRLB_LINCMD_SOFTWARE_CONTROL_TRANSMIT_CMD_Val _UINT32_(0x1)                                        /* (SERCOM_USART_EXT_CTRLB) Break field is transmitted when DATA is written  */
719 #define   SERCOM_USART_EXT_CTRLB_LINCMD_AUTO_TRANSMIT_CMD_Val _UINT32_(0x2)                                        /* (SERCOM_USART_EXT_CTRLB) Break, sync and identifier are automatically transmitted when DATA is written with the identifier  */
720 #define SERCOM_USART_EXT_CTRLB_LINCMD_NONE    (SERCOM_USART_EXT_CTRLB_LINCMD_NONE_Val << SERCOM_USART_EXT_CTRLB_LINCMD_Pos) /* (SERCOM_USART_EXT_CTRLB) Normal USART transmission Position  */
721 #define SERCOM_USART_EXT_CTRLB_LINCMD_SOFTWARE_CONTROL_TRANSMIT_CMD (SERCOM_USART_EXT_CTRLB_LINCMD_SOFTWARE_CONTROL_TRANSMIT_CMD_Val << SERCOM_USART_EXT_CTRLB_LINCMD_Pos) /* (SERCOM_USART_EXT_CTRLB) Break field is transmitted when DATA is written Position  */
722 #define SERCOM_USART_EXT_CTRLB_LINCMD_AUTO_TRANSMIT_CMD (SERCOM_USART_EXT_CTRLB_LINCMD_AUTO_TRANSMIT_CMD_Val << SERCOM_USART_EXT_CTRLB_LINCMD_Pos) /* (SERCOM_USART_EXT_CTRLB) Break, sync and identifier are automatically transmitted when DATA is written with the identifier Position  */
723 #define SERCOM_USART_EXT_CTRLB_Msk            _UINT32_(0x03032747)                                 /* (SERCOM_USART_EXT_CTRLB) Register Mask  */
724 
725 
726 /* -------- SERCOM_USART_INT_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART_INT Control B -------- */
727 #define SERCOM_USART_INT_CTRLB_RESETVALUE     _UINT32_(0x00)                                       /*  (SERCOM_USART_INT_CTRLB) USART_INT Control B  Reset Value */
728 
729 #define SERCOM_USART_INT_CTRLB_CHSIZE_Pos     _UINT32_(0)                                          /* (SERCOM_USART_INT_CTRLB) Character Size Position */
730 #define SERCOM_USART_INT_CTRLB_CHSIZE_Msk     (_UINT32_(0x7) << SERCOM_USART_INT_CTRLB_CHSIZE_Pos) /* (SERCOM_USART_INT_CTRLB) Character Size Mask */
731 #define SERCOM_USART_INT_CTRLB_CHSIZE(value)  (SERCOM_USART_INT_CTRLB_CHSIZE_Msk & (_UINT32_(value) << SERCOM_USART_INT_CTRLB_CHSIZE_Pos)) /* Assigment of value for CHSIZE in the SERCOM_USART_INT_CTRLB register */
732 #define   SERCOM_USART_INT_CTRLB_CHSIZE_8_BIT_Val _UINT32_(0x0)                                        /* (SERCOM_USART_INT_CTRLB) 8 Bits  */
733 #define   SERCOM_USART_INT_CTRLB_CHSIZE_9_BIT_Val _UINT32_(0x1)                                        /* (SERCOM_USART_INT_CTRLB) 9 Bits  */
734 #define   SERCOM_USART_INT_CTRLB_CHSIZE_5_BIT_Val _UINT32_(0x5)                                        /* (SERCOM_USART_INT_CTRLB) 5 Bits  */
735 #define   SERCOM_USART_INT_CTRLB_CHSIZE_6_BIT_Val _UINT32_(0x6)                                        /* (SERCOM_USART_INT_CTRLB) 6 Bits  */
736 #define   SERCOM_USART_INT_CTRLB_CHSIZE_7_BIT_Val _UINT32_(0x7)                                        /* (SERCOM_USART_INT_CTRLB) 7 Bits  */
737 #define SERCOM_USART_INT_CTRLB_CHSIZE_8_BIT   (SERCOM_USART_INT_CTRLB_CHSIZE_8_BIT_Val << SERCOM_USART_INT_CTRLB_CHSIZE_Pos) /* (SERCOM_USART_INT_CTRLB) 8 Bits Position  */
738 #define SERCOM_USART_INT_CTRLB_CHSIZE_9_BIT   (SERCOM_USART_INT_CTRLB_CHSIZE_9_BIT_Val << SERCOM_USART_INT_CTRLB_CHSIZE_Pos) /* (SERCOM_USART_INT_CTRLB) 9 Bits Position  */
739 #define SERCOM_USART_INT_CTRLB_CHSIZE_5_BIT   (SERCOM_USART_INT_CTRLB_CHSIZE_5_BIT_Val << SERCOM_USART_INT_CTRLB_CHSIZE_Pos) /* (SERCOM_USART_INT_CTRLB) 5 Bits Position  */
740 #define SERCOM_USART_INT_CTRLB_CHSIZE_6_BIT   (SERCOM_USART_INT_CTRLB_CHSIZE_6_BIT_Val << SERCOM_USART_INT_CTRLB_CHSIZE_Pos) /* (SERCOM_USART_INT_CTRLB) 6 Bits Position  */
741 #define SERCOM_USART_INT_CTRLB_CHSIZE_7_BIT   (SERCOM_USART_INT_CTRLB_CHSIZE_7_BIT_Val << SERCOM_USART_INT_CTRLB_CHSIZE_Pos) /* (SERCOM_USART_INT_CTRLB) 7 Bits Position  */
742 #define SERCOM_USART_INT_CTRLB_SBMODE_Pos     _UINT32_(6)                                          /* (SERCOM_USART_INT_CTRLB) Stop Bit Mode Position */
743 #define SERCOM_USART_INT_CTRLB_SBMODE_Msk     (_UINT32_(0x1) << SERCOM_USART_INT_CTRLB_SBMODE_Pos) /* (SERCOM_USART_INT_CTRLB) Stop Bit Mode Mask */
744 #define SERCOM_USART_INT_CTRLB_SBMODE(value)  (SERCOM_USART_INT_CTRLB_SBMODE_Msk & (_UINT32_(value) << SERCOM_USART_INT_CTRLB_SBMODE_Pos)) /* Assigment of value for SBMODE in the SERCOM_USART_INT_CTRLB register */
745 #define   SERCOM_USART_INT_CTRLB_SBMODE_1_BIT_Val _UINT32_(0x0)                                        /* (SERCOM_USART_INT_CTRLB) One Stop Bit  */
746 #define   SERCOM_USART_INT_CTRLB_SBMODE_2_BIT_Val _UINT32_(0x1)                                        /* (SERCOM_USART_INT_CTRLB) Two Stop Bits  */
747 #define SERCOM_USART_INT_CTRLB_SBMODE_1_BIT   (SERCOM_USART_INT_CTRLB_SBMODE_1_BIT_Val << SERCOM_USART_INT_CTRLB_SBMODE_Pos) /* (SERCOM_USART_INT_CTRLB) One Stop Bit Position  */
748 #define SERCOM_USART_INT_CTRLB_SBMODE_2_BIT   (SERCOM_USART_INT_CTRLB_SBMODE_2_BIT_Val << SERCOM_USART_INT_CTRLB_SBMODE_Pos) /* (SERCOM_USART_INT_CTRLB) Two Stop Bits Position  */
749 #define SERCOM_USART_INT_CTRLB_COLDEN_Pos     _UINT32_(8)                                          /* (SERCOM_USART_INT_CTRLB) Collision Detection Enable Position */
750 #define SERCOM_USART_INT_CTRLB_COLDEN_Msk     (_UINT32_(0x1) << SERCOM_USART_INT_CTRLB_COLDEN_Pos) /* (SERCOM_USART_INT_CTRLB) Collision Detection Enable Mask */
751 #define SERCOM_USART_INT_CTRLB_COLDEN(value)  (SERCOM_USART_INT_CTRLB_COLDEN_Msk & (_UINT32_(value) << SERCOM_USART_INT_CTRLB_COLDEN_Pos)) /* Assigment of value for COLDEN in the SERCOM_USART_INT_CTRLB register */
752 #define SERCOM_USART_INT_CTRLB_SFDE_Pos       _UINT32_(9)                                          /* (SERCOM_USART_INT_CTRLB) Start of Frame Detection Enable Position */
753 #define SERCOM_USART_INT_CTRLB_SFDE_Msk       (_UINT32_(0x1) << SERCOM_USART_INT_CTRLB_SFDE_Pos)   /* (SERCOM_USART_INT_CTRLB) Start of Frame Detection Enable Mask */
754 #define SERCOM_USART_INT_CTRLB_SFDE(value)    (SERCOM_USART_INT_CTRLB_SFDE_Msk & (_UINT32_(value) << SERCOM_USART_INT_CTRLB_SFDE_Pos)) /* Assigment of value for SFDE in the SERCOM_USART_INT_CTRLB register */
755 #define SERCOM_USART_INT_CTRLB_ENC_Pos        _UINT32_(10)                                         /* (SERCOM_USART_INT_CTRLB) Encoding Format Position */
756 #define SERCOM_USART_INT_CTRLB_ENC_Msk        (_UINT32_(0x1) << SERCOM_USART_INT_CTRLB_ENC_Pos)    /* (SERCOM_USART_INT_CTRLB) Encoding Format Mask */
757 #define SERCOM_USART_INT_CTRLB_ENC(value)     (SERCOM_USART_INT_CTRLB_ENC_Msk & (_UINT32_(value) << SERCOM_USART_INT_CTRLB_ENC_Pos)) /* Assigment of value for ENC in the SERCOM_USART_INT_CTRLB register */
758 #define SERCOM_USART_INT_CTRLB_PMODE_Pos      _UINT32_(13)                                         /* (SERCOM_USART_INT_CTRLB) Parity Mode Position */
759 #define SERCOM_USART_INT_CTRLB_PMODE_Msk      (_UINT32_(0x1) << SERCOM_USART_INT_CTRLB_PMODE_Pos)  /* (SERCOM_USART_INT_CTRLB) Parity Mode Mask */
760 #define SERCOM_USART_INT_CTRLB_PMODE(value)   (SERCOM_USART_INT_CTRLB_PMODE_Msk & (_UINT32_(value) << SERCOM_USART_INT_CTRLB_PMODE_Pos)) /* Assigment of value for PMODE in the SERCOM_USART_INT_CTRLB register */
761 #define   SERCOM_USART_INT_CTRLB_PMODE_EVEN_Val _UINT32_(0x0)                                        /* (SERCOM_USART_INT_CTRLB) Even Parity  */
762 #define   SERCOM_USART_INT_CTRLB_PMODE_ODD_Val _UINT32_(0x1)                                        /* (SERCOM_USART_INT_CTRLB) Odd Parity  */
763 #define SERCOM_USART_INT_CTRLB_PMODE_EVEN     (SERCOM_USART_INT_CTRLB_PMODE_EVEN_Val << SERCOM_USART_INT_CTRLB_PMODE_Pos) /* (SERCOM_USART_INT_CTRLB) Even Parity Position  */
764 #define SERCOM_USART_INT_CTRLB_PMODE_ODD      (SERCOM_USART_INT_CTRLB_PMODE_ODD_Val << SERCOM_USART_INT_CTRLB_PMODE_Pos) /* (SERCOM_USART_INT_CTRLB) Odd Parity Position  */
765 #define SERCOM_USART_INT_CTRLB_TXEN_Pos       _UINT32_(16)                                         /* (SERCOM_USART_INT_CTRLB) Transmitter Enable Position */
766 #define SERCOM_USART_INT_CTRLB_TXEN_Msk       (_UINT32_(0x1) << SERCOM_USART_INT_CTRLB_TXEN_Pos)   /* (SERCOM_USART_INT_CTRLB) Transmitter Enable Mask */
767 #define SERCOM_USART_INT_CTRLB_TXEN(value)    (SERCOM_USART_INT_CTRLB_TXEN_Msk & (_UINT32_(value) << SERCOM_USART_INT_CTRLB_TXEN_Pos)) /* Assigment of value for TXEN in the SERCOM_USART_INT_CTRLB register */
768 #define SERCOM_USART_INT_CTRLB_RXEN_Pos       _UINT32_(17)                                         /* (SERCOM_USART_INT_CTRLB) Receiver Enable Position */
769 #define SERCOM_USART_INT_CTRLB_RXEN_Msk       (_UINT32_(0x1) << SERCOM_USART_INT_CTRLB_RXEN_Pos)   /* (SERCOM_USART_INT_CTRLB) Receiver Enable Mask */
770 #define SERCOM_USART_INT_CTRLB_RXEN(value)    (SERCOM_USART_INT_CTRLB_RXEN_Msk & (_UINT32_(value) << SERCOM_USART_INT_CTRLB_RXEN_Pos)) /* Assigment of value for RXEN in the SERCOM_USART_INT_CTRLB register */
771 #define SERCOM_USART_INT_CTRLB_LINCMD_Pos     _UINT32_(24)                                         /* (SERCOM_USART_INT_CTRLB) LIN Command Position */
772 #define SERCOM_USART_INT_CTRLB_LINCMD_Msk     (_UINT32_(0x3) << SERCOM_USART_INT_CTRLB_LINCMD_Pos) /* (SERCOM_USART_INT_CTRLB) LIN Command Mask */
773 #define SERCOM_USART_INT_CTRLB_LINCMD(value)  (SERCOM_USART_INT_CTRLB_LINCMD_Msk & (_UINT32_(value) << SERCOM_USART_INT_CTRLB_LINCMD_Pos)) /* Assigment of value for LINCMD in the SERCOM_USART_INT_CTRLB register */
774 #define   SERCOM_USART_INT_CTRLB_LINCMD_NONE_Val _UINT32_(0x0)                                        /* (SERCOM_USART_INT_CTRLB) Normal USART transmission  */
775 #define   SERCOM_USART_INT_CTRLB_LINCMD_SOFTWARE_CONTROL_TRANSMIT_CMD_Val _UINT32_(0x1)                                        /* (SERCOM_USART_INT_CTRLB) Break field is transmitted when DATA is written  */
776 #define   SERCOM_USART_INT_CTRLB_LINCMD_AUTO_TRANSMIT_CMD_Val _UINT32_(0x2)                                        /* (SERCOM_USART_INT_CTRLB) Break, sync and identifier are automatically transmitted when DATA is written with the identifier  */
777 #define SERCOM_USART_INT_CTRLB_LINCMD_NONE    (SERCOM_USART_INT_CTRLB_LINCMD_NONE_Val << SERCOM_USART_INT_CTRLB_LINCMD_Pos) /* (SERCOM_USART_INT_CTRLB) Normal USART transmission Position  */
778 #define SERCOM_USART_INT_CTRLB_LINCMD_SOFTWARE_CONTROL_TRANSMIT_CMD (SERCOM_USART_INT_CTRLB_LINCMD_SOFTWARE_CONTROL_TRANSMIT_CMD_Val << SERCOM_USART_INT_CTRLB_LINCMD_Pos) /* (SERCOM_USART_INT_CTRLB) Break field is transmitted when DATA is written Position  */
779 #define SERCOM_USART_INT_CTRLB_LINCMD_AUTO_TRANSMIT_CMD (SERCOM_USART_INT_CTRLB_LINCMD_AUTO_TRANSMIT_CMD_Val << SERCOM_USART_INT_CTRLB_LINCMD_Pos) /* (SERCOM_USART_INT_CTRLB) Break, sync and identifier are automatically transmitted when DATA is written with the identifier Position  */
780 #define SERCOM_USART_INT_CTRLB_Msk            _UINT32_(0x03032747)                                 /* (SERCOM_USART_INT_CTRLB) Register Mask  */
781 
782 
783 /* -------- SERCOM_I2CM_CTRLC : (SERCOM Offset: 0x08) (R/W 32) I2CM Control C -------- */
784 #define SERCOM_I2CM_CTRLC_RESETVALUE          _UINT32_(0x00)                                       /*  (SERCOM_I2CM_CTRLC) I2CM Control C  Reset Value */
785 
786 #define SERCOM_I2CM_CTRLC_DATA32B_Pos         _UINT32_(24)                                         /* (SERCOM_I2CM_CTRLC) Data 32 Bit Position */
787 #define SERCOM_I2CM_CTRLC_DATA32B_Msk         (_UINT32_(0x1) << SERCOM_I2CM_CTRLC_DATA32B_Pos)     /* (SERCOM_I2CM_CTRLC) Data 32 Bit Mask */
788 #define SERCOM_I2CM_CTRLC_DATA32B(value)      (SERCOM_I2CM_CTRLC_DATA32B_Msk & (_UINT32_(value) << SERCOM_I2CM_CTRLC_DATA32B_Pos)) /* Assigment of value for DATA32B in the SERCOM_I2CM_CTRLC register */
789 #define   SERCOM_I2CM_CTRLC_DATA32B_DATA_TRANS_8BIT_Val _UINT32_(0x0)                                        /* (SERCOM_I2CM_CTRLC) Data transaction from/to DATA register are 8-bit  */
790 #define   SERCOM_I2CM_CTRLC_DATA32B_DATA_TRANS_32BIT_Val _UINT32_(0x1)                                        /* (SERCOM_I2CM_CTRLC) Data transaction from/to DATA register are 32-bit  */
791 #define SERCOM_I2CM_CTRLC_DATA32B_DATA_TRANS_8BIT (SERCOM_I2CM_CTRLC_DATA32B_DATA_TRANS_8BIT_Val << SERCOM_I2CM_CTRLC_DATA32B_Pos) /* (SERCOM_I2CM_CTRLC) Data transaction from/to DATA register are 8-bit Position  */
792 #define SERCOM_I2CM_CTRLC_DATA32B_DATA_TRANS_32BIT (SERCOM_I2CM_CTRLC_DATA32B_DATA_TRANS_32BIT_Val << SERCOM_I2CM_CTRLC_DATA32B_Pos) /* (SERCOM_I2CM_CTRLC) Data transaction from/to DATA register are 32-bit Position  */
793 #define SERCOM_I2CM_CTRLC_Msk                 _UINT32_(0x01000000)                                 /* (SERCOM_I2CM_CTRLC) Register Mask  */
794 
795 
796 /* -------- SERCOM_I2CS_CTRLC : (SERCOM Offset: 0x08) (R/W 32) I2CS Control C -------- */
797 #define SERCOM_I2CS_CTRLC_RESETVALUE          _UINT32_(0x00)                                       /*  (SERCOM_I2CS_CTRLC) I2CS Control C  Reset Value */
798 
799 #define SERCOM_I2CS_CTRLC_SDASETUP_Pos        _UINT32_(0)                                          /* (SERCOM_I2CS_CTRLC) SDA Setup Time Position */
800 #define SERCOM_I2CS_CTRLC_SDASETUP_Msk        (_UINT32_(0xF) << SERCOM_I2CS_CTRLC_SDASETUP_Pos)    /* (SERCOM_I2CS_CTRLC) SDA Setup Time Mask */
801 #define SERCOM_I2CS_CTRLC_SDASETUP(value)     (SERCOM_I2CS_CTRLC_SDASETUP_Msk & (_UINT32_(value) << SERCOM_I2CS_CTRLC_SDASETUP_Pos)) /* Assigment of value for SDASETUP in the SERCOM_I2CS_CTRLC register */
802 #define SERCOM_I2CS_CTRLC_DATA32B_Pos         _UINT32_(24)                                         /* (SERCOM_I2CS_CTRLC) Data 32 Bit Position */
803 #define SERCOM_I2CS_CTRLC_DATA32B_Msk         (_UINT32_(0x1) << SERCOM_I2CS_CTRLC_DATA32B_Pos)     /* (SERCOM_I2CS_CTRLC) Data 32 Bit Mask */
804 #define SERCOM_I2CS_CTRLC_DATA32B(value)      (SERCOM_I2CS_CTRLC_DATA32B_Msk & (_UINT32_(value) << SERCOM_I2CS_CTRLC_DATA32B_Pos)) /* Assigment of value for DATA32B in the SERCOM_I2CS_CTRLC register */
805 #define   SERCOM_I2CS_CTRLC_DATA32B_DATA_TRANS_8BIT_Val _UINT32_(0x0)                                        /* (SERCOM_I2CS_CTRLC) Data transaction from/to DATA register are 8-bit  */
806 #define   SERCOM_I2CS_CTRLC_DATA32B_DATA_TRANS_32BIT_Val _UINT32_(0x1)                                        /* (SERCOM_I2CS_CTRLC) Data transaction from/to DATA register are 32-bit  */
807 #define SERCOM_I2CS_CTRLC_DATA32B_DATA_TRANS_8BIT (SERCOM_I2CS_CTRLC_DATA32B_DATA_TRANS_8BIT_Val << SERCOM_I2CS_CTRLC_DATA32B_Pos) /* (SERCOM_I2CS_CTRLC) Data transaction from/to DATA register are 8-bit Position  */
808 #define SERCOM_I2CS_CTRLC_DATA32B_DATA_TRANS_32BIT (SERCOM_I2CS_CTRLC_DATA32B_DATA_TRANS_32BIT_Val << SERCOM_I2CS_CTRLC_DATA32B_Pos) /* (SERCOM_I2CS_CTRLC) Data transaction from/to DATA register are 32-bit Position  */
809 #define SERCOM_I2CS_CTRLC_Msk                 _UINT32_(0x0100000F)                                 /* (SERCOM_I2CS_CTRLC) Register Mask  */
810 
811 
812 /* -------- SERCOM_SPIM_CTRLC : (SERCOM Offset: 0x08) (R/W 32) SPIM Control C -------- */
813 #define SERCOM_SPIM_CTRLC_RESETVALUE          _UINT32_(0x00)                                       /*  (SERCOM_SPIM_CTRLC) SPIM Control C  Reset Value */
814 
815 #define SERCOM_SPIM_CTRLC_ICSPACE_Pos         _UINT32_(0)                                          /* (SERCOM_SPIM_CTRLC) Inter-Character Spacing Position */
816 #define SERCOM_SPIM_CTRLC_ICSPACE_Msk         (_UINT32_(0x3F) << SERCOM_SPIM_CTRLC_ICSPACE_Pos)    /* (SERCOM_SPIM_CTRLC) Inter-Character Spacing Mask */
817 #define SERCOM_SPIM_CTRLC_ICSPACE(value)      (SERCOM_SPIM_CTRLC_ICSPACE_Msk & (_UINT32_(value) << SERCOM_SPIM_CTRLC_ICSPACE_Pos)) /* Assigment of value for ICSPACE in the SERCOM_SPIM_CTRLC register */
818 #define SERCOM_SPIM_CTRLC_DATA32B_Pos         _UINT32_(24)                                         /* (SERCOM_SPIM_CTRLC) Data 32 Bit Position */
819 #define SERCOM_SPIM_CTRLC_DATA32B_Msk         (_UINT32_(0x1) << SERCOM_SPIM_CTRLC_DATA32B_Pos)     /* (SERCOM_SPIM_CTRLC) Data 32 Bit Mask */
820 #define SERCOM_SPIM_CTRLC_DATA32B(value)      (SERCOM_SPIM_CTRLC_DATA32B_Msk & (_UINT32_(value) << SERCOM_SPIM_CTRLC_DATA32B_Pos)) /* Assigment of value for DATA32B in the SERCOM_SPIM_CTRLC register */
821 #define   SERCOM_SPIM_CTRLC_DATA32B_DATA_TRANS_8BIT_Val _UINT32_(0x0)                                        /* (SERCOM_SPIM_CTRLC) Transaction from and to DATA register are 8-bit  */
822 #define   SERCOM_SPIM_CTRLC_DATA32B_DATA_TRANS_32BIT_Val _UINT32_(0x1)                                        /* (SERCOM_SPIM_CTRLC) Transaction from and to DATA register are 32-bit  */
823 #define SERCOM_SPIM_CTRLC_DATA32B_DATA_TRANS_8BIT (SERCOM_SPIM_CTRLC_DATA32B_DATA_TRANS_8BIT_Val << SERCOM_SPIM_CTRLC_DATA32B_Pos) /* (SERCOM_SPIM_CTRLC) Transaction from and to DATA register are 8-bit Position  */
824 #define SERCOM_SPIM_CTRLC_DATA32B_DATA_TRANS_32BIT (SERCOM_SPIM_CTRLC_DATA32B_DATA_TRANS_32BIT_Val << SERCOM_SPIM_CTRLC_DATA32B_Pos) /* (SERCOM_SPIM_CTRLC) Transaction from and to DATA register are 32-bit Position  */
825 #define SERCOM_SPIM_CTRLC_Msk                 _UINT32_(0x0100003F)                                 /* (SERCOM_SPIM_CTRLC) Register Mask  */
826 
827 
828 /* -------- SERCOM_SPIS_CTRLC : (SERCOM Offset: 0x08) (R/W 32) SPIS Control C -------- */
829 #define SERCOM_SPIS_CTRLC_RESETVALUE          _UINT32_(0x00)                                       /*  (SERCOM_SPIS_CTRLC) SPIS Control C  Reset Value */
830 
831 #define SERCOM_SPIS_CTRLC_ICSPACE_Pos         _UINT32_(0)                                          /* (SERCOM_SPIS_CTRLC) Inter-Character Spacing Position */
832 #define SERCOM_SPIS_CTRLC_ICSPACE_Msk         (_UINT32_(0x3F) << SERCOM_SPIS_CTRLC_ICSPACE_Pos)    /* (SERCOM_SPIS_CTRLC) Inter-Character Spacing Mask */
833 #define SERCOM_SPIS_CTRLC_ICSPACE(value)      (SERCOM_SPIS_CTRLC_ICSPACE_Msk & (_UINT32_(value) << SERCOM_SPIS_CTRLC_ICSPACE_Pos)) /* Assigment of value for ICSPACE in the SERCOM_SPIS_CTRLC register */
834 #define SERCOM_SPIS_CTRLC_DATA32B_Pos         _UINT32_(24)                                         /* (SERCOM_SPIS_CTRLC) Data 32 Bit Position */
835 #define SERCOM_SPIS_CTRLC_DATA32B_Msk         (_UINT32_(0x1) << SERCOM_SPIS_CTRLC_DATA32B_Pos)     /* (SERCOM_SPIS_CTRLC) Data 32 Bit Mask */
836 #define SERCOM_SPIS_CTRLC_DATA32B(value)      (SERCOM_SPIS_CTRLC_DATA32B_Msk & (_UINT32_(value) << SERCOM_SPIS_CTRLC_DATA32B_Pos)) /* Assigment of value for DATA32B in the SERCOM_SPIS_CTRLC register */
837 #define   SERCOM_SPIS_CTRLC_DATA32B_DATA_TRANS_8BIT_Val _UINT32_(0x0)                                        /* (SERCOM_SPIS_CTRLC) Transaction from and to DATA register are 8-bit  */
838 #define   SERCOM_SPIS_CTRLC_DATA32B_DATA_TRANS_32BIT_Val _UINT32_(0x1)                                        /* (SERCOM_SPIS_CTRLC) Transaction from and to DATA register are 32-bit  */
839 #define SERCOM_SPIS_CTRLC_DATA32B_DATA_TRANS_8BIT (SERCOM_SPIS_CTRLC_DATA32B_DATA_TRANS_8BIT_Val << SERCOM_SPIS_CTRLC_DATA32B_Pos) /* (SERCOM_SPIS_CTRLC) Transaction from and to DATA register are 8-bit Position  */
840 #define SERCOM_SPIS_CTRLC_DATA32B_DATA_TRANS_32BIT (SERCOM_SPIS_CTRLC_DATA32B_DATA_TRANS_32BIT_Val << SERCOM_SPIS_CTRLC_DATA32B_Pos) /* (SERCOM_SPIS_CTRLC) Transaction from and to DATA register are 32-bit Position  */
841 #define SERCOM_SPIS_CTRLC_Msk                 _UINT32_(0x0100003F)                                 /* (SERCOM_SPIS_CTRLC) Register Mask  */
842 
843 
844 /* -------- SERCOM_USART_EXT_CTRLC : (SERCOM Offset: 0x08) (R/W 32) USART_EXT Control C -------- */
845 #define SERCOM_USART_EXT_CTRLC_RESETVALUE     _UINT32_(0x00)                                       /*  (SERCOM_USART_EXT_CTRLC) USART_EXT Control C  Reset Value */
846 
847 #define SERCOM_USART_EXT_CTRLC_GTIME_Pos      _UINT32_(0)                                          /* (SERCOM_USART_EXT_CTRLC) Guard Time Position */
848 #define SERCOM_USART_EXT_CTRLC_GTIME_Msk      (_UINT32_(0x7) << SERCOM_USART_EXT_CTRLC_GTIME_Pos)  /* (SERCOM_USART_EXT_CTRLC) Guard Time Mask */
849 #define SERCOM_USART_EXT_CTRLC_GTIME(value)   (SERCOM_USART_EXT_CTRLC_GTIME_Msk & (_UINT32_(value) << SERCOM_USART_EXT_CTRLC_GTIME_Pos)) /* Assigment of value for GTIME in the SERCOM_USART_EXT_CTRLC register */
850 #define SERCOM_USART_EXT_CTRLC_BRKLEN_Pos     _UINT32_(8)                                          /* (SERCOM_USART_EXT_CTRLC) LIN Master Break Length Position */
851 #define SERCOM_USART_EXT_CTRLC_BRKLEN_Msk     (_UINT32_(0x3) << SERCOM_USART_EXT_CTRLC_BRKLEN_Pos) /* (SERCOM_USART_EXT_CTRLC) LIN Master Break Length Mask */
852 #define SERCOM_USART_EXT_CTRLC_BRKLEN(value)  (SERCOM_USART_EXT_CTRLC_BRKLEN_Msk & (_UINT32_(value) << SERCOM_USART_EXT_CTRLC_BRKLEN_Pos)) /* Assigment of value for BRKLEN in the SERCOM_USART_EXT_CTRLC register */
853 #define   SERCOM_USART_EXT_CTRLC_BRKLEN_13_BIT_Val _UINT32_(0x0)                                        /* (SERCOM_USART_EXT_CTRLC) Break field transmission is 13 bit times  */
854 #define   SERCOM_USART_EXT_CTRLC_BRKLEN_17_BIT_Val _UINT32_(0x1)                                        /* (SERCOM_USART_EXT_CTRLC) Break field transmission is 17 bit times  */
855 #define   SERCOM_USART_EXT_CTRLC_BRKLEN_21_BIT_Val _UINT32_(0x2)                                        /* (SERCOM_USART_EXT_CTRLC) Break field transmission is 21 bit times  */
856 #define   SERCOM_USART_EXT_CTRLC_BRKLEN_26_BIT_Val _UINT32_(0x3)                                        /* (SERCOM_USART_EXT_CTRLC) Break field transmission is 26 bit times  */
857 #define SERCOM_USART_EXT_CTRLC_BRKLEN_13_BIT  (SERCOM_USART_EXT_CTRLC_BRKLEN_13_BIT_Val << SERCOM_USART_EXT_CTRLC_BRKLEN_Pos) /* (SERCOM_USART_EXT_CTRLC) Break field transmission is 13 bit times Position  */
858 #define SERCOM_USART_EXT_CTRLC_BRKLEN_17_BIT  (SERCOM_USART_EXT_CTRLC_BRKLEN_17_BIT_Val << SERCOM_USART_EXT_CTRLC_BRKLEN_Pos) /* (SERCOM_USART_EXT_CTRLC) Break field transmission is 17 bit times Position  */
859 #define SERCOM_USART_EXT_CTRLC_BRKLEN_21_BIT  (SERCOM_USART_EXT_CTRLC_BRKLEN_21_BIT_Val << SERCOM_USART_EXT_CTRLC_BRKLEN_Pos) /* (SERCOM_USART_EXT_CTRLC) Break field transmission is 21 bit times Position  */
860 #define SERCOM_USART_EXT_CTRLC_BRKLEN_26_BIT  (SERCOM_USART_EXT_CTRLC_BRKLEN_26_BIT_Val << SERCOM_USART_EXT_CTRLC_BRKLEN_Pos) /* (SERCOM_USART_EXT_CTRLC) Break field transmission is 26 bit times Position  */
861 #define SERCOM_USART_EXT_CTRLC_HDRDLY_Pos     _UINT32_(10)                                         /* (SERCOM_USART_EXT_CTRLC) LIN Master Header Delay Position */
862 #define SERCOM_USART_EXT_CTRLC_HDRDLY_Msk     (_UINT32_(0x3) << SERCOM_USART_EXT_CTRLC_HDRDLY_Pos) /* (SERCOM_USART_EXT_CTRLC) LIN Master Header Delay Mask */
863 #define SERCOM_USART_EXT_CTRLC_HDRDLY(value)  (SERCOM_USART_EXT_CTRLC_HDRDLY_Msk & (_UINT32_(value) << SERCOM_USART_EXT_CTRLC_HDRDLY_Pos)) /* Assigment of value for HDRDLY in the SERCOM_USART_EXT_CTRLC register */
864 #define   SERCOM_USART_EXT_CTRLC_HDRDLY_DELAY0_Val _UINT32_(0x0)                                        /* (SERCOM_USART_EXT_CTRLC) Delay between break and sync transmission is 1 bit time; Delay between sync and ID transmission is 1 bit time  */
865 #define   SERCOM_USART_EXT_CTRLC_HDRDLY_DELAY1_Val _UINT32_(0x1)                                        /* (SERCOM_USART_EXT_CTRLC) Delay between break and sync transmission is 4 bit time; Delay between sync and ID transmission is 4 bit time  */
866 #define   SERCOM_USART_EXT_CTRLC_HDRDLY_DELAY2_Val _UINT32_(0x2)                                        /* (SERCOM_USART_EXT_CTRLC) Delay between break and sync transmission is 8 bit time; Delay between sync and ID transmission is 4 bit time  */
867 #define   SERCOM_USART_EXT_CTRLC_HDRDLY_DELAY3_Val _UINT32_(0x3)                                        /* (SERCOM_USART_EXT_CTRLC) Delay between break and sync transmission is 14 bit time; Delay between sync and ID transmission is 4 bit time  */
868 #define SERCOM_USART_EXT_CTRLC_HDRDLY_DELAY0  (SERCOM_USART_EXT_CTRLC_HDRDLY_DELAY0_Val << SERCOM_USART_EXT_CTRLC_HDRDLY_Pos) /* (SERCOM_USART_EXT_CTRLC) Delay between break and sync transmission is 1 bit time; Delay between sync and ID transmission is 1 bit time Position  */
869 #define SERCOM_USART_EXT_CTRLC_HDRDLY_DELAY1  (SERCOM_USART_EXT_CTRLC_HDRDLY_DELAY1_Val << SERCOM_USART_EXT_CTRLC_HDRDLY_Pos) /* (SERCOM_USART_EXT_CTRLC) Delay between break and sync transmission is 4 bit time; Delay between sync and ID transmission is 4 bit time Position  */
870 #define SERCOM_USART_EXT_CTRLC_HDRDLY_DELAY2  (SERCOM_USART_EXT_CTRLC_HDRDLY_DELAY2_Val << SERCOM_USART_EXT_CTRLC_HDRDLY_Pos) /* (SERCOM_USART_EXT_CTRLC) Delay between break and sync transmission is 8 bit time; Delay between sync and ID transmission is 4 bit time Position  */
871 #define SERCOM_USART_EXT_CTRLC_HDRDLY_DELAY3  (SERCOM_USART_EXT_CTRLC_HDRDLY_DELAY3_Val << SERCOM_USART_EXT_CTRLC_HDRDLY_Pos) /* (SERCOM_USART_EXT_CTRLC) Delay between break and sync transmission is 14 bit time; Delay between sync and ID transmission is 4 bit time Position  */
872 #define SERCOM_USART_EXT_CTRLC_INACK_Pos      _UINT32_(16)                                         /* (SERCOM_USART_EXT_CTRLC) Inhibit Not Acknowledge Position */
873 #define SERCOM_USART_EXT_CTRLC_INACK_Msk      (_UINT32_(0x1) << SERCOM_USART_EXT_CTRLC_INACK_Pos)  /* (SERCOM_USART_EXT_CTRLC) Inhibit Not Acknowledge Mask */
874 #define SERCOM_USART_EXT_CTRLC_INACK(value)   (SERCOM_USART_EXT_CTRLC_INACK_Msk & (_UINT32_(value) << SERCOM_USART_EXT_CTRLC_INACK_Pos)) /* Assigment of value for INACK in the SERCOM_USART_EXT_CTRLC register */
875 #define SERCOM_USART_EXT_CTRLC_DSNACK_Pos     _UINT32_(17)                                         /* (SERCOM_USART_EXT_CTRLC) Disable Successive NACK Position */
876 #define SERCOM_USART_EXT_CTRLC_DSNACK_Msk     (_UINT32_(0x1) << SERCOM_USART_EXT_CTRLC_DSNACK_Pos) /* (SERCOM_USART_EXT_CTRLC) Disable Successive NACK Mask */
877 #define SERCOM_USART_EXT_CTRLC_DSNACK(value)  (SERCOM_USART_EXT_CTRLC_DSNACK_Msk & (_UINT32_(value) << SERCOM_USART_EXT_CTRLC_DSNACK_Pos)) /* Assigment of value for DSNACK in the SERCOM_USART_EXT_CTRLC register */
878 #define SERCOM_USART_EXT_CTRLC_MAXITER_Pos    _UINT32_(20)                                         /* (SERCOM_USART_EXT_CTRLC) Maximum Iterations Position */
879 #define SERCOM_USART_EXT_CTRLC_MAXITER_Msk    (_UINT32_(0x7) << SERCOM_USART_EXT_CTRLC_MAXITER_Pos) /* (SERCOM_USART_EXT_CTRLC) Maximum Iterations Mask */
880 #define SERCOM_USART_EXT_CTRLC_MAXITER(value) (SERCOM_USART_EXT_CTRLC_MAXITER_Msk & (_UINT32_(value) << SERCOM_USART_EXT_CTRLC_MAXITER_Pos)) /* Assigment of value for MAXITER in the SERCOM_USART_EXT_CTRLC register */
881 #define SERCOM_USART_EXT_CTRLC_DATA32B_Pos    _UINT32_(24)                                         /* (SERCOM_USART_EXT_CTRLC) Data 32 Bit Position */
882 #define SERCOM_USART_EXT_CTRLC_DATA32B_Msk    (_UINT32_(0x3) << SERCOM_USART_EXT_CTRLC_DATA32B_Pos) /* (SERCOM_USART_EXT_CTRLC) Data 32 Bit Mask */
883 #define SERCOM_USART_EXT_CTRLC_DATA32B(value) (SERCOM_USART_EXT_CTRLC_DATA32B_Msk & (_UINT32_(value) << SERCOM_USART_EXT_CTRLC_DATA32B_Pos)) /* Assigment of value for DATA32B in the SERCOM_USART_EXT_CTRLC register */
884 #define   SERCOM_USART_EXT_CTRLC_DATA32B_DATA_READ_WRITE_CHSIZE_Val _UINT32_(0x0)                                        /* (SERCOM_USART_EXT_CTRLC) Data reads and writes according CTRLB.CHSIZE  */
885 #define   SERCOM_USART_EXT_CTRLC_DATA32B_DATA_READ_CHSIZE_WRITE_32BIT_Val _UINT32_(0x1)                                        /* (SERCOM_USART_EXT_CTRLC) Data reads according CTRLB.CHSIZE and writes according 32-bit extension  */
886 #define   SERCOM_USART_EXT_CTRLC_DATA32B_DATA_READ_32BIT_WRITE_CHSIZE_Val _UINT32_(0x2)                                        /* (SERCOM_USART_EXT_CTRLC) Data reads according 32-bit extension and writes according CTRLB.CHSIZE  */
887 #define   SERCOM_USART_EXT_CTRLC_DATA32B_DATA_READ_WRITE_32BIT_Val _UINT32_(0x3)                                        /* (SERCOM_USART_EXT_CTRLC) Data reads and writes according 32-bit extension  */
888 #define SERCOM_USART_EXT_CTRLC_DATA32B_DATA_READ_WRITE_CHSIZE (SERCOM_USART_EXT_CTRLC_DATA32B_DATA_READ_WRITE_CHSIZE_Val << SERCOM_USART_EXT_CTRLC_DATA32B_Pos) /* (SERCOM_USART_EXT_CTRLC) Data reads and writes according CTRLB.CHSIZE Position  */
889 #define SERCOM_USART_EXT_CTRLC_DATA32B_DATA_READ_CHSIZE_WRITE_32BIT (SERCOM_USART_EXT_CTRLC_DATA32B_DATA_READ_CHSIZE_WRITE_32BIT_Val << SERCOM_USART_EXT_CTRLC_DATA32B_Pos) /* (SERCOM_USART_EXT_CTRLC) Data reads according CTRLB.CHSIZE and writes according 32-bit extension Position  */
890 #define SERCOM_USART_EXT_CTRLC_DATA32B_DATA_READ_32BIT_WRITE_CHSIZE (SERCOM_USART_EXT_CTRLC_DATA32B_DATA_READ_32BIT_WRITE_CHSIZE_Val << SERCOM_USART_EXT_CTRLC_DATA32B_Pos) /* (SERCOM_USART_EXT_CTRLC) Data reads according 32-bit extension and writes according CTRLB.CHSIZE Position  */
891 #define SERCOM_USART_EXT_CTRLC_DATA32B_DATA_READ_WRITE_32BIT (SERCOM_USART_EXT_CTRLC_DATA32B_DATA_READ_WRITE_32BIT_Val << SERCOM_USART_EXT_CTRLC_DATA32B_Pos) /* (SERCOM_USART_EXT_CTRLC) Data reads and writes according 32-bit extension Position  */
892 #define SERCOM_USART_EXT_CTRLC_Msk            _UINT32_(0x03730F07)                                 /* (SERCOM_USART_EXT_CTRLC) Register Mask  */
893 
894 
895 /* -------- SERCOM_USART_INT_CTRLC : (SERCOM Offset: 0x08) (R/W 32) USART_INT Control C -------- */
896 #define SERCOM_USART_INT_CTRLC_RESETVALUE     _UINT32_(0x00)                                       /*  (SERCOM_USART_INT_CTRLC) USART_INT Control C  Reset Value */
897 
898 #define SERCOM_USART_INT_CTRLC_GTIME_Pos      _UINT32_(0)                                          /* (SERCOM_USART_INT_CTRLC) Guard Time Position */
899 #define SERCOM_USART_INT_CTRLC_GTIME_Msk      (_UINT32_(0x7) << SERCOM_USART_INT_CTRLC_GTIME_Pos)  /* (SERCOM_USART_INT_CTRLC) Guard Time Mask */
900 #define SERCOM_USART_INT_CTRLC_GTIME(value)   (SERCOM_USART_INT_CTRLC_GTIME_Msk & (_UINT32_(value) << SERCOM_USART_INT_CTRLC_GTIME_Pos)) /* Assigment of value for GTIME in the SERCOM_USART_INT_CTRLC register */
901 #define SERCOM_USART_INT_CTRLC_BRKLEN_Pos     _UINT32_(8)                                          /* (SERCOM_USART_INT_CTRLC) LIN Master Break Length Position */
902 #define SERCOM_USART_INT_CTRLC_BRKLEN_Msk     (_UINT32_(0x3) << SERCOM_USART_INT_CTRLC_BRKLEN_Pos) /* (SERCOM_USART_INT_CTRLC) LIN Master Break Length Mask */
903 #define SERCOM_USART_INT_CTRLC_BRKLEN(value)  (SERCOM_USART_INT_CTRLC_BRKLEN_Msk & (_UINT32_(value) << SERCOM_USART_INT_CTRLC_BRKLEN_Pos)) /* Assigment of value for BRKLEN in the SERCOM_USART_INT_CTRLC register */
904 #define   SERCOM_USART_INT_CTRLC_BRKLEN_13_BIT_Val _UINT32_(0x0)                                        /* (SERCOM_USART_INT_CTRLC) Break field transmission is 13 bit times  */
905 #define   SERCOM_USART_INT_CTRLC_BRKLEN_17_BIT_Val _UINT32_(0x1)                                        /* (SERCOM_USART_INT_CTRLC) Break field transmission is 17 bit times  */
906 #define   SERCOM_USART_INT_CTRLC_BRKLEN_21_BIT_Val _UINT32_(0x2)                                        /* (SERCOM_USART_INT_CTRLC) Break field transmission is 21 bit times  */
907 #define   SERCOM_USART_INT_CTRLC_BRKLEN_26_BIT_Val _UINT32_(0x3)                                        /* (SERCOM_USART_INT_CTRLC) Break field transmission is 26 bit times  */
908 #define SERCOM_USART_INT_CTRLC_BRKLEN_13_BIT  (SERCOM_USART_INT_CTRLC_BRKLEN_13_BIT_Val << SERCOM_USART_INT_CTRLC_BRKLEN_Pos) /* (SERCOM_USART_INT_CTRLC) Break field transmission is 13 bit times Position  */
909 #define SERCOM_USART_INT_CTRLC_BRKLEN_17_BIT  (SERCOM_USART_INT_CTRLC_BRKLEN_17_BIT_Val << SERCOM_USART_INT_CTRLC_BRKLEN_Pos) /* (SERCOM_USART_INT_CTRLC) Break field transmission is 17 bit times Position  */
910 #define SERCOM_USART_INT_CTRLC_BRKLEN_21_BIT  (SERCOM_USART_INT_CTRLC_BRKLEN_21_BIT_Val << SERCOM_USART_INT_CTRLC_BRKLEN_Pos) /* (SERCOM_USART_INT_CTRLC) Break field transmission is 21 bit times Position  */
911 #define SERCOM_USART_INT_CTRLC_BRKLEN_26_BIT  (SERCOM_USART_INT_CTRLC_BRKLEN_26_BIT_Val << SERCOM_USART_INT_CTRLC_BRKLEN_Pos) /* (SERCOM_USART_INT_CTRLC) Break field transmission is 26 bit times Position  */
912 #define SERCOM_USART_INT_CTRLC_HDRDLY_Pos     _UINT32_(10)                                         /* (SERCOM_USART_INT_CTRLC) LIN Master Header Delay Position */
913 #define SERCOM_USART_INT_CTRLC_HDRDLY_Msk     (_UINT32_(0x3) << SERCOM_USART_INT_CTRLC_HDRDLY_Pos) /* (SERCOM_USART_INT_CTRLC) LIN Master Header Delay Mask */
914 #define SERCOM_USART_INT_CTRLC_HDRDLY(value)  (SERCOM_USART_INT_CTRLC_HDRDLY_Msk & (_UINT32_(value) << SERCOM_USART_INT_CTRLC_HDRDLY_Pos)) /* Assigment of value for HDRDLY in the SERCOM_USART_INT_CTRLC register */
915 #define   SERCOM_USART_INT_CTRLC_HDRDLY_DELAY0_Val _UINT32_(0x0)                                        /* (SERCOM_USART_INT_CTRLC) Delay between break and sync transmission is 1 bit time; Delay between sync and ID transmission is 1 bit time  */
916 #define   SERCOM_USART_INT_CTRLC_HDRDLY_DELAY1_Val _UINT32_(0x1)                                        /* (SERCOM_USART_INT_CTRLC) Delay between break and sync transmission is 4 bit time; Delay between sync and ID transmission is 4 bit time  */
917 #define   SERCOM_USART_INT_CTRLC_HDRDLY_DELAY2_Val _UINT32_(0x2)                                        /* (SERCOM_USART_INT_CTRLC) Delay between break and sync transmission is 8 bit time; Delay between sync and ID transmission is 4 bit time  */
918 #define   SERCOM_USART_INT_CTRLC_HDRDLY_DELAY3_Val _UINT32_(0x3)                                        /* (SERCOM_USART_INT_CTRLC) Delay between break and sync transmission is 14 bit time; Delay between sync and ID transmission is 4 bit time  */
919 #define SERCOM_USART_INT_CTRLC_HDRDLY_DELAY0  (SERCOM_USART_INT_CTRLC_HDRDLY_DELAY0_Val << SERCOM_USART_INT_CTRLC_HDRDLY_Pos) /* (SERCOM_USART_INT_CTRLC) Delay between break and sync transmission is 1 bit time; Delay between sync and ID transmission is 1 bit time Position  */
920 #define SERCOM_USART_INT_CTRLC_HDRDLY_DELAY1  (SERCOM_USART_INT_CTRLC_HDRDLY_DELAY1_Val << SERCOM_USART_INT_CTRLC_HDRDLY_Pos) /* (SERCOM_USART_INT_CTRLC) Delay between break and sync transmission is 4 bit time; Delay between sync and ID transmission is 4 bit time Position  */
921 #define SERCOM_USART_INT_CTRLC_HDRDLY_DELAY2  (SERCOM_USART_INT_CTRLC_HDRDLY_DELAY2_Val << SERCOM_USART_INT_CTRLC_HDRDLY_Pos) /* (SERCOM_USART_INT_CTRLC) Delay between break and sync transmission is 8 bit time; Delay between sync and ID transmission is 4 bit time Position  */
922 #define SERCOM_USART_INT_CTRLC_HDRDLY_DELAY3  (SERCOM_USART_INT_CTRLC_HDRDLY_DELAY3_Val << SERCOM_USART_INT_CTRLC_HDRDLY_Pos) /* (SERCOM_USART_INT_CTRLC) Delay between break and sync transmission is 14 bit time; Delay between sync and ID transmission is 4 bit time Position  */
923 #define SERCOM_USART_INT_CTRLC_INACK_Pos      _UINT32_(16)                                         /* (SERCOM_USART_INT_CTRLC) Inhibit Not Acknowledge Position */
924 #define SERCOM_USART_INT_CTRLC_INACK_Msk      (_UINT32_(0x1) << SERCOM_USART_INT_CTRLC_INACK_Pos)  /* (SERCOM_USART_INT_CTRLC) Inhibit Not Acknowledge Mask */
925 #define SERCOM_USART_INT_CTRLC_INACK(value)   (SERCOM_USART_INT_CTRLC_INACK_Msk & (_UINT32_(value) << SERCOM_USART_INT_CTRLC_INACK_Pos)) /* Assigment of value for INACK in the SERCOM_USART_INT_CTRLC register */
926 #define SERCOM_USART_INT_CTRLC_DSNACK_Pos     _UINT32_(17)                                         /* (SERCOM_USART_INT_CTRLC) Disable Successive NACK Position */
927 #define SERCOM_USART_INT_CTRLC_DSNACK_Msk     (_UINT32_(0x1) << SERCOM_USART_INT_CTRLC_DSNACK_Pos) /* (SERCOM_USART_INT_CTRLC) Disable Successive NACK Mask */
928 #define SERCOM_USART_INT_CTRLC_DSNACK(value)  (SERCOM_USART_INT_CTRLC_DSNACK_Msk & (_UINT32_(value) << SERCOM_USART_INT_CTRLC_DSNACK_Pos)) /* Assigment of value for DSNACK in the SERCOM_USART_INT_CTRLC register */
929 #define SERCOM_USART_INT_CTRLC_MAXITER_Pos    _UINT32_(20)                                         /* (SERCOM_USART_INT_CTRLC) Maximum Iterations Position */
930 #define SERCOM_USART_INT_CTRLC_MAXITER_Msk    (_UINT32_(0x7) << SERCOM_USART_INT_CTRLC_MAXITER_Pos) /* (SERCOM_USART_INT_CTRLC) Maximum Iterations Mask */
931 #define SERCOM_USART_INT_CTRLC_MAXITER(value) (SERCOM_USART_INT_CTRLC_MAXITER_Msk & (_UINT32_(value) << SERCOM_USART_INT_CTRLC_MAXITER_Pos)) /* Assigment of value for MAXITER in the SERCOM_USART_INT_CTRLC register */
932 #define SERCOM_USART_INT_CTRLC_DATA32B_Pos    _UINT32_(24)                                         /* (SERCOM_USART_INT_CTRLC) Data 32 Bit Position */
933 #define SERCOM_USART_INT_CTRLC_DATA32B_Msk    (_UINT32_(0x3) << SERCOM_USART_INT_CTRLC_DATA32B_Pos) /* (SERCOM_USART_INT_CTRLC) Data 32 Bit Mask */
934 #define SERCOM_USART_INT_CTRLC_DATA32B(value) (SERCOM_USART_INT_CTRLC_DATA32B_Msk & (_UINT32_(value) << SERCOM_USART_INT_CTRLC_DATA32B_Pos)) /* Assigment of value for DATA32B in the SERCOM_USART_INT_CTRLC register */
935 #define   SERCOM_USART_INT_CTRLC_DATA32B_DATA_READ_WRITE_CHSIZE_Val _UINT32_(0x0)                                        /* (SERCOM_USART_INT_CTRLC) Data reads and writes according CTRLB.CHSIZE  */
936 #define   SERCOM_USART_INT_CTRLC_DATA32B_DATA_READ_CHSIZE_WRITE_32BIT_Val _UINT32_(0x1)                                        /* (SERCOM_USART_INT_CTRLC) Data reads according CTRLB.CHSIZE and writes according 32-bit extension  */
937 #define   SERCOM_USART_INT_CTRLC_DATA32B_DATA_READ_32BIT_WRITE_CHSIZE_Val _UINT32_(0x2)                                        /* (SERCOM_USART_INT_CTRLC) Data reads according 32-bit extension and writes according CTRLB.CHSIZE  */
938 #define   SERCOM_USART_INT_CTRLC_DATA32B_DATA_READ_WRITE_32BIT_Val _UINT32_(0x3)                                        /* (SERCOM_USART_INT_CTRLC) Data reads and writes according 32-bit extension  */
939 #define SERCOM_USART_INT_CTRLC_DATA32B_DATA_READ_WRITE_CHSIZE (SERCOM_USART_INT_CTRLC_DATA32B_DATA_READ_WRITE_CHSIZE_Val << SERCOM_USART_INT_CTRLC_DATA32B_Pos) /* (SERCOM_USART_INT_CTRLC) Data reads and writes according CTRLB.CHSIZE Position  */
940 #define SERCOM_USART_INT_CTRLC_DATA32B_DATA_READ_CHSIZE_WRITE_32BIT (SERCOM_USART_INT_CTRLC_DATA32B_DATA_READ_CHSIZE_WRITE_32BIT_Val << SERCOM_USART_INT_CTRLC_DATA32B_Pos) /* (SERCOM_USART_INT_CTRLC) Data reads according CTRLB.CHSIZE and writes according 32-bit extension Position  */
941 #define SERCOM_USART_INT_CTRLC_DATA32B_DATA_READ_32BIT_WRITE_CHSIZE (SERCOM_USART_INT_CTRLC_DATA32B_DATA_READ_32BIT_WRITE_CHSIZE_Val << SERCOM_USART_INT_CTRLC_DATA32B_Pos) /* (SERCOM_USART_INT_CTRLC) Data reads according 32-bit extension and writes according CTRLB.CHSIZE Position  */
942 #define SERCOM_USART_INT_CTRLC_DATA32B_DATA_READ_WRITE_32BIT (SERCOM_USART_INT_CTRLC_DATA32B_DATA_READ_WRITE_32BIT_Val << SERCOM_USART_INT_CTRLC_DATA32B_Pos) /* (SERCOM_USART_INT_CTRLC) Data reads and writes according 32-bit extension Position  */
943 #define SERCOM_USART_INT_CTRLC_Msk            _UINT32_(0x03730F07)                                 /* (SERCOM_USART_INT_CTRLC) Register Mask  */
944 
945 
946 /* -------- SERCOM_I2CM_BAUD : (SERCOM Offset: 0x0C) (R/W 32) I2CM Baud Rate -------- */
947 #define SERCOM_I2CM_BAUD_RESETVALUE           _UINT32_(0x00)                                       /*  (SERCOM_I2CM_BAUD) I2CM Baud Rate  Reset Value */
948 
949 #define SERCOM_I2CM_BAUD_BAUD_Pos             _UINT32_(0)                                          /* (SERCOM_I2CM_BAUD) Baud Rate Value Position */
950 #define SERCOM_I2CM_BAUD_BAUD_Msk             (_UINT32_(0xFF) << SERCOM_I2CM_BAUD_BAUD_Pos)        /* (SERCOM_I2CM_BAUD) Baud Rate Value Mask */
951 #define SERCOM_I2CM_BAUD_BAUD(value)          (SERCOM_I2CM_BAUD_BAUD_Msk & (_UINT32_(value) << SERCOM_I2CM_BAUD_BAUD_Pos)) /* Assigment of value for BAUD in the SERCOM_I2CM_BAUD register */
952 #define SERCOM_I2CM_BAUD_BAUDLOW_Pos          _UINT32_(8)                                          /* (SERCOM_I2CM_BAUD) Baud Rate Value Low Position */
953 #define SERCOM_I2CM_BAUD_BAUDLOW_Msk          (_UINT32_(0xFF) << SERCOM_I2CM_BAUD_BAUDLOW_Pos)     /* (SERCOM_I2CM_BAUD) Baud Rate Value Low Mask */
954 #define SERCOM_I2CM_BAUD_BAUDLOW(value)       (SERCOM_I2CM_BAUD_BAUDLOW_Msk & (_UINT32_(value) << SERCOM_I2CM_BAUD_BAUDLOW_Pos)) /* Assigment of value for BAUDLOW in the SERCOM_I2CM_BAUD register */
955 #define SERCOM_I2CM_BAUD_HSBAUD_Pos           _UINT32_(16)                                         /* (SERCOM_I2CM_BAUD) High Speed Baud Rate Value Position */
956 #define SERCOM_I2CM_BAUD_HSBAUD_Msk           (_UINT32_(0xFF) << SERCOM_I2CM_BAUD_HSBAUD_Pos)      /* (SERCOM_I2CM_BAUD) High Speed Baud Rate Value Mask */
957 #define SERCOM_I2CM_BAUD_HSBAUD(value)        (SERCOM_I2CM_BAUD_HSBAUD_Msk & (_UINT32_(value) << SERCOM_I2CM_BAUD_HSBAUD_Pos)) /* Assigment of value for HSBAUD in the SERCOM_I2CM_BAUD register */
958 #define SERCOM_I2CM_BAUD_HSBAUDLOW_Pos        _UINT32_(24)                                         /* (SERCOM_I2CM_BAUD) High Speed Baud Rate Value Low Position */
959 #define SERCOM_I2CM_BAUD_HSBAUDLOW_Msk        (_UINT32_(0xFF) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos)   /* (SERCOM_I2CM_BAUD) High Speed Baud Rate Value Low Mask */
960 #define SERCOM_I2CM_BAUD_HSBAUDLOW(value)     (SERCOM_I2CM_BAUD_HSBAUDLOW_Msk & (_UINT32_(value) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos)) /* Assigment of value for HSBAUDLOW in the SERCOM_I2CM_BAUD register */
961 #define SERCOM_I2CM_BAUD_Msk                  _UINT32_(0xFFFFFFFF)                                 /* (SERCOM_I2CM_BAUD) Register Mask  */
962 
963 
964 /* -------- SERCOM_SPIM_BAUD : (SERCOM Offset: 0x0C) (R/W 8) SPIM Baud Rate -------- */
965 #define SERCOM_SPIM_BAUD_RESETVALUE           _UINT8_(0x00)                                        /*  (SERCOM_SPIM_BAUD) SPIM Baud Rate  Reset Value */
966 
967 #define SERCOM_SPIM_BAUD_BAUD_Pos             _UINT8_(0)                                           /* (SERCOM_SPIM_BAUD) Baud Rate Value Position */
968 #define SERCOM_SPIM_BAUD_BAUD_Msk             (_UINT8_(0xFF) << SERCOM_SPIM_BAUD_BAUD_Pos)         /* (SERCOM_SPIM_BAUD) Baud Rate Value Mask */
969 #define SERCOM_SPIM_BAUD_BAUD(value)          (SERCOM_SPIM_BAUD_BAUD_Msk & (_UINT8_(value) << SERCOM_SPIM_BAUD_BAUD_Pos)) /* Assigment of value for BAUD in the SERCOM_SPIM_BAUD register */
970 #define SERCOM_SPIM_BAUD_Msk                  _UINT8_(0xFF)                                        /* (SERCOM_SPIM_BAUD) Register Mask  */
971 
972 
973 /* -------- SERCOM_SPIS_BAUD : (SERCOM Offset: 0x0C) (R/W 8) SPIS Baud Rate -------- */
974 #define SERCOM_SPIS_BAUD_RESETVALUE           _UINT8_(0x00)                                        /*  (SERCOM_SPIS_BAUD) SPIS Baud Rate  Reset Value */
975 
976 #define SERCOM_SPIS_BAUD_BAUD_Pos             _UINT8_(0)                                           /* (SERCOM_SPIS_BAUD) Baud Rate Value Position */
977 #define SERCOM_SPIS_BAUD_BAUD_Msk             (_UINT8_(0xFF) << SERCOM_SPIS_BAUD_BAUD_Pos)         /* (SERCOM_SPIS_BAUD) Baud Rate Value Mask */
978 #define SERCOM_SPIS_BAUD_BAUD(value)          (SERCOM_SPIS_BAUD_BAUD_Msk & (_UINT8_(value) << SERCOM_SPIS_BAUD_BAUD_Pos)) /* Assigment of value for BAUD in the SERCOM_SPIS_BAUD register */
979 #define SERCOM_SPIS_BAUD_Msk                  _UINT8_(0xFF)                                        /* (SERCOM_SPIS_BAUD) Register Mask  */
980 
981 
982 /* -------- SERCOM_USART_EXT_BAUD : (SERCOM Offset: 0x0C) (R/W 16) USART_EXT Baud Rate -------- */
983 #define SERCOM_USART_EXT_BAUD_RESETVALUE      _UINT16_(0x00)                                       /*  (SERCOM_USART_EXT_BAUD) USART_EXT Baud Rate  Reset Value */
984 
985 #define SERCOM_USART_EXT_BAUD_BAUD_Pos        _UINT16_(0)                                          /* (SERCOM_USART_EXT_BAUD) Baud Rate Value Position */
986 #define SERCOM_USART_EXT_BAUD_BAUD_Msk        (_UINT16_(0xFFFF) << SERCOM_USART_EXT_BAUD_BAUD_Pos) /* (SERCOM_USART_EXT_BAUD) Baud Rate Value Mask */
987 #define SERCOM_USART_EXT_BAUD_BAUD(value)     (SERCOM_USART_EXT_BAUD_BAUD_Msk & (_UINT16_(value) << SERCOM_USART_EXT_BAUD_BAUD_Pos)) /* Assigment of value for BAUD in the SERCOM_USART_EXT_BAUD register */
988 #define SERCOM_USART_EXT_BAUD_Msk             _UINT16_(0xFFFF)                                     /* (SERCOM_USART_EXT_BAUD) Register Mask  */
989 
990 /* FRAC mode */
991 #define SERCOM_USART_EXT_BAUD_FRAC_BAUD_Pos   _UINT16_(0)                                          /* (SERCOM_USART_EXT_BAUD) Baud Rate Value Position */
992 #define SERCOM_USART_EXT_BAUD_FRAC_BAUD_Msk   (_UINT16_(0x1FFF) << SERCOM_USART_EXT_BAUD_FRAC_BAUD_Pos) /* (SERCOM_USART_EXT_BAUD) Baud Rate Value Mask */
993 #define SERCOM_USART_EXT_BAUD_FRAC_BAUD(value) (SERCOM_USART_EXT_BAUD_FRAC_BAUD_Msk & (_UINT16_(value) << SERCOM_USART_EXT_BAUD_FRAC_BAUD_Pos))
994 #define SERCOM_USART_EXT_BAUD_FRAC_FP_Pos     _UINT16_(13)                                         /* (SERCOM_USART_EXT_BAUD) Fractional Part Position */
995 #define SERCOM_USART_EXT_BAUD_FRAC_FP_Msk     (_UINT16_(0x7) << SERCOM_USART_EXT_BAUD_FRAC_FP_Pos) /* (SERCOM_USART_EXT_BAUD) Fractional Part Mask */
996 #define SERCOM_USART_EXT_BAUD_FRAC_FP(value)  (SERCOM_USART_EXT_BAUD_FRAC_FP_Msk & (_UINT16_(value) << SERCOM_USART_EXT_BAUD_FRAC_FP_Pos))
997 #define SERCOM_USART_EXT_BAUD_FRAC_Msk        _UINT16_(0xFFFF)                                      /* (SERCOM_USART_EXT_BAUD_FRAC) Register Mask  */
998 
999 /* FRACFP mode */
1000 #define SERCOM_USART_EXT_BAUD_FRACFP_BAUD_Pos _UINT16_(0)                                          /* (SERCOM_USART_EXT_BAUD) Baud Rate Value Position */
1001 #define SERCOM_USART_EXT_BAUD_FRACFP_BAUD_Msk (_UINT16_(0x1FFF) << SERCOM_USART_EXT_BAUD_FRACFP_BAUD_Pos) /* (SERCOM_USART_EXT_BAUD) Baud Rate Value Mask */
1002 #define SERCOM_USART_EXT_BAUD_FRACFP_BAUD(value) (SERCOM_USART_EXT_BAUD_FRACFP_BAUD_Msk & (_UINT16_(value) << SERCOM_USART_EXT_BAUD_FRACFP_BAUD_Pos))
1003 #define SERCOM_USART_EXT_BAUD_FRACFP_FP_Pos   _UINT16_(13)                                         /* (SERCOM_USART_EXT_BAUD) Fractional Part Position */
1004 #define SERCOM_USART_EXT_BAUD_FRACFP_FP_Msk   (_UINT16_(0x7) << SERCOM_USART_EXT_BAUD_FRACFP_FP_Pos) /* (SERCOM_USART_EXT_BAUD) Fractional Part Mask */
1005 #define SERCOM_USART_EXT_BAUD_FRACFP_FP(value) (SERCOM_USART_EXT_BAUD_FRACFP_FP_Msk & (_UINT16_(value) << SERCOM_USART_EXT_BAUD_FRACFP_FP_Pos))
1006 #define SERCOM_USART_EXT_BAUD_FRACFP_Msk      _UINT16_(0xFFFF)                                      /* (SERCOM_USART_EXT_BAUD_FRACFP) Register Mask  */
1007 
1008 /* USARTFP mode */
1009 #define SERCOM_USART_EXT_BAUD_USARTFP_BAUD_Pos _UINT16_(0)                                          /* (SERCOM_USART_EXT_BAUD) Baud Rate Value Position */
1010 #define SERCOM_USART_EXT_BAUD_USARTFP_BAUD_Msk (_UINT16_(0xFFFF) << SERCOM_USART_EXT_BAUD_USARTFP_BAUD_Pos) /* (SERCOM_USART_EXT_BAUD) Baud Rate Value Mask */
1011 #define SERCOM_USART_EXT_BAUD_USARTFP_BAUD(value) (SERCOM_USART_EXT_BAUD_USARTFP_BAUD_Msk & (_UINT16_(value) << SERCOM_USART_EXT_BAUD_USARTFP_BAUD_Pos))
1012 #define SERCOM_USART_EXT_BAUD_USARTFP_Msk     _UINT16_(0xFFFF)                                      /* (SERCOM_USART_EXT_BAUD_USARTFP) Register Mask  */
1013 
1014 
1015 /* -------- SERCOM_USART_INT_BAUD : (SERCOM Offset: 0x0C) (R/W 16) USART_INT Baud Rate -------- */
1016 #define SERCOM_USART_INT_BAUD_RESETVALUE      _UINT16_(0x00)                                       /*  (SERCOM_USART_INT_BAUD) USART_INT Baud Rate  Reset Value */
1017 
1018 #define SERCOM_USART_INT_BAUD_BAUD_Pos        _UINT16_(0)                                          /* (SERCOM_USART_INT_BAUD) Baud Rate Value Position */
1019 #define SERCOM_USART_INT_BAUD_BAUD_Msk        (_UINT16_(0xFFFF) << SERCOM_USART_INT_BAUD_BAUD_Pos) /* (SERCOM_USART_INT_BAUD) Baud Rate Value Mask */
1020 #define SERCOM_USART_INT_BAUD_BAUD(value)     (SERCOM_USART_INT_BAUD_BAUD_Msk & (_UINT16_(value) << SERCOM_USART_INT_BAUD_BAUD_Pos)) /* Assigment of value for BAUD in the SERCOM_USART_INT_BAUD register */
1021 #define SERCOM_USART_INT_BAUD_Msk             _UINT16_(0xFFFF)                                     /* (SERCOM_USART_INT_BAUD) Register Mask  */
1022 
1023 /* FRAC mode */
1024 #define SERCOM_USART_INT_BAUD_FRAC_BAUD_Pos   _UINT16_(0)                                          /* (SERCOM_USART_INT_BAUD) Baud Rate Value Position */
1025 #define SERCOM_USART_INT_BAUD_FRAC_BAUD_Msk   (_UINT16_(0x1FFF) << SERCOM_USART_INT_BAUD_FRAC_BAUD_Pos) /* (SERCOM_USART_INT_BAUD) Baud Rate Value Mask */
1026 #define SERCOM_USART_INT_BAUD_FRAC_BAUD(value) (SERCOM_USART_INT_BAUD_FRAC_BAUD_Msk & (_UINT16_(value) << SERCOM_USART_INT_BAUD_FRAC_BAUD_Pos))
1027 #define SERCOM_USART_INT_BAUD_FRAC_FP_Pos     _UINT16_(13)                                         /* (SERCOM_USART_INT_BAUD) Fractional Part Position */
1028 #define SERCOM_USART_INT_BAUD_FRAC_FP_Msk     (_UINT16_(0x7) << SERCOM_USART_INT_BAUD_FRAC_FP_Pos) /* (SERCOM_USART_INT_BAUD) Fractional Part Mask */
1029 #define SERCOM_USART_INT_BAUD_FRAC_FP(value)  (SERCOM_USART_INT_BAUD_FRAC_FP_Msk & (_UINT16_(value) << SERCOM_USART_INT_BAUD_FRAC_FP_Pos))
1030 #define SERCOM_USART_INT_BAUD_FRAC_Msk        _UINT16_(0xFFFF)                                      /* (SERCOM_USART_INT_BAUD_FRAC) Register Mask  */
1031 
1032 /* FRACFP mode */
1033 #define SERCOM_USART_INT_BAUD_FRACFP_BAUD_Pos _UINT16_(0)                                          /* (SERCOM_USART_INT_BAUD) Baud Rate Value Position */
1034 #define SERCOM_USART_INT_BAUD_FRACFP_BAUD_Msk (_UINT16_(0x1FFF) << SERCOM_USART_INT_BAUD_FRACFP_BAUD_Pos) /* (SERCOM_USART_INT_BAUD) Baud Rate Value Mask */
1035 #define SERCOM_USART_INT_BAUD_FRACFP_BAUD(value) (SERCOM_USART_INT_BAUD_FRACFP_BAUD_Msk & (_UINT16_(value) << SERCOM_USART_INT_BAUD_FRACFP_BAUD_Pos))
1036 #define SERCOM_USART_INT_BAUD_FRACFP_FP_Pos   _UINT16_(13)                                         /* (SERCOM_USART_INT_BAUD) Fractional Part Position */
1037 #define SERCOM_USART_INT_BAUD_FRACFP_FP_Msk   (_UINT16_(0x7) << SERCOM_USART_INT_BAUD_FRACFP_FP_Pos) /* (SERCOM_USART_INT_BAUD) Fractional Part Mask */
1038 #define SERCOM_USART_INT_BAUD_FRACFP_FP(value) (SERCOM_USART_INT_BAUD_FRACFP_FP_Msk & (_UINT16_(value) << SERCOM_USART_INT_BAUD_FRACFP_FP_Pos))
1039 #define SERCOM_USART_INT_BAUD_FRACFP_Msk      _UINT16_(0xFFFF)                                      /* (SERCOM_USART_INT_BAUD_FRACFP) Register Mask  */
1040 
1041 /* USARTFP mode */
1042 #define SERCOM_USART_INT_BAUD_USARTFP_BAUD_Pos _UINT16_(0)                                          /* (SERCOM_USART_INT_BAUD) Baud Rate Value Position */
1043 #define SERCOM_USART_INT_BAUD_USARTFP_BAUD_Msk (_UINT16_(0xFFFF) << SERCOM_USART_INT_BAUD_USARTFP_BAUD_Pos) /* (SERCOM_USART_INT_BAUD) Baud Rate Value Mask */
1044 #define SERCOM_USART_INT_BAUD_USARTFP_BAUD(value) (SERCOM_USART_INT_BAUD_USARTFP_BAUD_Msk & (_UINT16_(value) << SERCOM_USART_INT_BAUD_USARTFP_BAUD_Pos))
1045 #define SERCOM_USART_INT_BAUD_USARTFP_Msk     _UINT16_(0xFFFF)                                      /* (SERCOM_USART_INT_BAUD_USARTFP) Register Mask  */
1046 
1047 
1048 /* -------- SERCOM_USART_EXT_RXPL : (SERCOM Offset: 0x0E) (R/W 8) USART_EXT Receive Pulse Length -------- */
1049 #define SERCOM_USART_EXT_RXPL_RESETVALUE      _UINT8_(0x00)                                        /*  (SERCOM_USART_EXT_RXPL) USART_EXT Receive Pulse Length  Reset Value */
1050 
1051 #define SERCOM_USART_EXT_RXPL_RXPL_Pos        _UINT8_(0)                                           /* (SERCOM_USART_EXT_RXPL) Receive Pulse Length Position */
1052 #define SERCOM_USART_EXT_RXPL_RXPL_Msk        (_UINT8_(0xFF) << SERCOM_USART_EXT_RXPL_RXPL_Pos)    /* (SERCOM_USART_EXT_RXPL) Receive Pulse Length Mask */
1053 #define SERCOM_USART_EXT_RXPL_RXPL(value)     (SERCOM_USART_EXT_RXPL_RXPL_Msk & (_UINT8_(value) << SERCOM_USART_EXT_RXPL_RXPL_Pos)) /* Assigment of value for RXPL in the SERCOM_USART_EXT_RXPL register */
1054 #define SERCOM_USART_EXT_RXPL_Msk             _UINT8_(0xFF)                                        /* (SERCOM_USART_EXT_RXPL) Register Mask  */
1055 
1056 
1057 /* -------- SERCOM_USART_INT_RXPL : (SERCOM Offset: 0x0E) (R/W 8) USART_INT Receive Pulse Length -------- */
1058 #define SERCOM_USART_INT_RXPL_RESETVALUE      _UINT8_(0x00)                                        /*  (SERCOM_USART_INT_RXPL) USART_INT Receive Pulse Length  Reset Value */
1059 
1060 #define SERCOM_USART_INT_RXPL_RXPL_Pos        _UINT8_(0)                                           /* (SERCOM_USART_INT_RXPL) Receive Pulse Length Position */
1061 #define SERCOM_USART_INT_RXPL_RXPL_Msk        (_UINT8_(0xFF) << SERCOM_USART_INT_RXPL_RXPL_Pos)    /* (SERCOM_USART_INT_RXPL) Receive Pulse Length Mask */
1062 #define SERCOM_USART_INT_RXPL_RXPL(value)     (SERCOM_USART_INT_RXPL_RXPL_Msk & (_UINT8_(value) << SERCOM_USART_INT_RXPL_RXPL_Pos)) /* Assigment of value for RXPL in the SERCOM_USART_INT_RXPL register */
1063 #define SERCOM_USART_INT_RXPL_Msk             _UINT8_(0xFF)                                        /* (SERCOM_USART_INT_RXPL) Register Mask  */
1064 
1065 
1066 /* -------- SERCOM_I2CM_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CM Interrupt Enable Clear -------- */
1067 #define SERCOM_I2CM_INTENCLR_RESETVALUE       _UINT8_(0x00)                                        /*  (SERCOM_I2CM_INTENCLR) I2CM Interrupt Enable Clear  Reset Value */
1068 
1069 #define SERCOM_I2CM_INTENCLR_MB_Pos           _UINT8_(0)                                           /* (SERCOM_I2CM_INTENCLR) Master On Bus Interrupt Disable Position */
1070 #define SERCOM_I2CM_INTENCLR_MB_Msk           (_UINT8_(0x1) << SERCOM_I2CM_INTENCLR_MB_Pos)        /* (SERCOM_I2CM_INTENCLR) Master On Bus Interrupt Disable Mask */
1071 #define SERCOM_I2CM_INTENCLR_MB(value)        (SERCOM_I2CM_INTENCLR_MB_Msk & (_UINT8_(value) << SERCOM_I2CM_INTENCLR_MB_Pos)) /* Assigment of value for MB in the SERCOM_I2CM_INTENCLR register */
1072 #define SERCOM_I2CM_INTENCLR_SB_Pos           _UINT8_(1)                                           /* (SERCOM_I2CM_INTENCLR) Slave On Bus Interrupt Disable Position */
1073 #define SERCOM_I2CM_INTENCLR_SB_Msk           (_UINT8_(0x1) << SERCOM_I2CM_INTENCLR_SB_Pos)        /* (SERCOM_I2CM_INTENCLR) Slave On Bus Interrupt Disable Mask */
1074 #define SERCOM_I2CM_INTENCLR_SB(value)        (SERCOM_I2CM_INTENCLR_SB_Msk & (_UINT8_(value) << SERCOM_I2CM_INTENCLR_SB_Pos)) /* Assigment of value for SB in the SERCOM_I2CM_INTENCLR register */
1075 #define SERCOM_I2CM_INTENCLR_ERROR_Pos        _UINT8_(7)                                           /* (SERCOM_I2CM_INTENCLR) Combined Error Interrupt Disable Position */
1076 #define SERCOM_I2CM_INTENCLR_ERROR_Msk        (_UINT8_(0x1) << SERCOM_I2CM_INTENCLR_ERROR_Pos)     /* (SERCOM_I2CM_INTENCLR) Combined Error Interrupt Disable Mask */
1077 #define SERCOM_I2CM_INTENCLR_ERROR(value)     (SERCOM_I2CM_INTENCLR_ERROR_Msk & (_UINT8_(value) << SERCOM_I2CM_INTENCLR_ERROR_Pos)) /* Assigment of value for ERROR in the SERCOM_I2CM_INTENCLR register */
1078 #define SERCOM_I2CM_INTENCLR_Msk              _UINT8_(0x83)                                        /* (SERCOM_I2CM_INTENCLR) Register Mask  */
1079 
1080 
1081 /* -------- SERCOM_I2CS_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CS Interrupt Enable Clear -------- */
1082 #define SERCOM_I2CS_INTENCLR_RESETVALUE       _UINT8_(0x00)                                        /*  (SERCOM_I2CS_INTENCLR) I2CS Interrupt Enable Clear  Reset Value */
1083 
1084 #define SERCOM_I2CS_INTENCLR_PREC_Pos         _UINT8_(0)                                           /* (SERCOM_I2CS_INTENCLR) Stop Received Interrupt Disable Position */
1085 #define SERCOM_I2CS_INTENCLR_PREC_Msk         (_UINT8_(0x1) << SERCOM_I2CS_INTENCLR_PREC_Pos)      /* (SERCOM_I2CS_INTENCLR) Stop Received Interrupt Disable Mask */
1086 #define SERCOM_I2CS_INTENCLR_PREC(value)      (SERCOM_I2CS_INTENCLR_PREC_Msk & (_UINT8_(value) << SERCOM_I2CS_INTENCLR_PREC_Pos)) /* Assigment of value for PREC in the SERCOM_I2CS_INTENCLR register */
1087 #define SERCOM_I2CS_INTENCLR_AMATCH_Pos       _UINT8_(1)                                           /* (SERCOM_I2CS_INTENCLR) Address Match Interrupt Disable Position */
1088 #define SERCOM_I2CS_INTENCLR_AMATCH_Msk       (_UINT8_(0x1) << SERCOM_I2CS_INTENCLR_AMATCH_Pos)    /* (SERCOM_I2CS_INTENCLR) Address Match Interrupt Disable Mask */
1089 #define SERCOM_I2CS_INTENCLR_AMATCH(value)    (SERCOM_I2CS_INTENCLR_AMATCH_Msk & (_UINT8_(value) << SERCOM_I2CS_INTENCLR_AMATCH_Pos)) /* Assigment of value for AMATCH in the SERCOM_I2CS_INTENCLR register */
1090 #define SERCOM_I2CS_INTENCLR_DRDY_Pos         _UINT8_(2)                                           /* (SERCOM_I2CS_INTENCLR) Data Interrupt Disable Position */
1091 #define SERCOM_I2CS_INTENCLR_DRDY_Msk         (_UINT8_(0x1) << SERCOM_I2CS_INTENCLR_DRDY_Pos)      /* (SERCOM_I2CS_INTENCLR) Data Interrupt Disable Mask */
1092 #define SERCOM_I2CS_INTENCLR_DRDY(value)      (SERCOM_I2CS_INTENCLR_DRDY_Msk & (_UINT8_(value) << SERCOM_I2CS_INTENCLR_DRDY_Pos)) /* Assigment of value for DRDY in the SERCOM_I2CS_INTENCLR register */
1093 #define SERCOM_I2CS_INTENCLR_ERROR_Pos        _UINT8_(7)                                           /* (SERCOM_I2CS_INTENCLR) Combined Error Interrupt Disable Position */
1094 #define SERCOM_I2CS_INTENCLR_ERROR_Msk        (_UINT8_(0x1) << SERCOM_I2CS_INTENCLR_ERROR_Pos)     /* (SERCOM_I2CS_INTENCLR) Combined Error Interrupt Disable Mask */
1095 #define SERCOM_I2CS_INTENCLR_ERROR(value)     (SERCOM_I2CS_INTENCLR_ERROR_Msk & (_UINT8_(value) << SERCOM_I2CS_INTENCLR_ERROR_Pos)) /* Assigment of value for ERROR in the SERCOM_I2CS_INTENCLR register */
1096 #define SERCOM_I2CS_INTENCLR_Msk              _UINT8_(0x87)                                        /* (SERCOM_I2CS_INTENCLR) Register Mask  */
1097 
1098 
1099 /* -------- SERCOM_SPIM_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) SPIM Interrupt Enable Clear -------- */
1100 #define SERCOM_SPIM_INTENCLR_RESETVALUE       _UINT8_(0x00)                                        /*  (SERCOM_SPIM_INTENCLR) SPIM Interrupt Enable Clear  Reset Value */
1101 
1102 #define SERCOM_SPIM_INTENCLR_DRE_Pos          _UINT8_(0)                                           /* (SERCOM_SPIM_INTENCLR) Data Register Empty Interrupt Disable Position */
1103 #define SERCOM_SPIM_INTENCLR_DRE_Msk          (_UINT8_(0x1) << SERCOM_SPIM_INTENCLR_DRE_Pos)       /* (SERCOM_SPIM_INTENCLR) Data Register Empty Interrupt Disable Mask */
1104 #define SERCOM_SPIM_INTENCLR_DRE(value)       (SERCOM_SPIM_INTENCLR_DRE_Msk & (_UINT8_(value) << SERCOM_SPIM_INTENCLR_DRE_Pos)) /* Assigment of value for DRE in the SERCOM_SPIM_INTENCLR register */
1105 #define SERCOM_SPIM_INTENCLR_TXC_Pos          _UINT8_(1)                                           /* (SERCOM_SPIM_INTENCLR) Transmit Complete Interrupt Disable Position */
1106 #define SERCOM_SPIM_INTENCLR_TXC_Msk          (_UINT8_(0x1) << SERCOM_SPIM_INTENCLR_TXC_Pos)       /* (SERCOM_SPIM_INTENCLR) Transmit Complete Interrupt Disable Mask */
1107 #define SERCOM_SPIM_INTENCLR_TXC(value)       (SERCOM_SPIM_INTENCLR_TXC_Msk & (_UINT8_(value) << SERCOM_SPIM_INTENCLR_TXC_Pos)) /* Assigment of value for TXC in the SERCOM_SPIM_INTENCLR register */
1108 #define SERCOM_SPIM_INTENCLR_RXC_Pos          _UINT8_(2)                                           /* (SERCOM_SPIM_INTENCLR) Receive Complete Interrupt Disable Position */
1109 #define SERCOM_SPIM_INTENCLR_RXC_Msk          (_UINT8_(0x1) << SERCOM_SPIM_INTENCLR_RXC_Pos)       /* (SERCOM_SPIM_INTENCLR) Receive Complete Interrupt Disable Mask */
1110 #define SERCOM_SPIM_INTENCLR_RXC(value)       (SERCOM_SPIM_INTENCLR_RXC_Msk & (_UINT8_(value) << SERCOM_SPIM_INTENCLR_RXC_Pos)) /* Assigment of value for RXC in the SERCOM_SPIM_INTENCLR register */
1111 #define SERCOM_SPIM_INTENCLR_SSL_Pos          _UINT8_(3)                                           /* (SERCOM_SPIM_INTENCLR) Slave Select Low Interrupt Disable Position */
1112 #define SERCOM_SPIM_INTENCLR_SSL_Msk          (_UINT8_(0x1) << SERCOM_SPIM_INTENCLR_SSL_Pos)       /* (SERCOM_SPIM_INTENCLR) Slave Select Low Interrupt Disable Mask */
1113 #define SERCOM_SPIM_INTENCLR_SSL(value)       (SERCOM_SPIM_INTENCLR_SSL_Msk & (_UINT8_(value) << SERCOM_SPIM_INTENCLR_SSL_Pos)) /* Assigment of value for SSL in the SERCOM_SPIM_INTENCLR register */
1114 #define SERCOM_SPIM_INTENCLR_ERROR_Pos        _UINT8_(7)                                           /* (SERCOM_SPIM_INTENCLR) Combined Error Interrupt Disable Position */
1115 #define SERCOM_SPIM_INTENCLR_ERROR_Msk        (_UINT8_(0x1) << SERCOM_SPIM_INTENCLR_ERROR_Pos)     /* (SERCOM_SPIM_INTENCLR) Combined Error Interrupt Disable Mask */
1116 #define SERCOM_SPIM_INTENCLR_ERROR(value)     (SERCOM_SPIM_INTENCLR_ERROR_Msk & (_UINT8_(value) << SERCOM_SPIM_INTENCLR_ERROR_Pos)) /* Assigment of value for ERROR in the SERCOM_SPIM_INTENCLR register */
1117 #define SERCOM_SPIM_INTENCLR_Msk              _UINT8_(0x8F)                                        /* (SERCOM_SPIM_INTENCLR) Register Mask  */
1118 
1119 
1120 /* -------- SERCOM_SPIS_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) SPIS Interrupt Enable Clear -------- */
1121 #define SERCOM_SPIS_INTENCLR_RESETVALUE       _UINT8_(0x00)                                        /*  (SERCOM_SPIS_INTENCLR) SPIS Interrupt Enable Clear  Reset Value */
1122 
1123 #define SERCOM_SPIS_INTENCLR_DRE_Pos          _UINT8_(0)                                           /* (SERCOM_SPIS_INTENCLR) Data Register Empty Interrupt Disable Position */
1124 #define SERCOM_SPIS_INTENCLR_DRE_Msk          (_UINT8_(0x1) << SERCOM_SPIS_INTENCLR_DRE_Pos)       /* (SERCOM_SPIS_INTENCLR) Data Register Empty Interrupt Disable Mask */
1125 #define SERCOM_SPIS_INTENCLR_DRE(value)       (SERCOM_SPIS_INTENCLR_DRE_Msk & (_UINT8_(value) << SERCOM_SPIS_INTENCLR_DRE_Pos)) /* Assigment of value for DRE in the SERCOM_SPIS_INTENCLR register */
1126 #define SERCOM_SPIS_INTENCLR_TXC_Pos          _UINT8_(1)                                           /* (SERCOM_SPIS_INTENCLR) Transmit Complete Interrupt Disable Position */
1127 #define SERCOM_SPIS_INTENCLR_TXC_Msk          (_UINT8_(0x1) << SERCOM_SPIS_INTENCLR_TXC_Pos)       /* (SERCOM_SPIS_INTENCLR) Transmit Complete Interrupt Disable Mask */
1128 #define SERCOM_SPIS_INTENCLR_TXC(value)       (SERCOM_SPIS_INTENCLR_TXC_Msk & (_UINT8_(value) << SERCOM_SPIS_INTENCLR_TXC_Pos)) /* Assigment of value for TXC in the SERCOM_SPIS_INTENCLR register */
1129 #define SERCOM_SPIS_INTENCLR_RXC_Pos          _UINT8_(2)                                           /* (SERCOM_SPIS_INTENCLR) Receive Complete Interrupt Disable Position */
1130 #define SERCOM_SPIS_INTENCLR_RXC_Msk          (_UINT8_(0x1) << SERCOM_SPIS_INTENCLR_RXC_Pos)       /* (SERCOM_SPIS_INTENCLR) Receive Complete Interrupt Disable Mask */
1131 #define SERCOM_SPIS_INTENCLR_RXC(value)       (SERCOM_SPIS_INTENCLR_RXC_Msk & (_UINT8_(value) << SERCOM_SPIS_INTENCLR_RXC_Pos)) /* Assigment of value for RXC in the SERCOM_SPIS_INTENCLR register */
1132 #define SERCOM_SPIS_INTENCLR_SSL_Pos          _UINT8_(3)                                           /* (SERCOM_SPIS_INTENCLR) Slave Select Low Interrupt Disable Position */
1133 #define SERCOM_SPIS_INTENCLR_SSL_Msk          (_UINT8_(0x1) << SERCOM_SPIS_INTENCLR_SSL_Pos)       /* (SERCOM_SPIS_INTENCLR) Slave Select Low Interrupt Disable Mask */
1134 #define SERCOM_SPIS_INTENCLR_SSL(value)       (SERCOM_SPIS_INTENCLR_SSL_Msk & (_UINT8_(value) << SERCOM_SPIS_INTENCLR_SSL_Pos)) /* Assigment of value for SSL in the SERCOM_SPIS_INTENCLR register */
1135 #define SERCOM_SPIS_INTENCLR_ERROR_Pos        _UINT8_(7)                                           /* (SERCOM_SPIS_INTENCLR) Combined Error Interrupt Disable Position */
1136 #define SERCOM_SPIS_INTENCLR_ERROR_Msk        (_UINT8_(0x1) << SERCOM_SPIS_INTENCLR_ERROR_Pos)     /* (SERCOM_SPIS_INTENCLR) Combined Error Interrupt Disable Mask */
1137 #define SERCOM_SPIS_INTENCLR_ERROR(value)     (SERCOM_SPIS_INTENCLR_ERROR_Msk & (_UINT8_(value) << SERCOM_SPIS_INTENCLR_ERROR_Pos)) /* Assigment of value for ERROR in the SERCOM_SPIS_INTENCLR register */
1138 #define SERCOM_SPIS_INTENCLR_Msk              _UINT8_(0x8F)                                        /* (SERCOM_SPIS_INTENCLR) Register Mask  */
1139 
1140 
1141 /* -------- SERCOM_USART_EXT_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) USART_EXT Interrupt Enable Clear -------- */
1142 #define SERCOM_USART_EXT_INTENCLR_RESETVALUE  _UINT8_(0x00)                                        /*  (SERCOM_USART_EXT_INTENCLR) USART_EXT Interrupt Enable Clear  Reset Value */
1143 
1144 #define SERCOM_USART_EXT_INTENCLR_DRE_Pos     _UINT8_(0)                                           /* (SERCOM_USART_EXT_INTENCLR) Data Register Empty Interrupt Disable Position */
1145 #define SERCOM_USART_EXT_INTENCLR_DRE_Msk     (_UINT8_(0x1) << SERCOM_USART_EXT_INTENCLR_DRE_Pos)  /* (SERCOM_USART_EXT_INTENCLR) Data Register Empty Interrupt Disable Mask */
1146 #define SERCOM_USART_EXT_INTENCLR_DRE(value)  (SERCOM_USART_EXT_INTENCLR_DRE_Msk & (_UINT8_(value) << SERCOM_USART_EXT_INTENCLR_DRE_Pos)) /* Assigment of value for DRE in the SERCOM_USART_EXT_INTENCLR register */
1147 #define SERCOM_USART_EXT_INTENCLR_TXC_Pos     _UINT8_(1)                                           /* (SERCOM_USART_EXT_INTENCLR) Transmit Complete Interrupt Disable Position */
1148 #define SERCOM_USART_EXT_INTENCLR_TXC_Msk     (_UINT8_(0x1) << SERCOM_USART_EXT_INTENCLR_TXC_Pos)  /* (SERCOM_USART_EXT_INTENCLR) Transmit Complete Interrupt Disable Mask */
1149 #define SERCOM_USART_EXT_INTENCLR_TXC(value)  (SERCOM_USART_EXT_INTENCLR_TXC_Msk & (_UINT8_(value) << SERCOM_USART_EXT_INTENCLR_TXC_Pos)) /* Assigment of value for TXC in the SERCOM_USART_EXT_INTENCLR register */
1150 #define SERCOM_USART_EXT_INTENCLR_RXC_Pos     _UINT8_(2)                                           /* (SERCOM_USART_EXT_INTENCLR) Receive Complete Interrupt Disable Position */
1151 #define SERCOM_USART_EXT_INTENCLR_RXC_Msk     (_UINT8_(0x1) << SERCOM_USART_EXT_INTENCLR_RXC_Pos)  /* (SERCOM_USART_EXT_INTENCLR) Receive Complete Interrupt Disable Mask */
1152 #define SERCOM_USART_EXT_INTENCLR_RXC(value)  (SERCOM_USART_EXT_INTENCLR_RXC_Msk & (_UINT8_(value) << SERCOM_USART_EXT_INTENCLR_RXC_Pos)) /* Assigment of value for RXC in the SERCOM_USART_EXT_INTENCLR register */
1153 #define SERCOM_USART_EXT_INTENCLR_RXS_Pos     _UINT8_(3)                                           /* (SERCOM_USART_EXT_INTENCLR) Receive Start Interrupt Disable Position */
1154 #define SERCOM_USART_EXT_INTENCLR_RXS_Msk     (_UINT8_(0x1) << SERCOM_USART_EXT_INTENCLR_RXS_Pos)  /* (SERCOM_USART_EXT_INTENCLR) Receive Start Interrupt Disable Mask */
1155 #define SERCOM_USART_EXT_INTENCLR_RXS(value)  (SERCOM_USART_EXT_INTENCLR_RXS_Msk & (_UINT8_(value) << SERCOM_USART_EXT_INTENCLR_RXS_Pos)) /* Assigment of value for RXS in the SERCOM_USART_EXT_INTENCLR register */
1156 #define SERCOM_USART_EXT_INTENCLR_CTSIC_Pos   _UINT8_(4)                                           /* (SERCOM_USART_EXT_INTENCLR) Clear To Send Input Change Interrupt Disable Position */
1157 #define SERCOM_USART_EXT_INTENCLR_CTSIC_Msk   (_UINT8_(0x1) << SERCOM_USART_EXT_INTENCLR_CTSIC_Pos) /* (SERCOM_USART_EXT_INTENCLR) Clear To Send Input Change Interrupt Disable Mask */
1158 #define SERCOM_USART_EXT_INTENCLR_CTSIC(value) (SERCOM_USART_EXT_INTENCLR_CTSIC_Msk & (_UINT8_(value) << SERCOM_USART_EXT_INTENCLR_CTSIC_Pos)) /* Assigment of value for CTSIC in the SERCOM_USART_EXT_INTENCLR register */
1159 #define SERCOM_USART_EXT_INTENCLR_RXBRK_Pos   _UINT8_(5)                                           /* (SERCOM_USART_EXT_INTENCLR) Break Received Interrupt Disable Position */
1160 #define SERCOM_USART_EXT_INTENCLR_RXBRK_Msk   (_UINT8_(0x1) << SERCOM_USART_EXT_INTENCLR_RXBRK_Pos) /* (SERCOM_USART_EXT_INTENCLR) Break Received Interrupt Disable Mask */
1161 #define SERCOM_USART_EXT_INTENCLR_RXBRK(value) (SERCOM_USART_EXT_INTENCLR_RXBRK_Msk & (_UINT8_(value) << SERCOM_USART_EXT_INTENCLR_RXBRK_Pos)) /* Assigment of value for RXBRK in the SERCOM_USART_EXT_INTENCLR register */
1162 #define SERCOM_USART_EXT_INTENCLR_ERROR_Pos   _UINT8_(7)                                           /* (SERCOM_USART_EXT_INTENCLR) Combined Error Interrupt Disable Position */
1163 #define SERCOM_USART_EXT_INTENCLR_ERROR_Msk   (_UINT8_(0x1) << SERCOM_USART_EXT_INTENCLR_ERROR_Pos) /* (SERCOM_USART_EXT_INTENCLR) Combined Error Interrupt Disable Mask */
1164 #define SERCOM_USART_EXT_INTENCLR_ERROR(value) (SERCOM_USART_EXT_INTENCLR_ERROR_Msk & (_UINT8_(value) << SERCOM_USART_EXT_INTENCLR_ERROR_Pos)) /* Assigment of value for ERROR in the SERCOM_USART_EXT_INTENCLR register */
1165 #define SERCOM_USART_EXT_INTENCLR_Msk         _UINT8_(0xBF)                                        /* (SERCOM_USART_EXT_INTENCLR) Register Mask  */
1166 
1167 
1168 /* -------- SERCOM_USART_INT_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) USART_INT Interrupt Enable Clear -------- */
1169 #define SERCOM_USART_INT_INTENCLR_RESETVALUE  _UINT8_(0x00)                                        /*  (SERCOM_USART_INT_INTENCLR) USART_INT Interrupt Enable Clear  Reset Value */
1170 
1171 #define SERCOM_USART_INT_INTENCLR_DRE_Pos     _UINT8_(0)                                           /* (SERCOM_USART_INT_INTENCLR) Data Register Empty Interrupt Disable Position */
1172 #define SERCOM_USART_INT_INTENCLR_DRE_Msk     (_UINT8_(0x1) << SERCOM_USART_INT_INTENCLR_DRE_Pos)  /* (SERCOM_USART_INT_INTENCLR) Data Register Empty Interrupt Disable Mask */
1173 #define SERCOM_USART_INT_INTENCLR_DRE(value)  (SERCOM_USART_INT_INTENCLR_DRE_Msk & (_UINT8_(value) << SERCOM_USART_INT_INTENCLR_DRE_Pos)) /* Assigment of value for DRE in the SERCOM_USART_INT_INTENCLR register */
1174 #define SERCOM_USART_INT_INTENCLR_TXC_Pos     _UINT8_(1)                                           /* (SERCOM_USART_INT_INTENCLR) Transmit Complete Interrupt Disable Position */
1175 #define SERCOM_USART_INT_INTENCLR_TXC_Msk     (_UINT8_(0x1) << SERCOM_USART_INT_INTENCLR_TXC_Pos)  /* (SERCOM_USART_INT_INTENCLR) Transmit Complete Interrupt Disable Mask */
1176 #define SERCOM_USART_INT_INTENCLR_TXC(value)  (SERCOM_USART_INT_INTENCLR_TXC_Msk & (_UINT8_(value) << SERCOM_USART_INT_INTENCLR_TXC_Pos)) /* Assigment of value for TXC in the SERCOM_USART_INT_INTENCLR register */
1177 #define SERCOM_USART_INT_INTENCLR_RXC_Pos     _UINT8_(2)                                           /* (SERCOM_USART_INT_INTENCLR) Receive Complete Interrupt Disable Position */
1178 #define SERCOM_USART_INT_INTENCLR_RXC_Msk     (_UINT8_(0x1) << SERCOM_USART_INT_INTENCLR_RXC_Pos)  /* (SERCOM_USART_INT_INTENCLR) Receive Complete Interrupt Disable Mask */
1179 #define SERCOM_USART_INT_INTENCLR_RXC(value)  (SERCOM_USART_INT_INTENCLR_RXC_Msk & (_UINT8_(value) << SERCOM_USART_INT_INTENCLR_RXC_Pos)) /* Assigment of value for RXC in the SERCOM_USART_INT_INTENCLR register */
1180 #define SERCOM_USART_INT_INTENCLR_RXS_Pos     _UINT8_(3)                                           /* (SERCOM_USART_INT_INTENCLR) Receive Start Interrupt Disable Position */
1181 #define SERCOM_USART_INT_INTENCLR_RXS_Msk     (_UINT8_(0x1) << SERCOM_USART_INT_INTENCLR_RXS_Pos)  /* (SERCOM_USART_INT_INTENCLR) Receive Start Interrupt Disable Mask */
1182 #define SERCOM_USART_INT_INTENCLR_RXS(value)  (SERCOM_USART_INT_INTENCLR_RXS_Msk & (_UINT8_(value) << SERCOM_USART_INT_INTENCLR_RXS_Pos)) /* Assigment of value for RXS in the SERCOM_USART_INT_INTENCLR register */
1183 #define SERCOM_USART_INT_INTENCLR_CTSIC_Pos   _UINT8_(4)                                           /* (SERCOM_USART_INT_INTENCLR) Clear To Send Input Change Interrupt Disable Position */
1184 #define SERCOM_USART_INT_INTENCLR_CTSIC_Msk   (_UINT8_(0x1) << SERCOM_USART_INT_INTENCLR_CTSIC_Pos) /* (SERCOM_USART_INT_INTENCLR) Clear To Send Input Change Interrupt Disable Mask */
1185 #define SERCOM_USART_INT_INTENCLR_CTSIC(value) (SERCOM_USART_INT_INTENCLR_CTSIC_Msk & (_UINT8_(value) << SERCOM_USART_INT_INTENCLR_CTSIC_Pos)) /* Assigment of value for CTSIC in the SERCOM_USART_INT_INTENCLR register */
1186 #define SERCOM_USART_INT_INTENCLR_RXBRK_Pos   _UINT8_(5)                                           /* (SERCOM_USART_INT_INTENCLR) Break Received Interrupt Disable Position */
1187 #define SERCOM_USART_INT_INTENCLR_RXBRK_Msk   (_UINT8_(0x1) << SERCOM_USART_INT_INTENCLR_RXBRK_Pos) /* (SERCOM_USART_INT_INTENCLR) Break Received Interrupt Disable Mask */
1188 #define SERCOM_USART_INT_INTENCLR_RXBRK(value) (SERCOM_USART_INT_INTENCLR_RXBRK_Msk & (_UINT8_(value) << SERCOM_USART_INT_INTENCLR_RXBRK_Pos)) /* Assigment of value for RXBRK in the SERCOM_USART_INT_INTENCLR register */
1189 #define SERCOM_USART_INT_INTENCLR_ERROR_Pos   _UINT8_(7)                                           /* (SERCOM_USART_INT_INTENCLR) Combined Error Interrupt Disable Position */
1190 #define SERCOM_USART_INT_INTENCLR_ERROR_Msk   (_UINT8_(0x1) << SERCOM_USART_INT_INTENCLR_ERROR_Pos) /* (SERCOM_USART_INT_INTENCLR) Combined Error Interrupt Disable Mask */
1191 #define SERCOM_USART_INT_INTENCLR_ERROR(value) (SERCOM_USART_INT_INTENCLR_ERROR_Msk & (_UINT8_(value) << SERCOM_USART_INT_INTENCLR_ERROR_Pos)) /* Assigment of value for ERROR in the SERCOM_USART_INT_INTENCLR register */
1192 #define SERCOM_USART_INT_INTENCLR_Msk         _UINT8_(0xBF)                                        /* (SERCOM_USART_INT_INTENCLR) Register Mask  */
1193 
1194 
1195 /* -------- SERCOM_I2CM_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CM Interrupt Enable Set -------- */
1196 #define SERCOM_I2CM_INTENSET_RESETVALUE       _UINT8_(0x00)                                        /*  (SERCOM_I2CM_INTENSET) I2CM Interrupt Enable Set  Reset Value */
1197 
1198 #define SERCOM_I2CM_INTENSET_MB_Pos           _UINT8_(0)                                           /* (SERCOM_I2CM_INTENSET) Master On Bus Interrupt Enable Position */
1199 #define SERCOM_I2CM_INTENSET_MB_Msk           (_UINT8_(0x1) << SERCOM_I2CM_INTENSET_MB_Pos)        /* (SERCOM_I2CM_INTENSET) Master On Bus Interrupt Enable Mask */
1200 #define SERCOM_I2CM_INTENSET_MB(value)        (SERCOM_I2CM_INTENSET_MB_Msk & (_UINT8_(value) << SERCOM_I2CM_INTENSET_MB_Pos)) /* Assigment of value for MB in the SERCOM_I2CM_INTENSET register */
1201 #define SERCOM_I2CM_INTENSET_SB_Pos           _UINT8_(1)                                           /* (SERCOM_I2CM_INTENSET) Slave On Bus Interrupt Enable Position */
1202 #define SERCOM_I2CM_INTENSET_SB_Msk           (_UINT8_(0x1) << SERCOM_I2CM_INTENSET_SB_Pos)        /* (SERCOM_I2CM_INTENSET) Slave On Bus Interrupt Enable Mask */
1203 #define SERCOM_I2CM_INTENSET_SB(value)        (SERCOM_I2CM_INTENSET_SB_Msk & (_UINT8_(value) << SERCOM_I2CM_INTENSET_SB_Pos)) /* Assigment of value for SB in the SERCOM_I2CM_INTENSET register */
1204 #define SERCOM_I2CM_INTENSET_ERROR_Pos        _UINT8_(7)                                           /* (SERCOM_I2CM_INTENSET) Combined Error Interrupt Enable Position */
1205 #define SERCOM_I2CM_INTENSET_ERROR_Msk        (_UINT8_(0x1) << SERCOM_I2CM_INTENSET_ERROR_Pos)     /* (SERCOM_I2CM_INTENSET) Combined Error Interrupt Enable Mask */
1206 #define SERCOM_I2CM_INTENSET_ERROR(value)     (SERCOM_I2CM_INTENSET_ERROR_Msk & (_UINT8_(value) << SERCOM_I2CM_INTENSET_ERROR_Pos)) /* Assigment of value for ERROR in the SERCOM_I2CM_INTENSET register */
1207 #define SERCOM_I2CM_INTENSET_Msk              _UINT8_(0x83)                                        /* (SERCOM_I2CM_INTENSET) Register Mask  */
1208 
1209 
1210 /* -------- SERCOM_I2CS_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CS Interrupt Enable Set -------- */
1211 #define SERCOM_I2CS_INTENSET_RESETVALUE       _UINT8_(0x00)                                        /*  (SERCOM_I2CS_INTENSET) I2CS Interrupt Enable Set  Reset Value */
1212 
1213 #define SERCOM_I2CS_INTENSET_PREC_Pos         _UINT8_(0)                                           /* (SERCOM_I2CS_INTENSET) Stop Received Interrupt Enable Position */
1214 #define SERCOM_I2CS_INTENSET_PREC_Msk         (_UINT8_(0x1) << SERCOM_I2CS_INTENSET_PREC_Pos)      /* (SERCOM_I2CS_INTENSET) Stop Received Interrupt Enable Mask */
1215 #define SERCOM_I2CS_INTENSET_PREC(value)      (SERCOM_I2CS_INTENSET_PREC_Msk & (_UINT8_(value) << SERCOM_I2CS_INTENSET_PREC_Pos)) /* Assigment of value for PREC in the SERCOM_I2CS_INTENSET register */
1216 #define SERCOM_I2CS_INTENSET_AMATCH_Pos       _UINT8_(1)                                           /* (SERCOM_I2CS_INTENSET) Address Match Interrupt Enable Position */
1217 #define SERCOM_I2CS_INTENSET_AMATCH_Msk       (_UINT8_(0x1) << SERCOM_I2CS_INTENSET_AMATCH_Pos)    /* (SERCOM_I2CS_INTENSET) Address Match Interrupt Enable Mask */
1218 #define SERCOM_I2CS_INTENSET_AMATCH(value)    (SERCOM_I2CS_INTENSET_AMATCH_Msk & (_UINT8_(value) << SERCOM_I2CS_INTENSET_AMATCH_Pos)) /* Assigment of value for AMATCH in the SERCOM_I2CS_INTENSET register */
1219 #define SERCOM_I2CS_INTENSET_DRDY_Pos         _UINT8_(2)                                           /* (SERCOM_I2CS_INTENSET) Data Interrupt Enable Position */
1220 #define SERCOM_I2CS_INTENSET_DRDY_Msk         (_UINT8_(0x1) << SERCOM_I2CS_INTENSET_DRDY_Pos)      /* (SERCOM_I2CS_INTENSET) Data Interrupt Enable Mask */
1221 #define SERCOM_I2CS_INTENSET_DRDY(value)      (SERCOM_I2CS_INTENSET_DRDY_Msk & (_UINT8_(value) << SERCOM_I2CS_INTENSET_DRDY_Pos)) /* Assigment of value for DRDY in the SERCOM_I2CS_INTENSET register */
1222 #define SERCOM_I2CS_INTENSET_ERROR_Pos        _UINT8_(7)                                           /* (SERCOM_I2CS_INTENSET) Combined Error Interrupt Enable Position */
1223 #define SERCOM_I2CS_INTENSET_ERROR_Msk        (_UINT8_(0x1) << SERCOM_I2CS_INTENSET_ERROR_Pos)     /* (SERCOM_I2CS_INTENSET) Combined Error Interrupt Enable Mask */
1224 #define SERCOM_I2CS_INTENSET_ERROR(value)     (SERCOM_I2CS_INTENSET_ERROR_Msk & (_UINT8_(value) << SERCOM_I2CS_INTENSET_ERROR_Pos)) /* Assigment of value for ERROR in the SERCOM_I2CS_INTENSET register */
1225 #define SERCOM_I2CS_INTENSET_Msk              _UINT8_(0x87)                                        /* (SERCOM_I2CS_INTENSET) Register Mask  */
1226 
1227 
1228 /* -------- SERCOM_SPIM_INTENSET : (SERCOM Offset: 0x16) (R/W 8) SPIM Interrupt Enable Set -------- */
1229 #define SERCOM_SPIM_INTENSET_RESETVALUE       _UINT8_(0x00)                                        /*  (SERCOM_SPIM_INTENSET) SPIM Interrupt Enable Set  Reset Value */
1230 
1231 #define SERCOM_SPIM_INTENSET_DRE_Pos          _UINT8_(0)                                           /* (SERCOM_SPIM_INTENSET) Data Register Empty Interrupt Enable Position */
1232 #define SERCOM_SPIM_INTENSET_DRE_Msk          (_UINT8_(0x1) << SERCOM_SPIM_INTENSET_DRE_Pos)       /* (SERCOM_SPIM_INTENSET) Data Register Empty Interrupt Enable Mask */
1233 #define SERCOM_SPIM_INTENSET_DRE(value)       (SERCOM_SPIM_INTENSET_DRE_Msk & (_UINT8_(value) << SERCOM_SPIM_INTENSET_DRE_Pos)) /* Assigment of value for DRE in the SERCOM_SPIM_INTENSET register */
1234 #define SERCOM_SPIM_INTENSET_TXC_Pos          _UINT8_(1)                                           /* (SERCOM_SPIM_INTENSET) Transmit Complete Interrupt Enable Position */
1235 #define SERCOM_SPIM_INTENSET_TXC_Msk          (_UINT8_(0x1) << SERCOM_SPIM_INTENSET_TXC_Pos)       /* (SERCOM_SPIM_INTENSET) Transmit Complete Interrupt Enable Mask */
1236 #define SERCOM_SPIM_INTENSET_TXC(value)       (SERCOM_SPIM_INTENSET_TXC_Msk & (_UINT8_(value) << SERCOM_SPIM_INTENSET_TXC_Pos)) /* Assigment of value for TXC in the SERCOM_SPIM_INTENSET register */
1237 #define SERCOM_SPIM_INTENSET_RXC_Pos          _UINT8_(2)                                           /* (SERCOM_SPIM_INTENSET) Receive Complete Interrupt Enable Position */
1238 #define SERCOM_SPIM_INTENSET_RXC_Msk          (_UINT8_(0x1) << SERCOM_SPIM_INTENSET_RXC_Pos)       /* (SERCOM_SPIM_INTENSET) Receive Complete Interrupt Enable Mask */
1239 #define SERCOM_SPIM_INTENSET_RXC(value)       (SERCOM_SPIM_INTENSET_RXC_Msk & (_UINT8_(value) << SERCOM_SPIM_INTENSET_RXC_Pos)) /* Assigment of value for RXC in the SERCOM_SPIM_INTENSET register */
1240 #define SERCOM_SPIM_INTENSET_SSL_Pos          _UINT8_(3)                                           /* (SERCOM_SPIM_INTENSET) Slave Select Low Interrupt Enable Position */
1241 #define SERCOM_SPIM_INTENSET_SSL_Msk          (_UINT8_(0x1) << SERCOM_SPIM_INTENSET_SSL_Pos)       /* (SERCOM_SPIM_INTENSET) Slave Select Low Interrupt Enable Mask */
1242 #define SERCOM_SPIM_INTENSET_SSL(value)       (SERCOM_SPIM_INTENSET_SSL_Msk & (_UINT8_(value) << SERCOM_SPIM_INTENSET_SSL_Pos)) /* Assigment of value for SSL in the SERCOM_SPIM_INTENSET register */
1243 #define SERCOM_SPIM_INTENSET_ERROR_Pos        _UINT8_(7)                                           /* (SERCOM_SPIM_INTENSET) Combined Error Interrupt Enable Position */
1244 #define SERCOM_SPIM_INTENSET_ERROR_Msk        (_UINT8_(0x1) << SERCOM_SPIM_INTENSET_ERROR_Pos)     /* (SERCOM_SPIM_INTENSET) Combined Error Interrupt Enable Mask */
1245 #define SERCOM_SPIM_INTENSET_ERROR(value)     (SERCOM_SPIM_INTENSET_ERROR_Msk & (_UINT8_(value) << SERCOM_SPIM_INTENSET_ERROR_Pos)) /* Assigment of value for ERROR in the SERCOM_SPIM_INTENSET register */
1246 #define SERCOM_SPIM_INTENSET_Msk              _UINT8_(0x8F)                                        /* (SERCOM_SPIM_INTENSET) Register Mask  */
1247 
1248 
1249 /* -------- SERCOM_SPIS_INTENSET : (SERCOM Offset: 0x16) (R/W 8) SPIS Interrupt Enable Set -------- */
1250 #define SERCOM_SPIS_INTENSET_RESETVALUE       _UINT8_(0x00)                                        /*  (SERCOM_SPIS_INTENSET) SPIS Interrupt Enable Set  Reset Value */
1251 
1252 #define SERCOM_SPIS_INTENSET_DRE_Pos          _UINT8_(0)                                           /* (SERCOM_SPIS_INTENSET) Data Register Empty Interrupt Enable Position */
1253 #define SERCOM_SPIS_INTENSET_DRE_Msk          (_UINT8_(0x1) << SERCOM_SPIS_INTENSET_DRE_Pos)       /* (SERCOM_SPIS_INTENSET) Data Register Empty Interrupt Enable Mask */
1254 #define SERCOM_SPIS_INTENSET_DRE(value)       (SERCOM_SPIS_INTENSET_DRE_Msk & (_UINT8_(value) << SERCOM_SPIS_INTENSET_DRE_Pos)) /* Assigment of value for DRE in the SERCOM_SPIS_INTENSET register */
1255 #define SERCOM_SPIS_INTENSET_TXC_Pos          _UINT8_(1)                                           /* (SERCOM_SPIS_INTENSET) Transmit Complete Interrupt Enable Position */
1256 #define SERCOM_SPIS_INTENSET_TXC_Msk          (_UINT8_(0x1) << SERCOM_SPIS_INTENSET_TXC_Pos)       /* (SERCOM_SPIS_INTENSET) Transmit Complete Interrupt Enable Mask */
1257 #define SERCOM_SPIS_INTENSET_TXC(value)       (SERCOM_SPIS_INTENSET_TXC_Msk & (_UINT8_(value) << SERCOM_SPIS_INTENSET_TXC_Pos)) /* Assigment of value for TXC in the SERCOM_SPIS_INTENSET register */
1258 #define SERCOM_SPIS_INTENSET_RXC_Pos          _UINT8_(2)                                           /* (SERCOM_SPIS_INTENSET) Receive Complete Interrupt Enable Position */
1259 #define SERCOM_SPIS_INTENSET_RXC_Msk          (_UINT8_(0x1) << SERCOM_SPIS_INTENSET_RXC_Pos)       /* (SERCOM_SPIS_INTENSET) Receive Complete Interrupt Enable Mask */
1260 #define SERCOM_SPIS_INTENSET_RXC(value)       (SERCOM_SPIS_INTENSET_RXC_Msk & (_UINT8_(value) << SERCOM_SPIS_INTENSET_RXC_Pos)) /* Assigment of value for RXC in the SERCOM_SPIS_INTENSET register */
1261 #define SERCOM_SPIS_INTENSET_SSL_Pos          _UINT8_(3)                                           /* (SERCOM_SPIS_INTENSET) Slave Select Low Interrupt Enable Position */
1262 #define SERCOM_SPIS_INTENSET_SSL_Msk          (_UINT8_(0x1) << SERCOM_SPIS_INTENSET_SSL_Pos)       /* (SERCOM_SPIS_INTENSET) Slave Select Low Interrupt Enable Mask */
1263 #define SERCOM_SPIS_INTENSET_SSL(value)       (SERCOM_SPIS_INTENSET_SSL_Msk & (_UINT8_(value) << SERCOM_SPIS_INTENSET_SSL_Pos)) /* Assigment of value for SSL in the SERCOM_SPIS_INTENSET register */
1264 #define SERCOM_SPIS_INTENSET_ERROR_Pos        _UINT8_(7)                                           /* (SERCOM_SPIS_INTENSET) Combined Error Interrupt Enable Position */
1265 #define SERCOM_SPIS_INTENSET_ERROR_Msk        (_UINT8_(0x1) << SERCOM_SPIS_INTENSET_ERROR_Pos)     /* (SERCOM_SPIS_INTENSET) Combined Error Interrupt Enable Mask */
1266 #define SERCOM_SPIS_INTENSET_ERROR(value)     (SERCOM_SPIS_INTENSET_ERROR_Msk & (_UINT8_(value) << SERCOM_SPIS_INTENSET_ERROR_Pos)) /* Assigment of value for ERROR in the SERCOM_SPIS_INTENSET register */
1267 #define SERCOM_SPIS_INTENSET_Msk              _UINT8_(0x8F)                                        /* (SERCOM_SPIS_INTENSET) Register Mask  */
1268 
1269 
1270 /* -------- SERCOM_USART_EXT_INTENSET : (SERCOM Offset: 0x16) (R/W 8) USART_EXT Interrupt Enable Set -------- */
1271 #define SERCOM_USART_EXT_INTENSET_RESETVALUE  _UINT8_(0x00)                                        /*  (SERCOM_USART_EXT_INTENSET) USART_EXT Interrupt Enable Set  Reset Value */
1272 
1273 #define SERCOM_USART_EXT_INTENSET_DRE_Pos     _UINT8_(0)                                           /* (SERCOM_USART_EXT_INTENSET) Data Register Empty Interrupt Enable Position */
1274 #define SERCOM_USART_EXT_INTENSET_DRE_Msk     (_UINT8_(0x1) << SERCOM_USART_EXT_INTENSET_DRE_Pos)  /* (SERCOM_USART_EXT_INTENSET) Data Register Empty Interrupt Enable Mask */
1275 #define SERCOM_USART_EXT_INTENSET_DRE(value)  (SERCOM_USART_EXT_INTENSET_DRE_Msk & (_UINT8_(value) << SERCOM_USART_EXT_INTENSET_DRE_Pos)) /* Assigment of value for DRE in the SERCOM_USART_EXT_INTENSET register */
1276 #define SERCOM_USART_EXT_INTENSET_TXC_Pos     _UINT8_(1)                                           /* (SERCOM_USART_EXT_INTENSET) Transmit Complete Interrupt Enable Position */
1277 #define SERCOM_USART_EXT_INTENSET_TXC_Msk     (_UINT8_(0x1) << SERCOM_USART_EXT_INTENSET_TXC_Pos)  /* (SERCOM_USART_EXT_INTENSET) Transmit Complete Interrupt Enable Mask */
1278 #define SERCOM_USART_EXT_INTENSET_TXC(value)  (SERCOM_USART_EXT_INTENSET_TXC_Msk & (_UINT8_(value) << SERCOM_USART_EXT_INTENSET_TXC_Pos)) /* Assigment of value for TXC in the SERCOM_USART_EXT_INTENSET register */
1279 #define SERCOM_USART_EXT_INTENSET_RXC_Pos     _UINT8_(2)                                           /* (SERCOM_USART_EXT_INTENSET) Receive Complete Interrupt Enable Position */
1280 #define SERCOM_USART_EXT_INTENSET_RXC_Msk     (_UINT8_(0x1) << SERCOM_USART_EXT_INTENSET_RXC_Pos)  /* (SERCOM_USART_EXT_INTENSET) Receive Complete Interrupt Enable Mask */
1281 #define SERCOM_USART_EXT_INTENSET_RXC(value)  (SERCOM_USART_EXT_INTENSET_RXC_Msk & (_UINT8_(value) << SERCOM_USART_EXT_INTENSET_RXC_Pos)) /* Assigment of value for RXC in the SERCOM_USART_EXT_INTENSET register */
1282 #define SERCOM_USART_EXT_INTENSET_RXS_Pos     _UINT8_(3)                                           /* (SERCOM_USART_EXT_INTENSET) Receive Start Interrupt Enable Position */
1283 #define SERCOM_USART_EXT_INTENSET_RXS_Msk     (_UINT8_(0x1) << SERCOM_USART_EXT_INTENSET_RXS_Pos)  /* (SERCOM_USART_EXT_INTENSET) Receive Start Interrupt Enable Mask */
1284 #define SERCOM_USART_EXT_INTENSET_RXS(value)  (SERCOM_USART_EXT_INTENSET_RXS_Msk & (_UINT8_(value) << SERCOM_USART_EXT_INTENSET_RXS_Pos)) /* Assigment of value for RXS in the SERCOM_USART_EXT_INTENSET register */
1285 #define SERCOM_USART_EXT_INTENSET_CTSIC_Pos   _UINT8_(4)                                           /* (SERCOM_USART_EXT_INTENSET) Clear To Send Input Change Interrupt Enable Position */
1286 #define SERCOM_USART_EXT_INTENSET_CTSIC_Msk   (_UINT8_(0x1) << SERCOM_USART_EXT_INTENSET_CTSIC_Pos) /* (SERCOM_USART_EXT_INTENSET) Clear To Send Input Change Interrupt Enable Mask */
1287 #define SERCOM_USART_EXT_INTENSET_CTSIC(value) (SERCOM_USART_EXT_INTENSET_CTSIC_Msk & (_UINT8_(value) << SERCOM_USART_EXT_INTENSET_CTSIC_Pos)) /* Assigment of value for CTSIC in the SERCOM_USART_EXT_INTENSET register */
1288 #define SERCOM_USART_EXT_INTENSET_RXBRK_Pos   _UINT8_(5)                                           /* (SERCOM_USART_EXT_INTENSET) Break Received Interrupt Enable Position */
1289 #define SERCOM_USART_EXT_INTENSET_RXBRK_Msk   (_UINT8_(0x1) << SERCOM_USART_EXT_INTENSET_RXBRK_Pos) /* (SERCOM_USART_EXT_INTENSET) Break Received Interrupt Enable Mask */
1290 #define SERCOM_USART_EXT_INTENSET_RXBRK(value) (SERCOM_USART_EXT_INTENSET_RXBRK_Msk & (_UINT8_(value) << SERCOM_USART_EXT_INTENSET_RXBRK_Pos)) /* Assigment of value for RXBRK in the SERCOM_USART_EXT_INTENSET register */
1291 #define SERCOM_USART_EXT_INTENSET_ERROR_Pos   _UINT8_(7)                                           /* (SERCOM_USART_EXT_INTENSET) Combined Error Interrupt Enable Position */
1292 #define SERCOM_USART_EXT_INTENSET_ERROR_Msk   (_UINT8_(0x1) << SERCOM_USART_EXT_INTENSET_ERROR_Pos) /* (SERCOM_USART_EXT_INTENSET) Combined Error Interrupt Enable Mask */
1293 #define SERCOM_USART_EXT_INTENSET_ERROR(value) (SERCOM_USART_EXT_INTENSET_ERROR_Msk & (_UINT8_(value) << SERCOM_USART_EXT_INTENSET_ERROR_Pos)) /* Assigment of value for ERROR in the SERCOM_USART_EXT_INTENSET register */
1294 #define SERCOM_USART_EXT_INTENSET_Msk         _UINT8_(0xBF)                                        /* (SERCOM_USART_EXT_INTENSET) Register Mask  */
1295 
1296 
1297 /* -------- SERCOM_USART_INT_INTENSET : (SERCOM Offset: 0x16) (R/W 8) USART_INT Interrupt Enable Set -------- */
1298 #define SERCOM_USART_INT_INTENSET_RESETVALUE  _UINT8_(0x00)                                        /*  (SERCOM_USART_INT_INTENSET) USART_INT Interrupt Enable Set  Reset Value */
1299 
1300 #define SERCOM_USART_INT_INTENSET_DRE_Pos     _UINT8_(0)                                           /* (SERCOM_USART_INT_INTENSET) Data Register Empty Interrupt Enable Position */
1301 #define SERCOM_USART_INT_INTENSET_DRE_Msk     (_UINT8_(0x1) << SERCOM_USART_INT_INTENSET_DRE_Pos)  /* (SERCOM_USART_INT_INTENSET) Data Register Empty Interrupt Enable Mask */
1302 #define SERCOM_USART_INT_INTENSET_DRE(value)  (SERCOM_USART_INT_INTENSET_DRE_Msk & (_UINT8_(value) << SERCOM_USART_INT_INTENSET_DRE_Pos)) /* Assigment of value for DRE in the SERCOM_USART_INT_INTENSET register */
1303 #define SERCOM_USART_INT_INTENSET_TXC_Pos     _UINT8_(1)                                           /* (SERCOM_USART_INT_INTENSET) Transmit Complete Interrupt Enable Position */
1304 #define SERCOM_USART_INT_INTENSET_TXC_Msk     (_UINT8_(0x1) << SERCOM_USART_INT_INTENSET_TXC_Pos)  /* (SERCOM_USART_INT_INTENSET) Transmit Complete Interrupt Enable Mask */
1305 #define SERCOM_USART_INT_INTENSET_TXC(value)  (SERCOM_USART_INT_INTENSET_TXC_Msk & (_UINT8_(value) << SERCOM_USART_INT_INTENSET_TXC_Pos)) /* Assigment of value for TXC in the SERCOM_USART_INT_INTENSET register */
1306 #define SERCOM_USART_INT_INTENSET_RXC_Pos     _UINT8_(2)                                           /* (SERCOM_USART_INT_INTENSET) Receive Complete Interrupt Enable Position */
1307 #define SERCOM_USART_INT_INTENSET_RXC_Msk     (_UINT8_(0x1) << SERCOM_USART_INT_INTENSET_RXC_Pos)  /* (SERCOM_USART_INT_INTENSET) Receive Complete Interrupt Enable Mask */
1308 #define SERCOM_USART_INT_INTENSET_RXC(value)  (SERCOM_USART_INT_INTENSET_RXC_Msk & (_UINT8_(value) << SERCOM_USART_INT_INTENSET_RXC_Pos)) /* Assigment of value for RXC in the SERCOM_USART_INT_INTENSET register */
1309 #define SERCOM_USART_INT_INTENSET_RXS_Pos     _UINT8_(3)                                           /* (SERCOM_USART_INT_INTENSET) Receive Start Interrupt Enable Position */
1310 #define SERCOM_USART_INT_INTENSET_RXS_Msk     (_UINT8_(0x1) << SERCOM_USART_INT_INTENSET_RXS_Pos)  /* (SERCOM_USART_INT_INTENSET) Receive Start Interrupt Enable Mask */
1311 #define SERCOM_USART_INT_INTENSET_RXS(value)  (SERCOM_USART_INT_INTENSET_RXS_Msk & (_UINT8_(value) << SERCOM_USART_INT_INTENSET_RXS_Pos)) /* Assigment of value for RXS in the SERCOM_USART_INT_INTENSET register */
1312 #define SERCOM_USART_INT_INTENSET_CTSIC_Pos   _UINT8_(4)                                           /* (SERCOM_USART_INT_INTENSET) Clear To Send Input Change Interrupt Enable Position */
1313 #define SERCOM_USART_INT_INTENSET_CTSIC_Msk   (_UINT8_(0x1) << SERCOM_USART_INT_INTENSET_CTSIC_Pos) /* (SERCOM_USART_INT_INTENSET) Clear To Send Input Change Interrupt Enable Mask */
1314 #define SERCOM_USART_INT_INTENSET_CTSIC(value) (SERCOM_USART_INT_INTENSET_CTSIC_Msk & (_UINT8_(value) << SERCOM_USART_INT_INTENSET_CTSIC_Pos)) /* Assigment of value for CTSIC in the SERCOM_USART_INT_INTENSET register */
1315 #define SERCOM_USART_INT_INTENSET_RXBRK_Pos   _UINT8_(5)                                           /* (SERCOM_USART_INT_INTENSET) Break Received Interrupt Enable Position */
1316 #define SERCOM_USART_INT_INTENSET_RXBRK_Msk   (_UINT8_(0x1) << SERCOM_USART_INT_INTENSET_RXBRK_Pos) /* (SERCOM_USART_INT_INTENSET) Break Received Interrupt Enable Mask */
1317 #define SERCOM_USART_INT_INTENSET_RXBRK(value) (SERCOM_USART_INT_INTENSET_RXBRK_Msk & (_UINT8_(value) << SERCOM_USART_INT_INTENSET_RXBRK_Pos)) /* Assigment of value for RXBRK in the SERCOM_USART_INT_INTENSET register */
1318 #define SERCOM_USART_INT_INTENSET_ERROR_Pos   _UINT8_(7)                                           /* (SERCOM_USART_INT_INTENSET) Combined Error Interrupt Enable Position */
1319 #define SERCOM_USART_INT_INTENSET_ERROR_Msk   (_UINT8_(0x1) << SERCOM_USART_INT_INTENSET_ERROR_Pos) /* (SERCOM_USART_INT_INTENSET) Combined Error Interrupt Enable Mask */
1320 #define SERCOM_USART_INT_INTENSET_ERROR(value) (SERCOM_USART_INT_INTENSET_ERROR_Msk & (_UINT8_(value) << SERCOM_USART_INT_INTENSET_ERROR_Pos)) /* Assigment of value for ERROR in the SERCOM_USART_INT_INTENSET register */
1321 #define SERCOM_USART_INT_INTENSET_Msk         _UINT8_(0xBF)                                        /* (SERCOM_USART_INT_INTENSET) Register Mask  */
1322 
1323 
1324 /* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CM Interrupt Flag Status and Clear -------- */
1325 #define SERCOM_I2CM_INTFLAG_RESETVALUE        _UINT8_(0x00)                                        /*  (SERCOM_I2CM_INTFLAG) I2CM Interrupt Flag Status and Clear  Reset Value */
1326 
1327 #define SERCOM_I2CM_INTFLAG_MB_Pos            _UINT8_(0)                                           /* (SERCOM_I2CM_INTFLAG) Master On Bus Interrupt Position */
1328 #define SERCOM_I2CM_INTFLAG_MB_Msk            (_UINT8_(0x1) << SERCOM_I2CM_INTFLAG_MB_Pos)         /* (SERCOM_I2CM_INTFLAG) Master On Bus Interrupt Mask */
1329 #define SERCOM_I2CM_INTFLAG_MB(value)         (SERCOM_I2CM_INTFLAG_MB_Msk & (_UINT8_(value) << SERCOM_I2CM_INTFLAG_MB_Pos)) /* Assigment of value for MB in the SERCOM_I2CM_INTFLAG register */
1330 #define SERCOM_I2CM_INTFLAG_SB_Pos            _UINT8_(1)                                           /* (SERCOM_I2CM_INTFLAG) Slave On Bus Interrupt Position */
1331 #define SERCOM_I2CM_INTFLAG_SB_Msk            (_UINT8_(0x1) << SERCOM_I2CM_INTFLAG_SB_Pos)         /* (SERCOM_I2CM_INTFLAG) Slave On Bus Interrupt Mask */
1332 #define SERCOM_I2CM_INTFLAG_SB(value)         (SERCOM_I2CM_INTFLAG_SB_Msk & (_UINT8_(value) << SERCOM_I2CM_INTFLAG_SB_Pos)) /* Assigment of value for SB in the SERCOM_I2CM_INTFLAG register */
1333 #define SERCOM_I2CM_INTFLAG_ERROR_Pos         _UINT8_(7)                                           /* (SERCOM_I2CM_INTFLAG) Combined Error Interrupt Position */
1334 #define SERCOM_I2CM_INTFLAG_ERROR_Msk         (_UINT8_(0x1) << SERCOM_I2CM_INTFLAG_ERROR_Pos)      /* (SERCOM_I2CM_INTFLAG) Combined Error Interrupt Mask */
1335 #define SERCOM_I2CM_INTFLAG_ERROR(value)      (SERCOM_I2CM_INTFLAG_ERROR_Msk & (_UINT8_(value) << SERCOM_I2CM_INTFLAG_ERROR_Pos)) /* Assigment of value for ERROR in the SERCOM_I2CM_INTFLAG register */
1336 #define SERCOM_I2CM_INTFLAG_Msk               _UINT8_(0x83)                                        /* (SERCOM_I2CM_INTFLAG) Register Mask  */
1337 
1338 
1339 /* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CS Interrupt Flag Status and Clear -------- */
1340 #define SERCOM_I2CS_INTFLAG_RESETVALUE        _UINT8_(0x00)                                        /*  (SERCOM_I2CS_INTFLAG) I2CS Interrupt Flag Status and Clear  Reset Value */
1341 
1342 #define SERCOM_I2CS_INTFLAG_PREC_Pos          _UINT8_(0)                                           /* (SERCOM_I2CS_INTFLAG) Stop Received Interrupt Position */
1343 #define SERCOM_I2CS_INTFLAG_PREC_Msk          (_UINT8_(0x1) << SERCOM_I2CS_INTFLAG_PREC_Pos)       /* (SERCOM_I2CS_INTFLAG) Stop Received Interrupt Mask */
1344 #define SERCOM_I2CS_INTFLAG_PREC(value)       (SERCOM_I2CS_INTFLAG_PREC_Msk & (_UINT8_(value) << SERCOM_I2CS_INTFLAG_PREC_Pos)) /* Assigment of value for PREC in the SERCOM_I2CS_INTFLAG register */
1345 #define SERCOM_I2CS_INTFLAG_AMATCH_Pos        _UINT8_(1)                                           /* (SERCOM_I2CS_INTFLAG) Address Match Interrupt Position */
1346 #define SERCOM_I2CS_INTFLAG_AMATCH_Msk        (_UINT8_(0x1) << SERCOM_I2CS_INTFLAG_AMATCH_Pos)     /* (SERCOM_I2CS_INTFLAG) Address Match Interrupt Mask */
1347 #define SERCOM_I2CS_INTFLAG_AMATCH(value)     (SERCOM_I2CS_INTFLAG_AMATCH_Msk & (_UINT8_(value) << SERCOM_I2CS_INTFLAG_AMATCH_Pos)) /* Assigment of value for AMATCH in the SERCOM_I2CS_INTFLAG register */
1348 #define SERCOM_I2CS_INTFLAG_DRDY_Pos          _UINT8_(2)                                           /* (SERCOM_I2CS_INTFLAG) Data Interrupt Position */
1349 #define SERCOM_I2CS_INTFLAG_DRDY_Msk          (_UINT8_(0x1) << SERCOM_I2CS_INTFLAG_DRDY_Pos)       /* (SERCOM_I2CS_INTFLAG) Data Interrupt Mask */
1350 #define SERCOM_I2CS_INTFLAG_DRDY(value)       (SERCOM_I2CS_INTFLAG_DRDY_Msk & (_UINT8_(value) << SERCOM_I2CS_INTFLAG_DRDY_Pos)) /* Assigment of value for DRDY in the SERCOM_I2CS_INTFLAG register */
1351 #define SERCOM_I2CS_INTFLAG_ERROR_Pos         _UINT8_(7)                                           /* (SERCOM_I2CS_INTFLAG) Combined Error Interrupt Position */
1352 #define SERCOM_I2CS_INTFLAG_ERROR_Msk         (_UINT8_(0x1) << SERCOM_I2CS_INTFLAG_ERROR_Pos)      /* (SERCOM_I2CS_INTFLAG) Combined Error Interrupt Mask */
1353 #define SERCOM_I2CS_INTFLAG_ERROR(value)      (SERCOM_I2CS_INTFLAG_ERROR_Msk & (_UINT8_(value) << SERCOM_I2CS_INTFLAG_ERROR_Pos)) /* Assigment of value for ERROR in the SERCOM_I2CS_INTFLAG register */
1354 #define SERCOM_I2CS_INTFLAG_Msk               _UINT8_(0x87)                                        /* (SERCOM_I2CS_INTFLAG) Register Mask  */
1355 
1356 
1357 /* -------- SERCOM_SPIM_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) SPIM Interrupt Flag Status and Clear -------- */
1358 #define SERCOM_SPIM_INTFLAG_RESETVALUE        _UINT8_(0x00)                                        /*  (SERCOM_SPIM_INTFLAG) SPIM Interrupt Flag Status and Clear  Reset Value */
1359 
1360 #define SERCOM_SPIM_INTFLAG_DRE_Pos           _UINT8_(0)                                           /* (SERCOM_SPIM_INTFLAG) Data Register Empty Interrupt Position */
1361 #define SERCOM_SPIM_INTFLAG_DRE_Msk           (_UINT8_(0x1) << SERCOM_SPIM_INTFLAG_DRE_Pos)        /* (SERCOM_SPIM_INTFLAG) Data Register Empty Interrupt Mask */
1362 #define SERCOM_SPIM_INTFLAG_DRE(value)        (SERCOM_SPIM_INTFLAG_DRE_Msk & (_UINT8_(value) << SERCOM_SPIM_INTFLAG_DRE_Pos)) /* Assigment of value for DRE in the SERCOM_SPIM_INTFLAG register */
1363 #define SERCOM_SPIM_INTFLAG_TXC_Pos           _UINT8_(1)                                           /* (SERCOM_SPIM_INTFLAG) Transmit Complete Interrupt Position */
1364 #define SERCOM_SPIM_INTFLAG_TXC_Msk           (_UINT8_(0x1) << SERCOM_SPIM_INTFLAG_TXC_Pos)        /* (SERCOM_SPIM_INTFLAG) Transmit Complete Interrupt Mask */
1365 #define SERCOM_SPIM_INTFLAG_TXC(value)        (SERCOM_SPIM_INTFLAG_TXC_Msk & (_UINT8_(value) << SERCOM_SPIM_INTFLAG_TXC_Pos)) /* Assigment of value for TXC in the SERCOM_SPIM_INTFLAG register */
1366 #define SERCOM_SPIM_INTFLAG_RXC_Pos           _UINT8_(2)                                           /* (SERCOM_SPIM_INTFLAG) Receive Complete Interrupt Position */
1367 #define SERCOM_SPIM_INTFLAG_RXC_Msk           (_UINT8_(0x1) << SERCOM_SPIM_INTFLAG_RXC_Pos)        /* (SERCOM_SPIM_INTFLAG) Receive Complete Interrupt Mask */
1368 #define SERCOM_SPIM_INTFLAG_RXC(value)        (SERCOM_SPIM_INTFLAG_RXC_Msk & (_UINT8_(value) << SERCOM_SPIM_INTFLAG_RXC_Pos)) /* Assigment of value for RXC in the SERCOM_SPIM_INTFLAG register */
1369 #define SERCOM_SPIM_INTFLAG_SSL_Pos           _UINT8_(3)                                           /* (SERCOM_SPIM_INTFLAG) Slave Select Low Interrupt Flag Position */
1370 #define SERCOM_SPIM_INTFLAG_SSL_Msk           (_UINT8_(0x1) << SERCOM_SPIM_INTFLAG_SSL_Pos)        /* (SERCOM_SPIM_INTFLAG) Slave Select Low Interrupt Flag Mask */
1371 #define SERCOM_SPIM_INTFLAG_SSL(value)        (SERCOM_SPIM_INTFLAG_SSL_Msk & (_UINT8_(value) << SERCOM_SPIM_INTFLAG_SSL_Pos)) /* Assigment of value for SSL in the SERCOM_SPIM_INTFLAG register */
1372 #define SERCOM_SPIM_INTFLAG_ERROR_Pos         _UINT8_(7)                                           /* (SERCOM_SPIM_INTFLAG) Combined Error Interrupt Position */
1373 #define SERCOM_SPIM_INTFLAG_ERROR_Msk         (_UINT8_(0x1) << SERCOM_SPIM_INTFLAG_ERROR_Pos)      /* (SERCOM_SPIM_INTFLAG) Combined Error Interrupt Mask */
1374 #define SERCOM_SPIM_INTFLAG_ERROR(value)      (SERCOM_SPIM_INTFLAG_ERROR_Msk & (_UINT8_(value) << SERCOM_SPIM_INTFLAG_ERROR_Pos)) /* Assigment of value for ERROR in the SERCOM_SPIM_INTFLAG register */
1375 #define SERCOM_SPIM_INTFLAG_Msk               _UINT8_(0x8F)                                        /* (SERCOM_SPIM_INTFLAG) Register Mask  */
1376 
1377 
1378 /* -------- SERCOM_SPIS_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) SPIS Interrupt Flag Status and Clear -------- */
1379 #define SERCOM_SPIS_INTFLAG_RESETVALUE        _UINT8_(0x00)                                        /*  (SERCOM_SPIS_INTFLAG) SPIS Interrupt Flag Status and Clear  Reset Value */
1380 
1381 #define SERCOM_SPIS_INTFLAG_DRE_Pos           _UINT8_(0)                                           /* (SERCOM_SPIS_INTFLAG) Data Register Empty Interrupt Position */
1382 #define SERCOM_SPIS_INTFLAG_DRE_Msk           (_UINT8_(0x1) << SERCOM_SPIS_INTFLAG_DRE_Pos)        /* (SERCOM_SPIS_INTFLAG) Data Register Empty Interrupt Mask */
1383 #define SERCOM_SPIS_INTFLAG_DRE(value)        (SERCOM_SPIS_INTFLAG_DRE_Msk & (_UINT8_(value) << SERCOM_SPIS_INTFLAG_DRE_Pos)) /* Assigment of value for DRE in the SERCOM_SPIS_INTFLAG register */
1384 #define SERCOM_SPIS_INTFLAG_TXC_Pos           _UINT8_(1)                                           /* (SERCOM_SPIS_INTFLAG) Transmit Complete Interrupt Position */
1385 #define SERCOM_SPIS_INTFLAG_TXC_Msk           (_UINT8_(0x1) << SERCOM_SPIS_INTFLAG_TXC_Pos)        /* (SERCOM_SPIS_INTFLAG) Transmit Complete Interrupt Mask */
1386 #define SERCOM_SPIS_INTFLAG_TXC(value)        (SERCOM_SPIS_INTFLAG_TXC_Msk & (_UINT8_(value) << SERCOM_SPIS_INTFLAG_TXC_Pos)) /* Assigment of value for TXC in the SERCOM_SPIS_INTFLAG register */
1387 #define SERCOM_SPIS_INTFLAG_RXC_Pos           _UINT8_(2)                                           /* (SERCOM_SPIS_INTFLAG) Receive Complete Interrupt Position */
1388 #define SERCOM_SPIS_INTFLAG_RXC_Msk           (_UINT8_(0x1) << SERCOM_SPIS_INTFLAG_RXC_Pos)        /* (SERCOM_SPIS_INTFLAG) Receive Complete Interrupt Mask */
1389 #define SERCOM_SPIS_INTFLAG_RXC(value)        (SERCOM_SPIS_INTFLAG_RXC_Msk & (_UINT8_(value) << SERCOM_SPIS_INTFLAG_RXC_Pos)) /* Assigment of value for RXC in the SERCOM_SPIS_INTFLAG register */
1390 #define SERCOM_SPIS_INTFLAG_SSL_Pos           _UINT8_(3)                                           /* (SERCOM_SPIS_INTFLAG) Slave Select Low Interrupt Flag Position */
1391 #define SERCOM_SPIS_INTFLAG_SSL_Msk           (_UINT8_(0x1) << SERCOM_SPIS_INTFLAG_SSL_Pos)        /* (SERCOM_SPIS_INTFLAG) Slave Select Low Interrupt Flag Mask */
1392 #define SERCOM_SPIS_INTFLAG_SSL(value)        (SERCOM_SPIS_INTFLAG_SSL_Msk & (_UINT8_(value) << SERCOM_SPIS_INTFLAG_SSL_Pos)) /* Assigment of value for SSL in the SERCOM_SPIS_INTFLAG register */
1393 #define SERCOM_SPIS_INTFLAG_ERROR_Pos         _UINT8_(7)                                           /* (SERCOM_SPIS_INTFLAG) Combined Error Interrupt Position */
1394 #define SERCOM_SPIS_INTFLAG_ERROR_Msk         (_UINT8_(0x1) << SERCOM_SPIS_INTFLAG_ERROR_Pos)      /* (SERCOM_SPIS_INTFLAG) Combined Error Interrupt Mask */
1395 #define SERCOM_SPIS_INTFLAG_ERROR(value)      (SERCOM_SPIS_INTFLAG_ERROR_Msk & (_UINT8_(value) << SERCOM_SPIS_INTFLAG_ERROR_Pos)) /* Assigment of value for ERROR in the SERCOM_SPIS_INTFLAG register */
1396 #define SERCOM_SPIS_INTFLAG_Msk               _UINT8_(0x8F)                                        /* (SERCOM_SPIS_INTFLAG) Register Mask  */
1397 
1398 
1399 /* -------- SERCOM_USART_EXT_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) USART_EXT Interrupt Flag Status and Clear -------- */
1400 #define SERCOM_USART_EXT_INTFLAG_RESETVALUE   _UINT8_(0x00)                                        /*  (SERCOM_USART_EXT_INTFLAG) USART_EXT Interrupt Flag Status and Clear  Reset Value */
1401 
1402 #define SERCOM_USART_EXT_INTFLAG_DRE_Pos      _UINT8_(0)                                           /* (SERCOM_USART_EXT_INTFLAG) Data Register Empty Interrupt Position */
1403 #define SERCOM_USART_EXT_INTFLAG_DRE_Msk      (_UINT8_(0x1) << SERCOM_USART_EXT_INTFLAG_DRE_Pos)   /* (SERCOM_USART_EXT_INTFLAG) Data Register Empty Interrupt Mask */
1404 #define SERCOM_USART_EXT_INTFLAG_DRE(value)   (SERCOM_USART_EXT_INTFLAG_DRE_Msk & (_UINT8_(value) << SERCOM_USART_EXT_INTFLAG_DRE_Pos)) /* Assigment of value for DRE in the SERCOM_USART_EXT_INTFLAG register */
1405 #define SERCOM_USART_EXT_INTFLAG_TXC_Pos      _UINT8_(1)                                           /* (SERCOM_USART_EXT_INTFLAG) Transmit Complete Interrupt Position */
1406 #define SERCOM_USART_EXT_INTFLAG_TXC_Msk      (_UINT8_(0x1) << SERCOM_USART_EXT_INTFLAG_TXC_Pos)   /* (SERCOM_USART_EXT_INTFLAG) Transmit Complete Interrupt Mask */
1407 #define SERCOM_USART_EXT_INTFLAG_TXC(value)   (SERCOM_USART_EXT_INTFLAG_TXC_Msk & (_UINT8_(value) << SERCOM_USART_EXT_INTFLAG_TXC_Pos)) /* Assigment of value for TXC in the SERCOM_USART_EXT_INTFLAG register */
1408 #define SERCOM_USART_EXT_INTFLAG_RXC_Pos      _UINT8_(2)                                           /* (SERCOM_USART_EXT_INTFLAG) Receive Complete Interrupt Position */
1409 #define SERCOM_USART_EXT_INTFLAG_RXC_Msk      (_UINT8_(0x1) << SERCOM_USART_EXT_INTFLAG_RXC_Pos)   /* (SERCOM_USART_EXT_INTFLAG) Receive Complete Interrupt Mask */
1410 #define SERCOM_USART_EXT_INTFLAG_RXC(value)   (SERCOM_USART_EXT_INTFLAG_RXC_Msk & (_UINT8_(value) << SERCOM_USART_EXT_INTFLAG_RXC_Pos)) /* Assigment of value for RXC in the SERCOM_USART_EXT_INTFLAG register */
1411 #define SERCOM_USART_EXT_INTFLAG_RXS_Pos      _UINT8_(3)                                           /* (SERCOM_USART_EXT_INTFLAG) Receive Start Interrupt Position */
1412 #define SERCOM_USART_EXT_INTFLAG_RXS_Msk      (_UINT8_(0x1) << SERCOM_USART_EXT_INTFLAG_RXS_Pos)   /* (SERCOM_USART_EXT_INTFLAG) Receive Start Interrupt Mask */
1413 #define SERCOM_USART_EXT_INTFLAG_RXS(value)   (SERCOM_USART_EXT_INTFLAG_RXS_Msk & (_UINT8_(value) << SERCOM_USART_EXT_INTFLAG_RXS_Pos)) /* Assigment of value for RXS in the SERCOM_USART_EXT_INTFLAG register */
1414 #define SERCOM_USART_EXT_INTFLAG_CTSIC_Pos    _UINT8_(4)                                           /* (SERCOM_USART_EXT_INTFLAG) Clear To Send Input Change Interrupt Position */
1415 #define SERCOM_USART_EXT_INTFLAG_CTSIC_Msk    (_UINT8_(0x1) << SERCOM_USART_EXT_INTFLAG_CTSIC_Pos) /* (SERCOM_USART_EXT_INTFLAG) Clear To Send Input Change Interrupt Mask */
1416 #define SERCOM_USART_EXT_INTFLAG_CTSIC(value) (SERCOM_USART_EXT_INTFLAG_CTSIC_Msk & (_UINT8_(value) << SERCOM_USART_EXT_INTFLAG_CTSIC_Pos)) /* Assigment of value for CTSIC in the SERCOM_USART_EXT_INTFLAG register */
1417 #define SERCOM_USART_EXT_INTFLAG_RXBRK_Pos    _UINT8_(5)                                           /* (SERCOM_USART_EXT_INTFLAG) Break Received Interrupt Position */
1418 #define SERCOM_USART_EXT_INTFLAG_RXBRK_Msk    (_UINT8_(0x1) << SERCOM_USART_EXT_INTFLAG_RXBRK_Pos) /* (SERCOM_USART_EXT_INTFLAG) Break Received Interrupt Mask */
1419 #define SERCOM_USART_EXT_INTFLAG_RXBRK(value) (SERCOM_USART_EXT_INTFLAG_RXBRK_Msk & (_UINT8_(value) << SERCOM_USART_EXT_INTFLAG_RXBRK_Pos)) /* Assigment of value for RXBRK in the SERCOM_USART_EXT_INTFLAG register */
1420 #define SERCOM_USART_EXT_INTFLAG_ERROR_Pos    _UINT8_(7)                                           /* (SERCOM_USART_EXT_INTFLAG) Combined Error Interrupt Position */
1421 #define SERCOM_USART_EXT_INTFLAG_ERROR_Msk    (_UINT8_(0x1) << SERCOM_USART_EXT_INTFLAG_ERROR_Pos) /* (SERCOM_USART_EXT_INTFLAG) Combined Error Interrupt Mask */
1422 #define SERCOM_USART_EXT_INTFLAG_ERROR(value) (SERCOM_USART_EXT_INTFLAG_ERROR_Msk & (_UINT8_(value) << SERCOM_USART_EXT_INTFLAG_ERROR_Pos)) /* Assigment of value for ERROR in the SERCOM_USART_EXT_INTFLAG register */
1423 #define SERCOM_USART_EXT_INTFLAG_Msk          _UINT8_(0xBF)                                        /* (SERCOM_USART_EXT_INTFLAG) Register Mask  */
1424 
1425 
1426 /* -------- SERCOM_USART_INT_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) USART_INT Interrupt Flag Status and Clear -------- */
1427 #define SERCOM_USART_INT_INTFLAG_RESETVALUE   _UINT8_(0x00)                                        /*  (SERCOM_USART_INT_INTFLAG) USART_INT Interrupt Flag Status and Clear  Reset Value */
1428 
1429 #define SERCOM_USART_INT_INTFLAG_DRE_Pos      _UINT8_(0)                                           /* (SERCOM_USART_INT_INTFLAG) Data Register Empty Interrupt Position */
1430 #define SERCOM_USART_INT_INTFLAG_DRE_Msk      (_UINT8_(0x1) << SERCOM_USART_INT_INTFLAG_DRE_Pos)   /* (SERCOM_USART_INT_INTFLAG) Data Register Empty Interrupt Mask */
1431 #define SERCOM_USART_INT_INTFLAG_DRE(value)   (SERCOM_USART_INT_INTFLAG_DRE_Msk & (_UINT8_(value) << SERCOM_USART_INT_INTFLAG_DRE_Pos)) /* Assigment of value for DRE in the SERCOM_USART_INT_INTFLAG register */
1432 #define SERCOM_USART_INT_INTFLAG_TXC_Pos      _UINT8_(1)                                           /* (SERCOM_USART_INT_INTFLAG) Transmit Complete Interrupt Position */
1433 #define SERCOM_USART_INT_INTFLAG_TXC_Msk      (_UINT8_(0x1) << SERCOM_USART_INT_INTFLAG_TXC_Pos)   /* (SERCOM_USART_INT_INTFLAG) Transmit Complete Interrupt Mask */
1434 #define SERCOM_USART_INT_INTFLAG_TXC(value)   (SERCOM_USART_INT_INTFLAG_TXC_Msk & (_UINT8_(value) << SERCOM_USART_INT_INTFLAG_TXC_Pos)) /* Assigment of value for TXC in the SERCOM_USART_INT_INTFLAG register */
1435 #define SERCOM_USART_INT_INTFLAG_RXC_Pos      _UINT8_(2)                                           /* (SERCOM_USART_INT_INTFLAG) Receive Complete Interrupt Position */
1436 #define SERCOM_USART_INT_INTFLAG_RXC_Msk      (_UINT8_(0x1) << SERCOM_USART_INT_INTFLAG_RXC_Pos)   /* (SERCOM_USART_INT_INTFLAG) Receive Complete Interrupt Mask */
1437 #define SERCOM_USART_INT_INTFLAG_RXC(value)   (SERCOM_USART_INT_INTFLAG_RXC_Msk & (_UINT8_(value) << SERCOM_USART_INT_INTFLAG_RXC_Pos)) /* Assigment of value for RXC in the SERCOM_USART_INT_INTFLAG register */
1438 #define SERCOM_USART_INT_INTFLAG_RXS_Pos      _UINT8_(3)                                           /* (SERCOM_USART_INT_INTFLAG) Receive Start Interrupt Position */
1439 #define SERCOM_USART_INT_INTFLAG_RXS_Msk      (_UINT8_(0x1) << SERCOM_USART_INT_INTFLAG_RXS_Pos)   /* (SERCOM_USART_INT_INTFLAG) Receive Start Interrupt Mask */
1440 #define SERCOM_USART_INT_INTFLAG_RXS(value)   (SERCOM_USART_INT_INTFLAG_RXS_Msk & (_UINT8_(value) << SERCOM_USART_INT_INTFLAG_RXS_Pos)) /* Assigment of value for RXS in the SERCOM_USART_INT_INTFLAG register */
1441 #define SERCOM_USART_INT_INTFLAG_CTSIC_Pos    _UINT8_(4)                                           /* (SERCOM_USART_INT_INTFLAG) Clear To Send Input Change Interrupt Position */
1442 #define SERCOM_USART_INT_INTFLAG_CTSIC_Msk    (_UINT8_(0x1) << SERCOM_USART_INT_INTFLAG_CTSIC_Pos) /* (SERCOM_USART_INT_INTFLAG) Clear To Send Input Change Interrupt Mask */
1443 #define SERCOM_USART_INT_INTFLAG_CTSIC(value) (SERCOM_USART_INT_INTFLAG_CTSIC_Msk & (_UINT8_(value) << SERCOM_USART_INT_INTFLAG_CTSIC_Pos)) /* Assigment of value for CTSIC in the SERCOM_USART_INT_INTFLAG register */
1444 #define SERCOM_USART_INT_INTFLAG_RXBRK_Pos    _UINT8_(5)                                           /* (SERCOM_USART_INT_INTFLAG) Break Received Interrupt Position */
1445 #define SERCOM_USART_INT_INTFLAG_RXBRK_Msk    (_UINT8_(0x1) << SERCOM_USART_INT_INTFLAG_RXBRK_Pos) /* (SERCOM_USART_INT_INTFLAG) Break Received Interrupt Mask */
1446 #define SERCOM_USART_INT_INTFLAG_RXBRK(value) (SERCOM_USART_INT_INTFLAG_RXBRK_Msk & (_UINT8_(value) << SERCOM_USART_INT_INTFLAG_RXBRK_Pos)) /* Assigment of value for RXBRK in the SERCOM_USART_INT_INTFLAG register */
1447 #define SERCOM_USART_INT_INTFLAG_ERROR_Pos    _UINT8_(7)                                           /* (SERCOM_USART_INT_INTFLAG) Combined Error Interrupt Position */
1448 #define SERCOM_USART_INT_INTFLAG_ERROR_Msk    (_UINT8_(0x1) << SERCOM_USART_INT_INTFLAG_ERROR_Pos) /* (SERCOM_USART_INT_INTFLAG) Combined Error Interrupt Mask */
1449 #define SERCOM_USART_INT_INTFLAG_ERROR(value) (SERCOM_USART_INT_INTFLAG_ERROR_Msk & (_UINT8_(value) << SERCOM_USART_INT_INTFLAG_ERROR_Pos)) /* Assigment of value for ERROR in the SERCOM_USART_INT_INTFLAG register */
1450 #define SERCOM_USART_INT_INTFLAG_Msk          _UINT8_(0xBF)                                        /* (SERCOM_USART_INT_INTFLAG) Register Mask  */
1451 
1452 
1453 /* -------- SERCOM_I2CM_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CM Status -------- */
1454 #define SERCOM_I2CM_STATUS_RESETVALUE         _UINT16_(0x00)                                       /*  (SERCOM_I2CM_STATUS) I2CM Status  Reset Value */
1455 
1456 #define SERCOM_I2CM_STATUS_BUSERR_Pos         _UINT16_(0)                                          /* (SERCOM_I2CM_STATUS) Bus Error Position */
1457 #define SERCOM_I2CM_STATUS_BUSERR_Msk         (_UINT16_(0x1) << SERCOM_I2CM_STATUS_BUSERR_Pos)     /* (SERCOM_I2CM_STATUS) Bus Error Mask */
1458 #define SERCOM_I2CM_STATUS_BUSERR(value)      (SERCOM_I2CM_STATUS_BUSERR_Msk & (_UINT16_(value) << SERCOM_I2CM_STATUS_BUSERR_Pos)) /* Assigment of value for BUSERR in the SERCOM_I2CM_STATUS register */
1459 #define SERCOM_I2CM_STATUS_ARBLOST_Pos        _UINT16_(1)                                          /* (SERCOM_I2CM_STATUS) Arbitration Lost Position */
1460 #define SERCOM_I2CM_STATUS_ARBLOST_Msk        (_UINT16_(0x1) << SERCOM_I2CM_STATUS_ARBLOST_Pos)    /* (SERCOM_I2CM_STATUS) Arbitration Lost Mask */
1461 #define SERCOM_I2CM_STATUS_ARBLOST(value)     (SERCOM_I2CM_STATUS_ARBLOST_Msk & (_UINT16_(value) << SERCOM_I2CM_STATUS_ARBLOST_Pos)) /* Assigment of value for ARBLOST in the SERCOM_I2CM_STATUS register */
1462 #define SERCOM_I2CM_STATUS_RXNACK_Pos         _UINT16_(2)                                          /* (SERCOM_I2CM_STATUS) Received Not Acknowledge Position */
1463 #define SERCOM_I2CM_STATUS_RXNACK_Msk         (_UINT16_(0x1) << SERCOM_I2CM_STATUS_RXNACK_Pos)     /* (SERCOM_I2CM_STATUS) Received Not Acknowledge Mask */
1464 #define SERCOM_I2CM_STATUS_RXNACK(value)      (SERCOM_I2CM_STATUS_RXNACK_Msk & (_UINT16_(value) << SERCOM_I2CM_STATUS_RXNACK_Pos)) /* Assigment of value for RXNACK in the SERCOM_I2CM_STATUS register */
1465 #define SERCOM_I2CM_STATUS_BUSSTATE_Pos       _UINT16_(4)                                          /* (SERCOM_I2CM_STATUS) Bus State Position */
1466 #define SERCOM_I2CM_STATUS_BUSSTATE_Msk       (_UINT16_(0x3) << SERCOM_I2CM_STATUS_BUSSTATE_Pos)   /* (SERCOM_I2CM_STATUS) Bus State Mask */
1467 #define SERCOM_I2CM_STATUS_BUSSTATE(value)    (SERCOM_I2CM_STATUS_BUSSTATE_Msk & (_UINT16_(value) << SERCOM_I2CM_STATUS_BUSSTATE_Pos)) /* Assigment of value for BUSSTATE in the SERCOM_I2CM_STATUS register */
1468 #define   SERCOM_I2CM_STATUS_BUSSTATE_UNKNOWN_Val _UINT16_(0x0)                                        /* (SERCOM_I2CM_STATUS) The Bus state is unknown to the I2C Host  */
1469 #define   SERCOM_I2CM_STATUS_BUSSTATE_IDLE_Val _UINT16_(0x1)                                        /* (SERCOM_I2CM_STATUS) The Bus state is waiting for a transaction to be initialized  */
1470 #define   SERCOM_I2CM_STATUS_BUSSTATE_OWNER_Val _UINT16_(0x2)                                        /* (SERCOM_I2CM_STATUS) The I2C Host is the current owner of the bus  */
1471 #define   SERCOM_I2CM_STATUS_BUSSTATE_BUSY_Val _UINT16_(0x3)                                        /* (SERCOM_I2CM_STATUS) Some other I2C Host owns the bus  */
1472 #define SERCOM_I2CM_STATUS_BUSSTATE_UNKNOWN   (SERCOM_I2CM_STATUS_BUSSTATE_UNKNOWN_Val << SERCOM_I2CM_STATUS_BUSSTATE_Pos) /* (SERCOM_I2CM_STATUS) The Bus state is unknown to the I2C Host Position  */
1473 #define SERCOM_I2CM_STATUS_BUSSTATE_IDLE      (SERCOM_I2CM_STATUS_BUSSTATE_IDLE_Val << SERCOM_I2CM_STATUS_BUSSTATE_Pos) /* (SERCOM_I2CM_STATUS) The Bus state is waiting for a transaction to be initialized Position  */
1474 #define SERCOM_I2CM_STATUS_BUSSTATE_OWNER     (SERCOM_I2CM_STATUS_BUSSTATE_OWNER_Val << SERCOM_I2CM_STATUS_BUSSTATE_Pos) /* (SERCOM_I2CM_STATUS) The I2C Host is the current owner of the bus Position  */
1475 #define SERCOM_I2CM_STATUS_BUSSTATE_BUSY      (SERCOM_I2CM_STATUS_BUSSTATE_BUSY_Val << SERCOM_I2CM_STATUS_BUSSTATE_Pos) /* (SERCOM_I2CM_STATUS) Some other I2C Host owns the bus Position  */
1476 #define SERCOM_I2CM_STATUS_LOWTOUT_Pos        _UINT16_(6)                                          /* (SERCOM_I2CM_STATUS) SCL Low Timeout Position */
1477 #define SERCOM_I2CM_STATUS_LOWTOUT_Msk        (_UINT16_(0x1) << SERCOM_I2CM_STATUS_LOWTOUT_Pos)    /* (SERCOM_I2CM_STATUS) SCL Low Timeout Mask */
1478 #define SERCOM_I2CM_STATUS_LOWTOUT(value)     (SERCOM_I2CM_STATUS_LOWTOUT_Msk & (_UINT16_(value) << SERCOM_I2CM_STATUS_LOWTOUT_Pos)) /* Assigment of value for LOWTOUT in the SERCOM_I2CM_STATUS register */
1479 #define SERCOM_I2CM_STATUS_CLKHOLD_Pos        _UINT16_(7)                                          /* (SERCOM_I2CM_STATUS) Clock Hold Position */
1480 #define SERCOM_I2CM_STATUS_CLKHOLD_Msk        (_UINT16_(0x1) << SERCOM_I2CM_STATUS_CLKHOLD_Pos)    /* (SERCOM_I2CM_STATUS) Clock Hold Mask */
1481 #define SERCOM_I2CM_STATUS_CLKHOLD(value)     (SERCOM_I2CM_STATUS_CLKHOLD_Msk & (_UINT16_(value) << SERCOM_I2CM_STATUS_CLKHOLD_Pos)) /* Assigment of value for CLKHOLD in the SERCOM_I2CM_STATUS register */
1482 #define SERCOM_I2CM_STATUS_MEXTTOUT_Pos       _UINT16_(8)                                          /* (SERCOM_I2CM_STATUS) Master SCL Low Extend Timeout Position */
1483 #define SERCOM_I2CM_STATUS_MEXTTOUT_Msk       (_UINT16_(0x1) << SERCOM_I2CM_STATUS_MEXTTOUT_Pos)   /* (SERCOM_I2CM_STATUS) Master SCL Low Extend Timeout Mask */
1484 #define SERCOM_I2CM_STATUS_MEXTTOUT(value)    (SERCOM_I2CM_STATUS_MEXTTOUT_Msk & (_UINT16_(value) << SERCOM_I2CM_STATUS_MEXTTOUT_Pos)) /* Assigment of value for MEXTTOUT in the SERCOM_I2CM_STATUS register */
1485 #define SERCOM_I2CM_STATUS_SEXTTOUT_Pos       _UINT16_(9)                                          /* (SERCOM_I2CM_STATUS) Slave SCL Low Extend Timeout Position */
1486 #define SERCOM_I2CM_STATUS_SEXTTOUT_Msk       (_UINT16_(0x1) << SERCOM_I2CM_STATUS_SEXTTOUT_Pos)   /* (SERCOM_I2CM_STATUS) Slave SCL Low Extend Timeout Mask */
1487 #define SERCOM_I2CM_STATUS_SEXTTOUT(value)    (SERCOM_I2CM_STATUS_SEXTTOUT_Msk & (_UINT16_(value) << SERCOM_I2CM_STATUS_SEXTTOUT_Pos)) /* Assigment of value for SEXTTOUT in the SERCOM_I2CM_STATUS register */
1488 #define SERCOM_I2CM_STATUS_LENERR_Pos         _UINT16_(10)                                         /* (SERCOM_I2CM_STATUS) Length Error Position */
1489 #define SERCOM_I2CM_STATUS_LENERR_Msk         (_UINT16_(0x1) << SERCOM_I2CM_STATUS_LENERR_Pos)     /* (SERCOM_I2CM_STATUS) Length Error Mask */
1490 #define SERCOM_I2CM_STATUS_LENERR(value)      (SERCOM_I2CM_STATUS_LENERR_Msk & (_UINT16_(value) << SERCOM_I2CM_STATUS_LENERR_Pos)) /* Assigment of value for LENERR in the SERCOM_I2CM_STATUS register */
1491 #define SERCOM_I2CM_STATUS_Msk                _UINT16_(0x07F7)                                     /* (SERCOM_I2CM_STATUS) Register Mask  */
1492 
1493 
1494 /* -------- SERCOM_I2CS_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CS Status -------- */
1495 #define SERCOM_I2CS_STATUS_RESETVALUE         _UINT16_(0x00)                                       /*  (SERCOM_I2CS_STATUS) I2CS Status  Reset Value */
1496 
1497 #define SERCOM_I2CS_STATUS_BUSERR_Pos         _UINT16_(0)                                          /* (SERCOM_I2CS_STATUS) Bus Error Position */
1498 #define SERCOM_I2CS_STATUS_BUSERR_Msk         (_UINT16_(0x1) << SERCOM_I2CS_STATUS_BUSERR_Pos)     /* (SERCOM_I2CS_STATUS) Bus Error Mask */
1499 #define SERCOM_I2CS_STATUS_BUSERR(value)      (SERCOM_I2CS_STATUS_BUSERR_Msk & (_UINT16_(value) << SERCOM_I2CS_STATUS_BUSERR_Pos)) /* Assigment of value for BUSERR in the SERCOM_I2CS_STATUS register */
1500 #define SERCOM_I2CS_STATUS_COLL_Pos           _UINT16_(1)                                          /* (SERCOM_I2CS_STATUS) Transmit Collision Position */
1501 #define SERCOM_I2CS_STATUS_COLL_Msk           (_UINT16_(0x1) << SERCOM_I2CS_STATUS_COLL_Pos)       /* (SERCOM_I2CS_STATUS) Transmit Collision Mask */
1502 #define SERCOM_I2CS_STATUS_COLL(value)        (SERCOM_I2CS_STATUS_COLL_Msk & (_UINT16_(value) << SERCOM_I2CS_STATUS_COLL_Pos)) /* Assigment of value for COLL in the SERCOM_I2CS_STATUS register */
1503 #define SERCOM_I2CS_STATUS_RXNACK_Pos         _UINT16_(2)                                          /* (SERCOM_I2CS_STATUS) Received Not Acknowledge Position */
1504 #define SERCOM_I2CS_STATUS_RXNACK_Msk         (_UINT16_(0x1) << SERCOM_I2CS_STATUS_RXNACK_Pos)     /* (SERCOM_I2CS_STATUS) Received Not Acknowledge Mask */
1505 #define SERCOM_I2CS_STATUS_RXNACK(value)      (SERCOM_I2CS_STATUS_RXNACK_Msk & (_UINT16_(value) << SERCOM_I2CS_STATUS_RXNACK_Pos)) /* Assigment of value for RXNACK in the SERCOM_I2CS_STATUS register */
1506 #define SERCOM_I2CS_STATUS_DIR_Pos            _UINT16_(3)                                          /* (SERCOM_I2CS_STATUS) Read/Write Direction Position */
1507 #define SERCOM_I2CS_STATUS_DIR_Msk            (_UINT16_(0x1) << SERCOM_I2CS_STATUS_DIR_Pos)        /* (SERCOM_I2CS_STATUS) Read/Write Direction Mask */
1508 #define SERCOM_I2CS_STATUS_DIR(value)         (SERCOM_I2CS_STATUS_DIR_Msk & (_UINT16_(value) << SERCOM_I2CS_STATUS_DIR_Pos)) /* Assigment of value for DIR in the SERCOM_I2CS_STATUS register */
1509 #define SERCOM_I2CS_STATUS_SR_Pos             _UINT16_(4)                                          /* (SERCOM_I2CS_STATUS) Repeated Start Position */
1510 #define SERCOM_I2CS_STATUS_SR_Msk             (_UINT16_(0x1) << SERCOM_I2CS_STATUS_SR_Pos)         /* (SERCOM_I2CS_STATUS) Repeated Start Mask */
1511 #define SERCOM_I2CS_STATUS_SR(value)          (SERCOM_I2CS_STATUS_SR_Msk & (_UINT16_(value) << SERCOM_I2CS_STATUS_SR_Pos)) /* Assigment of value for SR in the SERCOM_I2CS_STATUS register */
1512 #define SERCOM_I2CS_STATUS_LOWTOUT_Pos        _UINT16_(6)                                          /* (SERCOM_I2CS_STATUS) SCL Low Timeout Position */
1513 #define SERCOM_I2CS_STATUS_LOWTOUT_Msk        (_UINT16_(0x1) << SERCOM_I2CS_STATUS_LOWTOUT_Pos)    /* (SERCOM_I2CS_STATUS) SCL Low Timeout Mask */
1514 #define SERCOM_I2CS_STATUS_LOWTOUT(value)     (SERCOM_I2CS_STATUS_LOWTOUT_Msk & (_UINT16_(value) << SERCOM_I2CS_STATUS_LOWTOUT_Pos)) /* Assigment of value for LOWTOUT in the SERCOM_I2CS_STATUS register */
1515 #define SERCOM_I2CS_STATUS_CLKHOLD_Pos        _UINT16_(7)                                          /* (SERCOM_I2CS_STATUS) Clock Hold Position */
1516 #define SERCOM_I2CS_STATUS_CLKHOLD_Msk        (_UINT16_(0x1) << SERCOM_I2CS_STATUS_CLKHOLD_Pos)    /* (SERCOM_I2CS_STATUS) Clock Hold Mask */
1517 #define SERCOM_I2CS_STATUS_CLKHOLD(value)     (SERCOM_I2CS_STATUS_CLKHOLD_Msk & (_UINT16_(value) << SERCOM_I2CS_STATUS_CLKHOLD_Pos)) /* Assigment of value for CLKHOLD in the SERCOM_I2CS_STATUS register */
1518 #define SERCOM_I2CS_STATUS_SEXTTOUT_Pos       _UINT16_(9)                                          /* (SERCOM_I2CS_STATUS) Slave SCL Low Extend Timeout Position */
1519 #define SERCOM_I2CS_STATUS_SEXTTOUT_Msk       (_UINT16_(0x1) << SERCOM_I2CS_STATUS_SEXTTOUT_Pos)   /* (SERCOM_I2CS_STATUS) Slave SCL Low Extend Timeout Mask */
1520 #define SERCOM_I2CS_STATUS_SEXTTOUT(value)    (SERCOM_I2CS_STATUS_SEXTTOUT_Msk & (_UINT16_(value) << SERCOM_I2CS_STATUS_SEXTTOUT_Pos)) /* Assigment of value for SEXTTOUT in the SERCOM_I2CS_STATUS register */
1521 #define SERCOM_I2CS_STATUS_HS_Pos             _UINT16_(10)                                         /* (SERCOM_I2CS_STATUS) High Speed Position */
1522 #define SERCOM_I2CS_STATUS_HS_Msk             (_UINT16_(0x1) << SERCOM_I2CS_STATUS_HS_Pos)         /* (SERCOM_I2CS_STATUS) High Speed Mask */
1523 #define SERCOM_I2CS_STATUS_HS(value)          (SERCOM_I2CS_STATUS_HS_Msk & (_UINT16_(value) << SERCOM_I2CS_STATUS_HS_Pos)) /* Assigment of value for HS in the SERCOM_I2CS_STATUS register */
1524 #define SERCOM_I2CS_STATUS_LENERR_Pos         _UINT16_(11)                                         /* (SERCOM_I2CS_STATUS) Transaction Length Error Position */
1525 #define SERCOM_I2CS_STATUS_LENERR_Msk         (_UINT16_(0x1) << SERCOM_I2CS_STATUS_LENERR_Pos)     /* (SERCOM_I2CS_STATUS) Transaction Length Error Mask */
1526 #define SERCOM_I2CS_STATUS_LENERR(value)      (SERCOM_I2CS_STATUS_LENERR_Msk & (_UINT16_(value) << SERCOM_I2CS_STATUS_LENERR_Pos)) /* Assigment of value for LENERR in the SERCOM_I2CS_STATUS register */
1527 #define SERCOM_I2CS_STATUS_Msk                _UINT16_(0x0EDF)                                     /* (SERCOM_I2CS_STATUS) Register Mask  */
1528 
1529 
1530 /* -------- SERCOM_SPIM_STATUS : (SERCOM Offset: 0x1A) (R/W 16) SPIM Status -------- */
1531 #define SERCOM_SPIM_STATUS_RESETVALUE         _UINT16_(0x00)                                       /*  (SERCOM_SPIM_STATUS) SPIM Status  Reset Value */
1532 
1533 #define SERCOM_SPIM_STATUS_BUFOVF_Pos         _UINT16_(2)                                          /* (SERCOM_SPIM_STATUS) Buffer Overflow Position */
1534 #define SERCOM_SPIM_STATUS_BUFOVF_Msk         (_UINT16_(0x1) << SERCOM_SPIM_STATUS_BUFOVF_Pos)     /* (SERCOM_SPIM_STATUS) Buffer Overflow Mask */
1535 #define SERCOM_SPIM_STATUS_BUFOVF(value)      (SERCOM_SPIM_STATUS_BUFOVF_Msk & (_UINT16_(value) << SERCOM_SPIM_STATUS_BUFOVF_Pos)) /* Assigment of value for BUFOVF in the SERCOM_SPIM_STATUS register */
1536 #define SERCOM_SPIM_STATUS_LENERR_Pos         _UINT16_(11)                                         /* (SERCOM_SPIM_STATUS) Transaction Length Error Position */
1537 #define SERCOM_SPIM_STATUS_LENERR_Msk         (_UINT16_(0x1) << SERCOM_SPIM_STATUS_LENERR_Pos)     /* (SERCOM_SPIM_STATUS) Transaction Length Error Mask */
1538 #define SERCOM_SPIM_STATUS_LENERR(value)      (SERCOM_SPIM_STATUS_LENERR_Msk & (_UINT16_(value) << SERCOM_SPIM_STATUS_LENERR_Pos)) /* Assigment of value for LENERR in the SERCOM_SPIM_STATUS register */
1539 #define SERCOM_SPIM_STATUS_Msk                _UINT16_(0x0804)                                     /* (SERCOM_SPIM_STATUS) Register Mask  */
1540 
1541 
1542 /* -------- SERCOM_SPIS_STATUS : (SERCOM Offset: 0x1A) (R/W 16) SPIS Status -------- */
1543 #define SERCOM_SPIS_STATUS_RESETVALUE         _UINT16_(0x00)                                       /*  (SERCOM_SPIS_STATUS) SPIS Status  Reset Value */
1544 
1545 #define SERCOM_SPIS_STATUS_BUFOVF_Pos         _UINT16_(2)                                          /* (SERCOM_SPIS_STATUS) Buffer Overflow Position */
1546 #define SERCOM_SPIS_STATUS_BUFOVF_Msk         (_UINT16_(0x1) << SERCOM_SPIS_STATUS_BUFOVF_Pos)     /* (SERCOM_SPIS_STATUS) Buffer Overflow Mask */
1547 #define SERCOM_SPIS_STATUS_BUFOVF(value)      (SERCOM_SPIS_STATUS_BUFOVF_Msk & (_UINT16_(value) << SERCOM_SPIS_STATUS_BUFOVF_Pos)) /* Assigment of value for BUFOVF in the SERCOM_SPIS_STATUS register */
1548 #define SERCOM_SPIS_STATUS_LENERR_Pos         _UINT16_(11)                                         /* (SERCOM_SPIS_STATUS) Transaction Length Error Position */
1549 #define SERCOM_SPIS_STATUS_LENERR_Msk         (_UINT16_(0x1) << SERCOM_SPIS_STATUS_LENERR_Pos)     /* (SERCOM_SPIS_STATUS) Transaction Length Error Mask */
1550 #define SERCOM_SPIS_STATUS_LENERR(value)      (SERCOM_SPIS_STATUS_LENERR_Msk & (_UINT16_(value) << SERCOM_SPIS_STATUS_LENERR_Pos)) /* Assigment of value for LENERR in the SERCOM_SPIS_STATUS register */
1551 #define SERCOM_SPIS_STATUS_Msk                _UINT16_(0x0804)                                     /* (SERCOM_SPIS_STATUS) Register Mask  */
1552 
1553 
1554 /* -------- SERCOM_USART_EXT_STATUS : (SERCOM Offset: 0x1A) (R/W 16) USART_EXT Status -------- */
1555 #define SERCOM_USART_EXT_STATUS_RESETVALUE    _UINT16_(0x00)                                       /*  (SERCOM_USART_EXT_STATUS) USART_EXT Status  Reset Value */
1556 
1557 #define SERCOM_USART_EXT_STATUS_PERR_Pos      _UINT16_(0)                                          /* (SERCOM_USART_EXT_STATUS) Parity Error Position */
1558 #define SERCOM_USART_EXT_STATUS_PERR_Msk      (_UINT16_(0x1) << SERCOM_USART_EXT_STATUS_PERR_Pos)  /* (SERCOM_USART_EXT_STATUS) Parity Error Mask */
1559 #define SERCOM_USART_EXT_STATUS_PERR(value)   (SERCOM_USART_EXT_STATUS_PERR_Msk & (_UINT16_(value) << SERCOM_USART_EXT_STATUS_PERR_Pos)) /* Assigment of value for PERR in the SERCOM_USART_EXT_STATUS register */
1560 #define SERCOM_USART_EXT_STATUS_FERR_Pos      _UINT16_(1)                                          /* (SERCOM_USART_EXT_STATUS) Frame Error Position */
1561 #define SERCOM_USART_EXT_STATUS_FERR_Msk      (_UINT16_(0x1) << SERCOM_USART_EXT_STATUS_FERR_Pos)  /* (SERCOM_USART_EXT_STATUS) Frame Error Mask */
1562 #define SERCOM_USART_EXT_STATUS_FERR(value)   (SERCOM_USART_EXT_STATUS_FERR_Msk & (_UINT16_(value) << SERCOM_USART_EXT_STATUS_FERR_Pos)) /* Assigment of value for FERR in the SERCOM_USART_EXT_STATUS register */
1563 #define SERCOM_USART_EXT_STATUS_BUFOVF_Pos    _UINT16_(2)                                          /* (SERCOM_USART_EXT_STATUS) Buffer Overflow Position */
1564 #define SERCOM_USART_EXT_STATUS_BUFOVF_Msk    (_UINT16_(0x1) << SERCOM_USART_EXT_STATUS_BUFOVF_Pos) /* (SERCOM_USART_EXT_STATUS) Buffer Overflow Mask */
1565 #define SERCOM_USART_EXT_STATUS_BUFOVF(value) (SERCOM_USART_EXT_STATUS_BUFOVF_Msk & (_UINT16_(value) << SERCOM_USART_EXT_STATUS_BUFOVF_Pos)) /* Assigment of value for BUFOVF in the SERCOM_USART_EXT_STATUS register */
1566 #define SERCOM_USART_EXT_STATUS_CTS_Pos       _UINT16_(3)                                          /* (SERCOM_USART_EXT_STATUS) Clear To Send Position */
1567 #define SERCOM_USART_EXT_STATUS_CTS_Msk       (_UINT16_(0x1) << SERCOM_USART_EXT_STATUS_CTS_Pos)   /* (SERCOM_USART_EXT_STATUS) Clear To Send Mask */
1568 #define SERCOM_USART_EXT_STATUS_CTS(value)    (SERCOM_USART_EXT_STATUS_CTS_Msk & (_UINT16_(value) << SERCOM_USART_EXT_STATUS_CTS_Pos)) /* Assigment of value for CTS in the SERCOM_USART_EXT_STATUS register */
1569 #define SERCOM_USART_EXT_STATUS_ISF_Pos       _UINT16_(4)                                          /* (SERCOM_USART_EXT_STATUS) Inconsistent Sync Field Position */
1570 #define SERCOM_USART_EXT_STATUS_ISF_Msk       (_UINT16_(0x1) << SERCOM_USART_EXT_STATUS_ISF_Pos)   /* (SERCOM_USART_EXT_STATUS) Inconsistent Sync Field Mask */
1571 #define SERCOM_USART_EXT_STATUS_ISF(value)    (SERCOM_USART_EXT_STATUS_ISF_Msk & (_UINT16_(value) << SERCOM_USART_EXT_STATUS_ISF_Pos)) /* Assigment of value for ISF in the SERCOM_USART_EXT_STATUS register */
1572 #define SERCOM_USART_EXT_STATUS_COLL_Pos      _UINT16_(5)                                          /* (SERCOM_USART_EXT_STATUS) Collision Detected Position */
1573 #define SERCOM_USART_EXT_STATUS_COLL_Msk      (_UINT16_(0x1) << SERCOM_USART_EXT_STATUS_COLL_Pos)  /* (SERCOM_USART_EXT_STATUS) Collision Detected Mask */
1574 #define SERCOM_USART_EXT_STATUS_COLL(value)   (SERCOM_USART_EXT_STATUS_COLL_Msk & (_UINT16_(value) << SERCOM_USART_EXT_STATUS_COLL_Pos)) /* Assigment of value for COLL in the SERCOM_USART_EXT_STATUS register */
1575 #define SERCOM_USART_EXT_STATUS_TXE_Pos       _UINT16_(6)                                          /* (SERCOM_USART_EXT_STATUS) Transmitter Empty Position */
1576 #define SERCOM_USART_EXT_STATUS_TXE_Msk       (_UINT16_(0x1) << SERCOM_USART_EXT_STATUS_TXE_Pos)   /* (SERCOM_USART_EXT_STATUS) Transmitter Empty Mask */
1577 #define SERCOM_USART_EXT_STATUS_TXE(value)    (SERCOM_USART_EXT_STATUS_TXE_Msk & (_UINT16_(value) << SERCOM_USART_EXT_STATUS_TXE_Pos)) /* Assigment of value for TXE in the SERCOM_USART_EXT_STATUS register */
1578 #define SERCOM_USART_EXT_STATUS_ITER_Pos      _UINT16_(7)                                          /* (SERCOM_USART_EXT_STATUS) Maximum Number of Repetitions Reached Position */
1579 #define SERCOM_USART_EXT_STATUS_ITER_Msk      (_UINT16_(0x1) << SERCOM_USART_EXT_STATUS_ITER_Pos)  /* (SERCOM_USART_EXT_STATUS) Maximum Number of Repetitions Reached Mask */
1580 #define SERCOM_USART_EXT_STATUS_ITER(value)   (SERCOM_USART_EXT_STATUS_ITER_Msk & (_UINT16_(value) << SERCOM_USART_EXT_STATUS_ITER_Pos)) /* Assigment of value for ITER in the SERCOM_USART_EXT_STATUS register */
1581 #define SERCOM_USART_EXT_STATUS_Msk           _UINT16_(0x00FF)                                     /* (SERCOM_USART_EXT_STATUS) Register Mask  */
1582 
1583 
1584 /* -------- SERCOM_USART_INT_STATUS : (SERCOM Offset: 0x1A) (R/W 16) USART_INT Status -------- */
1585 #define SERCOM_USART_INT_STATUS_RESETVALUE    _UINT16_(0x00)                                       /*  (SERCOM_USART_INT_STATUS) USART_INT Status  Reset Value */
1586 
1587 #define SERCOM_USART_INT_STATUS_PERR_Pos      _UINT16_(0)                                          /* (SERCOM_USART_INT_STATUS) Parity Error Position */
1588 #define SERCOM_USART_INT_STATUS_PERR_Msk      (_UINT16_(0x1) << SERCOM_USART_INT_STATUS_PERR_Pos)  /* (SERCOM_USART_INT_STATUS) Parity Error Mask */
1589 #define SERCOM_USART_INT_STATUS_PERR(value)   (SERCOM_USART_INT_STATUS_PERR_Msk & (_UINT16_(value) << SERCOM_USART_INT_STATUS_PERR_Pos)) /* Assigment of value for PERR in the SERCOM_USART_INT_STATUS register */
1590 #define SERCOM_USART_INT_STATUS_FERR_Pos      _UINT16_(1)                                          /* (SERCOM_USART_INT_STATUS) Frame Error Position */
1591 #define SERCOM_USART_INT_STATUS_FERR_Msk      (_UINT16_(0x1) << SERCOM_USART_INT_STATUS_FERR_Pos)  /* (SERCOM_USART_INT_STATUS) Frame Error Mask */
1592 #define SERCOM_USART_INT_STATUS_FERR(value)   (SERCOM_USART_INT_STATUS_FERR_Msk & (_UINT16_(value) << SERCOM_USART_INT_STATUS_FERR_Pos)) /* Assigment of value for FERR in the SERCOM_USART_INT_STATUS register */
1593 #define SERCOM_USART_INT_STATUS_BUFOVF_Pos    _UINT16_(2)                                          /* (SERCOM_USART_INT_STATUS) Buffer Overflow Position */
1594 #define SERCOM_USART_INT_STATUS_BUFOVF_Msk    (_UINT16_(0x1) << SERCOM_USART_INT_STATUS_BUFOVF_Pos) /* (SERCOM_USART_INT_STATUS) Buffer Overflow Mask */
1595 #define SERCOM_USART_INT_STATUS_BUFOVF(value) (SERCOM_USART_INT_STATUS_BUFOVF_Msk & (_UINT16_(value) << SERCOM_USART_INT_STATUS_BUFOVF_Pos)) /* Assigment of value for BUFOVF in the SERCOM_USART_INT_STATUS register */
1596 #define SERCOM_USART_INT_STATUS_CTS_Pos       _UINT16_(3)                                          /* (SERCOM_USART_INT_STATUS) Clear To Send Position */
1597 #define SERCOM_USART_INT_STATUS_CTS_Msk       (_UINT16_(0x1) << SERCOM_USART_INT_STATUS_CTS_Pos)   /* (SERCOM_USART_INT_STATUS) Clear To Send Mask */
1598 #define SERCOM_USART_INT_STATUS_CTS(value)    (SERCOM_USART_INT_STATUS_CTS_Msk & (_UINT16_(value) << SERCOM_USART_INT_STATUS_CTS_Pos)) /* Assigment of value for CTS in the SERCOM_USART_INT_STATUS register */
1599 #define SERCOM_USART_INT_STATUS_ISF_Pos       _UINT16_(4)                                          /* (SERCOM_USART_INT_STATUS) Inconsistent Sync Field Position */
1600 #define SERCOM_USART_INT_STATUS_ISF_Msk       (_UINT16_(0x1) << SERCOM_USART_INT_STATUS_ISF_Pos)   /* (SERCOM_USART_INT_STATUS) Inconsistent Sync Field Mask */
1601 #define SERCOM_USART_INT_STATUS_ISF(value)    (SERCOM_USART_INT_STATUS_ISF_Msk & (_UINT16_(value) << SERCOM_USART_INT_STATUS_ISF_Pos)) /* Assigment of value for ISF in the SERCOM_USART_INT_STATUS register */
1602 #define SERCOM_USART_INT_STATUS_COLL_Pos      _UINT16_(5)                                          /* (SERCOM_USART_INT_STATUS) Collision Detected Position */
1603 #define SERCOM_USART_INT_STATUS_COLL_Msk      (_UINT16_(0x1) << SERCOM_USART_INT_STATUS_COLL_Pos)  /* (SERCOM_USART_INT_STATUS) Collision Detected Mask */
1604 #define SERCOM_USART_INT_STATUS_COLL(value)   (SERCOM_USART_INT_STATUS_COLL_Msk & (_UINT16_(value) << SERCOM_USART_INT_STATUS_COLL_Pos)) /* Assigment of value for COLL in the SERCOM_USART_INT_STATUS register */
1605 #define SERCOM_USART_INT_STATUS_TXE_Pos       _UINT16_(6)                                          /* (SERCOM_USART_INT_STATUS) Transmitter Empty Position */
1606 #define SERCOM_USART_INT_STATUS_TXE_Msk       (_UINT16_(0x1) << SERCOM_USART_INT_STATUS_TXE_Pos)   /* (SERCOM_USART_INT_STATUS) Transmitter Empty Mask */
1607 #define SERCOM_USART_INT_STATUS_TXE(value)    (SERCOM_USART_INT_STATUS_TXE_Msk & (_UINT16_(value) << SERCOM_USART_INT_STATUS_TXE_Pos)) /* Assigment of value for TXE in the SERCOM_USART_INT_STATUS register */
1608 #define SERCOM_USART_INT_STATUS_ITER_Pos      _UINT16_(7)                                          /* (SERCOM_USART_INT_STATUS) Maximum Number of Repetitions Reached Position */
1609 #define SERCOM_USART_INT_STATUS_ITER_Msk      (_UINT16_(0x1) << SERCOM_USART_INT_STATUS_ITER_Pos)  /* (SERCOM_USART_INT_STATUS) Maximum Number of Repetitions Reached Mask */
1610 #define SERCOM_USART_INT_STATUS_ITER(value)   (SERCOM_USART_INT_STATUS_ITER_Msk & (_UINT16_(value) << SERCOM_USART_INT_STATUS_ITER_Pos)) /* Assigment of value for ITER in the SERCOM_USART_INT_STATUS register */
1611 #define SERCOM_USART_INT_STATUS_Msk           _UINT16_(0x00FF)                                     /* (SERCOM_USART_INT_STATUS) Register Mask  */
1612 
1613 
1614 /* -------- SERCOM_I2CM_SYNCBUSY : (SERCOM Offset: 0x1C) ( R/ 32) I2CM Synchronization Busy -------- */
1615 #define SERCOM_I2CM_SYNCBUSY_RESETVALUE       _UINT32_(0x00)                                       /*  (SERCOM_I2CM_SYNCBUSY) I2CM Synchronization Busy  Reset Value */
1616 
1617 #define SERCOM_I2CM_SYNCBUSY_SWRST_Pos        _UINT32_(0)                                          /* (SERCOM_I2CM_SYNCBUSY) Software Reset Synchronization Busy Position */
1618 #define SERCOM_I2CM_SYNCBUSY_SWRST_Msk        (_UINT32_(0x1) << SERCOM_I2CM_SYNCBUSY_SWRST_Pos)    /* (SERCOM_I2CM_SYNCBUSY) Software Reset Synchronization Busy Mask */
1619 #define SERCOM_I2CM_SYNCBUSY_SWRST(value)     (SERCOM_I2CM_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << SERCOM_I2CM_SYNCBUSY_SWRST_Pos)) /* Assigment of value for SWRST in the SERCOM_I2CM_SYNCBUSY register */
1620 #define SERCOM_I2CM_SYNCBUSY_ENABLE_Pos       _UINT32_(1)                                          /* (SERCOM_I2CM_SYNCBUSY) SERCOM Enable Synchronization Busy Position */
1621 #define SERCOM_I2CM_SYNCBUSY_ENABLE_Msk       (_UINT32_(0x1) << SERCOM_I2CM_SYNCBUSY_ENABLE_Pos)   /* (SERCOM_I2CM_SYNCBUSY) SERCOM Enable Synchronization Busy Mask */
1622 #define SERCOM_I2CM_SYNCBUSY_ENABLE(value)    (SERCOM_I2CM_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << SERCOM_I2CM_SYNCBUSY_ENABLE_Pos)) /* Assigment of value for ENABLE in the SERCOM_I2CM_SYNCBUSY register */
1623 #define SERCOM_I2CM_SYNCBUSY_SYSOP_Pos        _UINT32_(2)                                          /* (SERCOM_I2CM_SYNCBUSY) System Operation Synchronization Busy Position */
1624 #define SERCOM_I2CM_SYNCBUSY_SYSOP_Msk        (_UINT32_(0x1) << SERCOM_I2CM_SYNCBUSY_SYSOP_Pos)    /* (SERCOM_I2CM_SYNCBUSY) System Operation Synchronization Busy Mask */
1625 #define SERCOM_I2CM_SYNCBUSY_SYSOP(value)     (SERCOM_I2CM_SYNCBUSY_SYSOP_Msk & (_UINT32_(value) << SERCOM_I2CM_SYNCBUSY_SYSOP_Pos)) /* Assigment of value for SYSOP in the SERCOM_I2CM_SYNCBUSY register */
1626 #define SERCOM_I2CM_SYNCBUSY_Msk              _UINT32_(0x00000007)                                 /* (SERCOM_I2CM_SYNCBUSY) Register Mask  */
1627 
1628 
1629 /* -------- SERCOM_I2CS_SYNCBUSY : (SERCOM Offset: 0x1C) ( R/ 32) I2CS Synchronization Busy -------- */
1630 #define SERCOM_I2CS_SYNCBUSY_RESETVALUE       _UINT32_(0x00)                                       /*  (SERCOM_I2CS_SYNCBUSY) I2CS Synchronization Busy  Reset Value */
1631 
1632 #define SERCOM_I2CS_SYNCBUSY_SWRST_Pos        _UINT32_(0)                                          /* (SERCOM_I2CS_SYNCBUSY) Software Reset Synchronization Busy Position */
1633 #define SERCOM_I2CS_SYNCBUSY_SWRST_Msk        (_UINT32_(0x1) << SERCOM_I2CS_SYNCBUSY_SWRST_Pos)    /* (SERCOM_I2CS_SYNCBUSY) Software Reset Synchronization Busy Mask */
1634 #define SERCOM_I2CS_SYNCBUSY_SWRST(value)     (SERCOM_I2CS_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << SERCOM_I2CS_SYNCBUSY_SWRST_Pos)) /* Assigment of value for SWRST in the SERCOM_I2CS_SYNCBUSY register */
1635 #define SERCOM_I2CS_SYNCBUSY_ENABLE_Pos       _UINT32_(1)                                          /* (SERCOM_I2CS_SYNCBUSY) SERCOM Enable Synchronization Busy Position */
1636 #define SERCOM_I2CS_SYNCBUSY_ENABLE_Msk       (_UINT32_(0x1) << SERCOM_I2CS_SYNCBUSY_ENABLE_Pos)   /* (SERCOM_I2CS_SYNCBUSY) SERCOM Enable Synchronization Busy Mask */
1637 #define SERCOM_I2CS_SYNCBUSY_ENABLE(value)    (SERCOM_I2CS_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << SERCOM_I2CS_SYNCBUSY_ENABLE_Pos)) /* Assigment of value for ENABLE in the SERCOM_I2CS_SYNCBUSY register */
1638 #define SERCOM_I2CS_SYNCBUSY_LENGTH_Pos       _UINT32_(4)                                          /* (SERCOM_I2CS_SYNCBUSY) Length Synchronization Busy Position */
1639 #define SERCOM_I2CS_SYNCBUSY_LENGTH_Msk       (_UINT32_(0x1) << SERCOM_I2CS_SYNCBUSY_LENGTH_Pos)   /* (SERCOM_I2CS_SYNCBUSY) Length Synchronization Busy Mask */
1640 #define SERCOM_I2CS_SYNCBUSY_LENGTH(value)    (SERCOM_I2CS_SYNCBUSY_LENGTH_Msk & (_UINT32_(value) << SERCOM_I2CS_SYNCBUSY_LENGTH_Pos)) /* Assigment of value for LENGTH in the SERCOM_I2CS_SYNCBUSY register */
1641 #define SERCOM_I2CS_SYNCBUSY_Msk              _UINT32_(0x00000013)                                 /* (SERCOM_I2CS_SYNCBUSY) Register Mask  */
1642 
1643 
1644 /* -------- SERCOM_SPIM_SYNCBUSY : (SERCOM Offset: 0x1C) ( R/ 32) SPIM Synchronization Busy -------- */
1645 #define SERCOM_SPIM_SYNCBUSY_RESETVALUE       _UINT32_(0x00)                                       /*  (SERCOM_SPIM_SYNCBUSY) SPIM Synchronization Busy  Reset Value */
1646 
1647 #define SERCOM_SPIM_SYNCBUSY_SWRST_Pos        _UINT32_(0)                                          /* (SERCOM_SPIM_SYNCBUSY) Software Reset Synchronization Busy Position */
1648 #define SERCOM_SPIM_SYNCBUSY_SWRST_Msk        (_UINT32_(0x1) << SERCOM_SPIM_SYNCBUSY_SWRST_Pos)    /* (SERCOM_SPIM_SYNCBUSY) Software Reset Synchronization Busy Mask */
1649 #define SERCOM_SPIM_SYNCBUSY_SWRST(value)     (SERCOM_SPIM_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << SERCOM_SPIM_SYNCBUSY_SWRST_Pos)) /* Assigment of value for SWRST in the SERCOM_SPIM_SYNCBUSY register */
1650 #define SERCOM_SPIM_SYNCBUSY_ENABLE_Pos       _UINT32_(1)                                          /* (SERCOM_SPIM_SYNCBUSY) SERCOM Enable Synchronization Busy Position */
1651 #define SERCOM_SPIM_SYNCBUSY_ENABLE_Msk       (_UINT32_(0x1) << SERCOM_SPIM_SYNCBUSY_ENABLE_Pos)   /* (SERCOM_SPIM_SYNCBUSY) SERCOM Enable Synchronization Busy Mask */
1652 #define SERCOM_SPIM_SYNCBUSY_ENABLE(value)    (SERCOM_SPIM_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << SERCOM_SPIM_SYNCBUSY_ENABLE_Pos)) /* Assigment of value for ENABLE in the SERCOM_SPIM_SYNCBUSY register */
1653 #define SERCOM_SPIM_SYNCBUSY_CTRLB_Pos        _UINT32_(2)                                          /* (SERCOM_SPIM_SYNCBUSY) CTRLB Synchronization Busy Position */
1654 #define SERCOM_SPIM_SYNCBUSY_CTRLB_Msk        (_UINT32_(0x1) << SERCOM_SPIM_SYNCBUSY_CTRLB_Pos)    /* (SERCOM_SPIM_SYNCBUSY) CTRLB Synchronization Busy Mask */
1655 #define SERCOM_SPIM_SYNCBUSY_CTRLB(value)     (SERCOM_SPIM_SYNCBUSY_CTRLB_Msk & (_UINT32_(value) << SERCOM_SPIM_SYNCBUSY_CTRLB_Pos)) /* Assigment of value for CTRLB in the SERCOM_SPIM_SYNCBUSY register */
1656 #define SERCOM_SPIM_SYNCBUSY_LENGTH_Pos       _UINT32_(4)                                          /* (SERCOM_SPIM_SYNCBUSY) LENGTH Synchronization Busy Position */
1657 #define SERCOM_SPIM_SYNCBUSY_LENGTH_Msk       (_UINT32_(0x1) << SERCOM_SPIM_SYNCBUSY_LENGTH_Pos)   /* (SERCOM_SPIM_SYNCBUSY) LENGTH Synchronization Busy Mask */
1658 #define SERCOM_SPIM_SYNCBUSY_LENGTH(value)    (SERCOM_SPIM_SYNCBUSY_LENGTH_Msk & (_UINT32_(value) << SERCOM_SPIM_SYNCBUSY_LENGTH_Pos)) /* Assigment of value for LENGTH in the SERCOM_SPIM_SYNCBUSY register */
1659 #define SERCOM_SPIM_SYNCBUSY_Msk              _UINT32_(0x00000017)                                 /* (SERCOM_SPIM_SYNCBUSY) Register Mask  */
1660 
1661 
1662 /* -------- SERCOM_SPIS_SYNCBUSY : (SERCOM Offset: 0x1C) ( R/ 32) SPIS Synchronization Busy -------- */
1663 #define SERCOM_SPIS_SYNCBUSY_RESETVALUE       _UINT32_(0x00)                                       /*  (SERCOM_SPIS_SYNCBUSY) SPIS Synchronization Busy  Reset Value */
1664 
1665 #define SERCOM_SPIS_SYNCBUSY_SWRST_Pos        _UINT32_(0)                                          /* (SERCOM_SPIS_SYNCBUSY) Software Reset Synchronization Busy Position */
1666 #define SERCOM_SPIS_SYNCBUSY_SWRST_Msk        (_UINT32_(0x1) << SERCOM_SPIS_SYNCBUSY_SWRST_Pos)    /* (SERCOM_SPIS_SYNCBUSY) Software Reset Synchronization Busy Mask */
1667 #define SERCOM_SPIS_SYNCBUSY_SWRST(value)     (SERCOM_SPIS_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << SERCOM_SPIS_SYNCBUSY_SWRST_Pos)) /* Assigment of value for SWRST in the SERCOM_SPIS_SYNCBUSY register */
1668 #define SERCOM_SPIS_SYNCBUSY_ENABLE_Pos       _UINT32_(1)                                          /* (SERCOM_SPIS_SYNCBUSY) SERCOM Enable Synchronization Busy Position */
1669 #define SERCOM_SPIS_SYNCBUSY_ENABLE_Msk       (_UINT32_(0x1) << SERCOM_SPIS_SYNCBUSY_ENABLE_Pos)   /* (SERCOM_SPIS_SYNCBUSY) SERCOM Enable Synchronization Busy Mask */
1670 #define SERCOM_SPIS_SYNCBUSY_ENABLE(value)    (SERCOM_SPIS_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << SERCOM_SPIS_SYNCBUSY_ENABLE_Pos)) /* Assigment of value for ENABLE in the SERCOM_SPIS_SYNCBUSY register */
1671 #define SERCOM_SPIS_SYNCBUSY_CTRLB_Pos        _UINT32_(2)                                          /* (SERCOM_SPIS_SYNCBUSY) CTRLB Synchronization Busy Position */
1672 #define SERCOM_SPIS_SYNCBUSY_CTRLB_Msk        (_UINT32_(0x1) << SERCOM_SPIS_SYNCBUSY_CTRLB_Pos)    /* (SERCOM_SPIS_SYNCBUSY) CTRLB Synchronization Busy Mask */
1673 #define SERCOM_SPIS_SYNCBUSY_CTRLB(value)     (SERCOM_SPIS_SYNCBUSY_CTRLB_Msk & (_UINT32_(value) << SERCOM_SPIS_SYNCBUSY_CTRLB_Pos)) /* Assigment of value for CTRLB in the SERCOM_SPIS_SYNCBUSY register */
1674 #define SERCOM_SPIS_SYNCBUSY_LENGTH_Pos       _UINT32_(4)                                          /* (SERCOM_SPIS_SYNCBUSY) LENGTH Synchronization Busy Position */
1675 #define SERCOM_SPIS_SYNCBUSY_LENGTH_Msk       (_UINT32_(0x1) << SERCOM_SPIS_SYNCBUSY_LENGTH_Pos)   /* (SERCOM_SPIS_SYNCBUSY) LENGTH Synchronization Busy Mask */
1676 #define SERCOM_SPIS_SYNCBUSY_LENGTH(value)    (SERCOM_SPIS_SYNCBUSY_LENGTH_Msk & (_UINT32_(value) << SERCOM_SPIS_SYNCBUSY_LENGTH_Pos)) /* Assigment of value for LENGTH in the SERCOM_SPIS_SYNCBUSY register */
1677 #define SERCOM_SPIS_SYNCBUSY_Msk              _UINT32_(0x00000017)                                 /* (SERCOM_SPIS_SYNCBUSY) Register Mask  */
1678 
1679 
1680 /* -------- SERCOM_USART_EXT_SYNCBUSY : (SERCOM Offset: 0x1C) ( R/ 32) USART_EXT Synchronization Busy -------- */
1681 #define SERCOM_USART_EXT_SYNCBUSY_RESETVALUE  _UINT32_(0x00)                                       /*  (SERCOM_USART_EXT_SYNCBUSY) USART_EXT Synchronization Busy  Reset Value */
1682 
1683 #define SERCOM_USART_EXT_SYNCBUSY_SWRST_Pos   _UINT32_(0)                                          /* (SERCOM_USART_EXT_SYNCBUSY) Software Reset Synchronization Busy Position */
1684 #define SERCOM_USART_EXT_SYNCBUSY_SWRST_Msk   (_UINT32_(0x1) << SERCOM_USART_EXT_SYNCBUSY_SWRST_Pos) /* (SERCOM_USART_EXT_SYNCBUSY) Software Reset Synchronization Busy Mask */
1685 #define SERCOM_USART_EXT_SYNCBUSY_SWRST(value) (SERCOM_USART_EXT_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << SERCOM_USART_EXT_SYNCBUSY_SWRST_Pos)) /* Assigment of value for SWRST in the SERCOM_USART_EXT_SYNCBUSY register */
1686 #define SERCOM_USART_EXT_SYNCBUSY_ENABLE_Pos  _UINT32_(1)                                          /* (SERCOM_USART_EXT_SYNCBUSY) SERCOM Enable Synchronization Busy Position */
1687 #define SERCOM_USART_EXT_SYNCBUSY_ENABLE_Msk  (_UINT32_(0x1) << SERCOM_USART_EXT_SYNCBUSY_ENABLE_Pos) /* (SERCOM_USART_EXT_SYNCBUSY) SERCOM Enable Synchronization Busy Mask */
1688 #define SERCOM_USART_EXT_SYNCBUSY_ENABLE(value) (SERCOM_USART_EXT_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << SERCOM_USART_EXT_SYNCBUSY_ENABLE_Pos)) /* Assigment of value for ENABLE in the SERCOM_USART_EXT_SYNCBUSY register */
1689 #define SERCOM_USART_EXT_SYNCBUSY_CTRLB_Pos   _UINT32_(2)                                          /* (SERCOM_USART_EXT_SYNCBUSY) CTRLB Synchronization Busy Position */
1690 #define SERCOM_USART_EXT_SYNCBUSY_CTRLB_Msk   (_UINT32_(0x1) << SERCOM_USART_EXT_SYNCBUSY_CTRLB_Pos) /* (SERCOM_USART_EXT_SYNCBUSY) CTRLB Synchronization Busy Mask */
1691 #define SERCOM_USART_EXT_SYNCBUSY_CTRLB(value) (SERCOM_USART_EXT_SYNCBUSY_CTRLB_Msk & (_UINT32_(value) << SERCOM_USART_EXT_SYNCBUSY_CTRLB_Pos)) /* Assigment of value for CTRLB in the SERCOM_USART_EXT_SYNCBUSY register */
1692 #define SERCOM_USART_EXT_SYNCBUSY_RXERRCNT_Pos _UINT32_(3)                                          /* (SERCOM_USART_EXT_SYNCBUSY) RXERRCNT Synchronization Busy Position */
1693 #define SERCOM_USART_EXT_SYNCBUSY_RXERRCNT_Msk (_UINT32_(0x1) << SERCOM_USART_EXT_SYNCBUSY_RXERRCNT_Pos) /* (SERCOM_USART_EXT_SYNCBUSY) RXERRCNT Synchronization Busy Mask */
1694 #define SERCOM_USART_EXT_SYNCBUSY_RXERRCNT(value) (SERCOM_USART_EXT_SYNCBUSY_RXERRCNT_Msk & (_UINT32_(value) << SERCOM_USART_EXT_SYNCBUSY_RXERRCNT_Pos)) /* Assigment of value for RXERRCNT in the SERCOM_USART_EXT_SYNCBUSY register */
1695 #define SERCOM_USART_EXT_SYNCBUSY_LENGTH_Pos  _UINT32_(4)                                          /* (SERCOM_USART_EXT_SYNCBUSY) LENGTH Synchronization Busy Position */
1696 #define SERCOM_USART_EXT_SYNCBUSY_LENGTH_Msk  (_UINT32_(0x1) << SERCOM_USART_EXT_SYNCBUSY_LENGTH_Pos) /* (SERCOM_USART_EXT_SYNCBUSY) LENGTH Synchronization Busy Mask */
1697 #define SERCOM_USART_EXT_SYNCBUSY_LENGTH(value) (SERCOM_USART_EXT_SYNCBUSY_LENGTH_Msk & (_UINT32_(value) << SERCOM_USART_EXT_SYNCBUSY_LENGTH_Pos)) /* Assigment of value for LENGTH in the SERCOM_USART_EXT_SYNCBUSY register */
1698 #define SERCOM_USART_EXT_SYNCBUSY_Msk         _UINT32_(0x0000001F)                                 /* (SERCOM_USART_EXT_SYNCBUSY) Register Mask  */
1699 
1700 
1701 /* -------- SERCOM_USART_INT_SYNCBUSY : (SERCOM Offset: 0x1C) ( R/ 32) USART_INT Synchronization Busy -------- */
1702 #define SERCOM_USART_INT_SYNCBUSY_RESETVALUE  _UINT32_(0x00)                                       /*  (SERCOM_USART_INT_SYNCBUSY) USART_INT Synchronization Busy  Reset Value */
1703 
1704 #define SERCOM_USART_INT_SYNCBUSY_SWRST_Pos   _UINT32_(0)                                          /* (SERCOM_USART_INT_SYNCBUSY) Software Reset Synchronization Busy Position */
1705 #define SERCOM_USART_INT_SYNCBUSY_SWRST_Msk   (_UINT32_(0x1) << SERCOM_USART_INT_SYNCBUSY_SWRST_Pos) /* (SERCOM_USART_INT_SYNCBUSY) Software Reset Synchronization Busy Mask */
1706 #define SERCOM_USART_INT_SYNCBUSY_SWRST(value) (SERCOM_USART_INT_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << SERCOM_USART_INT_SYNCBUSY_SWRST_Pos)) /* Assigment of value for SWRST in the SERCOM_USART_INT_SYNCBUSY register */
1707 #define SERCOM_USART_INT_SYNCBUSY_ENABLE_Pos  _UINT32_(1)                                          /* (SERCOM_USART_INT_SYNCBUSY) SERCOM Enable Synchronization Busy Position */
1708 #define SERCOM_USART_INT_SYNCBUSY_ENABLE_Msk  (_UINT32_(0x1) << SERCOM_USART_INT_SYNCBUSY_ENABLE_Pos) /* (SERCOM_USART_INT_SYNCBUSY) SERCOM Enable Synchronization Busy Mask */
1709 #define SERCOM_USART_INT_SYNCBUSY_ENABLE(value) (SERCOM_USART_INT_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << SERCOM_USART_INT_SYNCBUSY_ENABLE_Pos)) /* Assigment of value for ENABLE in the SERCOM_USART_INT_SYNCBUSY register */
1710 #define SERCOM_USART_INT_SYNCBUSY_CTRLB_Pos   _UINT32_(2)                                          /* (SERCOM_USART_INT_SYNCBUSY) CTRLB Synchronization Busy Position */
1711 #define SERCOM_USART_INT_SYNCBUSY_CTRLB_Msk   (_UINT32_(0x1) << SERCOM_USART_INT_SYNCBUSY_CTRLB_Pos) /* (SERCOM_USART_INT_SYNCBUSY) CTRLB Synchronization Busy Mask */
1712 #define SERCOM_USART_INT_SYNCBUSY_CTRLB(value) (SERCOM_USART_INT_SYNCBUSY_CTRLB_Msk & (_UINT32_(value) << SERCOM_USART_INT_SYNCBUSY_CTRLB_Pos)) /* Assigment of value for CTRLB in the SERCOM_USART_INT_SYNCBUSY register */
1713 #define SERCOM_USART_INT_SYNCBUSY_RXERRCNT_Pos _UINT32_(3)                                          /* (SERCOM_USART_INT_SYNCBUSY) RXERRCNT Synchronization Busy Position */
1714 #define SERCOM_USART_INT_SYNCBUSY_RXERRCNT_Msk (_UINT32_(0x1) << SERCOM_USART_INT_SYNCBUSY_RXERRCNT_Pos) /* (SERCOM_USART_INT_SYNCBUSY) RXERRCNT Synchronization Busy Mask */
1715 #define SERCOM_USART_INT_SYNCBUSY_RXERRCNT(value) (SERCOM_USART_INT_SYNCBUSY_RXERRCNT_Msk & (_UINT32_(value) << SERCOM_USART_INT_SYNCBUSY_RXERRCNT_Pos)) /* Assigment of value for RXERRCNT in the SERCOM_USART_INT_SYNCBUSY register */
1716 #define SERCOM_USART_INT_SYNCBUSY_LENGTH_Pos  _UINT32_(4)                                          /* (SERCOM_USART_INT_SYNCBUSY) LENGTH Synchronization Busy Position */
1717 #define SERCOM_USART_INT_SYNCBUSY_LENGTH_Msk  (_UINT32_(0x1) << SERCOM_USART_INT_SYNCBUSY_LENGTH_Pos) /* (SERCOM_USART_INT_SYNCBUSY) LENGTH Synchronization Busy Mask */
1718 #define SERCOM_USART_INT_SYNCBUSY_LENGTH(value) (SERCOM_USART_INT_SYNCBUSY_LENGTH_Msk & (_UINT32_(value) << SERCOM_USART_INT_SYNCBUSY_LENGTH_Pos)) /* Assigment of value for LENGTH in the SERCOM_USART_INT_SYNCBUSY register */
1719 #define SERCOM_USART_INT_SYNCBUSY_Msk         _UINT32_(0x0000001F)                                 /* (SERCOM_USART_INT_SYNCBUSY) Register Mask  */
1720 
1721 
1722 /* -------- SERCOM_USART_EXT_RXERRCNT : (SERCOM Offset: 0x20) ( R/ 8) USART_EXT Receive Error Count -------- */
1723 #define SERCOM_USART_EXT_RXERRCNT_RESETVALUE  _UINT8_(0x00)                                        /*  (SERCOM_USART_EXT_RXERRCNT) USART_EXT Receive Error Count  Reset Value */
1724 
1725 #define SERCOM_USART_EXT_RXERRCNT_RXERRCNT_Pos _UINT8_(0)                                           /* (SERCOM_USART_EXT_RXERRCNT) Receive Error Count Position */
1726 #define SERCOM_USART_EXT_RXERRCNT_RXERRCNT_Msk (_UINT8_(0xFF) << SERCOM_USART_EXT_RXERRCNT_RXERRCNT_Pos) /* (SERCOM_USART_EXT_RXERRCNT) Receive Error Count Mask */
1727 #define SERCOM_USART_EXT_RXERRCNT_RXERRCNT(value) (SERCOM_USART_EXT_RXERRCNT_RXERRCNT_Msk & (_UINT8_(value) << SERCOM_USART_EXT_RXERRCNT_RXERRCNT_Pos)) /* Assigment of value for RXERRCNT in the SERCOM_USART_EXT_RXERRCNT register */
1728 #define SERCOM_USART_EXT_RXERRCNT_Msk         _UINT8_(0xFF)                                        /* (SERCOM_USART_EXT_RXERRCNT) Register Mask  */
1729 
1730 
1731 /* -------- SERCOM_USART_INT_RXERRCNT : (SERCOM Offset: 0x20) ( R/ 8) USART_INT Receive Error Count -------- */
1732 #define SERCOM_USART_INT_RXERRCNT_RESETVALUE  _UINT8_(0x00)                                        /*  (SERCOM_USART_INT_RXERRCNT) USART_INT Receive Error Count  Reset Value */
1733 
1734 #define SERCOM_USART_INT_RXERRCNT_RXERRCNT_Pos _UINT8_(0)                                           /* (SERCOM_USART_INT_RXERRCNT) Receive Error Count Position */
1735 #define SERCOM_USART_INT_RXERRCNT_RXERRCNT_Msk (_UINT8_(0xFF) << SERCOM_USART_INT_RXERRCNT_RXERRCNT_Pos) /* (SERCOM_USART_INT_RXERRCNT) Receive Error Count Mask */
1736 #define SERCOM_USART_INT_RXERRCNT_RXERRCNT(value) (SERCOM_USART_INT_RXERRCNT_RXERRCNT_Msk & (_UINT8_(value) << SERCOM_USART_INT_RXERRCNT_RXERRCNT_Pos)) /* Assigment of value for RXERRCNT in the SERCOM_USART_INT_RXERRCNT register */
1737 #define SERCOM_USART_INT_RXERRCNT_Msk         _UINT8_(0xFF)                                        /* (SERCOM_USART_INT_RXERRCNT) Register Mask  */
1738 
1739 
1740 /* -------- SERCOM_I2CS_LENGTH : (SERCOM Offset: 0x22) (R/W 16) I2CS Length -------- */
1741 #define SERCOM_I2CS_LENGTH_RESETVALUE         _UINT16_(0x00)                                       /*  (SERCOM_I2CS_LENGTH) I2CS Length  Reset Value */
1742 
1743 #define SERCOM_I2CS_LENGTH_LEN_Pos            _UINT16_(0)                                          /* (SERCOM_I2CS_LENGTH) Data Length Position */
1744 #define SERCOM_I2CS_LENGTH_LEN_Msk            (_UINT16_(0xFF) << SERCOM_I2CS_LENGTH_LEN_Pos)       /* (SERCOM_I2CS_LENGTH) Data Length Mask */
1745 #define SERCOM_I2CS_LENGTH_LEN(value)         (SERCOM_I2CS_LENGTH_LEN_Msk & (_UINT16_(value) << SERCOM_I2CS_LENGTH_LEN_Pos)) /* Assigment of value for LEN in the SERCOM_I2CS_LENGTH register */
1746 #define SERCOM_I2CS_LENGTH_LENEN_Pos          _UINT16_(8)                                          /* (SERCOM_I2CS_LENGTH) Data Length Enable Position */
1747 #define SERCOM_I2CS_LENGTH_LENEN_Msk          (_UINT16_(0x1) << SERCOM_I2CS_LENGTH_LENEN_Pos)      /* (SERCOM_I2CS_LENGTH) Data Length Enable Mask */
1748 #define SERCOM_I2CS_LENGTH_LENEN(value)       (SERCOM_I2CS_LENGTH_LENEN_Msk & (_UINT16_(value) << SERCOM_I2CS_LENGTH_LENEN_Pos)) /* Assigment of value for LENEN in the SERCOM_I2CS_LENGTH register */
1749 #define SERCOM_I2CS_LENGTH_Msk                _UINT16_(0x01FF)                                     /* (SERCOM_I2CS_LENGTH) Register Mask  */
1750 
1751 
1752 /* -------- SERCOM_SPIM_LENGTH : (SERCOM Offset: 0x22) (R/W 16) SPIM Length -------- */
1753 #define SERCOM_SPIM_LENGTH_RESETVALUE         _UINT16_(0x00)                                       /*  (SERCOM_SPIM_LENGTH) SPIM Length  Reset Value */
1754 
1755 #define SERCOM_SPIM_LENGTH_LEN_Pos            _UINT16_(0)                                          /* (SERCOM_SPIM_LENGTH) Data Length Position */
1756 #define SERCOM_SPIM_LENGTH_LEN_Msk            (_UINT16_(0xFF) << SERCOM_SPIM_LENGTH_LEN_Pos)       /* (SERCOM_SPIM_LENGTH) Data Length Mask */
1757 #define SERCOM_SPIM_LENGTH_LEN(value)         (SERCOM_SPIM_LENGTH_LEN_Msk & (_UINT16_(value) << SERCOM_SPIM_LENGTH_LEN_Pos)) /* Assigment of value for LEN in the SERCOM_SPIM_LENGTH register */
1758 #define SERCOM_SPIM_LENGTH_LENEN_Pos          _UINT16_(8)                                          /* (SERCOM_SPIM_LENGTH) Data Length Enable Position */
1759 #define SERCOM_SPIM_LENGTH_LENEN_Msk          (_UINT16_(0x1) << SERCOM_SPIM_LENGTH_LENEN_Pos)      /* (SERCOM_SPIM_LENGTH) Data Length Enable Mask */
1760 #define SERCOM_SPIM_LENGTH_LENEN(value)       (SERCOM_SPIM_LENGTH_LENEN_Msk & (_UINT16_(value) << SERCOM_SPIM_LENGTH_LENEN_Pos)) /* Assigment of value for LENEN in the SERCOM_SPIM_LENGTH register */
1761 #define SERCOM_SPIM_LENGTH_Msk                _UINT16_(0x01FF)                                     /* (SERCOM_SPIM_LENGTH) Register Mask  */
1762 
1763 
1764 /* -------- SERCOM_SPIS_LENGTH : (SERCOM Offset: 0x22) (R/W 16) SPIS Length -------- */
1765 #define SERCOM_SPIS_LENGTH_RESETVALUE         _UINT16_(0x00)                                       /*  (SERCOM_SPIS_LENGTH) SPIS Length  Reset Value */
1766 
1767 #define SERCOM_SPIS_LENGTH_LEN_Pos            _UINT16_(0)                                          /* (SERCOM_SPIS_LENGTH) Data Length Position */
1768 #define SERCOM_SPIS_LENGTH_LEN_Msk            (_UINT16_(0xFF) << SERCOM_SPIS_LENGTH_LEN_Pos)       /* (SERCOM_SPIS_LENGTH) Data Length Mask */
1769 #define SERCOM_SPIS_LENGTH_LEN(value)         (SERCOM_SPIS_LENGTH_LEN_Msk & (_UINT16_(value) << SERCOM_SPIS_LENGTH_LEN_Pos)) /* Assigment of value for LEN in the SERCOM_SPIS_LENGTH register */
1770 #define SERCOM_SPIS_LENGTH_LENEN_Pos          _UINT16_(8)                                          /* (SERCOM_SPIS_LENGTH) Data Length Enable Position */
1771 #define SERCOM_SPIS_LENGTH_LENEN_Msk          (_UINT16_(0x1) << SERCOM_SPIS_LENGTH_LENEN_Pos)      /* (SERCOM_SPIS_LENGTH) Data Length Enable Mask */
1772 #define SERCOM_SPIS_LENGTH_LENEN(value)       (SERCOM_SPIS_LENGTH_LENEN_Msk & (_UINT16_(value) << SERCOM_SPIS_LENGTH_LENEN_Pos)) /* Assigment of value for LENEN in the SERCOM_SPIS_LENGTH register */
1773 #define SERCOM_SPIS_LENGTH_Msk                _UINT16_(0x01FF)                                     /* (SERCOM_SPIS_LENGTH) Register Mask  */
1774 
1775 
1776 /* -------- SERCOM_USART_EXT_LENGTH : (SERCOM Offset: 0x22) (R/W 16) USART_EXT Length -------- */
1777 #define SERCOM_USART_EXT_LENGTH_RESETVALUE    _UINT16_(0x00)                                       /*  (SERCOM_USART_EXT_LENGTH) USART_EXT Length  Reset Value */
1778 
1779 #define SERCOM_USART_EXT_LENGTH_LEN_Pos       _UINT16_(0)                                          /* (SERCOM_USART_EXT_LENGTH) Data Length Position */
1780 #define SERCOM_USART_EXT_LENGTH_LEN_Msk       (_UINT16_(0xFF) << SERCOM_USART_EXT_LENGTH_LEN_Pos)  /* (SERCOM_USART_EXT_LENGTH) Data Length Mask */
1781 #define SERCOM_USART_EXT_LENGTH_LEN(value)    (SERCOM_USART_EXT_LENGTH_LEN_Msk & (_UINT16_(value) << SERCOM_USART_EXT_LENGTH_LEN_Pos)) /* Assigment of value for LEN in the SERCOM_USART_EXT_LENGTH register */
1782 #define SERCOM_USART_EXT_LENGTH_LENEN_Pos     _UINT16_(8)                                          /* (SERCOM_USART_EXT_LENGTH) Data Length Enable Position */
1783 #define SERCOM_USART_EXT_LENGTH_LENEN_Msk     (_UINT16_(0x3) << SERCOM_USART_EXT_LENGTH_LENEN_Pos) /* (SERCOM_USART_EXT_LENGTH) Data Length Enable Mask */
1784 #define SERCOM_USART_EXT_LENGTH_LENEN(value)  (SERCOM_USART_EXT_LENGTH_LENEN_Msk & (_UINT16_(value) << SERCOM_USART_EXT_LENGTH_LENEN_Pos)) /* Assigment of value for LENEN in the SERCOM_USART_EXT_LENGTH register */
1785 #define SERCOM_USART_EXT_LENGTH_Msk           _UINT16_(0x03FF)                                     /* (SERCOM_USART_EXT_LENGTH) Register Mask  */
1786 
1787 
1788 /* -------- SERCOM_USART_INT_LENGTH : (SERCOM Offset: 0x22) (R/W 16) USART_INT Length -------- */
1789 #define SERCOM_USART_INT_LENGTH_RESETVALUE    _UINT16_(0x00)                                       /*  (SERCOM_USART_INT_LENGTH) USART_INT Length  Reset Value */
1790 
1791 #define SERCOM_USART_INT_LENGTH_LEN_Pos       _UINT16_(0)                                          /* (SERCOM_USART_INT_LENGTH) Data Length Position */
1792 #define SERCOM_USART_INT_LENGTH_LEN_Msk       (_UINT16_(0xFF) << SERCOM_USART_INT_LENGTH_LEN_Pos)  /* (SERCOM_USART_INT_LENGTH) Data Length Mask */
1793 #define SERCOM_USART_INT_LENGTH_LEN(value)    (SERCOM_USART_INT_LENGTH_LEN_Msk & (_UINT16_(value) << SERCOM_USART_INT_LENGTH_LEN_Pos)) /* Assigment of value for LEN in the SERCOM_USART_INT_LENGTH register */
1794 #define SERCOM_USART_INT_LENGTH_LENEN_Pos     _UINT16_(8)                                          /* (SERCOM_USART_INT_LENGTH) Data Length Enable Position */
1795 #define SERCOM_USART_INT_LENGTH_LENEN_Msk     (_UINT16_(0x3) << SERCOM_USART_INT_LENGTH_LENEN_Pos) /* (SERCOM_USART_INT_LENGTH) Data Length Enable Mask */
1796 #define SERCOM_USART_INT_LENGTH_LENEN(value)  (SERCOM_USART_INT_LENGTH_LENEN_Msk & (_UINT16_(value) << SERCOM_USART_INT_LENGTH_LENEN_Pos)) /* Assigment of value for LENEN in the SERCOM_USART_INT_LENGTH register */
1797 #define SERCOM_USART_INT_LENGTH_Msk           _UINT16_(0x03FF)                                     /* (SERCOM_USART_INT_LENGTH) Register Mask  */
1798 
1799 
1800 /* -------- SERCOM_I2CM_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CM Address -------- */
1801 #define SERCOM_I2CM_ADDR_RESETVALUE           _UINT32_(0x00)                                       /*  (SERCOM_I2CM_ADDR) I2CM Address  Reset Value */
1802 
1803 #define SERCOM_I2CM_ADDR_ADDR_Pos             _UINT32_(0)                                          /* (SERCOM_I2CM_ADDR) Address Value Position */
1804 #define SERCOM_I2CM_ADDR_ADDR_Msk             (_UINT32_(0x7FF) << SERCOM_I2CM_ADDR_ADDR_Pos)       /* (SERCOM_I2CM_ADDR) Address Value Mask */
1805 #define SERCOM_I2CM_ADDR_ADDR(value)          (SERCOM_I2CM_ADDR_ADDR_Msk & (_UINT32_(value) << SERCOM_I2CM_ADDR_ADDR_Pos)) /* Assigment of value for ADDR in the SERCOM_I2CM_ADDR register */
1806 #define SERCOM_I2CM_ADDR_LENEN_Pos            _UINT32_(13)                                         /* (SERCOM_I2CM_ADDR) Length Enable Position */
1807 #define SERCOM_I2CM_ADDR_LENEN_Msk            (_UINT32_(0x1) << SERCOM_I2CM_ADDR_LENEN_Pos)        /* (SERCOM_I2CM_ADDR) Length Enable Mask */
1808 #define SERCOM_I2CM_ADDR_LENEN(value)         (SERCOM_I2CM_ADDR_LENEN_Msk & (_UINT32_(value) << SERCOM_I2CM_ADDR_LENEN_Pos)) /* Assigment of value for LENEN in the SERCOM_I2CM_ADDR register */
1809 #define SERCOM_I2CM_ADDR_HS_Pos               _UINT32_(14)                                         /* (SERCOM_I2CM_ADDR) High Speed Mode Position */
1810 #define SERCOM_I2CM_ADDR_HS_Msk               (_UINT32_(0x1) << SERCOM_I2CM_ADDR_HS_Pos)           /* (SERCOM_I2CM_ADDR) High Speed Mode Mask */
1811 #define SERCOM_I2CM_ADDR_HS(value)            (SERCOM_I2CM_ADDR_HS_Msk & (_UINT32_(value) << SERCOM_I2CM_ADDR_HS_Pos)) /* Assigment of value for HS in the SERCOM_I2CM_ADDR register */
1812 #define SERCOM_I2CM_ADDR_TENBITEN_Pos         _UINT32_(15)                                         /* (SERCOM_I2CM_ADDR) Ten Bit Addressing Enable Position */
1813 #define SERCOM_I2CM_ADDR_TENBITEN_Msk         (_UINT32_(0x1) << SERCOM_I2CM_ADDR_TENBITEN_Pos)     /* (SERCOM_I2CM_ADDR) Ten Bit Addressing Enable Mask */
1814 #define SERCOM_I2CM_ADDR_TENBITEN(value)      (SERCOM_I2CM_ADDR_TENBITEN_Msk & (_UINT32_(value) << SERCOM_I2CM_ADDR_TENBITEN_Pos)) /* Assigment of value for TENBITEN in the SERCOM_I2CM_ADDR register */
1815 #define SERCOM_I2CM_ADDR_LEN_Pos              _UINT32_(16)                                         /* (SERCOM_I2CM_ADDR) Length Position */
1816 #define SERCOM_I2CM_ADDR_LEN_Msk              (_UINT32_(0xFF) << SERCOM_I2CM_ADDR_LEN_Pos)         /* (SERCOM_I2CM_ADDR) Length Mask */
1817 #define SERCOM_I2CM_ADDR_LEN(value)           (SERCOM_I2CM_ADDR_LEN_Msk & (_UINT32_(value) << SERCOM_I2CM_ADDR_LEN_Pos)) /* Assigment of value for LEN in the SERCOM_I2CM_ADDR register */
1818 #define SERCOM_I2CM_ADDR_Msk                  _UINT32_(0x00FFE7FF)                                 /* (SERCOM_I2CM_ADDR) Register Mask  */
1819 
1820 
1821 /* -------- SERCOM_I2CS_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CS Address -------- */
1822 #define SERCOM_I2CS_ADDR_RESETVALUE           _UINT32_(0x00)                                       /*  (SERCOM_I2CS_ADDR) I2CS Address  Reset Value */
1823 
1824 #define SERCOM_I2CS_ADDR_GENCEN_Pos           _UINT32_(0)                                          /* (SERCOM_I2CS_ADDR) General Call Address Enable Position */
1825 #define SERCOM_I2CS_ADDR_GENCEN_Msk           (_UINT32_(0x1) << SERCOM_I2CS_ADDR_GENCEN_Pos)       /* (SERCOM_I2CS_ADDR) General Call Address Enable Mask */
1826 #define SERCOM_I2CS_ADDR_GENCEN(value)        (SERCOM_I2CS_ADDR_GENCEN_Msk & (_UINT32_(value) << SERCOM_I2CS_ADDR_GENCEN_Pos)) /* Assigment of value for GENCEN in the SERCOM_I2CS_ADDR register */
1827 #define SERCOM_I2CS_ADDR_ADDR_Pos             _UINT32_(1)                                          /* (SERCOM_I2CS_ADDR) Address Value Position */
1828 #define SERCOM_I2CS_ADDR_ADDR_Msk             (_UINT32_(0x3FF) << SERCOM_I2CS_ADDR_ADDR_Pos)       /* (SERCOM_I2CS_ADDR) Address Value Mask */
1829 #define SERCOM_I2CS_ADDR_ADDR(value)          (SERCOM_I2CS_ADDR_ADDR_Msk & (_UINT32_(value) << SERCOM_I2CS_ADDR_ADDR_Pos)) /* Assigment of value for ADDR in the SERCOM_I2CS_ADDR register */
1830 #define SERCOM_I2CS_ADDR_TENBITEN_Pos         _UINT32_(15)                                         /* (SERCOM_I2CS_ADDR) Ten Bit Addressing Enable Position */
1831 #define SERCOM_I2CS_ADDR_TENBITEN_Msk         (_UINT32_(0x1) << SERCOM_I2CS_ADDR_TENBITEN_Pos)     /* (SERCOM_I2CS_ADDR) Ten Bit Addressing Enable Mask */
1832 #define SERCOM_I2CS_ADDR_TENBITEN(value)      (SERCOM_I2CS_ADDR_TENBITEN_Msk & (_UINT32_(value) << SERCOM_I2CS_ADDR_TENBITEN_Pos)) /* Assigment of value for TENBITEN in the SERCOM_I2CS_ADDR register */
1833 #define SERCOM_I2CS_ADDR_ADDRMASK_Pos         _UINT32_(17)                                         /* (SERCOM_I2CS_ADDR) Address Mask Position */
1834 #define SERCOM_I2CS_ADDR_ADDRMASK_Msk         (_UINT32_(0x3FF) << SERCOM_I2CS_ADDR_ADDRMASK_Pos)   /* (SERCOM_I2CS_ADDR) Address Mask Mask */
1835 #define SERCOM_I2CS_ADDR_ADDRMASK(value)      (SERCOM_I2CS_ADDR_ADDRMASK_Msk & (_UINT32_(value) << SERCOM_I2CS_ADDR_ADDRMASK_Pos)) /* Assigment of value for ADDRMASK in the SERCOM_I2CS_ADDR register */
1836 #define SERCOM_I2CS_ADDR_Msk                  _UINT32_(0x07FE87FF)                                 /* (SERCOM_I2CS_ADDR) Register Mask  */
1837 
1838 
1839 /* -------- SERCOM_SPIM_ADDR : (SERCOM Offset: 0x24) (R/W 32) SPIM Address -------- */
1840 #define SERCOM_SPIM_ADDR_RESETVALUE           _UINT32_(0x00)                                       /*  (SERCOM_SPIM_ADDR) SPIM Address  Reset Value */
1841 
1842 #define SERCOM_SPIM_ADDR_ADDR_Pos             _UINT32_(0)                                          /* (SERCOM_SPIM_ADDR) Address Value Position */
1843 #define SERCOM_SPIM_ADDR_ADDR_Msk             (_UINT32_(0xFF) << SERCOM_SPIM_ADDR_ADDR_Pos)        /* (SERCOM_SPIM_ADDR) Address Value Mask */
1844 #define SERCOM_SPIM_ADDR_ADDR(value)          (SERCOM_SPIM_ADDR_ADDR_Msk & (_UINT32_(value) << SERCOM_SPIM_ADDR_ADDR_Pos)) /* Assigment of value for ADDR in the SERCOM_SPIM_ADDR register */
1845 #define SERCOM_SPIM_ADDR_ADDRMASK_Pos         _UINT32_(16)                                         /* (SERCOM_SPIM_ADDR) Address Mask Position */
1846 #define SERCOM_SPIM_ADDR_ADDRMASK_Msk         (_UINT32_(0xFF) << SERCOM_SPIM_ADDR_ADDRMASK_Pos)    /* (SERCOM_SPIM_ADDR) Address Mask Mask */
1847 #define SERCOM_SPIM_ADDR_ADDRMASK(value)      (SERCOM_SPIM_ADDR_ADDRMASK_Msk & (_UINT32_(value) << SERCOM_SPIM_ADDR_ADDRMASK_Pos)) /* Assigment of value for ADDRMASK in the SERCOM_SPIM_ADDR register */
1848 #define SERCOM_SPIM_ADDR_Msk                  _UINT32_(0x00FF00FF)                                 /* (SERCOM_SPIM_ADDR) Register Mask  */
1849 
1850 
1851 /* -------- SERCOM_SPIS_ADDR : (SERCOM Offset: 0x24) (R/W 32) SPIS Address -------- */
1852 #define SERCOM_SPIS_ADDR_RESETVALUE           _UINT32_(0x00)                                       /*  (SERCOM_SPIS_ADDR) SPIS Address  Reset Value */
1853 
1854 #define SERCOM_SPIS_ADDR_ADDR_Pos             _UINT32_(0)                                          /* (SERCOM_SPIS_ADDR) Address Value Position */
1855 #define SERCOM_SPIS_ADDR_ADDR_Msk             (_UINT32_(0xFF) << SERCOM_SPIS_ADDR_ADDR_Pos)        /* (SERCOM_SPIS_ADDR) Address Value Mask */
1856 #define SERCOM_SPIS_ADDR_ADDR(value)          (SERCOM_SPIS_ADDR_ADDR_Msk & (_UINT32_(value) << SERCOM_SPIS_ADDR_ADDR_Pos)) /* Assigment of value for ADDR in the SERCOM_SPIS_ADDR register */
1857 #define SERCOM_SPIS_ADDR_ADDRMASK_Pos         _UINT32_(16)                                         /* (SERCOM_SPIS_ADDR) Address Mask Position */
1858 #define SERCOM_SPIS_ADDR_ADDRMASK_Msk         (_UINT32_(0xFF) << SERCOM_SPIS_ADDR_ADDRMASK_Pos)    /* (SERCOM_SPIS_ADDR) Address Mask Mask */
1859 #define SERCOM_SPIS_ADDR_ADDRMASK(value)      (SERCOM_SPIS_ADDR_ADDRMASK_Msk & (_UINT32_(value) << SERCOM_SPIS_ADDR_ADDRMASK_Pos)) /* Assigment of value for ADDRMASK in the SERCOM_SPIS_ADDR register */
1860 #define SERCOM_SPIS_ADDR_Msk                  _UINT32_(0x00FF00FF)                                 /* (SERCOM_SPIS_ADDR) Register Mask  */
1861 
1862 
1863 /* -------- SERCOM_I2CM_DATA : (SERCOM Offset: 0x28) (R/W 32) I2CM Data -------- */
1864 #define SERCOM_I2CM_DATA_RESETVALUE           _UINT32_(0x00)                                       /*  (SERCOM_I2CM_DATA) I2CM Data  Reset Value */
1865 
1866 #define SERCOM_I2CM_DATA_DATA_Pos             _UINT32_(0)                                          /* (SERCOM_I2CM_DATA) Data Value Position */
1867 #define SERCOM_I2CM_DATA_DATA_Msk             (_UINT32_(0xFFFFFFFF) << SERCOM_I2CM_DATA_DATA_Pos)  /* (SERCOM_I2CM_DATA) Data Value Mask */
1868 #define SERCOM_I2CM_DATA_DATA(value)          (SERCOM_I2CM_DATA_DATA_Msk & (_UINT32_(value) << SERCOM_I2CM_DATA_DATA_Pos)) /* Assigment of value for DATA in the SERCOM_I2CM_DATA register */
1869 #define SERCOM_I2CM_DATA_Msk                  _UINT32_(0xFFFFFFFF)                                 /* (SERCOM_I2CM_DATA) Register Mask  */
1870 
1871 
1872 /* -------- SERCOM_I2CS_DATA : (SERCOM Offset: 0x28) (R/W 32) I2CS Data -------- */
1873 #define SERCOM_I2CS_DATA_RESETVALUE           _UINT32_(0x00)                                       /*  (SERCOM_I2CS_DATA) I2CS Data  Reset Value */
1874 
1875 #define SERCOM_I2CS_DATA_DATA_Pos             _UINT32_(0)                                          /* (SERCOM_I2CS_DATA) Data Value Position */
1876 #define SERCOM_I2CS_DATA_DATA_Msk             (_UINT32_(0xFFFFFFFF) << SERCOM_I2CS_DATA_DATA_Pos)  /* (SERCOM_I2CS_DATA) Data Value Mask */
1877 #define SERCOM_I2CS_DATA_DATA(value)          (SERCOM_I2CS_DATA_DATA_Msk & (_UINT32_(value) << SERCOM_I2CS_DATA_DATA_Pos)) /* Assigment of value for DATA in the SERCOM_I2CS_DATA register */
1878 #define SERCOM_I2CS_DATA_Msk                  _UINT32_(0xFFFFFFFF)                                 /* (SERCOM_I2CS_DATA) Register Mask  */
1879 
1880 
1881 /* -------- SERCOM_SPIM_DATA : (SERCOM Offset: 0x28) (R/W 32) SPIM Data -------- */
1882 #define SERCOM_SPIM_DATA_RESETVALUE           _UINT32_(0x00)                                       /*  (SERCOM_SPIM_DATA) SPIM Data  Reset Value */
1883 
1884 #define SERCOM_SPIM_DATA_DATA_Pos             _UINT32_(0)                                          /* (SERCOM_SPIM_DATA) Data Value Position */
1885 #define SERCOM_SPIM_DATA_DATA_Msk             (_UINT32_(0xFFFFFFFF) << SERCOM_SPIM_DATA_DATA_Pos)  /* (SERCOM_SPIM_DATA) Data Value Mask */
1886 #define SERCOM_SPIM_DATA_DATA(value)          (SERCOM_SPIM_DATA_DATA_Msk & (_UINT32_(value) << SERCOM_SPIM_DATA_DATA_Pos)) /* Assigment of value for DATA in the SERCOM_SPIM_DATA register */
1887 #define SERCOM_SPIM_DATA_Msk                  _UINT32_(0xFFFFFFFF)                                 /* (SERCOM_SPIM_DATA) Register Mask  */
1888 
1889 
1890 /* -------- SERCOM_SPIS_DATA : (SERCOM Offset: 0x28) (R/W 32) SPIS Data -------- */
1891 #define SERCOM_SPIS_DATA_RESETVALUE           _UINT32_(0x00)                                       /*  (SERCOM_SPIS_DATA) SPIS Data  Reset Value */
1892 
1893 #define SERCOM_SPIS_DATA_DATA_Pos             _UINT32_(0)                                          /* (SERCOM_SPIS_DATA) Data Value Position */
1894 #define SERCOM_SPIS_DATA_DATA_Msk             (_UINT32_(0xFFFFFFFF) << SERCOM_SPIS_DATA_DATA_Pos)  /* (SERCOM_SPIS_DATA) Data Value Mask */
1895 #define SERCOM_SPIS_DATA_DATA(value)          (SERCOM_SPIS_DATA_DATA_Msk & (_UINT32_(value) << SERCOM_SPIS_DATA_DATA_Pos)) /* Assigment of value for DATA in the SERCOM_SPIS_DATA register */
1896 #define SERCOM_SPIS_DATA_Msk                  _UINT32_(0xFFFFFFFF)                                 /* (SERCOM_SPIS_DATA) Register Mask  */
1897 
1898 
1899 /* -------- SERCOM_USART_EXT_DATA : (SERCOM Offset: 0x28) (R/W 32) USART_EXT Data -------- */
1900 #define SERCOM_USART_EXT_DATA_RESETVALUE      _UINT32_(0x00)                                       /*  (SERCOM_USART_EXT_DATA) USART_EXT Data  Reset Value */
1901 
1902 #define SERCOM_USART_EXT_DATA_DATA_Pos        _UINT32_(0)                                          /* (SERCOM_USART_EXT_DATA) Data Value Position */
1903 #define SERCOM_USART_EXT_DATA_DATA_Msk        (_UINT32_(0xFFFFFFFF) << SERCOM_USART_EXT_DATA_DATA_Pos) /* (SERCOM_USART_EXT_DATA) Data Value Mask */
1904 #define SERCOM_USART_EXT_DATA_DATA(value)     (SERCOM_USART_EXT_DATA_DATA_Msk & (_UINT32_(value) << SERCOM_USART_EXT_DATA_DATA_Pos)) /* Assigment of value for DATA in the SERCOM_USART_EXT_DATA register */
1905 #define SERCOM_USART_EXT_DATA_Msk             _UINT32_(0xFFFFFFFF)                                 /* (SERCOM_USART_EXT_DATA) Register Mask  */
1906 
1907 
1908 /* -------- SERCOM_USART_INT_DATA : (SERCOM Offset: 0x28) (R/W 32) USART_INT Data -------- */
1909 #define SERCOM_USART_INT_DATA_RESETVALUE      _UINT32_(0x00)                                       /*  (SERCOM_USART_INT_DATA) USART_INT Data  Reset Value */
1910 
1911 #define SERCOM_USART_INT_DATA_DATA_Pos        _UINT32_(0)                                          /* (SERCOM_USART_INT_DATA) Data Value Position */
1912 #define SERCOM_USART_INT_DATA_DATA_Msk        (_UINT32_(0xFFFFFFFF) << SERCOM_USART_INT_DATA_DATA_Pos) /* (SERCOM_USART_INT_DATA) Data Value Mask */
1913 #define SERCOM_USART_INT_DATA_DATA(value)     (SERCOM_USART_INT_DATA_DATA_Msk & (_UINT32_(value) << SERCOM_USART_INT_DATA_DATA_Pos)) /* Assigment of value for DATA in the SERCOM_USART_INT_DATA register */
1914 #define SERCOM_USART_INT_DATA_Msk             _UINT32_(0xFFFFFFFF)                                 /* (SERCOM_USART_INT_DATA) Register Mask  */
1915 
1916 
1917 /* -------- SERCOM_I2CM_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) I2CM Debug Control -------- */
1918 #define SERCOM_I2CM_DBGCTRL_RESETVALUE        _UINT8_(0x00)                                        /*  (SERCOM_I2CM_DBGCTRL) I2CM Debug Control  Reset Value */
1919 
1920 #define SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos       _UINT8_(0)                                           /* (SERCOM_I2CM_DBGCTRL) Debug Mode Position */
1921 #define SERCOM_I2CM_DBGCTRL_DBGSTOP_Msk       (_UINT8_(0x1) << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos)    /* (SERCOM_I2CM_DBGCTRL) Debug Mode Mask */
1922 #define SERCOM_I2CM_DBGCTRL_DBGSTOP(value)    (SERCOM_I2CM_DBGCTRL_DBGSTOP_Msk & (_UINT8_(value) << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos)) /* Assigment of value for DBGSTOP in the SERCOM_I2CM_DBGCTRL register */
1923 #define SERCOM_I2CM_DBGCTRL_Msk               _UINT8_(0x01)                                        /* (SERCOM_I2CM_DBGCTRL) Register Mask  */
1924 
1925 
1926 /* -------- SERCOM_SPIM_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) SPIM Debug Control -------- */
1927 #define SERCOM_SPIM_DBGCTRL_RESETVALUE        _UINT8_(0x00)                                        /*  (SERCOM_SPIM_DBGCTRL) SPIM Debug Control  Reset Value */
1928 
1929 #define SERCOM_SPIM_DBGCTRL_DBGSTOP_Pos       _UINT8_(0)                                           /* (SERCOM_SPIM_DBGCTRL) Debug Mode Position */
1930 #define SERCOM_SPIM_DBGCTRL_DBGSTOP_Msk       (_UINT8_(0x1) << SERCOM_SPIM_DBGCTRL_DBGSTOP_Pos)    /* (SERCOM_SPIM_DBGCTRL) Debug Mode Mask */
1931 #define SERCOM_SPIM_DBGCTRL_DBGSTOP(value)    (SERCOM_SPIM_DBGCTRL_DBGSTOP_Msk & (_UINT8_(value) << SERCOM_SPIM_DBGCTRL_DBGSTOP_Pos)) /* Assigment of value for DBGSTOP in the SERCOM_SPIM_DBGCTRL register */
1932 #define SERCOM_SPIM_DBGCTRL_Msk               _UINT8_(0x01)                                        /* (SERCOM_SPIM_DBGCTRL) Register Mask  */
1933 
1934 
1935 /* -------- SERCOM_SPIS_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) SPIS Debug Control -------- */
1936 #define SERCOM_SPIS_DBGCTRL_RESETVALUE        _UINT8_(0x00)                                        /*  (SERCOM_SPIS_DBGCTRL) SPIS Debug Control  Reset Value */
1937 
1938 #define SERCOM_SPIS_DBGCTRL_DBGSTOP_Pos       _UINT8_(0)                                           /* (SERCOM_SPIS_DBGCTRL) Debug Mode Position */
1939 #define SERCOM_SPIS_DBGCTRL_DBGSTOP_Msk       (_UINT8_(0x1) << SERCOM_SPIS_DBGCTRL_DBGSTOP_Pos)    /* (SERCOM_SPIS_DBGCTRL) Debug Mode Mask */
1940 #define SERCOM_SPIS_DBGCTRL_DBGSTOP(value)    (SERCOM_SPIS_DBGCTRL_DBGSTOP_Msk & (_UINT8_(value) << SERCOM_SPIS_DBGCTRL_DBGSTOP_Pos)) /* Assigment of value for DBGSTOP in the SERCOM_SPIS_DBGCTRL register */
1941 #define SERCOM_SPIS_DBGCTRL_Msk               _UINT8_(0x01)                                        /* (SERCOM_SPIS_DBGCTRL) Register Mask  */
1942 
1943 
1944 /* -------- SERCOM_USART_EXT_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) USART_EXT Debug Control -------- */
1945 #define SERCOM_USART_EXT_DBGCTRL_RESETVALUE   _UINT8_(0x00)                                        /*  (SERCOM_USART_EXT_DBGCTRL) USART_EXT Debug Control  Reset Value */
1946 
1947 #define SERCOM_USART_EXT_DBGCTRL_DBGSTOP_Pos  _UINT8_(0)                                           /* (SERCOM_USART_EXT_DBGCTRL) Debug Mode Position */
1948 #define SERCOM_USART_EXT_DBGCTRL_DBGSTOP_Msk  (_UINT8_(0x1) << SERCOM_USART_EXT_DBGCTRL_DBGSTOP_Pos) /* (SERCOM_USART_EXT_DBGCTRL) Debug Mode Mask */
1949 #define SERCOM_USART_EXT_DBGCTRL_DBGSTOP(value) (SERCOM_USART_EXT_DBGCTRL_DBGSTOP_Msk & (_UINT8_(value) << SERCOM_USART_EXT_DBGCTRL_DBGSTOP_Pos)) /* Assigment of value for DBGSTOP in the SERCOM_USART_EXT_DBGCTRL register */
1950 #define SERCOM_USART_EXT_DBGCTRL_Msk          _UINT8_(0x01)                                        /* (SERCOM_USART_EXT_DBGCTRL) Register Mask  */
1951 
1952 
1953 /* -------- SERCOM_USART_INT_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) USART_INT Debug Control -------- */
1954 #define SERCOM_USART_INT_DBGCTRL_RESETVALUE   _UINT8_(0x00)                                        /*  (SERCOM_USART_INT_DBGCTRL) USART_INT Debug Control  Reset Value */
1955 
1956 #define SERCOM_USART_INT_DBGCTRL_DBGSTOP_Pos  _UINT8_(0)                                           /* (SERCOM_USART_INT_DBGCTRL) Debug Mode Position */
1957 #define SERCOM_USART_INT_DBGCTRL_DBGSTOP_Msk  (_UINT8_(0x1) << SERCOM_USART_INT_DBGCTRL_DBGSTOP_Pos) /* (SERCOM_USART_INT_DBGCTRL) Debug Mode Mask */
1958 #define SERCOM_USART_INT_DBGCTRL_DBGSTOP(value) (SERCOM_USART_INT_DBGCTRL_DBGSTOP_Msk & (_UINT8_(value) << SERCOM_USART_INT_DBGCTRL_DBGSTOP_Pos)) /* Assigment of value for DBGSTOP in the SERCOM_USART_INT_DBGCTRL register */
1959 #define SERCOM_USART_INT_DBGCTRL_Msk          _UINT8_(0x01)                                        /* (SERCOM_USART_INT_DBGCTRL) Register Mask  */
1960 
1961 
1962 /** \brief SERCOM register offsets definitions */
1963 #define SERCOM_I2CM_CTRLA_REG_OFST     _UINT32_(0x00)      /* (SERCOM_I2CM_CTRLA) I2CM Control A Offset */
1964 #define SERCOM_I2CS_CTRLA_REG_OFST     _UINT32_(0x00)      /* (SERCOM_I2CS_CTRLA) I2CS Control A Offset */
1965 #define SERCOM_SPIM_CTRLA_REG_OFST     _UINT32_(0x00)      /* (SERCOM_SPIM_CTRLA) SPIM Control A Offset */
1966 #define SERCOM_SPIS_CTRLA_REG_OFST     _UINT32_(0x00)      /* (SERCOM_SPIS_CTRLA) SPIS Control A Offset */
1967 #define SERCOM_USART_EXT_CTRLA_REG_OFST _UINT32_(0x00)      /* (SERCOM_USART_EXT_CTRLA) USART_EXT Control A Offset */
1968 #define SERCOM_USART_INT_CTRLA_REG_OFST _UINT32_(0x00)      /* (SERCOM_USART_INT_CTRLA) USART_INT Control A Offset */
1969 #define SERCOM_I2CM_CTRLB_REG_OFST     _UINT32_(0x04)      /* (SERCOM_I2CM_CTRLB) I2CM Control B Offset */
1970 #define SERCOM_I2CS_CTRLB_REG_OFST     _UINT32_(0x04)      /* (SERCOM_I2CS_CTRLB) I2CS Control B Offset */
1971 #define SERCOM_SPIM_CTRLB_REG_OFST     _UINT32_(0x04)      /* (SERCOM_SPIM_CTRLB) SPIM Control B Offset */
1972 #define SERCOM_SPIS_CTRLB_REG_OFST     _UINT32_(0x04)      /* (SERCOM_SPIS_CTRLB) SPIS Control B Offset */
1973 #define SERCOM_USART_EXT_CTRLB_REG_OFST _UINT32_(0x04)      /* (SERCOM_USART_EXT_CTRLB) USART_EXT Control B Offset */
1974 #define SERCOM_USART_INT_CTRLB_REG_OFST _UINT32_(0x04)      /* (SERCOM_USART_INT_CTRLB) USART_INT Control B Offset */
1975 #define SERCOM_I2CM_CTRLC_REG_OFST     _UINT32_(0x08)      /* (SERCOM_I2CM_CTRLC) I2CM Control C Offset */
1976 #define SERCOM_I2CS_CTRLC_REG_OFST     _UINT32_(0x08)      /* (SERCOM_I2CS_CTRLC) I2CS Control C Offset */
1977 #define SERCOM_SPIM_CTRLC_REG_OFST     _UINT32_(0x08)      /* (SERCOM_SPIM_CTRLC) SPIM Control C Offset */
1978 #define SERCOM_SPIS_CTRLC_REG_OFST     _UINT32_(0x08)      /* (SERCOM_SPIS_CTRLC) SPIS Control C Offset */
1979 #define SERCOM_USART_EXT_CTRLC_REG_OFST _UINT32_(0x08)      /* (SERCOM_USART_EXT_CTRLC) USART_EXT Control C Offset */
1980 #define SERCOM_USART_INT_CTRLC_REG_OFST _UINT32_(0x08)      /* (SERCOM_USART_INT_CTRLC) USART_INT Control C Offset */
1981 #define SERCOM_I2CM_BAUD_REG_OFST      _UINT32_(0x0C)      /* (SERCOM_I2CM_BAUD) I2CM Baud Rate Offset */
1982 #define SERCOM_SPIM_BAUD_REG_OFST      _UINT32_(0x0C)      /* (SERCOM_SPIM_BAUD) SPIM Baud Rate Offset */
1983 #define SERCOM_SPIS_BAUD_REG_OFST      _UINT32_(0x0C)      /* (SERCOM_SPIS_BAUD) SPIS Baud Rate Offset */
1984 #define SERCOM_USART_EXT_BAUD_REG_OFST _UINT32_(0x0C)      /* (SERCOM_USART_EXT_BAUD) USART_EXT Baud Rate Offset */
1985 #define SERCOM_USART_INT_BAUD_REG_OFST _UINT32_(0x0C)      /* (SERCOM_USART_INT_BAUD) USART_INT Baud Rate Offset */
1986 #define SERCOM_USART_EXT_RXPL_REG_OFST _UINT32_(0x0E)      /* (SERCOM_USART_EXT_RXPL) USART_EXT Receive Pulse Length Offset */
1987 #define SERCOM_USART_INT_RXPL_REG_OFST _UINT32_(0x0E)      /* (SERCOM_USART_INT_RXPL) USART_INT Receive Pulse Length Offset */
1988 #define SERCOM_I2CM_INTENCLR_REG_OFST  _UINT32_(0x14)      /* (SERCOM_I2CM_INTENCLR) I2CM Interrupt Enable Clear Offset */
1989 #define SERCOM_I2CS_INTENCLR_REG_OFST  _UINT32_(0x14)      /* (SERCOM_I2CS_INTENCLR) I2CS Interrupt Enable Clear Offset */
1990 #define SERCOM_SPIM_INTENCLR_REG_OFST  _UINT32_(0x14)      /* (SERCOM_SPIM_INTENCLR) SPIM Interrupt Enable Clear Offset */
1991 #define SERCOM_SPIS_INTENCLR_REG_OFST  _UINT32_(0x14)      /* (SERCOM_SPIS_INTENCLR) SPIS Interrupt Enable Clear Offset */
1992 #define SERCOM_USART_EXT_INTENCLR_REG_OFST _UINT32_(0x14)      /* (SERCOM_USART_EXT_INTENCLR) USART_EXT Interrupt Enable Clear Offset */
1993 #define SERCOM_USART_INT_INTENCLR_REG_OFST _UINT32_(0x14)      /* (SERCOM_USART_INT_INTENCLR) USART_INT Interrupt Enable Clear Offset */
1994 #define SERCOM_I2CM_INTENSET_REG_OFST  _UINT32_(0x16)      /* (SERCOM_I2CM_INTENSET) I2CM Interrupt Enable Set Offset */
1995 #define SERCOM_I2CS_INTENSET_REG_OFST  _UINT32_(0x16)      /* (SERCOM_I2CS_INTENSET) I2CS Interrupt Enable Set Offset */
1996 #define SERCOM_SPIM_INTENSET_REG_OFST  _UINT32_(0x16)      /* (SERCOM_SPIM_INTENSET) SPIM Interrupt Enable Set Offset */
1997 #define SERCOM_SPIS_INTENSET_REG_OFST  _UINT32_(0x16)      /* (SERCOM_SPIS_INTENSET) SPIS Interrupt Enable Set Offset */
1998 #define SERCOM_USART_EXT_INTENSET_REG_OFST _UINT32_(0x16)      /* (SERCOM_USART_EXT_INTENSET) USART_EXT Interrupt Enable Set Offset */
1999 #define SERCOM_USART_INT_INTENSET_REG_OFST _UINT32_(0x16)      /* (SERCOM_USART_INT_INTENSET) USART_INT Interrupt Enable Set Offset */
2000 #define SERCOM_I2CM_INTFLAG_REG_OFST   _UINT32_(0x18)      /* (SERCOM_I2CM_INTFLAG) I2CM Interrupt Flag Status and Clear Offset */
2001 #define SERCOM_I2CS_INTFLAG_REG_OFST   _UINT32_(0x18)      /* (SERCOM_I2CS_INTFLAG) I2CS Interrupt Flag Status and Clear Offset */
2002 #define SERCOM_SPIM_INTFLAG_REG_OFST   _UINT32_(0x18)      /* (SERCOM_SPIM_INTFLAG) SPIM Interrupt Flag Status and Clear Offset */
2003 #define SERCOM_SPIS_INTFLAG_REG_OFST   _UINT32_(0x18)      /* (SERCOM_SPIS_INTFLAG) SPIS Interrupt Flag Status and Clear Offset */
2004 #define SERCOM_USART_EXT_INTFLAG_REG_OFST _UINT32_(0x18)      /* (SERCOM_USART_EXT_INTFLAG) USART_EXT Interrupt Flag Status and Clear Offset */
2005 #define SERCOM_USART_INT_INTFLAG_REG_OFST _UINT32_(0x18)      /* (SERCOM_USART_INT_INTFLAG) USART_INT Interrupt Flag Status and Clear Offset */
2006 #define SERCOM_I2CM_STATUS_REG_OFST    _UINT32_(0x1A)      /* (SERCOM_I2CM_STATUS) I2CM Status Offset */
2007 #define SERCOM_I2CS_STATUS_REG_OFST    _UINT32_(0x1A)      /* (SERCOM_I2CS_STATUS) I2CS Status Offset */
2008 #define SERCOM_SPIM_STATUS_REG_OFST    _UINT32_(0x1A)      /* (SERCOM_SPIM_STATUS) SPIM Status Offset */
2009 #define SERCOM_SPIS_STATUS_REG_OFST    _UINT32_(0x1A)      /* (SERCOM_SPIS_STATUS) SPIS Status Offset */
2010 #define SERCOM_USART_EXT_STATUS_REG_OFST _UINT32_(0x1A)      /* (SERCOM_USART_EXT_STATUS) USART_EXT Status Offset */
2011 #define SERCOM_USART_INT_STATUS_REG_OFST _UINT32_(0x1A)      /* (SERCOM_USART_INT_STATUS) USART_INT Status Offset */
2012 #define SERCOM_I2CM_SYNCBUSY_REG_OFST  _UINT32_(0x1C)      /* (SERCOM_I2CM_SYNCBUSY) I2CM Synchronization Busy Offset */
2013 #define SERCOM_I2CS_SYNCBUSY_REG_OFST  _UINT32_(0x1C)      /* (SERCOM_I2CS_SYNCBUSY) I2CS Synchronization Busy Offset */
2014 #define SERCOM_SPIM_SYNCBUSY_REG_OFST  _UINT32_(0x1C)      /* (SERCOM_SPIM_SYNCBUSY) SPIM Synchronization Busy Offset */
2015 #define SERCOM_SPIS_SYNCBUSY_REG_OFST  _UINT32_(0x1C)      /* (SERCOM_SPIS_SYNCBUSY) SPIS Synchronization Busy Offset */
2016 #define SERCOM_USART_EXT_SYNCBUSY_REG_OFST _UINT32_(0x1C)      /* (SERCOM_USART_EXT_SYNCBUSY) USART_EXT Synchronization Busy Offset */
2017 #define SERCOM_USART_INT_SYNCBUSY_REG_OFST _UINT32_(0x1C)      /* (SERCOM_USART_INT_SYNCBUSY) USART_INT Synchronization Busy Offset */
2018 #define SERCOM_USART_EXT_RXERRCNT_REG_OFST _UINT32_(0x20)      /* (SERCOM_USART_EXT_RXERRCNT) USART_EXT Receive Error Count Offset */
2019 #define SERCOM_USART_INT_RXERRCNT_REG_OFST _UINT32_(0x20)      /* (SERCOM_USART_INT_RXERRCNT) USART_INT Receive Error Count Offset */
2020 #define SERCOM_I2CS_LENGTH_REG_OFST    _UINT32_(0x22)      /* (SERCOM_I2CS_LENGTH) I2CS Length Offset */
2021 #define SERCOM_SPIM_LENGTH_REG_OFST    _UINT32_(0x22)      /* (SERCOM_SPIM_LENGTH) SPIM Length Offset */
2022 #define SERCOM_SPIS_LENGTH_REG_OFST    _UINT32_(0x22)      /* (SERCOM_SPIS_LENGTH) SPIS Length Offset */
2023 #define SERCOM_USART_EXT_LENGTH_REG_OFST _UINT32_(0x22)      /* (SERCOM_USART_EXT_LENGTH) USART_EXT Length Offset */
2024 #define SERCOM_USART_INT_LENGTH_REG_OFST _UINT32_(0x22)      /* (SERCOM_USART_INT_LENGTH) USART_INT Length Offset */
2025 #define SERCOM_I2CM_ADDR_REG_OFST      _UINT32_(0x24)      /* (SERCOM_I2CM_ADDR) I2CM Address Offset */
2026 #define SERCOM_I2CS_ADDR_REG_OFST      _UINT32_(0x24)      /* (SERCOM_I2CS_ADDR) I2CS Address Offset */
2027 #define SERCOM_SPIM_ADDR_REG_OFST      _UINT32_(0x24)      /* (SERCOM_SPIM_ADDR) SPIM Address Offset */
2028 #define SERCOM_SPIS_ADDR_REG_OFST      _UINT32_(0x24)      /* (SERCOM_SPIS_ADDR) SPIS Address Offset */
2029 #define SERCOM_I2CM_DATA_REG_OFST      _UINT32_(0x28)      /* (SERCOM_I2CM_DATA) I2CM Data Offset */
2030 #define SERCOM_I2CS_DATA_REG_OFST      _UINT32_(0x28)      /* (SERCOM_I2CS_DATA) I2CS Data Offset */
2031 #define SERCOM_SPIM_DATA_REG_OFST      _UINT32_(0x28)      /* (SERCOM_SPIM_DATA) SPIM Data Offset */
2032 #define SERCOM_SPIS_DATA_REG_OFST      _UINT32_(0x28)      /* (SERCOM_SPIS_DATA) SPIS Data Offset */
2033 #define SERCOM_USART_EXT_DATA_REG_OFST _UINT32_(0x28)      /* (SERCOM_USART_EXT_DATA) USART_EXT Data Offset */
2034 #define SERCOM_USART_INT_DATA_REG_OFST _UINT32_(0x28)      /* (SERCOM_USART_INT_DATA) USART_INT Data Offset */
2035 #define SERCOM_I2CM_DBGCTRL_REG_OFST   _UINT32_(0x30)      /* (SERCOM_I2CM_DBGCTRL) I2CM Debug Control Offset */
2036 #define SERCOM_SPIM_DBGCTRL_REG_OFST   _UINT32_(0x30)      /* (SERCOM_SPIM_DBGCTRL) SPIM Debug Control Offset */
2037 #define SERCOM_SPIS_DBGCTRL_REG_OFST   _UINT32_(0x30)      /* (SERCOM_SPIS_DBGCTRL) SPIS Debug Control Offset */
2038 #define SERCOM_USART_EXT_DBGCTRL_REG_OFST _UINT32_(0x30)      /* (SERCOM_USART_EXT_DBGCTRL) USART_EXT Debug Control Offset */
2039 #define SERCOM_USART_INT_DBGCTRL_REG_OFST _UINT32_(0x30)      /* (SERCOM_USART_INT_DBGCTRL) USART_INT Debug Control Offset */
2040 
2041 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
2042 /** \brief SERCOM register API structure */
2043 typedef struct
2044 {  /* Serial Communication Interface */
2045   __IO  uint32_t                       SERCOM_CTRLA;       /**< Offset: 0x00 (R/W  32) I2CM Control A */
2046   __IO  uint32_t                       SERCOM_CTRLB;       /**< Offset: 0x04 (R/W  32) I2CM Control B */
2047   __IO  uint32_t                       SERCOM_CTRLC;       /**< Offset: 0x08 (R/W  32) I2CM Control C */
2048   __IO  uint32_t                       SERCOM_BAUD;        /**< Offset: 0x0C (R/W  32) I2CM Baud Rate */
2049   __I   uint8_t                        Reserved1[0x04];
2050   __IO  uint8_t                        SERCOM_INTENCLR;    /**< Offset: 0x14 (R/W  8) I2CM Interrupt Enable Clear */
2051   __I   uint8_t                        Reserved2[0x01];
2052   __IO  uint8_t                        SERCOM_INTENSET;    /**< Offset: 0x16 (R/W  8) I2CM Interrupt Enable Set */
2053   __I   uint8_t                        Reserved3[0x01];
2054   __IO  uint8_t                        SERCOM_INTFLAG;     /**< Offset: 0x18 (R/W  8) I2CM Interrupt Flag Status and Clear */
2055   __I   uint8_t                        Reserved4[0x01];
2056   __IO  uint16_t                       SERCOM_STATUS;      /**< Offset: 0x1A (R/W  16) I2CM Status */
2057   __I   uint32_t                       SERCOM_SYNCBUSY;    /**< Offset: 0x1C (R/   32) I2CM Synchronization Busy */
2058   __I   uint8_t                        Reserved5[0x04];
2059   __IO  uint32_t                       SERCOM_ADDR;        /**< Offset: 0x24 (R/W  32) I2CM Address */
2060   __IO  uint32_t                       SERCOM_DATA;        /**< Offset: 0x28 (R/W  32) I2CM Data */
2061   __I   uint8_t                        Reserved6[0x04];
2062   __IO  uint8_t                        SERCOM_DBGCTRL;     /**< Offset: 0x30 (R/W  8) I2CM Debug Control */
2063 } sercom_i2cm_registers_t;
2064 
2065 /** \brief SERCOM register API structure */
2066 typedef struct
2067 {  /* Serial Communication Interface */
2068   __IO  uint32_t                       SERCOM_CTRLA;       /**< Offset: 0x00 (R/W  32) I2CS Control A */
2069   __IO  uint32_t                       SERCOM_CTRLB;       /**< Offset: 0x04 (R/W  32) I2CS Control B */
2070   __IO  uint32_t                       SERCOM_CTRLC;       /**< Offset: 0x08 (R/W  32) I2CS Control C */
2071   __I   uint8_t                        Reserved1[0x08];
2072   __IO  uint8_t                        SERCOM_INTENCLR;    /**< Offset: 0x14 (R/W  8) I2CS Interrupt Enable Clear */
2073   __I   uint8_t                        Reserved2[0x01];
2074   __IO  uint8_t                        SERCOM_INTENSET;    /**< Offset: 0x16 (R/W  8) I2CS Interrupt Enable Set */
2075   __I   uint8_t                        Reserved3[0x01];
2076   __IO  uint8_t                        SERCOM_INTFLAG;     /**< Offset: 0x18 (R/W  8) I2CS Interrupt Flag Status and Clear */
2077   __I   uint8_t                        Reserved4[0x01];
2078   __IO  uint16_t                       SERCOM_STATUS;      /**< Offset: 0x1A (R/W  16) I2CS Status */
2079   __I   uint32_t                       SERCOM_SYNCBUSY;    /**< Offset: 0x1C (R/   32) I2CS Synchronization Busy */
2080   __I   uint8_t                        Reserved5[0x02];
2081   __IO  uint16_t                       SERCOM_LENGTH;      /**< Offset: 0x22 (R/W  16) I2CS Length */
2082   __IO  uint32_t                       SERCOM_ADDR;        /**< Offset: 0x24 (R/W  32) I2CS Address */
2083   __IO  uint32_t                       SERCOM_DATA;        /**< Offset: 0x28 (R/W  32) I2CS Data */
2084 } sercom_i2cs_registers_t;
2085 
2086 /** \brief SERCOM register API structure */
2087 typedef struct
2088 {  /* Serial Communication Interface */
2089   __IO  uint32_t                       SERCOM_CTRLA;       /**< Offset: 0x00 (R/W  32) SPIS Control A */
2090   __IO  uint32_t                       SERCOM_CTRLB;       /**< Offset: 0x04 (R/W  32) SPIS Control B */
2091   __IO  uint32_t                       SERCOM_CTRLC;       /**< Offset: 0x08 (R/W  32) SPIS Control C */
2092   __IO  uint8_t                        SERCOM_BAUD;        /**< Offset: 0x0C (R/W  8) SPIS Baud Rate */
2093   __I   uint8_t                        Reserved1[0x07];
2094   __IO  uint8_t                        SERCOM_INTENCLR;    /**< Offset: 0x14 (R/W  8) SPIS Interrupt Enable Clear */
2095   __I   uint8_t                        Reserved2[0x01];
2096   __IO  uint8_t                        SERCOM_INTENSET;    /**< Offset: 0x16 (R/W  8) SPIS Interrupt Enable Set */
2097   __I   uint8_t                        Reserved3[0x01];
2098   __IO  uint8_t                        SERCOM_INTFLAG;     /**< Offset: 0x18 (R/W  8) SPIS Interrupt Flag Status and Clear */
2099   __I   uint8_t                        Reserved4[0x01];
2100   __IO  uint16_t                       SERCOM_STATUS;      /**< Offset: 0x1A (R/W  16) SPIS Status */
2101   __I   uint32_t                       SERCOM_SYNCBUSY;    /**< Offset: 0x1C (R/   32) SPIS Synchronization Busy */
2102   __I   uint8_t                        Reserved5[0x02];
2103   __IO  uint16_t                       SERCOM_LENGTH;      /**< Offset: 0x22 (R/W  16) SPIS Length */
2104   __IO  uint32_t                       SERCOM_ADDR;        /**< Offset: 0x24 (R/W  32) SPIS Address */
2105   __IO  uint32_t                       SERCOM_DATA;        /**< Offset: 0x28 (R/W  32) SPIS Data */
2106   __I   uint8_t                        Reserved6[0x04];
2107   __IO  uint8_t                        SERCOM_DBGCTRL;     /**< Offset: 0x30 (R/W  8) SPIS Debug Control */
2108 } sercom_spis_registers_t;
2109 
2110 /** \brief SERCOM register API structure */
2111 typedef struct
2112 {  /* Serial Communication Interface */
2113   __IO  uint32_t                       SERCOM_CTRLA;       /**< Offset: 0x00 (R/W  32) SPIM Control A */
2114   __IO  uint32_t                       SERCOM_CTRLB;       /**< Offset: 0x04 (R/W  32) SPIM Control B */
2115   __IO  uint32_t                       SERCOM_CTRLC;       /**< Offset: 0x08 (R/W  32) SPIM Control C */
2116   __IO  uint8_t                        SERCOM_BAUD;        /**< Offset: 0x0C (R/W  8) SPIM Baud Rate */
2117   __I   uint8_t                        Reserved1[0x07];
2118   __IO  uint8_t                        SERCOM_INTENCLR;    /**< Offset: 0x14 (R/W  8) SPIM Interrupt Enable Clear */
2119   __I   uint8_t                        Reserved2[0x01];
2120   __IO  uint8_t                        SERCOM_INTENSET;    /**< Offset: 0x16 (R/W  8) SPIM Interrupt Enable Set */
2121   __I   uint8_t                        Reserved3[0x01];
2122   __IO  uint8_t                        SERCOM_INTFLAG;     /**< Offset: 0x18 (R/W  8) SPIM Interrupt Flag Status and Clear */
2123   __I   uint8_t                        Reserved4[0x01];
2124   __IO  uint16_t                       SERCOM_STATUS;      /**< Offset: 0x1A (R/W  16) SPIM Status */
2125   __I   uint32_t                       SERCOM_SYNCBUSY;    /**< Offset: 0x1C (R/   32) SPIM Synchronization Busy */
2126   __I   uint8_t                        Reserved5[0x02];
2127   __IO  uint16_t                       SERCOM_LENGTH;      /**< Offset: 0x22 (R/W  16) SPIM Length */
2128   __IO  uint32_t                       SERCOM_ADDR;        /**< Offset: 0x24 (R/W  32) SPIM Address */
2129   __IO  uint32_t                       SERCOM_DATA;        /**< Offset: 0x28 (R/W  32) SPIM Data */
2130   __I   uint8_t                        Reserved6[0x04];
2131   __IO  uint8_t                        SERCOM_DBGCTRL;     /**< Offset: 0x30 (R/W  8) SPIM Debug Control */
2132 } sercom_spim_registers_t;
2133 
2134 /** \brief SERCOM register API structure */
2135 typedef struct
2136 {  /* Serial Communication Interface */
2137   __IO  uint32_t                       SERCOM_CTRLA;       /**< Offset: 0x00 (R/W  32) USART_EXT Control A */
2138   __IO  uint32_t                       SERCOM_CTRLB;       /**< Offset: 0x04 (R/W  32) USART_EXT Control B */
2139   __IO  uint32_t                       SERCOM_CTRLC;       /**< Offset: 0x08 (R/W  32) USART_EXT Control C */
2140   __IO  uint16_t                       SERCOM_BAUD;        /**< Offset: 0x0C (R/W  16) USART_EXT Baud Rate */
2141   __IO  uint8_t                        SERCOM_RXPL;        /**< Offset: 0x0E (R/W  8) USART_EXT Receive Pulse Length */
2142   __I   uint8_t                        Reserved1[0x05];
2143   __IO  uint8_t                        SERCOM_INTENCLR;    /**< Offset: 0x14 (R/W  8) USART_EXT Interrupt Enable Clear */
2144   __I   uint8_t                        Reserved2[0x01];
2145   __IO  uint8_t                        SERCOM_INTENSET;    /**< Offset: 0x16 (R/W  8) USART_EXT Interrupt Enable Set */
2146   __I   uint8_t                        Reserved3[0x01];
2147   __IO  uint8_t                        SERCOM_INTFLAG;     /**< Offset: 0x18 (R/W  8) USART_EXT Interrupt Flag Status and Clear */
2148   __I   uint8_t                        Reserved4[0x01];
2149   __IO  uint16_t                       SERCOM_STATUS;      /**< Offset: 0x1A (R/W  16) USART_EXT Status */
2150   __I   uint32_t                       SERCOM_SYNCBUSY;    /**< Offset: 0x1C (R/   32) USART_EXT Synchronization Busy */
2151   __I   uint8_t                        SERCOM_RXERRCNT;    /**< Offset: 0x20 (R/   8) USART_EXT Receive Error Count */
2152   __I   uint8_t                        Reserved5[0x01];
2153   __IO  uint16_t                       SERCOM_LENGTH;      /**< Offset: 0x22 (R/W  16) USART_EXT Length */
2154   __I   uint8_t                        Reserved6[0x04];
2155   __IO  uint32_t                       SERCOM_DATA;        /**< Offset: 0x28 (R/W  32) USART_EXT Data */
2156   __I   uint8_t                        Reserved7[0x04];
2157   __IO  uint8_t                        SERCOM_DBGCTRL;     /**< Offset: 0x30 (R/W  8) USART_EXT Debug Control */
2158 } sercom_usart_ext_registers_t;
2159 
2160 /** \brief SERCOM register API structure */
2161 typedef struct
2162 {  /* Serial Communication Interface */
2163   __IO  uint32_t                       SERCOM_CTRLA;       /**< Offset: 0x00 (R/W  32) USART_INT Control A */
2164   __IO  uint32_t                       SERCOM_CTRLB;       /**< Offset: 0x04 (R/W  32) USART_INT Control B */
2165   __IO  uint32_t                       SERCOM_CTRLC;       /**< Offset: 0x08 (R/W  32) USART_INT Control C */
2166   __IO  uint16_t                       SERCOM_BAUD;        /**< Offset: 0x0C (R/W  16) USART_INT Baud Rate */
2167   __IO  uint8_t                        SERCOM_RXPL;        /**< Offset: 0x0E (R/W  8) USART_INT Receive Pulse Length */
2168   __I   uint8_t                        Reserved1[0x05];
2169   __IO  uint8_t                        SERCOM_INTENCLR;    /**< Offset: 0x14 (R/W  8) USART_INT Interrupt Enable Clear */
2170   __I   uint8_t                        Reserved2[0x01];
2171   __IO  uint8_t                        SERCOM_INTENSET;    /**< Offset: 0x16 (R/W  8) USART_INT Interrupt Enable Set */
2172   __I   uint8_t                        Reserved3[0x01];
2173   __IO  uint8_t                        SERCOM_INTFLAG;     /**< Offset: 0x18 (R/W  8) USART_INT Interrupt Flag Status and Clear */
2174   __I   uint8_t                        Reserved4[0x01];
2175   __IO  uint16_t                       SERCOM_STATUS;      /**< Offset: 0x1A (R/W  16) USART_INT Status */
2176   __I   uint32_t                       SERCOM_SYNCBUSY;    /**< Offset: 0x1C (R/   32) USART_INT Synchronization Busy */
2177   __I   uint8_t                        SERCOM_RXERRCNT;    /**< Offset: 0x20 (R/   8) USART_INT Receive Error Count */
2178   __I   uint8_t                        Reserved5[0x01];
2179   __IO  uint16_t                       SERCOM_LENGTH;      /**< Offset: 0x22 (R/W  16) USART_INT Length */
2180   __I   uint8_t                        Reserved6[0x04];
2181   __IO  uint32_t                       SERCOM_DATA;        /**< Offset: 0x28 (R/W  32) USART_INT Data */
2182   __I   uint8_t                        Reserved7[0x04];
2183   __IO  uint8_t                        SERCOM_DBGCTRL;     /**< Offset: 0x30 (R/W  8) USART_INT Debug Control */
2184 } sercom_usart_int_registers_t;
2185 
2186 /** \brief SERCOM hardware registers */
2187 typedef union
2188 {  /* Serial Communication Interface */
2189        sercom_i2cm_registers_t        I2CM;           /**< I2C Master Mode */
2190        sercom_i2cs_registers_t        I2CS;           /**< I2C Slave Mode */
2191        sercom_spis_registers_t        SPIS;           /**< SPI Slave Mode */
2192        sercom_spim_registers_t        SPIM;           /**< SPI Master Mode */
2193        sercom_usart_ext_registers_t   USART_EXT;      /**< USART EXTERNAL CLOCK Mode */
2194        sercom_usart_int_registers_t   USART_INT;      /**< USART INTERNAL CLOCK Mode */
2195 } sercom_registers_t;
2196 
2197 
2198 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
2199 #endif /* _PIC32CXSG60_SERCOM_COMPONENT_H_ */
2200