1 /* 2 * Component description for FREQM 3 * 4 * Copyright (c) 2023 Microchip Technology Inc. and its subsidiaries. 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 */ 19 20 /* file generated from device description file (ATDF) version 2023-03-17T09:48:46Z */ 21 #ifndef _PIC32CXSG60_FREQM_COMPONENT_H_ 22 #define _PIC32CXSG60_FREQM_COMPONENT_H_ 23 24 /* ************************************************************************** */ 25 /* SOFTWARE API DEFINITION FOR FREQM */ 26 /* ************************************************************************** */ 27 28 /* -------- FREQM_CTRLA : (FREQM Offset: 0x00) (R/W 8) Control A Register -------- */ 29 #define FREQM_CTRLA_RESETVALUE _UINT8_(0x00) /* (FREQM_CTRLA) Control A Register Reset Value */ 30 31 #define FREQM_CTRLA_SWRST_Pos _UINT8_(0) /* (FREQM_CTRLA) Software Reset Position */ 32 #define FREQM_CTRLA_SWRST_Msk (_UINT8_(0x1) << FREQM_CTRLA_SWRST_Pos) /* (FREQM_CTRLA) Software Reset Mask */ 33 #define FREQM_CTRLA_SWRST(value) (FREQM_CTRLA_SWRST_Msk & (_UINT8_(value) << FREQM_CTRLA_SWRST_Pos)) /* Assigment of value for SWRST in the FREQM_CTRLA register */ 34 #define FREQM_CTRLA_ENABLE_Pos _UINT8_(1) /* (FREQM_CTRLA) Enable Position */ 35 #define FREQM_CTRLA_ENABLE_Msk (_UINT8_(0x1) << FREQM_CTRLA_ENABLE_Pos) /* (FREQM_CTRLA) Enable Mask */ 36 #define FREQM_CTRLA_ENABLE(value) (FREQM_CTRLA_ENABLE_Msk & (_UINT8_(value) << FREQM_CTRLA_ENABLE_Pos)) /* Assigment of value for ENABLE in the FREQM_CTRLA register */ 37 #define FREQM_CTRLA_Msk _UINT8_(0x03) /* (FREQM_CTRLA) Register Mask */ 38 39 40 /* -------- FREQM_CTRLB : (FREQM Offset: 0x01) ( /W 8) Control B Register -------- */ 41 #define FREQM_CTRLB_RESETVALUE _UINT8_(0x00) /* (FREQM_CTRLB) Control B Register Reset Value */ 42 43 #define FREQM_CTRLB_START_Pos _UINT8_(0) /* (FREQM_CTRLB) Start Measurement Position */ 44 #define FREQM_CTRLB_START_Msk (_UINT8_(0x1) << FREQM_CTRLB_START_Pos) /* (FREQM_CTRLB) Start Measurement Mask */ 45 #define FREQM_CTRLB_START(value) (FREQM_CTRLB_START_Msk & (_UINT8_(value) << FREQM_CTRLB_START_Pos)) /* Assigment of value for START in the FREQM_CTRLB register */ 46 #define FREQM_CTRLB_Msk _UINT8_(0x01) /* (FREQM_CTRLB) Register Mask */ 47 48 49 /* -------- FREQM_CFGA : (FREQM Offset: 0x02) (R/W 16) Config A register -------- */ 50 #define FREQM_CFGA_RESETVALUE _UINT16_(0x00) /* (FREQM_CFGA) Config A register Reset Value */ 51 52 #define FREQM_CFGA_REFNUM_Pos _UINT16_(0) /* (FREQM_CFGA) Number of Reference Clock Cycles Position */ 53 #define FREQM_CFGA_REFNUM_Msk (_UINT16_(0xFF) << FREQM_CFGA_REFNUM_Pos) /* (FREQM_CFGA) Number of Reference Clock Cycles Mask */ 54 #define FREQM_CFGA_REFNUM(value) (FREQM_CFGA_REFNUM_Msk & (_UINT16_(value) << FREQM_CFGA_REFNUM_Pos)) /* Assigment of value for REFNUM in the FREQM_CFGA register */ 55 #define FREQM_CFGA_Msk _UINT16_(0x00FF) /* (FREQM_CFGA) Register Mask */ 56 57 58 /* -------- FREQM_INTENCLR : (FREQM Offset: 0x08) (R/W 8) Interrupt Enable Clear Register -------- */ 59 #define FREQM_INTENCLR_RESETVALUE _UINT8_(0x00) /* (FREQM_INTENCLR) Interrupt Enable Clear Register Reset Value */ 60 61 #define FREQM_INTENCLR_DONE_Pos _UINT8_(0) /* (FREQM_INTENCLR) Measurement Done Interrupt Enable Position */ 62 #define FREQM_INTENCLR_DONE_Msk (_UINT8_(0x1) << FREQM_INTENCLR_DONE_Pos) /* (FREQM_INTENCLR) Measurement Done Interrupt Enable Mask */ 63 #define FREQM_INTENCLR_DONE(value) (FREQM_INTENCLR_DONE_Msk & (_UINT8_(value) << FREQM_INTENCLR_DONE_Pos)) /* Assigment of value for DONE in the FREQM_INTENCLR register */ 64 #define FREQM_INTENCLR_Msk _UINT8_(0x01) /* (FREQM_INTENCLR) Register Mask */ 65 66 67 /* -------- FREQM_INTENSET : (FREQM Offset: 0x09) (R/W 8) Interrupt Enable Set Register -------- */ 68 #define FREQM_INTENSET_RESETVALUE _UINT8_(0x00) /* (FREQM_INTENSET) Interrupt Enable Set Register Reset Value */ 69 70 #define FREQM_INTENSET_DONE_Pos _UINT8_(0) /* (FREQM_INTENSET) Measurement Done Interrupt Enable Position */ 71 #define FREQM_INTENSET_DONE_Msk (_UINT8_(0x1) << FREQM_INTENSET_DONE_Pos) /* (FREQM_INTENSET) Measurement Done Interrupt Enable Mask */ 72 #define FREQM_INTENSET_DONE(value) (FREQM_INTENSET_DONE_Msk & (_UINT8_(value) << FREQM_INTENSET_DONE_Pos)) /* Assigment of value for DONE in the FREQM_INTENSET register */ 73 #define FREQM_INTENSET_Msk _UINT8_(0x01) /* (FREQM_INTENSET) Register Mask */ 74 75 76 /* -------- FREQM_INTFLAG : (FREQM Offset: 0x0A) (R/W 8) Interrupt Flag Register -------- */ 77 #define FREQM_INTFLAG_RESETVALUE _UINT8_(0x00) /* (FREQM_INTFLAG) Interrupt Flag Register Reset Value */ 78 79 #define FREQM_INTFLAG_DONE_Pos _UINT8_(0) /* (FREQM_INTFLAG) Measurement Done Position */ 80 #define FREQM_INTFLAG_DONE_Msk (_UINT8_(0x1) << FREQM_INTFLAG_DONE_Pos) /* (FREQM_INTFLAG) Measurement Done Mask */ 81 #define FREQM_INTFLAG_DONE(value) (FREQM_INTFLAG_DONE_Msk & (_UINT8_(value) << FREQM_INTFLAG_DONE_Pos)) /* Assigment of value for DONE in the FREQM_INTFLAG register */ 82 #define FREQM_INTFLAG_Msk _UINT8_(0x01) /* (FREQM_INTFLAG) Register Mask */ 83 84 85 /* -------- FREQM_STATUS : (FREQM Offset: 0x0B) (R/W 8) Status Register -------- */ 86 #define FREQM_STATUS_RESETVALUE _UINT8_(0x00) /* (FREQM_STATUS) Status Register Reset Value */ 87 88 #define FREQM_STATUS_BUSY_Pos _UINT8_(0) /* (FREQM_STATUS) FREQM Status Position */ 89 #define FREQM_STATUS_BUSY_Msk (_UINT8_(0x1) << FREQM_STATUS_BUSY_Pos) /* (FREQM_STATUS) FREQM Status Mask */ 90 #define FREQM_STATUS_BUSY(value) (FREQM_STATUS_BUSY_Msk & (_UINT8_(value) << FREQM_STATUS_BUSY_Pos)) /* Assigment of value for BUSY in the FREQM_STATUS register */ 91 #define FREQM_STATUS_OVF_Pos _UINT8_(1) /* (FREQM_STATUS) Sticky Count Value Overflow Position */ 92 #define FREQM_STATUS_OVF_Msk (_UINT8_(0x1) << FREQM_STATUS_OVF_Pos) /* (FREQM_STATUS) Sticky Count Value Overflow Mask */ 93 #define FREQM_STATUS_OVF(value) (FREQM_STATUS_OVF_Msk & (_UINT8_(value) << FREQM_STATUS_OVF_Pos)) /* Assigment of value for OVF in the FREQM_STATUS register */ 94 #define FREQM_STATUS_Msk _UINT8_(0x03) /* (FREQM_STATUS) Register Mask */ 95 96 97 /* -------- FREQM_SYNCBUSY : (FREQM Offset: 0x0C) ( R/ 32) Synchronization Busy Register -------- */ 98 #define FREQM_SYNCBUSY_RESETVALUE _UINT32_(0x00) /* (FREQM_SYNCBUSY) Synchronization Busy Register Reset Value */ 99 100 #define FREQM_SYNCBUSY_SWRST_Pos _UINT32_(0) /* (FREQM_SYNCBUSY) Software Reset Position */ 101 #define FREQM_SYNCBUSY_SWRST_Msk (_UINT32_(0x1) << FREQM_SYNCBUSY_SWRST_Pos) /* (FREQM_SYNCBUSY) Software Reset Mask */ 102 #define FREQM_SYNCBUSY_SWRST(value) (FREQM_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << FREQM_SYNCBUSY_SWRST_Pos)) /* Assigment of value for SWRST in the FREQM_SYNCBUSY register */ 103 #define FREQM_SYNCBUSY_ENABLE_Pos _UINT32_(1) /* (FREQM_SYNCBUSY) Enable Position */ 104 #define FREQM_SYNCBUSY_ENABLE_Msk (_UINT32_(0x1) << FREQM_SYNCBUSY_ENABLE_Pos) /* (FREQM_SYNCBUSY) Enable Mask */ 105 #define FREQM_SYNCBUSY_ENABLE(value) (FREQM_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << FREQM_SYNCBUSY_ENABLE_Pos)) /* Assigment of value for ENABLE in the FREQM_SYNCBUSY register */ 106 #define FREQM_SYNCBUSY_Msk _UINT32_(0x00000003) /* (FREQM_SYNCBUSY) Register Mask */ 107 108 109 /* -------- FREQM_VALUE : (FREQM Offset: 0x10) ( R/ 32) Count Value Register -------- */ 110 #define FREQM_VALUE_RESETVALUE _UINT32_(0x00) /* (FREQM_VALUE) Count Value Register Reset Value */ 111 112 #define FREQM_VALUE_VALUE_Pos _UINT32_(0) /* (FREQM_VALUE) Measurement Value Position */ 113 #define FREQM_VALUE_VALUE_Msk (_UINT32_(0xFFFFFF) << FREQM_VALUE_VALUE_Pos) /* (FREQM_VALUE) Measurement Value Mask */ 114 #define FREQM_VALUE_VALUE(value) (FREQM_VALUE_VALUE_Msk & (_UINT32_(value) << FREQM_VALUE_VALUE_Pos)) /* Assigment of value for VALUE in the FREQM_VALUE register */ 115 #define FREQM_VALUE_Msk _UINT32_(0x00FFFFFF) /* (FREQM_VALUE) Register Mask */ 116 117 118 /** \brief FREQM register offsets definitions */ 119 #define FREQM_CTRLA_REG_OFST _UINT32_(0x00) /* (FREQM_CTRLA) Control A Register Offset */ 120 #define FREQM_CTRLB_REG_OFST _UINT32_(0x01) /* (FREQM_CTRLB) Control B Register Offset */ 121 #define FREQM_CFGA_REG_OFST _UINT32_(0x02) /* (FREQM_CFGA) Config A register Offset */ 122 #define FREQM_INTENCLR_REG_OFST _UINT32_(0x08) /* (FREQM_INTENCLR) Interrupt Enable Clear Register Offset */ 123 #define FREQM_INTENSET_REG_OFST _UINT32_(0x09) /* (FREQM_INTENSET) Interrupt Enable Set Register Offset */ 124 #define FREQM_INTFLAG_REG_OFST _UINT32_(0x0A) /* (FREQM_INTFLAG) Interrupt Flag Register Offset */ 125 #define FREQM_STATUS_REG_OFST _UINT32_(0x0B) /* (FREQM_STATUS) Status Register Offset */ 126 #define FREQM_SYNCBUSY_REG_OFST _UINT32_(0x0C) /* (FREQM_SYNCBUSY) Synchronization Busy Register Offset */ 127 #define FREQM_VALUE_REG_OFST _UINT32_(0x10) /* (FREQM_VALUE) Count Value Register Offset */ 128 129 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 130 /** \brief FREQM register API structure */ 131 typedef struct 132 { /* Frequency Meter */ 133 __IO uint8_t FREQM_CTRLA; /**< Offset: 0x00 (R/W 8) Control A Register */ 134 __O uint8_t FREQM_CTRLB; /**< Offset: 0x01 ( /W 8) Control B Register */ 135 __IO uint16_t FREQM_CFGA; /**< Offset: 0x02 (R/W 16) Config A register */ 136 __I uint8_t Reserved1[0x04]; 137 __IO uint8_t FREQM_INTENCLR; /**< Offset: 0x08 (R/W 8) Interrupt Enable Clear Register */ 138 __IO uint8_t FREQM_INTENSET; /**< Offset: 0x09 (R/W 8) Interrupt Enable Set Register */ 139 __IO uint8_t FREQM_INTFLAG; /**< Offset: 0x0A (R/W 8) Interrupt Flag Register */ 140 __IO uint8_t FREQM_STATUS; /**< Offset: 0x0B (R/W 8) Status Register */ 141 __I uint32_t FREQM_SYNCBUSY; /**< Offset: 0x0C (R/ 32) Synchronization Busy Register */ 142 __I uint32_t FREQM_VALUE; /**< Offset: 0x10 (R/ 32) Count Value Register */ 143 } freqm_registers_t; 144 145 146 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 147 #endif /* _PIC32CXSG60_FREQM_COMPONENT_H_ */ 148
