1 /* 2 * Component description for EVSYS 3 * 4 * Copyright (c) 2023 Microchip Technology Inc. and its subsidiaries. 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 */ 19 20 /* file generated from device description file (ATDF) version 2023-03-17T09:48:46Z */ 21 #ifndef _PIC32CXSG60_EVSYS_COMPONENT_H_ 22 #define _PIC32CXSG60_EVSYS_COMPONENT_H_ 23 24 /* ************************************************************************** */ 25 /* SOFTWARE API DEFINITION FOR EVSYS */ 26 /* ************************************************************************** */ 27 28 /* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x00) (R/W 32) Channel n Control -------- */ 29 #define EVSYS_CHANNEL_RESETVALUE _UINT32_(0x8000) /* (EVSYS_CHANNEL) Channel n Control Reset Value */ 30 31 #define EVSYS_CHANNEL_EVGEN_Pos _UINT32_(0) /* (EVSYS_CHANNEL) Event Generator Selection Position */ 32 #define EVSYS_CHANNEL_EVGEN_Msk (_UINT32_(0x7F) << EVSYS_CHANNEL_EVGEN_Pos) /* (EVSYS_CHANNEL) Event Generator Selection Mask */ 33 #define EVSYS_CHANNEL_EVGEN(value) (EVSYS_CHANNEL_EVGEN_Msk & (_UINT32_(value) << EVSYS_CHANNEL_EVGEN_Pos)) /* Assigment of value for EVGEN in the EVSYS_CHANNEL register */ 34 #define EVSYS_CHANNEL_PATH_Pos _UINT32_(8) /* (EVSYS_CHANNEL) Path Selection Position */ 35 #define EVSYS_CHANNEL_PATH_Msk (_UINT32_(0x3) << EVSYS_CHANNEL_PATH_Pos) /* (EVSYS_CHANNEL) Path Selection Mask */ 36 #define EVSYS_CHANNEL_PATH(value) (EVSYS_CHANNEL_PATH_Msk & (_UINT32_(value) << EVSYS_CHANNEL_PATH_Pos)) /* Assigment of value for PATH in the EVSYS_CHANNEL register */ 37 #define EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val _UINT32_(0x0) /* (EVSYS_CHANNEL) Synchronous path */ 38 #define EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val _UINT32_(0x1) /* (EVSYS_CHANNEL) Resynchronized path */ 39 #define EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val _UINT32_(0x2) /* (EVSYS_CHANNEL) Asynchronous path */ 40 #define EVSYS_CHANNEL_PATH_SYNCHRONOUS (EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos) /* (EVSYS_CHANNEL) Synchronous path Position */ 41 #define EVSYS_CHANNEL_PATH_RESYNCHRONIZED (EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val << EVSYS_CHANNEL_PATH_Pos) /* (EVSYS_CHANNEL) Resynchronized path Position */ 42 #define EVSYS_CHANNEL_PATH_ASYNCHRONOUS (EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos) /* (EVSYS_CHANNEL) Asynchronous path Position */ 43 #define EVSYS_CHANNEL_EDGSEL_Pos _UINT32_(10) /* (EVSYS_CHANNEL) Edge Detection Selection Position */ 44 #define EVSYS_CHANNEL_EDGSEL_Msk (_UINT32_(0x3) << EVSYS_CHANNEL_EDGSEL_Pos) /* (EVSYS_CHANNEL) Edge Detection Selection Mask */ 45 #define EVSYS_CHANNEL_EDGSEL(value) (EVSYS_CHANNEL_EDGSEL_Msk & (_UINT32_(value) << EVSYS_CHANNEL_EDGSEL_Pos)) /* Assigment of value for EDGSEL in the EVSYS_CHANNEL register */ 46 #define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val _UINT32_(0x0) /* (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path */ 47 #define EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val _UINT32_(0x1) /* (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path */ 48 #define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val _UINT32_(0x2) /* (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path */ 49 #define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val _UINT32_(0x3) /* (EVSYS_CHANNEL) Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path */ 50 #define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT (EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val << EVSYS_CHANNEL_EDGSEL_Pos) /* (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path Position */ 51 #define EVSYS_CHANNEL_EDGSEL_RISING_EDGE (EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos) /* (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path Position */ 52 #define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE (EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos) /* (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path Position */ 53 #define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES (EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val << EVSYS_CHANNEL_EDGSEL_Pos) /* (EVSYS_CHANNEL) Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path Position */ 54 #define EVSYS_CHANNEL_RUNSTDBY_Pos _UINT32_(14) /* (EVSYS_CHANNEL) Run in standby Position */ 55 #define EVSYS_CHANNEL_RUNSTDBY_Msk (_UINT32_(0x1) << EVSYS_CHANNEL_RUNSTDBY_Pos) /* (EVSYS_CHANNEL) Run in standby Mask */ 56 #define EVSYS_CHANNEL_RUNSTDBY(value) (EVSYS_CHANNEL_RUNSTDBY_Msk & (_UINT32_(value) << EVSYS_CHANNEL_RUNSTDBY_Pos)) /* Assigment of value for RUNSTDBY in the EVSYS_CHANNEL register */ 57 #define EVSYS_CHANNEL_ONDEMAND_Pos _UINT32_(15) /* (EVSYS_CHANNEL) Generic Clock On Demand Position */ 58 #define EVSYS_CHANNEL_ONDEMAND_Msk (_UINT32_(0x1) << EVSYS_CHANNEL_ONDEMAND_Pos) /* (EVSYS_CHANNEL) Generic Clock On Demand Mask */ 59 #define EVSYS_CHANNEL_ONDEMAND(value) (EVSYS_CHANNEL_ONDEMAND_Msk & (_UINT32_(value) << EVSYS_CHANNEL_ONDEMAND_Pos)) /* Assigment of value for ONDEMAND in the EVSYS_CHANNEL register */ 60 #define EVSYS_CHANNEL_Msk _UINT32_(0x0000CF7F) /* (EVSYS_CHANNEL) Register Mask */ 61 62 63 /* -------- EVSYS_CHINTENCLR : (EVSYS Offset: 0x04) (R/W 8) Channel n Interrupt Enable Clear -------- */ 64 #define EVSYS_CHINTENCLR_RESETVALUE _UINT8_(0x00) /* (EVSYS_CHINTENCLR) Channel n Interrupt Enable Clear Reset Value */ 65 66 #define EVSYS_CHINTENCLR_OVR_Pos _UINT8_(0) /* (EVSYS_CHINTENCLR) Channel Overrun Interrupt Disable Position */ 67 #define EVSYS_CHINTENCLR_OVR_Msk (_UINT8_(0x1) << EVSYS_CHINTENCLR_OVR_Pos) /* (EVSYS_CHINTENCLR) Channel Overrun Interrupt Disable Mask */ 68 #define EVSYS_CHINTENCLR_OVR(value) (EVSYS_CHINTENCLR_OVR_Msk & (_UINT8_(value) << EVSYS_CHINTENCLR_OVR_Pos)) /* Assigment of value for OVR in the EVSYS_CHINTENCLR register */ 69 #define EVSYS_CHINTENCLR_EVD_Pos _UINT8_(1) /* (EVSYS_CHINTENCLR) Channel Event Detected Interrupt Disable Position */ 70 #define EVSYS_CHINTENCLR_EVD_Msk (_UINT8_(0x1) << EVSYS_CHINTENCLR_EVD_Pos) /* (EVSYS_CHINTENCLR) Channel Event Detected Interrupt Disable Mask */ 71 #define EVSYS_CHINTENCLR_EVD(value) (EVSYS_CHINTENCLR_EVD_Msk & (_UINT8_(value) << EVSYS_CHINTENCLR_EVD_Pos)) /* Assigment of value for EVD in the EVSYS_CHINTENCLR register */ 72 #define EVSYS_CHINTENCLR_Msk _UINT8_(0x03) /* (EVSYS_CHINTENCLR) Register Mask */ 73 74 75 /* -------- EVSYS_CHINTENSET : (EVSYS Offset: 0x05) (R/W 8) Channel n Interrupt Enable Set -------- */ 76 #define EVSYS_CHINTENSET_RESETVALUE _UINT8_(0x00) /* (EVSYS_CHINTENSET) Channel n Interrupt Enable Set Reset Value */ 77 78 #define EVSYS_CHINTENSET_OVR_Pos _UINT8_(0) /* (EVSYS_CHINTENSET) Channel Overrun Interrupt Enable Position */ 79 #define EVSYS_CHINTENSET_OVR_Msk (_UINT8_(0x1) << EVSYS_CHINTENSET_OVR_Pos) /* (EVSYS_CHINTENSET) Channel Overrun Interrupt Enable Mask */ 80 #define EVSYS_CHINTENSET_OVR(value) (EVSYS_CHINTENSET_OVR_Msk & (_UINT8_(value) << EVSYS_CHINTENSET_OVR_Pos)) /* Assigment of value for OVR in the EVSYS_CHINTENSET register */ 81 #define EVSYS_CHINTENSET_EVD_Pos _UINT8_(1) /* (EVSYS_CHINTENSET) Channel Event Detected Interrupt Enable Position */ 82 #define EVSYS_CHINTENSET_EVD_Msk (_UINT8_(0x1) << EVSYS_CHINTENSET_EVD_Pos) /* (EVSYS_CHINTENSET) Channel Event Detected Interrupt Enable Mask */ 83 #define EVSYS_CHINTENSET_EVD(value) (EVSYS_CHINTENSET_EVD_Msk & (_UINT8_(value) << EVSYS_CHINTENSET_EVD_Pos)) /* Assigment of value for EVD in the EVSYS_CHINTENSET register */ 84 #define EVSYS_CHINTENSET_Msk _UINT8_(0x03) /* (EVSYS_CHINTENSET) Register Mask */ 85 86 87 /* -------- EVSYS_CHINTFLAG : (EVSYS Offset: 0x06) (R/W 8) Channel n Interrupt Flag Status and Clear -------- */ 88 #define EVSYS_CHINTFLAG_RESETVALUE _UINT8_(0x00) /* (EVSYS_CHINTFLAG) Channel n Interrupt Flag Status and Clear Reset Value */ 89 90 #define EVSYS_CHINTFLAG_OVR_Pos _UINT8_(0) /* (EVSYS_CHINTFLAG) Channel Overrun Position */ 91 #define EVSYS_CHINTFLAG_OVR_Msk (_UINT8_(0x1) << EVSYS_CHINTFLAG_OVR_Pos) /* (EVSYS_CHINTFLAG) Channel Overrun Mask */ 92 #define EVSYS_CHINTFLAG_OVR(value) (EVSYS_CHINTFLAG_OVR_Msk & (_UINT8_(value) << EVSYS_CHINTFLAG_OVR_Pos)) /* Assigment of value for OVR in the EVSYS_CHINTFLAG register */ 93 #define EVSYS_CHINTFLAG_EVD_Pos _UINT8_(1) /* (EVSYS_CHINTFLAG) Channel Event Detected Position */ 94 #define EVSYS_CHINTFLAG_EVD_Msk (_UINT8_(0x1) << EVSYS_CHINTFLAG_EVD_Pos) /* (EVSYS_CHINTFLAG) Channel Event Detected Mask */ 95 #define EVSYS_CHINTFLAG_EVD(value) (EVSYS_CHINTFLAG_EVD_Msk & (_UINT8_(value) << EVSYS_CHINTFLAG_EVD_Pos)) /* Assigment of value for EVD in the EVSYS_CHINTFLAG register */ 96 #define EVSYS_CHINTFLAG_Msk _UINT8_(0x03) /* (EVSYS_CHINTFLAG) Register Mask */ 97 98 99 /* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x07) ( R/ 8) Channel n Status -------- */ 100 #define EVSYS_CHSTATUS_RESETVALUE _UINT8_(0x01) /* (EVSYS_CHSTATUS) Channel n Status Reset Value */ 101 102 #define EVSYS_CHSTATUS_RDYUSR_Pos _UINT8_(0) /* (EVSYS_CHSTATUS) Ready User Position */ 103 #define EVSYS_CHSTATUS_RDYUSR_Msk (_UINT8_(0x1) << EVSYS_CHSTATUS_RDYUSR_Pos) /* (EVSYS_CHSTATUS) Ready User Mask */ 104 #define EVSYS_CHSTATUS_RDYUSR(value) (EVSYS_CHSTATUS_RDYUSR_Msk & (_UINT8_(value) << EVSYS_CHSTATUS_RDYUSR_Pos)) /* Assigment of value for RDYUSR in the EVSYS_CHSTATUS register */ 105 #define EVSYS_CHSTATUS_BUSYCH_Pos _UINT8_(1) /* (EVSYS_CHSTATUS) Busy Channel Position */ 106 #define EVSYS_CHSTATUS_BUSYCH_Msk (_UINT8_(0x1) << EVSYS_CHSTATUS_BUSYCH_Pos) /* (EVSYS_CHSTATUS) Busy Channel Mask */ 107 #define EVSYS_CHSTATUS_BUSYCH(value) (EVSYS_CHSTATUS_BUSYCH_Msk & (_UINT8_(value) << EVSYS_CHSTATUS_BUSYCH_Pos)) /* Assigment of value for BUSYCH in the EVSYS_CHSTATUS register */ 108 #define EVSYS_CHSTATUS_Msk _UINT8_(0x03) /* (EVSYS_CHSTATUS) Register Mask */ 109 110 111 /* -------- EVSYS_CTRLA : (EVSYS Offset: 0x00) (R/W 8) Control -------- */ 112 #define EVSYS_CTRLA_RESETVALUE _UINT8_(0x00) /* (EVSYS_CTRLA) Control Reset Value */ 113 114 #define EVSYS_CTRLA_SWRST_Pos _UINT8_(0) /* (EVSYS_CTRLA) Software Reset Position */ 115 #define EVSYS_CTRLA_SWRST_Msk (_UINT8_(0x1) << EVSYS_CTRLA_SWRST_Pos) /* (EVSYS_CTRLA) Software Reset Mask */ 116 #define EVSYS_CTRLA_SWRST(value) (EVSYS_CTRLA_SWRST_Msk & (_UINT8_(value) << EVSYS_CTRLA_SWRST_Pos)) /* Assigment of value for SWRST in the EVSYS_CTRLA register */ 117 #define EVSYS_CTRLA_Msk _UINT8_(0x01) /* (EVSYS_CTRLA) Register Mask */ 118 119 120 /* -------- EVSYS_SWEVT : (EVSYS Offset: 0x04) ( /W 32) Software Event -------- */ 121 #define EVSYS_SWEVT_RESETVALUE _UINT32_(0x00) /* (EVSYS_SWEVT) Software Event Reset Value */ 122 123 #define EVSYS_SWEVT_CHANNEL0_Pos _UINT32_(0) /* (EVSYS_SWEVT) Channel 0 Software Selection Position */ 124 #define EVSYS_SWEVT_CHANNEL0_Msk (_UINT32_(0x1) << EVSYS_SWEVT_CHANNEL0_Pos) /* (EVSYS_SWEVT) Channel 0 Software Selection Mask */ 125 #define EVSYS_SWEVT_CHANNEL0(value) (EVSYS_SWEVT_CHANNEL0_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL0_Pos)) /* Assigment of value for CHANNEL0 in the EVSYS_SWEVT register */ 126 #define EVSYS_SWEVT_CHANNEL1_Pos _UINT32_(1) /* (EVSYS_SWEVT) Channel 1 Software Selection Position */ 127 #define EVSYS_SWEVT_CHANNEL1_Msk (_UINT32_(0x1) << EVSYS_SWEVT_CHANNEL1_Pos) /* (EVSYS_SWEVT) Channel 1 Software Selection Mask */ 128 #define EVSYS_SWEVT_CHANNEL1(value) (EVSYS_SWEVT_CHANNEL1_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL1_Pos)) /* Assigment of value for CHANNEL1 in the EVSYS_SWEVT register */ 129 #define EVSYS_SWEVT_CHANNEL2_Pos _UINT32_(2) /* (EVSYS_SWEVT) Channel 2 Software Selection Position */ 130 #define EVSYS_SWEVT_CHANNEL2_Msk (_UINT32_(0x1) << EVSYS_SWEVT_CHANNEL2_Pos) /* (EVSYS_SWEVT) Channel 2 Software Selection Mask */ 131 #define EVSYS_SWEVT_CHANNEL2(value) (EVSYS_SWEVT_CHANNEL2_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL2_Pos)) /* Assigment of value for CHANNEL2 in the EVSYS_SWEVT register */ 132 #define EVSYS_SWEVT_CHANNEL3_Pos _UINT32_(3) /* (EVSYS_SWEVT) Channel 3 Software Selection Position */ 133 #define EVSYS_SWEVT_CHANNEL3_Msk (_UINT32_(0x1) << EVSYS_SWEVT_CHANNEL3_Pos) /* (EVSYS_SWEVT) Channel 3 Software Selection Mask */ 134 #define EVSYS_SWEVT_CHANNEL3(value) (EVSYS_SWEVT_CHANNEL3_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL3_Pos)) /* Assigment of value for CHANNEL3 in the EVSYS_SWEVT register */ 135 #define EVSYS_SWEVT_CHANNEL4_Pos _UINT32_(4) /* (EVSYS_SWEVT) Channel 4 Software Selection Position */ 136 #define EVSYS_SWEVT_CHANNEL4_Msk (_UINT32_(0x1) << EVSYS_SWEVT_CHANNEL4_Pos) /* (EVSYS_SWEVT) Channel 4 Software Selection Mask */ 137 #define EVSYS_SWEVT_CHANNEL4(value) (EVSYS_SWEVT_CHANNEL4_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL4_Pos)) /* Assigment of value for CHANNEL4 in the EVSYS_SWEVT register */ 138 #define EVSYS_SWEVT_CHANNEL5_Pos _UINT32_(5) /* (EVSYS_SWEVT) Channel 5 Software Selection Position */ 139 #define EVSYS_SWEVT_CHANNEL5_Msk (_UINT32_(0x1) << EVSYS_SWEVT_CHANNEL5_Pos) /* (EVSYS_SWEVT) Channel 5 Software Selection Mask */ 140 #define EVSYS_SWEVT_CHANNEL5(value) (EVSYS_SWEVT_CHANNEL5_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL5_Pos)) /* Assigment of value for CHANNEL5 in the EVSYS_SWEVT register */ 141 #define EVSYS_SWEVT_CHANNEL6_Pos _UINT32_(6) /* (EVSYS_SWEVT) Channel 6 Software Selection Position */ 142 #define EVSYS_SWEVT_CHANNEL6_Msk (_UINT32_(0x1) << EVSYS_SWEVT_CHANNEL6_Pos) /* (EVSYS_SWEVT) Channel 6 Software Selection Mask */ 143 #define EVSYS_SWEVT_CHANNEL6(value) (EVSYS_SWEVT_CHANNEL6_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL6_Pos)) /* Assigment of value for CHANNEL6 in the EVSYS_SWEVT register */ 144 #define EVSYS_SWEVT_CHANNEL7_Pos _UINT32_(7) /* (EVSYS_SWEVT) Channel 7 Software Selection Position */ 145 #define EVSYS_SWEVT_CHANNEL7_Msk (_UINT32_(0x1) << EVSYS_SWEVT_CHANNEL7_Pos) /* (EVSYS_SWEVT) Channel 7 Software Selection Mask */ 146 #define EVSYS_SWEVT_CHANNEL7(value) (EVSYS_SWEVT_CHANNEL7_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL7_Pos)) /* Assigment of value for CHANNEL7 in the EVSYS_SWEVT register */ 147 #define EVSYS_SWEVT_CHANNEL8_Pos _UINT32_(8) /* (EVSYS_SWEVT) Channel 8 Software Selection Position */ 148 #define EVSYS_SWEVT_CHANNEL8_Msk (_UINT32_(0x1) << EVSYS_SWEVT_CHANNEL8_Pos) /* (EVSYS_SWEVT) Channel 8 Software Selection Mask */ 149 #define EVSYS_SWEVT_CHANNEL8(value) (EVSYS_SWEVT_CHANNEL8_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL8_Pos)) /* Assigment of value for CHANNEL8 in the EVSYS_SWEVT register */ 150 #define EVSYS_SWEVT_CHANNEL9_Pos _UINT32_(9) /* (EVSYS_SWEVT) Channel 9 Software Selection Position */ 151 #define EVSYS_SWEVT_CHANNEL9_Msk (_UINT32_(0x1) << EVSYS_SWEVT_CHANNEL9_Pos) /* (EVSYS_SWEVT) Channel 9 Software Selection Mask */ 152 #define EVSYS_SWEVT_CHANNEL9(value) (EVSYS_SWEVT_CHANNEL9_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL9_Pos)) /* Assigment of value for CHANNEL9 in the EVSYS_SWEVT register */ 153 #define EVSYS_SWEVT_CHANNEL10_Pos _UINT32_(10) /* (EVSYS_SWEVT) Channel 10 Software Selection Position */ 154 #define EVSYS_SWEVT_CHANNEL10_Msk (_UINT32_(0x1) << EVSYS_SWEVT_CHANNEL10_Pos) /* (EVSYS_SWEVT) Channel 10 Software Selection Mask */ 155 #define EVSYS_SWEVT_CHANNEL10(value) (EVSYS_SWEVT_CHANNEL10_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL10_Pos)) /* Assigment of value for CHANNEL10 in the EVSYS_SWEVT register */ 156 #define EVSYS_SWEVT_CHANNEL11_Pos _UINT32_(11) /* (EVSYS_SWEVT) Channel 11 Software Selection Position */ 157 #define EVSYS_SWEVT_CHANNEL11_Msk (_UINT32_(0x1) << EVSYS_SWEVT_CHANNEL11_Pos) /* (EVSYS_SWEVT) Channel 11 Software Selection Mask */ 158 #define EVSYS_SWEVT_CHANNEL11(value) (EVSYS_SWEVT_CHANNEL11_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL11_Pos)) /* Assigment of value for CHANNEL11 in the EVSYS_SWEVT register */ 159 #define EVSYS_SWEVT_CHANNEL12_Pos _UINT32_(12) /* (EVSYS_SWEVT) Channel 12 Software Selection Position */ 160 #define EVSYS_SWEVT_CHANNEL12_Msk (_UINT32_(0x1) << EVSYS_SWEVT_CHANNEL12_Pos) /* (EVSYS_SWEVT) Channel 12 Software Selection Mask */ 161 #define EVSYS_SWEVT_CHANNEL12(value) (EVSYS_SWEVT_CHANNEL12_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL12_Pos)) /* Assigment of value for CHANNEL12 in the EVSYS_SWEVT register */ 162 #define EVSYS_SWEVT_CHANNEL13_Pos _UINT32_(13) /* (EVSYS_SWEVT) Channel 13 Software Selection Position */ 163 #define EVSYS_SWEVT_CHANNEL13_Msk (_UINT32_(0x1) << EVSYS_SWEVT_CHANNEL13_Pos) /* (EVSYS_SWEVT) Channel 13 Software Selection Mask */ 164 #define EVSYS_SWEVT_CHANNEL13(value) (EVSYS_SWEVT_CHANNEL13_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL13_Pos)) /* Assigment of value for CHANNEL13 in the EVSYS_SWEVT register */ 165 #define EVSYS_SWEVT_CHANNEL14_Pos _UINT32_(14) /* (EVSYS_SWEVT) Channel 14 Software Selection Position */ 166 #define EVSYS_SWEVT_CHANNEL14_Msk (_UINT32_(0x1) << EVSYS_SWEVT_CHANNEL14_Pos) /* (EVSYS_SWEVT) Channel 14 Software Selection Mask */ 167 #define EVSYS_SWEVT_CHANNEL14(value) (EVSYS_SWEVT_CHANNEL14_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL14_Pos)) /* Assigment of value for CHANNEL14 in the EVSYS_SWEVT register */ 168 #define EVSYS_SWEVT_CHANNEL15_Pos _UINT32_(15) /* (EVSYS_SWEVT) Channel 15 Software Selection Position */ 169 #define EVSYS_SWEVT_CHANNEL15_Msk (_UINT32_(0x1) << EVSYS_SWEVT_CHANNEL15_Pos) /* (EVSYS_SWEVT) Channel 15 Software Selection Mask */ 170 #define EVSYS_SWEVT_CHANNEL15(value) (EVSYS_SWEVT_CHANNEL15_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL15_Pos)) /* Assigment of value for CHANNEL15 in the EVSYS_SWEVT register */ 171 #define EVSYS_SWEVT_CHANNEL16_Pos _UINT32_(16) /* (EVSYS_SWEVT) Channel 16 Software Selection Position */ 172 #define EVSYS_SWEVT_CHANNEL16_Msk (_UINT32_(0x1) << EVSYS_SWEVT_CHANNEL16_Pos) /* (EVSYS_SWEVT) Channel 16 Software Selection Mask */ 173 #define EVSYS_SWEVT_CHANNEL16(value) (EVSYS_SWEVT_CHANNEL16_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL16_Pos)) /* Assigment of value for CHANNEL16 in the EVSYS_SWEVT register */ 174 #define EVSYS_SWEVT_CHANNEL17_Pos _UINT32_(17) /* (EVSYS_SWEVT) Channel 17 Software Selection Position */ 175 #define EVSYS_SWEVT_CHANNEL17_Msk (_UINT32_(0x1) << EVSYS_SWEVT_CHANNEL17_Pos) /* (EVSYS_SWEVT) Channel 17 Software Selection Mask */ 176 #define EVSYS_SWEVT_CHANNEL17(value) (EVSYS_SWEVT_CHANNEL17_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL17_Pos)) /* Assigment of value for CHANNEL17 in the EVSYS_SWEVT register */ 177 #define EVSYS_SWEVT_CHANNEL18_Pos _UINT32_(18) /* (EVSYS_SWEVT) Channel 18 Software Selection Position */ 178 #define EVSYS_SWEVT_CHANNEL18_Msk (_UINT32_(0x1) << EVSYS_SWEVT_CHANNEL18_Pos) /* (EVSYS_SWEVT) Channel 18 Software Selection Mask */ 179 #define EVSYS_SWEVT_CHANNEL18(value) (EVSYS_SWEVT_CHANNEL18_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL18_Pos)) /* Assigment of value for CHANNEL18 in the EVSYS_SWEVT register */ 180 #define EVSYS_SWEVT_CHANNEL19_Pos _UINT32_(19) /* (EVSYS_SWEVT) Channel 19 Software Selection Position */ 181 #define EVSYS_SWEVT_CHANNEL19_Msk (_UINT32_(0x1) << EVSYS_SWEVT_CHANNEL19_Pos) /* (EVSYS_SWEVT) Channel 19 Software Selection Mask */ 182 #define EVSYS_SWEVT_CHANNEL19(value) (EVSYS_SWEVT_CHANNEL19_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL19_Pos)) /* Assigment of value for CHANNEL19 in the EVSYS_SWEVT register */ 183 #define EVSYS_SWEVT_CHANNEL20_Pos _UINT32_(20) /* (EVSYS_SWEVT) Channel 20 Software Selection Position */ 184 #define EVSYS_SWEVT_CHANNEL20_Msk (_UINT32_(0x1) << EVSYS_SWEVT_CHANNEL20_Pos) /* (EVSYS_SWEVT) Channel 20 Software Selection Mask */ 185 #define EVSYS_SWEVT_CHANNEL20(value) (EVSYS_SWEVT_CHANNEL20_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL20_Pos)) /* Assigment of value for CHANNEL20 in the EVSYS_SWEVT register */ 186 #define EVSYS_SWEVT_CHANNEL21_Pos _UINT32_(21) /* (EVSYS_SWEVT) Channel 21 Software Selection Position */ 187 #define EVSYS_SWEVT_CHANNEL21_Msk (_UINT32_(0x1) << EVSYS_SWEVT_CHANNEL21_Pos) /* (EVSYS_SWEVT) Channel 21 Software Selection Mask */ 188 #define EVSYS_SWEVT_CHANNEL21(value) (EVSYS_SWEVT_CHANNEL21_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL21_Pos)) /* Assigment of value for CHANNEL21 in the EVSYS_SWEVT register */ 189 #define EVSYS_SWEVT_CHANNEL22_Pos _UINT32_(22) /* (EVSYS_SWEVT) Channel 22 Software Selection Position */ 190 #define EVSYS_SWEVT_CHANNEL22_Msk (_UINT32_(0x1) << EVSYS_SWEVT_CHANNEL22_Pos) /* (EVSYS_SWEVT) Channel 22 Software Selection Mask */ 191 #define EVSYS_SWEVT_CHANNEL22(value) (EVSYS_SWEVT_CHANNEL22_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL22_Pos)) /* Assigment of value for CHANNEL22 in the EVSYS_SWEVT register */ 192 #define EVSYS_SWEVT_CHANNEL23_Pos _UINT32_(23) /* (EVSYS_SWEVT) Channel 23 Software Selection Position */ 193 #define EVSYS_SWEVT_CHANNEL23_Msk (_UINT32_(0x1) << EVSYS_SWEVT_CHANNEL23_Pos) /* (EVSYS_SWEVT) Channel 23 Software Selection Mask */ 194 #define EVSYS_SWEVT_CHANNEL23(value) (EVSYS_SWEVT_CHANNEL23_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL23_Pos)) /* Assigment of value for CHANNEL23 in the EVSYS_SWEVT register */ 195 #define EVSYS_SWEVT_CHANNEL24_Pos _UINT32_(24) /* (EVSYS_SWEVT) Channel 24 Software Selection Position */ 196 #define EVSYS_SWEVT_CHANNEL24_Msk (_UINT32_(0x1) << EVSYS_SWEVT_CHANNEL24_Pos) /* (EVSYS_SWEVT) Channel 24 Software Selection Mask */ 197 #define EVSYS_SWEVT_CHANNEL24(value) (EVSYS_SWEVT_CHANNEL24_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL24_Pos)) /* Assigment of value for CHANNEL24 in the EVSYS_SWEVT register */ 198 #define EVSYS_SWEVT_CHANNEL25_Pos _UINT32_(25) /* (EVSYS_SWEVT) Channel 25 Software Selection Position */ 199 #define EVSYS_SWEVT_CHANNEL25_Msk (_UINT32_(0x1) << EVSYS_SWEVT_CHANNEL25_Pos) /* (EVSYS_SWEVT) Channel 25 Software Selection Mask */ 200 #define EVSYS_SWEVT_CHANNEL25(value) (EVSYS_SWEVT_CHANNEL25_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL25_Pos)) /* Assigment of value for CHANNEL25 in the EVSYS_SWEVT register */ 201 #define EVSYS_SWEVT_CHANNEL26_Pos _UINT32_(26) /* (EVSYS_SWEVT) Channel 26 Software Selection Position */ 202 #define EVSYS_SWEVT_CHANNEL26_Msk (_UINT32_(0x1) << EVSYS_SWEVT_CHANNEL26_Pos) /* (EVSYS_SWEVT) Channel 26 Software Selection Mask */ 203 #define EVSYS_SWEVT_CHANNEL26(value) (EVSYS_SWEVT_CHANNEL26_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL26_Pos)) /* Assigment of value for CHANNEL26 in the EVSYS_SWEVT register */ 204 #define EVSYS_SWEVT_CHANNEL27_Pos _UINT32_(27) /* (EVSYS_SWEVT) Channel 27 Software Selection Position */ 205 #define EVSYS_SWEVT_CHANNEL27_Msk (_UINT32_(0x1) << EVSYS_SWEVT_CHANNEL27_Pos) /* (EVSYS_SWEVT) Channel 27 Software Selection Mask */ 206 #define EVSYS_SWEVT_CHANNEL27(value) (EVSYS_SWEVT_CHANNEL27_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL27_Pos)) /* Assigment of value for CHANNEL27 in the EVSYS_SWEVT register */ 207 #define EVSYS_SWEVT_CHANNEL28_Pos _UINT32_(28) /* (EVSYS_SWEVT) Channel 28 Software Selection Position */ 208 #define EVSYS_SWEVT_CHANNEL28_Msk (_UINT32_(0x1) << EVSYS_SWEVT_CHANNEL28_Pos) /* (EVSYS_SWEVT) Channel 28 Software Selection Mask */ 209 #define EVSYS_SWEVT_CHANNEL28(value) (EVSYS_SWEVT_CHANNEL28_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL28_Pos)) /* Assigment of value for CHANNEL28 in the EVSYS_SWEVT register */ 210 #define EVSYS_SWEVT_CHANNEL29_Pos _UINT32_(29) /* (EVSYS_SWEVT) Channel 29 Software Selection Position */ 211 #define EVSYS_SWEVT_CHANNEL29_Msk (_UINT32_(0x1) << EVSYS_SWEVT_CHANNEL29_Pos) /* (EVSYS_SWEVT) Channel 29 Software Selection Mask */ 212 #define EVSYS_SWEVT_CHANNEL29(value) (EVSYS_SWEVT_CHANNEL29_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL29_Pos)) /* Assigment of value for CHANNEL29 in the EVSYS_SWEVT register */ 213 #define EVSYS_SWEVT_CHANNEL30_Pos _UINT32_(30) /* (EVSYS_SWEVT) Channel 30 Software Selection Position */ 214 #define EVSYS_SWEVT_CHANNEL30_Msk (_UINT32_(0x1) << EVSYS_SWEVT_CHANNEL30_Pos) /* (EVSYS_SWEVT) Channel 30 Software Selection Mask */ 215 #define EVSYS_SWEVT_CHANNEL30(value) (EVSYS_SWEVT_CHANNEL30_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL30_Pos)) /* Assigment of value for CHANNEL30 in the EVSYS_SWEVT register */ 216 #define EVSYS_SWEVT_CHANNEL31_Pos _UINT32_(31) /* (EVSYS_SWEVT) Channel 31 Software Selection Position */ 217 #define EVSYS_SWEVT_CHANNEL31_Msk (_UINT32_(0x1) << EVSYS_SWEVT_CHANNEL31_Pos) /* (EVSYS_SWEVT) Channel 31 Software Selection Mask */ 218 #define EVSYS_SWEVT_CHANNEL31(value) (EVSYS_SWEVT_CHANNEL31_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL31_Pos)) /* Assigment of value for CHANNEL31 in the EVSYS_SWEVT register */ 219 #define EVSYS_SWEVT_Msk _UINT32_(0xFFFFFFFF) /* (EVSYS_SWEVT) Register Mask */ 220 221 #define EVSYS_SWEVT_CHANNEL_Pos _UINT32_(0) /* (EVSYS_SWEVT Position) Channel 3x Software Selection */ 222 #define EVSYS_SWEVT_CHANNEL_Msk (_UINT32_(0xFFFFFFFF) << EVSYS_SWEVT_CHANNEL_Pos) /* (EVSYS_SWEVT Mask) CHANNEL */ 223 #define EVSYS_SWEVT_CHANNEL(value) (EVSYS_SWEVT_CHANNEL_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL_Pos)) 224 225 /* -------- EVSYS_PRICTRL : (EVSYS Offset: 0x08) (R/W 8) Priority Control -------- */ 226 #define EVSYS_PRICTRL_RESETVALUE _UINT8_(0x00) /* (EVSYS_PRICTRL) Priority Control Reset Value */ 227 228 #define EVSYS_PRICTRL_PRI_Pos _UINT8_(0) /* (EVSYS_PRICTRL) Channel Priority Number Position */ 229 #define EVSYS_PRICTRL_PRI_Msk (_UINT8_(0xF) << EVSYS_PRICTRL_PRI_Pos) /* (EVSYS_PRICTRL) Channel Priority Number Mask */ 230 #define EVSYS_PRICTRL_PRI(value) (EVSYS_PRICTRL_PRI_Msk & (_UINT8_(value) << EVSYS_PRICTRL_PRI_Pos)) /* Assigment of value for PRI in the EVSYS_PRICTRL register */ 231 #define EVSYS_PRICTRL_RREN_Pos _UINT8_(7) /* (EVSYS_PRICTRL) Round-Robin Scheduling Enable Position */ 232 #define EVSYS_PRICTRL_RREN_Msk (_UINT8_(0x1) << EVSYS_PRICTRL_RREN_Pos) /* (EVSYS_PRICTRL) Round-Robin Scheduling Enable Mask */ 233 #define EVSYS_PRICTRL_RREN(value) (EVSYS_PRICTRL_RREN_Msk & (_UINT8_(value) << EVSYS_PRICTRL_RREN_Pos)) /* Assigment of value for RREN in the EVSYS_PRICTRL register */ 234 #define EVSYS_PRICTRL_Msk _UINT8_(0x8F) /* (EVSYS_PRICTRL) Register Mask */ 235 236 237 /* -------- EVSYS_INTPEND : (EVSYS Offset: 0x10) (R/W 16) Channel Pending Interrupt -------- */ 238 #define EVSYS_INTPEND_RESETVALUE _UINT16_(0x4000) /* (EVSYS_INTPEND) Channel Pending Interrupt Reset Value */ 239 240 #define EVSYS_INTPEND_ID_Pos _UINT16_(0) /* (EVSYS_INTPEND) Channel ID Position */ 241 #define EVSYS_INTPEND_ID_Msk (_UINT16_(0xF) << EVSYS_INTPEND_ID_Pos) /* (EVSYS_INTPEND) Channel ID Mask */ 242 #define EVSYS_INTPEND_ID(value) (EVSYS_INTPEND_ID_Msk & (_UINT16_(value) << EVSYS_INTPEND_ID_Pos)) /* Assigment of value for ID in the EVSYS_INTPEND register */ 243 #define EVSYS_INTPEND_OVR_Pos _UINT16_(8) /* (EVSYS_INTPEND) Channel Overrun Position */ 244 #define EVSYS_INTPEND_OVR_Msk (_UINT16_(0x1) << EVSYS_INTPEND_OVR_Pos) /* (EVSYS_INTPEND) Channel Overrun Mask */ 245 #define EVSYS_INTPEND_OVR(value) (EVSYS_INTPEND_OVR_Msk & (_UINT16_(value) << EVSYS_INTPEND_OVR_Pos)) /* Assigment of value for OVR in the EVSYS_INTPEND register */ 246 #define EVSYS_INTPEND_EVD_Pos _UINT16_(9) /* (EVSYS_INTPEND) Channel Event Detected Position */ 247 #define EVSYS_INTPEND_EVD_Msk (_UINT16_(0x1) << EVSYS_INTPEND_EVD_Pos) /* (EVSYS_INTPEND) Channel Event Detected Mask */ 248 #define EVSYS_INTPEND_EVD(value) (EVSYS_INTPEND_EVD_Msk & (_UINT16_(value) << EVSYS_INTPEND_EVD_Pos)) /* Assigment of value for EVD in the EVSYS_INTPEND register */ 249 #define EVSYS_INTPEND_READY_Pos _UINT16_(14) /* (EVSYS_INTPEND) Ready Position */ 250 #define EVSYS_INTPEND_READY_Msk (_UINT16_(0x1) << EVSYS_INTPEND_READY_Pos) /* (EVSYS_INTPEND) Ready Mask */ 251 #define EVSYS_INTPEND_READY(value) (EVSYS_INTPEND_READY_Msk & (_UINT16_(value) << EVSYS_INTPEND_READY_Pos)) /* Assigment of value for READY in the EVSYS_INTPEND register */ 252 #define EVSYS_INTPEND_BUSY_Pos _UINT16_(15) /* (EVSYS_INTPEND) Busy Position */ 253 #define EVSYS_INTPEND_BUSY_Msk (_UINT16_(0x1) << EVSYS_INTPEND_BUSY_Pos) /* (EVSYS_INTPEND) Busy Mask */ 254 #define EVSYS_INTPEND_BUSY(value) (EVSYS_INTPEND_BUSY_Msk & (_UINT16_(value) << EVSYS_INTPEND_BUSY_Pos)) /* Assigment of value for BUSY in the EVSYS_INTPEND register */ 255 #define EVSYS_INTPEND_Msk _UINT16_(0xC30F) /* (EVSYS_INTPEND) Register Mask */ 256 257 258 /* -------- EVSYS_INTSTATUS : (EVSYS Offset: 0x14) ( R/ 32) Interrupt Status -------- */ 259 #define EVSYS_INTSTATUS_RESETVALUE _UINT32_(0x00) /* (EVSYS_INTSTATUS) Interrupt Status Reset Value */ 260 261 #define EVSYS_INTSTATUS_CHINT0_Pos _UINT32_(0) /* (EVSYS_INTSTATUS) Channel 0 Pending Interrupt Position */ 262 #define EVSYS_INTSTATUS_CHINT0_Msk (_UINT32_(0x1) << EVSYS_INTSTATUS_CHINT0_Pos) /* (EVSYS_INTSTATUS) Channel 0 Pending Interrupt Mask */ 263 #define EVSYS_INTSTATUS_CHINT0(value) (EVSYS_INTSTATUS_CHINT0_Msk & (_UINT32_(value) << EVSYS_INTSTATUS_CHINT0_Pos)) /* Assigment of value for CHINT0 in the EVSYS_INTSTATUS register */ 264 #define EVSYS_INTSTATUS_CHINT1_Pos _UINT32_(1) /* (EVSYS_INTSTATUS) Channel 1 Pending Interrupt Position */ 265 #define EVSYS_INTSTATUS_CHINT1_Msk (_UINT32_(0x1) << EVSYS_INTSTATUS_CHINT1_Pos) /* (EVSYS_INTSTATUS) Channel 1 Pending Interrupt Mask */ 266 #define EVSYS_INTSTATUS_CHINT1(value) (EVSYS_INTSTATUS_CHINT1_Msk & (_UINT32_(value) << EVSYS_INTSTATUS_CHINT1_Pos)) /* Assigment of value for CHINT1 in the EVSYS_INTSTATUS register */ 267 #define EVSYS_INTSTATUS_CHINT2_Pos _UINT32_(2) /* (EVSYS_INTSTATUS) Channel 2 Pending Interrupt Position */ 268 #define EVSYS_INTSTATUS_CHINT2_Msk (_UINT32_(0x1) << EVSYS_INTSTATUS_CHINT2_Pos) /* (EVSYS_INTSTATUS) Channel 2 Pending Interrupt Mask */ 269 #define EVSYS_INTSTATUS_CHINT2(value) (EVSYS_INTSTATUS_CHINT2_Msk & (_UINT32_(value) << EVSYS_INTSTATUS_CHINT2_Pos)) /* Assigment of value for CHINT2 in the EVSYS_INTSTATUS register */ 270 #define EVSYS_INTSTATUS_CHINT3_Pos _UINT32_(3) /* (EVSYS_INTSTATUS) Channel 3 Pending Interrupt Position */ 271 #define EVSYS_INTSTATUS_CHINT3_Msk (_UINT32_(0x1) << EVSYS_INTSTATUS_CHINT3_Pos) /* (EVSYS_INTSTATUS) Channel 3 Pending Interrupt Mask */ 272 #define EVSYS_INTSTATUS_CHINT3(value) (EVSYS_INTSTATUS_CHINT3_Msk & (_UINT32_(value) << EVSYS_INTSTATUS_CHINT3_Pos)) /* Assigment of value for CHINT3 in the EVSYS_INTSTATUS register */ 273 #define EVSYS_INTSTATUS_CHINT4_Pos _UINT32_(4) /* (EVSYS_INTSTATUS) Channel 4 Pending Interrupt Position */ 274 #define EVSYS_INTSTATUS_CHINT4_Msk (_UINT32_(0x1) << EVSYS_INTSTATUS_CHINT4_Pos) /* (EVSYS_INTSTATUS) Channel 4 Pending Interrupt Mask */ 275 #define EVSYS_INTSTATUS_CHINT4(value) (EVSYS_INTSTATUS_CHINT4_Msk & (_UINT32_(value) << EVSYS_INTSTATUS_CHINT4_Pos)) /* Assigment of value for CHINT4 in the EVSYS_INTSTATUS register */ 276 #define EVSYS_INTSTATUS_CHINT5_Pos _UINT32_(5) /* (EVSYS_INTSTATUS) Channel 5 Pending Interrupt Position */ 277 #define EVSYS_INTSTATUS_CHINT5_Msk (_UINT32_(0x1) << EVSYS_INTSTATUS_CHINT5_Pos) /* (EVSYS_INTSTATUS) Channel 5 Pending Interrupt Mask */ 278 #define EVSYS_INTSTATUS_CHINT5(value) (EVSYS_INTSTATUS_CHINT5_Msk & (_UINT32_(value) << EVSYS_INTSTATUS_CHINT5_Pos)) /* Assigment of value for CHINT5 in the EVSYS_INTSTATUS register */ 279 #define EVSYS_INTSTATUS_CHINT6_Pos _UINT32_(6) /* (EVSYS_INTSTATUS) Channel 6 Pending Interrupt Position */ 280 #define EVSYS_INTSTATUS_CHINT6_Msk (_UINT32_(0x1) << EVSYS_INTSTATUS_CHINT6_Pos) /* (EVSYS_INTSTATUS) Channel 6 Pending Interrupt Mask */ 281 #define EVSYS_INTSTATUS_CHINT6(value) (EVSYS_INTSTATUS_CHINT6_Msk & (_UINT32_(value) << EVSYS_INTSTATUS_CHINT6_Pos)) /* Assigment of value for CHINT6 in the EVSYS_INTSTATUS register */ 282 #define EVSYS_INTSTATUS_CHINT7_Pos _UINT32_(7) /* (EVSYS_INTSTATUS) Channel 7 Pending Interrupt Position */ 283 #define EVSYS_INTSTATUS_CHINT7_Msk (_UINT32_(0x1) << EVSYS_INTSTATUS_CHINT7_Pos) /* (EVSYS_INTSTATUS) Channel 7 Pending Interrupt Mask */ 284 #define EVSYS_INTSTATUS_CHINT7(value) (EVSYS_INTSTATUS_CHINT7_Msk & (_UINT32_(value) << EVSYS_INTSTATUS_CHINT7_Pos)) /* Assigment of value for CHINT7 in the EVSYS_INTSTATUS register */ 285 #define EVSYS_INTSTATUS_CHINT8_Pos _UINT32_(8) /* (EVSYS_INTSTATUS) Channel 8 Pending Interrupt Position */ 286 #define EVSYS_INTSTATUS_CHINT8_Msk (_UINT32_(0x1) << EVSYS_INTSTATUS_CHINT8_Pos) /* (EVSYS_INTSTATUS) Channel 8 Pending Interrupt Mask */ 287 #define EVSYS_INTSTATUS_CHINT8(value) (EVSYS_INTSTATUS_CHINT8_Msk & (_UINT32_(value) << EVSYS_INTSTATUS_CHINT8_Pos)) /* Assigment of value for CHINT8 in the EVSYS_INTSTATUS register */ 288 #define EVSYS_INTSTATUS_CHINT9_Pos _UINT32_(9) /* (EVSYS_INTSTATUS) Channel 9 Pending Interrupt Position */ 289 #define EVSYS_INTSTATUS_CHINT9_Msk (_UINT32_(0x1) << EVSYS_INTSTATUS_CHINT9_Pos) /* (EVSYS_INTSTATUS) Channel 9 Pending Interrupt Mask */ 290 #define EVSYS_INTSTATUS_CHINT9(value) (EVSYS_INTSTATUS_CHINT9_Msk & (_UINT32_(value) << EVSYS_INTSTATUS_CHINT9_Pos)) /* Assigment of value for CHINT9 in the EVSYS_INTSTATUS register */ 291 #define EVSYS_INTSTATUS_CHINT10_Pos _UINT32_(10) /* (EVSYS_INTSTATUS) Channel 10 Pending Interrupt Position */ 292 #define EVSYS_INTSTATUS_CHINT10_Msk (_UINT32_(0x1) << EVSYS_INTSTATUS_CHINT10_Pos) /* (EVSYS_INTSTATUS) Channel 10 Pending Interrupt Mask */ 293 #define EVSYS_INTSTATUS_CHINT10(value) (EVSYS_INTSTATUS_CHINT10_Msk & (_UINT32_(value) << EVSYS_INTSTATUS_CHINT10_Pos)) /* Assigment of value for CHINT10 in the EVSYS_INTSTATUS register */ 294 #define EVSYS_INTSTATUS_CHINT11_Pos _UINT32_(11) /* (EVSYS_INTSTATUS) Channel 11 Pending Interrupt Position */ 295 #define EVSYS_INTSTATUS_CHINT11_Msk (_UINT32_(0x1) << EVSYS_INTSTATUS_CHINT11_Pos) /* (EVSYS_INTSTATUS) Channel 11 Pending Interrupt Mask */ 296 #define EVSYS_INTSTATUS_CHINT11(value) (EVSYS_INTSTATUS_CHINT11_Msk & (_UINT32_(value) << EVSYS_INTSTATUS_CHINT11_Pos)) /* Assigment of value for CHINT11 in the EVSYS_INTSTATUS register */ 297 #define EVSYS_INTSTATUS_Msk _UINT32_(0x00000FFF) /* (EVSYS_INTSTATUS) Register Mask */ 298 299 #define EVSYS_INTSTATUS_CHINT_Pos _UINT32_(0) /* (EVSYS_INTSTATUS Position) Channel xx Pending Interrupt */ 300 #define EVSYS_INTSTATUS_CHINT_Msk (_UINT32_(0xFFF) << EVSYS_INTSTATUS_CHINT_Pos) /* (EVSYS_INTSTATUS Mask) CHINT */ 301 #define EVSYS_INTSTATUS_CHINT(value) (EVSYS_INTSTATUS_CHINT_Msk & (_UINT32_(value) << EVSYS_INTSTATUS_CHINT_Pos)) 302 303 /* -------- EVSYS_BUSYCH : (EVSYS Offset: 0x18) ( R/ 32) Busy Channels -------- */ 304 #define EVSYS_BUSYCH_RESETVALUE _UINT32_(0x00) /* (EVSYS_BUSYCH) Busy Channels Reset Value */ 305 306 #define EVSYS_BUSYCH_BUSYCH0_Pos _UINT32_(0) /* (EVSYS_BUSYCH) Busy Channel 0 Position */ 307 #define EVSYS_BUSYCH_BUSYCH0_Msk (_UINT32_(0x1) << EVSYS_BUSYCH_BUSYCH0_Pos) /* (EVSYS_BUSYCH) Busy Channel 0 Mask */ 308 #define EVSYS_BUSYCH_BUSYCH0(value) (EVSYS_BUSYCH_BUSYCH0_Msk & (_UINT32_(value) << EVSYS_BUSYCH_BUSYCH0_Pos)) /* Assigment of value for BUSYCH0 in the EVSYS_BUSYCH register */ 309 #define EVSYS_BUSYCH_BUSYCH1_Pos _UINT32_(1) /* (EVSYS_BUSYCH) Busy Channel 1 Position */ 310 #define EVSYS_BUSYCH_BUSYCH1_Msk (_UINT32_(0x1) << EVSYS_BUSYCH_BUSYCH1_Pos) /* (EVSYS_BUSYCH) Busy Channel 1 Mask */ 311 #define EVSYS_BUSYCH_BUSYCH1(value) (EVSYS_BUSYCH_BUSYCH1_Msk & (_UINT32_(value) << EVSYS_BUSYCH_BUSYCH1_Pos)) /* Assigment of value for BUSYCH1 in the EVSYS_BUSYCH register */ 312 #define EVSYS_BUSYCH_BUSYCH2_Pos _UINT32_(2) /* (EVSYS_BUSYCH) Busy Channel 2 Position */ 313 #define EVSYS_BUSYCH_BUSYCH2_Msk (_UINT32_(0x1) << EVSYS_BUSYCH_BUSYCH2_Pos) /* (EVSYS_BUSYCH) Busy Channel 2 Mask */ 314 #define EVSYS_BUSYCH_BUSYCH2(value) (EVSYS_BUSYCH_BUSYCH2_Msk & (_UINT32_(value) << EVSYS_BUSYCH_BUSYCH2_Pos)) /* Assigment of value for BUSYCH2 in the EVSYS_BUSYCH register */ 315 #define EVSYS_BUSYCH_BUSYCH3_Pos _UINT32_(3) /* (EVSYS_BUSYCH) Busy Channel 3 Position */ 316 #define EVSYS_BUSYCH_BUSYCH3_Msk (_UINT32_(0x1) << EVSYS_BUSYCH_BUSYCH3_Pos) /* (EVSYS_BUSYCH) Busy Channel 3 Mask */ 317 #define EVSYS_BUSYCH_BUSYCH3(value) (EVSYS_BUSYCH_BUSYCH3_Msk & (_UINT32_(value) << EVSYS_BUSYCH_BUSYCH3_Pos)) /* Assigment of value for BUSYCH3 in the EVSYS_BUSYCH register */ 318 #define EVSYS_BUSYCH_BUSYCH4_Pos _UINT32_(4) /* (EVSYS_BUSYCH) Busy Channel 4 Position */ 319 #define EVSYS_BUSYCH_BUSYCH4_Msk (_UINT32_(0x1) << EVSYS_BUSYCH_BUSYCH4_Pos) /* (EVSYS_BUSYCH) Busy Channel 4 Mask */ 320 #define EVSYS_BUSYCH_BUSYCH4(value) (EVSYS_BUSYCH_BUSYCH4_Msk & (_UINT32_(value) << EVSYS_BUSYCH_BUSYCH4_Pos)) /* Assigment of value for BUSYCH4 in the EVSYS_BUSYCH register */ 321 #define EVSYS_BUSYCH_BUSYCH5_Pos _UINT32_(5) /* (EVSYS_BUSYCH) Busy Channel 5 Position */ 322 #define EVSYS_BUSYCH_BUSYCH5_Msk (_UINT32_(0x1) << EVSYS_BUSYCH_BUSYCH5_Pos) /* (EVSYS_BUSYCH) Busy Channel 5 Mask */ 323 #define EVSYS_BUSYCH_BUSYCH5(value) (EVSYS_BUSYCH_BUSYCH5_Msk & (_UINT32_(value) << EVSYS_BUSYCH_BUSYCH5_Pos)) /* Assigment of value for BUSYCH5 in the EVSYS_BUSYCH register */ 324 #define EVSYS_BUSYCH_BUSYCH6_Pos _UINT32_(6) /* (EVSYS_BUSYCH) Busy Channel 6 Position */ 325 #define EVSYS_BUSYCH_BUSYCH6_Msk (_UINT32_(0x1) << EVSYS_BUSYCH_BUSYCH6_Pos) /* (EVSYS_BUSYCH) Busy Channel 6 Mask */ 326 #define EVSYS_BUSYCH_BUSYCH6(value) (EVSYS_BUSYCH_BUSYCH6_Msk & (_UINT32_(value) << EVSYS_BUSYCH_BUSYCH6_Pos)) /* Assigment of value for BUSYCH6 in the EVSYS_BUSYCH register */ 327 #define EVSYS_BUSYCH_BUSYCH7_Pos _UINT32_(7) /* (EVSYS_BUSYCH) Busy Channel 7 Position */ 328 #define EVSYS_BUSYCH_BUSYCH7_Msk (_UINT32_(0x1) << EVSYS_BUSYCH_BUSYCH7_Pos) /* (EVSYS_BUSYCH) Busy Channel 7 Mask */ 329 #define EVSYS_BUSYCH_BUSYCH7(value) (EVSYS_BUSYCH_BUSYCH7_Msk & (_UINT32_(value) << EVSYS_BUSYCH_BUSYCH7_Pos)) /* Assigment of value for BUSYCH7 in the EVSYS_BUSYCH register */ 330 #define EVSYS_BUSYCH_BUSYCH8_Pos _UINT32_(8) /* (EVSYS_BUSYCH) Busy Channel 8 Position */ 331 #define EVSYS_BUSYCH_BUSYCH8_Msk (_UINT32_(0x1) << EVSYS_BUSYCH_BUSYCH8_Pos) /* (EVSYS_BUSYCH) Busy Channel 8 Mask */ 332 #define EVSYS_BUSYCH_BUSYCH8(value) (EVSYS_BUSYCH_BUSYCH8_Msk & (_UINT32_(value) << EVSYS_BUSYCH_BUSYCH8_Pos)) /* Assigment of value for BUSYCH8 in the EVSYS_BUSYCH register */ 333 #define EVSYS_BUSYCH_BUSYCH9_Pos _UINT32_(9) /* (EVSYS_BUSYCH) Busy Channel 9 Position */ 334 #define EVSYS_BUSYCH_BUSYCH9_Msk (_UINT32_(0x1) << EVSYS_BUSYCH_BUSYCH9_Pos) /* (EVSYS_BUSYCH) Busy Channel 9 Mask */ 335 #define EVSYS_BUSYCH_BUSYCH9(value) (EVSYS_BUSYCH_BUSYCH9_Msk & (_UINT32_(value) << EVSYS_BUSYCH_BUSYCH9_Pos)) /* Assigment of value for BUSYCH9 in the EVSYS_BUSYCH register */ 336 #define EVSYS_BUSYCH_BUSYCH10_Pos _UINT32_(10) /* (EVSYS_BUSYCH) Busy Channel 10 Position */ 337 #define EVSYS_BUSYCH_BUSYCH10_Msk (_UINT32_(0x1) << EVSYS_BUSYCH_BUSYCH10_Pos) /* (EVSYS_BUSYCH) Busy Channel 10 Mask */ 338 #define EVSYS_BUSYCH_BUSYCH10(value) (EVSYS_BUSYCH_BUSYCH10_Msk & (_UINT32_(value) << EVSYS_BUSYCH_BUSYCH10_Pos)) /* Assigment of value for BUSYCH10 in the EVSYS_BUSYCH register */ 339 #define EVSYS_BUSYCH_BUSYCH11_Pos _UINT32_(11) /* (EVSYS_BUSYCH) Busy Channel 11 Position */ 340 #define EVSYS_BUSYCH_BUSYCH11_Msk (_UINT32_(0x1) << EVSYS_BUSYCH_BUSYCH11_Pos) /* (EVSYS_BUSYCH) Busy Channel 11 Mask */ 341 #define EVSYS_BUSYCH_BUSYCH11(value) (EVSYS_BUSYCH_BUSYCH11_Msk & (_UINT32_(value) << EVSYS_BUSYCH_BUSYCH11_Pos)) /* Assigment of value for BUSYCH11 in the EVSYS_BUSYCH register */ 342 #define EVSYS_BUSYCH_Msk _UINT32_(0x00000FFF) /* (EVSYS_BUSYCH) Register Mask */ 343 344 #define EVSYS_BUSYCH_BUSYCH_Pos _UINT32_(0) /* (EVSYS_BUSYCH Position) Busy Channel xx */ 345 #define EVSYS_BUSYCH_BUSYCH_Msk (_UINT32_(0xFFF) << EVSYS_BUSYCH_BUSYCH_Pos) /* (EVSYS_BUSYCH Mask) BUSYCH */ 346 #define EVSYS_BUSYCH_BUSYCH(value) (EVSYS_BUSYCH_BUSYCH_Msk & (_UINT32_(value) << EVSYS_BUSYCH_BUSYCH_Pos)) 347 348 /* -------- EVSYS_READYUSR : (EVSYS Offset: 0x1C) ( R/ 32) Ready Users -------- */ 349 #define EVSYS_READYUSR_RESETVALUE _UINT32_(0xFFFFFFFF) /* (EVSYS_READYUSR) Ready Users Reset Value */ 350 351 #define EVSYS_READYUSR_READYUSR0_Pos _UINT32_(0) /* (EVSYS_READYUSR) Ready User for Channel 0 Position */ 352 #define EVSYS_READYUSR_READYUSR0_Msk (_UINT32_(0x1) << EVSYS_READYUSR_READYUSR0_Pos) /* (EVSYS_READYUSR) Ready User for Channel 0 Mask */ 353 #define EVSYS_READYUSR_READYUSR0(value) (EVSYS_READYUSR_READYUSR0_Msk & (_UINT32_(value) << EVSYS_READYUSR_READYUSR0_Pos)) /* Assigment of value for READYUSR0 in the EVSYS_READYUSR register */ 354 #define EVSYS_READYUSR_READYUSR1_Pos _UINT32_(1) /* (EVSYS_READYUSR) Ready User for Channel 1 Position */ 355 #define EVSYS_READYUSR_READYUSR1_Msk (_UINT32_(0x1) << EVSYS_READYUSR_READYUSR1_Pos) /* (EVSYS_READYUSR) Ready User for Channel 1 Mask */ 356 #define EVSYS_READYUSR_READYUSR1(value) (EVSYS_READYUSR_READYUSR1_Msk & (_UINT32_(value) << EVSYS_READYUSR_READYUSR1_Pos)) /* Assigment of value for READYUSR1 in the EVSYS_READYUSR register */ 357 #define EVSYS_READYUSR_READYUSR2_Pos _UINT32_(2) /* (EVSYS_READYUSR) Ready User for Channel 2 Position */ 358 #define EVSYS_READYUSR_READYUSR2_Msk (_UINT32_(0x1) << EVSYS_READYUSR_READYUSR2_Pos) /* (EVSYS_READYUSR) Ready User for Channel 2 Mask */ 359 #define EVSYS_READYUSR_READYUSR2(value) (EVSYS_READYUSR_READYUSR2_Msk & (_UINT32_(value) << EVSYS_READYUSR_READYUSR2_Pos)) /* Assigment of value for READYUSR2 in the EVSYS_READYUSR register */ 360 #define EVSYS_READYUSR_READYUSR3_Pos _UINT32_(3) /* (EVSYS_READYUSR) Ready User for Channel 3 Position */ 361 #define EVSYS_READYUSR_READYUSR3_Msk (_UINT32_(0x1) << EVSYS_READYUSR_READYUSR3_Pos) /* (EVSYS_READYUSR) Ready User for Channel 3 Mask */ 362 #define EVSYS_READYUSR_READYUSR3(value) (EVSYS_READYUSR_READYUSR3_Msk & (_UINT32_(value) << EVSYS_READYUSR_READYUSR3_Pos)) /* Assigment of value for READYUSR3 in the EVSYS_READYUSR register */ 363 #define EVSYS_READYUSR_READYUSR4_Pos _UINT32_(4) /* (EVSYS_READYUSR) Ready User for Channel 4 Position */ 364 #define EVSYS_READYUSR_READYUSR4_Msk (_UINT32_(0x1) << EVSYS_READYUSR_READYUSR4_Pos) /* (EVSYS_READYUSR) Ready User for Channel 4 Mask */ 365 #define EVSYS_READYUSR_READYUSR4(value) (EVSYS_READYUSR_READYUSR4_Msk & (_UINT32_(value) << EVSYS_READYUSR_READYUSR4_Pos)) /* Assigment of value for READYUSR4 in the EVSYS_READYUSR register */ 366 #define EVSYS_READYUSR_READYUSR5_Pos _UINT32_(5) /* (EVSYS_READYUSR) Ready User for Channel 5 Position */ 367 #define EVSYS_READYUSR_READYUSR5_Msk (_UINT32_(0x1) << EVSYS_READYUSR_READYUSR5_Pos) /* (EVSYS_READYUSR) Ready User for Channel 5 Mask */ 368 #define EVSYS_READYUSR_READYUSR5(value) (EVSYS_READYUSR_READYUSR5_Msk & (_UINT32_(value) << EVSYS_READYUSR_READYUSR5_Pos)) /* Assigment of value for READYUSR5 in the EVSYS_READYUSR register */ 369 #define EVSYS_READYUSR_READYUSR6_Pos _UINT32_(6) /* (EVSYS_READYUSR) Ready User for Channel 6 Position */ 370 #define EVSYS_READYUSR_READYUSR6_Msk (_UINT32_(0x1) << EVSYS_READYUSR_READYUSR6_Pos) /* (EVSYS_READYUSR) Ready User for Channel 6 Mask */ 371 #define EVSYS_READYUSR_READYUSR6(value) (EVSYS_READYUSR_READYUSR6_Msk & (_UINT32_(value) << EVSYS_READYUSR_READYUSR6_Pos)) /* Assigment of value for READYUSR6 in the EVSYS_READYUSR register */ 372 #define EVSYS_READYUSR_READYUSR7_Pos _UINT32_(7) /* (EVSYS_READYUSR) Ready User for Channel 7 Position */ 373 #define EVSYS_READYUSR_READYUSR7_Msk (_UINT32_(0x1) << EVSYS_READYUSR_READYUSR7_Pos) /* (EVSYS_READYUSR) Ready User for Channel 7 Mask */ 374 #define EVSYS_READYUSR_READYUSR7(value) (EVSYS_READYUSR_READYUSR7_Msk & (_UINT32_(value) << EVSYS_READYUSR_READYUSR7_Pos)) /* Assigment of value for READYUSR7 in the EVSYS_READYUSR register */ 375 #define EVSYS_READYUSR_READYUSR8_Pos _UINT32_(8) /* (EVSYS_READYUSR) Ready User for Channel 8 Position */ 376 #define EVSYS_READYUSR_READYUSR8_Msk (_UINT32_(0x1) << EVSYS_READYUSR_READYUSR8_Pos) /* (EVSYS_READYUSR) Ready User for Channel 8 Mask */ 377 #define EVSYS_READYUSR_READYUSR8(value) (EVSYS_READYUSR_READYUSR8_Msk & (_UINT32_(value) << EVSYS_READYUSR_READYUSR8_Pos)) /* Assigment of value for READYUSR8 in the EVSYS_READYUSR register */ 378 #define EVSYS_READYUSR_READYUSR9_Pos _UINT32_(9) /* (EVSYS_READYUSR) Ready User for Channel 9 Position */ 379 #define EVSYS_READYUSR_READYUSR9_Msk (_UINT32_(0x1) << EVSYS_READYUSR_READYUSR9_Pos) /* (EVSYS_READYUSR) Ready User for Channel 9 Mask */ 380 #define EVSYS_READYUSR_READYUSR9(value) (EVSYS_READYUSR_READYUSR9_Msk & (_UINT32_(value) << EVSYS_READYUSR_READYUSR9_Pos)) /* Assigment of value for READYUSR9 in the EVSYS_READYUSR register */ 381 #define EVSYS_READYUSR_READYUSR10_Pos _UINT32_(10) /* (EVSYS_READYUSR) Ready User for Channel 10 Position */ 382 #define EVSYS_READYUSR_READYUSR10_Msk (_UINT32_(0x1) << EVSYS_READYUSR_READYUSR10_Pos) /* (EVSYS_READYUSR) Ready User for Channel 10 Mask */ 383 #define EVSYS_READYUSR_READYUSR10(value) (EVSYS_READYUSR_READYUSR10_Msk & (_UINT32_(value) << EVSYS_READYUSR_READYUSR10_Pos)) /* Assigment of value for READYUSR10 in the EVSYS_READYUSR register */ 384 #define EVSYS_READYUSR_READYUSR11_Pos _UINT32_(11) /* (EVSYS_READYUSR) Ready User for Channel 11 Position */ 385 #define EVSYS_READYUSR_READYUSR11_Msk (_UINT32_(0x1) << EVSYS_READYUSR_READYUSR11_Pos) /* (EVSYS_READYUSR) Ready User for Channel 11 Mask */ 386 #define EVSYS_READYUSR_READYUSR11(value) (EVSYS_READYUSR_READYUSR11_Msk & (_UINT32_(value) << EVSYS_READYUSR_READYUSR11_Pos)) /* Assigment of value for READYUSR11 in the EVSYS_READYUSR register */ 387 #define EVSYS_READYUSR_Msk _UINT32_(0x00000FFF) /* (EVSYS_READYUSR) Register Mask */ 388 389 #define EVSYS_READYUSR_READYUSR_Pos _UINT32_(0) /* (EVSYS_READYUSR Position) Ready User for Channel xx */ 390 #define EVSYS_READYUSR_READYUSR_Msk (_UINT32_(0xFFF) << EVSYS_READYUSR_READYUSR_Pos) /* (EVSYS_READYUSR Mask) READYUSR */ 391 #define EVSYS_READYUSR_READYUSR(value) (EVSYS_READYUSR_READYUSR_Msk & (_UINT32_(value) << EVSYS_READYUSR_READYUSR_Pos)) 392 393 /* -------- EVSYS_USER : (EVSYS Offset: 0x120) (R/W 32) User Multiplexer n -------- */ 394 #define EVSYS_USER_RESETVALUE _UINT32_(0x00) /* (EVSYS_USER) User Multiplexer n Reset Value */ 395 396 #define EVSYS_USER_CHANNEL_Pos _UINT32_(0) /* (EVSYS_USER) Channel Event Selection Position */ 397 #define EVSYS_USER_CHANNEL_Msk (_UINT32_(0x3F) << EVSYS_USER_CHANNEL_Pos) /* (EVSYS_USER) Channel Event Selection Mask */ 398 #define EVSYS_USER_CHANNEL(value) (EVSYS_USER_CHANNEL_Msk & (_UINT32_(value) << EVSYS_USER_CHANNEL_Pos)) /* Assigment of value for CHANNEL in the EVSYS_USER register */ 399 #define EVSYS_USER_Msk _UINT32_(0x0000003F) /* (EVSYS_USER) Register Mask */ 400 401 402 /** \brief EVSYS register offsets definitions */ 403 #define EVSYS_CHANNEL_REG_OFST _UINT32_(0x00) /* (EVSYS_CHANNEL) Channel n Control Offset */ 404 #define EVSYS_CHINTENCLR_REG_OFST _UINT32_(0x04) /* (EVSYS_CHINTENCLR) Channel n Interrupt Enable Clear Offset */ 405 #define EVSYS_CHINTENSET_REG_OFST _UINT32_(0x05) /* (EVSYS_CHINTENSET) Channel n Interrupt Enable Set Offset */ 406 #define EVSYS_CHINTFLAG_REG_OFST _UINT32_(0x06) /* (EVSYS_CHINTFLAG) Channel n Interrupt Flag Status and Clear Offset */ 407 #define EVSYS_CHSTATUS_REG_OFST _UINT32_(0x07) /* (EVSYS_CHSTATUS) Channel n Status Offset */ 408 #define EVSYS_CTRLA_REG_OFST _UINT32_(0x00) /* (EVSYS_CTRLA) Control Offset */ 409 #define EVSYS_SWEVT_REG_OFST _UINT32_(0x04) /* (EVSYS_SWEVT) Software Event Offset */ 410 #define EVSYS_PRICTRL_REG_OFST _UINT32_(0x08) /* (EVSYS_PRICTRL) Priority Control Offset */ 411 #define EVSYS_INTPEND_REG_OFST _UINT32_(0x10) /* (EVSYS_INTPEND) Channel Pending Interrupt Offset */ 412 #define EVSYS_INTSTATUS_REG_OFST _UINT32_(0x14) /* (EVSYS_INTSTATUS) Interrupt Status Offset */ 413 #define EVSYS_BUSYCH_REG_OFST _UINT32_(0x18) /* (EVSYS_BUSYCH) Busy Channels Offset */ 414 #define EVSYS_READYUSR_REG_OFST _UINT32_(0x1C) /* (EVSYS_READYUSR) Ready Users Offset */ 415 #define EVSYS_USER_REG_OFST _UINT32_(0x120) /* (EVSYS_USER) User Multiplexer n Offset */ 416 #define EVSYS_USER0_REG_OFST _UINT32_(0x120) /* (EVSYS_USER0) User Multiplexer n Offset */ 417 #define EVSYS_USER1_REG_OFST _UINT32_(0x124) /* (EVSYS_USER1) User Multiplexer n Offset */ 418 #define EVSYS_USER2_REG_OFST _UINT32_(0x128) /* (EVSYS_USER2) User Multiplexer n Offset */ 419 #define EVSYS_USER3_REG_OFST _UINT32_(0x12C) /* (EVSYS_USER3) User Multiplexer n Offset */ 420 #define EVSYS_USER4_REG_OFST _UINT32_(0x130) /* (EVSYS_USER4) User Multiplexer n Offset */ 421 #define EVSYS_USER5_REG_OFST _UINT32_(0x134) /* (EVSYS_USER5) User Multiplexer n Offset */ 422 #define EVSYS_USER6_REG_OFST _UINT32_(0x138) /* (EVSYS_USER6) User Multiplexer n Offset */ 423 #define EVSYS_USER7_REG_OFST _UINT32_(0x13C) /* (EVSYS_USER7) User Multiplexer n Offset */ 424 #define EVSYS_USER8_REG_OFST _UINT32_(0x140) /* (EVSYS_USER8) User Multiplexer n Offset */ 425 #define EVSYS_USER9_REG_OFST _UINT32_(0x144) /* (EVSYS_USER9) User Multiplexer n Offset */ 426 #define EVSYS_USER10_REG_OFST _UINT32_(0x148) /* (EVSYS_USER10) User Multiplexer n Offset */ 427 #define EVSYS_USER11_REG_OFST _UINT32_(0x14C) /* (EVSYS_USER11) User Multiplexer n Offset */ 428 #define EVSYS_USER12_REG_OFST _UINT32_(0x150) /* (EVSYS_USER12) User Multiplexer n Offset */ 429 #define EVSYS_USER13_REG_OFST _UINT32_(0x154) /* (EVSYS_USER13) User Multiplexer n Offset */ 430 #define EVSYS_USER14_REG_OFST _UINT32_(0x158) /* (EVSYS_USER14) User Multiplexer n Offset */ 431 #define EVSYS_USER15_REG_OFST _UINT32_(0x15C) /* (EVSYS_USER15) User Multiplexer n Offset */ 432 #define EVSYS_USER16_REG_OFST _UINT32_(0x160) /* (EVSYS_USER16) User Multiplexer n Offset */ 433 #define EVSYS_USER17_REG_OFST _UINT32_(0x164) /* (EVSYS_USER17) User Multiplexer n Offset */ 434 #define EVSYS_USER18_REG_OFST _UINT32_(0x168) /* (EVSYS_USER18) User Multiplexer n Offset */ 435 #define EVSYS_USER19_REG_OFST _UINT32_(0x16C) /* (EVSYS_USER19) User Multiplexer n Offset */ 436 #define EVSYS_USER20_REG_OFST _UINT32_(0x170) /* (EVSYS_USER20) User Multiplexer n Offset */ 437 #define EVSYS_USER21_REG_OFST _UINT32_(0x174) /* (EVSYS_USER21) User Multiplexer n Offset */ 438 #define EVSYS_USER22_REG_OFST _UINT32_(0x178) /* (EVSYS_USER22) User Multiplexer n Offset */ 439 #define EVSYS_USER23_REG_OFST _UINT32_(0x17C) /* (EVSYS_USER23) User Multiplexer n Offset */ 440 #define EVSYS_USER24_REG_OFST _UINT32_(0x180) /* (EVSYS_USER24) User Multiplexer n Offset */ 441 #define EVSYS_USER25_REG_OFST _UINT32_(0x184) /* (EVSYS_USER25) User Multiplexer n Offset */ 442 #define EVSYS_USER26_REG_OFST _UINT32_(0x188) /* (EVSYS_USER26) User Multiplexer n Offset */ 443 #define EVSYS_USER27_REG_OFST _UINT32_(0x18C) /* (EVSYS_USER27) User Multiplexer n Offset */ 444 #define EVSYS_USER28_REG_OFST _UINT32_(0x190) /* (EVSYS_USER28) User Multiplexer n Offset */ 445 #define EVSYS_USER29_REG_OFST _UINT32_(0x194) /* (EVSYS_USER29) User Multiplexer n Offset */ 446 #define EVSYS_USER30_REG_OFST _UINT32_(0x198) /* (EVSYS_USER30) User Multiplexer n Offset */ 447 #define EVSYS_USER31_REG_OFST _UINT32_(0x19C) /* (EVSYS_USER31) User Multiplexer n Offset */ 448 #define EVSYS_USER32_REG_OFST _UINT32_(0x1A0) /* (EVSYS_USER32) User Multiplexer n Offset */ 449 #define EVSYS_USER33_REG_OFST _UINT32_(0x1A4) /* (EVSYS_USER33) User Multiplexer n Offset */ 450 #define EVSYS_USER34_REG_OFST _UINT32_(0x1A8) /* (EVSYS_USER34) User Multiplexer n Offset */ 451 #define EVSYS_USER35_REG_OFST _UINT32_(0x1AC) /* (EVSYS_USER35) User Multiplexer n Offset */ 452 #define EVSYS_USER36_REG_OFST _UINT32_(0x1B0) /* (EVSYS_USER36) User Multiplexer n Offset */ 453 #define EVSYS_USER37_REG_OFST _UINT32_(0x1B4) /* (EVSYS_USER37) User Multiplexer n Offset */ 454 #define EVSYS_USER38_REG_OFST _UINT32_(0x1B8) /* (EVSYS_USER38) User Multiplexer n Offset */ 455 #define EVSYS_USER39_REG_OFST _UINT32_(0x1BC) /* (EVSYS_USER39) User Multiplexer n Offset */ 456 #define EVSYS_USER40_REG_OFST _UINT32_(0x1C0) /* (EVSYS_USER40) User Multiplexer n Offset */ 457 #define EVSYS_USER41_REG_OFST _UINT32_(0x1C4) /* (EVSYS_USER41) User Multiplexer n Offset */ 458 #define EVSYS_USER42_REG_OFST _UINT32_(0x1C8) /* (EVSYS_USER42) User Multiplexer n Offset */ 459 #define EVSYS_USER43_REG_OFST _UINT32_(0x1CC) /* (EVSYS_USER43) User Multiplexer n Offset */ 460 #define EVSYS_USER44_REG_OFST _UINT32_(0x1D0) /* (EVSYS_USER44) User Multiplexer n Offset */ 461 #define EVSYS_USER45_REG_OFST _UINT32_(0x1D4) /* (EVSYS_USER45) User Multiplexer n Offset */ 462 #define EVSYS_USER46_REG_OFST _UINT32_(0x1D8) /* (EVSYS_USER46) User Multiplexer n Offset */ 463 #define EVSYS_USER47_REG_OFST _UINT32_(0x1DC) /* (EVSYS_USER47) User Multiplexer n Offset */ 464 #define EVSYS_USER48_REG_OFST _UINT32_(0x1E0) /* (EVSYS_USER48) User Multiplexer n Offset */ 465 #define EVSYS_USER49_REG_OFST _UINT32_(0x1E4) /* (EVSYS_USER49) User Multiplexer n Offset */ 466 #define EVSYS_USER50_REG_OFST _UINT32_(0x1E8) /* (EVSYS_USER50) User Multiplexer n Offset */ 467 #define EVSYS_USER51_REG_OFST _UINT32_(0x1EC) /* (EVSYS_USER51) User Multiplexer n Offset */ 468 #define EVSYS_USER52_REG_OFST _UINT32_(0x1F0) /* (EVSYS_USER52) User Multiplexer n Offset */ 469 #define EVSYS_USER53_REG_OFST _UINT32_(0x1F4) /* (EVSYS_USER53) User Multiplexer n Offset */ 470 #define EVSYS_USER54_REG_OFST _UINT32_(0x1F8) /* (EVSYS_USER54) User Multiplexer n Offset */ 471 #define EVSYS_USER55_REG_OFST _UINT32_(0x1FC) /* (EVSYS_USER55) User Multiplexer n Offset */ 472 #define EVSYS_USER56_REG_OFST _UINT32_(0x200) /* (EVSYS_USER56) User Multiplexer n Offset */ 473 #define EVSYS_USER57_REG_OFST _UINT32_(0x204) /* (EVSYS_USER57) User Multiplexer n Offset */ 474 #define EVSYS_USER58_REG_OFST _UINT32_(0x208) /* (EVSYS_USER58) User Multiplexer n Offset */ 475 #define EVSYS_USER59_REG_OFST _UINT32_(0x20C) /* (EVSYS_USER59) User Multiplexer n Offset */ 476 #define EVSYS_USER60_REG_OFST _UINT32_(0x210) /* (EVSYS_USER60) User Multiplexer n Offset */ 477 #define EVSYS_USER61_REG_OFST _UINT32_(0x214) /* (EVSYS_USER61) User Multiplexer n Offset */ 478 #define EVSYS_USER62_REG_OFST _UINT32_(0x218) /* (EVSYS_USER62) User Multiplexer n Offset */ 479 #define EVSYS_USER63_REG_OFST _UINT32_(0x21C) /* (EVSYS_USER63) User Multiplexer n Offset */ 480 #define EVSYS_USER64_REG_OFST _UINT32_(0x220) /* (EVSYS_USER64) User Multiplexer n Offset */ 481 #define EVSYS_USER65_REG_OFST _UINT32_(0x224) /* (EVSYS_USER65) User Multiplexer n Offset */ 482 #define EVSYS_USER66_REG_OFST _UINT32_(0x228) /* (EVSYS_USER66) User Multiplexer n Offset */ 483 484 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 485 /** \brief CHANNEL register API structure */ 486 typedef struct 487 { 488 __IO uint32_t EVSYS_CHANNEL; /**< Offset: 0x00 (R/W 32) Channel n Control */ 489 __IO uint8_t EVSYS_CHINTENCLR; /**< Offset: 0x04 (R/W 8) Channel n Interrupt Enable Clear */ 490 __IO uint8_t EVSYS_CHINTENSET; /**< Offset: 0x05 (R/W 8) Channel n Interrupt Enable Set */ 491 __IO uint8_t EVSYS_CHINTFLAG; /**< Offset: 0x06 (R/W 8) Channel n Interrupt Flag Status and Clear */ 492 __I uint8_t EVSYS_CHSTATUS; /**< Offset: 0x07 (R/ 8) Channel n Status */ 493 } evsys_channel_registers_t; 494 495 #define EVSYS_CHANNEL_NUMBER 32 496 497 /** \brief EVSYS register API structure */ 498 typedef struct 499 { /* Event System Interface */ 500 __IO uint8_t EVSYS_CTRLA; /**< Offset: 0x00 (R/W 8) Control */ 501 __I uint8_t Reserved1[0x03]; 502 __O uint32_t EVSYS_SWEVT; /**< Offset: 0x04 ( /W 32) Software Event */ 503 __IO uint8_t EVSYS_PRICTRL; /**< Offset: 0x08 (R/W 8) Priority Control */ 504 __I uint8_t Reserved2[0x07]; 505 __IO uint16_t EVSYS_INTPEND; /**< Offset: 0x10 (R/W 16) Channel Pending Interrupt */ 506 __I uint8_t Reserved3[0x02]; 507 __I uint32_t EVSYS_INTSTATUS; /**< Offset: 0x14 (R/ 32) Interrupt Status */ 508 __I uint32_t EVSYS_BUSYCH; /**< Offset: 0x18 (R/ 32) Busy Channels */ 509 __I uint32_t EVSYS_READYUSR; /**< Offset: 0x1C (R/ 32) Ready Users */ 510 evsys_channel_registers_t CHANNEL[EVSYS_CHANNEL_NUMBER]; /**< Offset: 0x20 */ 511 __IO uint32_t EVSYS_USER[67]; /**< Offset: 0x120 (R/W 32) User Multiplexer n */ 512 } evsys_registers_t; 513 514 515 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 516 #endif /* _PIC32CXSG60_EVSYS_COMPONENT_H_ */ 517
