1 /* 2 * Component description for CCL 3 * 4 * Copyright (c) 2023 Microchip Technology Inc. and its subsidiaries. 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 */ 19 20 /* file generated from device description file (ATDF) version 2023-03-17T09:48:46Z */ 21 #ifndef _PIC32CXSG60_CCL_COMPONENT_H_ 22 #define _PIC32CXSG60_CCL_COMPONENT_H_ 23 24 /* ************************************************************************** */ 25 /* SOFTWARE API DEFINITION FOR CCL */ 26 /* ************************************************************************** */ 27 28 /* -------- CCL_CTRL : (CCL Offset: 0x00) (R/W 8) Control -------- */ 29 #define CCL_CTRL_RESETVALUE _UINT8_(0x00) /* (CCL_CTRL) Control Reset Value */ 30 31 #define CCL_CTRL_SWRST_Pos _UINT8_(0) /* (CCL_CTRL) Software Reset Position */ 32 #define CCL_CTRL_SWRST_Msk (_UINT8_(0x1) << CCL_CTRL_SWRST_Pos) /* (CCL_CTRL) Software Reset Mask */ 33 #define CCL_CTRL_SWRST(value) (CCL_CTRL_SWRST_Msk & (_UINT8_(value) << CCL_CTRL_SWRST_Pos)) /* Assigment of value for SWRST in the CCL_CTRL register */ 34 #define CCL_CTRL_SWRST_DISABLE_Val _UINT8_(0x0) /* (CCL_CTRL) The peripheral is not reset */ 35 #define CCL_CTRL_SWRST_ENABLE_Val _UINT8_(0x1) /* (CCL_CTRL) The peripheral is reset */ 36 #define CCL_CTRL_SWRST_DISABLE (CCL_CTRL_SWRST_DISABLE_Val << CCL_CTRL_SWRST_Pos) /* (CCL_CTRL) The peripheral is not reset Position */ 37 #define CCL_CTRL_SWRST_ENABLE (CCL_CTRL_SWRST_ENABLE_Val << CCL_CTRL_SWRST_Pos) /* (CCL_CTRL) The peripheral is reset Position */ 38 #define CCL_CTRL_ENABLE_Pos _UINT8_(1) /* (CCL_CTRL) Enable Position */ 39 #define CCL_CTRL_ENABLE_Msk (_UINT8_(0x1) << CCL_CTRL_ENABLE_Pos) /* (CCL_CTRL) Enable Mask */ 40 #define CCL_CTRL_ENABLE(value) (CCL_CTRL_ENABLE_Msk & (_UINT8_(value) << CCL_CTRL_ENABLE_Pos)) /* Assigment of value for ENABLE in the CCL_CTRL register */ 41 #define CCL_CTRL_ENABLE_DISABLE_Val _UINT8_(0x0) /* (CCL_CTRL) The peripheral is disabled */ 42 #define CCL_CTRL_ENABLE_ENABLE_Val _UINT8_(0x1) /* (CCL_CTRL) The peripheral is enabled */ 43 #define CCL_CTRL_ENABLE_DISABLE (CCL_CTRL_ENABLE_DISABLE_Val << CCL_CTRL_ENABLE_Pos) /* (CCL_CTRL) The peripheral is disabled Position */ 44 #define CCL_CTRL_ENABLE_ENABLE (CCL_CTRL_ENABLE_ENABLE_Val << CCL_CTRL_ENABLE_Pos) /* (CCL_CTRL) The peripheral is enabled Position */ 45 #define CCL_CTRL_RUNSTDBY_Pos _UINT8_(6) /* (CCL_CTRL) Run in Standby Position */ 46 #define CCL_CTRL_RUNSTDBY_Msk (_UINT8_(0x1) << CCL_CTRL_RUNSTDBY_Pos) /* (CCL_CTRL) Run in Standby Mask */ 47 #define CCL_CTRL_RUNSTDBY(value) (CCL_CTRL_RUNSTDBY_Msk & (_UINT8_(value) << CCL_CTRL_RUNSTDBY_Pos)) /* Assigment of value for RUNSTDBY in the CCL_CTRL register */ 48 #define CCL_CTRL_RUNSTDBY_DISABLE_Val _UINT8_(0x0) /* (CCL_CTRL) Generic clock is not required in standby sleep mode */ 49 #define CCL_CTRL_RUNSTDBY_ENABLE_Val _UINT8_(0x1) /* (CCL_CTRL) Generic clock is required in standby sleep mode */ 50 #define CCL_CTRL_RUNSTDBY_DISABLE (CCL_CTRL_RUNSTDBY_DISABLE_Val << CCL_CTRL_RUNSTDBY_Pos) /* (CCL_CTRL) Generic clock is not required in standby sleep mode Position */ 51 #define CCL_CTRL_RUNSTDBY_ENABLE (CCL_CTRL_RUNSTDBY_ENABLE_Val << CCL_CTRL_RUNSTDBY_Pos) /* (CCL_CTRL) Generic clock is required in standby sleep mode Position */ 52 #define CCL_CTRL_Msk _UINT8_(0x43) /* (CCL_CTRL) Register Mask */ 53 54 55 /* -------- CCL_SEQCTRL : (CCL Offset: 0x04) (R/W 8) SEQ Control x -------- */ 56 #define CCL_SEQCTRL_RESETVALUE _UINT8_(0x00) /* (CCL_SEQCTRL) SEQ Control x Reset Value */ 57 58 #define CCL_SEQCTRL_SEQSEL_Pos _UINT8_(0) /* (CCL_SEQCTRL) Sequential Selection Position */ 59 #define CCL_SEQCTRL_SEQSEL_Msk (_UINT8_(0xF) << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) Sequential Selection Mask */ 60 #define CCL_SEQCTRL_SEQSEL(value) (CCL_SEQCTRL_SEQSEL_Msk & (_UINT8_(value) << CCL_SEQCTRL_SEQSEL_Pos)) /* Assigment of value for SEQSEL in the CCL_SEQCTRL register */ 61 #define CCL_SEQCTRL_SEQSEL_DISABLE_Val _UINT8_(0x0) /* (CCL_SEQCTRL) Sequential logic is disabled */ 62 #define CCL_SEQCTRL_SEQSEL_DFF_Val _UINT8_(0x1) /* (CCL_SEQCTRL) D flip flop */ 63 #define CCL_SEQCTRL_SEQSEL_JK_Val _UINT8_(0x2) /* (CCL_SEQCTRL) JK flip flop */ 64 #define CCL_SEQCTRL_SEQSEL_LATCH_Val _UINT8_(0x3) /* (CCL_SEQCTRL) D latch */ 65 #define CCL_SEQCTRL_SEQSEL_RS_Val _UINT8_(0x4) /* (CCL_SEQCTRL) RS latch */ 66 #define CCL_SEQCTRL_SEQSEL_DISABLE (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) Sequential logic is disabled Position */ 67 #define CCL_SEQCTRL_SEQSEL_DFF (CCL_SEQCTRL_SEQSEL_DFF_Val << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) D flip flop Position */ 68 #define CCL_SEQCTRL_SEQSEL_JK (CCL_SEQCTRL_SEQSEL_JK_Val << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) JK flip flop Position */ 69 #define CCL_SEQCTRL_SEQSEL_LATCH (CCL_SEQCTRL_SEQSEL_LATCH_Val << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) D latch Position */ 70 #define CCL_SEQCTRL_SEQSEL_RS (CCL_SEQCTRL_SEQSEL_RS_Val << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) RS latch Position */ 71 #define CCL_SEQCTRL_Msk _UINT8_(0x0F) /* (CCL_SEQCTRL) Register Mask */ 72 73 74 /* -------- CCL_LUTCTRL : (CCL Offset: 0x08) (R/W 32) LUT Control x -------- */ 75 #define CCL_LUTCTRL_RESETVALUE _UINT32_(0x00) /* (CCL_LUTCTRL) LUT Control x Reset Value */ 76 77 #define CCL_LUTCTRL_ENABLE_Pos _UINT32_(1) /* (CCL_LUTCTRL) LUT Enable Position */ 78 #define CCL_LUTCTRL_ENABLE_Msk (_UINT32_(0x1) << CCL_LUTCTRL_ENABLE_Pos) /* (CCL_LUTCTRL) LUT Enable Mask */ 79 #define CCL_LUTCTRL_ENABLE(value) (CCL_LUTCTRL_ENABLE_Msk & (_UINT32_(value) << CCL_LUTCTRL_ENABLE_Pos)) /* Assigment of value for ENABLE in the CCL_LUTCTRL register */ 80 #define CCL_LUTCTRL_ENABLE_DISABLE_Val _UINT32_(0x0) /* (CCL_LUTCTRL) LUT block is disabled */ 81 #define CCL_LUTCTRL_ENABLE_ENABLE_Val _UINT32_(0x1) /* (CCL_LUTCTRL) LUT block is enabled */ 82 #define CCL_LUTCTRL_ENABLE_DISABLE (CCL_LUTCTRL_ENABLE_DISABLE_Val << CCL_LUTCTRL_ENABLE_Pos) /* (CCL_LUTCTRL) LUT block is disabled Position */ 83 #define CCL_LUTCTRL_ENABLE_ENABLE (CCL_LUTCTRL_ENABLE_ENABLE_Val << CCL_LUTCTRL_ENABLE_Pos) /* (CCL_LUTCTRL) LUT block is enabled Position */ 84 #define CCL_LUTCTRL_FILTSEL_Pos _UINT32_(4) /* (CCL_LUTCTRL) Filter Selection Position */ 85 #define CCL_LUTCTRL_FILTSEL_Msk (_UINT32_(0x3) << CCL_LUTCTRL_FILTSEL_Pos) /* (CCL_LUTCTRL) Filter Selection Mask */ 86 #define CCL_LUTCTRL_FILTSEL(value) (CCL_LUTCTRL_FILTSEL_Msk & (_UINT32_(value) << CCL_LUTCTRL_FILTSEL_Pos)) /* Assigment of value for FILTSEL in the CCL_LUTCTRL register */ 87 #define CCL_LUTCTRL_FILTSEL_DISABLE_Val _UINT32_(0x0) /* (CCL_LUTCTRL) Filter disabled */ 88 #define CCL_LUTCTRL_FILTSEL_SYNCH_Val _UINT32_(0x1) /* (CCL_LUTCTRL) Synchronizer enabled */ 89 #define CCL_LUTCTRL_FILTSEL_FILTER_Val _UINT32_(0x2) /* (CCL_LUTCTRL) Filter enabled */ 90 #define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos) /* (CCL_LUTCTRL) Filter disabled Position */ 91 #define CCL_LUTCTRL_FILTSEL_SYNCH (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos) /* (CCL_LUTCTRL) Synchronizer enabled Position */ 92 #define CCL_LUTCTRL_FILTSEL_FILTER (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos) /* (CCL_LUTCTRL) Filter enabled Position */ 93 #define CCL_LUTCTRL_EDGESEL_Pos _UINT32_(7) /* (CCL_LUTCTRL) Edge Selection Position */ 94 #define CCL_LUTCTRL_EDGESEL_Msk (_UINT32_(0x1) << CCL_LUTCTRL_EDGESEL_Pos) /* (CCL_LUTCTRL) Edge Selection Mask */ 95 #define CCL_LUTCTRL_EDGESEL(value) (CCL_LUTCTRL_EDGESEL_Msk & (_UINT32_(value) << CCL_LUTCTRL_EDGESEL_Pos)) /* Assigment of value for EDGESEL in the CCL_LUTCTRL register */ 96 #define CCL_LUTCTRL_EDGESEL_DISABLE_Val _UINT32_(0x0) /* (CCL_LUTCTRL) Edge detector is disabled */ 97 #define CCL_LUTCTRL_EDGESEL_ENABLE_Val _UINT32_(0x1) /* (CCL_LUTCTRL) Edge detector is enabled */ 98 #define CCL_LUTCTRL_EDGESEL_DISABLE (CCL_LUTCTRL_EDGESEL_DISABLE_Val << CCL_LUTCTRL_EDGESEL_Pos) /* (CCL_LUTCTRL) Edge detector is disabled Position */ 99 #define CCL_LUTCTRL_EDGESEL_ENABLE (CCL_LUTCTRL_EDGESEL_ENABLE_Val << CCL_LUTCTRL_EDGESEL_Pos) /* (CCL_LUTCTRL) Edge detector is enabled Position */ 100 #define CCL_LUTCTRL_INSEL0_Pos _UINT32_(8) /* (CCL_LUTCTRL) Input Selection 0 Position */ 101 #define CCL_LUTCTRL_INSEL0_Msk (_UINT32_(0xF) << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Input Selection 0 Mask */ 102 #define CCL_LUTCTRL_INSEL0(value) (CCL_LUTCTRL_INSEL0_Msk & (_UINT32_(value) << CCL_LUTCTRL_INSEL0_Pos)) /* Assigment of value for INSEL0 in the CCL_LUTCTRL register */ 103 #define CCL_LUTCTRL_INSEL0_MASK_Val _UINT32_(0x0) /* (CCL_LUTCTRL) Masked input */ 104 #define CCL_LUTCTRL_INSEL0_FEEDBACK_Val _UINT32_(0x1) /* (CCL_LUTCTRL) Feedback input source */ 105 #define CCL_LUTCTRL_INSEL0_LINK_Val _UINT32_(0x2) /* (CCL_LUTCTRL) Linked LUT input source */ 106 #define CCL_LUTCTRL_INSEL0_EVENT_Val _UINT32_(0x3) /* (CCL_LUTCTRL) Event input source */ 107 #define CCL_LUTCTRL_INSEL0_IO_Val _UINT32_(0x4) /* (CCL_LUTCTRL) I/O pin input source */ 108 #define CCL_LUTCTRL_INSEL0_AC_Val _UINT32_(0x5) /* (CCL_LUTCTRL) AC input source */ 109 #define CCL_LUTCTRL_INSEL0_TC_Val _UINT32_(0x6) /* (CCL_LUTCTRL) TC input source */ 110 #define CCL_LUTCTRL_INSEL0_ALTTC_Val _UINT32_(0x7) /* (CCL_LUTCTRL) Alternate TC input source */ 111 #define CCL_LUTCTRL_INSEL0_TCC_Val _UINT32_(0x8) /* (CCL_LUTCTRL) TCC input source */ 112 #define CCL_LUTCTRL_INSEL0_SERCOM_Val _UINT32_(0x9) /* (CCL_LUTCTRL) SERCOM input source */ 113 #define CCL_LUTCTRL_INSEL0_MASK (CCL_LUTCTRL_INSEL0_MASK_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Masked input Position */ 114 #define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Feedback input source Position */ 115 #define CCL_LUTCTRL_INSEL0_LINK (CCL_LUTCTRL_INSEL0_LINK_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Linked LUT input source Position */ 116 #define CCL_LUTCTRL_INSEL0_EVENT (CCL_LUTCTRL_INSEL0_EVENT_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Event input source Position */ 117 #define CCL_LUTCTRL_INSEL0_IO (CCL_LUTCTRL_INSEL0_IO_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) I/O pin input source Position */ 118 #define CCL_LUTCTRL_INSEL0_AC (CCL_LUTCTRL_INSEL0_AC_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) AC input source Position */ 119 #define CCL_LUTCTRL_INSEL0_TC (CCL_LUTCTRL_INSEL0_TC_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) TC input source Position */ 120 #define CCL_LUTCTRL_INSEL0_ALTTC (CCL_LUTCTRL_INSEL0_ALTTC_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Alternate TC input source Position */ 121 #define CCL_LUTCTRL_INSEL0_TCC (CCL_LUTCTRL_INSEL0_TCC_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) TCC input source Position */ 122 #define CCL_LUTCTRL_INSEL0_SERCOM (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) SERCOM input source Position */ 123 #define CCL_LUTCTRL_INSEL1_Pos _UINT32_(12) /* (CCL_LUTCTRL) Input Selection 1 Position */ 124 #define CCL_LUTCTRL_INSEL1_Msk (_UINT32_(0xF) << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Input Selection 1 Mask */ 125 #define CCL_LUTCTRL_INSEL1(value) (CCL_LUTCTRL_INSEL1_Msk & (_UINT32_(value) << CCL_LUTCTRL_INSEL1_Pos)) /* Assigment of value for INSEL1 in the CCL_LUTCTRL register */ 126 #define CCL_LUTCTRL_INSEL1_MASK_Val _UINT32_(0x0) /* (CCL_LUTCTRL) Masked input */ 127 #define CCL_LUTCTRL_INSEL1_FEEDBACK_Val _UINT32_(0x1) /* (CCL_LUTCTRL) Feedback input source */ 128 #define CCL_LUTCTRL_INSEL1_LINK_Val _UINT32_(0x2) /* (CCL_LUTCTRL) Linked LUT input source */ 129 #define CCL_LUTCTRL_INSEL1_EVENT_Val _UINT32_(0x3) /* (CCL_LUTCTRL) Event input source */ 130 #define CCL_LUTCTRL_INSEL1_IO_Val _UINT32_(0x4) /* (CCL_LUTCTRL) I/O pin input source */ 131 #define CCL_LUTCTRL_INSEL1_AC_Val _UINT32_(0x5) /* (CCL_LUTCTRL) AC input source */ 132 #define CCL_LUTCTRL_INSEL1_TC_Val _UINT32_(0x6) /* (CCL_LUTCTRL) TC input source */ 133 #define CCL_LUTCTRL_INSEL1_ALTTC_Val _UINT32_(0x7) /* (CCL_LUTCTRL) Alternate TC input source */ 134 #define CCL_LUTCTRL_INSEL1_TCC_Val _UINT32_(0x8) /* (CCL_LUTCTRL) TCC input source */ 135 #define CCL_LUTCTRL_INSEL1_SERCOM_Val _UINT32_(0x9) /* (CCL_LUTCTRL) SERCOM input source */ 136 #define CCL_LUTCTRL_INSEL1_MASK (CCL_LUTCTRL_INSEL1_MASK_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Masked input Position */ 137 #define CCL_LUTCTRL_INSEL1_FEEDBACK (CCL_LUTCTRL_INSEL1_FEEDBACK_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Feedback input source Position */ 138 #define CCL_LUTCTRL_INSEL1_LINK (CCL_LUTCTRL_INSEL1_LINK_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Linked LUT input source Position */ 139 #define CCL_LUTCTRL_INSEL1_EVENT (CCL_LUTCTRL_INSEL1_EVENT_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Event input source Position */ 140 #define CCL_LUTCTRL_INSEL1_IO (CCL_LUTCTRL_INSEL1_IO_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) I/O pin input source Position */ 141 #define CCL_LUTCTRL_INSEL1_AC (CCL_LUTCTRL_INSEL1_AC_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) AC input source Position */ 142 #define CCL_LUTCTRL_INSEL1_TC (CCL_LUTCTRL_INSEL1_TC_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) TC input source Position */ 143 #define CCL_LUTCTRL_INSEL1_ALTTC (CCL_LUTCTRL_INSEL1_ALTTC_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Alternate TC input source Position */ 144 #define CCL_LUTCTRL_INSEL1_TCC (CCL_LUTCTRL_INSEL1_TCC_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) TCC input source Position */ 145 #define CCL_LUTCTRL_INSEL1_SERCOM (CCL_LUTCTRL_INSEL1_SERCOM_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) SERCOM input source Position */ 146 #define CCL_LUTCTRL_INSEL2_Pos _UINT32_(16) /* (CCL_LUTCTRL) Input Selection 2 Position */ 147 #define CCL_LUTCTRL_INSEL2_Msk (_UINT32_(0xF) << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Input Selection 2 Mask */ 148 #define CCL_LUTCTRL_INSEL2(value) (CCL_LUTCTRL_INSEL2_Msk & (_UINT32_(value) << CCL_LUTCTRL_INSEL2_Pos)) /* Assigment of value for INSEL2 in the CCL_LUTCTRL register */ 149 #define CCL_LUTCTRL_INSEL2_MASK_Val _UINT32_(0x0) /* (CCL_LUTCTRL) Masked input */ 150 #define CCL_LUTCTRL_INSEL2_FEEDBACK_Val _UINT32_(0x1) /* (CCL_LUTCTRL) Feedback input source */ 151 #define CCL_LUTCTRL_INSEL2_LINK_Val _UINT32_(0x2) /* (CCL_LUTCTRL) Linked LUT input source */ 152 #define CCL_LUTCTRL_INSEL2_EVENT_Val _UINT32_(0x3) /* (CCL_LUTCTRL) Event input source */ 153 #define CCL_LUTCTRL_INSEL2_IO_Val _UINT32_(0x4) /* (CCL_LUTCTRL) I/O pin input source */ 154 #define CCL_LUTCTRL_INSEL2_AC_Val _UINT32_(0x5) /* (CCL_LUTCTRL) AC input source */ 155 #define CCL_LUTCTRL_INSEL2_TC_Val _UINT32_(0x6) /* (CCL_LUTCTRL) TC input source */ 156 #define CCL_LUTCTRL_INSEL2_ALTTC_Val _UINT32_(0x7) /* (CCL_LUTCTRL) Alternate TC input source */ 157 #define CCL_LUTCTRL_INSEL2_TCC_Val _UINT32_(0x8) /* (CCL_LUTCTRL) TCC input source */ 158 #define CCL_LUTCTRL_INSEL2_SERCOM_Val _UINT32_(0x9) /* (CCL_LUTCTRL) SERCOM input source */ 159 #define CCL_LUTCTRL_INSEL2_MASK (CCL_LUTCTRL_INSEL2_MASK_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Masked input Position */ 160 #define CCL_LUTCTRL_INSEL2_FEEDBACK (CCL_LUTCTRL_INSEL2_FEEDBACK_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Feedback input source Position */ 161 #define CCL_LUTCTRL_INSEL2_LINK (CCL_LUTCTRL_INSEL2_LINK_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Linked LUT input source Position */ 162 #define CCL_LUTCTRL_INSEL2_EVENT (CCL_LUTCTRL_INSEL2_EVENT_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Event input source Position */ 163 #define CCL_LUTCTRL_INSEL2_IO (CCL_LUTCTRL_INSEL2_IO_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) I/O pin input source Position */ 164 #define CCL_LUTCTRL_INSEL2_AC (CCL_LUTCTRL_INSEL2_AC_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) AC input source Position */ 165 #define CCL_LUTCTRL_INSEL2_TC (CCL_LUTCTRL_INSEL2_TC_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) TC input source Position */ 166 #define CCL_LUTCTRL_INSEL2_ALTTC (CCL_LUTCTRL_INSEL2_ALTTC_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Alternate TC input source Position */ 167 #define CCL_LUTCTRL_INSEL2_TCC (CCL_LUTCTRL_INSEL2_TCC_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) TCC input source Position */ 168 #define CCL_LUTCTRL_INSEL2_SERCOM (CCL_LUTCTRL_INSEL2_SERCOM_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) SERCOM input source Position */ 169 #define CCL_LUTCTRL_INVEI_Pos _UINT32_(20) /* (CCL_LUTCTRL) Inverted Event Input Enable Position */ 170 #define CCL_LUTCTRL_INVEI_Msk (_UINT32_(0x1) << CCL_LUTCTRL_INVEI_Pos) /* (CCL_LUTCTRL) Inverted Event Input Enable Mask */ 171 #define CCL_LUTCTRL_INVEI(value) (CCL_LUTCTRL_INVEI_Msk & (_UINT32_(value) << CCL_LUTCTRL_INVEI_Pos)) /* Assigment of value for INVEI in the CCL_LUTCTRL register */ 172 #define CCL_LUTCTRL_INVEI_DISABLE_Val _UINT32_(0x0) /* (CCL_LUTCTRL) Incoming event is not inverted */ 173 #define CCL_LUTCTRL_INVEI_ENABLE_Val _UINT32_(0x1) /* (CCL_LUTCTRL) Incoming event is inverted */ 174 #define CCL_LUTCTRL_INVEI_DISABLE (CCL_LUTCTRL_INVEI_DISABLE_Val << CCL_LUTCTRL_INVEI_Pos) /* (CCL_LUTCTRL) Incoming event is not inverted Position */ 175 #define CCL_LUTCTRL_INVEI_ENABLE (CCL_LUTCTRL_INVEI_ENABLE_Val << CCL_LUTCTRL_INVEI_Pos) /* (CCL_LUTCTRL) Incoming event is inverted Position */ 176 #define CCL_LUTCTRL_LUTEI_Pos _UINT32_(21) /* (CCL_LUTCTRL) LUT Event Input Enable Position */ 177 #define CCL_LUTCTRL_LUTEI_Msk (_UINT32_(0x1) << CCL_LUTCTRL_LUTEI_Pos) /* (CCL_LUTCTRL) LUT Event Input Enable Mask */ 178 #define CCL_LUTCTRL_LUTEI(value) (CCL_LUTCTRL_LUTEI_Msk & (_UINT32_(value) << CCL_LUTCTRL_LUTEI_Pos)) /* Assigment of value for LUTEI in the CCL_LUTCTRL register */ 179 #define CCL_LUTCTRL_LUTEI_DISABLE_Val _UINT32_(0x0) /* (CCL_LUTCTRL) LUT incoming event is disabled */ 180 #define CCL_LUTCTRL_LUTEI_ENABLE_Val _UINT32_(0x1) /* (CCL_LUTCTRL) LUT incoming event is enabled */ 181 #define CCL_LUTCTRL_LUTEI_DISABLE (CCL_LUTCTRL_LUTEI_DISABLE_Val << CCL_LUTCTRL_LUTEI_Pos) /* (CCL_LUTCTRL) LUT incoming event is disabled Position */ 182 #define CCL_LUTCTRL_LUTEI_ENABLE (CCL_LUTCTRL_LUTEI_ENABLE_Val << CCL_LUTCTRL_LUTEI_Pos) /* (CCL_LUTCTRL) LUT incoming event is enabled Position */ 183 #define CCL_LUTCTRL_LUTEO_Pos _UINT32_(22) /* (CCL_LUTCTRL) LUT Event Output Enable Position */ 184 #define CCL_LUTCTRL_LUTEO_Msk (_UINT32_(0x1) << CCL_LUTCTRL_LUTEO_Pos) /* (CCL_LUTCTRL) LUT Event Output Enable Mask */ 185 #define CCL_LUTCTRL_LUTEO(value) (CCL_LUTCTRL_LUTEO_Msk & (_UINT32_(value) << CCL_LUTCTRL_LUTEO_Pos)) /* Assigment of value for LUTEO in the CCL_LUTCTRL register */ 186 #define CCL_LUTCTRL_LUTEO_DISABLE_Val _UINT32_(0x0) /* (CCL_LUTCTRL) LUT event output is disabled */ 187 #define CCL_LUTCTRL_LUTEO_ENABLE_Val _UINT32_(0x1) /* (CCL_LUTCTRL) LUT event output is enabled */ 188 #define CCL_LUTCTRL_LUTEO_DISABLE (CCL_LUTCTRL_LUTEO_DISABLE_Val << CCL_LUTCTRL_LUTEO_Pos) /* (CCL_LUTCTRL) LUT event output is disabled Position */ 189 #define CCL_LUTCTRL_LUTEO_ENABLE (CCL_LUTCTRL_LUTEO_ENABLE_Val << CCL_LUTCTRL_LUTEO_Pos) /* (CCL_LUTCTRL) LUT event output is enabled Position */ 190 #define CCL_LUTCTRL_TRUTH_Pos _UINT32_(24) /* (CCL_LUTCTRL) Truth Value Position */ 191 #define CCL_LUTCTRL_TRUTH_Msk (_UINT32_(0xFF) << CCL_LUTCTRL_TRUTH_Pos) /* (CCL_LUTCTRL) Truth Value Mask */ 192 #define CCL_LUTCTRL_TRUTH(value) (CCL_LUTCTRL_TRUTH_Msk & (_UINT32_(value) << CCL_LUTCTRL_TRUTH_Pos)) /* Assigment of value for TRUTH in the CCL_LUTCTRL register */ 193 #define CCL_LUTCTRL_Msk _UINT32_(0xFF7FFFB2) /* (CCL_LUTCTRL) Register Mask */ 194 195 196 /** \brief CCL register offsets definitions */ 197 #define CCL_CTRL_REG_OFST _UINT32_(0x00) /* (CCL_CTRL) Control Offset */ 198 #define CCL_SEQCTRL_REG_OFST _UINT32_(0x04) /* (CCL_SEQCTRL) SEQ Control x Offset */ 199 #define CCL_SEQCTRL0_REG_OFST _UINT32_(0x04) /* (CCL_SEQCTRL0) SEQ Control x Offset */ 200 #define CCL_SEQCTRL1_REG_OFST _UINT32_(0x05) /* (CCL_SEQCTRL1) SEQ Control x Offset */ 201 #define CCL_LUTCTRL_REG_OFST _UINT32_(0x08) /* (CCL_LUTCTRL) LUT Control x Offset */ 202 #define CCL_LUTCTRL0_REG_OFST _UINT32_(0x08) /* (CCL_LUTCTRL0) LUT Control x Offset */ 203 #define CCL_LUTCTRL1_REG_OFST _UINT32_(0x0C) /* (CCL_LUTCTRL1) LUT Control x Offset */ 204 #define CCL_LUTCTRL2_REG_OFST _UINT32_(0x10) /* (CCL_LUTCTRL2) LUT Control x Offset */ 205 #define CCL_LUTCTRL3_REG_OFST _UINT32_(0x14) /* (CCL_LUTCTRL3) LUT Control x Offset */ 206 207 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 208 /** \brief CCL register API structure */ 209 typedef struct 210 { /* Configurable Custom Logic */ 211 __IO uint8_t CCL_CTRL; /**< Offset: 0x00 (R/W 8) Control */ 212 __I uint8_t Reserved1[0x03]; 213 __IO uint8_t CCL_SEQCTRL[2]; /**< Offset: 0x04 (R/W 8) SEQ Control x */ 214 __I uint8_t Reserved2[0x02]; 215 __IO uint32_t CCL_LUTCTRL[4]; /**< Offset: 0x08 (R/W 32) LUT Control x */ 216 } ccl_registers_t; 217 218 219 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 220 #endif /* _PIC32CXSG60_CCL_COMPONENT_H_ */ 221
