1 /* 2 * Header file for PIC32CX1025SG41064 3 * 4 * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 */ 19 20 /* File generated from device description file (ATDF) version 2023-03-17T09:50:01Z */ 21 #ifndef _PIC32CX1025SG41064_H_ 22 #define _PIC32CX1025SG41064_H_ 23 24 /* Header version uses Semantic Versioning 2.0.0 (https://semver.org/) */ 25 #define HEADER_FORMAT_VERSION "2.1.1" 26 27 #define HEADER_FORMAT_VERSION_MAJOR (2) 28 #define HEADER_FORMAT_VERSION_MINOR (1) 29 #define HEADER_FORMAT_VERSION_PATCH (1) 30 31 /* PIC32CX1025SG41064 definitions 32 This file defines all structures and symbols for PIC32CX1025SG41064: 33 - registers and bitfields 34 - peripheral base address 35 - peripheral ID 36 - PIO definitions 37 */ 38 39 #ifdef __cplusplus 40 extern "C" { 41 #endif 42 43 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 44 # include <stdint.h> 45 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 46 47 #if !defined(SKIP_INTEGER_LITERALS) 48 # if defined(_UINT8_) || defined(_UINT16_) || defined(_UINT32_) 49 # error "Integer constant value macros already defined elsewhere" 50 # endif 51 52 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 53 /* Macros that deal with sizes of integer constants for C/C++ */ 54 # define _UINT8_(x) ((uint8_t)(x)) /* C code: 8-bits unsigned integer constant value */ 55 # define _UINT16_(x) ((uint16_t)(x)) /* C code: 16-bits unsigned integer constant value */ 56 # define _UINT32_(x) ((uint32_t)(x)) /* C code: 32-bits unsigned integer constant value */ 57 58 #else /* Assembler */ 59 60 # define _UINT8_(x) x /* Assembler: 8-bits unsigned integer constant value */ 61 # define _UINT16_(x) x /* Assembler: 16-bits unsigned integer constant value */ 62 # define _UINT32_(x) x /* Assembler: 32-bits unsigned integer constant value */ 63 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 64 #endif /* SKIP_INTEGER_LITERALS */ 65 66 /* ************************************************************************** */ 67 /* CMSIS DEFINITIONS FOR PIC32CX1025SG41064 */ 68 /* ************************************************************************** */ 69 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 70 /* Interrupt Number Definition */ 71 typedef enum IRQn 72 { 73 /****** CORTEX-M4 Processor Exceptions Numbers ******************************/ 74 Reset_IRQn = -15, /* -15 Reset Vector, invoked on Power up and warm reset */ 75 NonMaskableInt_IRQn = -14, /* -14 Non maskable Interrupt, cannot be stopped or preempted */ 76 HardFault_IRQn = -13, /* -13 Hard Fault, all classes of Fault */ 77 MemoryManagement_IRQn = -12, /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ 78 BusFault_IRQn = -11, /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ 79 UsageFault_IRQn = -10, /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 80 SVCall_IRQn = -5, /* -5 System Service Call via SVC instruction */ 81 DebugMonitor_IRQn = -4, /* -4 Debug Monitor */ 82 PendSV_IRQn = -2, /* -2 Pendable request for system service */ 83 SysTick_IRQn = -1, /* -1 System Tick Timer */ 84 85 /* ************* PIC32CX1025SG41064 specific Interrupt Numbers ************** */ 86 PM_IRQn = 0, /* 0 Power Manager (PM) */ 87 MCLK_IRQn = 1, /* 1 Main Clock (MCLK) */ 88 OSCCTRL_XOSC0_IRQn = 2, /* 2 Oscillators Control (OSCCTRL) */ 89 OSCCTRL_XOSC1_IRQn = 3, /* 3 Oscillators Control (OSCCTRL) */ 90 OSCCTRL_DFLL_IRQn = 4, /* 4 Oscillators Control (OSCCTRL) */ 91 OSCCTRL_DPLL0_IRQn = 5, /* 5 Oscillators Control (OSCCTRL) */ 92 OSCCTRL_DPLL1_IRQn = 6, /* 6 Oscillators Control (OSCCTRL) */ 93 OSC32KCTRL_IRQn = 7, /* 7 32kHz Oscillators Control (OSC32KCTRL) */ 94 SUPC_OTHER_IRQn = 8, /* 8 Supply Controller (SUPC) */ 95 SUPC_BODDET_IRQn = 9, /* 9 Supply Controller (SUPC) */ 96 WDT_IRQn = 10, /* 10 Watchdog Timer (WDT) */ 97 RTC_IRQn = 11, /* 11 Real-Time Counter (RTC) */ 98 EIC_EXTINT_0_IRQn = 12, /* 12 External Interrupt Controller (EIC) */ 99 EIC_EXTINT_1_IRQn = 13, /* 13 External Interrupt Controller (EIC) */ 100 EIC_EXTINT_2_IRQn = 14, /* 14 External Interrupt Controller (EIC) */ 101 EIC_EXTINT_3_IRQn = 15, /* 15 External Interrupt Controller (EIC) */ 102 EIC_EXTINT_4_IRQn = 16, /* 16 External Interrupt Controller (EIC) */ 103 EIC_EXTINT_5_IRQn = 17, /* 17 External Interrupt Controller (EIC) */ 104 EIC_EXTINT_6_IRQn = 18, /* 18 External Interrupt Controller (EIC) */ 105 EIC_EXTINT_7_IRQn = 19, /* 19 External Interrupt Controller (EIC) */ 106 EIC_EXTINT_8_IRQn = 20, /* 20 External Interrupt Controller (EIC) */ 107 EIC_EXTINT_9_IRQn = 21, /* 21 External Interrupt Controller (EIC) */ 108 EIC_EXTINT_10_IRQn = 22, /* 22 External Interrupt Controller (EIC) */ 109 EIC_EXTINT_11_IRQn = 23, /* 23 External Interrupt Controller (EIC) */ 110 EIC_EXTINT_12_IRQn = 24, /* 24 External Interrupt Controller (EIC) */ 111 EIC_EXTINT_13_IRQn = 25, /* 25 External Interrupt Controller (EIC) */ 112 EIC_EXTINT_14_IRQn = 26, /* 26 External Interrupt Controller (EIC) */ 113 EIC_EXTINT_15_IRQn = 27, /* 27 External Interrupt Controller (EIC) */ 114 FREQM_IRQn = 28, /* 28 Frequency Meter (FREQM) */ 115 NVMCTRL_0_IRQn = 29, /* 29 Non-Volatile Memory Controller (NVMCTRL) */ 116 NVMCTRL_1_IRQn = 30, /* 30 Non-Volatile Memory Controller (NVMCTRL) */ 117 DMAC_0_IRQn = 31, /* 31 Direct Memory Access Controller (DMAC) */ 118 DMAC_1_IRQn = 32, /* 32 Direct Memory Access Controller (DMAC) */ 119 DMAC_2_IRQn = 33, /* 33 Direct Memory Access Controller (DMAC) */ 120 DMAC_3_IRQn = 34, /* 34 Direct Memory Access Controller (DMAC) */ 121 DMAC_OTHER_IRQn = 35, /* 35 Direct Memory Access Controller (DMAC) */ 122 EVSYS_0_IRQn = 36, /* 36 Event System Interface (EVSYS) */ 123 EVSYS_1_IRQn = 37, /* 37 Event System Interface (EVSYS) */ 124 EVSYS_2_IRQn = 38, /* 38 Event System Interface (EVSYS) */ 125 EVSYS_3_IRQn = 39, /* 39 Event System Interface (EVSYS) */ 126 EVSYS_OTHER_IRQn = 40, /* 40 Event System Interface (EVSYS) */ 127 PAC_IRQn = 41, /* 41 Peripheral Access Controller (PAC) */ 128 RAMECC_IRQn = 45, /* 45 RAM ECC (RAMECC) */ 129 SERCOM0_0_IRQn = 46, /* 46 Serial Communication Interface (SERCOM0) */ 130 SERCOM0_1_IRQn = 47, /* 47 Serial Communication Interface (SERCOM0) */ 131 SERCOM0_2_IRQn = 48, /* 48 Serial Communication Interface (SERCOM0) */ 132 SERCOM0_OTHER_IRQn = 49, /* 49 Serial Communication Interface (SERCOM0) */ 133 SERCOM1_0_IRQn = 50, /* 50 Serial Communication Interface (SERCOM1) */ 134 SERCOM1_1_IRQn = 51, /* 51 Serial Communication Interface (SERCOM1) */ 135 SERCOM1_2_IRQn = 52, /* 52 Serial Communication Interface (SERCOM1) */ 136 SERCOM1_OTHER_IRQn = 53, /* 53 Serial Communication Interface (SERCOM1) */ 137 SERCOM2_0_IRQn = 54, /* 54 Serial Communication Interface (SERCOM2) */ 138 SERCOM2_1_IRQn = 55, /* 55 Serial Communication Interface (SERCOM2) */ 139 SERCOM2_2_IRQn = 56, /* 56 Serial Communication Interface (SERCOM2) */ 140 SERCOM2_OTHER_IRQn = 57, /* 57 Serial Communication Interface (SERCOM2) */ 141 SERCOM3_0_IRQn = 58, /* 58 Serial Communication Interface (SERCOM3) */ 142 SERCOM3_1_IRQn = 59, /* 59 Serial Communication Interface (SERCOM3) */ 143 SERCOM3_2_IRQn = 60, /* 60 Serial Communication Interface (SERCOM3) */ 144 SERCOM3_OTHER_IRQn = 61, /* 61 Serial Communication Interface (SERCOM3) */ 145 SERCOM4_0_IRQn = 62, /* 62 Serial Communication Interface (SERCOM4) */ 146 SERCOM4_1_IRQn = 63, /* 63 Serial Communication Interface (SERCOM4) */ 147 SERCOM4_2_IRQn = 64, /* 64 Serial Communication Interface (SERCOM4) */ 148 SERCOM4_OTHER_IRQn = 65, /* 65 Serial Communication Interface (SERCOM4) */ 149 SERCOM5_0_IRQn = 66, /* 66 Serial Communication Interface (SERCOM5) */ 150 SERCOM5_1_IRQn = 67, /* 67 Serial Communication Interface (SERCOM5) */ 151 SERCOM5_2_IRQn = 68, /* 68 Serial Communication Interface (SERCOM5) */ 152 SERCOM5_OTHER_IRQn = 69, /* 69 Serial Communication Interface (SERCOM5) */ 153 USB_OTHER_IRQn = 80, /* 80 Universal Serial Bus (USB) */ 154 USB_SOF_HSOF_IRQn = 81, /* 81 Universal Serial Bus (USB) */ 155 USB_TRCPT0_IRQn = 82, /* 82 Universal Serial Bus (USB) */ 156 USB_TRCPT1_IRQn = 83, /* 83 Universal Serial Bus (USB) */ 157 GMAC_IRQn = 84, /* 84 Ethernet MAC (GMAC) */ 158 TCC0_OTHER_IRQn = 85, /* 85 Timer Counter Control (TCC0) */ 159 TCC0_MC0_IRQn = 86, /* 86 Timer Counter Control (TCC0) */ 160 TCC0_MC1_IRQn = 87, /* 87 Timer Counter Control (TCC0) */ 161 TCC0_MC2_IRQn = 88, /* 88 Timer Counter Control (TCC0) */ 162 TCC0_MC3_IRQn = 89, /* 89 Timer Counter Control (TCC0) */ 163 TCC0_MC4_IRQn = 90, /* 90 Timer Counter Control (TCC0) */ 164 TCC0_MC5_IRQn = 91, /* 91 Timer Counter Control (TCC0) */ 165 TCC1_OTHER_IRQn = 92, /* 92 Timer Counter Control (TCC1) */ 166 TCC1_MC0_IRQn = 93, /* 93 Timer Counter Control (TCC1) */ 167 TCC1_MC1_IRQn = 94, /* 94 Timer Counter Control (TCC1) */ 168 TCC1_MC2_IRQn = 95, /* 95 Timer Counter Control (TCC1) */ 169 TCC1_MC3_IRQn = 96, /* 96 Timer Counter Control (TCC1) */ 170 TCC2_OTHER_IRQn = 97, /* 97 Timer Counter Control (TCC2) */ 171 TCC2_MC0_IRQn = 98, /* 98 Timer Counter Control (TCC2) */ 172 TCC2_MC1_IRQn = 99, /* 99 Timer Counter Control (TCC2) */ 173 TCC2_MC2_IRQn = 100, /* 100 Timer Counter Control (TCC2) */ 174 TCC3_OTHER_IRQn = 101, /* 101 Timer Counter Control (TCC3) */ 175 TCC3_MC0_IRQn = 102, /* 102 Timer Counter Control (TCC3) */ 176 TCC3_MC1_IRQn = 103, /* 103 Timer Counter Control (TCC3) */ 177 TCC4_OTHER_IRQn = 104, /* 104 Timer Counter Control (TCC4) */ 178 TCC4_MC0_IRQn = 105, /* 105 Timer Counter Control (TCC4) */ 179 TCC4_MC1_IRQn = 106, /* 106 Timer Counter Control (TCC4) */ 180 TC0_IRQn = 107, /* 107 Basic Timer Counter (TC0) */ 181 TC1_IRQn = 108, /* 108 Basic Timer Counter (TC1) */ 182 TC2_IRQn = 109, /* 109 Basic Timer Counter (TC2) */ 183 TC3_IRQn = 110, /* 110 Basic Timer Counter (TC3) */ 184 TC4_IRQn = 111, /* 111 Basic Timer Counter (TC4) */ 185 TC5_IRQn = 112, /* 112 Basic Timer Counter (TC5) */ 186 PDEC_OTHER_IRQn = 115, /* 115 Quadrature Decodeur (PDEC) */ 187 PDEC_MC0_IRQn = 116, /* 116 Quadrature Decodeur (PDEC) */ 188 PDEC_MC1_IRQn = 117, /* 117 Quadrature Decodeur (PDEC) */ 189 ADC0_OTHER_IRQn = 118, /* 118 Analog Digital Converter (ADC0) */ 190 ADC0_RESRDY_IRQn = 119, /* 119 Analog Digital Converter (ADC0) */ 191 ADC1_OTHER_IRQn = 120, /* 120 Analog Digital Converter (ADC1) */ 192 ADC1_RESRDY_IRQn = 121, /* 121 Analog Digital Converter (ADC1) */ 193 AC_IRQn = 122, /* 122 Analog Comparators (AC) */ 194 DAC_OTHER_IRQn = 123, /* 123 Digital-to-Analog Converter (DAC) */ 195 DAC_EMPTY_0_IRQn = 124, /* 124 Digital-to-Analog Converter (DAC) */ 196 DAC_EMPTY_1_IRQn = 125, /* 125 Digital-to-Analog Converter (DAC) */ 197 I2S_IRQn = 128, /* 128 Inter-IC Sound Interface (I2S) */ 198 PCC_IRQn = 129, /* 129 Parallel Capture Controller (PCC) */ 199 AES_IRQn = 130, /* 130 Advanced Encryption Standard (AES) */ 200 TRNG_IRQn = 131, /* 131 True Random Generator (TRNG) */ 201 ICM_IRQn = 132, /* 132 Integrity Check Monitor (ICM) */ 202 PUKCC_IRQn = 133, /* 133 PUblic-Key Cryptography Controller (PUKCC) */ 203 QSPI_IRQn = 134, /* 134 Quad SPI interface (QSPI) */ 204 SDHC0_IRQn = 135, /* 135 SD/MMC Host Controller (SDHC0) */ 205 206 PERIPH_MAX_IRQn = 135 /* Max peripheral ID */ 207 } IRQn_Type; 208 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 209 210 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 211 typedef struct _DeviceVectors 212 { 213 /* Stack pointer */ 214 void* pvStack; 215 /* CORTEX-M4 handlers */ 216 void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ 217 void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ 218 void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ 219 void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ 220 void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ 221 void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 222 void* pvReservedC9; 223 void* pvReservedC8; 224 void* pvReservedC7; 225 void* pvReservedC6; 226 void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ 227 void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ 228 void* pvReservedC3; 229 void* pfnPendSV_Handler; /* -2 Pendable request for system service */ 230 void* pfnSysTick_Handler; /* -1 System Tick Timer */ 231 232 /* Peripheral handlers */ 233 void* pfnPM_Handler; /* 0 Power Manager (PM) */ 234 void* pfnMCLK_Handler; /* 1 Main Clock (MCLK) */ 235 void* pfnOSCCTRL_XOSC0_Handler; /* 2 Oscillators Control (OSCCTRL) */ 236 void* pfnOSCCTRL_XOSC1_Handler; /* 3 Oscillators Control (OSCCTRL) */ 237 void* pfnOSCCTRL_DFLL_Handler; /* 4 Oscillators Control (OSCCTRL) */ 238 void* pfnOSCCTRL_DPLL0_Handler; /* 5 Oscillators Control (OSCCTRL) */ 239 void* pfnOSCCTRL_DPLL1_Handler; /* 6 Oscillators Control (OSCCTRL) */ 240 void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control (OSC32KCTRL) */ 241 void* pfnSUPC_OTHER_Handler; /* 8 Supply Controller (SUPC) */ 242 void* pfnSUPC_BODDET_Handler; /* 9 Supply Controller (SUPC) */ 243 void* pfnWDT_Handler; /* 10 Watchdog Timer (WDT) */ 244 void* pfnRTC_Handler; /* 11 Real-Time Counter (RTC) */ 245 void* pfnEIC_EXTINT_0_Handler; /* 12 External Interrupt Controller (EIC) */ 246 void* pfnEIC_EXTINT_1_Handler; /* 13 External Interrupt Controller (EIC) */ 247 void* pfnEIC_EXTINT_2_Handler; /* 14 External Interrupt Controller (EIC) */ 248 void* pfnEIC_EXTINT_3_Handler; /* 15 External Interrupt Controller (EIC) */ 249 void* pfnEIC_EXTINT_4_Handler; /* 16 External Interrupt Controller (EIC) */ 250 void* pfnEIC_EXTINT_5_Handler; /* 17 External Interrupt Controller (EIC) */ 251 void* pfnEIC_EXTINT_6_Handler; /* 18 External Interrupt Controller (EIC) */ 252 void* pfnEIC_EXTINT_7_Handler; /* 19 External Interrupt Controller (EIC) */ 253 void* pfnEIC_EXTINT_8_Handler; /* 20 External Interrupt Controller (EIC) */ 254 void* pfnEIC_EXTINT_9_Handler; /* 21 External Interrupt Controller (EIC) */ 255 void* pfnEIC_EXTINT_10_Handler; /* 22 External Interrupt Controller (EIC) */ 256 void* pfnEIC_EXTINT_11_Handler; /* 23 External Interrupt Controller (EIC) */ 257 void* pfnEIC_EXTINT_12_Handler; /* 24 External Interrupt Controller (EIC) */ 258 void* pfnEIC_EXTINT_13_Handler; /* 25 External Interrupt Controller (EIC) */ 259 void* pfnEIC_EXTINT_14_Handler; /* 26 External Interrupt Controller (EIC) */ 260 void* pfnEIC_EXTINT_15_Handler; /* 27 External Interrupt Controller (EIC) */ 261 void* pfnFREQM_Handler; /* 28 Frequency Meter (FREQM) */ 262 void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller (NVMCTRL) */ 263 void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller (NVMCTRL) */ 264 void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller (DMAC) */ 265 void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller (DMAC) */ 266 void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller (DMAC) */ 267 void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller (DMAC) */ 268 void* pfnDMAC_OTHER_Handler; /* 35 Direct Memory Access Controller (DMAC) */ 269 void* pfnEVSYS_0_Handler; /* 36 Event System Interface (EVSYS) */ 270 void* pfnEVSYS_1_Handler; /* 37 Event System Interface (EVSYS) */ 271 void* pfnEVSYS_2_Handler; /* 38 Event System Interface (EVSYS) */ 272 void* pfnEVSYS_3_Handler; /* 39 Event System Interface (EVSYS) */ 273 void* pfnEVSYS_OTHER_Handler; /* 40 Event System Interface (EVSYS) */ 274 void* pfnPAC_Handler; /* 41 Peripheral Access Controller (PAC) */ 275 void* pvReserved42; 276 void* pvReserved43; 277 void* pvReserved44; 278 void* pfnRAMECC_Handler; /* 45 RAM ECC (RAMECC) */ 279 void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface (SERCOM0) */ 280 void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface (SERCOM0) */ 281 void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface (SERCOM0) */ 282 void* pfnSERCOM0_OTHER_Handler; /* 49 Serial Communication Interface (SERCOM0) */ 283 void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface (SERCOM1) */ 284 void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface (SERCOM1) */ 285 void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface (SERCOM1) */ 286 void* pfnSERCOM1_OTHER_Handler; /* 53 Serial Communication Interface (SERCOM1) */ 287 void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface (SERCOM2) */ 288 void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface (SERCOM2) */ 289 void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface (SERCOM2) */ 290 void* pfnSERCOM2_OTHER_Handler; /* 57 Serial Communication Interface (SERCOM2) */ 291 void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface (SERCOM3) */ 292 void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface (SERCOM3) */ 293 void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface (SERCOM3) */ 294 void* pfnSERCOM3_OTHER_Handler; /* 61 Serial Communication Interface (SERCOM3) */ 295 void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface (SERCOM4) */ 296 void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface (SERCOM4) */ 297 void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface (SERCOM4) */ 298 void* pfnSERCOM4_OTHER_Handler; /* 65 Serial Communication Interface (SERCOM4) */ 299 void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface (SERCOM5) */ 300 void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface (SERCOM5) */ 301 void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface (SERCOM5) */ 302 void* pfnSERCOM5_OTHER_Handler; /* 69 Serial Communication Interface (SERCOM5) */ 303 void* pvReserved70; 304 void* pvReserved71; 305 void* pvReserved72; 306 void* pvReserved73; 307 void* pvReserved74; 308 void* pvReserved75; 309 void* pvReserved76; 310 void* pvReserved77; 311 void* pvReserved78; 312 void* pvReserved79; 313 void* pfnUSB_OTHER_Handler; /* 80 Universal Serial Bus (USB) */ 314 void* pfnUSB_SOF_HSOF_Handler; /* 81 Universal Serial Bus (USB) */ 315 void* pfnUSB_TRCPT0_Handler; /* 82 Universal Serial Bus (USB) */ 316 void* pfnUSB_TRCPT1_Handler; /* 83 Universal Serial Bus (USB) */ 317 void* pfnGMAC_Handler; /* 84 Ethernet MAC (GMAC) */ 318 void* pfnTCC0_OTHER_Handler; /* 85 Timer Counter Control (TCC0) */ 319 void* pfnTCC0_MC0_Handler; /* 86 Timer Counter Control (TCC0) */ 320 void* pfnTCC0_MC1_Handler; /* 87 Timer Counter Control (TCC0) */ 321 void* pfnTCC0_MC2_Handler; /* 88 Timer Counter Control (TCC0) */ 322 void* pfnTCC0_MC3_Handler; /* 89 Timer Counter Control (TCC0) */ 323 void* pfnTCC0_MC4_Handler; /* 90 Timer Counter Control (TCC0) */ 324 void* pfnTCC0_MC5_Handler; /* 91 Timer Counter Control (TCC0) */ 325 void* pfnTCC1_OTHER_Handler; /* 92 Timer Counter Control (TCC1) */ 326 void* pfnTCC1_MC0_Handler; /* 93 Timer Counter Control (TCC1) */ 327 void* pfnTCC1_MC1_Handler; /* 94 Timer Counter Control (TCC1) */ 328 void* pfnTCC1_MC2_Handler; /* 95 Timer Counter Control (TCC1) */ 329 void* pfnTCC1_MC3_Handler; /* 96 Timer Counter Control (TCC1) */ 330 void* pfnTCC2_OTHER_Handler; /* 97 Timer Counter Control (TCC2) */ 331 void* pfnTCC2_MC0_Handler; /* 98 Timer Counter Control (TCC2) */ 332 void* pfnTCC2_MC1_Handler; /* 99 Timer Counter Control (TCC2) */ 333 void* pfnTCC2_MC2_Handler; /* 100 Timer Counter Control (TCC2) */ 334 void* pfnTCC3_OTHER_Handler; /* 101 Timer Counter Control (TCC3) */ 335 void* pfnTCC3_MC0_Handler; /* 102 Timer Counter Control (TCC3) */ 336 void* pfnTCC3_MC1_Handler; /* 103 Timer Counter Control (TCC3) */ 337 void* pfnTCC4_OTHER_Handler; /* 104 Timer Counter Control (TCC4) */ 338 void* pfnTCC4_MC0_Handler; /* 105 Timer Counter Control (TCC4) */ 339 void* pfnTCC4_MC1_Handler; /* 106 Timer Counter Control (TCC4) */ 340 void* pfnTC0_Handler; /* 107 Basic Timer Counter (TC0) */ 341 void* pfnTC1_Handler; /* 108 Basic Timer Counter (TC1) */ 342 void* pfnTC2_Handler; /* 109 Basic Timer Counter (TC2) */ 343 void* pfnTC3_Handler; /* 110 Basic Timer Counter (TC3) */ 344 void* pfnTC4_Handler; /* 111 Basic Timer Counter (TC4) */ 345 void* pfnTC5_Handler; /* 112 Basic Timer Counter (TC5) */ 346 void* pvReserved113; 347 void* pvReserved114; 348 void* pfnPDEC_OTHER_Handler; /* 115 Quadrature Decodeur (PDEC) */ 349 void* pfnPDEC_MC0_Handler; /* 116 Quadrature Decodeur (PDEC) */ 350 void* pfnPDEC_MC1_Handler; /* 117 Quadrature Decodeur (PDEC) */ 351 void* pfnADC0_OTHER_Handler; /* 118 Analog Digital Converter (ADC0) */ 352 void* pfnADC0_RESRDY_Handler; /* 119 Analog Digital Converter (ADC0) */ 353 void* pfnADC1_OTHER_Handler; /* 120 Analog Digital Converter (ADC1) */ 354 void* pfnADC1_RESRDY_Handler; /* 121 Analog Digital Converter (ADC1) */ 355 void* pfnAC_Handler; /* 122 Analog Comparators (AC) */ 356 void* pfnDAC_OTHER_Handler; /* 123 Digital-to-Analog Converter (DAC) */ 357 void* pfnDAC_EMPTY_0_Handler; /* 124 Digital-to-Analog Converter (DAC) */ 358 void* pfnDAC_EMPTY_1_Handler; /* 125 Digital-to-Analog Converter (DAC) */ 359 void* pvReserved126; 360 void* pvReserved127; 361 void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface (I2S) */ 362 void* pfnPCC_Handler; /* 129 Parallel Capture Controller (PCC) */ 363 void* pfnAES_Handler; /* 130 Advanced Encryption Standard (AES) */ 364 void* pfnTRNG_Handler; /* 131 True Random Generator (TRNG) */ 365 void* pfnICM_Handler; /* 132 Integrity Check Monitor (ICM) */ 366 void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller (PUKCC) */ 367 void* pfnQSPI_Handler; /* 134 Quad SPI interface (QSPI) */ 368 void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller (SDHC0) */ 369 } DeviceVectors; 370 371 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 372 373 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 374 #if !defined DONT_USE_PREDEFINED_CORE_HANDLERS 375 /* CORTEX-M4 exception handlers */ 376 void Reset_Handler ( void ); 377 void NonMaskableInt_Handler ( void ); 378 void HardFault_Handler ( void ); 379 void MemoryManagement_Handler ( void ); 380 void BusFault_Handler ( void ); 381 void UsageFault_Handler ( void ); 382 void SVCall_Handler ( void ); 383 void DebugMonitor_Handler ( void ); 384 void PendSV_Handler ( void ); 385 void SysTick_Handler ( void ); 386 #endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ 387 388 #if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS 389 /* Peripherals interrupt handlers */ 390 void PM_Handler ( void ); 391 void MCLK_Handler ( void ); 392 void OSCCTRL_XOSC0_Handler ( void ); 393 void OSCCTRL_XOSC1_Handler ( void ); 394 void OSCCTRL_DFLL_Handler ( void ); 395 void OSCCTRL_DPLL0_Handler ( void ); 396 void OSCCTRL_DPLL1_Handler ( void ); 397 void OSC32KCTRL_Handler ( void ); 398 void SUPC_OTHER_Handler ( void ); 399 void SUPC_BODDET_Handler ( void ); 400 void WDT_Handler ( void ); 401 void RTC_Handler ( void ); 402 void EIC_EXTINT_0_Handler ( void ); 403 void EIC_EXTINT_1_Handler ( void ); 404 void EIC_EXTINT_2_Handler ( void ); 405 void EIC_EXTINT_3_Handler ( void ); 406 void EIC_EXTINT_4_Handler ( void ); 407 void EIC_EXTINT_5_Handler ( void ); 408 void EIC_EXTINT_6_Handler ( void ); 409 void EIC_EXTINT_7_Handler ( void ); 410 void EIC_EXTINT_8_Handler ( void ); 411 void EIC_EXTINT_9_Handler ( void ); 412 void EIC_EXTINT_10_Handler ( void ); 413 void EIC_EXTINT_11_Handler ( void ); 414 void EIC_EXTINT_12_Handler ( void ); 415 void EIC_EXTINT_13_Handler ( void ); 416 void EIC_EXTINT_14_Handler ( void ); 417 void EIC_EXTINT_15_Handler ( void ); 418 void FREQM_Handler ( void ); 419 void NVMCTRL_0_Handler ( void ); 420 void NVMCTRL_1_Handler ( void ); 421 void DMAC_0_Handler ( void ); 422 void DMAC_1_Handler ( void ); 423 void DMAC_2_Handler ( void ); 424 void DMAC_3_Handler ( void ); 425 void DMAC_OTHER_Handler ( void ); 426 void EVSYS_0_Handler ( void ); 427 void EVSYS_1_Handler ( void ); 428 void EVSYS_2_Handler ( void ); 429 void EVSYS_3_Handler ( void ); 430 void EVSYS_OTHER_Handler ( void ); 431 void PAC_Handler ( void ); 432 void RAMECC_Handler ( void ); 433 void SERCOM0_0_Handler ( void ); 434 void SERCOM0_1_Handler ( void ); 435 void SERCOM0_2_Handler ( void ); 436 void SERCOM0_OTHER_Handler ( void ); 437 void SERCOM1_0_Handler ( void ); 438 void SERCOM1_1_Handler ( void ); 439 void SERCOM1_2_Handler ( void ); 440 void SERCOM1_OTHER_Handler ( void ); 441 void SERCOM2_0_Handler ( void ); 442 void SERCOM2_1_Handler ( void ); 443 void SERCOM2_2_Handler ( void ); 444 void SERCOM2_OTHER_Handler ( void ); 445 void SERCOM3_0_Handler ( void ); 446 void SERCOM3_1_Handler ( void ); 447 void SERCOM3_2_Handler ( void ); 448 void SERCOM3_OTHER_Handler ( void ); 449 void SERCOM4_0_Handler ( void ); 450 void SERCOM4_1_Handler ( void ); 451 void SERCOM4_2_Handler ( void ); 452 void SERCOM4_OTHER_Handler ( void ); 453 void SERCOM5_0_Handler ( void ); 454 void SERCOM5_1_Handler ( void ); 455 void SERCOM5_2_Handler ( void ); 456 void SERCOM5_OTHER_Handler ( void ); 457 void USB_OTHER_Handler ( void ); 458 void USB_SOF_HSOF_Handler ( void ); 459 void USB_TRCPT0_Handler ( void ); 460 void USB_TRCPT1_Handler ( void ); 461 void GMAC_Handler ( void ); 462 void TCC0_OTHER_Handler ( void ); 463 void TCC0_MC0_Handler ( void ); 464 void TCC0_MC1_Handler ( void ); 465 void TCC0_MC2_Handler ( void ); 466 void TCC0_MC3_Handler ( void ); 467 void TCC0_MC4_Handler ( void ); 468 void TCC0_MC5_Handler ( void ); 469 void TCC1_OTHER_Handler ( void ); 470 void TCC1_MC0_Handler ( void ); 471 void TCC1_MC1_Handler ( void ); 472 void TCC1_MC2_Handler ( void ); 473 void TCC1_MC3_Handler ( void ); 474 void TCC2_OTHER_Handler ( void ); 475 void TCC2_MC0_Handler ( void ); 476 void TCC2_MC1_Handler ( void ); 477 void TCC2_MC2_Handler ( void ); 478 void TCC3_OTHER_Handler ( void ); 479 void TCC3_MC0_Handler ( void ); 480 void TCC3_MC1_Handler ( void ); 481 void TCC4_OTHER_Handler ( void ); 482 void TCC4_MC0_Handler ( void ); 483 void TCC4_MC1_Handler ( void ); 484 void TC0_Handler ( void ); 485 void TC1_Handler ( void ); 486 void TC2_Handler ( void ); 487 void TC3_Handler ( void ); 488 void TC4_Handler ( void ); 489 void TC5_Handler ( void ); 490 void PDEC_OTHER_Handler ( void ); 491 void PDEC_MC0_Handler ( void ); 492 void PDEC_MC1_Handler ( void ); 493 void ADC0_OTHER_Handler ( void ); 494 void ADC0_RESRDY_Handler ( void ); 495 void ADC1_OTHER_Handler ( void ); 496 void ADC1_RESRDY_Handler ( void ); 497 void AC_Handler ( void ); 498 void DAC_OTHER_Handler ( void ); 499 void DAC_EMPTY_0_Handler ( void ); 500 void DAC_EMPTY_1_Handler ( void ); 501 void I2S_Handler ( void ); 502 void PCC_Handler ( void ); 503 void AES_Handler ( void ); 504 void TRNG_Handler ( void ); 505 void ICM_Handler ( void ); 506 void PUKCC_Handler ( void ); 507 void QSPI_Handler ( void ); 508 void SDHC0_Handler ( void ); 509 #endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ 510 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 511 512 /* Configuration of the CORTEX-M4 Processor and Core Peripherals */ 513 #define __CM4_REV 0x0001 /* Cortex-M4 Core Revision */ 514 #define __DEBUG_LVL 3 /* Debug Level */ 515 #define __FPU_PRESENT 1 /* FPU present or not */ 516 #define __MPU_PRESENT 1 /* MPU present or not */ 517 #define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */ 518 #define __TRACE_LVL 2 /* Trace Level */ 519 #define __VTOR_PRESENT 1 /* Vector Table Offset Register present or not */ 520 #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ 521 #define __ARCH_ARM 1 522 #define __ARCH_ARM_CORTEX_M 1 523 524 /* CMSIS includes */ 525 #include "core_cm4.h" 526 #if defined USE_CMSIS_INIT 527 #include "system_pic32cxsg41.h" 528 #endif /* USE_CMSIS_INIT */ 529 530 /* ************************************************************************** */ 531 /* SOFTWARE PERIPHERAL API DEFINITIONS FOR PIC32CX1025SG41064 */ 532 /* ************************************************************************** */ 533 #include "component/ac.h" 534 #include "component/adc.h" 535 #include "component/aes.h" 536 #include "component/ccl.h" 537 #include "component/cmcc.h" 538 #include "component/dac.h" 539 #include "component/dmac.h" 540 #include "component/dsu.h" 541 #include "component/eic.h" 542 #include "component/evsys.h" 543 #include "component/freqm.h" 544 #include "component/fuses.h" 545 #include "component/gclk.h" 546 #include "component/gmac.h" 547 #include "component/hmatrixb.h" 548 #include "component/i2s.h" 549 #include "component/icm.h" 550 #include "component/mclk.h" 551 #include "component/nvmctrl.h" 552 #include "component/osc32kctrl.h" 553 #include "component/oscctrl.h" 554 #include "component/pac.h" 555 #include "component/pcc.h" 556 #include "component/pdec.h" 557 #include "component/pm.h" 558 #include "component/port.h" 559 #include "component/pukcc.h" 560 #include "component/qspi.h" 561 #include "component/ramecc.h" 562 #include "component/rstc.h" 563 #include "component/rtc.h" 564 #include "component/sdhc.h" 565 #include "component/sercom.h" 566 #include "component/supc.h" 567 #include "component/tc.h" 568 #include "component/tcc.h" 569 #include "component/trng.h" 570 #include "component/usb.h" 571 #include "component/wdt.h" 572 573 /* ************************************************************************** */ 574 /* INSTANCE DEFINITIONS FOR PIC32CX1025SG41064 */ 575 /* ************************************************************************** */ 576 #include "instance/ac.h" 577 #include "instance/adc0.h" 578 #include "instance/adc1.h" 579 #include "instance/aes.h" 580 #include "instance/ccl.h" 581 #include "instance/cmcc.h" 582 #include "instance/dac.h" 583 #include "instance/dmac.h" 584 #include "instance/dsu.h" 585 #include "instance/eic.h" 586 #include "instance/evsys.h" 587 #include "instance/freqm.h" 588 #include "instance/fuses.h" 589 #include "instance/gclk.h" 590 #include "instance/gmac.h" 591 #include "instance/hmatrix.h" 592 #include "instance/i2s.h" 593 #include "instance/icm.h" 594 #include "instance/mclk.h" 595 #include "instance/nvmctrl.h" 596 #include "instance/osc32kctrl.h" 597 #include "instance/oscctrl.h" 598 #include "instance/pac.h" 599 #include "instance/pcc.h" 600 #include "instance/pdec.h" 601 #include "instance/pm.h" 602 #include "instance/port.h" 603 #include "instance/qspi.h" 604 #include "instance/ramecc.h" 605 #include "instance/rstc.h" 606 #include "instance/rtc.h" 607 #include "instance/sdhc0.h" 608 #include "instance/sercom0.h" 609 #include "instance/sercom1.h" 610 #include "instance/sercom2.h" 611 #include "instance/sercom3.h" 612 #include "instance/sercom4.h" 613 #include "instance/sercom5.h" 614 #include "instance/supc.h" 615 #include "instance/tc0.h" 616 #include "instance/tc1.h" 617 #include "instance/tc2.h" 618 #include "instance/tc3.h" 619 #include "instance/tc4.h" 620 #include "instance/tc5.h" 621 #include "instance/tcc0.h" 622 #include "instance/tcc1.h" 623 #include "instance/tcc2.h" 624 #include "instance/tcc3.h" 625 #include "instance/tcc4.h" 626 #include "instance/trng.h" 627 #include "instance/usb.h" 628 #include "instance/wdt.h" 629 630 /* ************************************************************************** */ 631 /* PERIPHERAL ID DEFINITIONS FOR PIC32CX1025SG41064 */ 632 /* ************************************************************************** */ 633 #define ID_PAC ( 0) /* Instance index for PAC (PAC) */ 634 #define ID_PM ( 1) /* Instance index for PM (PM) */ 635 #define ID_MCLK ( 2) /* Instance index for MCLK (MCLK) */ 636 #define ID_RSTC ( 3) /* Instance index for RSTC (RSTC) */ 637 #define ID_OSCCTRL ( 4) /* Instance index for OSCCTRL (OSCCTRL) */ 638 #define ID_OSC32KCTRL ( 5) /* Instance index for OSC32KCTRL (OSC32KCTRL) */ 639 #define ID_SUPC ( 6) /* Instance index for SUPC (SUPC) */ 640 #define ID_GCLK ( 7) /* Instance index for GCLK (GCLK) */ 641 #define ID_WDT ( 8) /* Instance index for WDT (WDT) */ 642 #define ID_RTC ( 9) /* Instance index for RTC (RTC) */ 643 #define ID_EIC ( 10) /* Instance index for EIC (EIC) */ 644 #define ID_FREQM ( 11) /* Instance index for FREQM (FREQM) */ 645 #define ID_SERCOM0 ( 12) /* Instance index for SERCOM0 (SERCOM0) */ 646 #define ID_SERCOM1 ( 13) /* Instance index for SERCOM1 (SERCOM1) */ 647 #define ID_TC0 ( 14) /* Instance index for TC0 (TC0) */ 648 #define ID_TC1 ( 15) /* Instance index for TC1 (TC1) */ 649 #define ID_USB ( 32) /* Instance index for USB (USB) */ 650 #define ID_DSU ( 33) /* Instance index for DSU (DSU) */ 651 #define ID_NVMCTRL ( 34) /* Instance index for NVMCTRL (NVMCTRL) */ 652 #define ID_CMCC ( 35) /* Instance index for CMCC (CMCC) */ 653 #define ID_PORT ( 36) /* Instance index for PORT (PORT) */ 654 #define ID_DMAC ( 37) /* Instance index for DMAC (DMAC) */ 655 #define ID_HMATRIX ( 38) /* Instance index for HMATRIX (HMATRIX) */ 656 #define ID_EVSYS ( 39) /* Instance index for EVSYS (EVSYS) */ 657 #define ID_SERCOM2 ( 41) /* Instance index for SERCOM2 (SERCOM2) */ 658 #define ID_SERCOM3 ( 42) /* Instance index for SERCOM3 (SERCOM3) */ 659 #define ID_TCC0 ( 43) /* Instance index for TCC0 (TCC0) */ 660 #define ID_TCC1 ( 44) /* Instance index for TCC1 (TCC1) */ 661 #define ID_TC2 ( 45) /* Instance index for TC2 (TC2) */ 662 #define ID_TC3 ( 46) /* Instance index for TC3 (TC3) */ 663 #define ID_RAMECC ( 48) /* Instance index for RAMECC (RAMECC) */ 664 #define ID_GMAC ( 66) /* Instance index for GMAC (GMAC) */ 665 #define ID_TCC2 ( 67) /* Instance index for TCC2 (TCC2) */ 666 #define ID_TCC3 ( 68) /* Instance index for TCC3 (TCC3) */ 667 #define ID_TC4 ( 69) /* Instance index for TC4 (TC4) */ 668 #define ID_TC5 ( 70) /* Basic Timer Counter (TC5) */ 669 #define ID_PDEC ( 71) /* Instance index for PDEC (PDEC) */ 670 #define ID_AC ( 72) /* Instance index for AC (AC) */ 671 #define ID_AES ( 73) /* Instance index for AES (AES) */ 672 #define ID_TRNG ( 74) /* Instance index for TRNG (TRNG) */ 673 #define ID_ICM ( 75) /* Integrity Check Monitor (ICM) */ 674 #define ID_PUKCC ( 76) /* Instance index for PUKCC (PUKCC) */ 675 #define ID_QSPI ( 77) /* Instance index for QSPI (QSPI) */ 676 #define ID_CCL ( 78) /* Instance index for CCL (CCL) */ 677 #define ID_SERCOM4 ( 96) /* Instance index for SERCOM4 (SERCOM4) */ 678 #define ID_SERCOM5 ( 97) /* Serial Communication Interface (SERCOM5) */ 679 #define ID_TCC4 (100) /* Instance index for TCC4 (TCC4) */ 680 #define ID_ADC0 (103) /* Instance index for ADC0 (ADC0) */ 681 #define ID_ADC1 (104) /* Instance index for ADC1 (ADC1) */ 682 #define ID_DAC (105) /* Instance index for DAC (DAC) */ 683 #define ID_I2S (106) /* Instance index for I2S (I2S) */ 684 #define ID_PCC (107) /* Instance index for PCC (PCC) */ 685 686 #define ID_PERIPH_MAX (107) /* Number of peripheral IDs */ 687 688 /* ************************************************************************** */ 689 /* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR PIC32CX1025SG41064 */ 690 /* ************************************************************************** */ 691 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 692 #define AC_REGS ((ac_registers_t*)0x42002000) /* AC Registers Address */ 693 #define ADC0_REGS ((adc_registers_t*)0x43001c00) /* ADC0 Registers Address */ 694 #define ADC1_REGS ((adc_registers_t*)0x43002000) /* ADC1 Registers Address */ 695 #define AES_REGS ((aes_registers_t*)0x42002400) /* AES Registers Address */ 696 #define CCL_REGS ((ccl_registers_t*)0x42003800) /* CCL Registers Address */ 697 #define CMCC_REGS ((cmcc_registers_t*)0x41006000) /* CMCC Registers Address */ 698 #define DAC_REGS ((dac_registers_t*)0x43002400) /* DAC Registers Address */ 699 #define DMAC_REGS ((dmac_registers_t*)0x4100a000) /* DMAC Registers Address */ 700 #define DSU_REGS ((dsu_registers_t*)0x41002000) /* DSU Registers Address */ 701 #define EIC_REGS ((eic_registers_t*)0x40002800) /* EIC Registers Address */ 702 #define EVSYS_REGS ((evsys_registers_t*)0x4100e000) /* EVSYS Registers Address */ 703 #define FREQM_REGS ((freqm_registers_t*)0x40002c00) /* FREQM Registers Address */ 704 #define GCLK_REGS ((gclk_registers_t*)0x40001c00) /* GCLK Registers Address */ 705 #define GMAC_REGS ((gmac_registers_t*)0x42000800) /* GMAC Registers Address */ 706 #define HMATRIX_REGS ((hmatrixb_registers_t*)0x4100c000) /* HMATRIX Registers Address */ 707 #define ICM_REGS ((icm_registers_t*)0x42002c00) /* ICM Registers Address */ 708 #define I2S_REGS ((i2s_registers_t*)0x43002800) /* I2S Registers Address */ 709 #define MCLK_REGS ((mclk_registers_t*)0x40000800) /* MCLK Registers Address */ 710 #define NVMCTRL_REGS ((nvmctrl_registers_t*)0x41004000) /* NVMCTRL Registers Address */ 711 #define SW0_FUSES_REGS ((fuses_sw0_fuses_registers_t*)0x00800080) /* FUSES Registers Address */ 712 #define USER_FUSES_REGS ((fuses_user_fuses_registers_t*)0x00804000) /* FUSES Registers Address */ 713 #define OSCCTRL_REGS ((oscctrl_registers_t*)0x40001000) /* OSCCTRL Registers Address */ 714 #define OSC32KCTRL_REGS ((osc32kctrl_registers_t*)0x40001400) /* OSC32KCTRL Registers Address */ 715 #define PAC_REGS ((pac_registers_t*)0x40000000) /* PAC Registers Address */ 716 #define PCC_REGS ((pcc_registers_t*)0x43002c00) /* PCC Registers Address */ 717 #define PDEC_REGS ((pdec_registers_t*)0x42001c00) /* PDEC Registers Address */ 718 #define PM_REGS ((pm_registers_t*)0x40000400) /* PM Registers Address */ 719 #define PORT_REGS ((port_registers_t*)0x41008000) /* PORT Registers Address */ 720 #define QSPI_REGS ((qspi_registers_t*)0x42003400) /* QSPI Registers Address */ 721 #define RAMECC_REGS ((ramecc_registers_t*)0x41020000) /* RAMECC Registers Address */ 722 #define RSTC_REGS ((rstc_registers_t*)0x40000c00) /* RSTC Registers Address */ 723 #define RTC_REGS ((rtc_registers_t*)0x40002400) /* RTC Registers Address */ 724 #define SDHC0_REGS ((sdhc_registers_t*)0x45000000) /* SDHC0 Registers Address */ 725 #define SERCOM0_REGS ((sercom_registers_t*)0x40003000) /* SERCOM0 Registers Address */ 726 #define SERCOM1_REGS ((sercom_registers_t*)0x40003400) /* SERCOM1 Registers Address */ 727 #define SERCOM2_REGS ((sercom_registers_t*)0x41012000) /* SERCOM2 Registers Address */ 728 #define SERCOM3_REGS ((sercom_registers_t*)0x41014000) /* SERCOM3 Registers Address */ 729 #define SERCOM4_REGS ((sercom_registers_t*)0x43000000) /* SERCOM4 Registers Address */ 730 #define SERCOM5_REGS ((sercom_registers_t*)0x43000400) /* SERCOM5 Registers Address */ 731 #define SUPC_REGS ((supc_registers_t*)0x40001800) /* SUPC Registers Address */ 732 #define TC0_REGS ((tc_registers_t*)0x40003800) /* TC0 Registers Address */ 733 #define TC1_REGS ((tc_registers_t*)0x40003c00) /* TC1 Registers Address */ 734 #define TC2_REGS ((tc_registers_t*)0x4101a000) /* TC2 Registers Address */ 735 #define TC3_REGS ((tc_registers_t*)0x4101c000) /* TC3 Registers Address */ 736 #define TC4_REGS ((tc_registers_t*)0x42001400) /* TC4 Registers Address */ 737 #define TC5_REGS ((tc_registers_t*)0x42001800) /* TC5 Registers Address */ 738 #define TCC0_REGS ((tcc_registers_t*)0x41016000) /* TCC0 Registers Address */ 739 #define TCC1_REGS ((tcc_registers_t*)0x41018000) /* TCC1 Registers Address */ 740 #define TCC2_REGS ((tcc_registers_t*)0x42000c00) /* TCC2 Registers Address */ 741 #define TCC3_REGS ((tcc_registers_t*)0x42001000) /* TCC3 Registers Address */ 742 #define TCC4_REGS ((tcc_registers_t*)0x43001000) /* TCC4 Registers Address */ 743 #define TRNG_REGS ((trng_registers_t*)0x42002800) /* TRNG Registers Address */ 744 #define USB_REGS ((usb_registers_t*)0x41000000) /* USB Registers Address */ 745 #define WDT_REGS ((wdt_registers_t*)0x40002000) /* WDT Registers Address */ 746 #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 747 748 /* ************************************************************************** */ 749 /* BASE ADDRESS DEFINITIONS FOR PIC32CX1025SG41064 */ 750 /* ************************************************************************** */ 751 #define AC_BASE_ADDRESS _UINT32_(0x42002000) /* AC Base Address */ 752 #define ADC0_BASE_ADDRESS _UINT32_(0x43001c00) /* ADC0 Base Address */ 753 #define ADC1_BASE_ADDRESS _UINT32_(0x43002000) /* ADC1 Base Address */ 754 #define AES_BASE_ADDRESS _UINT32_(0x42002400) /* AES Base Address */ 755 #define CCL_BASE_ADDRESS _UINT32_(0x42003800) /* CCL Base Address */ 756 #define CMCC_BASE_ADDRESS _UINT32_(0x41006000) /* CMCC Base Address */ 757 #define DAC_BASE_ADDRESS _UINT32_(0x43002400) /* DAC Base Address */ 758 #define DMAC_BASE_ADDRESS _UINT32_(0x4100a000) /* DMAC Base Address */ 759 #define DSU_BASE_ADDRESS _UINT32_(0x41002000) /* DSU Base Address */ 760 #define EIC_BASE_ADDRESS _UINT32_(0x40002800) /* EIC Base Address */ 761 #define EVSYS_BASE_ADDRESS _UINT32_(0x4100e000) /* EVSYS Base Address */ 762 #define FREQM_BASE_ADDRESS _UINT32_(0x40002c00) /* FREQM Base Address */ 763 #define GCLK_BASE_ADDRESS _UINT32_(0x40001c00) /* GCLK Base Address */ 764 #define GMAC_BASE_ADDRESS _UINT32_(0x42000800) /* GMAC Base Address */ 765 #define HMATRIX_BASE_ADDRESS _UINT32_(0x4100c000) /* HMATRIX Base Address */ 766 #define ICM_BASE_ADDRESS _UINT32_(0x42002c00) /* ICM Base Address */ 767 #define I2S_BASE_ADDRESS _UINT32_(0x43002800) /* I2S Base Address */ 768 #define MCLK_BASE_ADDRESS _UINT32_(0x40000800) /* MCLK Base Address */ 769 #define NVMCTRL_BASE_ADDRESS _UINT32_(0x41004000) /* NVMCTRL Base Address */ 770 #define SW0_FUSES_BASE_ADDRESS _UINT32_(0x00800080) /* FUSES Base Address */ 771 #define USER_FUSES_BASE_ADDRESS _UINT32_(0x00804000) /* FUSES Base Address */ 772 #define OSCCTRL_BASE_ADDRESS _UINT32_(0x40001000) /* OSCCTRL Base Address */ 773 #define OSC32KCTRL_BASE_ADDRESS _UINT32_(0x40001400) /* OSC32KCTRL Base Address */ 774 #define PAC_BASE_ADDRESS _UINT32_(0x40000000) /* PAC Base Address */ 775 #define PCC_BASE_ADDRESS _UINT32_(0x43002c00) /* PCC Base Address */ 776 #define PDEC_BASE_ADDRESS _UINT32_(0x42001c00) /* PDEC Base Address */ 777 #define PM_BASE_ADDRESS _UINT32_(0x40000400) /* PM Base Address */ 778 #define PORT_BASE_ADDRESS _UINT32_(0x41008000) /* PORT Base Address */ 779 #define QSPI_BASE_ADDRESS _UINT32_(0x42003400) /* QSPI Base Address */ 780 #define RAMECC_BASE_ADDRESS _UINT32_(0x41020000) /* RAMECC Base Address */ 781 #define RSTC_BASE_ADDRESS _UINT32_(0x40000c00) /* RSTC Base Address */ 782 #define RTC_BASE_ADDRESS _UINT32_(0x40002400) /* RTC Base Address */ 783 #define SDHC0_BASE_ADDRESS _UINT32_(0x45000000) /* SDHC0 Base Address */ 784 #define SERCOM0_BASE_ADDRESS _UINT32_(0x40003000) /* SERCOM0 Base Address */ 785 #define SERCOM1_BASE_ADDRESS _UINT32_(0x40003400) /* SERCOM1 Base Address */ 786 #define SERCOM2_BASE_ADDRESS _UINT32_(0x41012000) /* SERCOM2 Base Address */ 787 #define SERCOM3_BASE_ADDRESS _UINT32_(0x41014000) /* SERCOM3 Base Address */ 788 #define SERCOM4_BASE_ADDRESS _UINT32_(0x43000000) /* SERCOM4 Base Address */ 789 #define SERCOM5_BASE_ADDRESS _UINT32_(0x43000400) /* SERCOM5 Base Address */ 790 #define SUPC_BASE_ADDRESS _UINT32_(0x40001800) /* SUPC Base Address */ 791 #define TC0_BASE_ADDRESS _UINT32_(0x40003800) /* TC0 Base Address */ 792 #define TC1_BASE_ADDRESS _UINT32_(0x40003c00) /* TC1 Base Address */ 793 #define TC2_BASE_ADDRESS _UINT32_(0x4101a000) /* TC2 Base Address */ 794 #define TC3_BASE_ADDRESS _UINT32_(0x4101c000) /* TC3 Base Address */ 795 #define TC4_BASE_ADDRESS _UINT32_(0x42001400) /* TC4 Base Address */ 796 #define TC5_BASE_ADDRESS _UINT32_(0x42001800) /* TC5 Base Address */ 797 #define TCC0_BASE_ADDRESS _UINT32_(0x41016000) /* TCC0 Base Address */ 798 #define TCC1_BASE_ADDRESS _UINT32_(0x41018000) /* TCC1 Base Address */ 799 #define TCC2_BASE_ADDRESS _UINT32_(0x42000c00) /* TCC2 Base Address */ 800 #define TCC3_BASE_ADDRESS _UINT32_(0x42001000) /* TCC3 Base Address */ 801 #define TCC4_BASE_ADDRESS _UINT32_(0x43001000) /* TCC4 Base Address */ 802 #define TRNG_BASE_ADDRESS _UINT32_(0x42002800) /* TRNG Base Address */ 803 #define USB_BASE_ADDRESS _UINT32_(0x41000000) /* USB Base Address */ 804 #define WDT_BASE_ADDRESS _UINT32_(0x40002000) /* WDT Base Address */ 805 806 /* ************************************************************************** */ 807 /* PIO DEFINITIONS FOR PIC32CX1025SG41064 */ 808 /* ************************************************************************** */ 809 #include "pio/pic32cx1025sg41064.h" 810 811 /* ************************************************************************** */ 812 /* MEMORY MAPPING DEFINITIONS FOR PIC32CX1025SG41064 */ 813 /* ************************************************************************** */ 814 #define FLASH_SIZE _UINT32_(0x00100000) /* 1024kB Memory segment type: flash */ 815 #define FLASH_PAGE_SIZE _UINT32_( 512) 816 #define FLASH_NB_OF_PAGES _UINT32_( 2048) 817 818 #define SW0_SIZE _UINT32_(0x00000008) /* 0kB Memory segment type: fuses */ 819 #define USER_PAGE_SIZE _UINT32_(0x00000200) /* 0kB Memory segment type: user_page */ 820 #define USER_PAGE_PAGE_SIZE _UINT32_( 512) 821 #define USER_PAGE_NB_OF_PAGES _UINT32_( 1) 822 823 #define CMCC_SIZE _UINT32_(0x01000000) /* 16384kB Memory segment type: io */ 824 #define CMCC_DATARAM_SIZE _UINT32_(0x00001000) /* 4kB Memory segment type: io */ 825 #define CMCC_TAGRAM_SIZE _UINT32_(0x00000400) /* 1kB Memory segment type: io */ 826 #define CMCC_VALIDRAM_SIZE _UINT32_(0x00000040) /* 0kB Memory segment type: io */ 827 #define QSPI_SIZE _UINT32_(0x01000000) /* 16384kB Memory segment type: other */ 828 #define HSRAM_SIZE _UINT32_(0x00040000) /* 256kB Memory segment type: ram */ 829 #define HSRAM_ETB_SIZE _UINT32_(0x00008000) /* 32kB Memory segment type: ram */ 830 #define HSRAM_RET1_SIZE _UINT32_(0x00008000) /* 32kB Memory segment type: ram */ 831 #define HPB0_SIZE _UINT32_(0x00004400) /* 17kB Memory segment type: io */ 832 #define HPB1_SIZE _UINT32_(0x00022000) /* 136kB Memory segment type: io */ 833 #define HPB2_SIZE _UINT32_(0x00003c00) /* 15kB Memory segment type: io */ 834 #define HPB3_SIZE _UINT32_(0x00003000) /* 12kB Memory segment type: io */ 835 #define SEEPROM_SIZE _UINT32_(0x00020000) /* 128kB Memory segment type: io */ 836 #define SDHC0_SIZE _UINT32_(0x00000c00) /* 3kB Memory segment type: io */ 837 #define BKUPRAM_SIZE _UINT32_(0x00002000) /* 8kB Memory segment type: ram */ 838 #define PPB_SIZE _UINT32_(0x00100000) /* 1024kB Memory segment type: io */ 839 #define SCS_SIZE _UINT32_(0x00001000) /* 4kB Memory segment type: io */ 840 841 #define FLASH_ADDR _UINT32_(0x00000000) /* FLASH base address (type: flash)*/ 842 #define SW0_ADDR _UINT32_(0x00800080) /* SW0 base address (type: fuses)*/ 843 #define USER_PAGE_ADDR _UINT32_(0x00804000) /* USER_PAGE base address (type: user_page)*/ 844 #define CMCC_ADDR _UINT32_(0x03000000) /* CMCC base address (type: io)*/ 845 #define CMCC_DATARAM_ADDR _UINT32_(0x03000000) /* CMCC_DATARAM base address (type: io)*/ 846 #define CMCC_TAGRAM_ADDR _UINT32_(0x03001000) /* CMCC_TAGRAM base address (type: io)*/ 847 #define CMCC_VALIDRAM_ADDR _UINT32_(0x03002000) /* CMCC_VALIDRAM base address (type: io)*/ 848 #define QSPI_ADDR _UINT32_(0x04000000) /* QSPI base address (type: other)*/ 849 #define HSRAM_ADDR _UINT32_(0x20000000) /* HSRAM base address (type: ram)*/ 850 #define HSRAM_ETB_ADDR _UINT32_(0x20000000) /* HSRAM_ETB base address (type: ram)*/ 851 #define HSRAM_RET1_ADDR _UINT32_(0x20000000) /* HSRAM_RET1 base address (type: ram)*/ 852 #define HPB0_ADDR _UINT32_(0x40000000) /* HPB0 base address (type: io)*/ 853 #define HPB1_ADDR _UINT32_(0x41000000) /* HPB1 base address (type: io)*/ 854 #define HPB2_ADDR _UINT32_(0x42000000) /* HPB2 base address (type: io)*/ 855 #define HPB3_ADDR _UINT32_(0x43000000) /* HPB3 base address (type: io)*/ 856 #define SEEPROM_ADDR _UINT32_(0x44000000) /* SEEPROM base address (type: io)*/ 857 #define SDHC0_ADDR _UINT32_(0x45000000) /* SDHC0 base address (type: io)*/ 858 #define BKUPRAM_ADDR _UINT32_(0x47000000) /* BKUPRAM base address (type: ram)*/ 859 #define PPB_ADDR _UINT32_(0xe0000000) /* PPB base address (type: io)*/ 860 #define SCS_ADDR _UINT32_(0xe000e000) /* SCS base address (type: io)*/ 861 862 /* ************************************************************************** */ 863 /* DEVICE SIGNATURES FOR PIC32CX1025SG41064 */ 864 /* ************************************************************************** */ 865 #define CHIP_DSU_DID _UINT32_(0X61870602) 866 867 /* ************************************************************************** */ 868 /* ELECTRICAL DEFINITIONS FOR PIC32CX1025SG41064 */ 869 /* ************************************************************************** */ 870 871 /* ************************************************************************** */ 872 /* Event Generator IDs for C32CX1025SG41064 */ 873 /* ************************************************************************** */ 874 #define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_0 1 /* ID for OSCCTRL event generator XOSC_FAIL_0 */ 875 #define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_1 2 /* ID for OSCCTRL event generator XOSC_FAIL_1 */ 876 #define EVENT_ID_GEN_OSC32KCTRL_XOSC32K_FAIL 3 /* ID for OSC32KCTRL event generator XOSC32K_FAIL */ 877 #define EVENT_ID_GEN_RTC_PER_0 4 /* ID for RTC event generator PER_0 */ 878 #define EVENT_ID_GEN_RTC_PER_1 5 /* ID for RTC event generator PER_1 */ 879 #define EVENT_ID_GEN_RTC_PER_2 6 /* ID for RTC event generator PER_2 */ 880 #define EVENT_ID_GEN_RTC_PER_3 7 /* ID for RTC event generator PER_3 */ 881 #define EVENT_ID_GEN_RTC_PER_4 8 /* ID for RTC event generator PER_4 */ 882 #define EVENT_ID_GEN_RTC_PER_5 9 /* ID for RTC event generator PER_5 */ 883 #define EVENT_ID_GEN_RTC_PER_6 10 /* ID for RTC event generator PER_6 */ 884 #define EVENT_ID_GEN_RTC_PER_7 11 /* ID for RTC event generator PER_7 */ 885 #define EVENT_ID_GEN_RTC_CMP_0 12 /* ID for RTC event generator CMP_0 */ 886 #define EVENT_ID_GEN_RTC_CMP_1 13 /* ID for RTC event generator CMP_1 */ 887 #define EVENT_ID_GEN_RTC_CMP_2 14 /* ID for RTC event generator CMP_2 */ 888 #define EVENT_ID_GEN_RTC_CMP_3 15 /* ID for RTC event generator CMP_3 */ 889 #define EVENT_ID_GEN_RTC_TAMPER 16 /* ID for RTC event generator TAMPER */ 890 #define EVENT_ID_GEN_RTC_OVF 17 /* ID for RTC event generator OVF */ 891 #define EVENT_ID_GEN_EIC_EXTINT_0 18 /* ID for EIC event generator EXTINT_0 */ 892 #define EVENT_ID_GEN_EIC_EXTINT_1 19 /* ID for EIC event generator EXTINT_1 */ 893 #define EVENT_ID_GEN_EIC_EXTINT_2 20 /* ID for EIC event generator EXTINT_2 */ 894 #define EVENT_ID_GEN_EIC_EXTINT_3 21 /* ID for EIC event generator EXTINT_3 */ 895 #define EVENT_ID_GEN_EIC_EXTINT_4 22 /* ID for EIC event generator EXTINT_4 */ 896 #define EVENT_ID_GEN_EIC_EXTINT_5 23 /* ID for EIC event generator EXTINT_5 */ 897 #define EVENT_ID_GEN_EIC_EXTINT_6 24 /* ID for EIC event generator EXTINT_6 */ 898 #define EVENT_ID_GEN_EIC_EXTINT_7 25 /* ID for EIC event generator EXTINT_7 */ 899 #define EVENT_ID_GEN_EIC_EXTINT_8 26 /* ID for EIC event generator EXTINT_8 */ 900 #define EVENT_ID_GEN_EIC_EXTINT_9 27 /* ID for EIC event generator EXTINT_9 */ 901 #define EVENT_ID_GEN_EIC_EXTINT_10 28 /* ID for EIC event generator EXTINT_10 */ 902 #define EVENT_ID_GEN_EIC_EXTINT_11 29 /* ID for EIC event generator EXTINT_11 */ 903 #define EVENT_ID_GEN_EIC_EXTINT_12 30 /* ID for EIC event generator EXTINT_12 */ 904 #define EVENT_ID_GEN_EIC_EXTINT_13 31 /* ID for EIC event generator EXTINT_13 */ 905 #define EVENT_ID_GEN_EIC_EXTINT_14 32 /* ID for EIC event generator EXTINT_14 */ 906 #define EVENT_ID_GEN_EIC_EXTINT_15 33 /* ID for EIC event generator EXTINT_15 */ 907 #define EVENT_ID_GEN_DMAC_CH_0 34 /* ID for DMAC event generator CH_0 */ 908 #define EVENT_ID_GEN_DMAC_CH_1 35 /* ID for DMAC event generator CH_1 */ 909 #define EVENT_ID_GEN_DMAC_CH_2 36 /* ID for DMAC event generator CH_2 */ 910 #define EVENT_ID_GEN_DMAC_CH_3 37 /* ID for DMAC event generator CH_3 */ 911 #define EVENT_ID_GEN_PAC_ACCERR 38 /* ID for PAC event generator ACCERR */ 912 #define EVENT_ID_GEN_TCC0_OVF 41 /* ID for TCC0 event generator OVF */ 913 #define EVENT_ID_GEN_TCC0_TRG 42 /* ID for TCC0 event generator TRG */ 914 #define EVENT_ID_GEN_TCC0_CNT 43 /* ID for TCC0 event generator CNT */ 915 #define EVENT_ID_GEN_TCC0_MC_0 44 /* ID for TCC0 event generator MC_0 */ 916 #define EVENT_ID_GEN_TCC0_MC_1 45 /* ID for TCC0 event generator MC_1 */ 917 #define EVENT_ID_GEN_TCC0_MC_2 46 /* ID for TCC0 event generator MC_2 */ 918 #define EVENT_ID_GEN_TCC0_MC_3 47 /* ID for TCC0 event generator MC_3 */ 919 #define EVENT_ID_GEN_TCC0_MC_4 48 /* ID for TCC0 event generator MC_4 */ 920 #define EVENT_ID_GEN_TCC0_MC_5 49 /* ID for TCC0 event generator MC_5 */ 921 #define EVENT_ID_GEN_TCC1_OVF 50 /* ID for TCC1 event generator OVF */ 922 #define EVENT_ID_GEN_TCC1_TRG 51 /* ID for TCC1 event generator TRG */ 923 #define EVENT_ID_GEN_TCC1_CNT 52 /* ID for TCC1 event generator CNT */ 924 #define EVENT_ID_GEN_TCC1_MC_0 53 /* ID for TCC1 event generator MC_0 */ 925 #define EVENT_ID_GEN_TCC1_MC_1 54 /* ID for TCC1 event generator MC_1 */ 926 #define EVENT_ID_GEN_TCC1_MC_2 55 /* ID for TCC1 event generator MC_2 */ 927 #define EVENT_ID_GEN_TCC1_MC_3 56 /* ID for TCC1 event generator MC_3 */ 928 #define EVENT_ID_GEN_TCC2_OVF 57 /* ID for TCC2 event generator OVF */ 929 #define EVENT_ID_GEN_TCC2_TRG 58 /* ID for TCC2 event generator TRG */ 930 #define EVENT_ID_GEN_TCC2_CNT 59 /* ID for TCC2 event generator CNT */ 931 #define EVENT_ID_GEN_TCC2_MC_0 60 /* ID for TCC2 event generator MC_0 */ 932 #define EVENT_ID_GEN_TCC2_MC_1 61 /* ID for TCC2 event generator MC_1 */ 933 #define EVENT_ID_GEN_TCC2_MC_2 62 /* ID for TCC2 event generator MC_2 */ 934 #define EVENT_ID_GEN_TCC3_OVF 63 /* ID for TCC3 event generator OVF */ 935 #define EVENT_ID_GEN_TCC3_TRG 64 /* ID for TCC3 event generator TRG */ 936 #define EVENT_ID_GEN_TCC3_CNT 65 /* ID for TCC3 event generator CNT */ 937 #define EVENT_ID_GEN_TCC3_MC_0 66 /* ID for TCC3 event generator MC_0 */ 938 #define EVENT_ID_GEN_TCC3_MC_1 67 /* ID for TCC3 event generator MC_1 */ 939 #define EVENT_ID_GEN_TCC4_OVF 68 /* ID for TCC4 event generator OVF */ 940 #define EVENT_ID_GEN_TCC4_TRG 69 /* ID for TCC4 event generator TRG */ 941 #define EVENT_ID_GEN_TCC4_CNT 70 /* ID for TCC4 event generator CNT */ 942 #define EVENT_ID_GEN_TCC4_MC_0 71 /* ID for TCC4 event generator MC_0 */ 943 #define EVENT_ID_GEN_TCC4_MC_1 72 /* ID for TCC4 event generator MC_1 */ 944 #define EVENT_ID_GEN_TC0_OVF 73 /* ID for TC0 event generator OVF */ 945 #define EVENT_ID_GEN_TC0_MC_0 74 /* ID for TC0 event generator MC_0 */ 946 #define EVENT_ID_GEN_TC0_MC_1 75 /* ID for TC0 event generator MC_1 */ 947 #define EVENT_ID_GEN_TC1_OVF 76 /* ID for TC1 event generator OVF */ 948 #define EVENT_ID_GEN_TC1_MC_0 77 /* ID for TC1 event generator MC_0 */ 949 #define EVENT_ID_GEN_TC1_MC_1 78 /* ID for TC1 event generator MC_1 */ 950 #define EVENT_ID_GEN_TC2_OVF 79 /* ID for TC2 event generator OVF */ 951 #define EVENT_ID_GEN_TC2_MC_0 80 /* ID for TC2 event generator MC_0 */ 952 #define EVENT_ID_GEN_TC2_MC_1 81 /* ID for TC2 event generator MC_1 */ 953 #define EVENT_ID_GEN_TC3_OVF 82 /* ID for TC3 event generator OVF */ 954 #define EVENT_ID_GEN_TC3_MC_0 83 /* ID for TC3 event generator MC_0 */ 955 #define EVENT_ID_GEN_TC3_MC_1 84 /* ID for TC3 event generator MC_1 */ 956 #define EVENT_ID_GEN_TC4_OVF 85 /* ID for TC4 event generator OVF */ 957 #define EVENT_ID_GEN_TC4_MC_0 86 /* ID for TC4 event generator MC_0 */ 958 #define EVENT_ID_GEN_TC4_MC_1 87 /* ID for TC4 event generator MC_1 */ 959 #define EVENT_ID_GEN_TC5_OVF 88 /* ID for TC5 event generator OVF */ 960 #define EVENT_ID_GEN_TC5_MC_0 89 /* ID for TC5 event generator MC_0 */ 961 #define EVENT_ID_GEN_TC5_MC_1 90 /* ID for TC5 event generator MC_1 */ 962 #define EVENT_ID_GEN_PDEC_OVF 97 /* ID for PDEC event generator OVF */ 963 #define EVENT_ID_GEN_PDEC_ERR 98 /* ID for PDEC event generator ERR */ 964 #define EVENT_ID_GEN_PDEC_DIR 99 /* ID for PDEC event generator DIR */ 965 #define EVENT_ID_GEN_PDEC_VLC 100 /* ID for PDEC event generator VLC */ 966 #define EVENT_ID_GEN_PDEC_MC_0 101 /* ID for PDEC event generator MC_0 */ 967 #define EVENT_ID_GEN_PDEC_MC_1 102 /* ID for PDEC event generator MC_1 */ 968 #define EVENT_ID_GEN_ADC0_RESRDY 103 /* ID for ADC0 event generator RESRDY */ 969 #define EVENT_ID_GEN_ADC0_WINMON 104 /* ID for ADC0 event generator WINMON */ 970 #define EVENT_ID_GEN_ADC1_RESRDY 105 /* ID for ADC1 event generator RESRDY */ 971 #define EVENT_ID_GEN_ADC1_WINMON 106 /* ID for ADC1 event generator WINMON */ 972 #define EVENT_ID_GEN_AC_COMP_0 107 /* ID for AC event generator COMP_0 */ 973 #define EVENT_ID_GEN_AC_COMP_1 108 /* ID for AC event generator COMP_1 */ 974 #define EVENT_ID_GEN_AC_WIN_0 109 /* ID for AC event generator WIN_0 */ 975 #define EVENT_ID_GEN_DAC_EMPTY_0 110 /* ID for DAC event generator EMPTY_0 */ 976 #define EVENT_ID_GEN_DAC_EMPTY_1 111 /* ID for DAC event generator EMPTY_1 */ 977 #define EVENT_ID_GEN_GMAC_TSU_CMP 114 /* ID for GMAC event generator TSU_CMP */ 978 #define EVENT_ID_GEN_TRNG_READY 115 /* ID for TRNG event generator READY */ 979 #define EVENT_ID_GEN_CCL_LUTOUT_0 116 /* ID for CCL event generator LUTOUT_0 */ 980 #define EVENT_ID_GEN_CCL_LUTOUT_1 117 /* ID for CCL event generator LUTOUT_1 */ 981 #define EVENT_ID_GEN_CCL_LUTOUT_2 118 /* ID for CCL event generator LUTOUT_2 */ 982 #define EVENT_ID_GEN_CCL_LUTOUT_3 119 /* ID for CCL event generator LUTOUT_3 */ 983 984 /* ************************************************************************** */ 985 /* Event User IDs for C32CX1025SG41064 */ 986 /* ************************************************************************** */ 987 #define EVENT_ID_USER_RTC_TAMPER 0 /* ID for RTC event user TAMPER */ 988 #define EVENT_ID_USER_PORT_EV_0 1 /* ID for PORT event user EV_0 */ 989 #define EVENT_ID_USER_PORT_EV_1 2 /* ID for PORT event user EV_1 */ 990 #define EVENT_ID_USER_PORT_EV_2 3 /* ID for PORT event user EV_2 */ 991 #define EVENT_ID_USER_PORT_EV_3 4 /* ID for PORT event user EV_3 */ 992 #define EVENT_ID_USER_DMAC_CH_0 5 /* ID for DMAC event user CH_0 */ 993 #define EVENT_ID_USER_DMAC_CH_1 6 /* ID for DMAC event user CH_1 */ 994 #define EVENT_ID_USER_DMAC_CH_2 7 /* ID for DMAC event user CH_2 */ 995 #define EVENT_ID_USER_DMAC_CH_3 8 /* ID for DMAC event user CH_3 */ 996 #define EVENT_ID_USER_DMAC_CH_4 9 /* ID for DMAC event user CH_4 */ 997 #define EVENT_ID_USER_DMAC_CH_5 10 /* ID for DMAC event user CH_5 */ 998 #define EVENT_ID_USER_DMAC_CH_6 11 /* ID for DMAC event user CH_6 */ 999 #define EVENT_ID_USER_DMAC_CH_7 12 /* ID for DMAC event user CH_7 */ 1000 #define EVENT_ID_USER_CM4_TRACE_START 14 /* ID for CM4 event user TRACE_START */ 1001 #define EVENT_ID_USER_CM4_TRACE_STOP 15 /* ID for CM4 event user TRACE_STOP */ 1002 #define EVENT_ID_USER_CM4_TRACE_TRIG 16 /* ID for CM4 event user TRACE_TRIG */ 1003 #define EVENT_ID_USER_TCC0_EV_0 17 /* ID for TCC0 event user EV_0 */ 1004 #define EVENT_ID_USER_TCC0_EV_1 18 /* ID for TCC0 event user EV_1 */ 1005 #define EVENT_ID_USER_TCC0_MC_0 19 /* ID for TCC0 event user MC_0 */ 1006 #define EVENT_ID_USER_TCC0_MC_1 20 /* ID for TCC0 event user MC_1 */ 1007 #define EVENT_ID_USER_TCC0_MC_2 21 /* ID for TCC0 event user MC_2 */ 1008 #define EVENT_ID_USER_TCC0_MC_3 22 /* ID for TCC0 event user MC_3 */ 1009 #define EVENT_ID_USER_TCC0_MC_4 23 /* ID for TCC0 event user MC_4 */ 1010 #define EVENT_ID_USER_TCC0_MC_5 24 /* ID for TCC0 event user MC_5 */ 1011 #define EVENT_ID_USER_TCC1_EV_0 25 /* ID for TCC1 event user EV_0 */ 1012 #define EVENT_ID_USER_TCC1_EV_1 26 /* ID for TCC1 event user EV_1 */ 1013 #define EVENT_ID_USER_TCC1_MC_0 27 /* ID for TCC1 event user MC_0 */ 1014 #define EVENT_ID_USER_TCC1_MC_1 28 /* ID for TCC1 event user MC_1 */ 1015 #define EVENT_ID_USER_TCC1_MC_2 29 /* ID for TCC1 event user MC_2 */ 1016 #define EVENT_ID_USER_TCC1_MC_3 30 /* ID for TCC1 event user MC_3 */ 1017 #define EVENT_ID_USER_TCC2_EV_0 31 /* ID for TCC2 event user EV_0 */ 1018 #define EVENT_ID_USER_TCC2_EV_1 32 /* ID for TCC2 event user EV_1 */ 1019 #define EVENT_ID_USER_TCC2_MC_0 33 /* ID for TCC2 event user MC_0 */ 1020 #define EVENT_ID_USER_TCC2_MC_1 34 /* ID for TCC2 event user MC_1 */ 1021 #define EVENT_ID_USER_TCC2_MC_2 35 /* ID for TCC2 event user MC_2 */ 1022 #define EVENT_ID_USER_TCC3_EV_0 36 /* ID for TCC3 event user EV_0 */ 1023 #define EVENT_ID_USER_TCC3_EV_1 37 /* ID for TCC3 event user EV_1 */ 1024 #define EVENT_ID_USER_TCC3_MC_0 38 /* ID for TCC3 event user MC_0 */ 1025 #define EVENT_ID_USER_TCC3_MC_1 39 /* ID for TCC3 event user MC_1 */ 1026 #define EVENT_ID_USER_TCC4_EV_0 40 /* ID for TCC4 event user EV_0 */ 1027 #define EVENT_ID_USER_TCC4_EV_1 41 /* ID for TCC4 event user EV_1 */ 1028 #define EVENT_ID_USER_TCC4_MC_0 42 /* ID for TCC4 event user MC_0 */ 1029 #define EVENT_ID_USER_TCC4_MC_1 43 /* ID for TCC4 event user MC_1 */ 1030 #define EVENT_ID_USER_TC0_EVU 44 /* ID for TC0 event user EVU */ 1031 #define EVENT_ID_USER_TC1_EVU 45 /* ID for TC1 event user EVU */ 1032 #define EVENT_ID_USER_TC2_EVU 46 /* ID for TC2 event user EVU */ 1033 #define EVENT_ID_USER_TC3_EVU 47 /* ID for TC3 event user EVU */ 1034 #define EVENT_ID_USER_TC4_EVU 48 /* ID for TC4 event user EVU */ 1035 #define EVENT_ID_USER_TC5_EVU 49 /* ID for TC5 event user EVU */ 1036 #define EVENT_ID_USER_PDEC_EVU_0 52 /* ID for PDEC event user EVU_0 */ 1037 #define EVENT_ID_USER_PDEC_EVU_1 53 /* ID for PDEC event user EVU_1 */ 1038 #define EVENT_ID_USER_PDEC_EVU_2 54 /* ID for PDEC event user EVU_2 */ 1039 #define EVENT_ID_USER_ADC0_START 55 /* ID for ADC0 event user START */ 1040 #define EVENT_ID_USER_ADC0_SYNC 56 /* ID for ADC0 event user SYNC */ 1041 #define EVENT_ID_USER_ADC1_START 57 /* ID for ADC1 event user START */ 1042 #define EVENT_ID_USER_ADC1_SYNC 58 /* ID for ADC1 event user SYNC */ 1043 #define EVENT_ID_USER_AC_SOC_0 59 /* ID for AC event user SOC_0 */ 1044 #define EVENT_ID_USER_AC_SOC_1 60 /* ID for AC event user SOC_1 */ 1045 #define EVENT_ID_USER_DAC_START_0 61 /* ID for DAC event user START_0 */ 1046 #define EVENT_ID_USER_DAC_START_1 62 /* ID for DAC event user START_1 */ 1047 #define EVENT_ID_USER_CCL_LUTIN_0 63 /* ID for CCL event user LUTIN_0 */ 1048 #define EVENT_ID_USER_CCL_LUTIN_1 64 /* ID for CCL event user LUTIN_1 */ 1049 #define EVENT_ID_USER_CCL_LUTIN_2 65 /* ID for CCL event user LUTIN_2 */ 1050 #define EVENT_ID_USER_CCL_LUTIN_3 66 /* ID for CCL event user LUTIN_3 */ 1051 1052 #ifdef __cplusplus 1053 } 1054 #endif 1055 1056 #endif /* _PIC32CX1025SG41064_H_ */ 1057 1058
