1 /* 2 * Instance header file for PIC32CX1025SG41128 3 * 4 * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 */ 19 20 /* file generated from device description file (ATDF) version 2023-03-17T09:48:34Z */ 21 #ifndef _PIC32CXSG41_SERCOM1_INSTANCE_ 22 #define _PIC32CXSG41_SERCOM1_INSTANCE_ 23 24 25 /* ========== Instance Parameter definitions for SERCOM1 peripheral ========== */ 26 #define SERCOM1_CLK_REDUCTION (1) /* Reduce clock options to pin 1 for SPI and USART */ 27 #define SERCOM1_DLY_COMPENSATION (1) /* Compensates for a fast DLY50 element. Assuming 20ns */ 28 #define SERCOM1_DMA (1) /* DMA support implemented? */ 29 #define SERCOM1_DMAC_ID_RX (6) /* Index of DMA RX trigger */ 30 #define SERCOM1_DMAC_ID_TX (7) /* Index of DMA TX trigger */ 31 #define SERCOM1_FIFO_DEPTH_POWER (1) /* 2^FIFO_DEPTH_POWER gives rx FIFO depth. */ 32 #define SERCOM1_GCLK_ID_CORE (8) 33 #define SERCOM1_GCLK_ID_SLOW (3) 34 #define SERCOM1_I2CM (1) /* I2C Master mode implemented? */ 35 #define SERCOM1_I2CS (1) /* I2C Slave mode implemented? */ 36 #define SERCOM1_I2CS_AUTO_ACK (1) /* I2C slave automatic acknowledge implemented? */ 37 #define SERCOM1_I2CS_GROUP_CMD (1) /* I2C slave group command implemented? */ 38 #define SERCOM1_I2CS_SDASETUP_CNT_SIZE (8) /* I2CS sda setup count size */ 39 #define SERCOM1_I2CS_SDASETUP_SIZE (4) /* I2CS sda setup size */ 40 #define SERCOM1_I2CS_SUDAT (1) /* I2C slave SDA setup implemented? */ 41 #define SERCOM1_I2C_0_INT_SRC (50) /* I2C 0 Interrupt */ 42 #define SERCOM1_I2C_1_INT_SRC (51) /* I2C 1 Interrupt */ 43 #define SERCOM1_I2C_2_INT_SRC (52) /* I2C 2 Interrupt */ 44 #define SERCOM1_I2C_3_INT_SRC (53) /* I2C 3 Interrupt */ 45 #define SERCOM1_I2C_FASTMP (1) /* I2C fast mode plus implemented? */ 46 #define SERCOM1_I2C_HSMODE (1) /* USART mode implemented? */ 47 #define SERCOM1_I2C_SCLSM_MODE (1) /* I2C SCL clock stretch mode implemented? */ 48 #define SERCOM1_I2C_SMB_TIMEOUTS (1) /* I2C SMBus timeouts implemented? */ 49 #define SERCOM1_I2C_TENBIT_ADR (1) /* I2C ten bit enabled? */ 50 #define SERCOM1_INSTANCE_ID (13) /* Instance index for SERCOM1 */ 51 #define SERCOM1_INT_MSB (6) 52 #define SERCOM1_PMSB (3) 53 #define SERCOM1_RETENTION_SUPPORT (0) /* Retention supported? */ 54 #define SERCOM1_SE_CNT (1) /* SE counter included? */ 55 #define SERCOM1_SPI (1) /* SPI mode implemented? */ 56 #define SERCOM1_SPI_ERROR_INT_SRC (53) /* SPI ERROR Interrupt */ 57 #define SERCOM1_SPI_HW_SS_CTRL (1) /* Master _SS hardware control implemented? */ 58 #define SERCOM1_SPI_ICSPACE_EXT (1) /* SPI inter character space implemented? */ 59 #define SERCOM1_SPI_OZMO (0) /* OZMO features implemented? */ 60 #define SERCOM1_SPI_RX_INT_SRC (52) /* SPI RX Interrupt */ 61 #define SERCOM1_SPI_TX_COMPLETE_INT_SRC (51) /* SPI TX COMPLETE Interrupt */ 62 #define SERCOM1_SPI_TX_READY_INT_SRC (50) /* SPI TX READY Interrupt */ 63 #define SERCOM1_SPI_WAKE_ON_SSL (1) /* _SS low detect implemented? */ 64 #define SERCOM1_TTBIT_EXTENSION (1) /* 32-bit extension implemented? */ 65 #define SERCOM1_USART (1) /* USART mode implemented? */ 66 #define SERCOM1_USART_AUTOBAUD (1) /* USART autobaud implemented? */ 67 #define SERCOM1_USART_COLDET (1) /* USART collision detection implemented? */ 68 #define SERCOM1_USART_ERROR_INT_SRC (53) /* USART ERROR Interrupt */ 69 #define SERCOM1_USART_FLOW_CTRL (1) /* USART flow control implemented? */ 70 #define SERCOM1_USART_FRAC_BAUD (1) /* USART fractional BAUD implemented? */ 71 #define SERCOM1_USART_IRDA (1) /* USART IrDA implemented? */ 72 #define SERCOM1_USART_ISO7816 (1) /* USART ISO7816 mode implemented? */ 73 #define SERCOM1_USART_LIN_MASTER (1) /* USART LIN Master mode implemented? */ 74 #define SERCOM1_USART_RS485 (1) /* USART RS485 mode implemented? */ 75 #define SERCOM1_USART_RX_INT_SRC (52) /* USART RX Interrupt */ 76 #define SERCOM1_USART_SAMPA_EXT (1) /* USART sample adjust implemented? */ 77 #define SERCOM1_USART_SAMPR_EXT (1) /* USART oversampling adjustment implemented? */ 78 #define SERCOM1_USART_TX_COMPLETE_INT_SRC (51) /* USART TX COMPLETE Interrupt */ 79 #define SERCOM1_USART_TX_READY_INT_SRC (50) /* USART TX READY Interrupt */ 80 81 #endif /* _PIC32CXSG41_SERCOM1_INSTANCE_ */ 82
