1 /* 2 * Instance header file for PIC32CX1025SG41128 3 * 4 * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 */ 19 20 /* file generated from device description file (ATDF) version 2023-03-17T09:48:34Z */ 21 #ifndef _PIC32CXSG41_DMAC_INSTANCE_ 22 #define _PIC32CXSG41_DMAC_INSTANCE_ 23 24 25 /* ========== Instance Parameter definitions for DMAC peripheral ========== */ 26 #define DMAC_BURST (1) /* 0: no burst support; 1: burst support */ 27 #define DMAC_CHANNEL0_INT_SRC (31) /* DMA Channel 0 Interrupt */ 28 #define DMAC_CHANNEL10_INT_SRC (35) /* DMA Channel 10 Interrupt */ 29 #define DMAC_CHANNEL11_INT_SRC (35) /* DMA Channel 11 Interrupt */ 30 #define DMAC_CHANNEL12_INT_SRC (35) /* DMA Channel 12 Interrupt */ 31 #define DMAC_CHANNEL13_INT_SRC (35) /* DMA Channel 13 Interrupt */ 32 #define DMAC_CHANNEL14_INT_SRC (35) /* DMA Channel 14 Interrupt */ 33 #define DMAC_CHANNEL15_INT_SRC (35) /* DMA Channel 15 Interrupt */ 34 #define DMAC_CHANNEL16_INT_SRC (35) /* DMA Channel 16 Interrupt */ 35 #define DMAC_CHANNEL17_INT_SRC (35) /* DMA Channel 17 Interrupt */ 36 #define DMAC_CHANNEL18_INT_SRC (35) /* DMA Channel 18 Interrupt */ 37 #define DMAC_CHANNEL19_INT_SRC (35) /* DMA Channel 19 Interrupt */ 38 #define DMAC_CHANNEL1_INT_SRC (32) /* DMA Channel 1 Interrupt */ 39 #define DMAC_CHANNEL20_INT_SRC (35) /* DMA Channel 20 Interrupt */ 40 #define DMAC_CHANNEL21_INT_SRC (35) /* DMA Channel 21 Interrupt */ 41 #define DMAC_CHANNEL22_INT_SRC (35) /* DMA Channel 22 Interrupt */ 42 #define DMAC_CHANNEL23_INT_SRC (35) /* DMA Channel 23 Interrupt */ 43 #define DMAC_CHANNEL24_INT_SRC (35) /* DMA Channel 24 Interrupt */ 44 #define DMAC_CHANNEL25_INT_SRC (35) /* DMA Channel 25 Interrupt */ 45 #define DMAC_CHANNEL26_INT_SRC (35) /* DMA Channel 26 Interrupt */ 46 #define DMAC_CHANNEL27_INT_SRC (35) /* DMA Channel 27 Interrupt */ 47 #define DMAC_CHANNEL28_INT_SRC (35) /* DMA Channel 28 Interrupt */ 48 #define DMAC_CHANNEL29_INT_SRC (35) /* DMA Channel 29 Interrupt */ 49 #define DMAC_CHANNEL2_INT_SRC (33) /* DMA Channel 2 Interrupt */ 50 #define DMAC_CHANNEL30_INT_SRC (35) /* DMA Channel 30 Interrupt */ 51 #define DMAC_CHANNEL31_INT_SRC (35) /* DMA Channel 31 Interrupt */ 52 #define DMAC_CHANNEL3_INT_SRC (34) /* DMA Channel 3 Interrupt */ 53 #define DMAC_CHANNEL4_INT_SRC (35) /* DMA Channel 4 Interrupt */ 54 #define DMAC_CHANNEL5_INT_SRC (35) /* DMA Channel 5 Interrupt */ 55 #define DMAC_CHANNEL6_INT_SRC (35) /* DMA Channel 6 Interrupt */ 56 #define DMAC_CHANNEL7_INT_SRC (35) /* DMA Channel 7 Interrupt */ 57 #define DMAC_CHANNEL8_INT_SRC (35) /* DMA Channel 8 Interrupt */ 58 #define DMAC_CHANNEL9_INT_SRC (35) /* DMA Channel 9 Interrupt */ 59 #define DMAC_CH_BITS (5) /* Number of bits to select channel */ 60 #define DMAC_CH_NUM (32) /* Number of channels */ 61 #define DMAC_EVIN_NUM (8) /* Number of input events */ 62 #define DMAC_EVOUT_NUM (4) /* Number of output events */ 63 #define DMAC_FIFO_SIZE (16) /* FIFO size for burst mode. */ 64 #define DMAC_INSTANCE_ID (37) /* Instance index for DMAC */ 65 #define DMAC_LVL_BITS (2) /* Number of bits to select level priority */ 66 #define DMAC_LVL_NUM (4) /* Enable priority level number */ 67 #define DMAC_QOSCTRL_D_RESETVALUE (2) /* QOS dmac ahb interface reset value */ 68 #define DMAC_QOSCTRL_F_RESETVALUE (2) /* QOS dmac fetch interface reset value */ 69 #define DMAC_QOSCTRL_WRB_RESETVALUE (2) /* QOS dmac write back interface reset value */ 70 #define DMAC_TRIG_BITS (7) /* Number of bits to select trigger source */ 71 #define DMAC_TRIG_NUM (85) /* Number of peripheral triggers */ 72 73 #endif /* _PIC32CXSG41_DMAC_INSTANCE_ */ 74
