1 /* 2 * Component description for TCC 3 * 4 * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 */ 19 20 /* file generated from device description file (ATDF) version 2023-03-17T09:48:34Z */ 21 #ifndef _PIC32CXSG41_TCC_COMPONENT_H_ 22 #define _PIC32CXSG41_TCC_COMPONENT_H_ 23 24 /* ************************************************************************** */ 25 /* SOFTWARE API DEFINITION FOR TCC */ 26 /* ************************************************************************** */ 27 28 /* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */ 29 #define TCC_CTRLA_RESETVALUE _UINT32_(0x00) /* (TCC_CTRLA) Control A Reset Value */ 30 31 #define TCC_CTRLA_SWRST_Pos _UINT32_(0) /* (TCC_CTRLA) Software Reset Position */ 32 #define TCC_CTRLA_SWRST_Msk (_UINT32_(0x1) << TCC_CTRLA_SWRST_Pos) /* (TCC_CTRLA) Software Reset Mask */ 33 #define TCC_CTRLA_SWRST(value) (TCC_CTRLA_SWRST_Msk & (_UINT32_(value) << TCC_CTRLA_SWRST_Pos)) /* Assignment of value for SWRST in the TCC_CTRLA register */ 34 #define TCC_CTRLA_ENABLE_Pos _UINT32_(1) /* (TCC_CTRLA) Enable Position */ 35 #define TCC_CTRLA_ENABLE_Msk (_UINT32_(0x1) << TCC_CTRLA_ENABLE_Pos) /* (TCC_CTRLA) Enable Mask */ 36 #define TCC_CTRLA_ENABLE(value) (TCC_CTRLA_ENABLE_Msk & (_UINT32_(value) << TCC_CTRLA_ENABLE_Pos)) /* Assignment of value for ENABLE in the TCC_CTRLA register */ 37 #define TCC_CTRLA_RESOLUTION_Pos _UINT32_(5) /* (TCC_CTRLA) Enhanced Resolution Position */ 38 #define TCC_CTRLA_RESOLUTION_Msk (_UINT32_(0x3) << TCC_CTRLA_RESOLUTION_Pos) /* (TCC_CTRLA) Enhanced Resolution Mask */ 39 #define TCC_CTRLA_RESOLUTION(value) (TCC_CTRLA_RESOLUTION_Msk & (_UINT32_(value) << TCC_CTRLA_RESOLUTION_Pos)) /* Assignment of value for RESOLUTION in the TCC_CTRLA register */ 40 #define TCC_CTRLA_RESOLUTION_NONE_Val _UINT32_(0x0) /* (TCC_CTRLA) Dithering is disabled */ 41 #define TCC_CTRLA_RESOLUTION_DITH4_Val _UINT32_(0x1) /* (TCC_CTRLA) Dithering is done every 16 PWM frames */ 42 #define TCC_CTRLA_RESOLUTION_DITH5_Val _UINT32_(0x2) /* (TCC_CTRLA) Dithering is done every 32 PWM frames */ 43 #define TCC_CTRLA_RESOLUTION_DITH6_Val _UINT32_(0x3) /* (TCC_CTRLA) Dithering is done every 64 PWM frames */ 44 #define TCC_CTRLA_RESOLUTION_NONE (TCC_CTRLA_RESOLUTION_NONE_Val << TCC_CTRLA_RESOLUTION_Pos) /* (TCC_CTRLA) Dithering is disabled Position */ 45 #define TCC_CTRLA_RESOLUTION_DITH4 (TCC_CTRLA_RESOLUTION_DITH4_Val << TCC_CTRLA_RESOLUTION_Pos) /* (TCC_CTRLA) Dithering is done every 16 PWM frames Position */ 46 #define TCC_CTRLA_RESOLUTION_DITH5 (TCC_CTRLA_RESOLUTION_DITH5_Val << TCC_CTRLA_RESOLUTION_Pos) /* (TCC_CTRLA) Dithering is done every 32 PWM frames Position */ 47 #define TCC_CTRLA_RESOLUTION_DITH6 (TCC_CTRLA_RESOLUTION_DITH6_Val << TCC_CTRLA_RESOLUTION_Pos) /* (TCC_CTRLA) Dithering is done every 64 PWM frames Position */ 48 #define TCC_CTRLA_PRESCALER_Pos _UINT32_(8) /* (TCC_CTRLA) Prescaler Position */ 49 #define TCC_CTRLA_PRESCALER_Msk (_UINT32_(0x7) << TCC_CTRLA_PRESCALER_Pos) /* (TCC_CTRLA) Prescaler Mask */ 50 #define TCC_CTRLA_PRESCALER(value) (TCC_CTRLA_PRESCALER_Msk & (_UINT32_(value) << TCC_CTRLA_PRESCALER_Pos)) /* Assignment of value for PRESCALER in the TCC_CTRLA register */ 51 #define TCC_CTRLA_PRESCALER_DIV1_Val _UINT32_(0x0) /* (TCC_CTRLA) No division */ 52 #define TCC_CTRLA_PRESCALER_DIV2_Val _UINT32_(0x1) /* (TCC_CTRLA) Divide by 2 */ 53 #define TCC_CTRLA_PRESCALER_DIV4_Val _UINT32_(0x2) /* (TCC_CTRLA) Divide by 4 */ 54 #define TCC_CTRLA_PRESCALER_DIV8_Val _UINT32_(0x3) /* (TCC_CTRLA) Divide by 8 */ 55 #define TCC_CTRLA_PRESCALER_DIV16_Val _UINT32_(0x4) /* (TCC_CTRLA) Divide by 16 */ 56 #define TCC_CTRLA_PRESCALER_DIV64_Val _UINT32_(0x5) /* (TCC_CTRLA) Divide by 64 */ 57 #define TCC_CTRLA_PRESCALER_DIV256_Val _UINT32_(0x6) /* (TCC_CTRLA) Divide by 256 */ 58 #define TCC_CTRLA_PRESCALER_DIV1024_Val _UINT32_(0x7) /* (TCC_CTRLA) Divide by 1024 */ 59 #define TCC_CTRLA_PRESCALER_DIV1 (TCC_CTRLA_PRESCALER_DIV1_Val << TCC_CTRLA_PRESCALER_Pos) /* (TCC_CTRLA) No division Position */ 60 #define TCC_CTRLA_PRESCALER_DIV2 (TCC_CTRLA_PRESCALER_DIV2_Val << TCC_CTRLA_PRESCALER_Pos) /* (TCC_CTRLA) Divide by 2 Position */ 61 #define TCC_CTRLA_PRESCALER_DIV4 (TCC_CTRLA_PRESCALER_DIV4_Val << TCC_CTRLA_PRESCALER_Pos) /* (TCC_CTRLA) Divide by 4 Position */ 62 #define TCC_CTRLA_PRESCALER_DIV8 (TCC_CTRLA_PRESCALER_DIV8_Val << TCC_CTRLA_PRESCALER_Pos) /* (TCC_CTRLA) Divide by 8 Position */ 63 #define TCC_CTRLA_PRESCALER_DIV16 (TCC_CTRLA_PRESCALER_DIV16_Val << TCC_CTRLA_PRESCALER_Pos) /* (TCC_CTRLA) Divide by 16 Position */ 64 #define TCC_CTRLA_PRESCALER_DIV64 (TCC_CTRLA_PRESCALER_DIV64_Val << TCC_CTRLA_PRESCALER_Pos) /* (TCC_CTRLA) Divide by 64 Position */ 65 #define TCC_CTRLA_PRESCALER_DIV256 (TCC_CTRLA_PRESCALER_DIV256_Val << TCC_CTRLA_PRESCALER_Pos) /* (TCC_CTRLA) Divide by 256 Position */ 66 #define TCC_CTRLA_PRESCALER_DIV1024 (TCC_CTRLA_PRESCALER_DIV1024_Val << TCC_CTRLA_PRESCALER_Pos) /* (TCC_CTRLA) Divide by 1024 Position */ 67 #define TCC_CTRLA_RUNSTDBY_Pos _UINT32_(11) /* (TCC_CTRLA) Run in Standby Position */ 68 #define TCC_CTRLA_RUNSTDBY_Msk (_UINT32_(0x1) << TCC_CTRLA_RUNSTDBY_Pos) /* (TCC_CTRLA) Run in Standby Mask */ 69 #define TCC_CTRLA_RUNSTDBY(value) (TCC_CTRLA_RUNSTDBY_Msk & (_UINT32_(value) << TCC_CTRLA_RUNSTDBY_Pos)) /* Assignment of value for RUNSTDBY in the TCC_CTRLA register */ 70 #define TCC_CTRLA_PRESCSYNC_Pos _UINT32_(12) /* (TCC_CTRLA) Prescaler and Counter Synchronization Selection Position */ 71 #define TCC_CTRLA_PRESCSYNC_Msk (_UINT32_(0x3) << TCC_CTRLA_PRESCSYNC_Pos) /* (TCC_CTRLA) Prescaler and Counter Synchronization Selection Mask */ 72 #define TCC_CTRLA_PRESCSYNC(value) (TCC_CTRLA_PRESCSYNC_Msk & (_UINT32_(value) << TCC_CTRLA_PRESCSYNC_Pos)) /* Assignment of value for PRESCSYNC in the TCC_CTRLA register */ 73 #define TCC_CTRLA_PRESCSYNC_GCLK_Val _UINT32_(0x0) /* (TCC_CTRLA) Reload or reset counter on next GCLK */ 74 #define TCC_CTRLA_PRESCSYNC_PRESC_Val _UINT32_(0x1) /* (TCC_CTRLA) Reload or reset counter on next prescaler clock */ 75 #define TCC_CTRLA_PRESCSYNC_RESYNC_Val _UINT32_(0x2) /* (TCC_CTRLA) Reload or reset counter on next GCLK and reset prescaler counter */ 76 #define TCC_CTRLA_PRESCSYNC_GCLK (TCC_CTRLA_PRESCSYNC_GCLK_Val << TCC_CTRLA_PRESCSYNC_Pos) /* (TCC_CTRLA) Reload or reset counter on next GCLK Position */ 77 #define TCC_CTRLA_PRESCSYNC_PRESC (TCC_CTRLA_PRESCSYNC_PRESC_Val << TCC_CTRLA_PRESCSYNC_Pos) /* (TCC_CTRLA) Reload or reset counter on next prescaler clock Position */ 78 #define TCC_CTRLA_PRESCSYNC_RESYNC (TCC_CTRLA_PRESCSYNC_RESYNC_Val << TCC_CTRLA_PRESCSYNC_Pos) /* (TCC_CTRLA) Reload or reset counter on next GCLK and reset prescaler counter Position */ 79 #define TCC_CTRLA_ALOCK_Pos _UINT32_(14) /* (TCC_CTRLA) Auto Lock Position */ 80 #define TCC_CTRLA_ALOCK_Msk (_UINT32_(0x1) << TCC_CTRLA_ALOCK_Pos) /* (TCC_CTRLA) Auto Lock Mask */ 81 #define TCC_CTRLA_ALOCK(value) (TCC_CTRLA_ALOCK_Msk & (_UINT32_(value) << TCC_CTRLA_ALOCK_Pos)) /* Assignment of value for ALOCK in the TCC_CTRLA register */ 82 #define TCC_CTRLA_MSYNC_Pos _UINT32_(15) /* (TCC_CTRLA) Master Synchronization (only for TCC Slave Instance) Position */ 83 #define TCC_CTRLA_MSYNC_Msk (_UINT32_(0x1) << TCC_CTRLA_MSYNC_Pos) /* (TCC_CTRLA) Master Synchronization (only for TCC Slave Instance) Mask */ 84 #define TCC_CTRLA_MSYNC(value) (TCC_CTRLA_MSYNC_Msk & (_UINT32_(value) << TCC_CTRLA_MSYNC_Pos)) /* Assignment of value for MSYNC in the TCC_CTRLA register */ 85 #define TCC_CTRLA_DMAOS_Pos _UINT32_(23) /* (TCC_CTRLA) DMA One-shot Trigger Mode Position */ 86 #define TCC_CTRLA_DMAOS_Msk (_UINT32_(0x1) << TCC_CTRLA_DMAOS_Pos) /* (TCC_CTRLA) DMA One-shot Trigger Mode Mask */ 87 #define TCC_CTRLA_DMAOS(value) (TCC_CTRLA_DMAOS_Msk & (_UINT32_(value) << TCC_CTRLA_DMAOS_Pos)) /* Assignment of value for DMAOS in the TCC_CTRLA register */ 88 #define TCC_CTRLA_CPTEN0_Pos _UINT32_(24) /* (TCC_CTRLA) Capture Channel 0 Enable Position */ 89 #define TCC_CTRLA_CPTEN0_Msk (_UINT32_(0x1) << TCC_CTRLA_CPTEN0_Pos) /* (TCC_CTRLA) Capture Channel 0 Enable Mask */ 90 #define TCC_CTRLA_CPTEN0(value) (TCC_CTRLA_CPTEN0_Msk & (_UINT32_(value) << TCC_CTRLA_CPTEN0_Pos)) /* Assignment of value for CPTEN0 in the TCC_CTRLA register */ 91 #define TCC_CTRLA_CPTEN1_Pos _UINT32_(25) /* (TCC_CTRLA) Capture Channel 1 Enable Position */ 92 #define TCC_CTRLA_CPTEN1_Msk (_UINT32_(0x1) << TCC_CTRLA_CPTEN1_Pos) /* (TCC_CTRLA) Capture Channel 1 Enable Mask */ 93 #define TCC_CTRLA_CPTEN1(value) (TCC_CTRLA_CPTEN1_Msk & (_UINT32_(value) << TCC_CTRLA_CPTEN1_Pos)) /* Assignment of value for CPTEN1 in the TCC_CTRLA register */ 94 #define TCC_CTRLA_CPTEN2_Pos _UINT32_(26) /* (TCC_CTRLA) Capture Channel 2 Enable Position */ 95 #define TCC_CTRLA_CPTEN2_Msk (_UINT32_(0x1) << TCC_CTRLA_CPTEN2_Pos) /* (TCC_CTRLA) Capture Channel 2 Enable Mask */ 96 #define TCC_CTRLA_CPTEN2(value) (TCC_CTRLA_CPTEN2_Msk & (_UINT32_(value) << TCC_CTRLA_CPTEN2_Pos)) /* Assignment of value for CPTEN2 in the TCC_CTRLA register */ 97 #define TCC_CTRLA_CPTEN3_Pos _UINT32_(27) /* (TCC_CTRLA) Capture Channel 3 Enable Position */ 98 #define TCC_CTRLA_CPTEN3_Msk (_UINT32_(0x1) << TCC_CTRLA_CPTEN3_Pos) /* (TCC_CTRLA) Capture Channel 3 Enable Mask */ 99 #define TCC_CTRLA_CPTEN3(value) (TCC_CTRLA_CPTEN3_Msk & (_UINT32_(value) << TCC_CTRLA_CPTEN3_Pos)) /* Assignment of value for CPTEN3 in the TCC_CTRLA register */ 100 #define TCC_CTRLA_CPTEN4_Pos _UINT32_(28) /* (TCC_CTRLA) Capture Channel 4 Enable Position */ 101 #define TCC_CTRLA_CPTEN4_Msk (_UINT32_(0x1) << TCC_CTRLA_CPTEN4_Pos) /* (TCC_CTRLA) Capture Channel 4 Enable Mask */ 102 #define TCC_CTRLA_CPTEN4(value) (TCC_CTRLA_CPTEN4_Msk & (_UINT32_(value) << TCC_CTRLA_CPTEN4_Pos)) /* Assignment of value for CPTEN4 in the TCC_CTRLA register */ 103 #define TCC_CTRLA_CPTEN5_Pos _UINT32_(29) /* (TCC_CTRLA) Capture Channel 5 Enable Position */ 104 #define TCC_CTRLA_CPTEN5_Msk (_UINT32_(0x1) << TCC_CTRLA_CPTEN5_Pos) /* (TCC_CTRLA) Capture Channel 5 Enable Mask */ 105 #define TCC_CTRLA_CPTEN5(value) (TCC_CTRLA_CPTEN5_Msk & (_UINT32_(value) << TCC_CTRLA_CPTEN5_Pos)) /* Assignment of value for CPTEN5 in the TCC_CTRLA register */ 106 #define TCC_CTRLA_Msk _UINT32_(0x3F80FF63) /* (TCC_CTRLA) Register Mask */ 107 108 #define TCC_CTRLA_CPTEN_Pos _UINT32_(24) /* (TCC_CTRLA Position) Capture Channel 5 Enable */ 109 #define TCC_CTRLA_CPTEN_Msk (_UINT32_(0x3F) << TCC_CTRLA_CPTEN_Pos) /* (TCC_CTRLA Mask) CPTEN */ 110 #define TCC_CTRLA_CPTEN(value) (TCC_CTRLA_CPTEN_Msk & (_UINT32_(value) << TCC_CTRLA_CPTEN_Pos)) 111 112 /* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W 8) Control B Clear -------- */ 113 #define TCC_CTRLBCLR_RESETVALUE _UINT8_(0x00) /* (TCC_CTRLBCLR) Control B Clear Reset Value */ 114 115 #define TCC_CTRLBCLR_DIR_Pos _UINT8_(0) /* (TCC_CTRLBCLR) Counter Direction Position */ 116 #define TCC_CTRLBCLR_DIR_Msk (_UINT8_(0x1) << TCC_CTRLBCLR_DIR_Pos) /* (TCC_CTRLBCLR) Counter Direction Mask */ 117 #define TCC_CTRLBCLR_DIR(value) (TCC_CTRLBCLR_DIR_Msk & (_UINT8_(value) << TCC_CTRLBCLR_DIR_Pos)) /* Assignment of value for DIR in the TCC_CTRLBCLR register */ 118 #define TCC_CTRLBCLR_LUPD_Pos _UINT8_(1) /* (TCC_CTRLBCLR) Lock Update Position */ 119 #define TCC_CTRLBCLR_LUPD_Msk (_UINT8_(0x1) << TCC_CTRLBCLR_LUPD_Pos) /* (TCC_CTRLBCLR) Lock Update Mask */ 120 #define TCC_CTRLBCLR_LUPD(value) (TCC_CTRLBCLR_LUPD_Msk & (_UINT8_(value) << TCC_CTRLBCLR_LUPD_Pos)) /* Assignment of value for LUPD in the TCC_CTRLBCLR register */ 121 #define TCC_CTRLBCLR_ONESHOT_Pos _UINT8_(2) /* (TCC_CTRLBCLR) One-Shot Position */ 122 #define TCC_CTRLBCLR_ONESHOT_Msk (_UINT8_(0x1) << TCC_CTRLBCLR_ONESHOT_Pos) /* (TCC_CTRLBCLR) One-Shot Mask */ 123 #define TCC_CTRLBCLR_ONESHOT(value) (TCC_CTRLBCLR_ONESHOT_Msk & (_UINT8_(value) << TCC_CTRLBCLR_ONESHOT_Pos)) /* Assignment of value for ONESHOT in the TCC_CTRLBCLR register */ 124 #define TCC_CTRLBCLR_IDXCMD_Pos _UINT8_(3) /* (TCC_CTRLBCLR) Ramp Index Command Position */ 125 #define TCC_CTRLBCLR_IDXCMD_Msk (_UINT8_(0x3) << TCC_CTRLBCLR_IDXCMD_Pos) /* (TCC_CTRLBCLR) Ramp Index Command Mask */ 126 #define TCC_CTRLBCLR_IDXCMD(value) (TCC_CTRLBCLR_IDXCMD_Msk & (_UINT8_(value) << TCC_CTRLBCLR_IDXCMD_Pos)) /* Assignment of value for IDXCMD in the TCC_CTRLBCLR register */ 127 #define TCC_CTRLBCLR_IDXCMD_DISABLE_Val _UINT8_(0x0) /* (TCC_CTRLBCLR) Command disabled: Index toggles between cycles A and B */ 128 #define TCC_CTRLBCLR_IDXCMD_SET_Val _UINT8_(0x1) /* (TCC_CTRLBCLR) Set index: cycle B will be forced in the next cycle */ 129 #define TCC_CTRLBCLR_IDXCMD_CLEAR_Val _UINT8_(0x2) /* (TCC_CTRLBCLR) Clear index: cycle A will be forced in the next cycle */ 130 #define TCC_CTRLBCLR_IDXCMD_HOLD_Val _UINT8_(0x3) /* (TCC_CTRLBCLR) Hold index: the next cycle will be the same as the current cycle */ 131 #define TCC_CTRLBCLR_IDXCMD_DISABLE (TCC_CTRLBCLR_IDXCMD_DISABLE_Val << TCC_CTRLBCLR_IDXCMD_Pos) /* (TCC_CTRLBCLR) Command disabled: Index toggles between cycles A and B Position */ 132 #define TCC_CTRLBCLR_IDXCMD_SET (TCC_CTRLBCLR_IDXCMD_SET_Val << TCC_CTRLBCLR_IDXCMD_Pos) /* (TCC_CTRLBCLR) Set index: cycle B will be forced in the next cycle Position */ 133 #define TCC_CTRLBCLR_IDXCMD_CLEAR (TCC_CTRLBCLR_IDXCMD_CLEAR_Val << TCC_CTRLBCLR_IDXCMD_Pos) /* (TCC_CTRLBCLR) Clear index: cycle A will be forced in the next cycle Position */ 134 #define TCC_CTRLBCLR_IDXCMD_HOLD (TCC_CTRLBCLR_IDXCMD_HOLD_Val << TCC_CTRLBCLR_IDXCMD_Pos) /* (TCC_CTRLBCLR) Hold index: the next cycle will be the same as the current cycle Position */ 135 #define TCC_CTRLBCLR_CMD_Pos _UINT8_(5) /* (TCC_CTRLBCLR) TCC Command Position */ 136 #define TCC_CTRLBCLR_CMD_Msk (_UINT8_(0x7) << TCC_CTRLBCLR_CMD_Pos) /* (TCC_CTRLBCLR) TCC Command Mask */ 137 #define TCC_CTRLBCLR_CMD(value) (TCC_CTRLBCLR_CMD_Msk & (_UINT8_(value) << TCC_CTRLBCLR_CMD_Pos)) /* Assignment of value for CMD in the TCC_CTRLBCLR register */ 138 #define TCC_CTRLBCLR_CMD_NONE_Val _UINT8_(0x0) /* (TCC_CTRLBCLR) No action */ 139 #define TCC_CTRLBCLR_CMD_RETRIGGER_Val _UINT8_(0x1) /* (TCC_CTRLBCLR) Clear start, restart or retrigger */ 140 #define TCC_CTRLBCLR_CMD_STOP_Val _UINT8_(0x2) /* (TCC_CTRLBCLR) Force stop */ 141 #define TCC_CTRLBCLR_CMD_UPDATE_Val _UINT8_(0x3) /* (TCC_CTRLBCLR) Force update or double buffered registers */ 142 #define TCC_CTRLBCLR_CMD_READSYNC_Val _UINT8_(0x4) /* (TCC_CTRLBCLR) Force COUNT read synchronization */ 143 #define TCC_CTRLBCLR_CMD_DMAOS_Val _UINT8_(0x5) /* (TCC_CTRLBCLR) One-shot DMA trigger */ 144 #define TCC_CTRLBCLR_CMD_NONE (TCC_CTRLBCLR_CMD_NONE_Val << TCC_CTRLBCLR_CMD_Pos) /* (TCC_CTRLBCLR) No action Position */ 145 #define TCC_CTRLBCLR_CMD_RETRIGGER (TCC_CTRLBCLR_CMD_RETRIGGER_Val << TCC_CTRLBCLR_CMD_Pos) /* (TCC_CTRLBCLR) Clear start, restart or retrigger Position */ 146 #define TCC_CTRLBCLR_CMD_STOP (TCC_CTRLBCLR_CMD_STOP_Val << TCC_CTRLBCLR_CMD_Pos) /* (TCC_CTRLBCLR) Force stop Position */ 147 #define TCC_CTRLBCLR_CMD_UPDATE (TCC_CTRLBCLR_CMD_UPDATE_Val << TCC_CTRLBCLR_CMD_Pos) /* (TCC_CTRLBCLR) Force update or double buffered registers Position */ 148 #define TCC_CTRLBCLR_CMD_READSYNC (TCC_CTRLBCLR_CMD_READSYNC_Val << TCC_CTRLBCLR_CMD_Pos) /* (TCC_CTRLBCLR) Force COUNT read synchronization Position */ 149 #define TCC_CTRLBCLR_CMD_DMAOS (TCC_CTRLBCLR_CMD_DMAOS_Val << TCC_CTRLBCLR_CMD_Pos) /* (TCC_CTRLBCLR) One-shot DMA trigger Position */ 150 #define TCC_CTRLBCLR_Msk _UINT8_(0xFF) /* (TCC_CTRLBCLR) Register Mask */ 151 152 153 /* -------- TCC_CTRLBSET : (TCC Offset: 0x05) (R/W 8) Control B Set -------- */ 154 #define TCC_CTRLBSET_RESETVALUE _UINT8_(0x00) /* (TCC_CTRLBSET) Control B Set Reset Value */ 155 156 #define TCC_CTRLBSET_DIR_Pos _UINT8_(0) /* (TCC_CTRLBSET) Counter Direction Position */ 157 #define TCC_CTRLBSET_DIR_Msk (_UINT8_(0x1) << TCC_CTRLBSET_DIR_Pos) /* (TCC_CTRLBSET) Counter Direction Mask */ 158 #define TCC_CTRLBSET_DIR(value) (TCC_CTRLBSET_DIR_Msk & (_UINT8_(value) << TCC_CTRLBSET_DIR_Pos)) /* Assignment of value for DIR in the TCC_CTRLBSET register */ 159 #define TCC_CTRLBSET_LUPD_Pos _UINT8_(1) /* (TCC_CTRLBSET) Lock Update Position */ 160 #define TCC_CTRLBSET_LUPD_Msk (_UINT8_(0x1) << TCC_CTRLBSET_LUPD_Pos) /* (TCC_CTRLBSET) Lock Update Mask */ 161 #define TCC_CTRLBSET_LUPD(value) (TCC_CTRLBSET_LUPD_Msk & (_UINT8_(value) << TCC_CTRLBSET_LUPD_Pos)) /* Assignment of value for LUPD in the TCC_CTRLBSET register */ 162 #define TCC_CTRLBSET_ONESHOT_Pos _UINT8_(2) /* (TCC_CTRLBSET) One-Shot Position */ 163 #define TCC_CTRLBSET_ONESHOT_Msk (_UINT8_(0x1) << TCC_CTRLBSET_ONESHOT_Pos) /* (TCC_CTRLBSET) One-Shot Mask */ 164 #define TCC_CTRLBSET_ONESHOT(value) (TCC_CTRLBSET_ONESHOT_Msk & (_UINT8_(value) << TCC_CTRLBSET_ONESHOT_Pos)) /* Assignment of value for ONESHOT in the TCC_CTRLBSET register */ 165 #define TCC_CTRLBSET_IDXCMD_Pos _UINT8_(3) /* (TCC_CTRLBSET) Ramp Index Command Position */ 166 #define TCC_CTRLBSET_IDXCMD_Msk (_UINT8_(0x3) << TCC_CTRLBSET_IDXCMD_Pos) /* (TCC_CTRLBSET) Ramp Index Command Mask */ 167 #define TCC_CTRLBSET_IDXCMD(value) (TCC_CTRLBSET_IDXCMD_Msk & (_UINT8_(value) << TCC_CTRLBSET_IDXCMD_Pos)) /* Assignment of value for IDXCMD in the TCC_CTRLBSET register */ 168 #define TCC_CTRLBSET_IDXCMD_DISABLE_Val _UINT8_(0x0) /* (TCC_CTRLBSET) Command disabled: Index toggles between cycles A and B */ 169 #define TCC_CTRLBSET_IDXCMD_SET_Val _UINT8_(0x1) /* (TCC_CTRLBSET) Set index: cycle B will be forced in the next cycle */ 170 #define TCC_CTRLBSET_IDXCMD_CLEAR_Val _UINT8_(0x2) /* (TCC_CTRLBSET) Clear index: cycle A will be forced in the next cycle */ 171 #define TCC_CTRLBSET_IDXCMD_HOLD_Val _UINT8_(0x3) /* (TCC_CTRLBSET) Hold index: the next cycle will be the same as the current cycle */ 172 #define TCC_CTRLBSET_IDXCMD_DISABLE (TCC_CTRLBSET_IDXCMD_DISABLE_Val << TCC_CTRLBSET_IDXCMD_Pos) /* (TCC_CTRLBSET) Command disabled: Index toggles between cycles A and B Position */ 173 #define TCC_CTRLBSET_IDXCMD_SET (TCC_CTRLBSET_IDXCMD_SET_Val << TCC_CTRLBSET_IDXCMD_Pos) /* (TCC_CTRLBSET) Set index: cycle B will be forced in the next cycle Position */ 174 #define TCC_CTRLBSET_IDXCMD_CLEAR (TCC_CTRLBSET_IDXCMD_CLEAR_Val << TCC_CTRLBSET_IDXCMD_Pos) /* (TCC_CTRLBSET) Clear index: cycle A will be forced in the next cycle Position */ 175 #define TCC_CTRLBSET_IDXCMD_HOLD (TCC_CTRLBSET_IDXCMD_HOLD_Val << TCC_CTRLBSET_IDXCMD_Pos) /* (TCC_CTRLBSET) Hold index: the next cycle will be the same as the current cycle Position */ 176 #define TCC_CTRLBSET_CMD_Pos _UINT8_(5) /* (TCC_CTRLBSET) TCC Command Position */ 177 #define TCC_CTRLBSET_CMD_Msk (_UINT8_(0x7) << TCC_CTRLBSET_CMD_Pos) /* (TCC_CTRLBSET) TCC Command Mask */ 178 #define TCC_CTRLBSET_CMD(value) (TCC_CTRLBSET_CMD_Msk & (_UINT8_(value) << TCC_CTRLBSET_CMD_Pos)) /* Assignment of value for CMD in the TCC_CTRLBSET register */ 179 #define TCC_CTRLBSET_CMD_NONE_Val _UINT8_(0x0) /* (TCC_CTRLBSET) No action */ 180 #define TCC_CTRLBSET_CMD_RETRIGGER_Val _UINT8_(0x1) /* (TCC_CTRLBSET) Clear start, restart or retrigger */ 181 #define TCC_CTRLBSET_CMD_STOP_Val _UINT8_(0x2) /* (TCC_CTRLBSET) Force stop */ 182 #define TCC_CTRLBSET_CMD_UPDATE_Val _UINT8_(0x3) /* (TCC_CTRLBSET) Force update or double buffered registers */ 183 #define TCC_CTRLBSET_CMD_READSYNC_Val _UINT8_(0x4) /* (TCC_CTRLBSET) Force COUNT read synchronization */ 184 #define TCC_CTRLBSET_CMD_DMAOS_Val _UINT8_(0x5) /* (TCC_CTRLBSET) One-shot DMA trigger */ 185 #define TCC_CTRLBSET_CMD_NONE (TCC_CTRLBSET_CMD_NONE_Val << TCC_CTRLBSET_CMD_Pos) /* (TCC_CTRLBSET) No action Position */ 186 #define TCC_CTRLBSET_CMD_RETRIGGER (TCC_CTRLBSET_CMD_RETRIGGER_Val << TCC_CTRLBSET_CMD_Pos) /* (TCC_CTRLBSET) Clear start, restart or retrigger Position */ 187 #define TCC_CTRLBSET_CMD_STOP (TCC_CTRLBSET_CMD_STOP_Val << TCC_CTRLBSET_CMD_Pos) /* (TCC_CTRLBSET) Force stop Position */ 188 #define TCC_CTRLBSET_CMD_UPDATE (TCC_CTRLBSET_CMD_UPDATE_Val << TCC_CTRLBSET_CMD_Pos) /* (TCC_CTRLBSET) Force update or double buffered registers Position */ 189 #define TCC_CTRLBSET_CMD_READSYNC (TCC_CTRLBSET_CMD_READSYNC_Val << TCC_CTRLBSET_CMD_Pos) /* (TCC_CTRLBSET) Force COUNT read synchronization Position */ 190 #define TCC_CTRLBSET_CMD_DMAOS (TCC_CTRLBSET_CMD_DMAOS_Val << TCC_CTRLBSET_CMD_Pos) /* (TCC_CTRLBSET) One-shot DMA trigger Position */ 191 #define TCC_CTRLBSET_Msk _UINT8_(0xFF) /* (TCC_CTRLBSET) Register Mask */ 192 193 194 /* -------- TCC_SYNCBUSY : (TCC Offset: 0x08) ( R/ 32) Synchronization Busy -------- */ 195 #define TCC_SYNCBUSY_RESETVALUE _UINT32_(0x00) /* (TCC_SYNCBUSY) Synchronization Busy Reset Value */ 196 197 #define TCC_SYNCBUSY_SWRST_Pos _UINT32_(0) /* (TCC_SYNCBUSY) Swrst Busy Position */ 198 #define TCC_SYNCBUSY_SWRST_Msk (_UINT32_(0x1) << TCC_SYNCBUSY_SWRST_Pos) /* (TCC_SYNCBUSY) Swrst Busy Mask */ 199 #define TCC_SYNCBUSY_SWRST(value) (TCC_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << TCC_SYNCBUSY_SWRST_Pos)) /* Assignment of value for SWRST in the TCC_SYNCBUSY register */ 200 #define TCC_SYNCBUSY_ENABLE_Pos _UINT32_(1) /* (TCC_SYNCBUSY) Enable Busy Position */ 201 #define TCC_SYNCBUSY_ENABLE_Msk (_UINT32_(0x1) << TCC_SYNCBUSY_ENABLE_Pos) /* (TCC_SYNCBUSY) Enable Busy Mask */ 202 #define TCC_SYNCBUSY_ENABLE(value) (TCC_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << TCC_SYNCBUSY_ENABLE_Pos)) /* Assignment of value for ENABLE in the TCC_SYNCBUSY register */ 203 #define TCC_SYNCBUSY_CTRLB_Pos _UINT32_(2) /* (TCC_SYNCBUSY) Ctrlb Busy Position */ 204 #define TCC_SYNCBUSY_CTRLB_Msk (_UINT32_(0x1) << TCC_SYNCBUSY_CTRLB_Pos) /* (TCC_SYNCBUSY) Ctrlb Busy Mask */ 205 #define TCC_SYNCBUSY_CTRLB(value) (TCC_SYNCBUSY_CTRLB_Msk & (_UINT32_(value) << TCC_SYNCBUSY_CTRLB_Pos)) /* Assignment of value for CTRLB in the TCC_SYNCBUSY register */ 206 #define TCC_SYNCBUSY_STATUS_Pos _UINT32_(3) /* (TCC_SYNCBUSY) Status Busy Position */ 207 #define TCC_SYNCBUSY_STATUS_Msk (_UINT32_(0x1) << TCC_SYNCBUSY_STATUS_Pos) /* (TCC_SYNCBUSY) Status Busy Mask */ 208 #define TCC_SYNCBUSY_STATUS(value) (TCC_SYNCBUSY_STATUS_Msk & (_UINT32_(value) << TCC_SYNCBUSY_STATUS_Pos)) /* Assignment of value for STATUS in the TCC_SYNCBUSY register */ 209 #define TCC_SYNCBUSY_COUNT_Pos _UINT32_(4) /* (TCC_SYNCBUSY) Count Busy Position */ 210 #define TCC_SYNCBUSY_COUNT_Msk (_UINT32_(0x1) << TCC_SYNCBUSY_COUNT_Pos) /* (TCC_SYNCBUSY) Count Busy Mask */ 211 #define TCC_SYNCBUSY_COUNT(value) (TCC_SYNCBUSY_COUNT_Msk & (_UINT32_(value) << TCC_SYNCBUSY_COUNT_Pos)) /* Assignment of value for COUNT in the TCC_SYNCBUSY register */ 212 #define TCC_SYNCBUSY_PATT_Pos _UINT32_(5) /* (TCC_SYNCBUSY) Pattern Busy Position */ 213 #define TCC_SYNCBUSY_PATT_Msk (_UINT32_(0x1) << TCC_SYNCBUSY_PATT_Pos) /* (TCC_SYNCBUSY) Pattern Busy Mask */ 214 #define TCC_SYNCBUSY_PATT(value) (TCC_SYNCBUSY_PATT_Msk & (_UINT32_(value) << TCC_SYNCBUSY_PATT_Pos)) /* Assignment of value for PATT in the TCC_SYNCBUSY register */ 215 #define TCC_SYNCBUSY_WAVE_Pos _UINT32_(6) /* (TCC_SYNCBUSY) Wave Busy Position */ 216 #define TCC_SYNCBUSY_WAVE_Msk (_UINT32_(0x1) << TCC_SYNCBUSY_WAVE_Pos) /* (TCC_SYNCBUSY) Wave Busy Mask */ 217 #define TCC_SYNCBUSY_WAVE(value) (TCC_SYNCBUSY_WAVE_Msk & (_UINT32_(value) << TCC_SYNCBUSY_WAVE_Pos)) /* Assignment of value for WAVE in the TCC_SYNCBUSY register */ 218 #define TCC_SYNCBUSY_PER_Pos _UINT32_(7) /* (TCC_SYNCBUSY) Period Busy Position */ 219 #define TCC_SYNCBUSY_PER_Msk (_UINT32_(0x1) << TCC_SYNCBUSY_PER_Pos) /* (TCC_SYNCBUSY) Period Busy Mask */ 220 #define TCC_SYNCBUSY_PER(value) (TCC_SYNCBUSY_PER_Msk & (_UINT32_(value) << TCC_SYNCBUSY_PER_Pos)) /* Assignment of value for PER in the TCC_SYNCBUSY register */ 221 #define TCC_SYNCBUSY_CC0_Pos _UINT32_(8) /* (TCC_SYNCBUSY) Compare Channel 0 Busy Position */ 222 #define TCC_SYNCBUSY_CC0_Msk (_UINT32_(0x1) << TCC_SYNCBUSY_CC0_Pos) /* (TCC_SYNCBUSY) Compare Channel 0 Busy Mask */ 223 #define TCC_SYNCBUSY_CC0(value) (TCC_SYNCBUSY_CC0_Msk & (_UINT32_(value) << TCC_SYNCBUSY_CC0_Pos)) /* Assignment of value for CC0 in the TCC_SYNCBUSY register */ 224 #define TCC_SYNCBUSY_CC1_Pos _UINT32_(9) /* (TCC_SYNCBUSY) Compare Channel 1 Busy Position */ 225 #define TCC_SYNCBUSY_CC1_Msk (_UINT32_(0x1) << TCC_SYNCBUSY_CC1_Pos) /* (TCC_SYNCBUSY) Compare Channel 1 Busy Mask */ 226 #define TCC_SYNCBUSY_CC1(value) (TCC_SYNCBUSY_CC1_Msk & (_UINT32_(value) << TCC_SYNCBUSY_CC1_Pos)) /* Assignment of value for CC1 in the TCC_SYNCBUSY register */ 227 #define TCC_SYNCBUSY_CC2_Pos _UINT32_(10) /* (TCC_SYNCBUSY) Compare Channel 2 Busy Position */ 228 #define TCC_SYNCBUSY_CC2_Msk (_UINT32_(0x1) << TCC_SYNCBUSY_CC2_Pos) /* (TCC_SYNCBUSY) Compare Channel 2 Busy Mask */ 229 #define TCC_SYNCBUSY_CC2(value) (TCC_SYNCBUSY_CC2_Msk & (_UINT32_(value) << TCC_SYNCBUSY_CC2_Pos)) /* Assignment of value for CC2 in the TCC_SYNCBUSY register */ 230 #define TCC_SYNCBUSY_CC3_Pos _UINT32_(11) /* (TCC_SYNCBUSY) Compare Channel 3 Busy Position */ 231 #define TCC_SYNCBUSY_CC3_Msk (_UINT32_(0x1) << TCC_SYNCBUSY_CC3_Pos) /* (TCC_SYNCBUSY) Compare Channel 3 Busy Mask */ 232 #define TCC_SYNCBUSY_CC3(value) (TCC_SYNCBUSY_CC3_Msk & (_UINT32_(value) << TCC_SYNCBUSY_CC3_Pos)) /* Assignment of value for CC3 in the TCC_SYNCBUSY register */ 233 #define TCC_SYNCBUSY_CC4_Pos _UINT32_(12) /* (TCC_SYNCBUSY) Compare Channel 4 Busy Position */ 234 #define TCC_SYNCBUSY_CC4_Msk (_UINT32_(0x1) << TCC_SYNCBUSY_CC4_Pos) /* (TCC_SYNCBUSY) Compare Channel 4 Busy Mask */ 235 #define TCC_SYNCBUSY_CC4(value) (TCC_SYNCBUSY_CC4_Msk & (_UINT32_(value) << TCC_SYNCBUSY_CC4_Pos)) /* Assignment of value for CC4 in the TCC_SYNCBUSY register */ 236 #define TCC_SYNCBUSY_CC5_Pos _UINT32_(13) /* (TCC_SYNCBUSY) Compare Channel 5 Busy Position */ 237 #define TCC_SYNCBUSY_CC5_Msk (_UINT32_(0x1) << TCC_SYNCBUSY_CC5_Pos) /* (TCC_SYNCBUSY) Compare Channel 5 Busy Mask */ 238 #define TCC_SYNCBUSY_CC5(value) (TCC_SYNCBUSY_CC5_Msk & (_UINT32_(value) << TCC_SYNCBUSY_CC5_Pos)) /* Assignment of value for CC5 in the TCC_SYNCBUSY register */ 239 #define TCC_SYNCBUSY_Msk _UINT32_(0x00003FFF) /* (TCC_SYNCBUSY) Register Mask */ 240 241 #define TCC_SYNCBUSY_CC_Pos _UINT32_(8) /* (TCC_SYNCBUSY Position) Compare Channel 5 Busy */ 242 #define TCC_SYNCBUSY_CC_Msk (_UINT32_(0x3F) << TCC_SYNCBUSY_CC_Pos) /* (TCC_SYNCBUSY Mask) CC */ 243 #define TCC_SYNCBUSY_CC(value) (TCC_SYNCBUSY_CC_Msk & (_UINT32_(value) << TCC_SYNCBUSY_CC_Pos)) 244 245 /* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable Fault A Configuration -------- */ 246 #define TCC_FCTRLA_RESETVALUE _UINT32_(0x00) /* (TCC_FCTRLA) Recoverable Fault A Configuration Reset Value */ 247 248 #define TCC_FCTRLA_SRC_Pos _UINT32_(0) /* (TCC_FCTRLA) Fault A Source Position */ 249 #define TCC_FCTRLA_SRC_Msk (_UINT32_(0x3) << TCC_FCTRLA_SRC_Pos) /* (TCC_FCTRLA) Fault A Source Mask */ 250 #define TCC_FCTRLA_SRC(value) (TCC_FCTRLA_SRC_Msk & (_UINT32_(value) << TCC_FCTRLA_SRC_Pos)) /* Assignment of value for SRC in the TCC_FCTRLA register */ 251 #define TCC_FCTRLA_SRC_DISABLE_Val _UINT32_(0x0) /* (TCC_FCTRLA) Fault input disabled */ 252 #define TCC_FCTRLA_SRC_ENABLE_Val _UINT32_(0x1) /* (TCC_FCTRLA) MCEx (x=0,1) event input */ 253 #define TCC_FCTRLA_SRC_INVERT_Val _UINT32_(0x2) /* (TCC_FCTRLA) Inverted MCEx (x=0,1) event input */ 254 #define TCC_FCTRLA_SRC_ALTFAULT_Val _UINT32_(0x3) /* (TCC_FCTRLA) Alternate fault (A or B) state at the end of the previous period */ 255 #define TCC_FCTRLA_SRC_DISABLE (TCC_FCTRLA_SRC_DISABLE_Val << TCC_FCTRLA_SRC_Pos) /* (TCC_FCTRLA) Fault input disabled Position */ 256 #define TCC_FCTRLA_SRC_ENABLE (TCC_FCTRLA_SRC_ENABLE_Val << TCC_FCTRLA_SRC_Pos) /* (TCC_FCTRLA) MCEx (x=0,1) event input Position */ 257 #define TCC_FCTRLA_SRC_INVERT (TCC_FCTRLA_SRC_INVERT_Val << TCC_FCTRLA_SRC_Pos) /* (TCC_FCTRLA) Inverted MCEx (x=0,1) event input Position */ 258 #define TCC_FCTRLA_SRC_ALTFAULT (TCC_FCTRLA_SRC_ALTFAULT_Val << TCC_FCTRLA_SRC_Pos) /* (TCC_FCTRLA) Alternate fault (A or B) state at the end of the previous period Position */ 259 #define TCC_FCTRLA_KEEP_Pos _UINT32_(3) /* (TCC_FCTRLA) Fault A Keeper Position */ 260 #define TCC_FCTRLA_KEEP_Msk (_UINT32_(0x1) << TCC_FCTRLA_KEEP_Pos) /* (TCC_FCTRLA) Fault A Keeper Mask */ 261 #define TCC_FCTRLA_KEEP(value) (TCC_FCTRLA_KEEP_Msk & (_UINT32_(value) << TCC_FCTRLA_KEEP_Pos)) /* Assignment of value for KEEP in the TCC_FCTRLA register */ 262 #define TCC_FCTRLA_QUAL_Pos _UINT32_(4) /* (TCC_FCTRLA) Fault A Qualification Position */ 263 #define TCC_FCTRLA_QUAL_Msk (_UINT32_(0x1) << TCC_FCTRLA_QUAL_Pos) /* (TCC_FCTRLA) Fault A Qualification Mask */ 264 #define TCC_FCTRLA_QUAL(value) (TCC_FCTRLA_QUAL_Msk & (_UINT32_(value) << TCC_FCTRLA_QUAL_Pos)) /* Assignment of value for QUAL in the TCC_FCTRLA register */ 265 #define TCC_FCTRLA_BLANK_Pos _UINT32_(5) /* (TCC_FCTRLA) Fault A Blanking Mode Position */ 266 #define TCC_FCTRLA_BLANK_Msk (_UINT32_(0x3) << TCC_FCTRLA_BLANK_Pos) /* (TCC_FCTRLA) Fault A Blanking Mode Mask */ 267 #define TCC_FCTRLA_BLANK(value) (TCC_FCTRLA_BLANK_Msk & (_UINT32_(value) << TCC_FCTRLA_BLANK_Pos)) /* Assignment of value for BLANK in the TCC_FCTRLA register */ 268 #define TCC_FCTRLA_BLANK_START_Val _UINT32_(0x0) /* (TCC_FCTRLA) Blanking applied from start of the ramp */ 269 #define TCC_FCTRLA_BLANK_RISE_Val _UINT32_(0x1) /* (TCC_FCTRLA) Blanking applied from rising edge of the output waveform */ 270 #define TCC_FCTRLA_BLANK_FALL_Val _UINT32_(0x2) /* (TCC_FCTRLA) Blanking applied from falling edge of the output waveform */ 271 #define TCC_FCTRLA_BLANK_BOTH_Val _UINT32_(0x3) /* (TCC_FCTRLA) Blanking applied from each toggle of the output waveform */ 272 #define TCC_FCTRLA_BLANK_START (TCC_FCTRLA_BLANK_START_Val << TCC_FCTRLA_BLANK_Pos) /* (TCC_FCTRLA) Blanking applied from start of the ramp Position */ 273 #define TCC_FCTRLA_BLANK_RISE (TCC_FCTRLA_BLANK_RISE_Val << TCC_FCTRLA_BLANK_Pos) /* (TCC_FCTRLA) Blanking applied from rising edge of the output waveform Position */ 274 #define TCC_FCTRLA_BLANK_FALL (TCC_FCTRLA_BLANK_FALL_Val << TCC_FCTRLA_BLANK_Pos) /* (TCC_FCTRLA) Blanking applied from falling edge of the output waveform Position */ 275 #define TCC_FCTRLA_BLANK_BOTH (TCC_FCTRLA_BLANK_BOTH_Val << TCC_FCTRLA_BLANK_Pos) /* (TCC_FCTRLA) Blanking applied from each toggle of the output waveform Position */ 276 #define TCC_FCTRLA_RESTART_Pos _UINT32_(7) /* (TCC_FCTRLA) Fault A Restart Position */ 277 #define TCC_FCTRLA_RESTART_Msk (_UINT32_(0x1) << TCC_FCTRLA_RESTART_Pos) /* (TCC_FCTRLA) Fault A Restart Mask */ 278 #define TCC_FCTRLA_RESTART(value) (TCC_FCTRLA_RESTART_Msk & (_UINT32_(value) << TCC_FCTRLA_RESTART_Pos)) /* Assignment of value for RESTART in the TCC_FCTRLA register */ 279 #define TCC_FCTRLA_HALT_Pos _UINT32_(8) /* (TCC_FCTRLA) Fault A Halt Mode Position */ 280 #define TCC_FCTRLA_HALT_Msk (_UINT32_(0x3) << TCC_FCTRLA_HALT_Pos) /* (TCC_FCTRLA) Fault A Halt Mode Mask */ 281 #define TCC_FCTRLA_HALT(value) (TCC_FCTRLA_HALT_Msk & (_UINT32_(value) << TCC_FCTRLA_HALT_Pos)) /* Assignment of value for HALT in the TCC_FCTRLA register */ 282 #define TCC_FCTRLA_HALT_DISABLE_Val _UINT32_(0x0) /* (TCC_FCTRLA) Halt action disabled */ 283 #define TCC_FCTRLA_HALT_HW_Val _UINT32_(0x1) /* (TCC_FCTRLA) Hardware halt action */ 284 #define TCC_FCTRLA_HALT_SW_Val _UINT32_(0x2) /* (TCC_FCTRLA) Software halt action */ 285 #define TCC_FCTRLA_HALT_NR_Val _UINT32_(0x3) /* (TCC_FCTRLA) Non-recoverable fault */ 286 #define TCC_FCTRLA_HALT_DISABLE (TCC_FCTRLA_HALT_DISABLE_Val << TCC_FCTRLA_HALT_Pos) /* (TCC_FCTRLA) Halt action disabled Position */ 287 #define TCC_FCTRLA_HALT_HW (TCC_FCTRLA_HALT_HW_Val << TCC_FCTRLA_HALT_Pos) /* (TCC_FCTRLA) Hardware halt action Position */ 288 #define TCC_FCTRLA_HALT_SW (TCC_FCTRLA_HALT_SW_Val << TCC_FCTRLA_HALT_Pos) /* (TCC_FCTRLA) Software halt action Position */ 289 #define TCC_FCTRLA_HALT_NR (TCC_FCTRLA_HALT_NR_Val << TCC_FCTRLA_HALT_Pos) /* (TCC_FCTRLA) Non-recoverable fault Position */ 290 #define TCC_FCTRLA_CHSEL_Pos _UINT32_(10) /* (TCC_FCTRLA) Fault A Capture Channel Position */ 291 #define TCC_FCTRLA_CHSEL_Msk (_UINT32_(0x3) << TCC_FCTRLA_CHSEL_Pos) /* (TCC_FCTRLA) Fault A Capture Channel Mask */ 292 #define TCC_FCTRLA_CHSEL(value) (TCC_FCTRLA_CHSEL_Msk & (_UINT32_(value) << TCC_FCTRLA_CHSEL_Pos)) /* Assignment of value for CHSEL in the TCC_FCTRLA register */ 293 #define TCC_FCTRLA_CHSEL_CC0_Val _UINT32_(0x0) /* (TCC_FCTRLA) Capture value stored in channel 0 */ 294 #define TCC_FCTRLA_CHSEL_CC1_Val _UINT32_(0x1) /* (TCC_FCTRLA) Capture value stored in channel 1 */ 295 #define TCC_FCTRLA_CHSEL_CC2_Val _UINT32_(0x2) /* (TCC_FCTRLA) Capture value stored in channel 2 */ 296 #define TCC_FCTRLA_CHSEL_CC3_Val _UINT32_(0x3) /* (TCC_FCTRLA) Capture value stored in channel 3 */ 297 #define TCC_FCTRLA_CHSEL_CC0 (TCC_FCTRLA_CHSEL_CC0_Val << TCC_FCTRLA_CHSEL_Pos) /* (TCC_FCTRLA) Capture value stored in channel 0 Position */ 298 #define TCC_FCTRLA_CHSEL_CC1 (TCC_FCTRLA_CHSEL_CC1_Val << TCC_FCTRLA_CHSEL_Pos) /* (TCC_FCTRLA) Capture value stored in channel 1 Position */ 299 #define TCC_FCTRLA_CHSEL_CC2 (TCC_FCTRLA_CHSEL_CC2_Val << TCC_FCTRLA_CHSEL_Pos) /* (TCC_FCTRLA) Capture value stored in channel 2 Position */ 300 #define TCC_FCTRLA_CHSEL_CC3 (TCC_FCTRLA_CHSEL_CC3_Val << TCC_FCTRLA_CHSEL_Pos) /* (TCC_FCTRLA) Capture value stored in channel 3 Position */ 301 #define TCC_FCTRLA_CAPTURE_Pos _UINT32_(12) /* (TCC_FCTRLA) Fault A Capture Action Position */ 302 #define TCC_FCTRLA_CAPTURE_Msk (_UINT32_(0x7) << TCC_FCTRLA_CAPTURE_Pos) /* (TCC_FCTRLA) Fault A Capture Action Mask */ 303 #define TCC_FCTRLA_CAPTURE(value) (TCC_FCTRLA_CAPTURE_Msk & (_UINT32_(value) << TCC_FCTRLA_CAPTURE_Pos)) /* Assignment of value for CAPTURE in the TCC_FCTRLA register */ 304 #define TCC_FCTRLA_CAPTURE_DISABLE_Val _UINT32_(0x0) /* (TCC_FCTRLA) No capture */ 305 #define TCC_FCTRLA_CAPTURE_CAPT_Val _UINT32_(0x1) /* (TCC_FCTRLA) Capture on fault */ 306 #define TCC_FCTRLA_CAPTURE_CAPTMIN_Val _UINT32_(0x2) /* (TCC_FCTRLA) Minimum capture */ 307 #define TCC_FCTRLA_CAPTURE_CAPTMAX_Val _UINT32_(0x3) /* (TCC_FCTRLA) Maximum capture */ 308 #define TCC_FCTRLA_CAPTURE_LOCMIN_Val _UINT32_(0x4) /* (TCC_FCTRLA) Minimum local detection */ 309 #define TCC_FCTRLA_CAPTURE_LOCMAX_Val _UINT32_(0x5) /* (TCC_FCTRLA) Maximum local detection */ 310 #define TCC_FCTRLA_CAPTURE_DERIV0_Val _UINT32_(0x6) /* (TCC_FCTRLA) Minimum and maximum local detection */ 311 #define TCC_FCTRLA_CAPTURE_CAPTMARK_Val _UINT32_(0x7) /* (TCC_FCTRLA) Capture with ramp index as MSB value */ 312 #define TCC_FCTRLA_CAPTURE_DISABLE (TCC_FCTRLA_CAPTURE_DISABLE_Val << TCC_FCTRLA_CAPTURE_Pos) /* (TCC_FCTRLA) No capture Position */ 313 #define TCC_FCTRLA_CAPTURE_CAPT (TCC_FCTRLA_CAPTURE_CAPT_Val << TCC_FCTRLA_CAPTURE_Pos) /* (TCC_FCTRLA) Capture on fault Position */ 314 #define TCC_FCTRLA_CAPTURE_CAPTMIN (TCC_FCTRLA_CAPTURE_CAPTMIN_Val << TCC_FCTRLA_CAPTURE_Pos) /* (TCC_FCTRLA) Minimum capture Position */ 315 #define TCC_FCTRLA_CAPTURE_CAPTMAX (TCC_FCTRLA_CAPTURE_CAPTMAX_Val << TCC_FCTRLA_CAPTURE_Pos) /* (TCC_FCTRLA) Maximum capture Position */ 316 #define TCC_FCTRLA_CAPTURE_LOCMIN (TCC_FCTRLA_CAPTURE_LOCMIN_Val << TCC_FCTRLA_CAPTURE_Pos) /* (TCC_FCTRLA) Minimum local detection Position */ 317 #define TCC_FCTRLA_CAPTURE_LOCMAX (TCC_FCTRLA_CAPTURE_LOCMAX_Val << TCC_FCTRLA_CAPTURE_Pos) /* (TCC_FCTRLA) Maximum local detection Position */ 318 #define TCC_FCTRLA_CAPTURE_DERIV0 (TCC_FCTRLA_CAPTURE_DERIV0_Val << TCC_FCTRLA_CAPTURE_Pos) /* (TCC_FCTRLA) Minimum and maximum local detection Position */ 319 #define TCC_FCTRLA_CAPTURE_CAPTMARK (TCC_FCTRLA_CAPTURE_CAPTMARK_Val << TCC_FCTRLA_CAPTURE_Pos) /* (TCC_FCTRLA) Capture with ramp index as MSB value Position */ 320 #define TCC_FCTRLA_BLANKPRESC_Pos _UINT32_(15) /* (TCC_FCTRLA) Fault A Blanking Prescaler Position */ 321 #define TCC_FCTRLA_BLANKPRESC_Msk (_UINT32_(0x1) << TCC_FCTRLA_BLANKPRESC_Pos) /* (TCC_FCTRLA) Fault A Blanking Prescaler Mask */ 322 #define TCC_FCTRLA_BLANKPRESC(value) (TCC_FCTRLA_BLANKPRESC_Msk & (_UINT32_(value) << TCC_FCTRLA_BLANKPRESC_Pos)) /* Assignment of value for BLANKPRESC in the TCC_FCTRLA register */ 323 #define TCC_FCTRLA_BLANKVAL_Pos _UINT32_(16) /* (TCC_FCTRLA) Fault A Blanking Time Position */ 324 #define TCC_FCTRLA_BLANKVAL_Msk (_UINT32_(0xFF) << TCC_FCTRLA_BLANKVAL_Pos) /* (TCC_FCTRLA) Fault A Blanking Time Mask */ 325 #define TCC_FCTRLA_BLANKVAL(value) (TCC_FCTRLA_BLANKVAL_Msk & (_UINT32_(value) << TCC_FCTRLA_BLANKVAL_Pos)) /* Assignment of value for BLANKVAL in the TCC_FCTRLA register */ 326 #define TCC_FCTRLA_FILTERVAL_Pos _UINT32_(24) /* (TCC_FCTRLA) Fault A Filter Value Position */ 327 #define TCC_FCTRLA_FILTERVAL_Msk (_UINT32_(0xF) << TCC_FCTRLA_FILTERVAL_Pos) /* (TCC_FCTRLA) Fault A Filter Value Mask */ 328 #define TCC_FCTRLA_FILTERVAL(value) (TCC_FCTRLA_FILTERVAL_Msk & (_UINT32_(value) << TCC_FCTRLA_FILTERVAL_Pos)) /* Assignment of value for FILTERVAL in the TCC_FCTRLA register */ 329 #define TCC_FCTRLA_Msk _UINT32_(0x0FFFFFFB) /* (TCC_FCTRLA) Register Mask */ 330 331 332 /* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable Fault B Configuration -------- */ 333 #define TCC_FCTRLB_RESETVALUE _UINT32_(0x00) /* (TCC_FCTRLB) Recoverable Fault B Configuration Reset Value */ 334 335 #define TCC_FCTRLB_SRC_Pos _UINT32_(0) /* (TCC_FCTRLB) Fault B Source Position */ 336 #define TCC_FCTRLB_SRC_Msk (_UINT32_(0x3) << TCC_FCTRLB_SRC_Pos) /* (TCC_FCTRLB) Fault B Source Mask */ 337 #define TCC_FCTRLB_SRC(value) (TCC_FCTRLB_SRC_Msk & (_UINT32_(value) << TCC_FCTRLB_SRC_Pos)) /* Assignment of value for SRC in the TCC_FCTRLB register */ 338 #define TCC_FCTRLB_SRC_DISABLE_Val _UINT32_(0x0) /* (TCC_FCTRLB) Fault input disabled */ 339 #define TCC_FCTRLB_SRC_ENABLE_Val _UINT32_(0x1) /* (TCC_FCTRLB) MCEx (x=0,1) event input */ 340 #define TCC_FCTRLB_SRC_INVERT_Val _UINT32_(0x2) /* (TCC_FCTRLB) Inverted MCEx (x=0,1) event input */ 341 #define TCC_FCTRLB_SRC_ALTFAULT_Val _UINT32_(0x3) /* (TCC_FCTRLB) Alternate fault (A or B) state at the end of the previous period */ 342 #define TCC_FCTRLB_SRC_DISABLE (TCC_FCTRLB_SRC_DISABLE_Val << TCC_FCTRLB_SRC_Pos) /* (TCC_FCTRLB) Fault input disabled Position */ 343 #define TCC_FCTRLB_SRC_ENABLE (TCC_FCTRLB_SRC_ENABLE_Val << TCC_FCTRLB_SRC_Pos) /* (TCC_FCTRLB) MCEx (x=0,1) event input Position */ 344 #define TCC_FCTRLB_SRC_INVERT (TCC_FCTRLB_SRC_INVERT_Val << TCC_FCTRLB_SRC_Pos) /* (TCC_FCTRLB) Inverted MCEx (x=0,1) event input Position */ 345 #define TCC_FCTRLB_SRC_ALTFAULT (TCC_FCTRLB_SRC_ALTFAULT_Val << TCC_FCTRLB_SRC_Pos) /* (TCC_FCTRLB) Alternate fault (A or B) state at the end of the previous period Position */ 346 #define TCC_FCTRLB_KEEP_Pos _UINT32_(3) /* (TCC_FCTRLB) Fault B Keeper Position */ 347 #define TCC_FCTRLB_KEEP_Msk (_UINT32_(0x1) << TCC_FCTRLB_KEEP_Pos) /* (TCC_FCTRLB) Fault B Keeper Mask */ 348 #define TCC_FCTRLB_KEEP(value) (TCC_FCTRLB_KEEP_Msk & (_UINT32_(value) << TCC_FCTRLB_KEEP_Pos)) /* Assignment of value for KEEP in the TCC_FCTRLB register */ 349 #define TCC_FCTRLB_QUAL_Pos _UINT32_(4) /* (TCC_FCTRLB) Fault B Qualification Position */ 350 #define TCC_FCTRLB_QUAL_Msk (_UINT32_(0x1) << TCC_FCTRLB_QUAL_Pos) /* (TCC_FCTRLB) Fault B Qualification Mask */ 351 #define TCC_FCTRLB_QUAL(value) (TCC_FCTRLB_QUAL_Msk & (_UINT32_(value) << TCC_FCTRLB_QUAL_Pos)) /* Assignment of value for QUAL in the TCC_FCTRLB register */ 352 #define TCC_FCTRLB_BLANK_Pos _UINT32_(5) /* (TCC_FCTRLB) Fault B Blanking Mode Position */ 353 #define TCC_FCTRLB_BLANK_Msk (_UINT32_(0x3) << TCC_FCTRLB_BLANK_Pos) /* (TCC_FCTRLB) Fault B Blanking Mode Mask */ 354 #define TCC_FCTRLB_BLANK(value) (TCC_FCTRLB_BLANK_Msk & (_UINT32_(value) << TCC_FCTRLB_BLANK_Pos)) /* Assignment of value for BLANK in the TCC_FCTRLB register */ 355 #define TCC_FCTRLB_BLANK_START_Val _UINT32_(0x0) /* (TCC_FCTRLB) Blanking applied from start of the ramp */ 356 #define TCC_FCTRLB_BLANK_RISE_Val _UINT32_(0x1) /* (TCC_FCTRLB) Blanking applied from rising edge of the output waveform */ 357 #define TCC_FCTRLB_BLANK_FALL_Val _UINT32_(0x2) /* (TCC_FCTRLB) Blanking applied from falling edge of the output waveform */ 358 #define TCC_FCTRLB_BLANK_BOTH_Val _UINT32_(0x3) /* (TCC_FCTRLB) Blanking applied from each toggle of the output waveform */ 359 #define TCC_FCTRLB_BLANK_START (TCC_FCTRLB_BLANK_START_Val << TCC_FCTRLB_BLANK_Pos) /* (TCC_FCTRLB) Blanking applied from start of the ramp Position */ 360 #define TCC_FCTRLB_BLANK_RISE (TCC_FCTRLB_BLANK_RISE_Val << TCC_FCTRLB_BLANK_Pos) /* (TCC_FCTRLB) Blanking applied from rising edge of the output waveform Position */ 361 #define TCC_FCTRLB_BLANK_FALL (TCC_FCTRLB_BLANK_FALL_Val << TCC_FCTRLB_BLANK_Pos) /* (TCC_FCTRLB) Blanking applied from falling edge of the output waveform Position */ 362 #define TCC_FCTRLB_BLANK_BOTH (TCC_FCTRLB_BLANK_BOTH_Val << TCC_FCTRLB_BLANK_Pos) /* (TCC_FCTRLB) Blanking applied from each toggle of the output waveform Position */ 363 #define TCC_FCTRLB_RESTART_Pos _UINT32_(7) /* (TCC_FCTRLB) Fault B Restart Position */ 364 #define TCC_FCTRLB_RESTART_Msk (_UINT32_(0x1) << TCC_FCTRLB_RESTART_Pos) /* (TCC_FCTRLB) Fault B Restart Mask */ 365 #define TCC_FCTRLB_RESTART(value) (TCC_FCTRLB_RESTART_Msk & (_UINT32_(value) << TCC_FCTRLB_RESTART_Pos)) /* Assignment of value for RESTART in the TCC_FCTRLB register */ 366 #define TCC_FCTRLB_HALT_Pos _UINT32_(8) /* (TCC_FCTRLB) Fault B Halt Mode Position */ 367 #define TCC_FCTRLB_HALT_Msk (_UINT32_(0x3) << TCC_FCTRLB_HALT_Pos) /* (TCC_FCTRLB) Fault B Halt Mode Mask */ 368 #define TCC_FCTRLB_HALT(value) (TCC_FCTRLB_HALT_Msk & (_UINT32_(value) << TCC_FCTRLB_HALT_Pos)) /* Assignment of value for HALT in the TCC_FCTRLB register */ 369 #define TCC_FCTRLB_HALT_DISABLE_Val _UINT32_(0x0) /* (TCC_FCTRLB) Halt action disabled */ 370 #define TCC_FCTRLB_HALT_HW_Val _UINT32_(0x1) /* (TCC_FCTRLB) Hardware halt action */ 371 #define TCC_FCTRLB_HALT_SW_Val _UINT32_(0x2) /* (TCC_FCTRLB) Software halt action */ 372 #define TCC_FCTRLB_HALT_NR_Val _UINT32_(0x3) /* (TCC_FCTRLB) Non-recoverable fault */ 373 #define TCC_FCTRLB_HALT_DISABLE (TCC_FCTRLB_HALT_DISABLE_Val << TCC_FCTRLB_HALT_Pos) /* (TCC_FCTRLB) Halt action disabled Position */ 374 #define TCC_FCTRLB_HALT_HW (TCC_FCTRLB_HALT_HW_Val << TCC_FCTRLB_HALT_Pos) /* (TCC_FCTRLB) Hardware halt action Position */ 375 #define TCC_FCTRLB_HALT_SW (TCC_FCTRLB_HALT_SW_Val << TCC_FCTRLB_HALT_Pos) /* (TCC_FCTRLB) Software halt action Position */ 376 #define TCC_FCTRLB_HALT_NR (TCC_FCTRLB_HALT_NR_Val << TCC_FCTRLB_HALT_Pos) /* (TCC_FCTRLB) Non-recoverable fault Position */ 377 #define TCC_FCTRLB_CHSEL_Pos _UINT32_(10) /* (TCC_FCTRLB) Fault B Capture Channel Position */ 378 #define TCC_FCTRLB_CHSEL_Msk (_UINT32_(0x3) << TCC_FCTRLB_CHSEL_Pos) /* (TCC_FCTRLB) Fault B Capture Channel Mask */ 379 #define TCC_FCTRLB_CHSEL(value) (TCC_FCTRLB_CHSEL_Msk & (_UINT32_(value) << TCC_FCTRLB_CHSEL_Pos)) /* Assignment of value for CHSEL in the TCC_FCTRLB register */ 380 #define TCC_FCTRLB_CHSEL_CC0_Val _UINT32_(0x0) /* (TCC_FCTRLB) Capture value stored in channel 0 */ 381 #define TCC_FCTRLB_CHSEL_CC1_Val _UINT32_(0x1) /* (TCC_FCTRLB) Capture value stored in channel 1 */ 382 #define TCC_FCTRLB_CHSEL_CC2_Val _UINT32_(0x2) /* (TCC_FCTRLB) Capture value stored in channel 2 */ 383 #define TCC_FCTRLB_CHSEL_CC3_Val _UINT32_(0x3) /* (TCC_FCTRLB) Capture value stored in channel 3 */ 384 #define TCC_FCTRLB_CHSEL_CC0 (TCC_FCTRLB_CHSEL_CC0_Val << TCC_FCTRLB_CHSEL_Pos) /* (TCC_FCTRLB) Capture value stored in channel 0 Position */ 385 #define TCC_FCTRLB_CHSEL_CC1 (TCC_FCTRLB_CHSEL_CC1_Val << TCC_FCTRLB_CHSEL_Pos) /* (TCC_FCTRLB) Capture value stored in channel 1 Position */ 386 #define TCC_FCTRLB_CHSEL_CC2 (TCC_FCTRLB_CHSEL_CC2_Val << TCC_FCTRLB_CHSEL_Pos) /* (TCC_FCTRLB) Capture value stored in channel 2 Position */ 387 #define TCC_FCTRLB_CHSEL_CC3 (TCC_FCTRLB_CHSEL_CC3_Val << TCC_FCTRLB_CHSEL_Pos) /* (TCC_FCTRLB) Capture value stored in channel 3 Position */ 388 #define TCC_FCTRLB_CAPTURE_Pos _UINT32_(12) /* (TCC_FCTRLB) Fault B Capture Action Position */ 389 #define TCC_FCTRLB_CAPTURE_Msk (_UINT32_(0x7) << TCC_FCTRLB_CAPTURE_Pos) /* (TCC_FCTRLB) Fault B Capture Action Mask */ 390 #define TCC_FCTRLB_CAPTURE(value) (TCC_FCTRLB_CAPTURE_Msk & (_UINT32_(value) << TCC_FCTRLB_CAPTURE_Pos)) /* Assignment of value for CAPTURE in the TCC_FCTRLB register */ 391 #define TCC_FCTRLB_CAPTURE_DISABLE_Val _UINT32_(0x0) /* (TCC_FCTRLB) No capture */ 392 #define TCC_FCTRLB_CAPTURE_CAPT_Val _UINT32_(0x1) /* (TCC_FCTRLB) Capture on fault */ 393 #define TCC_FCTRLB_CAPTURE_CAPTMIN_Val _UINT32_(0x2) /* (TCC_FCTRLB) Minimum capture */ 394 #define TCC_FCTRLB_CAPTURE_CAPTMAX_Val _UINT32_(0x3) /* (TCC_FCTRLB) Maximum capture */ 395 #define TCC_FCTRLB_CAPTURE_LOCMIN_Val _UINT32_(0x4) /* (TCC_FCTRLB) Minimum local detection */ 396 #define TCC_FCTRLB_CAPTURE_LOCMAX_Val _UINT32_(0x5) /* (TCC_FCTRLB) Maximum local detection */ 397 #define TCC_FCTRLB_CAPTURE_DERIV0_Val _UINT32_(0x6) /* (TCC_FCTRLB) Minimum and maximum local detection */ 398 #define TCC_FCTRLB_CAPTURE_CAPTMARK_Val _UINT32_(0x7) /* (TCC_FCTRLB) Capture with ramp index as MSB value */ 399 #define TCC_FCTRLB_CAPTURE_DISABLE (TCC_FCTRLB_CAPTURE_DISABLE_Val << TCC_FCTRLB_CAPTURE_Pos) /* (TCC_FCTRLB) No capture Position */ 400 #define TCC_FCTRLB_CAPTURE_CAPT (TCC_FCTRLB_CAPTURE_CAPT_Val << TCC_FCTRLB_CAPTURE_Pos) /* (TCC_FCTRLB) Capture on fault Position */ 401 #define TCC_FCTRLB_CAPTURE_CAPTMIN (TCC_FCTRLB_CAPTURE_CAPTMIN_Val << TCC_FCTRLB_CAPTURE_Pos) /* (TCC_FCTRLB) Minimum capture Position */ 402 #define TCC_FCTRLB_CAPTURE_CAPTMAX (TCC_FCTRLB_CAPTURE_CAPTMAX_Val << TCC_FCTRLB_CAPTURE_Pos) /* (TCC_FCTRLB) Maximum capture Position */ 403 #define TCC_FCTRLB_CAPTURE_LOCMIN (TCC_FCTRLB_CAPTURE_LOCMIN_Val << TCC_FCTRLB_CAPTURE_Pos) /* (TCC_FCTRLB) Minimum local detection Position */ 404 #define TCC_FCTRLB_CAPTURE_LOCMAX (TCC_FCTRLB_CAPTURE_LOCMAX_Val << TCC_FCTRLB_CAPTURE_Pos) /* (TCC_FCTRLB) Maximum local detection Position */ 405 #define TCC_FCTRLB_CAPTURE_DERIV0 (TCC_FCTRLB_CAPTURE_DERIV0_Val << TCC_FCTRLB_CAPTURE_Pos) /* (TCC_FCTRLB) Minimum and maximum local detection Position */ 406 #define TCC_FCTRLB_CAPTURE_CAPTMARK (TCC_FCTRLB_CAPTURE_CAPTMARK_Val << TCC_FCTRLB_CAPTURE_Pos) /* (TCC_FCTRLB) Capture with ramp index as MSB value Position */ 407 #define TCC_FCTRLB_BLANKPRESC_Pos _UINT32_(15) /* (TCC_FCTRLB) Fault B Blanking Prescaler Position */ 408 #define TCC_FCTRLB_BLANKPRESC_Msk (_UINT32_(0x1) << TCC_FCTRLB_BLANKPRESC_Pos) /* (TCC_FCTRLB) Fault B Blanking Prescaler Mask */ 409 #define TCC_FCTRLB_BLANKPRESC(value) (TCC_FCTRLB_BLANKPRESC_Msk & (_UINT32_(value) << TCC_FCTRLB_BLANKPRESC_Pos)) /* Assignment of value for BLANKPRESC in the TCC_FCTRLB register */ 410 #define TCC_FCTRLB_BLANKVAL_Pos _UINT32_(16) /* (TCC_FCTRLB) Fault B Blanking Time Position */ 411 #define TCC_FCTRLB_BLANKVAL_Msk (_UINT32_(0xFF) << TCC_FCTRLB_BLANKVAL_Pos) /* (TCC_FCTRLB) Fault B Blanking Time Mask */ 412 #define TCC_FCTRLB_BLANKVAL(value) (TCC_FCTRLB_BLANKVAL_Msk & (_UINT32_(value) << TCC_FCTRLB_BLANKVAL_Pos)) /* Assignment of value for BLANKVAL in the TCC_FCTRLB register */ 413 #define TCC_FCTRLB_FILTERVAL_Pos _UINT32_(24) /* (TCC_FCTRLB) Fault B Filter Value Position */ 414 #define TCC_FCTRLB_FILTERVAL_Msk (_UINT32_(0xF) << TCC_FCTRLB_FILTERVAL_Pos) /* (TCC_FCTRLB) Fault B Filter Value Mask */ 415 #define TCC_FCTRLB_FILTERVAL(value) (TCC_FCTRLB_FILTERVAL_Msk & (_UINT32_(value) << TCC_FCTRLB_FILTERVAL_Pos)) /* Assignment of value for FILTERVAL in the TCC_FCTRLB register */ 416 #define TCC_FCTRLB_Msk _UINT32_(0x0FFFFFFB) /* (TCC_FCTRLB) Register Mask */ 417 418 419 /* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */ 420 #define TCC_WEXCTRL_RESETVALUE _UINT32_(0x00) /* (TCC_WEXCTRL) Waveform Extension Configuration Reset Value */ 421 422 #define TCC_WEXCTRL_OTMX_Pos _UINT32_(0) /* (TCC_WEXCTRL) Output Matrix Position */ 423 #define TCC_WEXCTRL_OTMX_Msk (_UINT32_(0x3) << TCC_WEXCTRL_OTMX_Pos) /* (TCC_WEXCTRL) Output Matrix Mask */ 424 #define TCC_WEXCTRL_OTMX(value) (TCC_WEXCTRL_OTMX_Msk & (_UINT32_(value) << TCC_WEXCTRL_OTMX_Pos)) /* Assignment of value for OTMX in the TCC_WEXCTRL register */ 425 #define TCC_WEXCTRL_DTIEN0_Pos _UINT32_(8) /* (TCC_WEXCTRL) Dead-time Insertion Generator 0 Enable Position */ 426 #define TCC_WEXCTRL_DTIEN0_Msk (_UINT32_(0x1) << TCC_WEXCTRL_DTIEN0_Pos) /* (TCC_WEXCTRL) Dead-time Insertion Generator 0 Enable Mask */ 427 #define TCC_WEXCTRL_DTIEN0(value) (TCC_WEXCTRL_DTIEN0_Msk & (_UINT32_(value) << TCC_WEXCTRL_DTIEN0_Pos)) /* Assignment of value for DTIEN0 in the TCC_WEXCTRL register */ 428 #define TCC_WEXCTRL_DTIEN1_Pos _UINT32_(9) /* (TCC_WEXCTRL) Dead-time Insertion Generator 1 Enable Position */ 429 #define TCC_WEXCTRL_DTIEN1_Msk (_UINT32_(0x1) << TCC_WEXCTRL_DTIEN1_Pos) /* (TCC_WEXCTRL) Dead-time Insertion Generator 1 Enable Mask */ 430 #define TCC_WEXCTRL_DTIEN1(value) (TCC_WEXCTRL_DTIEN1_Msk & (_UINT32_(value) << TCC_WEXCTRL_DTIEN1_Pos)) /* Assignment of value for DTIEN1 in the TCC_WEXCTRL register */ 431 #define TCC_WEXCTRL_DTIEN2_Pos _UINT32_(10) /* (TCC_WEXCTRL) Dead-time Insertion Generator 2 Enable Position */ 432 #define TCC_WEXCTRL_DTIEN2_Msk (_UINT32_(0x1) << TCC_WEXCTRL_DTIEN2_Pos) /* (TCC_WEXCTRL) Dead-time Insertion Generator 2 Enable Mask */ 433 #define TCC_WEXCTRL_DTIEN2(value) (TCC_WEXCTRL_DTIEN2_Msk & (_UINT32_(value) << TCC_WEXCTRL_DTIEN2_Pos)) /* Assignment of value for DTIEN2 in the TCC_WEXCTRL register */ 434 #define TCC_WEXCTRL_DTIEN3_Pos _UINT32_(11) /* (TCC_WEXCTRL) Dead-time Insertion Generator 3 Enable Position */ 435 #define TCC_WEXCTRL_DTIEN3_Msk (_UINT32_(0x1) << TCC_WEXCTRL_DTIEN3_Pos) /* (TCC_WEXCTRL) Dead-time Insertion Generator 3 Enable Mask */ 436 #define TCC_WEXCTRL_DTIEN3(value) (TCC_WEXCTRL_DTIEN3_Msk & (_UINT32_(value) << TCC_WEXCTRL_DTIEN3_Pos)) /* Assignment of value for DTIEN3 in the TCC_WEXCTRL register */ 437 #define TCC_WEXCTRL_DTLS_Pos _UINT32_(16) /* (TCC_WEXCTRL) Dead-time Low Side Outputs Value Position */ 438 #define TCC_WEXCTRL_DTLS_Msk (_UINT32_(0xFF) << TCC_WEXCTRL_DTLS_Pos) /* (TCC_WEXCTRL) Dead-time Low Side Outputs Value Mask */ 439 #define TCC_WEXCTRL_DTLS(value) (TCC_WEXCTRL_DTLS_Msk & (_UINT32_(value) << TCC_WEXCTRL_DTLS_Pos)) /* Assignment of value for DTLS in the TCC_WEXCTRL register */ 440 #define TCC_WEXCTRL_DTHS_Pos _UINT32_(24) /* (TCC_WEXCTRL) Dead-time High Side Outputs Value Position */ 441 #define TCC_WEXCTRL_DTHS_Msk (_UINT32_(0xFF) << TCC_WEXCTRL_DTHS_Pos) /* (TCC_WEXCTRL) Dead-time High Side Outputs Value Mask */ 442 #define TCC_WEXCTRL_DTHS(value) (TCC_WEXCTRL_DTHS_Msk & (_UINT32_(value) << TCC_WEXCTRL_DTHS_Pos)) /* Assignment of value for DTHS in the TCC_WEXCTRL register */ 443 #define TCC_WEXCTRL_Msk _UINT32_(0xFFFF0F03) /* (TCC_WEXCTRL) Register Mask */ 444 445 #define TCC_WEXCTRL_DTIEN_Pos _UINT32_(8) /* (TCC_WEXCTRL Position) Dead-time Insertion Generator x Enable */ 446 #define TCC_WEXCTRL_DTIEN_Msk (_UINT32_(0xF) << TCC_WEXCTRL_DTIEN_Pos) /* (TCC_WEXCTRL Mask) DTIEN */ 447 #define TCC_WEXCTRL_DTIEN(value) (TCC_WEXCTRL_DTIEN_Msk & (_UINT32_(value) << TCC_WEXCTRL_DTIEN_Pos)) 448 449 /* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Control -------- */ 450 #define TCC_DRVCTRL_RESETVALUE _UINT32_(0x00) /* (TCC_DRVCTRL) Driver Control Reset Value */ 451 452 #define TCC_DRVCTRL_NRE0_Pos _UINT32_(0) /* (TCC_DRVCTRL) Non-Recoverable State 0 Output Enable Position */ 453 #define TCC_DRVCTRL_NRE0_Msk (_UINT32_(0x1) << TCC_DRVCTRL_NRE0_Pos) /* (TCC_DRVCTRL) Non-Recoverable State 0 Output Enable Mask */ 454 #define TCC_DRVCTRL_NRE0(value) (TCC_DRVCTRL_NRE0_Msk & (_UINT32_(value) << TCC_DRVCTRL_NRE0_Pos)) /* Assignment of value for NRE0 in the TCC_DRVCTRL register */ 455 #define TCC_DRVCTRL_NRE1_Pos _UINT32_(1) /* (TCC_DRVCTRL) Non-Recoverable State 1 Output Enable Position */ 456 #define TCC_DRVCTRL_NRE1_Msk (_UINT32_(0x1) << TCC_DRVCTRL_NRE1_Pos) /* (TCC_DRVCTRL) Non-Recoverable State 1 Output Enable Mask */ 457 #define TCC_DRVCTRL_NRE1(value) (TCC_DRVCTRL_NRE1_Msk & (_UINT32_(value) << TCC_DRVCTRL_NRE1_Pos)) /* Assignment of value for NRE1 in the TCC_DRVCTRL register */ 458 #define TCC_DRVCTRL_NRE2_Pos _UINT32_(2) /* (TCC_DRVCTRL) Non-Recoverable State 2 Output Enable Position */ 459 #define TCC_DRVCTRL_NRE2_Msk (_UINT32_(0x1) << TCC_DRVCTRL_NRE2_Pos) /* (TCC_DRVCTRL) Non-Recoverable State 2 Output Enable Mask */ 460 #define TCC_DRVCTRL_NRE2(value) (TCC_DRVCTRL_NRE2_Msk & (_UINT32_(value) << TCC_DRVCTRL_NRE2_Pos)) /* Assignment of value for NRE2 in the TCC_DRVCTRL register */ 461 #define TCC_DRVCTRL_NRE3_Pos _UINT32_(3) /* (TCC_DRVCTRL) Non-Recoverable State 3 Output Enable Position */ 462 #define TCC_DRVCTRL_NRE3_Msk (_UINT32_(0x1) << TCC_DRVCTRL_NRE3_Pos) /* (TCC_DRVCTRL) Non-Recoverable State 3 Output Enable Mask */ 463 #define TCC_DRVCTRL_NRE3(value) (TCC_DRVCTRL_NRE3_Msk & (_UINT32_(value) << TCC_DRVCTRL_NRE3_Pos)) /* Assignment of value for NRE3 in the TCC_DRVCTRL register */ 464 #define TCC_DRVCTRL_NRE4_Pos _UINT32_(4) /* (TCC_DRVCTRL) Non-Recoverable State 4 Output Enable Position */ 465 #define TCC_DRVCTRL_NRE4_Msk (_UINT32_(0x1) << TCC_DRVCTRL_NRE4_Pos) /* (TCC_DRVCTRL) Non-Recoverable State 4 Output Enable Mask */ 466 #define TCC_DRVCTRL_NRE4(value) (TCC_DRVCTRL_NRE4_Msk & (_UINT32_(value) << TCC_DRVCTRL_NRE4_Pos)) /* Assignment of value for NRE4 in the TCC_DRVCTRL register */ 467 #define TCC_DRVCTRL_NRE5_Pos _UINT32_(5) /* (TCC_DRVCTRL) Non-Recoverable State 5 Output Enable Position */ 468 #define TCC_DRVCTRL_NRE5_Msk (_UINT32_(0x1) << TCC_DRVCTRL_NRE5_Pos) /* (TCC_DRVCTRL) Non-Recoverable State 5 Output Enable Mask */ 469 #define TCC_DRVCTRL_NRE5(value) (TCC_DRVCTRL_NRE5_Msk & (_UINT32_(value) << TCC_DRVCTRL_NRE5_Pos)) /* Assignment of value for NRE5 in the TCC_DRVCTRL register */ 470 #define TCC_DRVCTRL_NRE6_Pos _UINT32_(6) /* (TCC_DRVCTRL) Non-Recoverable State 6 Output Enable Position */ 471 #define TCC_DRVCTRL_NRE6_Msk (_UINT32_(0x1) << TCC_DRVCTRL_NRE6_Pos) /* (TCC_DRVCTRL) Non-Recoverable State 6 Output Enable Mask */ 472 #define TCC_DRVCTRL_NRE6(value) (TCC_DRVCTRL_NRE6_Msk & (_UINT32_(value) << TCC_DRVCTRL_NRE6_Pos)) /* Assignment of value for NRE6 in the TCC_DRVCTRL register */ 473 #define TCC_DRVCTRL_NRE7_Pos _UINT32_(7) /* (TCC_DRVCTRL) Non-Recoverable State 7 Output Enable Position */ 474 #define TCC_DRVCTRL_NRE7_Msk (_UINT32_(0x1) << TCC_DRVCTRL_NRE7_Pos) /* (TCC_DRVCTRL) Non-Recoverable State 7 Output Enable Mask */ 475 #define TCC_DRVCTRL_NRE7(value) (TCC_DRVCTRL_NRE7_Msk & (_UINT32_(value) << TCC_DRVCTRL_NRE7_Pos)) /* Assignment of value for NRE7 in the TCC_DRVCTRL register */ 476 #define TCC_DRVCTRL_NRV0_Pos _UINT32_(8) /* (TCC_DRVCTRL) Non-Recoverable State 0 Output Value Position */ 477 #define TCC_DRVCTRL_NRV0_Msk (_UINT32_(0x1) << TCC_DRVCTRL_NRV0_Pos) /* (TCC_DRVCTRL) Non-Recoverable State 0 Output Value Mask */ 478 #define TCC_DRVCTRL_NRV0(value) (TCC_DRVCTRL_NRV0_Msk & (_UINT32_(value) << TCC_DRVCTRL_NRV0_Pos)) /* Assignment of value for NRV0 in the TCC_DRVCTRL register */ 479 #define TCC_DRVCTRL_NRV1_Pos _UINT32_(9) /* (TCC_DRVCTRL) Non-Recoverable State 1 Output Value Position */ 480 #define TCC_DRVCTRL_NRV1_Msk (_UINT32_(0x1) << TCC_DRVCTRL_NRV1_Pos) /* (TCC_DRVCTRL) Non-Recoverable State 1 Output Value Mask */ 481 #define TCC_DRVCTRL_NRV1(value) (TCC_DRVCTRL_NRV1_Msk & (_UINT32_(value) << TCC_DRVCTRL_NRV1_Pos)) /* Assignment of value for NRV1 in the TCC_DRVCTRL register */ 482 #define TCC_DRVCTRL_NRV2_Pos _UINT32_(10) /* (TCC_DRVCTRL) Non-Recoverable State 2 Output Value Position */ 483 #define TCC_DRVCTRL_NRV2_Msk (_UINT32_(0x1) << TCC_DRVCTRL_NRV2_Pos) /* (TCC_DRVCTRL) Non-Recoverable State 2 Output Value Mask */ 484 #define TCC_DRVCTRL_NRV2(value) (TCC_DRVCTRL_NRV2_Msk & (_UINT32_(value) << TCC_DRVCTRL_NRV2_Pos)) /* Assignment of value for NRV2 in the TCC_DRVCTRL register */ 485 #define TCC_DRVCTRL_NRV3_Pos _UINT32_(11) /* (TCC_DRVCTRL) Non-Recoverable State 3 Output Value Position */ 486 #define TCC_DRVCTRL_NRV3_Msk (_UINT32_(0x1) << TCC_DRVCTRL_NRV3_Pos) /* (TCC_DRVCTRL) Non-Recoverable State 3 Output Value Mask */ 487 #define TCC_DRVCTRL_NRV3(value) (TCC_DRVCTRL_NRV3_Msk & (_UINT32_(value) << TCC_DRVCTRL_NRV3_Pos)) /* Assignment of value for NRV3 in the TCC_DRVCTRL register */ 488 #define TCC_DRVCTRL_NRV4_Pos _UINT32_(12) /* (TCC_DRVCTRL) Non-Recoverable State 4 Output Value Position */ 489 #define TCC_DRVCTRL_NRV4_Msk (_UINT32_(0x1) << TCC_DRVCTRL_NRV4_Pos) /* (TCC_DRVCTRL) Non-Recoverable State 4 Output Value Mask */ 490 #define TCC_DRVCTRL_NRV4(value) (TCC_DRVCTRL_NRV4_Msk & (_UINT32_(value) << TCC_DRVCTRL_NRV4_Pos)) /* Assignment of value for NRV4 in the TCC_DRVCTRL register */ 491 #define TCC_DRVCTRL_NRV5_Pos _UINT32_(13) /* (TCC_DRVCTRL) Non-Recoverable State 5 Output Value Position */ 492 #define TCC_DRVCTRL_NRV5_Msk (_UINT32_(0x1) << TCC_DRVCTRL_NRV5_Pos) /* (TCC_DRVCTRL) Non-Recoverable State 5 Output Value Mask */ 493 #define TCC_DRVCTRL_NRV5(value) (TCC_DRVCTRL_NRV5_Msk & (_UINT32_(value) << TCC_DRVCTRL_NRV5_Pos)) /* Assignment of value for NRV5 in the TCC_DRVCTRL register */ 494 #define TCC_DRVCTRL_NRV6_Pos _UINT32_(14) /* (TCC_DRVCTRL) Non-Recoverable State 6 Output Value Position */ 495 #define TCC_DRVCTRL_NRV6_Msk (_UINT32_(0x1) << TCC_DRVCTRL_NRV6_Pos) /* (TCC_DRVCTRL) Non-Recoverable State 6 Output Value Mask */ 496 #define TCC_DRVCTRL_NRV6(value) (TCC_DRVCTRL_NRV6_Msk & (_UINT32_(value) << TCC_DRVCTRL_NRV6_Pos)) /* Assignment of value for NRV6 in the TCC_DRVCTRL register */ 497 #define TCC_DRVCTRL_NRV7_Pos _UINT32_(15) /* (TCC_DRVCTRL) Non-Recoverable State 7 Output Value Position */ 498 #define TCC_DRVCTRL_NRV7_Msk (_UINT32_(0x1) << TCC_DRVCTRL_NRV7_Pos) /* (TCC_DRVCTRL) Non-Recoverable State 7 Output Value Mask */ 499 #define TCC_DRVCTRL_NRV7(value) (TCC_DRVCTRL_NRV7_Msk & (_UINT32_(value) << TCC_DRVCTRL_NRV7_Pos)) /* Assignment of value for NRV7 in the TCC_DRVCTRL register */ 500 #define TCC_DRVCTRL_INVEN0_Pos _UINT32_(16) /* (TCC_DRVCTRL) Output Waveform 0 Inversion Position */ 501 #define TCC_DRVCTRL_INVEN0_Msk (_UINT32_(0x1) << TCC_DRVCTRL_INVEN0_Pos) /* (TCC_DRVCTRL) Output Waveform 0 Inversion Mask */ 502 #define TCC_DRVCTRL_INVEN0(value) (TCC_DRVCTRL_INVEN0_Msk & (_UINT32_(value) << TCC_DRVCTRL_INVEN0_Pos)) /* Assignment of value for INVEN0 in the TCC_DRVCTRL register */ 503 #define TCC_DRVCTRL_INVEN1_Pos _UINT32_(17) /* (TCC_DRVCTRL) Output Waveform 1 Inversion Position */ 504 #define TCC_DRVCTRL_INVEN1_Msk (_UINT32_(0x1) << TCC_DRVCTRL_INVEN1_Pos) /* (TCC_DRVCTRL) Output Waveform 1 Inversion Mask */ 505 #define TCC_DRVCTRL_INVEN1(value) (TCC_DRVCTRL_INVEN1_Msk & (_UINT32_(value) << TCC_DRVCTRL_INVEN1_Pos)) /* Assignment of value for INVEN1 in the TCC_DRVCTRL register */ 506 #define TCC_DRVCTRL_INVEN2_Pos _UINT32_(18) /* (TCC_DRVCTRL) Output Waveform 2 Inversion Position */ 507 #define TCC_DRVCTRL_INVEN2_Msk (_UINT32_(0x1) << TCC_DRVCTRL_INVEN2_Pos) /* (TCC_DRVCTRL) Output Waveform 2 Inversion Mask */ 508 #define TCC_DRVCTRL_INVEN2(value) (TCC_DRVCTRL_INVEN2_Msk & (_UINT32_(value) << TCC_DRVCTRL_INVEN2_Pos)) /* Assignment of value for INVEN2 in the TCC_DRVCTRL register */ 509 #define TCC_DRVCTRL_INVEN3_Pos _UINT32_(19) /* (TCC_DRVCTRL) Output Waveform 3 Inversion Position */ 510 #define TCC_DRVCTRL_INVEN3_Msk (_UINT32_(0x1) << TCC_DRVCTRL_INVEN3_Pos) /* (TCC_DRVCTRL) Output Waveform 3 Inversion Mask */ 511 #define TCC_DRVCTRL_INVEN3(value) (TCC_DRVCTRL_INVEN3_Msk & (_UINT32_(value) << TCC_DRVCTRL_INVEN3_Pos)) /* Assignment of value for INVEN3 in the TCC_DRVCTRL register */ 512 #define TCC_DRVCTRL_INVEN4_Pos _UINT32_(20) /* (TCC_DRVCTRL) Output Waveform 4 Inversion Position */ 513 #define TCC_DRVCTRL_INVEN4_Msk (_UINT32_(0x1) << TCC_DRVCTRL_INVEN4_Pos) /* (TCC_DRVCTRL) Output Waveform 4 Inversion Mask */ 514 #define TCC_DRVCTRL_INVEN4(value) (TCC_DRVCTRL_INVEN4_Msk & (_UINT32_(value) << TCC_DRVCTRL_INVEN4_Pos)) /* Assignment of value for INVEN4 in the TCC_DRVCTRL register */ 515 #define TCC_DRVCTRL_INVEN5_Pos _UINT32_(21) /* (TCC_DRVCTRL) Output Waveform 5 Inversion Position */ 516 #define TCC_DRVCTRL_INVEN5_Msk (_UINT32_(0x1) << TCC_DRVCTRL_INVEN5_Pos) /* (TCC_DRVCTRL) Output Waveform 5 Inversion Mask */ 517 #define TCC_DRVCTRL_INVEN5(value) (TCC_DRVCTRL_INVEN5_Msk & (_UINT32_(value) << TCC_DRVCTRL_INVEN5_Pos)) /* Assignment of value for INVEN5 in the TCC_DRVCTRL register */ 518 #define TCC_DRVCTRL_INVEN6_Pos _UINT32_(22) /* (TCC_DRVCTRL) Output Waveform 6 Inversion Position */ 519 #define TCC_DRVCTRL_INVEN6_Msk (_UINT32_(0x1) << TCC_DRVCTRL_INVEN6_Pos) /* (TCC_DRVCTRL) Output Waveform 6 Inversion Mask */ 520 #define TCC_DRVCTRL_INVEN6(value) (TCC_DRVCTRL_INVEN6_Msk & (_UINT32_(value) << TCC_DRVCTRL_INVEN6_Pos)) /* Assignment of value for INVEN6 in the TCC_DRVCTRL register */ 521 #define TCC_DRVCTRL_INVEN7_Pos _UINT32_(23) /* (TCC_DRVCTRL) Output Waveform 7 Inversion Position */ 522 #define TCC_DRVCTRL_INVEN7_Msk (_UINT32_(0x1) << TCC_DRVCTRL_INVEN7_Pos) /* (TCC_DRVCTRL) Output Waveform 7 Inversion Mask */ 523 #define TCC_DRVCTRL_INVEN7(value) (TCC_DRVCTRL_INVEN7_Msk & (_UINT32_(value) << TCC_DRVCTRL_INVEN7_Pos)) /* Assignment of value for INVEN7 in the TCC_DRVCTRL register */ 524 #define TCC_DRVCTRL_FILTERVAL0_Pos _UINT32_(24) /* (TCC_DRVCTRL) Non-Recoverable Fault Input 0 Filter Value Position */ 525 #define TCC_DRVCTRL_FILTERVAL0_Msk (_UINT32_(0xF) << TCC_DRVCTRL_FILTERVAL0_Pos) /* (TCC_DRVCTRL) Non-Recoverable Fault Input 0 Filter Value Mask */ 526 #define TCC_DRVCTRL_FILTERVAL0(value) (TCC_DRVCTRL_FILTERVAL0_Msk & (_UINT32_(value) << TCC_DRVCTRL_FILTERVAL0_Pos)) /* Assignment of value for FILTERVAL0 in the TCC_DRVCTRL register */ 527 #define TCC_DRVCTRL_FILTERVAL1_Pos _UINT32_(28) /* (TCC_DRVCTRL) Non-Recoverable Fault Input 1 Filter Value Position */ 528 #define TCC_DRVCTRL_FILTERVAL1_Msk (_UINT32_(0xF) << TCC_DRVCTRL_FILTERVAL1_Pos) /* (TCC_DRVCTRL) Non-Recoverable Fault Input 1 Filter Value Mask */ 529 #define TCC_DRVCTRL_FILTERVAL1(value) (TCC_DRVCTRL_FILTERVAL1_Msk & (_UINT32_(value) << TCC_DRVCTRL_FILTERVAL1_Pos)) /* Assignment of value for FILTERVAL1 in the TCC_DRVCTRL register */ 530 #define TCC_DRVCTRL_Msk _UINT32_(0xFFFFFFFF) /* (TCC_DRVCTRL) Register Mask */ 531 532 #define TCC_DRVCTRL_NRE_Pos _UINT32_(0) /* (TCC_DRVCTRL Position) Non-Recoverable State x Output Enable */ 533 #define TCC_DRVCTRL_NRE_Msk (_UINT32_(0xFF) << TCC_DRVCTRL_NRE_Pos) /* (TCC_DRVCTRL Mask) NRE */ 534 #define TCC_DRVCTRL_NRE(value) (TCC_DRVCTRL_NRE_Msk & (_UINT32_(value) << TCC_DRVCTRL_NRE_Pos)) 535 #define TCC_DRVCTRL_NRV_Pos _UINT32_(8) /* (TCC_DRVCTRL Position) Non-Recoverable State x Output Value */ 536 #define TCC_DRVCTRL_NRV_Msk (_UINT32_(0xFF) << TCC_DRVCTRL_NRV_Pos) /* (TCC_DRVCTRL Mask) NRV */ 537 #define TCC_DRVCTRL_NRV(value) (TCC_DRVCTRL_NRV_Msk & (_UINT32_(value) << TCC_DRVCTRL_NRV_Pos)) 538 #define TCC_DRVCTRL_INVEN_Pos _UINT32_(16) /* (TCC_DRVCTRL Position) Output Waveform x Inversion */ 539 #define TCC_DRVCTRL_INVEN_Msk (_UINT32_(0xFF) << TCC_DRVCTRL_INVEN_Pos) /* (TCC_DRVCTRL Mask) INVEN */ 540 #define TCC_DRVCTRL_INVEN(value) (TCC_DRVCTRL_INVEN_Msk & (_UINT32_(value) << TCC_DRVCTRL_INVEN_Pos)) 541 542 /* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W 8) Debug Control -------- */ 543 #define TCC_DBGCTRL_RESETVALUE _UINT8_(0x00) /* (TCC_DBGCTRL) Debug Control Reset Value */ 544 545 #define TCC_DBGCTRL_DBGRUN_Pos _UINT8_(0) /* (TCC_DBGCTRL) Debug Running Mode Position */ 546 #define TCC_DBGCTRL_DBGRUN_Msk (_UINT8_(0x1) << TCC_DBGCTRL_DBGRUN_Pos) /* (TCC_DBGCTRL) Debug Running Mode Mask */ 547 #define TCC_DBGCTRL_DBGRUN(value) (TCC_DBGCTRL_DBGRUN_Msk & (_UINT8_(value) << TCC_DBGCTRL_DBGRUN_Pos)) /* Assignment of value for DBGRUN in the TCC_DBGCTRL register */ 548 #define TCC_DBGCTRL_FDDBD_Pos _UINT8_(2) /* (TCC_DBGCTRL) Fault Detection on Debug Break Detection Position */ 549 #define TCC_DBGCTRL_FDDBD_Msk (_UINT8_(0x1) << TCC_DBGCTRL_FDDBD_Pos) /* (TCC_DBGCTRL) Fault Detection on Debug Break Detection Mask */ 550 #define TCC_DBGCTRL_FDDBD(value) (TCC_DBGCTRL_FDDBD_Msk & (_UINT8_(value) << TCC_DBGCTRL_FDDBD_Pos)) /* Assignment of value for FDDBD in the TCC_DBGCTRL register */ 551 #define TCC_DBGCTRL_Msk _UINT8_(0x05) /* (TCC_DBGCTRL) Register Mask */ 552 553 554 /* -------- TCC_EVCTRL : (TCC Offset: 0x20) (R/W 32) Event Control -------- */ 555 #define TCC_EVCTRL_RESETVALUE _UINT32_(0x00) /* (TCC_EVCTRL) Event Control Reset Value */ 556 557 #define TCC_EVCTRL_EVACT0_Pos _UINT32_(0) /* (TCC_EVCTRL) Timer/counter Input Event0 Action Position */ 558 #define TCC_EVCTRL_EVACT0_Msk (_UINT32_(0x7) << TCC_EVCTRL_EVACT0_Pos) /* (TCC_EVCTRL) Timer/counter Input Event0 Action Mask */ 559 #define TCC_EVCTRL_EVACT0(value) (TCC_EVCTRL_EVACT0_Msk & (_UINT32_(value) << TCC_EVCTRL_EVACT0_Pos)) /* Assignment of value for EVACT0 in the TCC_EVCTRL register */ 560 #define TCC_EVCTRL_EVACT0_OFF_Val _UINT32_(0x0) /* (TCC_EVCTRL) Event action disabled */ 561 #define TCC_EVCTRL_EVACT0_RETRIGGER_Val _UINT32_(0x1) /* (TCC_EVCTRL) Start, restart or re-trigger counter on event */ 562 #define TCC_EVCTRL_EVACT0_COUNTEV_Val _UINT32_(0x2) /* (TCC_EVCTRL) Count on event */ 563 #define TCC_EVCTRL_EVACT0_START_Val _UINT32_(0x3) /* (TCC_EVCTRL) Start counter on event */ 564 #define TCC_EVCTRL_EVACT0_INC_Val _UINT32_(0x4) /* (TCC_EVCTRL) Increment counter on event */ 565 #define TCC_EVCTRL_EVACT0_COUNT_Val _UINT32_(0x5) /* (TCC_EVCTRL) Count on active state of asynchronous event */ 566 #define TCC_EVCTRL_EVACT0_STAMP_Val _UINT32_(0x6) /* (TCC_EVCTRL) Stamp capture */ 567 #define TCC_EVCTRL_EVACT0_FAULT_Val _UINT32_(0x7) /* (TCC_EVCTRL) Non-recoverable fault */ 568 #define TCC_EVCTRL_EVACT0_OFF (TCC_EVCTRL_EVACT0_OFF_Val << TCC_EVCTRL_EVACT0_Pos) /* (TCC_EVCTRL) Event action disabled Position */ 569 #define TCC_EVCTRL_EVACT0_RETRIGGER (TCC_EVCTRL_EVACT0_RETRIGGER_Val << TCC_EVCTRL_EVACT0_Pos) /* (TCC_EVCTRL) Start, restart or re-trigger counter on event Position */ 570 #define TCC_EVCTRL_EVACT0_COUNTEV (TCC_EVCTRL_EVACT0_COUNTEV_Val << TCC_EVCTRL_EVACT0_Pos) /* (TCC_EVCTRL) Count on event Position */ 571 #define TCC_EVCTRL_EVACT0_START (TCC_EVCTRL_EVACT0_START_Val << TCC_EVCTRL_EVACT0_Pos) /* (TCC_EVCTRL) Start counter on event Position */ 572 #define TCC_EVCTRL_EVACT0_INC (TCC_EVCTRL_EVACT0_INC_Val << TCC_EVCTRL_EVACT0_Pos) /* (TCC_EVCTRL) Increment counter on event Position */ 573 #define TCC_EVCTRL_EVACT0_COUNT (TCC_EVCTRL_EVACT0_COUNT_Val << TCC_EVCTRL_EVACT0_Pos) /* (TCC_EVCTRL) Count on active state of asynchronous event Position */ 574 #define TCC_EVCTRL_EVACT0_STAMP (TCC_EVCTRL_EVACT0_STAMP_Val << TCC_EVCTRL_EVACT0_Pos) /* (TCC_EVCTRL) Stamp capture Position */ 575 #define TCC_EVCTRL_EVACT0_FAULT (TCC_EVCTRL_EVACT0_FAULT_Val << TCC_EVCTRL_EVACT0_Pos) /* (TCC_EVCTRL) Non-recoverable fault Position */ 576 #define TCC_EVCTRL_EVACT1_Pos _UINT32_(3) /* (TCC_EVCTRL) Timer/counter Input Event1 Action Position */ 577 #define TCC_EVCTRL_EVACT1_Msk (_UINT32_(0x7) << TCC_EVCTRL_EVACT1_Pos) /* (TCC_EVCTRL) Timer/counter Input Event1 Action Mask */ 578 #define TCC_EVCTRL_EVACT1(value) (TCC_EVCTRL_EVACT1_Msk & (_UINT32_(value) << TCC_EVCTRL_EVACT1_Pos)) /* Assignment of value for EVACT1 in the TCC_EVCTRL register */ 579 #define TCC_EVCTRL_EVACT1_OFF_Val _UINT32_(0x0) /* (TCC_EVCTRL) Event action disabled */ 580 #define TCC_EVCTRL_EVACT1_RETRIGGER_Val _UINT32_(0x1) /* (TCC_EVCTRL) Re-trigger counter on event */ 581 #define TCC_EVCTRL_EVACT1_DIR_Val _UINT32_(0x2) /* (TCC_EVCTRL) Direction control */ 582 #define TCC_EVCTRL_EVACT1_STOP_Val _UINT32_(0x3) /* (TCC_EVCTRL) Stop counter on event */ 583 #define TCC_EVCTRL_EVACT1_DEC_Val _UINT32_(0x4) /* (TCC_EVCTRL) Decrement counter on event */ 584 #define TCC_EVCTRL_EVACT1_PPW_Val _UINT32_(0x5) /* (TCC_EVCTRL) Period capture value in CC0 register, pulse width capture value in CC1 register */ 585 #define TCC_EVCTRL_EVACT1_PWP_Val _UINT32_(0x6) /* (TCC_EVCTRL) Period capture value in CC1 register, pulse width capture value in CC0 register */ 586 #define TCC_EVCTRL_EVACT1_FAULT_Val _UINT32_(0x7) /* (TCC_EVCTRL) Non-recoverable fault */ 587 #define TCC_EVCTRL_EVACT1_OFF (TCC_EVCTRL_EVACT1_OFF_Val << TCC_EVCTRL_EVACT1_Pos) /* (TCC_EVCTRL) Event action disabled Position */ 588 #define TCC_EVCTRL_EVACT1_RETRIGGER (TCC_EVCTRL_EVACT1_RETRIGGER_Val << TCC_EVCTRL_EVACT1_Pos) /* (TCC_EVCTRL) Re-trigger counter on event Position */ 589 #define TCC_EVCTRL_EVACT1_DIR (TCC_EVCTRL_EVACT1_DIR_Val << TCC_EVCTRL_EVACT1_Pos) /* (TCC_EVCTRL) Direction control Position */ 590 #define TCC_EVCTRL_EVACT1_STOP (TCC_EVCTRL_EVACT1_STOP_Val << TCC_EVCTRL_EVACT1_Pos) /* (TCC_EVCTRL) Stop counter on event Position */ 591 #define TCC_EVCTRL_EVACT1_DEC (TCC_EVCTRL_EVACT1_DEC_Val << TCC_EVCTRL_EVACT1_Pos) /* (TCC_EVCTRL) Decrement counter on event Position */ 592 #define TCC_EVCTRL_EVACT1_PPW (TCC_EVCTRL_EVACT1_PPW_Val << TCC_EVCTRL_EVACT1_Pos) /* (TCC_EVCTRL) Period capture value in CC0 register, pulse width capture value in CC1 register Position */ 593 #define TCC_EVCTRL_EVACT1_PWP (TCC_EVCTRL_EVACT1_PWP_Val << TCC_EVCTRL_EVACT1_Pos) /* (TCC_EVCTRL) Period capture value in CC1 register, pulse width capture value in CC0 register Position */ 594 #define TCC_EVCTRL_EVACT1_FAULT (TCC_EVCTRL_EVACT1_FAULT_Val << TCC_EVCTRL_EVACT1_Pos) /* (TCC_EVCTRL) Non-recoverable fault Position */ 595 #define TCC_EVCTRL_CNTSEL_Pos _UINT32_(6) /* (TCC_EVCTRL) Timer/counter Output Event Mode Position */ 596 #define TCC_EVCTRL_CNTSEL_Msk (_UINT32_(0x3) << TCC_EVCTRL_CNTSEL_Pos) /* (TCC_EVCTRL) Timer/counter Output Event Mode Mask */ 597 #define TCC_EVCTRL_CNTSEL(value) (TCC_EVCTRL_CNTSEL_Msk & (_UINT32_(value) << TCC_EVCTRL_CNTSEL_Pos)) /* Assignment of value for CNTSEL in the TCC_EVCTRL register */ 598 #define TCC_EVCTRL_CNTSEL_START_Val _UINT32_(0x0) /* (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts */ 599 #define TCC_EVCTRL_CNTSEL_END_Val _UINT32_(0x1) /* (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends */ 600 #define TCC_EVCTRL_CNTSEL_BETWEEN_Val _UINT32_(0x2) /* (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends, except for the first and last cycles */ 601 #define TCC_EVCTRL_CNTSEL_BOUNDARY_Val _UINT32_(0x3) /* (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts or a counter cycle ends */ 602 #define TCC_EVCTRL_CNTSEL_START (TCC_EVCTRL_CNTSEL_START_Val << TCC_EVCTRL_CNTSEL_Pos) /* (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts Position */ 603 #define TCC_EVCTRL_CNTSEL_END (TCC_EVCTRL_CNTSEL_END_Val << TCC_EVCTRL_CNTSEL_Pos) /* (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends Position */ 604 #define TCC_EVCTRL_CNTSEL_BETWEEN (TCC_EVCTRL_CNTSEL_BETWEEN_Val << TCC_EVCTRL_CNTSEL_Pos) /* (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends, except for the first and last cycles Position */ 605 #define TCC_EVCTRL_CNTSEL_BOUNDARY (TCC_EVCTRL_CNTSEL_BOUNDARY_Val << TCC_EVCTRL_CNTSEL_Pos) /* (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts or a counter cycle ends Position */ 606 #define TCC_EVCTRL_OVFEO_Pos _UINT32_(8) /* (TCC_EVCTRL) Overflow/Underflow Output Event Enable Position */ 607 #define TCC_EVCTRL_OVFEO_Msk (_UINT32_(0x1) << TCC_EVCTRL_OVFEO_Pos) /* (TCC_EVCTRL) Overflow/Underflow Output Event Enable Mask */ 608 #define TCC_EVCTRL_OVFEO(value) (TCC_EVCTRL_OVFEO_Msk & (_UINT32_(value) << TCC_EVCTRL_OVFEO_Pos)) /* Assignment of value for OVFEO in the TCC_EVCTRL register */ 609 #define TCC_EVCTRL_TRGEO_Pos _UINT32_(9) /* (TCC_EVCTRL) Retrigger Output Event Enable Position */ 610 #define TCC_EVCTRL_TRGEO_Msk (_UINT32_(0x1) << TCC_EVCTRL_TRGEO_Pos) /* (TCC_EVCTRL) Retrigger Output Event Enable Mask */ 611 #define TCC_EVCTRL_TRGEO(value) (TCC_EVCTRL_TRGEO_Msk & (_UINT32_(value) << TCC_EVCTRL_TRGEO_Pos)) /* Assignment of value for TRGEO in the TCC_EVCTRL register */ 612 #define TCC_EVCTRL_CNTEO_Pos _UINT32_(10) /* (TCC_EVCTRL) Timer/counter Output Event Enable Position */ 613 #define TCC_EVCTRL_CNTEO_Msk (_UINT32_(0x1) << TCC_EVCTRL_CNTEO_Pos) /* (TCC_EVCTRL) Timer/counter Output Event Enable Mask */ 614 #define TCC_EVCTRL_CNTEO(value) (TCC_EVCTRL_CNTEO_Msk & (_UINT32_(value) << TCC_EVCTRL_CNTEO_Pos)) /* Assignment of value for CNTEO in the TCC_EVCTRL register */ 615 #define TCC_EVCTRL_TCINV0_Pos _UINT32_(12) /* (TCC_EVCTRL) Inverted Event 0 Input Enable Position */ 616 #define TCC_EVCTRL_TCINV0_Msk (_UINT32_(0x1) << TCC_EVCTRL_TCINV0_Pos) /* (TCC_EVCTRL) Inverted Event 0 Input Enable Mask */ 617 #define TCC_EVCTRL_TCINV0(value) (TCC_EVCTRL_TCINV0_Msk & (_UINT32_(value) << TCC_EVCTRL_TCINV0_Pos)) /* Assignment of value for TCINV0 in the TCC_EVCTRL register */ 618 #define TCC_EVCTRL_TCINV1_Pos _UINT32_(13) /* (TCC_EVCTRL) Inverted Event 1 Input Enable Position */ 619 #define TCC_EVCTRL_TCINV1_Msk (_UINT32_(0x1) << TCC_EVCTRL_TCINV1_Pos) /* (TCC_EVCTRL) Inverted Event 1 Input Enable Mask */ 620 #define TCC_EVCTRL_TCINV1(value) (TCC_EVCTRL_TCINV1_Msk & (_UINT32_(value) << TCC_EVCTRL_TCINV1_Pos)) /* Assignment of value for TCINV1 in the TCC_EVCTRL register */ 621 #define TCC_EVCTRL_TCEI0_Pos _UINT32_(14) /* (TCC_EVCTRL) Timer/counter Event 0 Input Enable Position */ 622 #define TCC_EVCTRL_TCEI0_Msk (_UINT32_(0x1) << TCC_EVCTRL_TCEI0_Pos) /* (TCC_EVCTRL) Timer/counter Event 0 Input Enable Mask */ 623 #define TCC_EVCTRL_TCEI0(value) (TCC_EVCTRL_TCEI0_Msk & (_UINT32_(value) << TCC_EVCTRL_TCEI0_Pos)) /* Assignment of value for TCEI0 in the TCC_EVCTRL register */ 624 #define TCC_EVCTRL_TCEI1_Pos _UINT32_(15) /* (TCC_EVCTRL) Timer/counter Event 1 Input Enable Position */ 625 #define TCC_EVCTRL_TCEI1_Msk (_UINT32_(0x1) << TCC_EVCTRL_TCEI1_Pos) /* (TCC_EVCTRL) Timer/counter Event 1 Input Enable Mask */ 626 #define TCC_EVCTRL_TCEI1(value) (TCC_EVCTRL_TCEI1_Msk & (_UINT32_(value) << TCC_EVCTRL_TCEI1_Pos)) /* Assignment of value for TCEI1 in the TCC_EVCTRL register */ 627 #define TCC_EVCTRL_MCEI0_Pos _UINT32_(16) /* (TCC_EVCTRL) Match or Capture Channel 0 Event Input Enable Position */ 628 #define TCC_EVCTRL_MCEI0_Msk (_UINT32_(0x1) << TCC_EVCTRL_MCEI0_Pos) /* (TCC_EVCTRL) Match or Capture Channel 0 Event Input Enable Mask */ 629 #define TCC_EVCTRL_MCEI0(value) (TCC_EVCTRL_MCEI0_Msk & (_UINT32_(value) << TCC_EVCTRL_MCEI0_Pos)) /* Assignment of value for MCEI0 in the TCC_EVCTRL register */ 630 #define TCC_EVCTRL_MCEI1_Pos _UINT32_(17) /* (TCC_EVCTRL) Match or Capture Channel 1 Event Input Enable Position */ 631 #define TCC_EVCTRL_MCEI1_Msk (_UINT32_(0x1) << TCC_EVCTRL_MCEI1_Pos) /* (TCC_EVCTRL) Match or Capture Channel 1 Event Input Enable Mask */ 632 #define TCC_EVCTRL_MCEI1(value) (TCC_EVCTRL_MCEI1_Msk & (_UINT32_(value) << TCC_EVCTRL_MCEI1_Pos)) /* Assignment of value for MCEI1 in the TCC_EVCTRL register */ 633 #define TCC_EVCTRL_MCEI2_Pos _UINT32_(18) /* (TCC_EVCTRL) Match or Capture Channel 2 Event Input Enable Position */ 634 #define TCC_EVCTRL_MCEI2_Msk (_UINT32_(0x1) << TCC_EVCTRL_MCEI2_Pos) /* (TCC_EVCTRL) Match or Capture Channel 2 Event Input Enable Mask */ 635 #define TCC_EVCTRL_MCEI2(value) (TCC_EVCTRL_MCEI2_Msk & (_UINT32_(value) << TCC_EVCTRL_MCEI2_Pos)) /* Assignment of value for MCEI2 in the TCC_EVCTRL register */ 636 #define TCC_EVCTRL_MCEI3_Pos _UINT32_(19) /* (TCC_EVCTRL) Match or Capture Channel 3 Event Input Enable Position */ 637 #define TCC_EVCTRL_MCEI3_Msk (_UINT32_(0x1) << TCC_EVCTRL_MCEI3_Pos) /* (TCC_EVCTRL) Match or Capture Channel 3 Event Input Enable Mask */ 638 #define TCC_EVCTRL_MCEI3(value) (TCC_EVCTRL_MCEI3_Msk & (_UINT32_(value) << TCC_EVCTRL_MCEI3_Pos)) /* Assignment of value for MCEI3 in the TCC_EVCTRL register */ 639 #define TCC_EVCTRL_MCEI4_Pos _UINT32_(20) /* (TCC_EVCTRL) Match or Capture Channel 4 Event Input Enable Position */ 640 #define TCC_EVCTRL_MCEI4_Msk (_UINT32_(0x1) << TCC_EVCTRL_MCEI4_Pos) /* (TCC_EVCTRL) Match or Capture Channel 4 Event Input Enable Mask */ 641 #define TCC_EVCTRL_MCEI4(value) (TCC_EVCTRL_MCEI4_Msk & (_UINT32_(value) << TCC_EVCTRL_MCEI4_Pos)) /* Assignment of value for MCEI4 in the TCC_EVCTRL register */ 642 #define TCC_EVCTRL_MCEI5_Pos _UINT32_(21) /* (TCC_EVCTRL) Match or Capture Channel 5 Event Input Enable Position */ 643 #define TCC_EVCTRL_MCEI5_Msk (_UINT32_(0x1) << TCC_EVCTRL_MCEI5_Pos) /* (TCC_EVCTRL) Match or Capture Channel 5 Event Input Enable Mask */ 644 #define TCC_EVCTRL_MCEI5(value) (TCC_EVCTRL_MCEI5_Msk & (_UINT32_(value) << TCC_EVCTRL_MCEI5_Pos)) /* Assignment of value for MCEI5 in the TCC_EVCTRL register */ 645 #define TCC_EVCTRL_MCEO0_Pos _UINT32_(24) /* (TCC_EVCTRL) Match or Capture Channel 0 Event Output Enable Position */ 646 #define TCC_EVCTRL_MCEO0_Msk (_UINT32_(0x1) << TCC_EVCTRL_MCEO0_Pos) /* (TCC_EVCTRL) Match or Capture Channel 0 Event Output Enable Mask */ 647 #define TCC_EVCTRL_MCEO0(value) (TCC_EVCTRL_MCEO0_Msk & (_UINT32_(value) << TCC_EVCTRL_MCEO0_Pos)) /* Assignment of value for MCEO0 in the TCC_EVCTRL register */ 648 #define TCC_EVCTRL_MCEO1_Pos _UINT32_(25) /* (TCC_EVCTRL) Match or Capture Channel 1 Event Output Enable Position */ 649 #define TCC_EVCTRL_MCEO1_Msk (_UINT32_(0x1) << TCC_EVCTRL_MCEO1_Pos) /* (TCC_EVCTRL) Match or Capture Channel 1 Event Output Enable Mask */ 650 #define TCC_EVCTRL_MCEO1(value) (TCC_EVCTRL_MCEO1_Msk & (_UINT32_(value) << TCC_EVCTRL_MCEO1_Pos)) /* Assignment of value for MCEO1 in the TCC_EVCTRL register */ 651 #define TCC_EVCTRL_MCEO2_Pos _UINT32_(26) /* (TCC_EVCTRL) Match or Capture Channel 2 Event Output Enable Position */ 652 #define TCC_EVCTRL_MCEO2_Msk (_UINT32_(0x1) << TCC_EVCTRL_MCEO2_Pos) /* (TCC_EVCTRL) Match or Capture Channel 2 Event Output Enable Mask */ 653 #define TCC_EVCTRL_MCEO2(value) (TCC_EVCTRL_MCEO2_Msk & (_UINT32_(value) << TCC_EVCTRL_MCEO2_Pos)) /* Assignment of value for MCEO2 in the TCC_EVCTRL register */ 654 #define TCC_EVCTRL_MCEO3_Pos _UINT32_(27) /* (TCC_EVCTRL) Match or Capture Channel 3 Event Output Enable Position */ 655 #define TCC_EVCTRL_MCEO3_Msk (_UINT32_(0x1) << TCC_EVCTRL_MCEO3_Pos) /* (TCC_EVCTRL) Match or Capture Channel 3 Event Output Enable Mask */ 656 #define TCC_EVCTRL_MCEO3(value) (TCC_EVCTRL_MCEO3_Msk & (_UINT32_(value) << TCC_EVCTRL_MCEO3_Pos)) /* Assignment of value for MCEO3 in the TCC_EVCTRL register */ 657 #define TCC_EVCTRL_MCEO4_Pos _UINT32_(28) /* (TCC_EVCTRL) Match or Capture Channel 4 Event Output Enable Position */ 658 #define TCC_EVCTRL_MCEO4_Msk (_UINT32_(0x1) << TCC_EVCTRL_MCEO4_Pos) /* (TCC_EVCTRL) Match or Capture Channel 4 Event Output Enable Mask */ 659 #define TCC_EVCTRL_MCEO4(value) (TCC_EVCTRL_MCEO4_Msk & (_UINT32_(value) << TCC_EVCTRL_MCEO4_Pos)) /* Assignment of value for MCEO4 in the TCC_EVCTRL register */ 660 #define TCC_EVCTRL_MCEO5_Pos _UINT32_(29) /* (TCC_EVCTRL) Match or Capture Channel 5 Event Output Enable Position */ 661 #define TCC_EVCTRL_MCEO5_Msk (_UINT32_(0x1) << TCC_EVCTRL_MCEO5_Pos) /* (TCC_EVCTRL) Match or Capture Channel 5 Event Output Enable Mask */ 662 #define TCC_EVCTRL_MCEO5(value) (TCC_EVCTRL_MCEO5_Msk & (_UINT32_(value) << TCC_EVCTRL_MCEO5_Pos)) /* Assignment of value for MCEO5 in the TCC_EVCTRL register */ 663 #define TCC_EVCTRL_Msk _UINT32_(0x3F3FF7FF) /* (TCC_EVCTRL) Register Mask */ 664 665 #define TCC_EVCTRL_TCINV_Pos _UINT32_(12) /* (TCC_EVCTRL Position) Inverted Event x Input Enable */ 666 #define TCC_EVCTRL_TCINV_Msk (_UINT32_(0x3) << TCC_EVCTRL_TCINV_Pos) /* (TCC_EVCTRL Mask) TCINV */ 667 #define TCC_EVCTRL_TCINV(value) (TCC_EVCTRL_TCINV_Msk & (_UINT32_(value) << TCC_EVCTRL_TCINV_Pos)) 668 #define TCC_EVCTRL_TCEI_Pos _UINT32_(14) /* (TCC_EVCTRL Position) Timer/counter Event x Input Enable */ 669 #define TCC_EVCTRL_TCEI_Msk (_UINT32_(0x3) << TCC_EVCTRL_TCEI_Pos) /* (TCC_EVCTRL Mask) TCEI */ 670 #define TCC_EVCTRL_TCEI(value) (TCC_EVCTRL_TCEI_Msk & (_UINT32_(value) << TCC_EVCTRL_TCEI_Pos)) 671 #define TCC_EVCTRL_MCEI_Pos _UINT32_(16) /* (TCC_EVCTRL Position) Match or Capture Channel x Event Input Enable */ 672 #define TCC_EVCTRL_MCEI_Msk (_UINT32_(0x3F) << TCC_EVCTRL_MCEI_Pos) /* (TCC_EVCTRL Mask) MCEI */ 673 #define TCC_EVCTRL_MCEI(value) (TCC_EVCTRL_MCEI_Msk & (_UINT32_(value) << TCC_EVCTRL_MCEI_Pos)) 674 #define TCC_EVCTRL_MCEO_Pos _UINT32_(24) /* (TCC_EVCTRL Position) Match or Capture Channel 5 Event Output Enable */ 675 #define TCC_EVCTRL_MCEO_Msk (_UINT32_(0x3F) << TCC_EVCTRL_MCEO_Pos) /* (TCC_EVCTRL Mask) MCEO */ 676 #define TCC_EVCTRL_MCEO(value) (TCC_EVCTRL_MCEO_Msk & (_UINT32_(value) << TCC_EVCTRL_MCEO_Pos)) 677 678 /* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */ 679 #define TCC_INTENCLR_RESETVALUE _UINT32_(0x00) /* (TCC_INTENCLR) Interrupt Enable Clear Reset Value */ 680 681 #define TCC_INTENCLR_OVF_Pos _UINT32_(0) /* (TCC_INTENCLR) Overflow Interrupt Enable Position */ 682 #define TCC_INTENCLR_OVF_Msk (_UINT32_(0x1) << TCC_INTENCLR_OVF_Pos) /* (TCC_INTENCLR) Overflow Interrupt Enable Mask */ 683 #define TCC_INTENCLR_OVF(value) (TCC_INTENCLR_OVF_Msk & (_UINT32_(value) << TCC_INTENCLR_OVF_Pos)) /* Assignment of value for OVF in the TCC_INTENCLR register */ 684 #define TCC_INTENCLR_TRG_Pos _UINT32_(1) /* (TCC_INTENCLR) Retrigger Interrupt Enable Position */ 685 #define TCC_INTENCLR_TRG_Msk (_UINT32_(0x1) << TCC_INTENCLR_TRG_Pos) /* (TCC_INTENCLR) Retrigger Interrupt Enable Mask */ 686 #define TCC_INTENCLR_TRG(value) (TCC_INTENCLR_TRG_Msk & (_UINT32_(value) << TCC_INTENCLR_TRG_Pos)) /* Assignment of value for TRG in the TCC_INTENCLR register */ 687 #define TCC_INTENCLR_CNT_Pos _UINT32_(2) /* (TCC_INTENCLR) Counter Interrupt Enable Position */ 688 #define TCC_INTENCLR_CNT_Msk (_UINT32_(0x1) << TCC_INTENCLR_CNT_Pos) /* (TCC_INTENCLR) Counter Interrupt Enable Mask */ 689 #define TCC_INTENCLR_CNT(value) (TCC_INTENCLR_CNT_Msk & (_UINT32_(value) << TCC_INTENCLR_CNT_Pos)) /* Assignment of value for CNT in the TCC_INTENCLR register */ 690 #define TCC_INTENCLR_ERR_Pos _UINT32_(3) /* (TCC_INTENCLR) Error Interrupt Enable Position */ 691 #define TCC_INTENCLR_ERR_Msk (_UINT32_(0x1) << TCC_INTENCLR_ERR_Pos) /* (TCC_INTENCLR) Error Interrupt Enable Mask */ 692 #define TCC_INTENCLR_ERR(value) (TCC_INTENCLR_ERR_Msk & (_UINT32_(value) << TCC_INTENCLR_ERR_Pos)) /* Assignment of value for ERR in the TCC_INTENCLR register */ 693 #define TCC_INTENCLR_UFS_Pos _UINT32_(10) /* (TCC_INTENCLR) Non-Recoverable Update Fault Interrupt Enable Position */ 694 #define TCC_INTENCLR_UFS_Msk (_UINT32_(0x1) << TCC_INTENCLR_UFS_Pos) /* (TCC_INTENCLR) Non-Recoverable Update Fault Interrupt Enable Mask */ 695 #define TCC_INTENCLR_UFS(value) (TCC_INTENCLR_UFS_Msk & (_UINT32_(value) << TCC_INTENCLR_UFS_Pos)) /* Assignment of value for UFS in the TCC_INTENCLR register */ 696 #define TCC_INTENCLR_DFS_Pos _UINT32_(11) /* (TCC_INTENCLR) Non-Recoverable Debug Fault Interrupt Enable Position */ 697 #define TCC_INTENCLR_DFS_Msk (_UINT32_(0x1) << TCC_INTENCLR_DFS_Pos) /* (TCC_INTENCLR) Non-Recoverable Debug Fault Interrupt Enable Mask */ 698 #define TCC_INTENCLR_DFS(value) (TCC_INTENCLR_DFS_Msk & (_UINT32_(value) << TCC_INTENCLR_DFS_Pos)) /* Assignment of value for DFS in the TCC_INTENCLR register */ 699 #define TCC_INTENCLR_FAULTA_Pos _UINT32_(12) /* (TCC_INTENCLR) Recoverable Fault A Interrupt Enable Position */ 700 #define TCC_INTENCLR_FAULTA_Msk (_UINT32_(0x1) << TCC_INTENCLR_FAULTA_Pos) /* (TCC_INTENCLR) Recoverable Fault A Interrupt Enable Mask */ 701 #define TCC_INTENCLR_FAULTA(value) (TCC_INTENCLR_FAULTA_Msk & (_UINT32_(value) << TCC_INTENCLR_FAULTA_Pos)) /* Assignment of value for FAULTA in the TCC_INTENCLR register */ 702 #define TCC_INTENCLR_FAULTB_Pos _UINT32_(13) /* (TCC_INTENCLR) Recoverable Fault B Interrupt Enable Position */ 703 #define TCC_INTENCLR_FAULTB_Msk (_UINT32_(0x1) << TCC_INTENCLR_FAULTB_Pos) /* (TCC_INTENCLR) Recoverable Fault B Interrupt Enable Mask */ 704 #define TCC_INTENCLR_FAULTB(value) (TCC_INTENCLR_FAULTB_Msk & (_UINT32_(value) << TCC_INTENCLR_FAULTB_Pos)) /* Assignment of value for FAULTB in the TCC_INTENCLR register */ 705 #define TCC_INTENCLR_FAULT0_Pos _UINT32_(14) /* (TCC_INTENCLR) Non-Recoverable Fault 0 Interrupt Enable Position */ 706 #define TCC_INTENCLR_FAULT0_Msk (_UINT32_(0x1) << TCC_INTENCLR_FAULT0_Pos) /* (TCC_INTENCLR) Non-Recoverable Fault 0 Interrupt Enable Mask */ 707 #define TCC_INTENCLR_FAULT0(value) (TCC_INTENCLR_FAULT0_Msk & (_UINT32_(value) << TCC_INTENCLR_FAULT0_Pos)) /* Assignment of value for FAULT0 in the TCC_INTENCLR register */ 708 #define TCC_INTENCLR_FAULT1_Pos _UINT32_(15) /* (TCC_INTENCLR) Non-Recoverable Fault 1 Interrupt Enable Position */ 709 #define TCC_INTENCLR_FAULT1_Msk (_UINT32_(0x1) << TCC_INTENCLR_FAULT1_Pos) /* (TCC_INTENCLR) Non-Recoverable Fault 1 Interrupt Enable Mask */ 710 #define TCC_INTENCLR_FAULT1(value) (TCC_INTENCLR_FAULT1_Msk & (_UINT32_(value) << TCC_INTENCLR_FAULT1_Pos)) /* Assignment of value for FAULT1 in the TCC_INTENCLR register */ 711 #define TCC_INTENCLR_MC0_Pos _UINT32_(16) /* (TCC_INTENCLR) Match or Capture Channel 0 Interrupt Enable Position */ 712 #define TCC_INTENCLR_MC0_Msk (_UINT32_(0x1) << TCC_INTENCLR_MC0_Pos) /* (TCC_INTENCLR) Match or Capture Channel 0 Interrupt Enable Mask */ 713 #define TCC_INTENCLR_MC0(value) (TCC_INTENCLR_MC0_Msk & (_UINT32_(value) << TCC_INTENCLR_MC0_Pos)) /* Assignment of value for MC0 in the TCC_INTENCLR register */ 714 #define TCC_INTENCLR_MC1_Pos _UINT32_(17) /* (TCC_INTENCLR) Match or Capture Channel 1 Interrupt Enable Position */ 715 #define TCC_INTENCLR_MC1_Msk (_UINT32_(0x1) << TCC_INTENCLR_MC1_Pos) /* (TCC_INTENCLR) Match or Capture Channel 1 Interrupt Enable Mask */ 716 #define TCC_INTENCLR_MC1(value) (TCC_INTENCLR_MC1_Msk & (_UINT32_(value) << TCC_INTENCLR_MC1_Pos)) /* Assignment of value for MC1 in the TCC_INTENCLR register */ 717 #define TCC_INTENCLR_MC2_Pos _UINT32_(18) /* (TCC_INTENCLR) Match or Capture Channel 2 Interrupt Enable Position */ 718 #define TCC_INTENCLR_MC2_Msk (_UINT32_(0x1) << TCC_INTENCLR_MC2_Pos) /* (TCC_INTENCLR) Match or Capture Channel 2 Interrupt Enable Mask */ 719 #define TCC_INTENCLR_MC2(value) (TCC_INTENCLR_MC2_Msk & (_UINT32_(value) << TCC_INTENCLR_MC2_Pos)) /* Assignment of value for MC2 in the TCC_INTENCLR register */ 720 #define TCC_INTENCLR_MC3_Pos _UINT32_(19) /* (TCC_INTENCLR) Match or Capture Channel 3 Interrupt Enable Position */ 721 #define TCC_INTENCLR_MC3_Msk (_UINT32_(0x1) << TCC_INTENCLR_MC3_Pos) /* (TCC_INTENCLR) Match or Capture Channel 3 Interrupt Enable Mask */ 722 #define TCC_INTENCLR_MC3(value) (TCC_INTENCLR_MC3_Msk & (_UINT32_(value) << TCC_INTENCLR_MC3_Pos)) /* Assignment of value for MC3 in the TCC_INTENCLR register */ 723 #define TCC_INTENCLR_MC4_Pos _UINT32_(20) /* (TCC_INTENCLR) Match or Capture Channel 4 Interrupt Enable Position */ 724 #define TCC_INTENCLR_MC4_Msk (_UINT32_(0x1) << TCC_INTENCLR_MC4_Pos) /* (TCC_INTENCLR) Match or Capture Channel 4 Interrupt Enable Mask */ 725 #define TCC_INTENCLR_MC4(value) (TCC_INTENCLR_MC4_Msk & (_UINT32_(value) << TCC_INTENCLR_MC4_Pos)) /* Assignment of value for MC4 in the TCC_INTENCLR register */ 726 #define TCC_INTENCLR_MC5_Pos _UINT32_(21) /* (TCC_INTENCLR) Match or Capture Channel 5 Interrupt Enable Position */ 727 #define TCC_INTENCLR_MC5_Msk (_UINT32_(0x1) << TCC_INTENCLR_MC5_Pos) /* (TCC_INTENCLR) Match or Capture Channel 5 Interrupt Enable Mask */ 728 #define TCC_INTENCLR_MC5(value) (TCC_INTENCLR_MC5_Msk & (_UINT32_(value) << TCC_INTENCLR_MC5_Pos)) /* Assignment of value for MC5 in the TCC_INTENCLR register */ 729 #define TCC_INTENCLR_Msk _UINT32_(0x003FFC0F) /* (TCC_INTENCLR) Register Mask */ 730 731 #define TCC_INTENCLR_FAULT_Pos _UINT32_(14) /* (TCC_INTENCLR Position) Non-Recoverable Fault x Interrupt Enable */ 732 #define TCC_INTENCLR_FAULT_Msk (_UINT32_(0x3) << TCC_INTENCLR_FAULT_Pos) /* (TCC_INTENCLR Mask) FAULT */ 733 #define TCC_INTENCLR_FAULT(value) (TCC_INTENCLR_FAULT_Msk & (_UINT32_(value) << TCC_INTENCLR_FAULT_Pos)) 734 #define TCC_INTENCLR_MC_Pos _UINT32_(16) /* (TCC_INTENCLR Position) Match or Capture Channel 5 Interrupt Enable */ 735 #define TCC_INTENCLR_MC_Msk (_UINT32_(0x3F) << TCC_INTENCLR_MC_Pos) /* (TCC_INTENCLR Mask) MC */ 736 #define TCC_INTENCLR_MC(value) (TCC_INTENCLR_MC_Msk & (_UINT32_(value) << TCC_INTENCLR_MC_Pos)) 737 738 /* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */ 739 #define TCC_INTENSET_RESETVALUE _UINT32_(0x00) /* (TCC_INTENSET) Interrupt Enable Set Reset Value */ 740 741 #define TCC_INTENSET_OVF_Pos _UINT32_(0) /* (TCC_INTENSET) Overflow Interrupt Enable Position */ 742 #define TCC_INTENSET_OVF_Msk (_UINT32_(0x1) << TCC_INTENSET_OVF_Pos) /* (TCC_INTENSET) Overflow Interrupt Enable Mask */ 743 #define TCC_INTENSET_OVF(value) (TCC_INTENSET_OVF_Msk & (_UINT32_(value) << TCC_INTENSET_OVF_Pos)) /* Assignment of value for OVF in the TCC_INTENSET register */ 744 #define TCC_INTENSET_TRG_Pos _UINT32_(1) /* (TCC_INTENSET) Retrigger Interrupt Enable Position */ 745 #define TCC_INTENSET_TRG_Msk (_UINT32_(0x1) << TCC_INTENSET_TRG_Pos) /* (TCC_INTENSET) Retrigger Interrupt Enable Mask */ 746 #define TCC_INTENSET_TRG(value) (TCC_INTENSET_TRG_Msk & (_UINT32_(value) << TCC_INTENSET_TRG_Pos)) /* Assignment of value for TRG in the TCC_INTENSET register */ 747 #define TCC_INTENSET_CNT_Pos _UINT32_(2) /* (TCC_INTENSET) Counter Interrupt Enable Position */ 748 #define TCC_INTENSET_CNT_Msk (_UINT32_(0x1) << TCC_INTENSET_CNT_Pos) /* (TCC_INTENSET) Counter Interrupt Enable Mask */ 749 #define TCC_INTENSET_CNT(value) (TCC_INTENSET_CNT_Msk & (_UINT32_(value) << TCC_INTENSET_CNT_Pos)) /* Assignment of value for CNT in the TCC_INTENSET register */ 750 #define TCC_INTENSET_ERR_Pos _UINT32_(3) /* (TCC_INTENSET) Error Interrupt Enable Position */ 751 #define TCC_INTENSET_ERR_Msk (_UINT32_(0x1) << TCC_INTENSET_ERR_Pos) /* (TCC_INTENSET) Error Interrupt Enable Mask */ 752 #define TCC_INTENSET_ERR(value) (TCC_INTENSET_ERR_Msk & (_UINT32_(value) << TCC_INTENSET_ERR_Pos)) /* Assignment of value for ERR in the TCC_INTENSET register */ 753 #define TCC_INTENSET_UFS_Pos _UINT32_(10) /* (TCC_INTENSET) Non-Recoverable Update Fault Interrupt Enable Position */ 754 #define TCC_INTENSET_UFS_Msk (_UINT32_(0x1) << TCC_INTENSET_UFS_Pos) /* (TCC_INTENSET) Non-Recoverable Update Fault Interrupt Enable Mask */ 755 #define TCC_INTENSET_UFS(value) (TCC_INTENSET_UFS_Msk & (_UINT32_(value) << TCC_INTENSET_UFS_Pos)) /* Assignment of value for UFS in the TCC_INTENSET register */ 756 #define TCC_INTENSET_DFS_Pos _UINT32_(11) /* (TCC_INTENSET) Non-Recoverable Debug Fault Interrupt Enable Position */ 757 #define TCC_INTENSET_DFS_Msk (_UINT32_(0x1) << TCC_INTENSET_DFS_Pos) /* (TCC_INTENSET) Non-Recoverable Debug Fault Interrupt Enable Mask */ 758 #define TCC_INTENSET_DFS(value) (TCC_INTENSET_DFS_Msk & (_UINT32_(value) << TCC_INTENSET_DFS_Pos)) /* Assignment of value for DFS in the TCC_INTENSET register */ 759 #define TCC_INTENSET_FAULTA_Pos _UINT32_(12) /* (TCC_INTENSET) Recoverable Fault A Interrupt Enable Position */ 760 #define TCC_INTENSET_FAULTA_Msk (_UINT32_(0x1) << TCC_INTENSET_FAULTA_Pos) /* (TCC_INTENSET) Recoverable Fault A Interrupt Enable Mask */ 761 #define TCC_INTENSET_FAULTA(value) (TCC_INTENSET_FAULTA_Msk & (_UINT32_(value) << TCC_INTENSET_FAULTA_Pos)) /* Assignment of value for FAULTA in the TCC_INTENSET register */ 762 #define TCC_INTENSET_FAULTB_Pos _UINT32_(13) /* (TCC_INTENSET) Recoverable Fault B Interrupt Enable Position */ 763 #define TCC_INTENSET_FAULTB_Msk (_UINT32_(0x1) << TCC_INTENSET_FAULTB_Pos) /* (TCC_INTENSET) Recoverable Fault B Interrupt Enable Mask */ 764 #define TCC_INTENSET_FAULTB(value) (TCC_INTENSET_FAULTB_Msk & (_UINT32_(value) << TCC_INTENSET_FAULTB_Pos)) /* Assignment of value for FAULTB in the TCC_INTENSET register */ 765 #define TCC_INTENSET_FAULT0_Pos _UINT32_(14) /* (TCC_INTENSET) Non-Recoverable Fault 0 Interrupt Enable Position */ 766 #define TCC_INTENSET_FAULT0_Msk (_UINT32_(0x1) << TCC_INTENSET_FAULT0_Pos) /* (TCC_INTENSET) Non-Recoverable Fault 0 Interrupt Enable Mask */ 767 #define TCC_INTENSET_FAULT0(value) (TCC_INTENSET_FAULT0_Msk & (_UINT32_(value) << TCC_INTENSET_FAULT0_Pos)) /* Assignment of value for FAULT0 in the TCC_INTENSET register */ 768 #define TCC_INTENSET_FAULT1_Pos _UINT32_(15) /* (TCC_INTENSET) Non-Recoverable Fault 1 Interrupt Enable Position */ 769 #define TCC_INTENSET_FAULT1_Msk (_UINT32_(0x1) << TCC_INTENSET_FAULT1_Pos) /* (TCC_INTENSET) Non-Recoverable Fault 1 Interrupt Enable Mask */ 770 #define TCC_INTENSET_FAULT1(value) (TCC_INTENSET_FAULT1_Msk & (_UINT32_(value) << TCC_INTENSET_FAULT1_Pos)) /* Assignment of value for FAULT1 in the TCC_INTENSET register */ 771 #define TCC_INTENSET_MC0_Pos _UINT32_(16) /* (TCC_INTENSET) Match or Capture Channel 0 Interrupt Enable Position */ 772 #define TCC_INTENSET_MC0_Msk (_UINT32_(0x1) << TCC_INTENSET_MC0_Pos) /* (TCC_INTENSET) Match or Capture Channel 0 Interrupt Enable Mask */ 773 #define TCC_INTENSET_MC0(value) (TCC_INTENSET_MC0_Msk & (_UINT32_(value) << TCC_INTENSET_MC0_Pos)) /* Assignment of value for MC0 in the TCC_INTENSET register */ 774 #define TCC_INTENSET_MC1_Pos _UINT32_(17) /* (TCC_INTENSET) Match or Capture Channel 1 Interrupt Enable Position */ 775 #define TCC_INTENSET_MC1_Msk (_UINT32_(0x1) << TCC_INTENSET_MC1_Pos) /* (TCC_INTENSET) Match or Capture Channel 1 Interrupt Enable Mask */ 776 #define TCC_INTENSET_MC1(value) (TCC_INTENSET_MC1_Msk & (_UINT32_(value) << TCC_INTENSET_MC1_Pos)) /* Assignment of value for MC1 in the TCC_INTENSET register */ 777 #define TCC_INTENSET_MC2_Pos _UINT32_(18) /* (TCC_INTENSET) Match or Capture Channel 2 Interrupt Enable Position */ 778 #define TCC_INTENSET_MC2_Msk (_UINT32_(0x1) << TCC_INTENSET_MC2_Pos) /* (TCC_INTENSET) Match or Capture Channel 2 Interrupt Enable Mask */ 779 #define TCC_INTENSET_MC2(value) (TCC_INTENSET_MC2_Msk & (_UINT32_(value) << TCC_INTENSET_MC2_Pos)) /* Assignment of value for MC2 in the TCC_INTENSET register */ 780 #define TCC_INTENSET_MC3_Pos _UINT32_(19) /* (TCC_INTENSET) Match or Capture Channel 3 Interrupt Enable Position */ 781 #define TCC_INTENSET_MC3_Msk (_UINT32_(0x1) << TCC_INTENSET_MC3_Pos) /* (TCC_INTENSET) Match or Capture Channel 3 Interrupt Enable Mask */ 782 #define TCC_INTENSET_MC3(value) (TCC_INTENSET_MC3_Msk & (_UINT32_(value) << TCC_INTENSET_MC3_Pos)) /* Assignment of value for MC3 in the TCC_INTENSET register */ 783 #define TCC_INTENSET_MC4_Pos _UINT32_(20) /* (TCC_INTENSET) Match or Capture Channel 4 Interrupt Enable Position */ 784 #define TCC_INTENSET_MC4_Msk (_UINT32_(0x1) << TCC_INTENSET_MC4_Pos) /* (TCC_INTENSET) Match or Capture Channel 4 Interrupt Enable Mask */ 785 #define TCC_INTENSET_MC4(value) (TCC_INTENSET_MC4_Msk & (_UINT32_(value) << TCC_INTENSET_MC4_Pos)) /* Assignment of value for MC4 in the TCC_INTENSET register */ 786 #define TCC_INTENSET_MC5_Pos _UINT32_(21) /* (TCC_INTENSET) Match or Capture Channel 5 Interrupt Enable Position */ 787 #define TCC_INTENSET_MC5_Msk (_UINT32_(0x1) << TCC_INTENSET_MC5_Pos) /* (TCC_INTENSET) Match or Capture Channel 5 Interrupt Enable Mask */ 788 #define TCC_INTENSET_MC5(value) (TCC_INTENSET_MC5_Msk & (_UINT32_(value) << TCC_INTENSET_MC5_Pos)) /* Assignment of value for MC5 in the TCC_INTENSET register */ 789 #define TCC_INTENSET_Msk _UINT32_(0x003FFC0F) /* (TCC_INTENSET) Register Mask */ 790 791 #define TCC_INTENSET_FAULT_Pos _UINT32_(14) /* (TCC_INTENSET Position) Non-Recoverable Fault x Interrupt Enable */ 792 #define TCC_INTENSET_FAULT_Msk (_UINT32_(0x3) << TCC_INTENSET_FAULT_Pos) /* (TCC_INTENSET Mask) FAULT */ 793 #define TCC_INTENSET_FAULT(value) (TCC_INTENSET_FAULT_Msk & (_UINT32_(value) << TCC_INTENSET_FAULT_Pos)) 794 #define TCC_INTENSET_MC_Pos _UINT32_(16) /* (TCC_INTENSET Position) Match or Capture Channel 5 Interrupt Enable */ 795 #define TCC_INTENSET_MC_Msk (_UINT32_(0x3F) << TCC_INTENSET_MC_Pos) /* (TCC_INTENSET Mask) MC */ 796 #define TCC_INTENSET_MC(value) (TCC_INTENSET_MC_Msk & (_UINT32_(value) << TCC_INTENSET_MC_Pos)) 797 798 /* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */ 799 #define TCC_INTFLAG_RESETVALUE _UINT32_(0x00) /* (TCC_INTFLAG) Interrupt Flag Status and Clear Reset Value */ 800 801 #define TCC_INTFLAG_OVF_Pos _UINT32_(0) /* (TCC_INTFLAG) Overflow Position */ 802 #define TCC_INTFLAG_OVF_Msk (_UINT32_(0x1) << TCC_INTFLAG_OVF_Pos) /* (TCC_INTFLAG) Overflow Mask */ 803 #define TCC_INTFLAG_OVF(value) (TCC_INTFLAG_OVF_Msk & (_UINT32_(value) << TCC_INTFLAG_OVF_Pos)) /* Assignment of value for OVF in the TCC_INTFLAG register */ 804 #define TCC_INTFLAG_TRG_Pos _UINT32_(1) /* (TCC_INTFLAG) Retrigger Position */ 805 #define TCC_INTFLAG_TRG_Msk (_UINT32_(0x1) << TCC_INTFLAG_TRG_Pos) /* (TCC_INTFLAG) Retrigger Mask */ 806 #define TCC_INTFLAG_TRG(value) (TCC_INTFLAG_TRG_Msk & (_UINT32_(value) << TCC_INTFLAG_TRG_Pos)) /* Assignment of value for TRG in the TCC_INTFLAG register */ 807 #define TCC_INTFLAG_CNT_Pos _UINT32_(2) /* (TCC_INTFLAG) Counter Position */ 808 #define TCC_INTFLAG_CNT_Msk (_UINT32_(0x1) << TCC_INTFLAG_CNT_Pos) /* (TCC_INTFLAG) Counter Mask */ 809 #define TCC_INTFLAG_CNT(value) (TCC_INTFLAG_CNT_Msk & (_UINT32_(value) << TCC_INTFLAG_CNT_Pos)) /* Assignment of value for CNT in the TCC_INTFLAG register */ 810 #define TCC_INTFLAG_ERR_Pos _UINT32_(3) /* (TCC_INTFLAG) Error Position */ 811 #define TCC_INTFLAG_ERR_Msk (_UINT32_(0x1) << TCC_INTFLAG_ERR_Pos) /* (TCC_INTFLAG) Error Mask */ 812 #define TCC_INTFLAG_ERR(value) (TCC_INTFLAG_ERR_Msk & (_UINT32_(value) << TCC_INTFLAG_ERR_Pos)) /* Assignment of value for ERR in the TCC_INTFLAG register */ 813 #define TCC_INTFLAG_UFS_Pos _UINT32_(10) /* (TCC_INTFLAG) Non-Recoverable Update Fault Position */ 814 #define TCC_INTFLAG_UFS_Msk (_UINT32_(0x1) << TCC_INTFLAG_UFS_Pos) /* (TCC_INTFLAG) Non-Recoverable Update Fault Mask */ 815 #define TCC_INTFLAG_UFS(value) (TCC_INTFLAG_UFS_Msk & (_UINT32_(value) << TCC_INTFLAG_UFS_Pos)) /* Assignment of value for UFS in the TCC_INTFLAG register */ 816 #define TCC_INTFLAG_DFS_Pos _UINT32_(11) /* (TCC_INTFLAG) Non-Recoverable Debug Fault Position */ 817 #define TCC_INTFLAG_DFS_Msk (_UINT32_(0x1) << TCC_INTFLAG_DFS_Pos) /* (TCC_INTFLAG) Non-Recoverable Debug Fault Mask */ 818 #define TCC_INTFLAG_DFS(value) (TCC_INTFLAG_DFS_Msk & (_UINT32_(value) << TCC_INTFLAG_DFS_Pos)) /* Assignment of value for DFS in the TCC_INTFLAG register */ 819 #define TCC_INTFLAG_FAULTA_Pos _UINT32_(12) /* (TCC_INTFLAG) Recoverable Fault A Position */ 820 #define TCC_INTFLAG_FAULTA_Msk (_UINT32_(0x1) << TCC_INTFLAG_FAULTA_Pos) /* (TCC_INTFLAG) Recoverable Fault A Mask */ 821 #define TCC_INTFLAG_FAULTA(value) (TCC_INTFLAG_FAULTA_Msk & (_UINT32_(value) << TCC_INTFLAG_FAULTA_Pos)) /* Assignment of value for FAULTA in the TCC_INTFLAG register */ 822 #define TCC_INTFLAG_FAULTB_Pos _UINT32_(13) /* (TCC_INTFLAG) Recoverable Fault B Position */ 823 #define TCC_INTFLAG_FAULTB_Msk (_UINT32_(0x1) << TCC_INTFLAG_FAULTB_Pos) /* (TCC_INTFLAG) Recoverable Fault B Mask */ 824 #define TCC_INTFLAG_FAULTB(value) (TCC_INTFLAG_FAULTB_Msk & (_UINT32_(value) << TCC_INTFLAG_FAULTB_Pos)) /* Assignment of value for FAULTB in the TCC_INTFLAG register */ 825 #define TCC_INTFLAG_FAULT0_Pos _UINT32_(14) /* (TCC_INTFLAG) Non-Recoverable Fault 0 Position */ 826 #define TCC_INTFLAG_FAULT0_Msk (_UINT32_(0x1) << TCC_INTFLAG_FAULT0_Pos) /* (TCC_INTFLAG) Non-Recoverable Fault 0 Mask */ 827 #define TCC_INTFLAG_FAULT0(value) (TCC_INTFLAG_FAULT0_Msk & (_UINT32_(value) << TCC_INTFLAG_FAULT0_Pos)) /* Assignment of value for FAULT0 in the TCC_INTFLAG register */ 828 #define TCC_INTFLAG_FAULT1_Pos _UINT32_(15) /* (TCC_INTFLAG) Non-Recoverable Fault 1 Position */ 829 #define TCC_INTFLAG_FAULT1_Msk (_UINT32_(0x1) << TCC_INTFLAG_FAULT1_Pos) /* (TCC_INTFLAG) Non-Recoverable Fault 1 Mask */ 830 #define TCC_INTFLAG_FAULT1(value) (TCC_INTFLAG_FAULT1_Msk & (_UINT32_(value) << TCC_INTFLAG_FAULT1_Pos)) /* Assignment of value for FAULT1 in the TCC_INTFLAG register */ 831 #define TCC_INTFLAG_MC0_Pos _UINT32_(16) /* (TCC_INTFLAG) Match or Capture 0 Position */ 832 #define TCC_INTFLAG_MC0_Msk (_UINT32_(0x1) << TCC_INTFLAG_MC0_Pos) /* (TCC_INTFLAG) Match or Capture 0 Mask */ 833 #define TCC_INTFLAG_MC0(value) (TCC_INTFLAG_MC0_Msk & (_UINT32_(value) << TCC_INTFLAG_MC0_Pos)) /* Assignment of value for MC0 in the TCC_INTFLAG register */ 834 #define TCC_INTFLAG_MC1_Pos _UINT32_(17) /* (TCC_INTFLAG) Match or Capture 1 Position */ 835 #define TCC_INTFLAG_MC1_Msk (_UINT32_(0x1) << TCC_INTFLAG_MC1_Pos) /* (TCC_INTFLAG) Match or Capture 1 Mask */ 836 #define TCC_INTFLAG_MC1(value) (TCC_INTFLAG_MC1_Msk & (_UINT32_(value) << TCC_INTFLAG_MC1_Pos)) /* Assignment of value for MC1 in the TCC_INTFLAG register */ 837 #define TCC_INTFLAG_MC2_Pos _UINT32_(18) /* (TCC_INTFLAG) Match or Capture 2 Position */ 838 #define TCC_INTFLAG_MC2_Msk (_UINT32_(0x1) << TCC_INTFLAG_MC2_Pos) /* (TCC_INTFLAG) Match or Capture 2 Mask */ 839 #define TCC_INTFLAG_MC2(value) (TCC_INTFLAG_MC2_Msk & (_UINT32_(value) << TCC_INTFLAG_MC2_Pos)) /* Assignment of value for MC2 in the TCC_INTFLAG register */ 840 #define TCC_INTFLAG_MC3_Pos _UINT32_(19) /* (TCC_INTFLAG) Match or Capture 3 Position */ 841 #define TCC_INTFLAG_MC3_Msk (_UINT32_(0x1) << TCC_INTFLAG_MC3_Pos) /* (TCC_INTFLAG) Match or Capture 3 Mask */ 842 #define TCC_INTFLAG_MC3(value) (TCC_INTFLAG_MC3_Msk & (_UINT32_(value) << TCC_INTFLAG_MC3_Pos)) /* Assignment of value for MC3 in the TCC_INTFLAG register */ 843 #define TCC_INTFLAG_MC4_Pos _UINT32_(20) /* (TCC_INTFLAG) Match or Capture 4 Position */ 844 #define TCC_INTFLAG_MC4_Msk (_UINT32_(0x1) << TCC_INTFLAG_MC4_Pos) /* (TCC_INTFLAG) Match or Capture 4 Mask */ 845 #define TCC_INTFLAG_MC4(value) (TCC_INTFLAG_MC4_Msk & (_UINT32_(value) << TCC_INTFLAG_MC4_Pos)) /* Assignment of value for MC4 in the TCC_INTFLAG register */ 846 #define TCC_INTFLAG_MC5_Pos _UINT32_(21) /* (TCC_INTFLAG) Match or Capture 5 Position */ 847 #define TCC_INTFLAG_MC5_Msk (_UINT32_(0x1) << TCC_INTFLAG_MC5_Pos) /* (TCC_INTFLAG) Match or Capture 5 Mask */ 848 #define TCC_INTFLAG_MC5(value) (TCC_INTFLAG_MC5_Msk & (_UINT32_(value) << TCC_INTFLAG_MC5_Pos)) /* Assignment of value for MC5 in the TCC_INTFLAG register */ 849 #define TCC_INTFLAG_Msk _UINT32_(0x003FFC0F) /* (TCC_INTFLAG) Register Mask */ 850 851 #define TCC_INTFLAG_FAULT_Pos _UINT32_(14) /* (TCC_INTFLAG Position) Non-Recoverable Fault x */ 852 #define TCC_INTFLAG_FAULT_Msk (_UINT32_(0x3) << TCC_INTFLAG_FAULT_Pos) /* (TCC_INTFLAG Mask) FAULT */ 853 #define TCC_INTFLAG_FAULT(value) (TCC_INTFLAG_FAULT_Msk & (_UINT32_(value) << TCC_INTFLAG_FAULT_Pos)) 854 #define TCC_INTFLAG_MC_Pos _UINT32_(16) /* (TCC_INTFLAG Position) Match or Capture 5 */ 855 #define TCC_INTFLAG_MC_Msk (_UINT32_(0x3F) << TCC_INTFLAG_MC_Pos) /* (TCC_INTFLAG Mask) MC */ 856 #define TCC_INTFLAG_MC(value) (TCC_INTFLAG_MC_Msk & (_UINT32_(value) << TCC_INTFLAG_MC_Pos)) 857 858 /* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */ 859 #define TCC_STATUS_RESETVALUE _UINT32_(0x01) /* (TCC_STATUS) Status Reset Value */ 860 861 #define TCC_STATUS_STOP_Pos _UINT32_(0) /* (TCC_STATUS) Stop Position */ 862 #define TCC_STATUS_STOP_Msk (_UINT32_(0x1) << TCC_STATUS_STOP_Pos) /* (TCC_STATUS) Stop Mask */ 863 #define TCC_STATUS_STOP(value) (TCC_STATUS_STOP_Msk & (_UINT32_(value) << TCC_STATUS_STOP_Pos)) /* Assignment of value for STOP in the TCC_STATUS register */ 864 #define TCC_STATUS_IDX_Pos _UINT32_(1) /* (TCC_STATUS) Ramp Position */ 865 #define TCC_STATUS_IDX_Msk (_UINT32_(0x1) << TCC_STATUS_IDX_Pos) /* (TCC_STATUS) Ramp Mask */ 866 #define TCC_STATUS_IDX(value) (TCC_STATUS_IDX_Msk & (_UINT32_(value) << TCC_STATUS_IDX_Pos)) /* Assignment of value for IDX in the TCC_STATUS register */ 867 #define TCC_STATUS_UFS_Pos _UINT32_(2) /* (TCC_STATUS) Non-recoverable Update Fault State Position */ 868 #define TCC_STATUS_UFS_Msk (_UINT32_(0x1) << TCC_STATUS_UFS_Pos) /* (TCC_STATUS) Non-recoverable Update Fault State Mask */ 869 #define TCC_STATUS_UFS(value) (TCC_STATUS_UFS_Msk & (_UINT32_(value) << TCC_STATUS_UFS_Pos)) /* Assignment of value for UFS in the TCC_STATUS register */ 870 #define TCC_STATUS_DFS_Pos _UINT32_(3) /* (TCC_STATUS) Non-Recoverable Debug Fault State Position */ 871 #define TCC_STATUS_DFS_Msk (_UINT32_(0x1) << TCC_STATUS_DFS_Pos) /* (TCC_STATUS) Non-Recoverable Debug Fault State Mask */ 872 #define TCC_STATUS_DFS(value) (TCC_STATUS_DFS_Msk & (_UINT32_(value) << TCC_STATUS_DFS_Pos)) /* Assignment of value for DFS in the TCC_STATUS register */ 873 #define TCC_STATUS_SLAVE_Pos _UINT32_(4) /* (TCC_STATUS) Slave Position */ 874 #define TCC_STATUS_SLAVE_Msk (_UINT32_(0x1) << TCC_STATUS_SLAVE_Pos) /* (TCC_STATUS) Slave Mask */ 875 #define TCC_STATUS_SLAVE(value) (TCC_STATUS_SLAVE_Msk & (_UINT32_(value) << TCC_STATUS_SLAVE_Pos)) /* Assignment of value for SLAVE in the TCC_STATUS register */ 876 #define TCC_STATUS_PATTBUFV_Pos _UINT32_(5) /* (TCC_STATUS) Pattern Buffer Valid Position */ 877 #define TCC_STATUS_PATTBUFV_Msk (_UINT32_(0x1) << TCC_STATUS_PATTBUFV_Pos) /* (TCC_STATUS) Pattern Buffer Valid Mask */ 878 #define TCC_STATUS_PATTBUFV(value) (TCC_STATUS_PATTBUFV_Msk & (_UINT32_(value) << TCC_STATUS_PATTBUFV_Pos)) /* Assignment of value for PATTBUFV in the TCC_STATUS register */ 879 #define TCC_STATUS_PERBUFV_Pos _UINT32_(7) /* (TCC_STATUS) Period Buffer Valid Position */ 880 #define TCC_STATUS_PERBUFV_Msk (_UINT32_(0x1) << TCC_STATUS_PERBUFV_Pos) /* (TCC_STATUS) Period Buffer Valid Mask */ 881 #define TCC_STATUS_PERBUFV(value) (TCC_STATUS_PERBUFV_Msk & (_UINT32_(value) << TCC_STATUS_PERBUFV_Pos)) /* Assignment of value for PERBUFV in the TCC_STATUS register */ 882 #define TCC_STATUS_FAULTAIN_Pos _UINT32_(8) /* (TCC_STATUS) Recoverable Fault A Input Position */ 883 #define TCC_STATUS_FAULTAIN_Msk (_UINT32_(0x1) << TCC_STATUS_FAULTAIN_Pos) /* (TCC_STATUS) Recoverable Fault A Input Mask */ 884 #define TCC_STATUS_FAULTAIN(value) (TCC_STATUS_FAULTAIN_Msk & (_UINT32_(value) << TCC_STATUS_FAULTAIN_Pos)) /* Assignment of value for FAULTAIN in the TCC_STATUS register */ 885 #define TCC_STATUS_FAULTBIN_Pos _UINT32_(9) /* (TCC_STATUS) Recoverable Fault B Input Position */ 886 #define TCC_STATUS_FAULTBIN_Msk (_UINT32_(0x1) << TCC_STATUS_FAULTBIN_Pos) /* (TCC_STATUS) Recoverable Fault B Input Mask */ 887 #define TCC_STATUS_FAULTBIN(value) (TCC_STATUS_FAULTBIN_Msk & (_UINT32_(value) << TCC_STATUS_FAULTBIN_Pos)) /* Assignment of value for FAULTBIN in the TCC_STATUS register */ 888 #define TCC_STATUS_FAULT0IN_Pos _UINT32_(10) /* (TCC_STATUS) Non-Recoverable Fault0 Input Position */ 889 #define TCC_STATUS_FAULT0IN_Msk (_UINT32_(0x1) << TCC_STATUS_FAULT0IN_Pos) /* (TCC_STATUS) Non-Recoverable Fault0 Input Mask */ 890 #define TCC_STATUS_FAULT0IN(value) (TCC_STATUS_FAULT0IN_Msk & (_UINT32_(value) << TCC_STATUS_FAULT0IN_Pos)) /* Assignment of value for FAULT0IN in the TCC_STATUS register */ 891 #define TCC_STATUS_FAULT1IN_Pos _UINT32_(11) /* (TCC_STATUS) Non-Recoverable Fault1 Input Position */ 892 #define TCC_STATUS_FAULT1IN_Msk (_UINT32_(0x1) << TCC_STATUS_FAULT1IN_Pos) /* (TCC_STATUS) Non-Recoverable Fault1 Input Mask */ 893 #define TCC_STATUS_FAULT1IN(value) (TCC_STATUS_FAULT1IN_Msk & (_UINT32_(value) << TCC_STATUS_FAULT1IN_Pos)) /* Assignment of value for FAULT1IN in the TCC_STATUS register */ 894 #define TCC_STATUS_FAULTA_Pos _UINT32_(12) /* (TCC_STATUS) Recoverable Fault A State Position */ 895 #define TCC_STATUS_FAULTA_Msk (_UINT32_(0x1) << TCC_STATUS_FAULTA_Pos) /* (TCC_STATUS) Recoverable Fault A State Mask */ 896 #define TCC_STATUS_FAULTA(value) (TCC_STATUS_FAULTA_Msk & (_UINT32_(value) << TCC_STATUS_FAULTA_Pos)) /* Assignment of value for FAULTA in the TCC_STATUS register */ 897 #define TCC_STATUS_FAULTB_Pos _UINT32_(13) /* (TCC_STATUS) Recoverable Fault B State Position */ 898 #define TCC_STATUS_FAULTB_Msk (_UINT32_(0x1) << TCC_STATUS_FAULTB_Pos) /* (TCC_STATUS) Recoverable Fault B State Mask */ 899 #define TCC_STATUS_FAULTB(value) (TCC_STATUS_FAULTB_Msk & (_UINT32_(value) << TCC_STATUS_FAULTB_Pos)) /* Assignment of value for FAULTB in the TCC_STATUS register */ 900 #define TCC_STATUS_FAULT0_Pos _UINT32_(14) /* (TCC_STATUS) Non-Recoverable Fault 0 State Position */ 901 #define TCC_STATUS_FAULT0_Msk (_UINT32_(0x1) << TCC_STATUS_FAULT0_Pos) /* (TCC_STATUS) Non-Recoverable Fault 0 State Mask */ 902 #define TCC_STATUS_FAULT0(value) (TCC_STATUS_FAULT0_Msk & (_UINT32_(value) << TCC_STATUS_FAULT0_Pos)) /* Assignment of value for FAULT0 in the TCC_STATUS register */ 903 #define TCC_STATUS_FAULT1_Pos _UINT32_(15) /* (TCC_STATUS) Non-Recoverable Fault 1 State Position */ 904 #define TCC_STATUS_FAULT1_Msk (_UINT32_(0x1) << TCC_STATUS_FAULT1_Pos) /* (TCC_STATUS) Non-Recoverable Fault 1 State Mask */ 905 #define TCC_STATUS_FAULT1(value) (TCC_STATUS_FAULT1_Msk & (_UINT32_(value) << TCC_STATUS_FAULT1_Pos)) /* Assignment of value for FAULT1 in the TCC_STATUS register */ 906 #define TCC_STATUS_CCBUFV0_Pos _UINT32_(16) /* (TCC_STATUS) Compare Channel 0 Buffer Valid Position */ 907 #define TCC_STATUS_CCBUFV0_Msk (_UINT32_(0x1) << TCC_STATUS_CCBUFV0_Pos) /* (TCC_STATUS) Compare Channel 0 Buffer Valid Mask */ 908 #define TCC_STATUS_CCBUFV0(value) (TCC_STATUS_CCBUFV0_Msk & (_UINT32_(value) << TCC_STATUS_CCBUFV0_Pos)) /* Assignment of value for CCBUFV0 in the TCC_STATUS register */ 909 #define TCC_STATUS_CCBUFV1_Pos _UINT32_(17) /* (TCC_STATUS) Compare Channel 1 Buffer Valid Position */ 910 #define TCC_STATUS_CCBUFV1_Msk (_UINT32_(0x1) << TCC_STATUS_CCBUFV1_Pos) /* (TCC_STATUS) Compare Channel 1 Buffer Valid Mask */ 911 #define TCC_STATUS_CCBUFV1(value) (TCC_STATUS_CCBUFV1_Msk & (_UINT32_(value) << TCC_STATUS_CCBUFV1_Pos)) /* Assignment of value for CCBUFV1 in the TCC_STATUS register */ 912 #define TCC_STATUS_CCBUFV2_Pos _UINT32_(18) /* (TCC_STATUS) Compare Channel 2 Buffer Valid Position */ 913 #define TCC_STATUS_CCBUFV2_Msk (_UINT32_(0x1) << TCC_STATUS_CCBUFV2_Pos) /* (TCC_STATUS) Compare Channel 2 Buffer Valid Mask */ 914 #define TCC_STATUS_CCBUFV2(value) (TCC_STATUS_CCBUFV2_Msk & (_UINT32_(value) << TCC_STATUS_CCBUFV2_Pos)) /* Assignment of value for CCBUFV2 in the TCC_STATUS register */ 915 #define TCC_STATUS_CCBUFV3_Pos _UINT32_(19) /* (TCC_STATUS) Compare Channel 3 Buffer Valid Position */ 916 #define TCC_STATUS_CCBUFV3_Msk (_UINT32_(0x1) << TCC_STATUS_CCBUFV3_Pos) /* (TCC_STATUS) Compare Channel 3 Buffer Valid Mask */ 917 #define TCC_STATUS_CCBUFV3(value) (TCC_STATUS_CCBUFV3_Msk & (_UINT32_(value) << TCC_STATUS_CCBUFV3_Pos)) /* Assignment of value for CCBUFV3 in the TCC_STATUS register */ 918 #define TCC_STATUS_CCBUFV4_Pos _UINT32_(20) /* (TCC_STATUS) Compare Channel 4 Buffer Valid Position */ 919 #define TCC_STATUS_CCBUFV4_Msk (_UINT32_(0x1) << TCC_STATUS_CCBUFV4_Pos) /* (TCC_STATUS) Compare Channel 4 Buffer Valid Mask */ 920 #define TCC_STATUS_CCBUFV4(value) (TCC_STATUS_CCBUFV4_Msk & (_UINT32_(value) << TCC_STATUS_CCBUFV4_Pos)) /* Assignment of value for CCBUFV4 in the TCC_STATUS register */ 921 #define TCC_STATUS_CCBUFV5_Pos _UINT32_(21) /* (TCC_STATUS) Compare Channel 5 Buffer Valid Position */ 922 #define TCC_STATUS_CCBUFV5_Msk (_UINT32_(0x1) << TCC_STATUS_CCBUFV5_Pos) /* (TCC_STATUS) Compare Channel 5 Buffer Valid Mask */ 923 #define TCC_STATUS_CCBUFV5(value) (TCC_STATUS_CCBUFV5_Msk & (_UINT32_(value) << TCC_STATUS_CCBUFV5_Pos)) /* Assignment of value for CCBUFV5 in the TCC_STATUS register */ 924 #define TCC_STATUS_CMP0_Pos _UINT32_(24) /* (TCC_STATUS) Compare Channel 0 Value Position */ 925 #define TCC_STATUS_CMP0_Msk (_UINT32_(0x1) << TCC_STATUS_CMP0_Pos) /* (TCC_STATUS) Compare Channel 0 Value Mask */ 926 #define TCC_STATUS_CMP0(value) (TCC_STATUS_CMP0_Msk & (_UINT32_(value) << TCC_STATUS_CMP0_Pos)) /* Assignment of value for CMP0 in the TCC_STATUS register */ 927 #define TCC_STATUS_CMP1_Pos _UINT32_(25) /* (TCC_STATUS) Compare Channel 1 Value Position */ 928 #define TCC_STATUS_CMP1_Msk (_UINT32_(0x1) << TCC_STATUS_CMP1_Pos) /* (TCC_STATUS) Compare Channel 1 Value Mask */ 929 #define TCC_STATUS_CMP1(value) (TCC_STATUS_CMP1_Msk & (_UINT32_(value) << TCC_STATUS_CMP1_Pos)) /* Assignment of value for CMP1 in the TCC_STATUS register */ 930 #define TCC_STATUS_CMP2_Pos _UINT32_(26) /* (TCC_STATUS) Compare Channel 2 Value Position */ 931 #define TCC_STATUS_CMP2_Msk (_UINT32_(0x1) << TCC_STATUS_CMP2_Pos) /* (TCC_STATUS) Compare Channel 2 Value Mask */ 932 #define TCC_STATUS_CMP2(value) (TCC_STATUS_CMP2_Msk & (_UINT32_(value) << TCC_STATUS_CMP2_Pos)) /* Assignment of value for CMP2 in the TCC_STATUS register */ 933 #define TCC_STATUS_CMP3_Pos _UINT32_(27) /* (TCC_STATUS) Compare Channel 3 Value Position */ 934 #define TCC_STATUS_CMP3_Msk (_UINT32_(0x1) << TCC_STATUS_CMP3_Pos) /* (TCC_STATUS) Compare Channel 3 Value Mask */ 935 #define TCC_STATUS_CMP3(value) (TCC_STATUS_CMP3_Msk & (_UINT32_(value) << TCC_STATUS_CMP3_Pos)) /* Assignment of value for CMP3 in the TCC_STATUS register */ 936 #define TCC_STATUS_CMP4_Pos _UINT32_(28) /* (TCC_STATUS) Compare Channel 4 Value Position */ 937 #define TCC_STATUS_CMP4_Msk (_UINT32_(0x1) << TCC_STATUS_CMP4_Pos) /* (TCC_STATUS) Compare Channel 4 Value Mask */ 938 #define TCC_STATUS_CMP4(value) (TCC_STATUS_CMP4_Msk & (_UINT32_(value) << TCC_STATUS_CMP4_Pos)) /* Assignment of value for CMP4 in the TCC_STATUS register */ 939 #define TCC_STATUS_CMP5_Pos _UINT32_(29) /* (TCC_STATUS) Compare Channel 5 Value Position */ 940 #define TCC_STATUS_CMP5_Msk (_UINT32_(0x1) << TCC_STATUS_CMP5_Pos) /* (TCC_STATUS) Compare Channel 5 Value Mask */ 941 #define TCC_STATUS_CMP5(value) (TCC_STATUS_CMP5_Msk & (_UINT32_(value) << TCC_STATUS_CMP5_Pos)) /* Assignment of value for CMP5 in the TCC_STATUS register */ 942 #define TCC_STATUS_Msk _UINT32_(0x3F3FFFBF) /* (TCC_STATUS) Register Mask */ 943 944 #define TCC_STATUS_FAULT_Pos _UINT32_(14) /* (TCC_STATUS Position) Non-Recoverable Fault x State */ 945 #define TCC_STATUS_FAULT_Msk (_UINT32_(0x3) << TCC_STATUS_FAULT_Pos) /* (TCC_STATUS Mask) FAULT */ 946 #define TCC_STATUS_FAULT(value) (TCC_STATUS_FAULT_Msk & (_UINT32_(value) << TCC_STATUS_FAULT_Pos)) 947 #define TCC_STATUS_CCBUFV_Pos _UINT32_(16) /* (TCC_STATUS Position) Compare Channel x Buffer Valid */ 948 #define TCC_STATUS_CCBUFV_Msk (_UINT32_(0x3F) << TCC_STATUS_CCBUFV_Pos) /* (TCC_STATUS Mask) CCBUFV */ 949 #define TCC_STATUS_CCBUFV(value) (TCC_STATUS_CCBUFV_Msk & (_UINT32_(value) << TCC_STATUS_CCBUFV_Pos)) 950 #define TCC_STATUS_CMP_Pos _UINT32_(24) /* (TCC_STATUS Position) Compare Channel 5 Value */ 951 #define TCC_STATUS_CMP_Msk (_UINT32_(0x3F) << TCC_STATUS_CMP_Pos) /* (TCC_STATUS Mask) CMP */ 952 #define TCC_STATUS_CMP(value) (TCC_STATUS_CMP_Msk & (_UINT32_(value) << TCC_STATUS_CMP_Pos)) 953 954 /* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */ 955 #define TCC_COUNT_RESETVALUE _UINT32_(0x00) /* (TCC_COUNT) Count Reset Value */ 956 957 #define TCC_COUNT_COUNT_Pos _UINT32_(0) /* (TCC_COUNT) Counter Value Position */ 958 #define TCC_COUNT_COUNT_Msk (_UINT32_(0xFFFFFF) << TCC_COUNT_COUNT_Pos) /* (TCC_COUNT) Counter Value Mask */ 959 #define TCC_COUNT_COUNT(value) (TCC_COUNT_COUNT_Msk & (_UINT32_(value) << TCC_COUNT_COUNT_Pos)) /* Assignment of value for COUNT in the TCC_COUNT register */ 960 #define TCC_COUNT_Msk _UINT32_(0x00FFFFFF) /* (TCC_COUNT) Register Mask */ 961 962 /* DITH4 mode */ 963 #define TCC_COUNT_DITH4_COUNT_Pos _UINT32_(4) /* (TCC_COUNT) Counter Value Position */ 964 #define TCC_COUNT_DITH4_COUNT_Msk (_UINT32_(0xFFFFF) << TCC_COUNT_DITH4_COUNT_Pos) /* (TCC_COUNT) Counter Value Mask */ 965 #define TCC_COUNT_DITH4_COUNT(value) (TCC_COUNT_DITH4_COUNT_Msk & (_UINT32_(value) << TCC_COUNT_DITH4_COUNT_Pos)) 966 #define TCC_COUNT_DITH4_Msk _UINT32_(0x00FFFFF0) /* (TCC_COUNT_DITH4) Register Mask */ 967 968 /* DITH5 mode */ 969 #define TCC_COUNT_DITH5_COUNT_Pos _UINT32_(5) /* (TCC_COUNT) Counter Value Position */ 970 #define TCC_COUNT_DITH5_COUNT_Msk (_UINT32_(0x7FFFF) << TCC_COUNT_DITH5_COUNT_Pos) /* (TCC_COUNT) Counter Value Mask */ 971 #define TCC_COUNT_DITH5_COUNT(value) (TCC_COUNT_DITH5_COUNT_Msk & (_UINT32_(value) << TCC_COUNT_DITH5_COUNT_Pos)) 972 #define TCC_COUNT_DITH5_Msk _UINT32_(0x00FFFFE0) /* (TCC_COUNT_DITH5) Register Mask */ 973 974 /* DITH6 mode */ 975 #define TCC_COUNT_DITH6_COUNT_Pos _UINT32_(6) /* (TCC_COUNT) Counter Value Position */ 976 #define TCC_COUNT_DITH6_COUNT_Msk (_UINT32_(0x3FFFF) << TCC_COUNT_DITH6_COUNT_Pos) /* (TCC_COUNT) Counter Value Mask */ 977 #define TCC_COUNT_DITH6_COUNT(value) (TCC_COUNT_DITH6_COUNT_Msk & (_UINT32_(value) << TCC_COUNT_DITH6_COUNT_Pos)) 978 #define TCC_COUNT_DITH6_Msk _UINT32_(0x00FFFFC0) /* (TCC_COUNT_DITH6) Register Mask */ 979 980 981 /* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */ 982 #define TCC_PATT_RESETVALUE _UINT16_(0x00) /* (TCC_PATT) Pattern Reset Value */ 983 984 #define TCC_PATT_PGE0_Pos _UINT16_(0) /* (TCC_PATT) Pattern Generator 0 Output Enable Position */ 985 #define TCC_PATT_PGE0_Msk (_UINT16_(0x1) << TCC_PATT_PGE0_Pos) /* (TCC_PATT) Pattern Generator 0 Output Enable Mask */ 986 #define TCC_PATT_PGE0(value) (TCC_PATT_PGE0_Msk & (_UINT16_(value) << TCC_PATT_PGE0_Pos)) /* Assignment of value for PGE0 in the TCC_PATT register */ 987 #define TCC_PATT_PGE1_Pos _UINT16_(1) /* (TCC_PATT) Pattern Generator 1 Output Enable Position */ 988 #define TCC_PATT_PGE1_Msk (_UINT16_(0x1) << TCC_PATT_PGE1_Pos) /* (TCC_PATT) Pattern Generator 1 Output Enable Mask */ 989 #define TCC_PATT_PGE1(value) (TCC_PATT_PGE1_Msk & (_UINT16_(value) << TCC_PATT_PGE1_Pos)) /* Assignment of value for PGE1 in the TCC_PATT register */ 990 #define TCC_PATT_PGE2_Pos _UINT16_(2) /* (TCC_PATT) Pattern Generator 2 Output Enable Position */ 991 #define TCC_PATT_PGE2_Msk (_UINT16_(0x1) << TCC_PATT_PGE2_Pos) /* (TCC_PATT) Pattern Generator 2 Output Enable Mask */ 992 #define TCC_PATT_PGE2(value) (TCC_PATT_PGE2_Msk & (_UINT16_(value) << TCC_PATT_PGE2_Pos)) /* Assignment of value for PGE2 in the TCC_PATT register */ 993 #define TCC_PATT_PGE3_Pos _UINT16_(3) /* (TCC_PATT) Pattern Generator 3 Output Enable Position */ 994 #define TCC_PATT_PGE3_Msk (_UINT16_(0x1) << TCC_PATT_PGE3_Pos) /* (TCC_PATT) Pattern Generator 3 Output Enable Mask */ 995 #define TCC_PATT_PGE3(value) (TCC_PATT_PGE3_Msk & (_UINT16_(value) << TCC_PATT_PGE3_Pos)) /* Assignment of value for PGE3 in the TCC_PATT register */ 996 #define TCC_PATT_PGE4_Pos _UINT16_(4) /* (TCC_PATT) Pattern Generator 4 Output Enable Position */ 997 #define TCC_PATT_PGE4_Msk (_UINT16_(0x1) << TCC_PATT_PGE4_Pos) /* (TCC_PATT) Pattern Generator 4 Output Enable Mask */ 998 #define TCC_PATT_PGE4(value) (TCC_PATT_PGE4_Msk & (_UINT16_(value) << TCC_PATT_PGE4_Pos)) /* Assignment of value for PGE4 in the TCC_PATT register */ 999 #define TCC_PATT_PGE5_Pos _UINT16_(5) /* (TCC_PATT) Pattern Generator 5 Output Enable Position */ 1000 #define TCC_PATT_PGE5_Msk (_UINT16_(0x1) << TCC_PATT_PGE5_Pos) /* (TCC_PATT) Pattern Generator 5 Output Enable Mask */ 1001 #define TCC_PATT_PGE5(value) (TCC_PATT_PGE5_Msk & (_UINT16_(value) << TCC_PATT_PGE5_Pos)) /* Assignment of value for PGE5 in the TCC_PATT register */ 1002 #define TCC_PATT_PGE6_Pos _UINT16_(6) /* (TCC_PATT) Pattern Generator 6 Output Enable Position */ 1003 #define TCC_PATT_PGE6_Msk (_UINT16_(0x1) << TCC_PATT_PGE6_Pos) /* (TCC_PATT) Pattern Generator 6 Output Enable Mask */ 1004 #define TCC_PATT_PGE6(value) (TCC_PATT_PGE6_Msk & (_UINT16_(value) << TCC_PATT_PGE6_Pos)) /* Assignment of value for PGE6 in the TCC_PATT register */ 1005 #define TCC_PATT_PGE7_Pos _UINT16_(7) /* (TCC_PATT) Pattern Generator 7 Output Enable Position */ 1006 #define TCC_PATT_PGE7_Msk (_UINT16_(0x1) << TCC_PATT_PGE7_Pos) /* (TCC_PATT) Pattern Generator 7 Output Enable Mask */ 1007 #define TCC_PATT_PGE7(value) (TCC_PATT_PGE7_Msk & (_UINT16_(value) << TCC_PATT_PGE7_Pos)) /* Assignment of value for PGE7 in the TCC_PATT register */ 1008 #define TCC_PATT_PGV0_Pos _UINT16_(8) /* (TCC_PATT) Pattern Generator 0 Output Value Position */ 1009 #define TCC_PATT_PGV0_Msk (_UINT16_(0x1) << TCC_PATT_PGV0_Pos) /* (TCC_PATT) Pattern Generator 0 Output Value Mask */ 1010 #define TCC_PATT_PGV0(value) (TCC_PATT_PGV0_Msk & (_UINT16_(value) << TCC_PATT_PGV0_Pos)) /* Assignment of value for PGV0 in the TCC_PATT register */ 1011 #define TCC_PATT_PGV1_Pos _UINT16_(9) /* (TCC_PATT) Pattern Generator 1 Output Value Position */ 1012 #define TCC_PATT_PGV1_Msk (_UINT16_(0x1) << TCC_PATT_PGV1_Pos) /* (TCC_PATT) Pattern Generator 1 Output Value Mask */ 1013 #define TCC_PATT_PGV1(value) (TCC_PATT_PGV1_Msk & (_UINT16_(value) << TCC_PATT_PGV1_Pos)) /* Assignment of value for PGV1 in the TCC_PATT register */ 1014 #define TCC_PATT_PGV2_Pos _UINT16_(10) /* (TCC_PATT) Pattern Generator 2 Output Value Position */ 1015 #define TCC_PATT_PGV2_Msk (_UINT16_(0x1) << TCC_PATT_PGV2_Pos) /* (TCC_PATT) Pattern Generator 2 Output Value Mask */ 1016 #define TCC_PATT_PGV2(value) (TCC_PATT_PGV2_Msk & (_UINT16_(value) << TCC_PATT_PGV2_Pos)) /* Assignment of value for PGV2 in the TCC_PATT register */ 1017 #define TCC_PATT_PGV3_Pos _UINT16_(11) /* (TCC_PATT) Pattern Generator 3 Output Value Position */ 1018 #define TCC_PATT_PGV3_Msk (_UINT16_(0x1) << TCC_PATT_PGV3_Pos) /* (TCC_PATT) Pattern Generator 3 Output Value Mask */ 1019 #define TCC_PATT_PGV3(value) (TCC_PATT_PGV3_Msk & (_UINT16_(value) << TCC_PATT_PGV3_Pos)) /* Assignment of value for PGV3 in the TCC_PATT register */ 1020 #define TCC_PATT_PGV4_Pos _UINT16_(12) /* (TCC_PATT) Pattern Generator 4 Output Value Position */ 1021 #define TCC_PATT_PGV4_Msk (_UINT16_(0x1) << TCC_PATT_PGV4_Pos) /* (TCC_PATT) Pattern Generator 4 Output Value Mask */ 1022 #define TCC_PATT_PGV4(value) (TCC_PATT_PGV4_Msk & (_UINT16_(value) << TCC_PATT_PGV4_Pos)) /* Assignment of value for PGV4 in the TCC_PATT register */ 1023 #define TCC_PATT_PGV5_Pos _UINT16_(13) /* (TCC_PATT) Pattern Generator 5 Output Value Position */ 1024 #define TCC_PATT_PGV5_Msk (_UINT16_(0x1) << TCC_PATT_PGV5_Pos) /* (TCC_PATT) Pattern Generator 5 Output Value Mask */ 1025 #define TCC_PATT_PGV5(value) (TCC_PATT_PGV5_Msk & (_UINT16_(value) << TCC_PATT_PGV5_Pos)) /* Assignment of value for PGV5 in the TCC_PATT register */ 1026 #define TCC_PATT_PGV6_Pos _UINT16_(14) /* (TCC_PATT) Pattern Generator 6 Output Value Position */ 1027 #define TCC_PATT_PGV6_Msk (_UINT16_(0x1) << TCC_PATT_PGV6_Pos) /* (TCC_PATT) Pattern Generator 6 Output Value Mask */ 1028 #define TCC_PATT_PGV6(value) (TCC_PATT_PGV6_Msk & (_UINT16_(value) << TCC_PATT_PGV6_Pos)) /* Assignment of value for PGV6 in the TCC_PATT register */ 1029 #define TCC_PATT_PGV7_Pos _UINT16_(15) /* (TCC_PATT) Pattern Generator 7 Output Value Position */ 1030 #define TCC_PATT_PGV7_Msk (_UINT16_(0x1) << TCC_PATT_PGV7_Pos) /* (TCC_PATT) Pattern Generator 7 Output Value Mask */ 1031 #define TCC_PATT_PGV7(value) (TCC_PATT_PGV7_Msk & (_UINT16_(value) << TCC_PATT_PGV7_Pos)) /* Assignment of value for PGV7 in the TCC_PATT register */ 1032 #define TCC_PATT_Msk _UINT16_(0xFFFF) /* (TCC_PATT) Register Mask */ 1033 1034 #define TCC_PATT_PGE_Pos _UINT16_(0) /* (TCC_PATT Position) Pattern Generator x Output Enable */ 1035 #define TCC_PATT_PGE_Msk (_UINT16_(0xFF) << TCC_PATT_PGE_Pos) /* (TCC_PATT Mask) PGE */ 1036 #define TCC_PATT_PGE(value) (TCC_PATT_PGE_Msk & (_UINT16_(value) << TCC_PATT_PGE_Pos)) 1037 #define TCC_PATT_PGV_Pos _UINT16_(8) /* (TCC_PATT Position) Pattern Generator 7 Output Value */ 1038 #define TCC_PATT_PGV_Msk (_UINT16_(0xFF) << TCC_PATT_PGV_Pos) /* (TCC_PATT Mask) PGV */ 1039 #define TCC_PATT_PGV(value) (TCC_PATT_PGV_Msk & (_UINT16_(value) << TCC_PATT_PGV_Pos)) 1040 1041 /* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */ 1042 #define TCC_WAVE_RESETVALUE _UINT32_(0x00) /* (TCC_WAVE) Waveform Control Reset Value */ 1043 1044 #define TCC_WAVE_WAVEGEN_Pos _UINT32_(0) /* (TCC_WAVE) Waveform Generation Position */ 1045 #define TCC_WAVE_WAVEGEN_Msk (_UINT32_(0x7) << TCC_WAVE_WAVEGEN_Pos) /* (TCC_WAVE) Waveform Generation Mask */ 1046 #define TCC_WAVE_WAVEGEN(value) (TCC_WAVE_WAVEGEN_Msk & (_UINT32_(value) << TCC_WAVE_WAVEGEN_Pos)) /* Assignment of value for WAVEGEN in the TCC_WAVE register */ 1047 #define TCC_WAVE_WAVEGEN_NFRQ_Val _UINT32_(0x0) /* (TCC_WAVE) Normal frequency */ 1048 #define TCC_WAVE_WAVEGEN_MFRQ_Val _UINT32_(0x1) /* (TCC_WAVE) Match frequency */ 1049 #define TCC_WAVE_WAVEGEN_NPWM_Val _UINT32_(0x2) /* (TCC_WAVE) Normal PWM */ 1050 #define TCC_WAVE_WAVEGEN_DSCRITICAL_Val _UINT32_(0x4) /* (TCC_WAVE) Dual-slope critical */ 1051 #define TCC_WAVE_WAVEGEN_DSBOTTOM_Val _UINT32_(0x5) /* (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO */ 1052 #define TCC_WAVE_WAVEGEN_DSBOTH_Val _UINT32_(0x6) /* (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */ 1053 #define TCC_WAVE_WAVEGEN_DSTOP_Val _UINT32_(0x7) /* (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches TOP */ 1054 #define TCC_WAVE_WAVEGEN_NFRQ (TCC_WAVE_WAVEGEN_NFRQ_Val << TCC_WAVE_WAVEGEN_Pos) /* (TCC_WAVE) Normal frequency Position */ 1055 #define TCC_WAVE_WAVEGEN_MFRQ (TCC_WAVE_WAVEGEN_MFRQ_Val << TCC_WAVE_WAVEGEN_Pos) /* (TCC_WAVE) Match frequency Position */ 1056 #define TCC_WAVE_WAVEGEN_NPWM (TCC_WAVE_WAVEGEN_NPWM_Val << TCC_WAVE_WAVEGEN_Pos) /* (TCC_WAVE) Normal PWM Position */ 1057 #define TCC_WAVE_WAVEGEN_DSCRITICAL (TCC_WAVE_WAVEGEN_DSCRITICAL_Val << TCC_WAVE_WAVEGEN_Pos) /* (TCC_WAVE) Dual-slope critical Position */ 1058 #define TCC_WAVE_WAVEGEN_DSBOTTOM (TCC_WAVE_WAVEGEN_DSBOTTOM_Val << TCC_WAVE_WAVEGEN_Pos) /* (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO Position */ 1059 #define TCC_WAVE_WAVEGEN_DSBOTH (TCC_WAVE_WAVEGEN_DSBOTH_Val << TCC_WAVE_WAVEGEN_Pos) /* (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP Position */ 1060 #define TCC_WAVE_WAVEGEN_DSTOP (TCC_WAVE_WAVEGEN_DSTOP_Val << TCC_WAVE_WAVEGEN_Pos) /* (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches TOP Position */ 1061 #define TCC_WAVE_RAMP_Pos _UINT32_(4) /* (TCC_WAVE) Ramp Mode Position */ 1062 #define TCC_WAVE_RAMP_Msk (_UINT32_(0x3) << TCC_WAVE_RAMP_Pos) /* (TCC_WAVE) Ramp Mode Mask */ 1063 #define TCC_WAVE_RAMP(value) (TCC_WAVE_RAMP_Msk & (_UINT32_(value) << TCC_WAVE_RAMP_Pos)) /* Assignment of value for RAMP in the TCC_WAVE register */ 1064 #define TCC_WAVE_RAMP_RAMP1_Val _UINT32_(0x0) /* (TCC_WAVE) RAMP1 operation */ 1065 #define TCC_WAVE_RAMP_RAMP2A_Val _UINT32_(0x1) /* (TCC_WAVE) Alternative RAMP2 operation */ 1066 #define TCC_WAVE_RAMP_RAMP2_Val _UINT32_(0x2) /* (TCC_WAVE) RAMP2 operation */ 1067 #define TCC_WAVE_RAMP_RAMP2C_Val _UINT32_(0x3) /* (TCC_WAVE) Critical RAMP2 operation */ 1068 #define TCC_WAVE_RAMP_RAMP1 (TCC_WAVE_RAMP_RAMP1_Val << TCC_WAVE_RAMP_Pos) /* (TCC_WAVE) RAMP1 operation Position */ 1069 #define TCC_WAVE_RAMP_RAMP2A (TCC_WAVE_RAMP_RAMP2A_Val << TCC_WAVE_RAMP_Pos) /* (TCC_WAVE) Alternative RAMP2 operation Position */ 1070 #define TCC_WAVE_RAMP_RAMP2 (TCC_WAVE_RAMP_RAMP2_Val << TCC_WAVE_RAMP_Pos) /* (TCC_WAVE) RAMP2 operation Position */ 1071 #define TCC_WAVE_RAMP_RAMP2C (TCC_WAVE_RAMP_RAMP2C_Val << TCC_WAVE_RAMP_Pos) /* (TCC_WAVE) Critical RAMP2 operation Position */ 1072 #define TCC_WAVE_CIPEREN_Pos _UINT32_(7) /* (TCC_WAVE) Circular period Enable Position */ 1073 #define TCC_WAVE_CIPEREN_Msk (_UINT32_(0x1) << TCC_WAVE_CIPEREN_Pos) /* (TCC_WAVE) Circular period Enable Mask */ 1074 #define TCC_WAVE_CIPEREN(value) (TCC_WAVE_CIPEREN_Msk & (_UINT32_(value) << TCC_WAVE_CIPEREN_Pos)) /* Assignment of value for CIPEREN in the TCC_WAVE register */ 1075 #define TCC_WAVE_CICCEN0_Pos _UINT32_(8) /* (TCC_WAVE) Circular Channel 0 Enable Position */ 1076 #define TCC_WAVE_CICCEN0_Msk (_UINT32_(0x1) << TCC_WAVE_CICCEN0_Pos) /* (TCC_WAVE) Circular Channel 0 Enable Mask */ 1077 #define TCC_WAVE_CICCEN0(value) (TCC_WAVE_CICCEN0_Msk & (_UINT32_(value) << TCC_WAVE_CICCEN0_Pos)) /* Assignment of value for CICCEN0 in the TCC_WAVE register */ 1078 #define TCC_WAVE_CICCEN1_Pos _UINT32_(9) /* (TCC_WAVE) Circular Channel 1 Enable Position */ 1079 #define TCC_WAVE_CICCEN1_Msk (_UINT32_(0x1) << TCC_WAVE_CICCEN1_Pos) /* (TCC_WAVE) Circular Channel 1 Enable Mask */ 1080 #define TCC_WAVE_CICCEN1(value) (TCC_WAVE_CICCEN1_Msk & (_UINT32_(value) << TCC_WAVE_CICCEN1_Pos)) /* Assignment of value for CICCEN1 in the TCC_WAVE register */ 1081 #define TCC_WAVE_CICCEN2_Pos _UINT32_(10) /* (TCC_WAVE) Circular Channel 2 Enable Position */ 1082 #define TCC_WAVE_CICCEN2_Msk (_UINT32_(0x1) << TCC_WAVE_CICCEN2_Pos) /* (TCC_WAVE) Circular Channel 2 Enable Mask */ 1083 #define TCC_WAVE_CICCEN2(value) (TCC_WAVE_CICCEN2_Msk & (_UINT32_(value) << TCC_WAVE_CICCEN2_Pos)) /* Assignment of value for CICCEN2 in the TCC_WAVE register */ 1084 #define TCC_WAVE_CICCEN3_Pos _UINT32_(11) /* (TCC_WAVE) Circular Channel 3 Enable Position */ 1085 #define TCC_WAVE_CICCEN3_Msk (_UINT32_(0x1) << TCC_WAVE_CICCEN3_Pos) /* (TCC_WAVE) Circular Channel 3 Enable Mask */ 1086 #define TCC_WAVE_CICCEN3(value) (TCC_WAVE_CICCEN3_Msk & (_UINT32_(value) << TCC_WAVE_CICCEN3_Pos)) /* Assignment of value for CICCEN3 in the TCC_WAVE register */ 1087 #define TCC_WAVE_POL0_Pos _UINT32_(16) /* (TCC_WAVE) Channel 0 Polarity Position */ 1088 #define TCC_WAVE_POL0_Msk (_UINT32_(0x1) << TCC_WAVE_POL0_Pos) /* (TCC_WAVE) Channel 0 Polarity Mask */ 1089 #define TCC_WAVE_POL0(value) (TCC_WAVE_POL0_Msk & (_UINT32_(value) << TCC_WAVE_POL0_Pos)) /* Assignment of value for POL0 in the TCC_WAVE register */ 1090 #define TCC_WAVE_POL1_Pos _UINT32_(17) /* (TCC_WAVE) Channel 1 Polarity Position */ 1091 #define TCC_WAVE_POL1_Msk (_UINT32_(0x1) << TCC_WAVE_POL1_Pos) /* (TCC_WAVE) Channel 1 Polarity Mask */ 1092 #define TCC_WAVE_POL1(value) (TCC_WAVE_POL1_Msk & (_UINT32_(value) << TCC_WAVE_POL1_Pos)) /* Assignment of value for POL1 in the TCC_WAVE register */ 1093 #define TCC_WAVE_POL2_Pos _UINT32_(18) /* (TCC_WAVE) Channel 2 Polarity Position */ 1094 #define TCC_WAVE_POL2_Msk (_UINT32_(0x1) << TCC_WAVE_POL2_Pos) /* (TCC_WAVE) Channel 2 Polarity Mask */ 1095 #define TCC_WAVE_POL2(value) (TCC_WAVE_POL2_Msk & (_UINT32_(value) << TCC_WAVE_POL2_Pos)) /* Assignment of value for POL2 in the TCC_WAVE register */ 1096 #define TCC_WAVE_POL3_Pos _UINT32_(19) /* (TCC_WAVE) Channel 3 Polarity Position */ 1097 #define TCC_WAVE_POL3_Msk (_UINT32_(0x1) << TCC_WAVE_POL3_Pos) /* (TCC_WAVE) Channel 3 Polarity Mask */ 1098 #define TCC_WAVE_POL3(value) (TCC_WAVE_POL3_Msk & (_UINT32_(value) << TCC_WAVE_POL3_Pos)) /* Assignment of value for POL3 in the TCC_WAVE register */ 1099 #define TCC_WAVE_POL4_Pos _UINT32_(20) /* (TCC_WAVE) Channel 4 Polarity Position */ 1100 #define TCC_WAVE_POL4_Msk (_UINT32_(0x1) << TCC_WAVE_POL4_Pos) /* (TCC_WAVE) Channel 4 Polarity Mask */ 1101 #define TCC_WAVE_POL4(value) (TCC_WAVE_POL4_Msk & (_UINT32_(value) << TCC_WAVE_POL4_Pos)) /* Assignment of value for POL4 in the TCC_WAVE register */ 1102 #define TCC_WAVE_POL5_Pos _UINT32_(21) /* (TCC_WAVE) Channel 5 Polarity Position */ 1103 #define TCC_WAVE_POL5_Msk (_UINT32_(0x1) << TCC_WAVE_POL5_Pos) /* (TCC_WAVE) Channel 5 Polarity Mask */ 1104 #define TCC_WAVE_POL5(value) (TCC_WAVE_POL5_Msk & (_UINT32_(value) << TCC_WAVE_POL5_Pos)) /* Assignment of value for POL5 in the TCC_WAVE register */ 1105 #define TCC_WAVE_SWAP0_Pos _UINT32_(24) /* (TCC_WAVE) Swap DTI Output Pair 0 Position */ 1106 #define TCC_WAVE_SWAP0_Msk (_UINT32_(0x1) << TCC_WAVE_SWAP0_Pos) /* (TCC_WAVE) Swap DTI Output Pair 0 Mask */ 1107 #define TCC_WAVE_SWAP0(value) (TCC_WAVE_SWAP0_Msk & (_UINT32_(value) << TCC_WAVE_SWAP0_Pos)) /* Assignment of value for SWAP0 in the TCC_WAVE register */ 1108 #define TCC_WAVE_SWAP1_Pos _UINT32_(25) /* (TCC_WAVE) Swap DTI Output Pair 1 Position */ 1109 #define TCC_WAVE_SWAP1_Msk (_UINT32_(0x1) << TCC_WAVE_SWAP1_Pos) /* (TCC_WAVE) Swap DTI Output Pair 1 Mask */ 1110 #define TCC_WAVE_SWAP1(value) (TCC_WAVE_SWAP1_Msk & (_UINT32_(value) << TCC_WAVE_SWAP1_Pos)) /* Assignment of value for SWAP1 in the TCC_WAVE register */ 1111 #define TCC_WAVE_SWAP2_Pos _UINT32_(26) /* (TCC_WAVE) Swap DTI Output Pair 2 Position */ 1112 #define TCC_WAVE_SWAP2_Msk (_UINT32_(0x1) << TCC_WAVE_SWAP2_Pos) /* (TCC_WAVE) Swap DTI Output Pair 2 Mask */ 1113 #define TCC_WAVE_SWAP2(value) (TCC_WAVE_SWAP2_Msk & (_UINT32_(value) << TCC_WAVE_SWAP2_Pos)) /* Assignment of value for SWAP2 in the TCC_WAVE register */ 1114 #define TCC_WAVE_SWAP3_Pos _UINT32_(27) /* (TCC_WAVE) Swap DTI Output Pair 3 Position */ 1115 #define TCC_WAVE_SWAP3_Msk (_UINT32_(0x1) << TCC_WAVE_SWAP3_Pos) /* (TCC_WAVE) Swap DTI Output Pair 3 Mask */ 1116 #define TCC_WAVE_SWAP3(value) (TCC_WAVE_SWAP3_Msk & (_UINT32_(value) << TCC_WAVE_SWAP3_Pos)) /* Assignment of value for SWAP3 in the TCC_WAVE register */ 1117 #define TCC_WAVE_Msk _UINT32_(0x0F3F0FB7) /* (TCC_WAVE) Register Mask */ 1118 1119 #define TCC_WAVE_CICCEN_Pos _UINT32_(8) /* (TCC_WAVE Position) Circular Channel x Enable */ 1120 #define TCC_WAVE_CICCEN_Msk (_UINT32_(0xF) << TCC_WAVE_CICCEN_Pos) /* (TCC_WAVE Mask) CICCEN */ 1121 #define TCC_WAVE_CICCEN(value) (TCC_WAVE_CICCEN_Msk & (_UINT32_(value) << TCC_WAVE_CICCEN_Pos)) 1122 #define TCC_WAVE_POL_Pos _UINT32_(16) /* (TCC_WAVE Position) Channel x Polarity */ 1123 #define TCC_WAVE_POL_Msk (_UINT32_(0x3F) << TCC_WAVE_POL_Pos) /* (TCC_WAVE Mask) POL */ 1124 #define TCC_WAVE_POL(value) (TCC_WAVE_POL_Msk & (_UINT32_(value) << TCC_WAVE_POL_Pos)) 1125 #define TCC_WAVE_SWAP_Pos _UINT32_(24) /* (TCC_WAVE Position) Swap DTI Output Pair 3 */ 1126 #define TCC_WAVE_SWAP_Msk (_UINT32_(0xF) << TCC_WAVE_SWAP_Pos) /* (TCC_WAVE Mask) SWAP */ 1127 #define TCC_WAVE_SWAP(value) (TCC_WAVE_SWAP_Msk & (_UINT32_(value) << TCC_WAVE_SWAP_Pos)) 1128 1129 /* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */ 1130 #define TCC_PER_RESETVALUE _UINT32_(0xFFFFFFFF) /* (TCC_PER) Period Reset Value */ 1131 1132 #define TCC_PER_PER_Pos _UINT32_(0) /* (TCC_PER) Period Value Position */ 1133 #define TCC_PER_PER_Msk (_UINT32_(0xFFFFFF) << TCC_PER_PER_Pos) /* (TCC_PER) Period Value Mask */ 1134 #define TCC_PER_PER(value) (TCC_PER_PER_Msk & (_UINT32_(value) << TCC_PER_PER_Pos)) /* Assignment of value for PER in the TCC_PER register */ 1135 #define TCC_PER_Msk _UINT32_(0x00FFFFFF) /* (TCC_PER) Register Mask */ 1136 1137 /* DITH4 mode */ 1138 #define TCC_PER_DITH4_DITHER_Pos _UINT32_(0) /* (TCC_PER) Dithering Cycle Number Position */ 1139 #define TCC_PER_DITH4_DITHER_Msk (_UINT32_(0xF) << TCC_PER_DITH4_DITHER_Pos) /* (TCC_PER) Dithering Cycle Number Mask */ 1140 #define TCC_PER_DITH4_DITHER(value) (TCC_PER_DITH4_DITHER_Msk & (_UINT32_(value) << TCC_PER_DITH4_DITHER_Pos)) 1141 #define TCC_PER_DITH4_PER_Pos _UINT32_(4) /* (TCC_PER) Period Value Position */ 1142 #define TCC_PER_DITH4_PER_Msk (_UINT32_(0xFFFFF) << TCC_PER_DITH4_PER_Pos) /* (TCC_PER) Period Value Mask */ 1143 #define TCC_PER_DITH4_PER(value) (TCC_PER_DITH4_PER_Msk & (_UINT32_(value) << TCC_PER_DITH4_PER_Pos)) 1144 #define TCC_PER_DITH4_Msk _UINT32_(0x00FFFFFF) /* (TCC_PER_DITH4) Register Mask */ 1145 1146 /* DITH5 mode */ 1147 #define TCC_PER_DITH5_DITHER_Pos _UINT32_(0) /* (TCC_PER) Dithering Cycle Number Position */ 1148 #define TCC_PER_DITH5_DITHER_Msk (_UINT32_(0x1F) << TCC_PER_DITH5_DITHER_Pos) /* (TCC_PER) Dithering Cycle Number Mask */ 1149 #define TCC_PER_DITH5_DITHER(value) (TCC_PER_DITH5_DITHER_Msk & (_UINT32_(value) << TCC_PER_DITH5_DITHER_Pos)) 1150 #define TCC_PER_DITH5_PER_Pos _UINT32_(5) /* (TCC_PER) Period Value Position */ 1151 #define TCC_PER_DITH5_PER_Msk (_UINT32_(0x7FFFF) << TCC_PER_DITH5_PER_Pos) /* (TCC_PER) Period Value Mask */ 1152 #define TCC_PER_DITH5_PER(value) (TCC_PER_DITH5_PER_Msk & (_UINT32_(value) << TCC_PER_DITH5_PER_Pos)) 1153 #define TCC_PER_DITH5_Msk _UINT32_(0x00FFFFFF) /* (TCC_PER_DITH5) Register Mask */ 1154 1155 /* DITH6 mode */ 1156 #define TCC_PER_DITH6_DITHER_Pos _UINT32_(0) /* (TCC_PER) Dithering Cycle Number Position */ 1157 #define TCC_PER_DITH6_DITHER_Msk (_UINT32_(0x3F) << TCC_PER_DITH6_DITHER_Pos) /* (TCC_PER) Dithering Cycle Number Mask */ 1158 #define TCC_PER_DITH6_DITHER(value) (TCC_PER_DITH6_DITHER_Msk & (_UINT32_(value) << TCC_PER_DITH6_DITHER_Pos)) 1159 #define TCC_PER_DITH6_PER_Pos _UINT32_(6) /* (TCC_PER) Period Value Position */ 1160 #define TCC_PER_DITH6_PER_Msk (_UINT32_(0x3FFFF) << TCC_PER_DITH6_PER_Pos) /* (TCC_PER) Period Value Mask */ 1161 #define TCC_PER_DITH6_PER(value) (TCC_PER_DITH6_PER_Msk & (_UINT32_(value) << TCC_PER_DITH6_PER_Pos)) 1162 #define TCC_PER_DITH6_Msk _UINT32_(0x00FFFFFF) /* (TCC_PER_DITH6) Register Mask */ 1163 1164 1165 /* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */ 1166 #define TCC_CC_RESETVALUE _UINT32_(0x00) /* (TCC_CC) Compare and Capture Reset Value */ 1167 1168 #define TCC_CC_CC_Pos _UINT32_(0) /* (TCC_CC) Channel Compare/Capture Value Position */ 1169 #define TCC_CC_CC_Msk (_UINT32_(0xFFFFFF) << TCC_CC_CC_Pos) /* (TCC_CC) Channel Compare/Capture Value Mask */ 1170 #define TCC_CC_CC(value) (TCC_CC_CC_Msk & (_UINT32_(value) << TCC_CC_CC_Pos)) /* Assignment of value for CC in the TCC_CC register */ 1171 #define TCC_CC_Msk _UINT32_(0x00FFFFFF) /* (TCC_CC) Register Mask */ 1172 1173 /* DITH4 mode */ 1174 #define TCC_CC_DITH4_DITHER_Pos _UINT32_(0) /* (TCC_CC) Dithering Cycle Number Position */ 1175 #define TCC_CC_DITH4_DITHER_Msk (_UINT32_(0xF) << TCC_CC_DITH4_DITHER_Pos) /* (TCC_CC) Dithering Cycle Number Mask */ 1176 #define TCC_CC_DITH4_DITHER(value) (TCC_CC_DITH4_DITHER_Msk & (_UINT32_(value) << TCC_CC_DITH4_DITHER_Pos)) 1177 #define TCC_CC_DITH4_CC_Pos _UINT32_(4) /* (TCC_CC) Channel Compare/Capture Value Position */ 1178 #define TCC_CC_DITH4_CC_Msk (_UINT32_(0xFFFFF) << TCC_CC_DITH4_CC_Pos) /* (TCC_CC) Channel Compare/Capture Value Mask */ 1179 #define TCC_CC_DITH4_CC(value) (TCC_CC_DITH4_CC_Msk & (_UINT32_(value) << TCC_CC_DITH4_CC_Pos)) 1180 #define TCC_CC_DITH4_Msk _UINT32_(0x00FFFFFF) /* (TCC_CC_DITH4) Register Mask */ 1181 1182 /* DITH5 mode */ 1183 #define TCC_CC_DITH5_DITHER_Pos _UINT32_(0) /* (TCC_CC) Dithering Cycle Number Position */ 1184 #define TCC_CC_DITH5_DITHER_Msk (_UINT32_(0x1F) << TCC_CC_DITH5_DITHER_Pos) /* (TCC_CC) Dithering Cycle Number Mask */ 1185 #define TCC_CC_DITH5_DITHER(value) (TCC_CC_DITH5_DITHER_Msk & (_UINT32_(value) << TCC_CC_DITH5_DITHER_Pos)) 1186 #define TCC_CC_DITH5_CC_Pos _UINT32_(5) /* (TCC_CC) Channel Compare/Capture Value Position */ 1187 #define TCC_CC_DITH5_CC_Msk (_UINT32_(0x7FFFF) << TCC_CC_DITH5_CC_Pos) /* (TCC_CC) Channel Compare/Capture Value Mask */ 1188 #define TCC_CC_DITH5_CC(value) (TCC_CC_DITH5_CC_Msk & (_UINT32_(value) << TCC_CC_DITH5_CC_Pos)) 1189 #define TCC_CC_DITH5_Msk _UINT32_(0x00FFFFFF) /* (TCC_CC_DITH5) Register Mask */ 1190 1191 /* DITH6 mode */ 1192 #define TCC_CC_DITH6_DITHER_Pos _UINT32_(0) /* (TCC_CC) Dithering Cycle Number Position */ 1193 #define TCC_CC_DITH6_DITHER_Msk (_UINT32_(0x3F) << TCC_CC_DITH6_DITHER_Pos) /* (TCC_CC) Dithering Cycle Number Mask */ 1194 #define TCC_CC_DITH6_DITHER(value) (TCC_CC_DITH6_DITHER_Msk & (_UINT32_(value) << TCC_CC_DITH6_DITHER_Pos)) 1195 #define TCC_CC_DITH6_CC_Pos _UINT32_(6) /* (TCC_CC) Channel Compare/Capture Value Position */ 1196 #define TCC_CC_DITH6_CC_Msk (_UINT32_(0x3FFFF) << TCC_CC_DITH6_CC_Pos) /* (TCC_CC) Channel Compare/Capture Value Mask */ 1197 #define TCC_CC_DITH6_CC(value) (TCC_CC_DITH6_CC_Msk & (_UINT32_(value) << TCC_CC_DITH6_CC_Pos)) 1198 #define TCC_CC_DITH6_Msk _UINT32_(0x00FFFFFF) /* (TCC_CC_DITH6) Register Mask */ 1199 1200 1201 /* -------- TCC_PATTBUF : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */ 1202 #define TCC_PATTBUF_RESETVALUE _UINT16_(0x00) /* (TCC_PATTBUF) Pattern Buffer Reset Value */ 1203 1204 #define TCC_PATTBUF_PGEB0_Pos _UINT16_(0) /* (TCC_PATTBUF) Pattern Generator 0 Output Enable Buffer Position */ 1205 #define TCC_PATTBUF_PGEB0_Msk (_UINT16_(0x1) << TCC_PATTBUF_PGEB0_Pos) /* (TCC_PATTBUF) Pattern Generator 0 Output Enable Buffer Mask */ 1206 #define TCC_PATTBUF_PGEB0(value) (TCC_PATTBUF_PGEB0_Msk & (_UINT16_(value) << TCC_PATTBUF_PGEB0_Pos)) /* Assignment of value for PGEB0 in the TCC_PATTBUF register */ 1207 #define TCC_PATTBUF_PGEB1_Pos _UINT16_(1) /* (TCC_PATTBUF) Pattern Generator 1 Output Enable Buffer Position */ 1208 #define TCC_PATTBUF_PGEB1_Msk (_UINT16_(0x1) << TCC_PATTBUF_PGEB1_Pos) /* (TCC_PATTBUF) Pattern Generator 1 Output Enable Buffer Mask */ 1209 #define TCC_PATTBUF_PGEB1(value) (TCC_PATTBUF_PGEB1_Msk & (_UINT16_(value) << TCC_PATTBUF_PGEB1_Pos)) /* Assignment of value for PGEB1 in the TCC_PATTBUF register */ 1210 #define TCC_PATTBUF_PGEB2_Pos _UINT16_(2) /* (TCC_PATTBUF) Pattern Generator 2 Output Enable Buffer Position */ 1211 #define TCC_PATTBUF_PGEB2_Msk (_UINT16_(0x1) << TCC_PATTBUF_PGEB2_Pos) /* (TCC_PATTBUF) Pattern Generator 2 Output Enable Buffer Mask */ 1212 #define TCC_PATTBUF_PGEB2(value) (TCC_PATTBUF_PGEB2_Msk & (_UINT16_(value) << TCC_PATTBUF_PGEB2_Pos)) /* Assignment of value for PGEB2 in the TCC_PATTBUF register */ 1213 #define TCC_PATTBUF_PGEB3_Pos _UINT16_(3) /* (TCC_PATTBUF) Pattern Generator 3 Output Enable Buffer Position */ 1214 #define TCC_PATTBUF_PGEB3_Msk (_UINT16_(0x1) << TCC_PATTBUF_PGEB3_Pos) /* (TCC_PATTBUF) Pattern Generator 3 Output Enable Buffer Mask */ 1215 #define TCC_PATTBUF_PGEB3(value) (TCC_PATTBUF_PGEB3_Msk & (_UINT16_(value) << TCC_PATTBUF_PGEB3_Pos)) /* Assignment of value for PGEB3 in the TCC_PATTBUF register */ 1216 #define TCC_PATTBUF_PGEB4_Pos _UINT16_(4) /* (TCC_PATTBUF) Pattern Generator 4 Output Enable Buffer Position */ 1217 #define TCC_PATTBUF_PGEB4_Msk (_UINT16_(0x1) << TCC_PATTBUF_PGEB4_Pos) /* (TCC_PATTBUF) Pattern Generator 4 Output Enable Buffer Mask */ 1218 #define TCC_PATTBUF_PGEB4(value) (TCC_PATTBUF_PGEB4_Msk & (_UINT16_(value) << TCC_PATTBUF_PGEB4_Pos)) /* Assignment of value for PGEB4 in the TCC_PATTBUF register */ 1219 #define TCC_PATTBUF_PGEB5_Pos _UINT16_(5) /* (TCC_PATTBUF) Pattern Generator 5 Output Enable Buffer Position */ 1220 #define TCC_PATTBUF_PGEB5_Msk (_UINT16_(0x1) << TCC_PATTBUF_PGEB5_Pos) /* (TCC_PATTBUF) Pattern Generator 5 Output Enable Buffer Mask */ 1221 #define TCC_PATTBUF_PGEB5(value) (TCC_PATTBUF_PGEB5_Msk & (_UINT16_(value) << TCC_PATTBUF_PGEB5_Pos)) /* Assignment of value for PGEB5 in the TCC_PATTBUF register */ 1222 #define TCC_PATTBUF_PGEB6_Pos _UINT16_(6) /* (TCC_PATTBUF) Pattern Generator 6 Output Enable Buffer Position */ 1223 #define TCC_PATTBUF_PGEB6_Msk (_UINT16_(0x1) << TCC_PATTBUF_PGEB6_Pos) /* (TCC_PATTBUF) Pattern Generator 6 Output Enable Buffer Mask */ 1224 #define TCC_PATTBUF_PGEB6(value) (TCC_PATTBUF_PGEB6_Msk & (_UINT16_(value) << TCC_PATTBUF_PGEB6_Pos)) /* Assignment of value for PGEB6 in the TCC_PATTBUF register */ 1225 #define TCC_PATTBUF_PGEB7_Pos _UINT16_(7) /* (TCC_PATTBUF) Pattern Generator 7 Output Enable Buffer Position */ 1226 #define TCC_PATTBUF_PGEB7_Msk (_UINT16_(0x1) << TCC_PATTBUF_PGEB7_Pos) /* (TCC_PATTBUF) Pattern Generator 7 Output Enable Buffer Mask */ 1227 #define TCC_PATTBUF_PGEB7(value) (TCC_PATTBUF_PGEB7_Msk & (_UINT16_(value) << TCC_PATTBUF_PGEB7_Pos)) /* Assignment of value for PGEB7 in the TCC_PATTBUF register */ 1228 #define TCC_PATTBUF_PGVB0_Pos _UINT16_(8) /* (TCC_PATTBUF) Pattern Generator 0 Output Enable Position */ 1229 #define TCC_PATTBUF_PGVB0_Msk (_UINT16_(0x1) << TCC_PATTBUF_PGVB0_Pos) /* (TCC_PATTBUF) Pattern Generator 0 Output Enable Mask */ 1230 #define TCC_PATTBUF_PGVB0(value) (TCC_PATTBUF_PGVB0_Msk & (_UINT16_(value) << TCC_PATTBUF_PGVB0_Pos)) /* Assignment of value for PGVB0 in the TCC_PATTBUF register */ 1231 #define TCC_PATTBUF_PGVB1_Pos _UINT16_(9) /* (TCC_PATTBUF) Pattern Generator 1 Output Enable Position */ 1232 #define TCC_PATTBUF_PGVB1_Msk (_UINT16_(0x1) << TCC_PATTBUF_PGVB1_Pos) /* (TCC_PATTBUF) Pattern Generator 1 Output Enable Mask */ 1233 #define TCC_PATTBUF_PGVB1(value) (TCC_PATTBUF_PGVB1_Msk & (_UINT16_(value) << TCC_PATTBUF_PGVB1_Pos)) /* Assignment of value for PGVB1 in the TCC_PATTBUF register */ 1234 #define TCC_PATTBUF_PGVB2_Pos _UINT16_(10) /* (TCC_PATTBUF) Pattern Generator 2 Output Enable Position */ 1235 #define TCC_PATTBUF_PGVB2_Msk (_UINT16_(0x1) << TCC_PATTBUF_PGVB2_Pos) /* (TCC_PATTBUF) Pattern Generator 2 Output Enable Mask */ 1236 #define TCC_PATTBUF_PGVB2(value) (TCC_PATTBUF_PGVB2_Msk & (_UINT16_(value) << TCC_PATTBUF_PGVB2_Pos)) /* Assignment of value for PGVB2 in the TCC_PATTBUF register */ 1237 #define TCC_PATTBUF_PGVB3_Pos _UINT16_(11) /* (TCC_PATTBUF) Pattern Generator 3 Output Enable Position */ 1238 #define TCC_PATTBUF_PGVB3_Msk (_UINT16_(0x1) << TCC_PATTBUF_PGVB3_Pos) /* (TCC_PATTBUF) Pattern Generator 3 Output Enable Mask */ 1239 #define TCC_PATTBUF_PGVB3(value) (TCC_PATTBUF_PGVB3_Msk & (_UINT16_(value) << TCC_PATTBUF_PGVB3_Pos)) /* Assignment of value for PGVB3 in the TCC_PATTBUF register */ 1240 #define TCC_PATTBUF_PGVB4_Pos _UINT16_(12) /* (TCC_PATTBUF) Pattern Generator 4 Output Enable Position */ 1241 #define TCC_PATTBUF_PGVB4_Msk (_UINT16_(0x1) << TCC_PATTBUF_PGVB4_Pos) /* (TCC_PATTBUF) Pattern Generator 4 Output Enable Mask */ 1242 #define TCC_PATTBUF_PGVB4(value) (TCC_PATTBUF_PGVB4_Msk & (_UINT16_(value) << TCC_PATTBUF_PGVB4_Pos)) /* Assignment of value for PGVB4 in the TCC_PATTBUF register */ 1243 #define TCC_PATTBUF_PGVB5_Pos _UINT16_(13) /* (TCC_PATTBUF) Pattern Generator 5 Output Enable Position */ 1244 #define TCC_PATTBUF_PGVB5_Msk (_UINT16_(0x1) << TCC_PATTBUF_PGVB5_Pos) /* (TCC_PATTBUF) Pattern Generator 5 Output Enable Mask */ 1245 #define TCC_PATTBUF_PGVB5(value) (TCC_PATTBUF_PGVB5_Msk & (_UINT16_(value) << TCC_PATTBUF_PGVB5_Pos)) /* Assignment of value for PGVB5 in the TCC_PATTBUF register */ 1246 #define TCC_PATTBUF_PGVB6_Pos _UINT16_(14) /* (TCC_PATTBUF) Pattern Generator 6 Output Enable Position */ 1247 #define TCC_PATTBUF_PGVB6_Msk (_UINT16_(0x1) << TCC_PATTBUF_PGVB6_Pos) /* (TCC_PATTBUF) Pattern Generator 6 Output Enable Mask */ 1248 #define TCC_PATTBUF_PGVB6(value) (TCC_PATTBUF_PGVB6_Msk & (_UINT16_(value) << TCC_PATTBUF_PGVB6_Pos)) /* Assignment of value for PGVB6 in the TCC_PATTBUF register */ 1249 #define TCC_PATTBUF_PGVB7_Pos _UINT16_(15) /* (TCC_PATTBUF) Pattern Generator 7 Output Enable Position */ 1250 #define TCC_PATTBUF_PGVB7_Msk (_UINT16_(0x1) << TCC_PATTBUF_PGVB7_Pos) /* (TCC_PATTBUF) Pattern Generator 7 Output Enable Mask */ 1251 #define TCC_PATTBUF_PGVB7(value) (TCC_PATTBUF_PGVB7_Msk & (_UINT16_(value) << TCC_PATTBUF_PGVB7_Pos)) /* Assignment of value for PGVB7 in the TCC_PATTBUF register */ 1252 #define TCC_PATTBUF_Msk _UINT16_(0xFFFF) /* (TCC_PATTBUF) Register Mask */ 1253 1254 #define TCC_PATTBUF_PGEB_Pos _UINT16_(0) /* (TCC_PATTBUF Position) Pattern Generator x Output Enable Buffer */ 1255 #define TCC_PATTBUF_PGEB_Msk (_UINT16_(0xFF) << TCC_PATTBUF_PGEB_Pos) /* (TCC_PATTBUF Mask) PGEB */ 1256 #define TCC_PATTBUF_PGEB(value) (TCC_PATTBUF_PGEB_Msk & (_UINT16_(value) << TCC_PATTBUF_PGEB_Pos)) 1257 #define TCC_PATTBUF_PGVB_Pos _UINT16_(8) /* (TCC_PATTBUF Position) Pattern Generator 7 Output Enable */ 1258 #define TCC_PATTBUF_PGVB_Msk (_UINT16_(0xFF) << TCC_PATTBUF_PGVB_Pos) /* (TCC_PATTBUF Mask) PGVB */ 1259 #define TCC_PATTBUF_PGVB(value) (TCC_PATTBUF_PGVB_Msk & (_UINT16_(value) << TCC_PATTBUF_PGVB_Pos)) 1260 1261 /* -------- TCC_PERBUF : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */ 1262 #define TCC_PERBUF_RESETVALUE _UINT32_(0xFFFFFFFF) /* (TCC_PERBUF) Period Buffer Reset Value */ 1263 1264 #define TCC_PERBUF_PERBUF_Pos _UINT32_(0) /* (TCC_PERBUF) Period Buffer Value Position */ 1265 #define TCC_PERBUF_PERBUF_Msk (_UINT32_(0xFFFFFF) << TCC_PERBUF_PERBUF_Pos) /* (TCC_PERBUF) Period Buffer Value Mask */ 1266 #define TCC_PERBUF_PERBUF(value) (TCC_PERBUF_PERBUF_Msk & (_UINT32_(value) << TCC_PERBUF_PERBUF_Pos)) /* Assignment of value for PERBUF in the TCC_PERBUF register */ 1267 #define TCC_PERBUF_Msk _UINT32_(0x00FFFFFF) /* (TCC_PERBUF) Register Mask */ 1268 1269 /* DITH4 mode */ 1270 #define TCC_PERBUF_DITH4_DITHERBUF_Pos _UINT32_(0) /* (TCC_PERBUF) Dithering Buffer Cycle Number Position */ 1271 #define TCC_PERBUF_DITH4_DITHERBUF_Msk (_UINT32_(0xF) << TCC_PERBUF_DITH4_DITHERBUF_Pos) /* (TCC_PERBUF) Dithering Buffer Cycle Number Mask */ 1272 #define TCC_PERBUF_DITH4_DITHERBUF(value) (TCC_PERBUF_DITH4_DITHERBUF_Msk & (_UINT32_(value) << TCC_PERBUF_DITH4_DITHERBUF_Pos)) 1273 #define TCC_PERBUF_DITH4_PERBUF_Pos _UINT32_(4) /* (TCC_PERBUF) Period Buffer Value Position */ 1274 #define TCC_PERBUF_DITH4_PERBUF_Msk (_UINT32_(0xFFFFF) << TCC_PERBUF_DITH4_PERBUF_Pos) /* (TCC_PERBUF) Period Buffer Value Mask */ 1275 #define TCC_PERBUF_DITH4_PERBUF(value) (TCC_PERBUF_DITH4_PERBUF_Msk & (_UINT32_(value) << TCC_PERBUF_DITH4_PERBUF_Pos)) 1276 #define TCC_PERBUF_DITH4_Msk _UINT32_(0x00FFFFFF) /* (TCC_PERBUF_DITH4) Register Mask */ 1277 1278 /* DITH5 mode */ 1279 #define TCC_PERBUF_DITH5_DITHERBUF_Pos _UINT32_(0) /* (TCC_PERBUF) Dithering Buffer Cycle Number Position */ 1280 #define TCC_PERBUF_DITH5_DITHERBUF_Msk (_UINT32_(0x1F) << TCC_PERBUF_DITH5_DITHERBUF_Pos) /* (TCC_PERBUF) Dithering Buffer Cycle Number Mask */ 1281 #define TCC_PERBUF_DITH5_DITHERBUF(value) (TCC_PERBUF_DITH5_DITHERBUF_Msk & (_UINT32_(value) << TCC_PERBUF_DITH5_DITHERBUF_Pos)) 1282 #define TCC_PERBUF_DITH5_PERBUF_Pos _UINT32_(5) /* (TCC_PERBUF) Period Buffer Value Position */ 1283 #define TCC_PERBUF_DITH5_PERBUF_Msk (_UINT32_(0x7FFFF) << TCC_PERBUF_DITH5_PERBUF_Pos) /* (TCC_PERBUF) Period Buffer Value Mask */ 1284 #define TCC_PERBUF_DITH5_PERBUF(value) (TCC_PERBUF_DITH5_PERBUF_Msk & (_UINT32_(value) << TCC_PERBUF_DITH5_PERBUF_Pos)) 1285 #define TCC_PERBUF_DITH5_Msk _UINT32_(0x00FFFFFF) /* (TCC_PERBUF_DITH5) Register Mask */ 1286 1287 /* DITH6 mode */ 1288 #define TCC_PERBUF_DITH6_DITHERBUF_Pos _UINT32_(0) /* (TCC_PERBUF) Dithering Buffer Cycle Number Position */ 1289 #define TCC_PERBUF_DITH6_DITHERBUF_Msk (_UINT32_(0x3F) << TCC_PERBUF_DITH6_DITHERBUF_Pos) /* (TCC_PERBUF) Dithering Buffer Cycle Number Mask */ 1290 #define TCC_PERBUF_DITH6_DITHERBUF(value) (TCC_PERBUF_DITH6_DITHERBUF_Msk & (_UINT32_(value) << TCC_PERBUF_DITH6_DITHERBUF_Pos)) 1291 #define TCC_PERBUF_DITH6_PERBUF_Pos _UINT32_(6) /* (TCC_PERBUF) Period Buffer Value Position */ 1292 #define TCC_PERBUF_DITH6_PERBUF_Msk (_UINT32_(0x3FFFF) << TCC_PERBUF_DITH6_PERBUF_Pos) /* (TCC_PERBUF) Period Buffer Value Mask */ 1293 #define TCC_PERBUF_DITH6_PERBUF(value) (TCC_PERBUF_DITH6_PERBUF_Msk & (_UINT32_(value) << TCC_PERBUF_DITH6_PERBUF_Pos)) 1294 #define TCC_PERBUF_DITH6_Msk _UINT32_(0x00FFFFFF) /* (TCC_PERBUF_DITH6) Register Mask */ 1295 1296 1297 /* -------- TCC_CCBUF : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */ 1298 #define TCC_CCBUF_RESETVALUE _UINT32_(0x00) /* (TCC_CCBUF) Compare and Capture Buffer Reset Value */ 1299 1300 #define TCC_CCBUF_CCBUF_Pos _UINT32_(0) /* (TCC_CCBUF) Channel Compare/Capture Buffer Value Position */ 1301 #define TCC_CCBUF_CCBUF_Msk (_UINT32_(0xFFFFFF) << TCC_CCBUF_CCBUF_Pos) /* (TCC_CCBUF) Channel Compare/Capture Buffer Value Mask */ 1302 #define TCC_CCBUF_CCBUF(value) (TCC_CCBUF_CCBUF_Msk & (_UINT32_(value) << TCC_CCBUF_CCBUF_Pos)) /* Assignment of value for CCBUF in the TCC_CCBUF register */ 1303 #define TCC_CCBUF_Msk _UINT32_(0x00FFFFFF) /* (TCC_CCBUF) Register Mask */ 1304 1305 /* DITH4 mode */ 1306 #define TCC_CCBUF_DITH4_CCBUF_Pos _UINT32_(0) /* (TCC_CCBUF) Channel Compare/Capture Buffer Value Position */ 1307 #define TCC_CCBUF_DITH4_CCBUF_Msk (_UINT32_(0xF) << TCC_CCBUF_DITH4_CCBUF_Pos) /* (TCC_CCBUF) Channel Compare/Capture Buffer Value Mask */ 1308 #define TCC_CCBUF_DITH4_CCBUF(value) (TCC_CCBUF_DITH4_CCBUF_Msk & (_UINT32_(value) << TCC_CCBUF_DITH4_CCBUF_Pos)) 1309 #define TCC_CCBUF_DITH4_DITHERBUF_Pos _UINT32_(4) /* (TCC_CCBUF) Dithering Buffer Cycle Number Position */ 1310 #define TCC_CCBUF_DITH4_DITHERBUF_Msk (_UINT32_(0xFFFFF) << TCC_CCBUF_DITH4_DITHERBUF_Pos) /* (TCC_CCBUF) Dithering Buffer Cycle Number Mask */ 1311 #define TCC_CCBUF_DITH4_DITHERBUF(value) (TCC_CCBUF_DITH4_DITHERBUF_Msk & (_UINT32_(value) << TCC_CCBUF_DITH4_DITHERBUF_Pos)) 1312 #define TCC_CCBUF_DITH4_Msk _UINT32_(0x00FFFFFF) /* (TCC_CCBUF_DITH4) Register Mask */ 1313 1314 /* DITH5 mode */ 1315 #define TCC_CCBUF_DITH5_DITHERBUF_Pos _UINT32_(0) /* (TCC_CCBUF) Dithering Buffer Cycle Number Position */ 1316 #define TCC_CCBUF_DITH5_DITHERBUF_Msk (_UINT32_(0x1F) << TCC_CCBUF_DITH5_DITHERBUF_Pos) /* (TCC_CCBUF) Dithering Buffer Cycle Number Mask */ 1317 #define TCC_CCBUF_DITH5_DITHERBUF(value) (TCC_CCBUF_DITH5_DITHERBUF_Msk & (_UINT32_(value) << TCC_CCBUF_DITH5_DITHERBUF_Pos)) 1318 #define TCC_CCBUF_DITH5_CCBUF_Pos _UINT32_(5) /* (TCC_CCBUF) Channel Compare/Capture Buffer Value Position */ 1319 #define TCC_CCBUF_DITH5_CCBUF_Msk (_UINT32_(0x7FFFF) << TCC_CCBUF_DITH5_CCBUF_Pos) /* (TCC_CCBUF) Channel Compare/Capture Buffer Value Mask */ 1320 #define TCC_CCBUF_DITH5_CCBUF(value) (TCC_CCBUF_DITH5_CCBUF_Msk & (_UINT32_(value) << TCC_CCBUF_DITH5_CCBUF_Pos)) 1321 #define TCC_CCBUF_DITH5_Msk _UINT32_(0x00FFFFFF) /* (TCC_CCBUF_DITH5) Register Mask */ 1322 1323 /* DITH6 mode */ 1324 #define TCC_CCBUF_DITH6_DITHERBUF_Pos _UINT32_(0) /* (TCC_CCBUF) Dithering Buffer Cycle Number Position */ 1325 #define TCC_CCBUF_DITH6_DITHERBUF_Msk (_UINT32_(0x3F) << TCC_CCBUF_DITH6_DITHERBUF_Pos) /* (TCC_CCBUF) Dithering Buffer Cycle Number Mask */ 1326 #define TCC_CCBUF_DITH6_DITHERBUF(value) (TCC_CCBUF_DITH6_DITHERBUF_Msk & (_UINT32_(value) << TCC_CCBUF_DITH6_DITHERBUF_Pos)) 1327 #define TCC_CCBUF_DITH6_CCBUF_Pos _UINT32_(6) /* (TCC_CCBUF) Channel Compare/Capture Buffer Value Position */ 1328 #define TCC_CCBUF_DITH6_CCBUF_Msk (_UINT32_(0x3FFFF) << TCC_CCBUF_DITH6_CCBUF_Pos) /* (TCC_CCBUF) Channel Compare/Capture Buffer Value Mask */ 1329 #define TCC_CCBUF_DITH6_CCBUF(value) (TCC_CCBUF_DITH6_CCBUF_Msk & (_UINT32_(value) << TCC_CCBUF_DITH6_CCBUF_Pos)) 1330 #define TCC_CCBUF_DITH6_Msk _UINT32_(0x00FFFFFF) /* (TCC_CCBUF_DITH6) Register Mask */ 1331 1332 1333 /* TCC register offsets definitions */ 1334 #define TCC_CTRLA_REG_OFST _UINT32_(0x00) /* (TCC_CTRLA) Control A Offset */ 1335 #define TCC_CTRLBCLR_REG_OFST _UINT32_(0x04) /* (TCC_CTRLBCLR) Control B Clear Offset */ 1336 #define TCC_CTRLBSET_REG_OFST _UINT32_(0x05) /* (TCC_CTRLBSET) Control B Set Offset */ 1337 #define TCC_SYNCBUSY_REG_OFST _UINT32_(0x08) /* (TCC_SYNCBUSY) Synchronization Busy Offset */ 1338 #define TCC_FCTRLA_REG_OFST _UINT32_(0x0C) /* (TCC_FCTRLA) Recoverable Fault A Configuration Offset */ 1339 #define TCC_FCTRLB_REG_OFST _UINT32_(0x10) /* (TCC_FCTRLB) Recoverable Fault B Configuration Offset */ 1340 #define TCC_WEXCTRL_REG_OFST _UINT32_(0x14) /* (TCC_WEXCTRL) Waveform Extension Configuration Offset */ 1341 #define TCC_DRVCTRL_REG_OFST _UINT32_(0x18) /* (TCC_DRVCTRL) Driver Control Offset */ 1342 #define TCC_DBGCTRL_REG_OFST _UINT32_(0x1E) /* (TCC_DBGCTRL) Debug Control Offset */ 1343 #define TCC_EVCTRL_REG_OFST _UINT32_(0x20) /* (TCC_EVCTRL) Event Control Offset */ 1344 #define TCC_INTENCLR_REG_OFST _UINT32_(0x24) /* (TCC_INTENCLR) Interrupt Enable Clear Offset */ 1345 #define TCC_INTENSET_REG_OFST _UINT32_(0x28) /* (TCC_INTENSET) Interrupt Enable Set Offset */ 1346 #define TCC_INTFLAG_REG_OFST _UINT32_(0x2C) /* (TCC_INTFLAG) Interrupt Flag Status and Clear Offset */ 1347 #define TCC_STATUS_REG_OFST _UINT32_(0x30) /* (TCC_STATUS) Status Offset */ 1348 #define TCC_COUNT_REG_OFST _UINT32_(0x34) /* (TCC_COUNT) Count Offset */ 1349 #define TCC_PATT_REG_OFST _UINT32_(0x38) /* (TCC_PATT) Pattern Offset */ 1350 #define TCC_WAVE_REG_OFST _UINT32_(0x3C) /* (TCC_WAVE) Waveform Control Offset */ 1351 #define TCC_PER_REG_OFST _UINT32_(0x40) /* (TCC_PER) Period Offset */ 1352 #define TCC_CC_REG_OFST _UINT32_(0x44) /* (TCC_CC) Compare and Capture Offset */ 1353 #define TCC_CC0_REG_OFST _UINT32_(0x44) /* (TCC_CC0) Compare and Capture Offset */ 1354 #define TCC_CC1_REG_OFST _UINT32_(0x48) /* (TCC_CC1) Compare and Capture Offset */ 1355 #define TCC_CC2_REG_OFST _UINT32_(0x4C) /* (TCC_CC2) Compare and Capture Offset */ 1356 #define TCC_CC3_REG_OFST _UINT32_(0x50) /* (TCC_CC3) Compare and Capture Offset */ 1357 #define TCC_CC4_REG_OFST _UINT32_(0x54) /* (TCC_CC4) Compare and Capture Offset */ 1358 #define TCC_CC5_REG_OFST _UINT32_(0x58) /* (TCC_CC5) Compare and Capture Offset */ 1359 #define TCC_PATTBUF_REG_OFST _UINT32_(0x64) /* (TCC_PATTBUF) Pattern Buffer Offset */ 1360 #define TCC_PERBUF_REG_OFST _UINT32_(0x6C) /* (TCC_PERBUF) Period Buffer Offset */ 1361 #define TCC_CCBUF_REG_OFST _UINT32_(0x70) /* (TCC_CCBUF) Compare and Capture Buffer Offset */ 1362 #define TCC_CCBUF0_REG_OFST _UINT32_(0x70) /* (TCC_CCBUF0) Compare and Capture Buffer Offset */ 1363 #define TCC_CCBUF1_REG_OFST _UINT32_(0x74) /* (TCC_CCBUF1) Compare and Capture Buffer Offset */ 1364 #define TCC_CCBUF2_REG_OFST _UINT32_(0x78) /* (TCC_CCBUF2) Compare and Capture Buffer Offset */ 1365 #define TCC_CCBUF3_REG_OFST _UINT32_(0x7C) /* (TCC_CCBUF3) Compare and Capture Buffer Offset */ 1366 #define TCC_CCBUF4_REG_OFST _UINT32_(0x80) /* (TCC_CCBUF4) Compare and Capture Buffer Offset */ 1367 #define TCC_CCBUF5_REG_OFST _UINT32_(0x84) /* (TCC_CCBUF5) Compare and Capture Buffer Offset */ 1368 1369 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1370 /* TCC register API structure */ 1371 typedef struct 1372 { /* Timer Counter Control */ 1373 __IO uint32_t TCC_CTRLA; /* Offset: 0x00 (R/W 32) Control A */ 1374 __IO uint8_t TCC_CTRLBCLR; /* Offset: 0x04 (R/W 8) Control B Clear */ 1375 __IO uint8_t TCC_CTRLBSET; /* Offset: 0x05 (R/W 8) Control B Set */ 1376 __I uint8_t Reserved1[0x02]; 1377 __I uint32_t TCC_SYNCBUSY; /* Offset: 0x08 (R/ 32) Synchronization Busy */ 1378 __IO uint32_t TCC_FCTRLA; /* Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */ 1379 __IO uint32_t TCC_FCTRLB; /* Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */ 1380 __IO uint32_t TCC_WEXCTRL; /* Offset: 0x14 (R/W 32) Waveform Extension Configuration */ 1381 __IO uint32_t TCC_DRVCTRL; /* Offset: 0x18 (R/W 32) Driver Control */ 1382 __I uint8_t Reserved2[0x02]; 1383 __IO uint8_t TCC_DBGCTRL; /* Offset: 0x1E (R/W 8) Debug Control */ 1384 __I uint8_t Reserved3[0x01]; 1385 __IO uint32_t TCC_EVCTRL; /* Offset: 0x20 (R/W 32) Event Control */ 1386 __IO uint32_t TCC_INTENCLR; /* Offset: 0x24 (R/W 32) Interrupt Enable Clear */ 1387 __IO uint32_t TCC_INTENSET; /* Offset: 0x28 (R/W 32) Interrupt Enable Set */ 1388 __IO uint32_t TCC_INTFLAG; /* Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */ 1389 __IO uint32_t TCC_STATUS; /* Offset: 0x30 (R/W 32) Status */ 1390 __IO uint32_t TCC_COUNT; /* Offset: 0x34 (R/W 32) Count */ 1391 __IO uint16_t TCC_PATT; /* Offset: 0x38 (R/W 16) Pattern */ 1392 __I uint8_t Reserved4[0x02]; 1393 __IO uint32_t TCC_WAVE; /* Offset: 0x3C (R/W 32) Waveform Control */ 1394 __IO uint32_t TCC_PER; /* Offset: 0x40 (R/W 32) Period */ 1395 __IO uint32_t TCC_CC[6]; /* Offset: 0x44 (R/W 32) Compare and Capture */ 1396 __I uint8_t Reserved5[0x08]; 1397 __IO uint16_t TCC_PATTBUF; /* Offset: 0x64 (R/W 16) Pattern Buffer */ 1398 __I uint8_t Reserved6[0x06]; 1399 __IO uint32_t TCC_PERBUF; /* Offset: 0x6C (R/W 32) Period Buffer */ 1400 __IO uint32_t TCC_CCBUF[6]; /* Offset: 0x70 (R/W 32) Compare and Capture Buffer */ 1401 } tcc_registers_t; 1402 1403 1404 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1405 #endif /* _PIC32CXSG41_TCC_COMPONENT_H_ */ 1406
