1 /* 2 * Component description for RTC 3 * 4 * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 */ 19 20 /* file generated from device description file (ATDF) version 2023-03-17T09:48:34Z */ 21 #ifndef _PIC32CXSG41_RTC_COMPONENT_H_ 22 #define _PIC32CXSG41_RTC_COMPONENT_H_ 23 24 /* ************************************************************************** */ 25 /* SOFTWARE API DEFINITION FOR RTC */ 26 /* ************************************************************************** */ 27 28 /* -------- RTC_MODE0_CTRLA : (RTC Offset: 0x00) (R/W 16) MODE0 Control A -------- */ 29 #define RTC_MODE0_CTRLA_RESETVALUE _UINT16_(0x00) /* (RTC_MODE0_CTRLA) MODE0 Control A Reset Value */ 30 31 #define RTC_MODE0_CTRLA_SWRST_Pos _UINT16_(0) /* (RTC_MODE0_CTRLA) Software Reset Position */ 32 #define RTC_MODE0_CTRLA_SWRST_Msk (_UINT16_(0x1) << RTC_MODE0_CTRLA_SWRST_Pos) /* (RTC_MODE0_CTRLA) Software Reset Mask */ 33 #define RTC_MODE0_CTRLA_SWRST(value) (RTC_MODE0_CTRLA_SWRST_Msk & (_UINT16_(value) << RTC_MODE0_CTRLA_SWRST_Pos)) /* Assignment of value for SWRST in the RTC_MODE0_CTRLA register */ 34 #define RTC_MODE0_CTRLA_ENABLE_Pos _UINT16_(1) /* (RTC_MODE0_CTRLA) Enable Position */ 35 #define RTC_MODE0_CTRLA_ENABLE_Msk (_UINT16_(0x1) << RTC_MODE0_CTRLA_ENABLE_Pos) /* (RTC_MODE0_CTRLA) Enable Mask */ 36 #define RTC_MODE0_CTRLA_ENABLE(value) (RTC_MODE0_CTRLA_ENABLE_Msk & (_UINT16_(value) << RTC_MODE0_CTRLA_ENABLE_Pos)) /* Assignment of value for ENABLE in the RTC_MODE0_CTRLA register */ 37 #define RTC_MODE0_CTRLA_MODE_Pos _UINT16_(2) /* (RTC_MODE0_CTRLA) Operating Mode Position */ 38 #define RTC_MODE0_CTRLA_MODE_Msk (_UINT16_(0x3) << RTC_MODE0_CTRLA_MODE_Pos) /* (RTC_MODE0_CTRLA) Operating Mode Mask */ 39 #define RTC_MODE0_CTRLA_MODE(value) (RTC_MODE0_CTRLA_MODE_Msk & (_UINT16_(value) << RTC_MODE0_CTRLA_MODE_Pos)) /* Assignment of value for MODE in the RTC_MODE0_CTRLA register */ 40 #define RTC_MODE0_CTRLA_MODE_COUNT32_Val _UINT16_(0x0) /* (RTC_MODE0_CTRLA) Mode 0: 32-bit Counter */ 41 #define RTC_MODE0_CTRLA_MODE_COUNT16_Val _UINT16_(0x1) /* (RTC_MODE0_CTRLA) Mode 1: 16-bit Counter */ 42 #define RTC_MODE0_CTRLA_MODE_CLOCK_Val _UINT16_(0x2) /* (RTC_MODE0_CTRLA) Mode 2: Clock/Calendar */ 43 #define RTC_MODE0_CTRLA_MODE_COUNT32 (RTC_MODE0_CTRLA_MODE_COUNT32_Val << RTC_MODE0_CTRLA_MODE_Pos) /* (RTC_MODE0_CTRLA) Mode 0: 32-bit Counter Position */ 44 #define RTC_MODE0_CTRLA_MODE_COUNT16 (RTC_MODE0_CTRLA_MODE_COUNT16_Val << RTC_MODE0_CTRLA_MODE_Pos) /* (RTC_MODE0_CTRLA) Mode 1: 16-bit Counter Position */ 45 #define RTC_MODE0_CTRLA_MODE_CLOCK (RTC_MODE0_CTRLA_MODE_CLOCK_Val << RTC_MODE0_CTRLA_MODE_Pos) /* (RTC_MODE0_CTRLA) Mode 2: Clock/Calendar Position */ 46 #define RTC_MODE0_CTRLA_MATCHCLR_Pos _UINT16_(7) /* (RTC_MODE0_CTRLA) Clear on Match Position */ 47 #define RTC_MODE0_CTRLA_MATCHCLR_Msk (_UINT16_(0x1) << RTC_MODE0_CTRLA_MATCHCLR_Pos) /* (RTC_MODE0_CTRLA) Clear on Match Mask */ 48 #define RTC_MODE0_CTRLA_MATCHCLR(value) (RTC_MODE0_CTRLA_MATCHCLR_Msk & (_UINT16_(value) << RTC_MODE0_CTRLA_MATCHCLR_Pos)) /* Assignment of value for MATCHCLR in the RTC_MODE0_CTRLA register */ 49 #define RTC_MODE0_CTRLA_PRESCALER_Pos _UINT16_(8) /* (RTC_MODE0_CTRLA) Prescaler Position */ 50 #define RTC_MODE0_CTRLA_PRESCALER_Msk (_UINT16_(0xF) << RTC_MODE0_CTRLA_PRESCALER_Pos) /* (RTC_MODE0_CTRLA) Prescaler Mask */ 51 #define RTC_MODE0_CTRLA_PRESCALER(value) (RTC_MODE0_CTRLA_PRESCALER_Msk & (_UINT16_(value) << RTC_MODE0_CTRLA_PRESCALER_Pos)) /* Assignment of value for PRESCALER in the RTC_MODE0_CTRLA register */ 52 #define RTC_MODE0_CTRLA_PRESCALER_OFF_Val _UINT16_(0x0) /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */ 53 #define RTC_MODE0_CTRLA_PRESCALER_DIV1_Val _UINT16_(0x1) /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */ 54 #define RTC_MODE0_CTRLA_PRESCALER_DIV2_Val _UINT16_(0x2) /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/2 */ 55 #define RTC_MODE0_CTRLA_PRESCALER_DIV4_Val _UINT16_(0x3) /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/4 */ 56 #define RTC_MODE0_CTRLA_PRESCALER_DIV8_Val _UINT16_(0x4) /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/8 */ 57 #define RTC_MODE0_CTRLA_PRESCALER_DIV16_Val _UINT16_(0x5) /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/16 */ 58 #define RTC_MODE0_CTRLA_PRESCALER_DIV32_Val _UINT16_(0x6) /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/32 */ 59 #define RTC_MODE0_CTRLA_PRESCALER_DIV64_Val _UINT16_(0x7) /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/64 */ 60 #define RTC_MODE0_CTRLA_PRESCALER_DIV128_Val _UINT16_(0x8) /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/128 */ 61 #define RTC_MODE0_CTRLA_PRESCALER_DIV256_Val _UINT16_(0x9) /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/256 */ 62 #define RTC_MODE0_CTRLA_PRESCALER_DIV512_Val _UINT16_(0xA) /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/512 */ 63 #define RTC_MODE0_CTRLA_PRESCALER_DIV1024_Val _UINT16_(0xB) /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024 */ 64 #define RTC_MODE0_CTRLA_PRESCALER_OFF (RTC_MODE0_CTRLA_PRESCALER_OFF_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 Position */ 65 #define RTC_MODE0_CTRLA_PRESCALER_DIV1 (RTC_MODE0_CTRLA_PRESCALER_DIV1_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 Position */ 66 #define RTC_MODE0_CTRLA_PRESCALER_DIV2 (RTC_MODE0_CTRLA_PRESCALER_DIV2_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/2 Position */ 67 #define RTC_MODE0_CTRLA_PRESCALER_DIV4 (RTC_MODE0_CTRLA_PRESCALER_DIV4_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/4 Position */ 68 #define RTC_MODE0_CTRLA_PRESCALER_DIV8 (RTC_MODE0_CTRLA_PRESCALER_DIV8_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/8 Position */ 69 #define RTC_MODE0_CTRLA_PRESCALER_DIV16 (RTC_MODE0_CTRLA_PRESCALER_DIV16_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/16 Position */ 70 #define RTC_MODE0_CTRLA_PRESCALER_DIV32 (RTC_MODE0_CTRLA_PRESCALER_DIV32_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/32 Position */ 71 #define RTC_MODE0_CTRLA_PRESCALER_DIV64 (RTC_MODE0_CTRLA_PRESCALER_DIV64_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/64 Position */ 72 #define RTC_MODE0_CTRLA_PRESCALER_DIV128 (RTC_MODE0_CTRLA_PRESCALER_DIV128_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/128 Position */ 73 #define RTC_MODE0_CTRLA_PRESCALER_DIV256 (RTC_MODE0_CTRLA_PRESCALER_DIV256_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/256 Position */ 74 #define RTC_MODE0_CTRLA_PRESCALER_DIV512 (RTC_MODE0_CTRLA_PRESCALER_DIV512_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/512 Position */ 75 #define RTC_MODE0_CTRLA_PRESCALER_DIV1024 (RTC_MODE0_CTRLA_PRESCALER_DIV1024_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024 Position */ 76 #define RTC_MODE0_CTRLA_BKTRST_Pos _UINT16_(13) /* (RTC_MODE0_CTRLA) BKUP Registers Reset On Tamper Enable Position */ 77 #define RTC_MODE0_CTRLA_BKTRST_Msk (_UINT16_(0x1) << RTC_MODE0_CTRLA_BKTRST_Pos) /* (RTC_MODE0_CTRLA) BKUP Registers Reset On Tamper Enable Mask */ 78 #define RTC_MODE0_CTRLA_BKTRST(value) (RTC_MODE0_CTRLA_BKTRST_Msk & (_UINT16_(value) << RTC_MODE0_CTRLA_BKTRST_Pos)) /* Assignment of value for BKTRST in the RTC_MODE0_CTRLA register */ 79 #define RTC_MODE0_CTRLA_COUNTSYNC_Pos _UINT16_(15) /* (RTC_MODE0_CTRLA) Count Read Synchronization Enable Position */ 80 #define RTC_MODE0_CTRLA_COUNTSYNC_Msk (_UINT16_(0x1) << RTC_MODE0_CTRLA_COUNTSYNC_Pos) /* (RTC_MODE0_CTRLA) Count Read Synchronization Enable Mask */ 81 #define RTC_MODE0_CTRLA_COUNTSYNC(value) (RTC_MODE0_CTRLA_COUNTSYNC_Msk & (_UINT16_(value) << RTC_MODE0_CTRLA_COUNTSYNC_Pos)) /* Assignment of value for COUNTSYNC in the RTC_MODE0_CTRLA register */ 82 #define RTC_MODE0_CTRLA_Msk _UINT16_(0xAF8F) /* (RTC_MODE0_CTRLA) Register Mask */ 83 84 85 /* -------- RTC_MODE1_CTRLA : (RTC Offset: 0x00) (R/W 16) MODE1 Control A -------- */ 86 #define RTC_MODE1_CTRLA_RESETVALUE _UINT16_(0x00) /* (RTC_MODE1_CTRLA) MODE1 Control A Reset Value */ 87 88 #define RTC_MODE1_CTRLA_SWRST_Pos _UINT16_(0) /* (RTC_MODE1_CTRLA) Software Reset Position */ 89 #define RTC_MODE1_CTRLA_SWRST_Msk (_UINT16_(0x1) << RTC_MODE1_CTRLA_SWRST_Pos) /* (RTC_MODE1_CTRLA) Software Reset Mask */ 90 #define RTC_MODE1_CTRLA_SWRST(value) (RTC_MODE1_CTRLA_SWRST_Msk & (_UINT16_(value) << RTC_MODE1_CTRLA_SWRST_Pos)) /* Assignment of value for SWRST in the RTC_MODE1_CTRLA register */ 91 #define RTC_MODE1_CTRLA_ENABLE_Pos _UINT16_(1) /* (RTC_MODE1_CTRLA) Enable Position */ 92 #define RTC_MODE1_CTRLA_ENABLE_Msk (_UINT16_(0x1) << RTC_MODE1_CTRLA_ENABLE_Pos) /* (RTC_MODE1_CTRLA) Enable Mask */ 93 #define RTC_MODE1_CTRLA_ENABLE(value) (RTC_MODE1_CTRLA_ENABLE_Msk & (_UINT16_(value) << RTC_MODE1_CTRLA_ENABLE_Pos)) /* Assignment of value for ENABLE in the RTC_MODE1_CTRLA register */ 94 #define RTC_MODE1_CTRLA_MODE_Pos _UINT16_(2) /* (RTC_MODE1_CTRLA) Operating Mode Position */ 95 #define RTC_MODE1_CTRLA_MODE_Msk (_UINT16_(0x3) << RTC_MODE1_CTRLA_MODE_Pos) /* (RTC_MODE1_CTRLA) Operating Mode Mask */ 96 #define RTC_MODE1_CTRLA_MODE(value) (RTC_MODE1_CTRLA_MODE_Msk & (_UINT16_(value) << RTC_MODE1_CTRLA_MODE_Pos)) /* Assignment of value for MODE in the RTC_MODE1_CTRLA register */ 97 #define RTC_MODE1_CTRLA_MODE_COUNT32_Val _UINT16_(0x0) /* (RTC_MODE1_CTRLA) Mode 0: 32-bit Counter */ 98 #define RTC_MODE1_CTRLA_MODE_COUNT16_Val _UINT16_(0x1) /* (RTC_MODE1_CTRLA) Mode 1: 16-bit Counter */ 99 #define RTC_MODE1_CTRLA_MODE_CLOCK_Val _UINT16_(0x2) /* (RTC_MODE1_CTRLA) Mode 2: Clock/Calendar */ 100 #define RTC_MODE1_CTRLA_MODE_COUNT32 (RTC_MODE1_CTRLA_MODE_COUNT32_Val << RTC_MODE1_CTRLA_MODE_Pos) /* (RTC_MODE1_CTRLA) Mode 0: 32-bit Counter Position */ 101 #define RTC_MODE1_CTRLA_MODE_COUNT16 (RTC_MODE1_CTRLA_MODE_COUNT16_Val << RTC_MODE1_CTRLA_MODE_Pos) /* (RTC_MODE1_CTRLA) Mode 1: 16-bit Counter Position */ 102 #define RTC_MODE1_CTRLA_MODE_CLOCK (RTC_MODE1_CTRLA_MODE_CLOCK_Val << RTC_MODE1_CTRLA_MODE_Pos) /* (RTC_MODE1_CTRLA) Mode 2: Clock/Calendar Position */ 103 #define RTC_MODE1_CTRLA_PRESCALER_Pos _UINT16_(8) /* (RTC_MODE1_CTRLA) Prescaler Position */ 104 #define RTC_MODE1_CTRLA_PRESCALER_Msk (_UINT16_(0xF) << RTC_MODE1_CTRLA_PRESCALER_Pos) /* (RTC_MODE1_CTRLA) Prescaler Mask */ 105 #define RTC_MODE1_CTRLA_PRESCALER(value) (RTC_MODE1_CTRLA_PRESCALER_Msk & (_UINT16_(value) << RTC_MODE1_CTRLA_PRESCALER_Pos)) /* Assignment of value for PRESCALER in the RTC_MODE1_CTRLA register */ 106 #define RTC_MODE1_CTRLA_PRESCALER_OFF_Val _UINT16_(0x0) /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */ 107 #define RTC_MODE1_CTRLA_PRESCALER_DIV1_Val _UINT16_(0x1) /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */ 108 #define RTC_MODE1_CTRLA_PRESCALER_DIV2_Val _UINT16_(0x2) /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/2 */ 109 #define RTC_MODE1_CTRLA_PRESCALER_DIV4_Val _UINT16_(0x3) /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/4 */ 110 #define RTC_MODE1_CTRLA_PRESCALER_DIV8_Val _UINT16_(0x4) /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/8 */ 111 #define RTC_MODE1_CTRLA_PRESCALER_DIV16_Val _UINT16_(0x5) /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/16 */ 112 #define RTC_MODE1_CTRLA_PRESCALER_DIV32_Val _UINT16_(0x6) /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/32 */ 113 #define RTC_MODE1_CTRLA_PRESCALER_DIV64_Val _UINT16_(0x7) /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/64 */ 114 #define RTC_MODE1_CTRLA_PRESCALER_DIV128_Val _UINT16_(0x8) /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/128 */ 115 #define RTC_MODE1_CTRLA_PRESCALER_DIV256_Val _UINT16_(0x9) /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/256 */ 116 #define RTC_MODE1_CTRLA_PRESCALER_DIV512_Val _UINT16_(0xA) /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/512 */ 117 #define RTC_MODE1_CTRLA_PRESCALER_DIV1024_Val _UINT16_(0xB) /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024 */ 118 #define RTC_MODE1_CTRLA_PRESCALER_OFF (RTC_MODE1_CTRLA_PRESCALER_OFF_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 Position */ 119 #define RTC_MODE1_CTRLA_PRESCALER_DIV1 (RTC_MODE1_CTRLA_PRESCALER_DIV1_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 Position */ 120 #define RTC_MODE1_CTRLA_PRESCALER_DIV2 (RTC_MODE1_CTRLA_PRESCALER_DIV2_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/2 Position */ 121 #define RTC_MODE1_CTRLA_PRESCALER_DIV4 (RTC_MODE1_CTRLA_PRESCALER_DIV4_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/4 Position */ 122 #define RTC_MODE1_CTRLA_PRESCALER_DIV8 (RTC_MODE1_CTRLA_PRESCALER_DIV8_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/8 Position */ 123 #define RTC_MODE1_CTRLA_PRESCALER_DIV16 (RTC_MODE1_CTRLA_PRESCALER_DIV16_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/16 Position */ 124 #define RTC_MODE1_CTRLA_PRESCALER_DIV32 (RTC_MODE1_CTRLA_PRESCALER_DIV32_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/32 Position */ 125 #define RTC_MODE1_CTRLA_PRESCALER_DIV64 (RTC_MODE1_CTRLA_PRESCALER_DIV64_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/64 Position */ 126 #define RTC_MODE1_CTRLA_PRESCALER_DIV128 (RTC_MODE1_CTRLA_PRESCALER_DIV128_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/128 Position */ 127 #define RTC_MODE1_CTRLA_PRESCALER_DIV256 (RTC_MODE1_CTRLA_PRESCALER_DIV256_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/256 Position */ 128 #define RTC_MODE1_CTRLA_PRESCALER_DIV512 (RTC_MODE1_CTRLA_PRESCALER_DIV512_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/512 Position */ 129 #define RTC_MODE1_CTRLA_PRESCALER_DIV1024 (RTC_MODE1_CTRLA_PRESCALER_DIV1024_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024 Position */ 130 #define RTC_MODE1_CTRLA_BKTRST_Pos _UINT16_(13) /* (RTC_MODE1_CTRLA) BKUP Registers Reset On Tamper Enable Position */ 131 #define RTC_MODE1_CTRLA_BKTRST_Msk (_UINT16_(0x1) << RTC_MODE1_CTRLA_BKTRST_Pos) /* (RTC_MODE1_CTRLA) BKUP Registers Reset On Tamper Enable Mask */ 132 #define RTC_MODE1_CTRLA_BKTRST(value) (RTC_MODE1_CTRLA_BKTRST_Msk & (_UINT16_(value) << RTC_MODE1_CTRLA_BKTRST_Pos)) /* Assignment of value for BKTRST in the RTC_MODE1_CTRLA register */ 133 #define RTC_MODE1_CTRLA_COUNTSYNC_Pos _UINT16_(15) /* (RTC_MODE1_CTRLA) Count Read Synchronization Enable Position */ 134 #define RTC_MODE1_CTRLA_COUNTSYNC_Msk (_UINT16_(0x1) << RTC_MODE1_CTRLA_COUNTSYNC_Pos) /* (RTC_MODE1_CTRLA) Count Read Synchronization Enable Mask */ 135 #define RTC_MODE1_CTRLA_COUNTSYNC(value) (RTC_MODE1_CTRLA_COUNTSYNC_Msk & (_UINT16_(value) << RTC_MODE1_CTRLA_COUNTSYNC_Pos)) /* Assignment of value for COUNTSYNC in the RTC_MODE1_CTRLA register */ 136 #define RTC_MODE1_CTRLA_Msk _UINT16_(0xAF0F) /* (RTC_MODE1_CTRLA) Register Mask */ 137 138 139 /* -------- RTC_MODE2_CTRLA : (RTC Offset: 0x00) (R/W 16) MODE2 Control A -------- */ 140 #define RTC_MODE2_CTRLA_RESETVALUE _UINT16_(0x00) /* (RTC_MODE2_CTRLA) MODE2 Control A Reset Value */ 141 142 #define RTC_MODE2_CTRLA_SWRST_Pos _UINT16_(0) /* (RTC_MODE2_CTRLA) Software Reset Position */ 143 #define RTC_MODE2_CTRLA_SWRST_Msk (_UINT16_(0x1) << RTC_MODE2_CTRLA_SWRST_Pos) /* (RTC_MODE2_CTRLA) Software Reset Mask */ 144 #define RTC_MODE2_CTRLA_SWRST(value) (RTC_MODE2_CTRLA_SWRST_Msk & (_UINT16_(value) << RTC_MODE2_CTRLA_SWRST_Pos)) /* Assignment of value for SWRST in the RTC_MODE2_CTRLA register */ 145 #define RTC_MODE2_CTRLA_ENABLE_Pos _UINT16_(1) /* (RTC_MODE2_CTRLA) Enable Position */ 146 #define RTC_MODE2_CTRLA_ENABLE_Msk (_UINT16_(0x1) << RTC_MODE2_CTRLA_ENABLE_Pos) /* (RTC_MODE2_CTRLA) Enable Mask */ 147 #define RTC_MODE2_CTRLA_ENABLE(value) (RTC_MODE2_CTRLA_ENABLE_Msk & (_UINT16_(value) << RTC_MODE2_CTRLA_ENABLE_Pos)) /* Assignment of value for ENABLE in the RTC_MODE2_CTRLA register */ 148 #define RTC_MODE2_CTRLA_MODE_Pos _UINT16_(2) /* (RTC_MODE2_CTRLA) Operating Mode Position */ 149 #define RTC_MODE2_CTRLA_MODE_Msk (_UINT16_(0x3) << RTC_MODE2_CTRLA_MODE_Pos) /* (RTC_MODE2_CTRLA) Operating Mode Mask */ 150 #define RTC_MODE2_CTRLA_MODE(value) (RTC_MODE2_CTRLA_MODE_Msk & (_UINT16_(value) << RTC_MODE2_CTRLA_MODE_Pos)) /* Assignment of value for MODE in the RTC_MODE2_CTRLA register */ 151 #define RTC_MODE2_CTRLA_MODE_COUNT32_Val _UINT16_(0x0) /* (RTC_MODE2_CTRLA) Mode 0: 32-bit Counter */ 152 #define RTC_MODE2_CTRLA_MODE_COUNT16_Val _UINT16_(0x1) /* (RTC_MODE2_CTRLA) Mode 1: 16-bit Counter */ 153 #define RTC_MODE2_CTRLA_MODE_CLOCK_Val _UINT16_(0x2) /* (RTC_MODE2_CTRLA) Mode 2: Clock/Calendar */ 154 #define RTC_MODE2_CTRLA_MODE_COUNT32 (RTC_MODE2_CTRLA_MODE_COUNT32_Val << RTC_MODE2_CTRLA_MODE_Pos) /* (RTC_MODE2_CTRLA) Mode 0: 32-bit Counter Position */ 155 #define RTC_MODE2_CTRLA_MODE_COUNT16 (RTC_MODE2_CTRLA_MODE_COUNT16_Val << RTC_MODE2_CTRLA_MODE_Pos) /* (RTC_MODE2_CTRLA) Mode 1: 16-bit Counter Position */ 156 #define RTC_MODE2_CTRLA_MODE_CLOCK (RTC_MODE2_CTRLA_MODE_CLOCK_Val << RTC_MODE2_CTRLA_MODE_Pos) /* (RTC_MODE2_CTRLA) Mode 2: Clock/Calendar Position */ 157 #define RTC_MODE2_CTRLA_CLKREP_Pos _UINT16_(6) /* (RTC_MODE2_CTRLA) Clock Representation Position */ 158 #define RTC_MODE2_CTRLA_CLKREP_Msk (_UINT16_(0x1) << RTC_MODE2_CTRLA_CLKREP_Pos) /* (RTC_MODE2_CTRLA) Clock Representation Mask */ 159 #define RTC_MODE2_CTRLA_CLKREP(value) (RTC_MODE2_CTRLA_CLKREP_Msk & (_UINT16_(value) << RTC_MODE2_CTRLA_CLKREP_Pos)) /* Assignment of value for CLKREP in the RTC_MODE2_CTRLA register */ 160 #define RTC_MODE2_CTRLA_MATCHCLR_Pos _UINT16_(7) /* (RTC_MODE2_CTRLA) Clear on Match Position */ 161 #define RTC_MODE2_CTRLA_MATCHCLR_Msk (_UINT16_(0x1) << RTC_MODE2_CTRLA_MATCHCLR_Pos) /* (RTC_MODE2_CTRLA) Clear on Match Mask */ 162 #define RTC_MODE2_CTRLA_MATCHCLR(value) (RTC_MODE2_CTRLA_MATCHCLR_Msk & (_UINT16_(value) << RTC_MODE2_CTRLA_MATCHCLR_Pos)) /* Assignment of value for MATCHCLR in the RTC_MODE2_CTRLA register */ 163 #define RTC_MODE2_CTRLA_PRESCALER_Pos _UINT16_(8) /* (RTC_MODE2_CTRLA) Prescaler Position */ 164 #define RTC_MODE2_CTRLA_PRESCALER_Msk (_UINT16_(0xF) << RTC_MODE2_CTRLA_PRESCALER_Pos) /* (RTC_MODE2_CTRLA) Prescaler Mask */ 165 #define RTC_MODE2_CTRLA_PRESCALER(value) (RTC_MODE2_CTRLA_PRESCALER_Msk & (_UINT16_(value) << RTC_MODE2_CTRLA_PRESCALER_Pos)) /* Assignment of value for PRESCALER in the RTC_MODE2_CTRLA register */ 166 #define RTC_MODE2_CTRLA_PRESCALER_OFF_Val _UINT16_(0x0) /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */ 167 #define RTC_MODE2_CTRLA_PRESCALER_DIV1_Val _UINT16_(0x1) /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */ 168 #define RTC_MODE2_CTRLA_PRESCALER_DIV2_Val _UINT16_(0x2) /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/2 */ 169 #define RTC_MODE2_CTRLA_PRESCALER_DIV4_Val _UINT16_(0x3) /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/4 */ 170 #define RTC_MODE2_CTRLA_PRESCALER_DIV8_Val _UINT16_(0x4) /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/8 */ 171 #define RTC_MODE2_CTRLA_PRESCALER_DIV16_Val _UINT16_(0x5) /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/16 */ 172 #define RTC_MODE2_CTRLA_PRESCALER_DIV32_Val _UINT16_(0x6) /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/32 */ 173 #define RTC_MODE2_CTRLA_PRESCALER_DIV64_Val _UINT16_(0x7) /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/64 */ 174 #define RTC_MODE2_CTRLA_PRESCALER_DIV128_Val _UINT16_(0x8) /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/128 */ 175 #define RTC_MODE2_CTRLA_PRESCALER_DIV256_Val _UINT16_(0x9) /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/256 */ 176 #define RTC_MODE2_CTRLA_PRESCALER_DIV512_Val _UINT16_(0xA) /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/512 */ 177 #define RTC_MODE2_CTRLA_PRESCALER_DIV1024_Val _UINT16_(0xB) /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024 */ 178 #define RTC_MODE2_CTRLA_PRESCALER_OFF (RTC_MODE2_CTRLA_PRESCALER_OFF_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 Position */ 179 #define RTC_MODE2_CTRLA_PRESCALER_DIV1 (RTC_MODE2_CTRLA_PRESCALER_DIV1_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 Position */ 180 #define RTC_MODE2_CTRLA_PRESCALER_DIV2 (RTC_MODE2_CTRLA_PRESCALER_DIV2_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/2 Position */ 181 #define RTC_MODE2_CTRLA_PRESCALER_DIV4 (RTC_MODE2_CTRLA_PRESCALER_DIV4_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/4 Position */ 182 #define RTC_MODE2_CTRLA_PRESCALER_DIV8 (RTC_MODE2_CTRLA_PRESCALER_DIV8_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/8 Position */ 183 #define RTC_MODE2_CTRLA_PRESCALER_DIV16 (RTC_MODE2_CTRLA_PRESCALER_DIV16_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/16 Position */ 184 #define RTC_MODE2_CTRLA_PRESCALER_DIV32 (RTC_MODE2_CTRLA_PRESCALER_DIV32_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/32 Position */ 185 #define RTC_MODE2_CTRLA_PRESCALER_DIV64 (RTC_MODE2_CTRLA_PRESCALER_DIV64_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/64 Position */ 186 #define RTC_MODE2_CTRLA_PRESCALER_DIV128 (RTC_MODE2_CTRLA_PRESCALER_DIV128_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/128 Position */ 187 #define RTC_MODE2_CTRLA_PRESCALER_DIV256 (RTC_MODE2_CTRLA_PRESCALER_DIV256_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/256 Position */ 188 #define RTC_MODE2_CTRLA_PRESCALER_DIV512 (RTC_MODE2_CTRLA_PRESCALER_DIV512_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/512 Position */ 189 #define RTC_MODE2_CTRLA_PRESCALER_DIV1024 (RTC_MODE2_CTRLA_PRESCALER_DIV1024_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024 Position */ 190 #define RTC_MODE2_CTRLA_BKTRST_Pos _UINT16_(13) /* (RTC_MODE2_CTRLA) BKUP Registers Reset On Tamper Enable Position */ 191 #define RTC_MODE2_CTRLA_BKTRST_Msk (_UINT16_(0x1) << RTC_MODE2_CTRLA_BKTRST_Pos) /* (RTC_MODE2_CTRLA) BKUP Registers Reset On Tamper Enable Mask */ 192 #define RTC_MODE2_CTRLA_BKTRST(value) (RTC_MODE2_CTRLA_BKTRST_Msk & (_UINT16_(value) << RTC_MODE2_CTRLA_BKTRST_Pos)) /* Assignment of value for BKTRST in the RTC_MODE2_CTRLA register */ 193 #define RTC_MODE2_CTRLA_CLOCKSYNC_Pos _UINT16_(15) /* (RTC_MODE2_CTRLA) Clock Read Synchronization Enable Position */ 194 #define RTC_MODE2_CTRLA_CLOCKSYNC_Msk (_UINT16_(0x1) << RTC_MODE2_CTRLA_CLOCKSYNC_Pos) /* (RTC_MODE2_CTRLA) Clock Read Synchronization Enable Mask */ 195 #define RTC_MODE2_CTRLA_CLOCKSYNC(value) (RTC_MODE2_CTRLA_CLOCKSYNC_Msk & (_UINT16_(value) << RTC_MODE2_CTRLA_CLOCKSYNC_Pos)) /* Assignment of value for CLOCKSYNC in the RTC_MODE2_CTRLA register */ 196 #define RTC_MODE2_CTRLA_Msk _UINT16_(0xAFCF) /* (RTC_MODE2_CTRLA) Register Mask */ 197 198 199 /* -------- RTC_MODE0_CTRLB : (RTC Offset: 0x02) (R/W 16) MODE0 Control B -------- */ 200 #define RTC_MODE0_CTRLB_RESETVALUE _UINT16_(0x00) /* (RTC_MODE0_CTRLB) MODE0 Control B Reset Value */ 201 202 #define RTC_MODE0_CTRLB_GP0EN_Pos _UINT16_(0) /* (RTC_MODE0_CTRLB) General Purpose 0 Enable Position */ 203 #define RTC_MODE0_CTRLB_GP0EN_Msk (_UINT16_(0x1) << RTC_MODE0_CTRLB_GP0EN_Pos) /* (RTC_MODE0_CTRLB) General Purpose 0 Enable Mask */ 204 #define RTC_MODE0_CTRLB_GP0EN(value) (RTC_MODE0_CTRLB_GP0EN_Msk & (_UINT16_(value) << RTC_MODE0_CTRLB_GP0EN_Pos)) /* Assignment of value for GP0EN in the RTC_MODE0_CTRLB register */ 205 #define RTC_MODE0_CTRLB_GP2EN_Pos _UINT16_(1) /* (RTC_MODE0_CTRLB) General Purpose 2 Enable Position */ 206 #define RTC_MODE0_CTRLB_GP2EN_Msk (_UINT16_(0x1) << RTC_MODE0_CTRLB_GP2EN_Pos) /* (RTC_MODE0_CTRLB) General Purpose 2 Enable Mask */ 207 #define RTC_MODE0_CTRLB_GP2EN(value) (RTC_MODE0_CTRLB_GP2EN_Msk & (_UINT16_(value) << RTC_MODE0_CTRLB_GP2EN_Pos)) /* Assignment of value for GP2EN in the RTC_MODE0_CTRLB register */ 208 #define RTC_MODE0_CTRLB_DEBASYNC_Pos _UINT16_(5) /* (RTC_MODE0_CTRLB) Debouncer Asynchronous Enable Position */ 209 #define RTC_MODE0_CTRLB_DEBASYNC_Msk (_UINT16_(0x1) << RTC_MODE0_CTRLB_DEBASYNC_Pos) /* (RTC_MODE0_CTRLB) Debouncer Asynchronous Enable Mask */ 210 #define RTC_MODE0_CTRLB_DEBASYNC(value) (RTC_MODE0_CTRLB_DEBASYNC_Msk & (_UINT16_(value) << RTC_MODE0_CTRLB_DEBASYNC_Pos)) /* Assignment of value for DEBASYNC in the RTC_MODE0_CTRLB register */ 211 #define RTC_MODE0_CTRLB_RTCOUT_Pos _UINT16_(6) /* (RTC_MODE0_CTRLB) RTC Output Enable Position */ 212 #define RTC_MODE0_CTRLB_RTCOUT_Msk (_UINT16_(0x1) << RTC_MODE0_CTRLB_RTCOUT_Pos) /* (RTC_MODE0_CTRLB) RTC Output Enable Mask */ 213 #define RTC_MODE0_CTRLB_RTCOUT(value) (RTC_MODE0_CTRLB_RTCOUT_Msk & (_UINT16_(value) << RTC_MODE0_CTRLB_RTCOUT_Pos)) /* Assignment of value for RTCOUT in the RTC_MODE0_CTRLB register */ 214 #define RTC_MODE0_CTRLB_DMAEN_Pos _UINT16_(7) /* (RTC_MODE0_CTRLB) DMA Enable Position */ 215 #define RTC_MODE0_CTRLB_DMAEN_Msk (_UINT16_(0x1) << RTC_MODE0_CTRLB_DMAEN_Pos) /* (RTC_MODE0_CTRLB) DMA Enable Mask */ 216 #define RTC_MODE0_CTRLB_DMAEN(value) (RTC_MODE0_CTRLB_DMAEN_Msk & (_UINT16_(value) << RTC_MODE0_CTRLB_DMAEN_Pos)) /* Assignment of value for DMAEN in the RTC_MODE0_CTRLB register */ 217 #define RTC_MODE0_CTRLB_DEBF_Pos _UINT16_(8) /* (RTC_MODE0_CTRLB) Debounce Freqnuency Position */ 218 #define RTC_MODE0_CTRLB_DEBF_Msk (_UINT16_(0x7) << RTC_MODE0_CTRLB_DEBF_Pos) /* (RTC_MODE0_CTRLB) Debounce Freqnuency Mask */ 219 #define RTC_MODE0_CTRLB_DEBF(value) (RTC_MODE0_CTRLB_DEBF_Msk & (_UINT16_(value) << RTC_MODE0_CTRLB_DEBF_Pos)) /* Assignment of value for DEBF in the RTC_MODE0_CTRLB register */ 220 #define RTC_MODE0_CTRLB_DEBF_DIV2_Val _UINT16_(0x0) /* (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/2 */ 221 #define RTC_MODE0_CTRLB_DEBF_DIV4_Val _UINT16_(0x1) /* (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/4 */ 222 #define RTC_MODE0_CTRLB_DEBF_DIV8_Val _UINT16_(0x2) /* (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/8 */ 223 #define RTC_MODE0_CTRLB_DEBF_DIV16_Val _UINT16_(0x3) /* (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/16 */ 224 #define RTC_MODE0_CTRLB_DEBF_DIV32_Val _UINT16_(0x4) /* (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/32 */ 225 #define RTC_MODE0_CTRLB_DEBF_DIV64_Val _UINT16_(0x5) /* (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/64 */ 226 #define RTC_MODE0_CTRLB_DEBF_DIV128_Val _UINT16_(0x6) /* (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/128 */ 227 #define RTC_MODE0_CTRLB_DEBF_DIV256_Val _UINT16_(0x7) /* (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/256 */ 228 #define RTC_MODE0_CTRLB_DEBF_DIV2 (RTC_MODE0_CTRLB_DEBF_DIV2_Val << RTC_MODE0_CTRLB_DEBF_Pos) /* (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/2 Position */ 229 #define RTC_MODE0_CTRLB_DEBF_DIV4 (RTC_MODE0_CTRLB_DEBF_DIV4_Val << RTC_MODE0_CTRLB_DEBF_Pos) /* (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/4 Position */ 230 #define RTC_MODE0_CTRLB_DEBF_DIV8 (RTC_MODE0_CTRLB_DEBF_DIV8_Val << RTC_MODE0_CTRLB_DEBF_Pos) /* (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/8 Position */ 231 #define RTC_MODE0_CTRLB_DEBF_DIV16 (RTC_MODE0_CTRLB_DEBF_DIV16_Val << RTC_MODE0_CTRLB_DEBF_Pos) /* (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/16 Position */ 232 #define RTC_MODE0_CTRLB_DEBF_DIV32 (RTC_MODE0_CTRLB_DEBF_DIV32_Val << RTC_MODE0_CTRLB_DEBF_Pos) /* (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/32 Position */ 233 #define RTC_MODE0_CTRLB_DEBF_DIV64 (RTC_MODE0_CTRLB_DEBF_DIV64_Val << RTC_MODE0_CTRLB_DEBF_Pos) /* (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/64 Position */ 234 #define RTC_MODE0_CTRLB_DEBF_DIV128 (RTC_MODE0_CTRLB_DEBF_DIV128_Val << RTC_MODE0_CTRLB_DEBF_Pos) /* (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/128 Position */ 235 #define RTC_MODE0_CTRLB_DEBF_DIV256 (RTC_MODE0_CTRLB_DEBF_DIV256_Val << RTC_MODE0_CTRLB_DEBF_Pos) /* (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/256 Position */ 236 #define RTC_MODE0_CTRLB_ACTF_Pos _UINT16_(12) /* (RTC_MODE0_CTRLB) Active Layer Freqnuency Position */ 237 #define RTC_MODE0_CTRLB_ACTF_Msk (_UINT16_(0x7) << RTC_MODE0_CTRLB_ACTF_Pos) /* (RTC_MODE0_CTRLB) Active Layer Freqnuency Mask */ 238 #define RTC_MODE0_CTRLB_ACTF(value) (RTC_MODE0_CTRLB_ACTF_Msk & (_UINT16_(value) << RTC_MODE0_CTRLB_ACTF_Pos)) /* Assignment of value for ACTF in the RTC_MODE0_CTRLB register */ 239 #define RTC_MODE0_CTRLB_ACTF_DIV2_Val _UINT16_(0x0) /* (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/2 */ 240 #define RTC_MODE0_CTRLB_ACTF_DIV4_Val _UINT16_(0x1) /* (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/4 */ 241 #define RTC_MODE0_CTRLB_ACTF_DIV8_Val _UINT16_(0x2) /* (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/8 */ 242 #define RTC_MODE0_CTRLB_ACTF_DIV16_Val _UINT16_(0x3) /* (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/16 */ 243 #define RTC_MODE0_CTRLB_ACTF_DIV32_Val _UINT16_(0x4) /* (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/32 */ 244 #define RTC_MODE0_CTRLB_ACTF_DIV64_Val _UINT16_(0x5) /* (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/64 */ 245 #define RTC_MODE0_CTRLB_ACTF_DIV128_Val _UINT16_(0x6) /* (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/128 */ 246 #define RTC_MODE0_CTRLB_ACTF_DIV256_Val _UINT16_(0x7) /* (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/256 */ 247 #define RTC_MODE0_CTRLB_ACTF_DIV2 (RTC_MODE0_CTRLB_ACTF_DIV2_Val << RTC_MODE0_CTRLB_ACTF_Pos) /* (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/2 Position */ 248 #define RTC_MODE0_CTRLB_ACTF_DIV4 (RTC_MODE0_CTRLB_ACTF_DIV4_Val << RTC_MODE0_CTRLB_ACTF_Pos) /* (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/4 Position */ 249 #define RTC_MODE0_CTRLB_ACTF_DIV8 (RTC_MODE0_CTRLB_ACTF_DIV8_Val << RTC_MODE0_CTRLB_ACTF_Pos) /* (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/8 Position */ 250 #define RTC_MODE0_CTRLB_ACTF_DIV16 (RTC_MODE0_CTRLB_ACTF_DIV16_Val << RTC_MODE0_CTRLB_ACTF_Pos) /* (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/16 Position */ 251 #define RTC_MODE0_CTRLB_ACTF_DIV32 (RTC_MODE0_CTRLB_ACTF_DIV32_Val << RTC_MODE0_CTRLB_ACTF_Pos) /* (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/32 Position */ 252 #define RTC_MODE0_CTRLB_ACTF_DIV64 (RTC_MODE0_CTRLB_ACTF_DIV64_Val << RTC_MODE0_CTRLB_ACTF_Pos) /* (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/64 Position */ 253 #define RTC_MODE0_CTRLB_ACTF_DIV128 (RTC_MODE0_CTRLB_ACTF_DIV128_Val << RTC_MODE0_CTRLB_ACTF_Pos) /* (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/128 Position */ 254 #define RTC_MODE0_CTRLB_ACTF_DIV256 (RTC_MODE0_CTRLB_ACTF_DIV256_Val << RTC_MODE0_CTRLB_ACTF_Pos) /* (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/256 Position */ 255 #define RTC_MODE0_CTRLB_Msk _UINT16_(0x77E3) /* (RTC_MODE0_CTRLB) Register Mask */ 256 257 258 /* -------- RTC_MODE1_CTRLB : (RTC Offset: 0x02) (R/W 16) MODE1 Control B -------- */ 259 #define RTC_MODE1_CTRLB_RESETVALUE _UINT16_(0x00) /* (RTC_MODE1_CTRLB) MODE1 Control B Reset Value */ 260 261 #define RTC_MODE1_CTRLB_GP0EN_Pos _UINT16_(0) /* (RTC_MODE1_CTRLB) General Purpose 0 Enable Position */ 262 #define RTC_MODE1_CTRLB_GP0EN_Msk (_UINT16_(0x1) << RTC_MODE1_CTRLB_GP0EN_Pos) /* (RTC_MODE1_CTRLB) General Purpose 0 Enable Mask */ 263 #define RTC_MODE1_CTRLB_GP0EN(value) (RTC_MODE1_CTRLB_GP0EN_Msk & (_UINT16_(value) << RTC_MODE1_CTRLB_GP0EN_Pos)) /* Assignment of value for GP0EN in the RTC_MODE1_CTRLB register */ 264 #define RTC_MODE1_CTRLB_GP2EN_Pos _UINT16_(1) /* (RTC_MODE1_CTRLB) General Purpose 2 Enable Position */ 265 #define RTC_MODE1_CTRLB_GP2EN_Msk (_UINT16_(0x1) << RTC_MODE1_CTRLB_GP2EN_Pos) /* (RTC_MODE1_CTRLB) General Purpose 2 Enable Mask */ 266 #define RTC_MODE1_CTRLB_GP2EN(value) (RTC_MODE1_CTRLB_GP2EN_Msk & (_UINT16_(value) << RTC_MODE1_CTRLB_GP2EN_Pos)) /* Assignment of value for GP2EN in the RTC_MODE1_CTRLB register */ 267 #define RTC_MODE1_CTRLB_DEBASYNC_Pos _UINT16_(5) /* (RTC_MODE1_CTRLB) Debouncer Asynchronous Enable Position */ 268 #define RTC_MODE1_CTRLB_DEBASYNC_Msk (_UINT16_(0x1) << RTC_MODE1_CTRLB_DEBASYNC_Pos) /* (RTC_MODE1_CTRLB) Debouncer Asynchronous Enable Mask */ 269 #define RTC_MODE1_CTRLB_DEBASYNC(value) (RTC_MODE1_CTRLB_DEBASYNC_Msk & (_UINT16_(value) << RTC_MODE1_CTRLB_DEBASYNC_Pos)) /* Assignment of value for DEBASYNC in the RTC_MODE1_CTRLB register */ 270 #define RTC_MODE1_CTRLB_RTCOUT_Pos _UINT16_(6) /* (RTC_MODE1_CTRLB) RTC Output Enable Position */ 271 #define RTC_MODE1_CTRLB_RTCOUT_Msk (_UINT16_(0x1) << RTC_MODE1_CTRLB_RTCOUT_Pos) /* (RTC_MODE1_CTRLB) RTC Output Enable Mask */ 272 #define RTC_MODE1_CTRLB_RTCOUT(value) (RTC_MODE1_CTRLB_RTCOUT_Msk & (_UINT16_(value) << RTC_MODE1_CTRLB_RTCOUT_Pos)) /* Assignment of value for RTCOUT in the RTC_MODE1_CTRLB register */ 273 #define RTC_MODE1_CTRLB_DMAEN_Pos _UINT16_(7) /* (RTC_MODE1_CTRLB) DMA Enable Position */ 274 #define RTC_MODE1_CTRLB_DMAEN_Msk (_UINT16_(0x1) << RTC_MODE1_CTRLB_DMAEN_Pos) /* (RTC_MODE1_CTRLB) DMA Enable Mask */ 275 #define RTC_MODE1_CTRLB_DMAEN(value) (RTC_MODE1_CTRLB_DMAEN_Msk & (_UINT16_(value) << RTC_MODE1_CTRLB_DMAEN_Pos)) /* Assignment of value for DMAEN in the RTC_MODE1_CTRLB register */ 276 #define RTC_MODE1_CTRLB_DEBF_Pos _UINT16_(8) /* (RTC_MODE1_CTRLB) Debounce Freqnuency Position */ 277 #define RTC_MODE1_CTRLB_DEBF_Msk (_UINT16_(0x7) << RTC_MODE1_CTRLB_DEBF_Pos) /* (RTC_MODE1_CTRLB) Debounce Freqnuency Mask */ 278 #define RTC_MODE1_CTRLB_DEBF(value) (RTC_MODE1_CTRLB_DEBF_Msk & (_UINT16_(value) << RTC_MODE1_CTRLB_DEBF_Pos)) /* Assignment of value for DEBF in the RTC_MODE1_CTRLB register */ 279 #define RTC_MODE1_CTRLB_DEBF_DIV2_Val _UINT16_(0x0) /* (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/2 */ 280 #define RTC_MODE1_CTRLB_DEBF_DIV4_Val _UINT16_(0x1) /* (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/4 */ 281 #define RTC_MODE1_CTRLB_DEBF_DIV8_Val _UINT16_(0x2) /* (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/8 */ 282 #define RTC_MODE1_CTRLB_DEBF_DIV16_Val _UINT16_(0x3) /* (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/16 */ 283 #define RTC_MODE1_CTRLB_DEBF_DIV32_Val _UINT16_(0x4) /* (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/32 */ 284 #define RTC_MODE1_CTRLB_DEBF_DIV64_Val _UINT16_(0x5) /* (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/64 */ 285 #define RTC_MODE1_CTRLB_DEBF_DIV128_Val _UINT16_(0x6) /* (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/128 */ 286 #define RTC_MODE1_CTRLB_DEBF_DIV256_Val _UINT16_(0x7) /* (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/256 */ 287 #define RTC_MODE1_CTRLB_DEBF_DIV2 (RTC_MODE1_CTRLB_DEBF_DIV2_Val << RTC_MODE1_CTRLB_DEBF_Pos) /* (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/2 Position */ 288 #define RTC_MODE1_CTRLB_DEBF_DIV4 (RTC_MODE1_CTRLB_DEBF_DIV4_Val << RTC_MODE1_CTRLB_DEBF_Pos) /* (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/4 Position */ 289 #define RTC_MODE1_CTRLB_DEBF_DIV8 (RTC_MODE1_CTRLB_DEBF_DIV8_Val << RTC_MODE1_CTRLB_DEBF_Pos) /* (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/8 Position */ 290 #define RTC_MODE1_CTRLB_DEBF_DIV16 (RTC_MODE1_CTRLB_DEBF_DIV16_Val << RTC_MODE1_CTRLB_DEBF_Pos) /* (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/16 Position */ 291 #define RTC_MODE1_CTRLB_DEBF_DIV32 (RTC_MODE1_CTRLB_DEBF_DIV32_Val << RTC_MODE1_CTRLB_DEBF_Pos) /* (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/32 Position */ 292 #define RTC_MODE1_CTRLB_DEBF_DIV64 (RTC_MODE1_CTRLB_DEBF_DIV64_Val << RTC_MODE1_CTRLB_DEBF_Pos) /* (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/64 Position */ 293 #define RTC_MODE1_CTRLB_DEBF_DIV128 (RTC_MODE1_CTRLB_DEBF_DIV128_Val << RTC_MODE1_CTRLB_DEBF_Pos) /* (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/128 Position */ 294 #define RTC_MODE1_CTRLB_DEBF_DIV256 (RTC_MODE1_CTRLB_DEBF_DIV256_Val << RTC_MODE1_CTRLB_DEBF_Pos) /* (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/256 Position */ 295 #define RTC_MODE1_CTRLB_ACTF_Pos _UINT16_(12) /* (RTC_MODE1_CTRLB) Active Layer Freqnuency Position */ 296 #define RTC_MODE1_CTRLB_ACTF_Msk (_UINT16_(0x7) << RTC_MODE1_CTRLB_ACTF_Pos) /* (RTC_MODE1_CTRLB) Active Layer Freqnuency Mask */ 297 #define RTC_MODE1_CTRLB_ACTF(value) (RTC_MODE1_CTRLB_ACTF_Msk & (_UINT16_(value) << RTC_MODE1_CTRLB_ACTF_Pos)) /* Assignment of value for ACTF in the RTC_MODE1_CTRLB register */ 298 #define RTC_MODE1_CTRLB_ACTF_DIV2_Val _UINT16_(0x0) /* (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/2 */ 299 #define RTC_MODE1_CTRLB_ACTF_DIV4_Val _UINT16_(0x1) /* (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/4 */ 300 #define RTC_MODE1_CTRLB_ACTF_DIV8_Val _UINT16_(0x2) /* (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/8 */ 301 #define RTC_MODE1_CTRLB_ACTF_DIV16_Val _UINT16_(0x3) /* (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/16 */ 302 #define RTC_MODE1_CTRLB_ACTF_DIV32_Val _UINT16_(0x4) /* (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/32 */ 303 #define RTC_MODE1_CTRLB_ACTF_DIV64_Val _UINT16_(0x5) /* (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/64 */ 304 #define RTC_MODE1_CTRLB_ACTF_DIV128_Val _UINT16_(0x6) /* (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/128 */ 305 #define RTC_MODE1_CTRLB_ACTF_DIV256_Val _UINT16_(0x7) /* (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/256 */ 306 #define RTC_MODE1_CTRLB_ACTF_DIV2 (RTC_MODE1_CTRLB_ACTF_DIV2_Val << RTC_MODE1_CTRLB_ACTF_Pos) /* (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/2 Position */ 307 #define RTC_MODE1_CTRLB_ACTF_DIV4 (RTC_MODE1_CTRLB_ACTF_DIV4_Val << RTC_MODE1_CTRLB_ACTF_Pos) /* (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/4 Position */ 308 #define RTC_MODE1_CTRLB_ACTF_DIV8 (RTC_MODE1_CTRLB_ACTF_DIV8_Val << RTC_MODE1_CTRLB_ACTF_Pos) /* (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/8 Position */ 309 #define RTC_MODE1_CTRLB_ACTF_DIV16 (RTC_MODE1_CTRLB_ACTF_DIV16_Val << RTC_MODE1_CTRLB_ACTF_Pos) /* (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/16 Position */ 310 #define RTC_MODE1_CTRLB_ACTF_DIV32 (RTC_MODE1_CTRLB_ACTF_DIV32_Val << RTC_MODE1_CTRLB_ACTF_Pos) /* (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/32 Position */ 311 #define RTC_MODE1_CTRLB_ACTF_DIV64 (RTC_MODE1_CTRLB_ACTF_DIV64_Val << RTC_MODE1_CTRLB_ACTF_Pos) /* (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/64 Position */ 312 #define RTC_MODE1_CTRLB_ACTF_DIV128 (RTC_MODE1_CTRLB_ACTF_DIV128_Val << RTC_MODE1_CTRLB_ACTF_Pos) /* (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/128 Position */ 313 #define RTC_MODE1_CTRLB_ACTF_DIV256 (RTC_MODE1_CTRLB_ACTF_DIV256_Val << RTC_MODE1_CTRLB_ACTF_Pos) /* (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/256 Position */ 314 #define RTC_MODE1_CTRLB_Msk _UINT16_(0x77E3) /* (RTC_MODE1_CTRLB) Register Mask */ 315 316 317 /* -------- RTC_MODE2_CTRLB : (RTC Offset: 0x02) (R/W 16) MODE2 Control B -------- */ 318 #define RTC_MODE2_CTRLB_RESETVALUE _UINT16_(0x00) /* (RTC_MODE2_CTRLB) MODE2 Control B Reset Value */ 319 320 #define RTC_MODE2_CTRLB_GP0EN_Pos _UINT16_(0) /* (RTC_MODE2_CTRLB) General Purpose 0 Enable Position */ 321 #define RTC_MODE2_CTRLB_GP0EN_Msk (_UINT16_(0x1) << RTC_MODE2_CTRLB_GP0EN_Pos) /* (RTC_MODE2_CTRLB) General Purpose 0 Enable Mask */ 322 #define RTC_MODE2_CTRLB_GP0EN(value) (RTC_MODE2_CTRLB_GP0EN_Msk & (_UINT16_(value) << RTC_MODE2_CTRLB_GP0EN_Pos)) /* Assignment of value for GP0EN in the RTC_MODE2_CTRLB register */ 323 #define RTC_MODE2_CTRLB_GP2EN_Pos _UINT16_(1) /* (RTC_MODE2_CTRLB) General Purpose 2 Enable Position */ 324 #define RTC_MODE2_CTRLB_GP2EN_Msk (_UINT16_(0x1) << RTC_MODE2_CTRLB_GP2EN_Pos) /* (RTC_MODE2_CTRLB) General Purpose 2 Enable Mask */ 325 #define RTC_MODE2_CTRLB_GP2EN(value) (RTC_MODE2_CTRLB_GP2EN_Msk & (_UINT16_(value) << RTC_MODE2_CTRLB_GP2EN_Pos)) /* Assignment of value for GP2EN in the RTC_MODE2_CTRLB register */ 326 #define RTC_MODE2_CTRLB_DEBASYNC_Pos _UINT16_(5) /* (RTC_MODE2_CTRLB) Debouncer Asynchronous Enable Position */ 327 #define RTC_MODE2_CTRLB_DEBASYNC_Msk (_UINT16_(0x1) << RTC_MODE2_CTRLB_DEBASYNC_Pos) /* (RTC_MODE2_CTRLB) Debouncer Asynchronous Enable Mask */ 328 #define RTC_MODE2_CTRLB_DEBASYNC(value) (RTC_MODE2_CTRLB_DEBASYNC_Msk & (_UINT16_(value) << RTC_MODE2_CTRLB_DEBASYNC_Pos)) /* Assignment of value for DEBASYNC in the RTC_MODE2_CTRLB register */ 329 #define RTC_MODE2_CTRLB_RTCOUT_Pos _UINT16_(6) /* (RTC_MODE2_CTRLB) RTC Output Enable Position */ 330 #define RTC_MODE2_CTRLB_RTCOUT_Msk (_UINT16_(0x1) << RTC_MODE2_CTRLB_RTCOUT_Pos) /* (RTC_MODE2_CTRLB) RTC Output Enable Mask */ 331 #define RTC_MODE2_CTRLB_RTCOUT(value) (RTC_MODE2_CTRLB_RTCOUT_Msk & (_UINT16_(value) << RTC_MODE2_CTRLB_RTCOUT_Pos)) /* Assignment of value for RTCOUT in the RTC_MODE2_CTRLB register */ 332 #define RTC_MODE2_CTRLB_DMAEN_Pos _UINT16_(7) /* (RTC_MODE2_CTRLB) DMA Enable Position */ 333 #define RTC_MODE2_CTRLB_DMAEN_Msk (_UINT16_(0x1) << RTC_MODE2_CTRLB_DMAEN_Pos) /* (RTC_MODE2_CTRLB) DMA Enable Mask */ 334 #define RTC_MODE2_CTRLB_DMAEN(value) (RTC_MODE2_CTRLB_DMAEN_Msk & (_UINT16_(value) << RTC_MODE2_CTRLB_DMAEN_Pos)) /* Assignment of value for DMAEN in the RTC_MODE2_CTRLB register */ 335 #define RTC_MODE2_CTRLB_DEBF_Pos _UINT16_(8) /* (RTC_MODE2_CTRLB) Debounce Freqnuency Position */ 336 #define RTC_MODE2_CTRLB_DEBF_Msk (_UINT16_(0x7) << RTC_MODE2_CTRLB_DEBF_Pos) /* (RTC_MODE2_CTRLB) Debounce Freqnuency Mask */ 337 #define RTC_MODE2_CTRLB_DEBF(value) (RTC_MODE2_CTRLB_DEBF_Msk & (_UINT16_(value) << RTC_MODE2_CTRLB_DEBF_Pos)) /* Assignment of value for DEBF in the RTC_MODE2_CTRLB register */ 338 #define RTC_MODE2_CTRLB_DEBF_DIV2_Val _UINT16_(0x0) /* (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/2 */ 339 #define RTC_MODE2_CTRLB_DEBF_DIV4_Val _UINT16_(0x1) /* (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/4 */ 340 #define RTC_MODE2_CTRLB_DEBF_DIV8_Val _UINT16_(0x2) /* (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/8 */ 341 #define RTC_MODE2_CTRLB_DEBF_DIV16_Val _UINT16_(0x3) /* (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/16 */ 342 #define RTC_MODE2_CTRLB_DEBF_DIV32_Val _UINT16_(0x4) /* (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/32 */ 343 #define RTC_MODE2_CTRLB_DEBF_DIV64_Val _UINT16_(0x5) /* (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/64 */ 344 #define RTC_MODE2_CTRLB_DEBF_DIV128_Val _UINT16_(0x6) /* (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/128 */ 345 #define RTC_MODE2_CTRLB_DEBF_DIV256_Val _UINT16_(0x7) /* (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/256 */ 346 #define RTC_MODE2_CTRLB_DEBF_DIV2 (RTC_MODE2_CTRLB_DEBF_DIV2_Val << RTC_MODE2_CTRLB_DEBF_Pos) /* (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/2 Position */ 347 #define RTC_MODE2_CTRLB_DEBF_DIV4 (RTC_MODE2_CTRLB_DEBF_DIV4_Val << RTC_MODE2_CTRLB_DEBF_Pos) /* (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/4 Position */ 348 #define RTC_MODE2_CTRLB_DEBF_DIV8 (RTC_MODE2_CTRLB_DEBF_DIV8_Val << RTC_MODE2_CTRLB_DEBF_Pos) /* (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/8 Position */ 349 #define RTC_MODE2_CTRLB_DEBF_DIV16 (RTC_MODE2_CTRLB_DEBF_DIV16_Val << RTC_MODE2_CTRLB_DEBF_Pos) /* (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/16 Position */ 350 #define RTC_MODE2_CTRLB_DEBF_DIV32 (RTC_MODE2_CTRLB_DEBF_DIV32_Val << RTC_MODE2_CTRLB_DEBF_Pos) /* (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/32 Position */ 351 #define RTC_MODE2_CTRLB_DEBF_DIV64 (RTC_MODE2_CTRLB_DEBF_DIV64_Val << RTC_MODE2_CTRLB_DEBF_Pos) /* (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/64 Position */ 352 #define RTC_MODE2_CTRLB_DEBF_DIV128 (RTC_MODE2_CTRLB_DEBF_DIV128_Val << RTC_MODE2_CTRLB_DEBF_Pos) /* (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/128 Position */ 353 #define RTC_MODE2_CTRLB_DEBF_DIV256 (RTC_MODE2_CTRLB_DEBF_DIV256_Val << RTC_MODE2_CTRLB_DEBF_Pos) /* (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/256 Position */ 354 #define RTC_MODE2_CTRLB_ACTF_Pos _UINT16_(12) /* (RTC_MODE2_CTRLB) Active Layer Freqnuency Position */ 355 #define RTC_MODE2_CTRLB_ACTF_Msk (_UINT16_(0x7) << RTC_MODE2_CTRLB_ACTF_Pos) /* (RTC_MODE2_CTRLB) Active Layer Freqnuency Mask */ 356 #define RTC_MODE2_CTRLB_ACTF(value) (RTC_MODE2_CTRLB_ACTF_Msk & (_UINT16_(value) << RTC_MODE2_CTRLB_ACTF_Pos)) /* Assignment of value for ACTF in the RTC_MODE2_CTRLB register */ 357 #define RTC_MODE2_CTRLB_ACTF_DIV2_Val _UINT16_(0x0) /* (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/2 */ 358 #define RTC_MODE2_CTRLB_ACTF_DIV4_Val _UINT16_(0x1) /* (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/4 */ 359 #define RTC_MODE2_CTRLB_ACTF_DIV8_Val _UINT16_(0x2) /* (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/8 */ 360 #define RTC_MODE2_CTRLB_ACTF_DIV16_Val _UINT16_(0x3) /* (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/16 */ 361 #define RTC_MODE2_CTRLB_ACTF_DIV32_Val _UINT16_(0x4) /* (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/32 */ 362 #define RTC_MODE2_CTRLB_ACTF_DIV64_Val _UINT16_(0x5) /* (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/64 */ 363 #define RTC_MODE2_CTRLB_ACTF_DIV128_Val _UINT16_(0x6) /* (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/128 */ 364 #define RTC_MODE2_CTRLB_ACTF_DIV256_Val _UINT16_(0x7) /* (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/256 */ 365 #define RTC_MODE2_CTRLB_ACTF_DIV2 (RTC_MODE2_CTRLB_ACTF_DIV2_Val << RTC_MODE2_CTRLB_ACTF_Pos) /* (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/2 Position */ 366 #define RTC_MODE2_CTRLB_ACTF_DIV4 (RTC_MODE2_CTRLB_ACTF_DIV4_Val << RTC_MODE2_CTRLB_ACTF_Pos) /* (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/4 Position */ 367 #define RTC_MODE2_CTRLB_ACTF_DIV8 (RTC_MODE2_CTRLB_ACTF_DIV8_Val << RTC_MODE2_CTRLB_ACTF_Pos) /* (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/8 Position */ 368 #define RTC_MODE2_CTRLB_ACTF_DIV16 (RTC_MODE2_CTRLB_ACTF_DIV16_Val << RTC_MODE2_CTRLB_ACTF_Pos) /* (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/16 Position */ 369 #define RTC_MODE2_CTRLB_ACTF_DIV32 (RTC_MODE2_CTRLB_ACTF_DIV32_Val << RTC_MODE2_CTRLB_ACTF_Pos) /* (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/32 Position */ 370 #define RTC_MODE2_CTRLB_ACTF_DIV64 (RTC_MODE2_CTRLB_ACTF_DIV64_Val << RTC_MODE2_CTRLB_ACTF_Pos) /* (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/64 Position */ 371 #define RTC_MODE2_CTRLB_ACTF_DIV128 (RTC_MODE2_CTRLB_ACTF_DIV128_Val << RTC_MODE2_CTRLB_ACTF_Pos) /* (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/128 Position */ 372 #define RTC_MODE2_CTRLB_ACTF_DIV256 (RTC_MODE2_CTRLB_ACTF_DIV256_Val << RTC_MODE2_CTRLB_ACTF_Pos) /* (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/256 Position */ 373 #define RTC_MODE2_CTRLB_Msk _UINT16_(0x77E3) /* (RTC_MODE2_CTRLB) Register Mask */ 374 375 376 /* -------- RTC_MODE0_EVCTRL : (RTC Offset: 0x04) (R/W 32) MODE0 Event Control -------- */ 377 #define RTC_MODE0_EVCTRL_RESETVALUE _UINT32_(0x00) /* (RTC_MODE0_EVCTRL) MODE0 Event Control Reset Value */ 378 379 #define RTC_MODE0_EVCTRL_PEREO0_Pos _UINT32_(0) /* (RTC_MODE0_EVCTRL) Periodic Interval 0 Event Output Enable Position */ 380 #define RTC_MODE0_EVCTRL_PEREO0_Msk (_UINT32_(0x1) << RTC_MODE0_EVCTRL_PEREO0_Pos) /* (RTC_MODE0_EVCTRL) Periodic Interval 0 Event Output Enable Mask */ 381 #define RTC_MODE0_EVCTRL_PEREO0(value) (RTC_MODE0_EVCTRL_PEREO0_Msk & (_UINT32_(value) << RTC_MODE0_EVCTRL_PEREO0_Pos)) /* Assignment of value for PEREO0 in the RTC_MODE0_EVCTRL register */ 382 #define RTC_MODE0_EVCTRL_PEREO1_Pos _UINT32_(1) /* (RTC_MODE0_EVCTRL) Periodic Interval 1 Event Output Enable Position */ 383 #define RTC_MODE0_EVCTRL_PEREO1_Msk (_UINT32_(0x1) << RTC_MODE0_EVCTRL_PEREO1_Pos) /* (RTC_MODE0_EVCTRL) Periodic Interval 1 Event Output Enable Mask */ 384 #define RTC_MODE0_EVCTRL_PEREO1(value) (RTC_MODE0_EVCTRL_PEREO1_Msk & (_UINT32_(value) << RTC_MODE0_EVCTRL_PEREO1_Pos)) /* Assignment of value for PEREO1 in the RTC_MODE0_EVCTRL register */ 385 #define RTC_MODE0_EVCTRL_PEREO2_Pos _UINT32_(2) /* (RTC_MODE0_EVCTRL) Periodic Interval 2 Event Output Enable Position */ 386 #define RTC_MODE0_EVCTRL_PEREO2_Msk (_UINT32_(0x1) << RTC_MODE0_EVCTRL_PEREO2_Pos) /* (RTC_MODE0_EVCTRL) Periodic Interval 2 Event Output Enable Mask */ 387 #define RTC_MODE0_EVCTRL_PEREO2(value) (RTC_MODE0_EVCTRL_PEREO2_Msk & (_UINT32_(value) << RTC_MODE0_EVCTRL_PEREO2_Pos)) /* Assignment of value for PEREO2 in the RTC_MODE0_EVCTRL register */ 388 #define RTC_MODE0_EVCTRL_PEREO3_Pos _UINT32_(3) /* (RTC_MODE0_EVCTRL) Periodic Interval 3 Event Output Enable Position */ 389 #define RTC_MODE0_EVCTRL_PEREO3_Msk (_UINT32_(0x1) << RTC_MODE0_EVCTRL_PEREO3_Pos) /* (RTC_MODE0_EVCTRL) Periodic Interval 3 Event Output Enable Mask */ 390 #define RTC_MODE0_EVCTRL_PEREO3(value) (RTC_MODE0_EVCTRL_PEREO3_Msk & (_UINT32_(value) << RTC_MODE0_EVCTRL_PEREO3_Pos)) /* Assignment of value for PEREO3 in the RTC_MODE0_EVCTRL register */ 391 #define RTC_MODE0_EVCTRL_PEREO4_Pos _UINT32_(4) /* (RTC_MODE0_EVCTRL) Periodic Interval 4 Event Output Enable Position */ 392 #define RTC_MODE0_EVCTRL_PEREO4_Msk (_UINT32_(0x1) << RTC_MODE0_EVCTRL_PEREO4_Pos) /* (RTC_MODE0_EVCTRL) Periodic Interval 4 Event Output Enable Mask */ 393 #define RTC_MODE0_EVCTRL_PEREO4(value) (RTC_MODE0_EVCTRL_PEREO4_Msk & (_UINT32_(value) << RTC_MODE0_EVCTRL_PEREO4_Pos)) /* Assignment of value for PEREO4 in the RTC_MODE0_EVCTRL register */ 394 #define RTC_MODE0_EVCTRL_PEREO5_Pos _UINT32_(5) /* (RTC_MODE0_EVCTRL) Periodic Interval 5 Event Output Enable Position */ 395 #define RTC_MODE0_EVCTRL_PEREO5_Msk (_UINT32_(0x1) << RTC_MODE0_EVCTRL_PEREO5_Pos) /* (RTC_MODE0_EVCTRL) Periodic Interval 5 Event Output Enable Mask */ 396 #define RTC_MODE0_EVCTRL_PEREO5(value) (RTC_MODE0_EVCTRL_PEREO5_Msk & (_UINT32_(value) << RTC_MODE0_EVCTRL_PEREO5_Pos)) /* Assignment of value for PEREO5 in the RTC_MODE0_EVCTRL register */ 397 #define RTC_MODE0_EVCTRL_PEREO6_Pos _UINT32_(6) /* (RTC_MODE0_EVCTRL) Periodic Interval 6 Event Output Enable Position */ 398 #define RTC_MODE0_EVCTRL_PEREO6_Msk (_UINT32_(0x1) << RTC_MODE0_EVCTRL_PEREO6_Pos) /* (RTC_MODE0_EVCTRL) Periodic Interval 6 Event Output Enable Mask */ 399 #define RTC_MODE0_EVCTRL_PEREO6(value) (RTC_MODE0_EVCTRL_PEREO6_Msk & (_UINT32_(value) << RTC_MODE0_EVCTRL_PEREO6_Pos)) /* Assignment of value for PEREO6 in the RTC_MODE0_EVCTRL register */ 400 #define RTC_MODE0_EVCTRL_PEREO7_Pos _UINT32_(7) /* (RTC_MODE0_EVCTRL) Periodic Interval 7 Event Output Enable Position */ 401 #define RTC_MODE0_EVCTRL_PEREO7_Msk (_UINT32_(0x1) << RTC_MODE0_EVCTRL_PEREO7_Pos) /* (RTC_MODE0_EVCTRL) Periodic Interval 7 Event Output Enable Mask */ 402 #define RTC_MODE0_EVCTRL_PEREO7(value) (RTC_MODE0_EVCTRL_PEREO7_Msk & (_UINT32_(value) << RTC_MODE0_EVCTRL_PEREO7_Pos)) /* Assignment of value for PEREO7 in the RTC_MODE0_EVCTRL register */ 403 #define RTC_MODE0_EVCTRL_CMPEO0_Pos _UINT32_(8) /* (RTC_MODE0_EVCTRL) Compare 0 Event Output Enable Position */ 404 #define RTC_MODE0_EVCTRL_CMPEO0_Msk (_UINT32_(0x1) << RTC_MODE0_EVCTRL_CMPEO0_Pos) /* (RTC_MODE0_EVCTRL) Compare 0 Event Output Enable Mask */ 405 #define RTC_MODE0_EVCTRL_CMPEO0(value) (RTC_MODE0_EVCTRL_CMPEO0_Msk & (_UINT32_(value) << RTC_MODE0_EVCTRL_CMPEO0_Pos)) /* Assignment of value for CMPEO0 in the RTC_MODE0_EVCTRL register */ 406 #define RTC_MODE0_EVCTRL_CMPEO1_Pos _UINT32_(9) /* (RTC_MODE0_EVCTRL) Compare 1 Event Output Enable Position */ 407 #define RTC_MODE0_EVCTRL_CMPEO1_Msk (_UINT32_(0x1) << RTC_MODE0_EVCTRL_CMPEO1_Pos) /* (RTC_MODE0_EVCTRL) Compare 1 Event Output Enable Mask */ 408 #define RTC_MODE0_EVCTRL_CMPEO1(value) (RTC_MODE0_EVCTRL_CMPEO1_Msk & (_UINT32_(value) << RTC_MODE0_EVCTRL_CMPEO1_Pos)) /* Assignment of value for CMPEO1 in the RTC_MODE0_EVCTRL register */ 409 #define RTC_MODE0_EVCTRL_TAMPEREO_Pos _UINT32_(14) /* (RTC_MODE0_EVCTRL) Tamper Event Output Enable Position */ 410 #define RTC_MODE0_EVCTRL_TAMPEREO_Msk (_UINT32_(0x1) << RTC_MODE0_EVCTRL_TAMPEREO_Pos) /* (RTC_MODE0_EVCTRL) Tamper Event Output Enable Mask */ 411 #define RTC_MODE0_EVCTRL_TAMPEREO(value) (RTC_MODE0_EVCTRL_TAMPEREO_Msk & (_UINT32_(value) << RTC_MODE0_EVCTRL_TAMPEREO_Pos)) /* Assignment of value for TAMPEREO in the RTC_MODE0_EVCTRL register */ 412 #define RTC_MODE0_EVCTRL_OVFEO_Pos _UINT32_(15) /* (RTC_MODE0_EVCTRL) Overflow Event Output Enable Position */ 413 #define RTC_MODE0_EVCTRL_OVFEO_Msk (_UINT32_(0x1) << RTC_MODE0_EVCTRL_OVFEO_Pos) /* (RTC_MODE0_EVCTRL) Overflow Event Output Enable Mask */ 414 #define RTC_MODE0_EVCTRL_OVFEO(value) (RTC_MODE0_EVCTRL_OVFEO_Msk & (_UINT32_(value) << RTC_MODE0_EVCTRL_OVFEO_Pos)) /* Assignment of value for OVFEO in the RTC_MODE0_EVCTRL register */ 415 #define RTC_MODE0_EVCTRL_TAMPEVEI_Pos _UINT32_(16) /* (RTC_MODE0_EVCTRL) Tamper Event Input Enable Position */ 416 #define RTC_MODE0_EVCTRL_TAMPEVEI_Msk (_UINT32_(0x1) << RTC_MODE0_EVCTRL_TAMPEVEI_Pos) /* (RTC_MODE0_EVCTRL) Tamper Event Input Enable Mask */ 417 #define RTC_MODE0_EVCTRL_TAMPEVEI(value) (RTC_MODE0_EVCTRL_TAMPEVEI_Msk & (_UINT32_(value) << RTC_MODE0_EVCTRL_TAMPEVEI_Pos)) /* Assignment of value for TAMPEVEI in the RTC_MODE0_EVCTRL register */ 418 #define RTC_MODE0_EVCTRL_Msk _UINT32_(0x0001C3FF) /* (RTC_MODE0_EVCTRL) Register Mask */ 419 420 #define RTC_MODE0_EVCTRL_PEREO_Pos _UINT32_(0) /* (RTC_MODE0_EVCTRL Position) Periodic Interval x Event Output Enable */ 421 #define RTC_MODE0_EVCTRL_PEREO_Msk (_UINT32_(0xFF) << RTC_MODE0_EVCTRL_PEREO_Pos) /* (RTC_MODE0_EVCTRL Mask) PEREO */ 422 #define RTC_MODE0_EVCTRL_PEREO(value) (RTC_MODE0_EVCTRL_PEREO_Msk & (_UINT32_(value) << RTC_MODE0_EVCTRL_PEREO_Pos)) 423 #define RTC_MODE0_EVCTRL_CMPEO_Pos _UINT32_(8) /* (RTC_MODE0_EVCTRL Position) Compare x Event Output Enable */ 424 #define RTC_MODE0_EVCTRL_CMPEO_Msk (_UINT32_(0x3) << RTC_MODE0_EVCTRL_CMPEO_Pos) /* (RTC_MODE0_EVCTRL Mask) CMPEO */ 425 #define RTC_MODE0_EVCTRL_CMPEO(value) (RTC_MODE0_EVCTRL_CMPEO_Msk & (_UINT32_(value) << RTC_MODE0_EVCTRL_CMPEO_Pos)) 426 427 /* -------- RTC_MODE1_EVCTRL : (RTC Offset: 0x04) (R/W 32) MODE1 Event Control -------- */ 428 #define RTC_MODE1_EVCTRL_RESETVALUE _UINT32_(0x00) /* (RTC_MODE1_EVCTRL) MODE1 Event Control Reset Value */ 429 430 #define RTC_MODE1_EVCTRL_PEREO0_Pos _UINT32_(0) /* (RTC_MODE1_EVCTRL) Periodic Interval 0 Event Output Enable Position */ 431 #define RTC_MODE1_EVCTRL_PEREO0_Msk (_UINT32_(0x1) << RTC_MODE1_EVCTRL_PEREO0_Pos) /* (RTC_MODE1_EVCTRL) Periodic Interval 0 Event Output Enable Mask */ 432 #define RTC_MODE1_EVCTRL_PEREO0(value) (RTC_MODE1_EVCTRL_PEREO0_Msk & (_UINT32_(value) << RTC_MODE1_EVCTRL_PEREO0_Pos)) /* Assignment of value for PEREO0 in the RTC_MODE1_EVCTRL register */ 433 #define RTC_MODE1_EVCTRL_PEREO1_Pos _UINT32_(1) /* (RTC_MODE1_EVCTRL) Periodic Interval 1 Event Output Enable Position */ 434 #define RTC_MODE1_EVCTRL_PEREO1_Msk (_UINT32_(0x1) << RTC_MODE1_EVCTRL_PEREO1_Pos) /* (RTC_MODE1_EVCTRL) Periodic Interval 1 Event Output Enable Mask */ 435 #define RTC_MODE1_EVCTRL_PEREO1(value) (RTC_MODE1_EVCTRL_PEREO1_Msk & (_UINT32_(value) << RTC_MODE1_EVCTRL_PEREO1_Pos)) /* Assignment of value for PEREO1 in the RTC_MODE1_EVCTRL register */ 436 #define RTC_MODE1_EVCTRL_PEREO2_Pos _UINT32_(2) /* (RTC_MODE1_EVCTRL) Periodic Interval 2 Event Output Enable Position */ 437 #define RTC_MODE1_EVCTRL_PEREO2_Msk (_UINT32_(0x1) << RTC_MODE1_EVCTRL_PEREO2_Pos) /* (RTC_MODE1_EVCTRL) Periodic Interval 2 Event Output Enable Mask */ 438 #define RTC_MODE1_EVCTRL_PEREO2(value) (RTC_MODE1_EVCTRL_PEREO2_Msk & (_UINT32_(value) << RTC_MODE1_EVCTRL_PEREO2_Pos)) /* Assignment of value for PEREO2 in the RTC_MODE1_EVCTRL register */ 439 #define RTC_MODE1_EVCTRL_PEREO3_Pos _UINT32_(3) /* (RTC_MODE1_EVCTRL) Periodic Interval 3 Event Output Enable Position */ 440 #define RTC_MODE1_EVCTRL_PEREO3_Msk (_UINT32_(0x1) << RTC_MODE1_EVCTRL_PEREO3_Pos) /* (RTC_MODE1_EVCTRL) Periodic Interval 3 Event Output Enable Mask */ 441 #define RTC_MODE1_EVCTRL_PEREO3(value) (RTC_MODE1_EVCTRL_PEREO3_Msk & (_UINT32_(value) << RTC_MODE1_EVCTRL_PEREO3_Pos)) /* Assignment of value for PEREO3 in the RTC_MODE1_EVCTRL register */ 442 #define RTC_MODE1_EVCTRL_PEREO4_Pos _UINT32_(4) /* (RTC_MODE1_EVCTRL) Periodic Interval 4 Event Output Enable Position */ 443 #define RTC_MODE1_EVCTRL_PEREO4_Msk (_UINT32_(0x1) << RTC_MODE1_EVCTRL_PEREO4_Pos) /* (RTC_MODE1_EVCTRL) Periodic Interval 4 Event Output Enable Mask */ 444 #define RTC_MODE1_EVCTRL_PEREO4(value) (RTC_MODE1_EVCTRL_PEREO4_Msk & (_UINT32_(value) << RTC_MODE1_EVCTRL_PEREO4_Pos)) /* Assignment of value for PEREO4 in the RTC_MODE1_EVCTRL register */ 445 #define RTC_MODE1_EVCTRL_PEREO5_Pos _UINT32_(5) /* (RTC_MODE1_EVCTRL) Periodic Interval 5 Event Output Enable Position */ 446 #define RTC_MODE1_EVCTRL_PEREO5_Msk (_UINT32_(0x1) << RTC_MODE1_EVCTRL_PEREO5_Pos) /* (RTC_MODE1_EVCTRL) Periodic Interval 5 Event Output Enable Mask */ 447 #define RTC_MODE1_EVCTRL_PEREO5(value) (RTC_MODE1_EVCTRL_PEREO5_Msk & (_UINT32_(value) << RTC_MODE1_EVCTRL_PEREO5_Pos)) /* Assignment of value for PEREO5 in the RTC_MODE1_EVCTRL register */ 448 #define RTC_MODE1_EVCTRL_PEREO6_Pos _UINT32_(6) /* (RTC_MODE1_EVCTRL) Periodic Interval 6 Event Output Enable Position */ 449 #define RTC_MODE1_EVCTRL_PEREO6_Msk (_UINT32_(0x1) << RTC_MODE1_EVCTRL_PEREO6_Pos) /* (RTC_MODE1_EVCTRL) Periodic Interval 6 Event Output Enable Mask */ 450 #define RTC_MODE1_EVCTRL_PEREO6(value) (RTC_MODE1_EVCTRL_PEREO6_Msk & (_UINT32_(value) << RTC_MODE1_EVCTRL_PEREO6_Pos)) /* Assignment of value for PEREO6 in the RTC_MODE1_EVCTRL register */ 451 #define RTC_MODE1_EVCTRL_PEREO7_Pos _UINT32_(7) /* (RTC_MODE1_EVCTRL) Periodic Interval 7 Event Output Enable Position */ 452 #define RTC_MODE1_EVCTRL_PEREO7_Msk (_UINT32_(0x1) << RTC_MODE1_EVCTRL_PEREO7_Pos) /* (RTC_MODE1_EVCTRL) Periodic Interval 7 Event Output Enable Mask */ 453 #define RTC_MODE1_EVCTRL_PEREO7(value) (RTC_MODE1_EVCTRL_PEREO7_Msk & (_UINT32_(value) << RTC_MODE1_EVCTRL_PEREO7_Pos)) /* Assignment of value for PEREO7 in the RTC_MODE1_EVCTRL register */ 454 #define RTC_MODE1_EVCTRL_CMPEO0_Pos _UINT32_(8) /* (RTC_MODE1_EVCTRL) Compare 0 Event Output Enable Position */ 455 #define RTC_MODE1_EVCTRL_CMPEO0_Msk (_UINT32_(0x1) << RTC_MODE1_EVCTRL_CMPEO0_Pos) /* (RTC_MODE1_EVCTRL) Compare 0 Event Output Enable Mask */ 456 #define RTC_MODE1_EVCTRL_CMPEO0(value) (RTC_MODE1_EVCTRL_CMPEO0_Msk & (_UINT32_(value) << RTC_MODE1_EVCTRL_CMPEO0_Pos)) /* Assignment of value for CMPEO0 in the RTC_MODE1_EVCTRL register */ 457 #define RTC_MODE1_EVCTRL_CMPEO1_Pos _UINT32_(9) /* (RTC_MODE1_EVCTRL) Compare 1 Event Output Enable Position */ 458 #define RTC_MODE1_EVCTRL_CMPEO1_Msk (_UINT32_(0x1) << RTC_MODE1_EVCTRL_CMPEO1_Pos) /* (RTC_MODE1_EVCTRL) Compare 1 Event Output Enable Mask */ 459 #define RTC_MODE1_EVCTRL_CMPEO1(value) (RTC_MODE1_EVCTRL_CMPEO1_Msk & (_UINT32_(value) << RTC_MODE1_EVCTRL_CMPEO1_Pos)) /* Assignment of value for CMPEO1 in the RTC_MODE1_EVCTRL register */ 460 #define RTC_MODE1_EVCTRL_CMPEO2_Pos _UINT32_(10) /* (RTC_MODE1_EVCTRL) Compare 2 Event Output Enable Position */ 461 #define RTC_MODE1_EVCTRL_CMPEO2_Msk (_UINT32_(0x1) << RTC_MODE1_EVCTRL_CMPEO2_Pos) /* (RTC_MODE1_EVCTRL) Compare 2 Event Output Enable Mask */ 462 #define RTC_MODE1_EVCTRL_CMPEO2(value) (RTC_MODE1_EVCTRL_CMPEO2_Msk & (_UINT32_(value) << RTC_MODE1_EVCTRL_CMPEO2_Pos)) /* Assignment of value for CMPEO2 in the RTC_MODE1_EVCTRL register */ 463 #define RTC_MODE1_EVCTRL_CMPEO3_Pos _UINT32_(11) /* (RTC_MODE1_EVCTRL) Compare 3 Event Output Enable Position */ 464 #define RTC_MODE1_EVCTRL_CMPEO3_Msk (_UINT32_(0x1) << RTC_MODE1_EVCTRL_CMPEO3_Pos) /* (RTC_MODE1_EVCTRL) Compare 3 Event Output Enable Mask */ 465 #define RTC_MODE1_EVCTRL_CMPEO3(value) (RTC_MODE1_EVCTRL_CMPEO3_Msk & (_UINT32_(value) << RTC_MODE1_EVCTRL_CMPEO3_Pos)) /* Assignment of value for CMPEO3 in the RTC_MODE1_EVCTRL register */ 466 #define RTC_MODE1_EVCTRL_TAMPEREO_Pos _UINT32_(14) /* (RTC_MODE1_EVCTRL) Tamper Event Output Enable Position */ 467 #define RTC_MODE1_EVCTRL_TAMPEREO_Msk (_UINT32_(0x1) << RTC_MODE1_EVCTRL_TAMPEREO_Pos) /* (RTC_MODE1_EVCTRL) Tamper Event Output Enable Mask */ 468 #define RTC_MODE1_EVCTRL_TAMPEREO(value) (RTC_MODE1_EVCTRL_TAMPEREO_Msk & (_UINT32_(value) << RTC_MODE1_EVCTRL_TAMPEREO_Pos)) /* Assignment of value for TAMPEREO in the RTC_MODE1_EVCTRL register */ 469 #define RTC_MODE1_EVCTRL_OVFEO_Pos _UINT32_(15) /* (RTC_MODE1_EVCTRL) Overflow Event Output Enable Position */ 470 #define RTC_MODE1_EVCTRL_OVFEO_Msk (_UINT32_(0x1) << RTC_MODE1_EVCTRL_OVFEO_Pos) /* (RTC_MODE1_EVCTRL) Overflow Event Output Enable Mask */ 471 #define RTC_MODE1_EVCTRL_OVFEO(value) (RTC_MODE1_EVCTRL_OVFEO_Msk & (_UINT32_(value) << RTC_MODE1_EVCTRL_OVFEO_Pos)) /* Assignment of value for OVFEO in the RTC_MODE1_EVCTRL register */ 472 #define RTC_MODE1_EVCTRL_TAMPEVEI_Pos _UINT32_(16) /* (RTC_MODE1_EVCTRL) Tamper Event Input Enable Position */ 473 #define RTC_MODE1_EVCTRL_TAMPEVEI_Msk (_UINT32_(0x1) << RTC_MODE1_EVCTRL_TAMPEVEI_Pos) /* (RTC_MODE1_EVCTRL) Tamper Event Input Enable Mask */ 474 #define RTC_MODE1_EVCTRL_TAMPEVEI(value) (RTC_MODE1_EVCTRL_TAMPEVEI_Msk & (_UINT32_(value) << RTC_MODE1_EVCTRL_TAMPEVEI_Pos)) /* Assignment of value for TAMPEVEI in the RTC_MODE1_EVCTRL register */ 475 #define RTC_MODE1_EVCTRL_Msk _UINT32_(0x0001CFFF) /* (RTC_MODE1_EVCTRL) Register Mask */ 476 477 #define RTC_MODE1_EVCTRL_PEREO_Pos _UINT32_(0) /* (RTC_MODE1_EVCTRL Position) Periodic Interval x Event Output Enable */ 478 #define RTC_MODE1_EVCTRL_PEREO_Msk (_UINT32_(0xFF) << RTC_MODE1_EVCTRL_PEREO_Pos) /* (RTC_MODE1_EVCTRL Mask) PEREO */ 479 #define RTC_MODE1_EVCTRL_PEREO(value) (RTC_MODE1_EVCTRL_PEREO_Msk & (_UINT32_(value) << RTC_MODE1_EVCTRL_PEREO_Pos)) 480 #define RTC_MODE1_EVCTRL_CMPEO_Pos _UINT32_(8) /* (RTC_MODE1_EVCTRL Position) Compare x Event Output Enable */ 481 #define RTC_MODE1_EVCTRL_CMPEO_Msk (_UINT32_(0xF) << RTC_MODE1_EVCTRL_CMPEO_Pos) /* (RTC_MODE1_EVCTRL Mask) CMPEO */ 482 #define RTC_MODE1_EVCTRL_CMPEO(value) (RTC_MODE1_EVCTRL_CMPEO_Msk & (_UINT32_(value) << RTC_MODE1_EVCTRL_CMPEO_Pos)) 483 484 /* -------- RTC_MODE2_EVCTRL : (RTC Offset: 0x04) (R/W 32) MODE2 Event Control -------- */ 485 #define RTC_MODE2_EVCTRL_RESETVALUE _UINT32_(0x00) /* (RTC_MODE2_EVCTRL) MODE2 Event Control Reset Value */ 486 487 #define RTC_MODE2_EVCTRL_PEREO0_Pos _UINT32_(0) /* (RTC_MODE2_EVCTRL) Periodic Interval 0 Event Output Enable Position */ 488 #define RTC_MODE2_EVCTRL_PEREO0_Msk (_UINT32_(0x1) << RTC_MODE2_EVCTRL_PEREO0_Pos) /* (RTC_MODE2_EVCTRL) Periodic Interval 0 Event Output Enable Mask */ 489 #define RTC_MODE2_EVCTRL_PEREO0(value) (RTC_MODE2_EVCTRL_PEREO0_Msk & (_UINT32_(value) << RTC_MODE2_EVCTRL_PEREO0_Pos)) /* Assignment of value for PEREO0 in the RTC_MODE2_EVCTRL register */ 490 #define RTC_MODE2_EVCTRL_PEREO1_Pos _UINT32_(1) /* (RTC_MODE2_EVCTRL) Periodic Interval 1 Event Output Enable Position */ 491 #define RTC_MODE2_EVCTRL_PEREO1_Msk (_UINT32_(0x1) << RTC_MODE2_EVCTRL_PEREO1_Pos) /* (RTC_MODE2_EVCTRL) Periodic Interval 1 Event Output Enable Mask */ 492 #define RTC_MODE2_EVCTRL_PEREO1(value) (RTC_MODE2_EVCTRL_PEREO1_Msk & (_UINT32_(value) << RTC_MODE2_EVCTRL_PEREO1_Pos)) /* Assignment of value for PEREO1 in the RTC_MODE2_EVCTRL register */ 493 #define RTC_MODE2_EVCTRL_PEREO2_Pos _UINT32_(2) /* (RTC_MODE2_EVCTRL) Periodic Interval 2 Event Output Enable Position */ 494 #define RTC_MODE2_EVCTRL_PEREO2_Msk (_UINT32_(0x1) << RTC_MODE2_EVCTRL_PEREO2_Pos) /* (RTC_MODE2_EVCTRL) Periodic Interval 2 Event Output Enable Mask */ 495 #define RTC_MODE2_EVCTRL_PEREO2(value) (RTC_MODE2_EVCTRL_PEREO2_Msk & (_UINT32_(value) << RTC_MODE2_EVCTRL_PEREO2_Pos)) /* Assignment of value for PEREO2 in the RTC_MODE2_EVCTRL register */ 496 #define RTC_MODE2_EVCTRL_PEREO3_Pos _UINT32_(3) /* (RTC_MODE2_EVCTRL) Periodic Interval 3 Event Output Enable Position */ 497 #define RTC_MODE2_EVCTRL_PEREO3_Msk (_UINT32_(0x1) << RTC_MODE2_EVCTRL_PEREO3_Pos) /* (RTC_MODE2_EVCTRL) Periodic Interval 3 Event Output Enable Mask */ 498 #define RTC_MODE2_EVCTRL_PEREO3(value) (RTC_MODE2_EVCTRL_PEREO3_Msk & (_UINT32_(value) << RTC_MODE2_EVCTRL_PEREO3_Pos)) /* Assignment of value for PEREO3 in the RTC_MODE2_EVCTRL register */ 499 #define RTC_MODE2_EVCTRL_PEREO4_Pos _UINT32_(4) /* (RTC_MODE2_EVCTRL) Periodic Interval 4 Event Output Enable Position */ 500 #define RTC_MODE2_EVCTRL_PEREO4_Msk (_UINT32_(0x1) << RTC_MODE2_EVCTRL_PEREO4_Pos) /* (RTC_MODE2_EVCTRL) Periodic Interval 4 Event Output Enable Mask */ 501 #define RTC_MODE2_EVCTRL_PEREO4(value) (RTC_MODE2_EVCTRL_PEREO4_Msk & (_UINT32_(value) << RTC_MODE2_EVCTRL_PEREO4_Pos)) /* Assignment of value for PEREO4 in the RTC_MODE2_EVCTRL register */ 502 #define RTC_MODE2_EVCTRL_PEREO5_Pos _UINT32_(5) /* (RTC_MODE2_EVCTRL) Periodic Interval 5 Event Output Enable Position */ 503 #define RTC_MODE2_EVCTRL_PEREO5_Msk (_UINT32_(0x1) << RTC_MODE2_EVCTRL_PEREO5_Pos) /* (RTC_MODE2_EVCTRL) Periodic Interval 5 Event Output Enable Mask */ 504 #define RTC_MODE2_EVCTRL_PEREO5(value) (RTC_MODE2_EVCTRL_PEREO5_Msk & (_UINT32_(value) << RTC_MODE2_EVCTRL_PEREO5_Pos)) /* Assignment of value for PEREO5 in the RTC_MODE2_EVCTRL register */ 505 #define RTC_MODE2_EVCTRL_PEREO6_Pos _UINT32_(6) /* (RTC_MODE2_EVCTRL) Periodic Interval 6 Event Output Enable Position */ 506 #define RTC_MODE2_EVCTRL_PEREO6_Msk (_UINT32_(0x1) << RTC_MODE2_EVCTRL_PEREO6_Pos) /* (RTC_MODE2_EVCTRL) Periodic Interval 6 Event Output Enable Mask */ 507 #define RTC_MODE2_EVCTRL_PEREO6(value) (RTC_MODE2_EVCTRL_PEREO6_Msk & (_UINT32_(value) << RTC_MODE2_EVCTRL_PEREO6_Pos)) /* Assignment of value for PEREO6 in the RTC_MODE2_EVCTRL register */ 508 #define RTC_MODE2_EVCTRL_PEREO7_Pos _UINT32_(7) /* (RTC_MODE2_EVCTRL) Periodic Interval 7 Event Output Enable Position */ 509 #define RTC_MODE2_EVCTRL_PEREO7_Msk (_UINT32_(0x1) << RTC_MODE2_EVCTRL_PEREO7_Pos) /* (RTC_MODE2_EVCTRL) Periodic Interval 7 Event Output Enable Mask */ 510 #define RTC_MODE2_EVCTRL_PEREO7(value) (RTC_MODE2_EVCTRL_PEREO7_Msk & (_UINT32_(value) << RTC_MODE2_EVCTRL_PEREO7_Pos)) /* Assignment of value for PEREO7 in the RTC_MODE2_EVCTRL register */ 511 #define RTC_MODE2_EVCTRL_ALARMEO0_Pos _UINT32_(8) /* (RTC_MODE2_EVCTRL) Alarm 0 Event Output Enable Position */ 512 #define RTC_MODE2_EVCTRL_ALARMEO0_Msk (_UINT32_(0x1) << RTC_MODE2_EVCTRL_ALARMEO0_Pos) /* (RTC_MODE2_EVCTRL) Alarm 0 Event Output Enable Mask */ 513 #define RTC_MODE2_EVCTRL_ALARMEO0(value) (RTC_MODE2_EVCTRL_ALARMEO0_Msk & (_UINT32_(value) << RTC_MODE2_EVCTRL_ALARMEO0_Pos)) /* Assignment of value for ALARMEO0 in the RTC_MODE2_EVCTRL register */ 514 #define RTC_MODE2_EVCTRL_ALARMEO1_Pos _UINT32_(9) /* (RTC_MODE2_EVCTRL) Alarm 1 Event Output Enable Position */ 515 #define RTC_MODE2_EVCTRL_ALARMEO1_Msk (_UINT32_(0x1) << RTC_MODE2_EVCTRL_ALARMEO1_Pos) /* (RTC_MODE2_EVCTRL) Alarm 1 Event Output Enable Mask */ 516 #define RTC_MODE2_EVCTRL_ALARMEO1(value) (RTC_MODE2_EVCTRL_ALARMEO1_Msk & (_UINT32_(value) << RTC_MODE2_EVCTRL_ALARMEO1_Pos)) /* Assignment of value for ALARMEO1 in the RTC_MODE2_EVCTRL register */ 517 #define RTC_MODE2_EVCTRL_TAMPEREO_Pos _UINT32_(14) /* (RTC_MODE2_EVCTRL) Tamper Event Output Enable Position */ 518 #define RTC_MODE2_EVCTRL_TAMPEREO_Msk (_UINT32_(0x1) << RTC_MODE2_EVCTRL_TAMPEREO_Pos) /* (RTC_MODE2_EVCTRL) Tamper Event Output Enable Mask */ 519 #define RTC_MODE2_EVCTRL_TAMPEREO(value) (RTC_MODE2_EVCTRL_TAMPEREO_Msk & (_UINT32_(value) << RTC_MODE2_EVCTRL_TAMPEREO_Pos)) /* Assignment of value for TAMPEREO in the RTC_MODE2_EVCTRL register */ 520 #define RTC_MODE2_EVCTRL_OVFEO_Pos _UINT32_(15) /* (RTC_MODE2_EVCTRL) Overflow Event Output Enable Position */ 521 #define RTC_MODE2_EVCTRL_OVFEO_Msk (_UINT32_(0x1) << RTC_MODE2_EVCTRL_OVFEO_Pos) /* (RTC_MODE2_EVCTRL) Overflow Event Output Enable Mask */ 522 #define RTC_MODE2_EVCTRL_OVFEO(value) (RTC_MODE2_EVCTRL_OVFEO_Msk & (_UINT32_(value) << RTC_MODE2_EVCTRL_OVFEO_Pos)) /* Assignment of value for OVFEO in the RTC_MODE2_EVCTRL register */ 523 #define RTC_MODE2_EVCTRL_TAMPEVEI_Pos _UINT32_(16) /* (RTC_MODE2_EVCTRL) Tamper Event Input Enable Position */ 524 #define RTC_MODE2_EVCTRL_TAMPEVEI_Msk (_UINT32_(0x1) << RTC_MODE2_EVCTRL_TAMPEVEI_Pos) /* (RTC_MODE2_EVCTRL) Tamper Event Input Enable Mask */ 525 #define RTC_MODE2_EVCTRL_TAMPEVEI(value) (RTC_MODE2_EVCTRL_TAMPEVEI_Msk & (_UINT32_(value) << RTC_MODE2_EVCTRL_TAMPEVEI_Pos)) /* Assignment of value for TAMPEVEI in the RTC_MODE2_EVCTRL register */ 526 #define RTC_MODE2_EVCTRL_Msk _UINT32_(0x0001C3FF) /* (RTC_MODE2_EVCTRL) Register Mask */ 527 528 #define RTC_MODE2_EVCTRL_PEREO_Pos _UINT32_(0) /* (RTC_MODE2_EVCTRL Position) Periodic Interval x Event Output Enable */ 529 #define RTC_MODE2_EVCTRL_PEREO_Msk (_UINT32_(0xFF) << RTC_MODE2_EVCTRL_PEREO_Pos) /* (RTC_MODE2_EVCTRL Mask) PEREO */ 530 #define RTC_MODE2_EVCTRL_PEREO(value) (RTC_MODE2_EVCTRL_PEREO_Msk & (_UINT32_(value) << RTC_MODE2_EVCTRL_PEREO_Pos)) 531 #define RTC_MODE2_EVCTRL_ALARMEO_Pos _UINT32_(8) /* (RTC_MODE2_EVCTRL Position) Alarm x Event Output Enable */ 532 #define RTC_MODE2_EVCTRL_ALARMEO_Msk (_UINT32_(0x3) << RTC_MODE2_EVCTRL_ALARMEO_Pos) /* (RTC_MODE2_EVCTRL Mask) ALARMEO */ 533 #define RTC_MODE2_EVCTRL_ALARMEO(value) (RTC_MODE2_EVCTRL_ALARMEO_Msk & (_UINT32_(value) << RTC_MODE2_EVCTRL_ALARMEO_Pos)) 534 535 /* -------- RTC_MODE0_INTENCLR : (RTC Offset: 0x08) (R/W 16) MODE0 Interrupt Enable Clear -------- */ 536 #define RTC_MODE0_INTENCLR_RESETVALUE _UINT16_(0x00) /* (RTC_MODE0_INTENCLR) MODE0 Interrupt Enable Clear Reset Value */ 537 538 #define RTC_MODE0_INTENCLR_PER0_Pos _UINT16_(0) /* (RTC_MODE0_INTENCLR) Periodic Interval 0 Interrupt Enable Position */ 539 #define RTC_MODE0_INTENCLR_PER0_Msk (_UINT16_(0x1) << RTC_MODE0_INTENCLR_PER0_Pos) /* (RTC_MODE0_INTENCLR) Periodic Interval 0 Interrupt Enable Mask */ 540 #define RTC_MODE0_INTENCLR_PER0(value) (RTC_MODE0_INTENCLR_PER0_Msk & (_UINT16_(value) << RTC_MODE0_INTENCLR_PER0_Pos)) /* Assignment of value for PER0 in the RTC_MODE0_INTENCLR register */ 541 #define RTC_MODE0_INTENCLR_PER1_Pos _UINT16_(1) /* (RTC_MODE0_INTENCLR) Periodic Interval 1 Interrupt Enable Position */ 542 #define RTC_MODE0_INTENCLR_PER1_Msk (_UINT16_(0x1) << RTC_MODE0_INTENCLR_PER1_Pos) /* (RTC_MODE0_INTENCLR) Periodic Interval 1 Interrupt Enable Mask */ 543 #define RTC_MODE0_INTENCLR_PER1(value) (RTC_MODE0_INTENCLR_PER1_Msk & (_UINT16_(value) << RTC_MODE0_INTENCLR_PER1_Pos)) /* Assignment of value for PER1 in the RTC_MODE0_INTENCLR register */ 544 #define RTC_MODE0_INTENCLR_PER2_Pos _UINT16_(2) /* (RTC_MODE0_INTENCLR) Periodic Interval 2 Interrupt Enable Position */ 545 #define RTC_MODE0_INTENCLR_PER2_Msk (_UINT16_(0x1) << RTC_MODE0_INTENCLR_PER2_Pos) /* (RTC_MODE0_INTENCLR) Periodic Interval 2 Interrupt Enable Mask */ 546 #define RTC_MODE0_INTENCLR_PER2(value) (RTC_MODE0_INTENCLR_PER2_Msk & (_UINT16_(value) << RTC_MODE0_INTENCLR_PER2_Pos)) /* Assignment of value for PER2 in the RTC_MODE0_INTENCLR register */ 547 #define RTC_MODE0_INTENCLR_PER3_Pos _UINT16_(3) /* (RTC_MODE0_INTENCLR) Periodic Interval 3 Interrupt Enable Position */ 548 #define RTC_MODE0_INTENCLR_PER3_Msk (_UINT16_(0x1) << RTC_MODE0_INTENCLR_PER3_Pos) /* (RTC_MODE0_INTENCLR) Periodic Interval 3 Interrupt Enable Mask */ 549 #define RTC_MODE0_INTENCLR_PER3(value) (RTC_MODE0_INTENCLR_PER3_Msk & (_UINT16_(value) << RTC_MODE0_INTENCLR_PER3_Pos)) /* Assignment of value for PER3 in the RTC_MODE0_INTENCLR register */ 550 #define RTC_MODE0_INTENCLR_PER4_Pos _UINT16_(4) /* (RTC_MODE0_INTENCLR) Periodic Interval 4 Interrupt Enable Position */ 551 #define RTC_MODE0_INTENCLR_PER4_Msk (_UINT16_(0x1) << RTC_MODE0_INTENCLR_PER4_Pos) /* (RTC_MODE0_INTENCLR) Periodic Interval 4 Interrupt Enable Mask */ 552 #define RTC_MODE0_INTENCLR_PER4(value) (RTC_MODE0_INTENCLR_PER4_Msk & (_UINT16_(value) << RTC_MODE0_INTENCLR_PER4_Pos)) /* Assignment of value for PER4 in the RTC_MODE0_INTENCLR register */ 553 #define RTC_MODE0_INTENCLR_PER5_Pos _UINT16_(5) /* (RTC_MODE0_INTENCLR) Periodic Interval 5 Interrupt Enable Position */ 554 #define RTC_MODE0_INTENCLR_PER5_Msk (_UINT16_(0x1) << RTC_MODE0_INTENCLR_PER5_Pos) /* (RTC_MODE0_INTENCLR) Periodic Interval 5 Interrupt Enable Mask */ 555 #define RTC_MODE0_INTENCLR_PER5(value) (RTC_MODE0_INTENCLR_PER5_Msk & (_UINT16_(value) << RTC_MODE0_INTENCLR_PER5_Pos)) /* Assignment of value for PER5 in the RTC_MODE0_INTENCLR register */ 556 #define RTC_MODE0_INTENCLR_PER6_Pos _UINT16_(6) /* (RTC_MODE0_INTENCLR) Periodic Interval 6 Interrupt Enable Position */ 557 #define RTC_MODE0_INTENCLR_PER6_Msk (_UINT16_(0x1) << RTC_MODE0_INTENCLR_PER6_Pos) /* (RTC_MODE0_INTENCLR) Periodic Interval 6 Interrupt Enable Mask */ 558 #define RTC_MODE0_INTENCLR_PER6(value) (RTC_MODE0_INTENCLR_PER6_Msk & (_UINT16_(value) << RTC_MODE0_INTENCLR_PER6_Pos)) /* Assignment of value for PER6 in the RTC_MODE0_INTENCLR register */ 559 #define RTC_MODE0_INTENCLR_PER7_Pos _UINT16_(7) /* (RTC_MODE0_INTENCLR) Periodic Interval 7 Interrupt Enable Position */ 560 #define RTC_MODE0_INTENCLR_PER7_Msk (_UINT16_(0x1) << RTC_MODE0_INTENCLR_PER7_Pos) /* (RTC_MODE0_INTENCLR) Periodic Interval 7 Interrupt Enable Mask */ 561 #define RTC_MODE0_INTENCLR_PER7(value) (RTC_MODE0_INTENCLR_PER7_Msk & (_UINT16_(value) << RTC_MODE0_INTENCLR_PER7_Pos)) /* Assignment of value for PER7 in the RTC_MODE0_INTENCLR register */ 562 #define RTC_MODE0_INTENCLR_CMP0_Pos _UINT16_(8) /* (RTC_MODE0_INTENCLR) Compare 0 Interrupt Enable Position */ 563 #define RTC_MODE0_INTENCLR_CMP0_Msk (_UINT16_(0x1) << RTC_MODE0_INTENCLR_CMP0_Pos) /* (RTC_MODE0_INTENCLR) Compare 0 Interrupt Enable Mask */ 564 #define RTC_MODE0_INTENCLR_CMP0(value) (RTC_MODE0_INTENCLR_CMP0_Msk & (_UINT16_(value) << RTC_MODE0_INTENCLR_CMP0_Pos)) /* Assignment of value for CMP0 in the RTC_MODE0_INTENCLR register */ 565 #define RTC_MODE0_INTENCLR_CMP1_Pos _UINT16_(9) /* (RTC_MODE0_INTENCLR) Compare 1 Interrupt Enable Position */ 566 #define RTC_MODE0_INTENCLR_CMP1_Msk (_UINT16_(0x1) << RTC_MODE0_INTENCLR_CMP1_Pos) /* (RTC_MODE0_INTENCLR) Compare 1 Interrupt Enable Mask */ 567 #define RTC_MODE0_INTENCLR_CMP1(value) (RTC_MODE0_INTENCLR_CMP1_Msk & (_UINT16_(value) << RTC_MODE0_INTENCLR_CMP1_Pos)) /* Assignment of value for CMP1 in the RTC_MODE0_INTENCLR register */ 568 #define RTC_MODE0_INTENCLR_TAMPER_Pos _UINT16_(14) /* (RTC_MODE0_INTENCLR) Tamper Enable Position */ 569 #define RTC_MODE0_INTENCLR_TAMPER_Msk (_UINT16_(0x1) << RTC_MODE0_INTENCLR_TAMPER_Pos) /* (RTC_MODE0_INTENCLR) Tamper Enable Mask */ 570 #define RTC_MODE0_INTENCLR_TAMPER(value) (RTC_MODE0_INTENCLR_TAMPER_Msk & (_UINT16_(value) << RTC_MODE0_INTENCLR_TAMPER_Pos)) /* Assignment of value for TAMPER in the RTC_MODE0_INTENCLR register */ 571 #define RTC_MODE0_INTENCLR_OVF_Pos _UINT16_(15) /* (RTC_MODE0_INTENCLR) Overflow Interrupt Enable Position */ 572 #define RTC_MODE0_INTENCLR_OVF_Msk (_UINT16_(0x1) << RTC_MODE0_INTENCLR_OVF_Pos) /* (RTC_MODE0_INTENCLR) Overflow Interrupt Enable Mask */ 573 #define RTC_MODE0_INTENCLR_OVF(value) (RTC_MODE0_INTENCLR_OVF_Msk & (_UINT16_(value) << RTC_MODE0_INTENCLR_OVF_Pos)) /* Assignment of value for OVF in the RTC_MODE0_INTENCLR register */ 574 #define RTC_MODE0_INTENCLR_Msk _UINT16_(0xC3FF) /* (RTC_MODE0_INTENCLR) Register Mask */ 575 576 #define RTC_MODE0_INTENCLR_PER_Pos _UINT16_(0) /* (RTC_MODE0_INTENCLR Position) Periodic Interval x Interrupt Enable */ 577 #define RTC_MODE0_INTENCLR_PER_Msk (_UINT16_(0xFF) << RTC_MODE0_INTENCLR_PER_Pos) /* (RTC_MODE0_INTENCLR Mask) PER */ 578 #define RTC_MODE0_INTENCLR_PER(value) (RTC_MODE0_INTENCLR_PER_Msk & (_UINT16_(value) << RTC_MODE0_INTENCLR_PER_Pos)) 579 #define RTC_MODE0_INTENCLR_CMP_Pos _UINT16_(8) /* (RTC_MODE0_INTENCLR Position) Compare x Interrupt Enable */ 580 #define RTC_MODE0_INTENCLR_CMP_Msk (_UINT16_(0x3) << RTC_MODE0_INTENCLR_CMP_Pos) /* (RTC_MODE0_INTENCLR Mask) CMP */ 581 #define RTC_MODE0_INTENCLR_CMP(value) (RTC_MODE0_INTENCLR_CMP_Msk & (_UINT16_(value) << RTC_MODE0_INTENCLR_CMP_Pos)) 582 583 /* -------- RTC_MODE1_INTENCLR : (RTC Offset: 0x08) (R/W 16) MODE1 Interrupt Enable Clear -------- */ 584 #define RTC_MODE1_INTENCLR_RESETVALUE _UINT16_(0x00) /* (RTC_MODE1_INTENCLR) MODE1 Interrupt Enable Clear Reset Value */ 585 586 #define RTC_MODE1_INTENCLR_PER0_Pos _UINT16_(0) /* (RTC_MODE1_INTENCLR) Periodic Interval 0 Interrupt Enable Position */ 587 #define RTC_MODE1_INTENCLR_PER0_Msk (_UINT16_(0x1) << RTC_MODE1_INTENCLR_PER0_Pos) /* (RTC_MODE1_INTENCLR) Periodic Interval 0 Interrupt Enable Mask */ 588 #define RTC_MODE1_INTENCLR_PER0(value) (RTC_MODE1_INTENCLR_PER0_Msk & (_UINT16_(value) << RTC_MODE1_INTENCLR_PER0_Pos)) /* Assignment of value for PER0 in the RTC_MODE1_INTENCLR register */ 589 #define RTC_MODE1_INTENCLR_PER1_Pos _UINT16_(1) /* (RTC_MODE1_INTENCLR) Periodic Interval 1 Interrupt Enable Position */ 590 #define RTC_MODE1_INTENCLR_PER1_Msk (_UINT16_(0x1) << RTC_MODE1_INTENCLR_PER1_Pos) /* (RTC_MODE1_INTENCLR) Periodic Interval 1 Interrupt Enable Mask */ 591 #define RTC_MODE1_INTENCLR_PER1(value) (RTC_MODE1_INTENCLR_PER1_Msk & (_UINT16_(value) << RTC_MODE1_INTENCLR_PER1_Pos)) /* Assignment of value for PER1 in the RTC_MODE1_INTENCLR register */ 592 #define RTC_MODE1_INTENCLR_PER2_Pos _UINT16_(2) /* (RTC_MODE1_INTENCLR) Periodic Interval 2 Interrupt Enable Position */ 593 #define RTC_MODE1_INTENCLR_PER2_Msk (_UINT16_(0x1) << RTC_MODE1_INTENCLR_PER2_Pos) /* (RTC_MODE1_INTENCLR) Periodic Interval 2 Interrupt Enable Mask */ 594 #define RTC_MODE1_INTENCLR_PER2(value) (RTC_MODE1_INTENCLR_PER2_Msk & (_UINT16_(value) << RTC_MODE1_INTENCLR_PER2_Pos)) /* Assignment of value for PER2 in the RTC_MODE1_INTENCLR register */ 595 #define RTC_MODE1_INTENCLR_PER3_Pos _UINT16_(3) /* (RTC_MODE1_INTENCLR) Periodic Interval 3 Interrupt Enable Position */ 596 #define RTC_MODE1_INTENCLR_PER3_Msk (_UINT16_(0x1) << RTC_MODE1_INTENCLR_PER3_Pos) /* (RTC_MODE1_INTENCLR) Periodic Interval 3 Interrupt Enable Mask */ 597 #define RTC_MODE1_INTENCLR_PER3(value) (RTC_MODE1_INTENCLR_PER3_Msk & (_UINT16_(value) << RTC_MODE1_INTENCLR_PER3_Pos)) /* Assignment of value for PER3 in the RTC_MODE1_INTENCLR register */ 598 #define RTC_MODE1_INTENCLR_PER4_Pos _UINT16_(4) /* (RTC_MODE1_INTENCLR) Periodic Interval 4 Interrupt Enable Position */ 599 #define RTC_MODE1_INTENCLR_PER4_Msk (_UINT16_(0x1) << RTC_MODE1_INTENCLR_PER4_Pos) /* (RTC_MODE1_INTENCLR) Periodic Interval 4 Interrupt Enable Mask */ 600 #define RTC_MODE1_INTENCLR_PER4(value) (RTC_MODE1_INTENCLR_PER4_Msk & (_UINT16_(value) << RTC_MODE1_INTENCLR_PER4_Pos)) /* Assignment of value for PER4 in the RTC_MODE1_INTENCLR register */ 601 #define RTC_MODE1_INTENCLR_PER5_Pos _UINT16_(5) /* (RTC_MODE1_INTENCLR) Periodic Interval 5 Interrupt Enable Position */ 602 #define RTC_MODE1_INTENCLR_PER5_Msk (_UINT16_(0x1) << RTC_MODE1_INTENCLR_PER5_Pos) /* (RTC_MODE1_INTENCLR) Periodic Interval 5 Interrupt Enable Mask */ 603 #define RTC_MODE1_INTENCLR_PER5(value) (RTC_MODE1_INTENCLR_PER5_Msk & (_UINT16_(value) << RTC_MODE1_INTENCLR_PER5_Pos)) /* Assignment of value for PER5 in the RTC_MODE1_INTENCLR register */ 604 #define RTC_MODE1_INTENCLR_PER6_Pos _UINT16_(6) /* (RTC_MODE1_INTENCLR) Periodic Interval 6 Interrupt Enable Position */ 605 #define RTC_MODE1_INTENCLR_PER6_Msk (_UINT16_(0x1) << RTC_MODE1_INTENCLR_PER6_Pos) /* (RTC_MODE1_INTENCLR) Periodic Interval 6 Interrupt Enable Mask */ 606 #define RTC_MODE1_INTENCLR_PER6(value) (RTC_MODE1_INTENCLR_PER6_Msk & (_UINT16_(value) << RTC_MODE1_INTENCLR_PER6_Pos)) /* Assignment of value for PER6 in the RTC_MODE1_INTENCLR register */ 607 #define RTC_MODE1_INTENCLR_PER7_Pos _UINT16_(7) /* (RTC_MODE1_INTENCLR) Periodic Interval 7 Interrupt Enable Position */ 608 #define RTC_MODE1_INTENCLR_PER7_Msk (_UINT16_(0x1) << RTC_MODE1_INTENCLR_PER7_Pos) /* (RTC_MODE1_INTENCLR) Periodic Interval 7 Interrupt Enable Mask */ 609 #define RTC_MODE1_INTENCLR_PER7(value) (RTC_MODE1_INTENCLR_PER7_Msk & (_UINT16_(value) << RTC_MODE1_INTENCLR_PER7_Pos)) /* Assignment of value for PER7 in the RTC_MODE1_INTENCLR register */ 610 #define RTC_MODE1_INTENCLR_CMP0_Pos _UINT16_(8) /* (RTC_MODE1_INTENCLR) Compare 0 Interrupt Enable Position */ 611 #define RTC_MODE1_INTENCLR_CMP0_Msk (_UINT16_(0x1) << RTC_MODE1_INTENCLR_CMP0_Pos) /* (RTC_MODE1_INTENCLR) Compare 0 Interrupt Enable Mask */ 612 #define RTC_MODE1_INTENCLR_CMP0(value) (RTC_MODE1_INTENCLR_CMP0_Msk & (_UINT16_(value) << RTC_MODE1_INTENCLR_CMP0_Pos)) /* Assignment of value for CMP0 in the RTC_MODE1_INTENCLR register */ 613 #define RTC_MODE1_INTENCLR_CMP1_Pos _UINT16_(9) /* (RTC_MODE1_INTENCLR) Compare 1 Interrupt Enable Position */ 614 #define RTC_MODE1_INTENCLR_CMP1_Msk (_UINT16_(0x1) << RTC_MODE1_INTENCLR_CMP1_Pos) /* (RTC_MODE1_INTENCLR) Compare 1 Interrupt Enable Mask */ 615 #define RTC_MODE1_INTENCLR_CMP1(value) (RTC_MODE1_INTENCLR_CMP1_Msk & (_UINT16_(value) << RTC_MODE1_INTENCLR_CMP1_Pos)) /* Assignment of value for CMP1 in the RTC_MODE1_INTENCLR register */ 616 #define RTC_MODE1_INTENCLR_CMP2_Pos _UINT16_(10) /* (RTC_MODE1_INTENCLR) Compare 2 Interrupt Enable Position */ 617 #define RTC_MODE1_INTENCLR_CMP2_Msk (_UINT16_(0x1) << RTC_MODE1_INTENCLR_CMP2_Pos) /* (RTC_MODE1_INTENCLR) Compare 2 Interrupt Enable Mask */ 618 #define RTC_MODE1_INTENCLR_CMP2(value) (RTC_MODE1_INTENCLR_CMP2_Msk & (_UINT16_(value) << RTC_MODE1_INTENCLR_CMP2_Pos)) /* Assignment of value for CMP2 in the RTC_MODE1_INTENCLR register */ 619 #define RTC_MODE1_INTENCLR_CMP3_Pos _UINT16_(11) /* (RTC_MODE1_INTENCLR) Compare 3 Interrupt Enable Position */ 620 #define RTC_MODE1_INTENCLR_CMP3_Msk (_UINT16_(0x1) << RTC_MODE1_INTENCLR_CMP3_Pos) /* (RTC_MODE1_INTENCLR) Compare 3 Interrupt Enable Mask */ 621 #define RTC_MODE1_INTENCLR_CMP3(value) (RTC_MODE1_INTENCLR_CMP3_Msk & (_UINT16_(value) << RTC_MODE1_INTENCLR_CMP3_Pos)) /* Assignment of value for CMP3 in the RTC_MODE1_INTENCLR register */ 622 #define RTC_MODE1_INTENCLR_TAMPER_Pos _UINT16_(14) /* (RTC_MODE1_INTENCLR) Tamper Enable Position */ 623 #define RTC_MODE1_INTENCLR_TAMPER_Msk (_UINT16_(0x1) << RTC_MODE1_INTENCLR_TAMPER_Pos) /* (RTC_MODE1_INTENCLR) Tamper Enable Mask */ 624 #define RTC_MODE1_INTENCLR_TAMPER(value) (RTC_MODE1_INTENCLR_TAMPER_Msk & (_UINT16_(value) << RTC_MODE1_INTENCLR_TAMPER_Pos)) /* Assignment of value for TAMPER in the RTC_MODE1_INTENCLR register */ 625 #define RTC_MODE1_INTENCLR_OVF_Pos _UINT16_(15) /* (RTC_MODE1_INTENCLR) Overflow Interrupt Enable Position */ 626 #define RTC_MODE1_INTENCLR_OVF_Msk (_UINT16_(0x1) << RTC_MODE1_INTENCLR_OVF_Pos) /* (RTC_MODE1_INTENCLR) Overflow Interrupt Enable Mask */ 627 #define RTC_MODE1_INTENCLR_OVF(value) (RTC_MODE1_INTENCLR_OVF_Msk & (_UINT16_(value) << RTC_MODE1_INTENCLR_OVF_Pos)) /* Assignment of value for OVF in the RTC_MODE1_INTENCLR register */ 628 #define RTC_MODE1_INTENCLR_Msk _UINT16_(0xCFFF) /* (RTC_MODE1_INTENCLR) Register Mask */ 629 630 #define RTC_MODE1_INTENCLR_PER_Pos _UINT16_(0) /* (RTC_MODE1_INTENCLR Position) Periodic Interval x Interrupt Enable */ 631 #define RTC_MODE1_INTENCLR_PER_Msk (_UINT16_(0xFF) << RTC_MODE1_INTENCLR_PER_Pos) /* (RTC_MODE1_INTENCLR Mask) PER */ 632 #define RTC_MODE1_INTENCLR_PER(value) (RTC_MODE1_INTENCLR_PER_Msk & (_UINT16_(value) << RTC_MODE1_INTENCLR_PER_Pos)) 633 #define RTC_MODE1_INTENCLR_CMP_Pos _UINT16_(8) /* (RTC_MODE1_INTENCLR Position) Compare x Interrupt Enable */ 634 #define RTC_MODE1_INTENCLR_CMP_Msk (_UINT16_(0xF) << RTC_MODE1_INTENCLR_CMP_Pos) /* (RTC_MODE1_INTENCLR Mask) CMP */ 635 #define RTC_MODE1_INTENCLR_CMP(value) (RTC_MODE1_INTENCLR_CMP_Msk & (_UINT16_(value) << RTC_MODE1_INTENCLR_CMP_Pos)) 636 637 /* -------- RTC_MODE2_INTENCLR : (RTC Offset: 0x08) (R/W 16) MODE2 Interrupt Enable Clear -------- */ 638 #define RTC_MODE2_INTENCLR_RESETVALUE _UINT16_(0x00) /* (RTC_MODE2_INTENCLR) MODE2 Interrupt Enable Clear Reset Value */ 639 640 #define RTC_MODE2_INTENCLR_PER0_Pos _UINT16_(0) /* (RTC_MODE2_INTENCLR) Periodic Interval 0 Interrupt Enable Position */ 641 #define RTC_MODE2_INTENCLR_PER0_Msk (_UINT16_(0x1) << RTC_MODE2_INTENCLR_PER0_Pos) /* (RTC_MODE2_INTENCLR) Periodic Interval 0 Interrupt Enable Mask */ 642 #define RTC_MODE2_INTENCLR_PER0(value) (RTC_MODE2_INTENCLR_PER0_Msk & (_UINT16_(value) << RTC_MODE2_INTENCLR_PER0_Pos)) /* Assignment of value for PER0 in the RTC_MODE2_INTENCLR register */ 643 #define RTC_MODE2_INTENCLR_PER1_Pos _UINT16_(1) /* (RTC_MODE2_INTENCLR) Periodic Interval 1 Interrupt Enable Position */ 644 #define RTC_MODE2_INTENCLR_PER1_Msk (_UINT16_(0x1) << RTC_MODE2_INTENCLR_PER1_Pos) /* (RTC_MODE2_INTENCLR) Periodic Interval 1 Interrupt Enable Mask */ 645 #define RTC_MODE2_INTENCLR_PER1(value) (RTC_MODE2_INTENCLR_PER1_Msk & (_UINT16_(value) << RTC_MODE2_INTENCLR_PER1_Pos)) /* Assignment of value for PER1 in the RTC_MODE2_INTENCLR register */ 646 #define RTC_MODE2_INTENCLR_PER2_Pos _UINT16_(2) /* (RTC_MODE2_INTENCLR) Periodic Interval 2 Interrupt Enable Position */ 647 #define RTC_MODE2_INTENCLR_PER2_Msk (_UINT16_(0x1) << RTC_MODE2_INTENCLR_PER2_Pos) /* (RTC_MODE2_INTENCLR) Periodic Interval 2 Interrupt Enable Mask */ 648 #define RTC_MODE2_INTENCLR_PER2(value) (RTC_MODE2_INTENCLR_PER2_Msk & (_UINT16_(value) << RTC_MODE2_INTENCLR_PER2_Pos)) /* Assignment of value for PER2 in the RTC_MODE2_INTENCLR register */ 649 #define RTC_MODE2_INTENCLR_PER3_Pos _UINT16_(3) /* (RTC_MODE2_INTENCLR) Periodic Interval 3 Interrupt Enable Position */ 650 #define RTC_MODE2_INTENCLR_PER3_Msk (_UINT16_(0x1) << RTC_MODE2_INTENCLR_PER3_Pos) /* (RTC_MODE2_INTENCLR) Periodic Interval 3 Interrupt Enable Mask */ 651 #define RTC_MODE2_INTENCLR_PER3(value) (RTC_MODE2_INTENCLR_PER3_Msk & (_UINT16_(value) << RTC_MODE2_INTENCLR_PER3_Pos)) /* Assignment of value for PER3 in the RTC_MODE2_INTENCLR register */ 652 #define RTC_MODE2_INTENCLR_PER4_Pos _UINT16_(4) /* (RTC_MODE2_INTENCLR) Periodic Interval 4 Interrupt Enable Position */ 653 #define RTC_MODE2_INTENCLR_PER4_Msk (_UINT16_(0x1) << RTC_MODE2_INTENCLR_PER4_Pos) /* (RTC_MODE2_INTENCLR) Periodic Interval 4 Interrupt Enable Mask */ 654 #define RTC_MODE2_INTENCLR_PER4(value) (RTC_MODE2_INTENCLR_PER4_Msk & (_UINT16_(value) << RTC_MODE2_INTENCLR_PER4_Pos)) /* Assignment of value for PER4 in the RTC_MODE2_INTENCLR register */ 655 #define RTC_MODE2_INTENCLR_PER5_Pos _UINT16_(5) /* (RTC_MODE2_INTENCLR) Periodic Interval 5 Interrupt Enable Position */ 656 #define RTC_MODE2_INTENCLR_PER5_Msk (_UINT16_(0x1) << RTC_MODE2_INTENCLR_PER5_Pos) /* (RTC_MODE2_INTENCLR) Periodic Interval 5 Interrupt Enable Mask */ 657 #define RTC_MODE2_INTENCLR_PER5(value) (RTC_MODE2_INTENCLR_PER5_Msk & (_UINT16_(value) << RTC_MODE2_INTENCLR_PER5_Pos)) /* Assignment of value for PER5 in the RTC_MODE2_INTENCLR register */ 658 #define RTC_MODE2_INTENCLR_PER6_Pos _UINT16_(6) /* (RTC_MODE2_INTENCLR) Periodic Interval 6 Interrupt Enable Position */ 659 #define RTC_MODE2_INTENCLR_PER6_Msk (_UINT16_(0x1) << RTC_MODE2_INTENCLR_PER6_Pos) /* (RTC_MODE2_INTENCLR) Periodic Interval 6 Interrupt Enable Mask */ 660 #define RTC_MODE2_INTENCLR_PER6(value) (RTC_MODE2_INTENCLR_PER6_Msk & (_UINT16_(value) << RTC_MODE2_INTENCLR_PER6_Pos)) /* Assignment of value for PER6 in the RTC_MODE2_INTENCLR register */ 661 #define RTC_MODE2_INTENCLR_PER7_Pos _UINT16_(7) /* (RTC_MODE2_INTENCLR) Periodic Interval 7 Interrupt Enable Position */ 662 #define RTC_MODE2_INTENCLR_PER7_Msk (_UINT16_(0x1) << RTC_MODE2_INTENCLR_PER7_Pos) /* (RTC_MODE2_INTENCLR) Periodic Interval 7 Interrupt Enable Mask */ 663 #define RTC_MODE2_INTENCLR_PER7(value) (RTC_MODE2_INTENCLR_PER7_Msk & (_UINT16_(value) << RTC_MODE2_INTENCLR_PER7_Pos)) /* Assignment of value for PER7 in the RTC_MODE2_INTENCLR register */ 664 #define RTC_MODE2_INTENCLR_ALARM0_Pos _UINT16_(8) /* (RTC_MODE2_INTENCLR) Alarm 0 Interrupt Enable Position */ 665 #define RTC_MODE2_INTENCLR_ALARM0_Msk (_UINT16_(0x1) << RTC_MODE2_INTENCLR_ALARM0_Pos) /* (RTC_MODE2_INTENCLR) Alarm 0 Interrupt Enable Mask */ 666 #define RTC_MODE2_INTENCLR_ALARM0(value) (RTC_MODE2_INTENCLR_ALARM0_Msk & (_UINT16_(value) << RTC_MODE2_INTENCLR_ALARM0_Pos)) /* Assignment of value for ALARM0 in the RTC_MODE2_INTENCLR register */ 667 #define RTC_MODE2_INTENCLR_ALARM1_Pos _UINT16_(9) /* (RTC_MODE2_INTENCLR) Alarm 1 Interrupt Enable Position */ 668 #define RTC_MODE2_INTENCLR_ALARM1_Msk (_UINT16_(0x1) << RTC_MODE2_INTENCLR_ALARM1_Pos) /* (RTC_MODE2_INTENCLR) Alarm 1 Interrupt Enable Mask */ 669 #define RTC_MODE2_INTENCLR_ALARM1(value) (RTC_MODE2_INTENCLR_ALARM1_Msk & (_UINT16_(value) << RTC_MODE2_INTENCLR_ALARM1_Pos)) /* Assignment of value for ALARM1 in the RTC_MODE2_INTENCLR register */ 670 #define RTC_MODE2_INTENCLR_TAMPER_Pos _UINT16_(14) /* (RTC_MODE2_INTENCLR) Tamper Enable Position */ 671 #define RTC_MODE2_INTENCLR_TAMPER_Msk (_UINT16_(0x1) << RTC_MODE2_INTENCLR_TAMPER_Pos) /* (RTC_MODE2_INTENCLR) Tamper Enable Mask */ 672 #define RTC_MODE2_INTENCLR_TAMPER(value) (RTC_MODE2_INTENCLR_TAMPER_Msk & (_UINT16_(value) << RTC_MODE2_INTENCLR_TAMPER_Pos)) /* Assignment of value for TAMPER in the RTC_MODE2_INTENCLR register */ 673 #define RTC_MODE2_INTENCLR_OVF_Pos _UINT16_(15) /* (RTC_MODE2_INTENCLR) Overflow Interrupt Enable Position */ 674 #define RTC_MODE2_INTENCLR_OVF_Msk (_UINT16_(0x1) << RTC_MODE2_INTENCLR_OVF_Pos) /* (RTC_MODE2_INTENCLR) Overflow Interrupt Enable Mask */ 675 #define RTC_MODE2_INTENCLR_OVF(value) (RTC_MODE2_INTENCLR_OVF_Msk & (_UINT16_(value) << RTC_MODE2_INTENCLR_OVF_Pos)) /* Assignment of value for OVF in the RTC_MODE2_INTENCLR register */ 676 #define RTC_MODE2_INTENCLR_Msk _UINT16_(0xC3FF) /* (RTC_MODE2_INTENCLR) Register Mask */ 677 678 #define RTC_MODE2_INTENCLR_PER_Pos _UINT16_(0) /* (RTC_MODE2_INTENCLR Position) Periodic Interval x Interrupt Enable */ 679 #define RTC_MODE2_INTENCLR_PER_Msk (_UINT16_(0xFF) << RTC_MODE2_INTENCLR_PER_Pos) /* (RTC_MODE2_INTENCLR Mask) PER */ 680 #define RTC_MODE2_INTENCLR_PER(value) (RTC_MODE2_INTENCLR_PER_Msk & (_UINT16_(value) << RTC_MODE2_INTENCLR_PER_Pos)) 681 #define RTC_MODE2_INTENCLR_ALARM_Pos _UINT16_(8) /* (RTC_MODE2_INTENCLR Position) Alarm x Interrupt Enable */ 682 #define RTC_MODE2_INTENCLR_ALARM_Msk (_UINT16_(0x3) << RTC_MODE2_INTENCLR_ALARM_Pos) /* (RTC_MODE2_INTENCLR Mask) ALARM */ 683 #define RTC_MODE2_INTENCLR_ALARM(value) (RTC_MODE2_INTENCLR_ALARM_Msk & (_UINT16_(value) << RTC_MODE2_INTENCLR_ALARM_Pos)) 684 685 /* -------- RTC_MODE0_INTENSET : (RTC Offset: 0x0A) (R/W 16) MODE0 Interrupt Enable Set -------- */ 686 #define RTC_MODE0_INTENSET_RESETVALUE _UINT16_(0x00) /* (RTC_MODE0_INTENSET) MODE0 Interrupt Enable Set Reset Value */ 687 688 #define RTC_MODE0_INTENSET_PER0_Pos _UINT16_(0) /* (RTC_MODE0_INTENSET) Periodic Interval 0 Interrupt Enable Position */ 689 #define RTC_MODE0_INTENSET_PER0_Msk (_UINT16_(0x1) << RTC_MODE0_INTENSET_PER0_Pos) /* (RTC_MODE0_INTENSET) Periodic Interval 0 Interrupt Enable Mask */ 690 #define RTC_MODE0_INTENSET_PER0(value) (RTC_MODE0_INTENSET_PER0_Msk & (_UINT16_(value) << RTC_MODE0_INTENSET_PER0_Pos)) /* Assignment of value for PER0 in the RTC_MODE0_INTENSET register */ 691 #define RTC_MODE0_INTENSET_PER1_Pos _UINT16_(1) /* (RTC_MODE0_INTENSET) Periodic Interval 1 Interrupt Enable Position */ 692 #define RTC_MODE0_INTENSET_PER1_Msk (_UINT16_(0x1) << RTC_MODE0_INTENSET_PER1_Pos) /* (RTC_MODE0_INTENSET) Periodic Interval 1 Interrupt Enable Mask */ 693 #define RTC_MODE0_INTENSET_PER1(value) (RTC_MODE0_INTENSET_PER1_Msk & (_UINT16_(value) << RTC_MODE0_INTENSET_PER1_Pos)) /* Assignment of value for PER1 in the RTC_MODE0_INTENSET register */ 694 #define RTC_MODE0_INTENSET_PER2_Pos _UINT16_(2) /* (RTC_MODE0_INTENSET) Periodic Interval 2 Interrupt Enable Position */ 695 #define RTC_MODE0_INTENSET_PER2_Msk (_UINT16_(0x1) << RTC_MODE0_INTENSET_PER2_Pos) /* (RTC_MODE0_INTENSET) Periodic Interval 2 Interrupt Enable Mask */ 696 #define RTC_MODE0_INTENSET_PER2(value) (RTC_MODE0_INTENSET_PER2_Msk & (_UINT16_(value) << RTC_MODE0_INTENSET_PER2_Pos)) /* Assignment of value for PER2 in the RTC_MODE0_INTENSET register */ 697 #define RTC_MODE0_INTENSET_PER3_Pos _UINT16_(3) /* (RTC_MODE0_INTENSET) Periodic Interval 3 Interrupt Enable Position */ 698 #define RTC_MODE0_INTENSET_PER3_Msk (_UINT16_(0x1) << RTC_MODE0_INTENSET_PER3_Pos) /* (RTC_MODE0_INTENSET) Periodic Interval 3 Interrupt Enable Mask */ 699 #define RTC_MODE0_INTENSET_PER3(value) (RTC_MODE0_INTENSET_PER3_Msk & (_UINT16_(value) << RTC_MODE0_INTENSET_PER3_Pos)) /* Assignment of value for PER3 in the RTC_MODE0_INTENSET register */ 700 #define RTC_MODE0_INTENSET_PER4_Pos _UINT16_(4) /* (RTC_MODE0_INTENSET) Periodic Interval 4 Interrupt Enable Position */ 701 #define RTC_MODE0_INTENSET_PER4_Msk (_UINT16_(0x1) << RTC_MODE0_INTENSET_PER4_Pos) /* (RTC_MODE0_INTENSET) Periodic Interval 4 Interrupt Enable Mask */ 702 #define RTC_MODE0_INTENSET_PER4(value) (RTC_MODE0_INTENSET_PER4_Msk & (_UINT16_(value) << RTC_MODE0_INTENSET_PER4_Pos)) /* Assignment of value for PER4 in the RTC_MODE0_INTENSET register */ 703 #define RTC_MODE0_INTENSET_PER5_Pos _UINT16_(5) /* (RTC_MODE0_INTENSET) Periodic Interval 5 Interrupt Enable Position */ 704 #define RTC_MODE0_INTENSET_PER5_Msk (_UINT16_(0x1) << RTC_MODE0_INTENSET_PER5_Pos) /* (RTC_MODE0_INTENSET) Periodic Interval 5 Interrupt Enable Mask */ 705 #define RTC_MODE0_INTENSET_PER5(value) (RTC_MODE0_INTENSET_PER5_Msk & (_UINT16_(value) << RTC_MODE0_INTENSET_PER5_Pos)) /* Assignment of value for PER5 in the RTC_MODE0_INTENSET register */ 706 #define RTC_MODE0_INTENSET_PER6_Pos _UINT16_(6) /* (RTC_MODE0_INTENSET) Periodic Interval 6 Interrupt Enable Position */ 707 #define RTC_MODE0_INTENSET_PER6_Msk (_UINT16_(0x1) << RTC_MODE0_INTENSET_PER6_Pos) /* (RTC_MODE0_INTENSET) Periodic Interval 6 Interrupt Enable Mask */ 708 #define RTC_MODE0_INTENSET_PER6(value) (RTC_MODE0_INTENSET_PER6_Msk & (_UINT16_(value) << RTC_MODE0_INTENSET_PER6_Pos)) /* Assignment of value for PER6 in the RTC_MODE0_INTENSET register */ 709 #define RTC_MODE0_INTENSET_PER7_Pos _UINT16_(7) /* (RTC_MODE0_INTENSET) Periodic Interval 7 Interrupt Enable Position */ 710 #define RTC_MODE0_INTENSET_PER7_Msk (_UINT16_(0x1) << RTC_MODE0_INTENSET_PER7_Pos) /* (RTC_MODE0_INTENSET) Periodic Interval 7 Interrupt Enable Mask */ 711 #define RTC_MODE0_INTENSET_PER7(value) (RTC_MODE0_INTENSET_PER7_Msk & (_UINT16_(value) << RTC_MODE0_INTENSET_PER7_Pos)) /* Assignment of value for PER7 in the RTC_MODE0_INTENSET register */ 712 #define RTC_MODE0_INTENSET_CMP0_Pos _UINT16_(8) /* (RTC_MODE0_INTENSET) Compare 0 Interrupt Enable Position */ 713 #define RTC_MODE0_INTENSET_CMP0_Msk (_UINT16_(0x1) << RTC_MODE0_INTENSET_CMP0_Pos) /* (RTC_MODE0_INTENSET) Compare 0 Interrupt Enable Mask */ 714 #define RTC_MODE0_INTENSET_CMP0(value) (RTC_MODE0_INTENSET_CMP0_Msk & (_UINT16_(value) << RTC_MODE0_INTENSET_CMP0_Pos)) /* Assignment of value for CMP0 in the RTC_MODE0_INTENSET register */ 715 #define RTC_MODE0_INTENSET_CMP1_Pos _UINT16_(9) /* (RTC_MODE0_INTENSET) Compare 1 Interrupt Enable Position */ 716 #define RTC_MODE0_INTENSET_CMP1_Msk (_UINT16_(0x1) << RTC_MODE0_INTENSET_CMP1_Pos) /* (RTC_MODE0_INTENSET) Compare 1 Interrupt Enable Mask */ 717 #define RTC_MODE0_INTENSET_CMP1(value) (RTC_MODE0_INTENSET_CMP1_Msk & (_UINT16_(value) << RTC_MODE0_INTENSET_CMP1_Pos)) /* Assignment of value for CMP1 in the RTC_MODE0_INTENSET register */ 718 #define RTC_MODE0_INTENSET_TAMPER_Pos _UINT16_(14) /* (RTC_MODE0_INTENSET) Tamper Enable Position */ 719 #define RTC_MODE0_INTENSET_TAMPER_Msk (_UINT16_(0x1) << RTC_MODE0_INTENSET_TAMPER_Pos) /* (RTC_MODE0_INTENSET) Tamper Enable Mask */ 720 #define RTC_MODE0_INTENSET_TAMPER(value) (RTC_MODE0_INTENSET_TAMPER_Msk & (_UINT16_(value) << RTC_MODE0_INTENSET_TAMPER_Pos)) /* Assignment of value for TAMPER in the RTC_MODE0_INTENSET register */ 721 #define RTC_MODE0_INTENSET_OVF_Pos _UINT16_(15) /* (RTC_MODE0_INTENSET) Overflow Interrupt Enable Position */ 722 #define RTC_MODE0_INTENSET_OVF_Msk (_UINT16_(0x1) << RTC_MODE0_INTENSET_OVF_Pos) /* (RTC_MODE0_INTENSET) Overflow Interrupt Enable Mask */ 723 #define RTC_MODE0_INTENSET_OVF(value) (RTC_MODE0_INTENSET_OVF_Msk & (_UINT16_(value) << RTC_MODE0_INTENSET_OVF_Pos)) /* Assignment of value for OVF in the RTC_MODE0_INTENSET register */ 724 #define RTC_MODE0_INTENSET_Msk _UINT16_(0xC3FF) /* (RTC_MODE0_INTENSET) Register Mask */ 725 726 #define RTC_MODE0_INTENSET_PER_Pos _UINT16_(0) /* (RTC_MODE0_INTENSET Position) Periodic Interval x Interrupt Enable */ 727 #define RTC_MODE0_INTENSET_PER_Msk (_UINT16_(0xFF) << RTC_MODE0_INTENSET_PER_Pos) /* (RTC_MODE0_INTENSET Mask) PER */ 728 #define RTC_MODE0_INTENSET_PER(value) (RTC_MODE0_INTENSET_PER_Msk & (_UINT16_(value) << RTC_MODE0_INTENSET_PER_Pos)) 729 #define RTC_MODE0_INTENSET_CMP_Pos _UINT16_(8) /* (RTC_MODE0_INTENSET Position) Compare x Interrupt Enable */ 730 #define RTC_MODE0_INTENSET_CMP_Msk (_UINT16_(0x3) << RTC_MODE0_INTENSET_CMP_Pos) /* (RTC_MODE0_INTENSET Mask) CMP */ 731 #define RTC_MODE0_INTENSET_CMP(value) (RTC_MODE0_INTENSET_CMP_Msk & (_UINT16_(value) << RTC_MODE0_INTENSET_CMP_Pos)) 732 733 /* -------- RTC_MODE1_INTENSET : (RTC Offset: 0x0A) (R/W 16) MODE1 Interrupt Enable Set -------- */ 734 #define RTC_MODE1_INTENSET_RESETVALUE _UINT16_(0x00) /* (RTC_MODE1_INTENSET) MODE1 Interrupt Enable Set Reset Value */ 735 736 #define RTC_MODE1_INTENSET_PER0_Pos _UINT16_(0) /* (RTC_MODE1_INTENSET) Periodic Interval 0 Interrupt Enable Position */ 737 #define RTC_MODE1_INTENSET_PER0_Msk (_UINT16_(0x1) << RTC_MODE1_INTENSET_PER0_Pos) /* (RTC_MODE1_INTENSET) Periodic Interval 0 Interrupt Enable Mask */ 738 #define RTC_MODE1_INTENSET_PER0(value) (RTC_MODE1_INTENSET_PER0_Msk & (_UINT16_(value) << RTC_MODE1_INTENSET_PER0_Pos)) /* Assignment of value for PER0 in the RTC_MODE1_INTENSET register */ 739 #define RTC_MODE1_INTENSET_PER1_Pos _UINT16_(1) /* (RTC_MODE1_INTENSET) Periodic Interval 1 Interrupt Enable Position */ 740 #define RTC_MODE1_INTENSET_PER1_Msk (_UINT16_(0x1) << RTC_MODE1_INTENSET_PER1_Pos) /* (RTC_MODE1_INTENSET) Periodic Interval 1 Interrupt Enable Mask */ 741 #define RTC_MODE1_INTENSET_PER1(value) (RTC_MODE1_INTENSET_PER1_Msk & (_UINT16_(value) << RTC_MODE1_INTENSET_PER1_Pos)) /* Assignment of value for PER1 in the RTC_MODE1_INTENSET register */ 742 #define RTC_MODE1_INTENSET_PER2_Pos _UINT16_(2) /* (RTC_MODE1_INTENSET) Periodic Interval 2 Interrupt Enable Position */ 743 #define RTC_MODE1_INTENSET_PER2_Msk (_UINT16_(0x1) << RTC_MODE1_INTENSET_PER2_Pos) /* (RTC_MODE1_INTENSET) Periodic Interval 2 Interrupt Enable Mask */ 744 #define RTC_MODE1_INTENSET_PER2(value) (RTC_MODE1_INTENSET_PER2_Msk & (_UINT16_(value) << RTC_MODE1_INTENSET_PER2_Pos)) /* Assignment of value for PER2 in the RTC_MODE1_INTENSET register */ 745 #define RTC_MODE1_INTENSET_PER3_Pos _UINT16_(3) /* (RTC_MODE1_INTENSET) Periodic Interval 3 Interrupt Enable Position */ 746 #define RTC_MODE1_INTENSET_PER3_Msk (_UINT16_(0x1) << RTC_MODE1_INTENSET_PER3_Pos) /* (RTC_MODE1_INTENSET) Periodic Interval 3 Interrupt Enable Mask */ 747 #define RTC_MODE1_INTENSET_PER3(value) (RTC_MODE1_INTENSET_PER3_Msk & (_UINT16_(value) << RTC_MODE1_INTENSET_PER3_Pos)) /* Assignment of value for PER3 in the RTC_MODE1_INTENSET register */ 748 #define RTC_MODE1_INTENSET_PER4_Pos _UINT16_(4) /* (RTC_MODE1_INTENSET) Periodic Interval 4 Interrupt Enable Position */ 749 #define RTC_MODE1_INTENSET_PER4_Msk (_UINT16_(0x1) << RTC_MODE1_INTENSET_PER4_Pos) /* (RTC_MODE1_INTENSET) Periodic Interval 4 Interrupt Enable Mask */ 750 #define RTC_MODE1_INTENSET_PER4(value) (RTC_MODE1_INTENSET_PER4_Msk & (_UINT16_(value) << RTC_MODE1_INTENSET_PER4_Pos)) /* Assignment of value for PER4 in the RTC_MODE1_INTENSET register */ 751 #define RTC_MODE1_INTENSET_PER5_Pos _UINT16_(5) /* (RTC_MODE1_INTENSET) Periodic Interval 5 Interrupt Enable Position */ 752 #define RTC_MODE1_INTENSET_PER5_Msk (_UINT16_(0x1) << RTC_MODE1_INTENSET_PER5_Pos) /* (RTC_MODE1_INTENSET) Periodic Interval 5 Interrupt Enable Mask */ 753 #define RTC_MODE1_INTENSET_PER5(value) (RTC_MODE1_INTENSET_PER5_Msk & (_UINT16_(value) << RTC_MODE1_INTENSET_PER5_Pos)) /* Assignment of value for PER5 in the RTC_MODE1_INTENSET register */ 754 #define RTC_MODE1_INTENSET_PER6_Pos _UINT16_(6) /* (RTC_MODE1_INTENSET) Periodic Interval 6 Interrupt Enable Position */ 755 #define RTC_MODE1_INTENSET_PER6_Msk (_UINT16_(0x1) << RTC_MODE1_INTENSET_PER6_Pos) /* (RTC_MODE1_INTENSET) Periodic Interval 6 Interrupt Enable Mask */ 756 #define RTC_MODE1_INTENSET_PER6(value) (RTC_MODE1_INTENSET_PER6_Msk & (_UINT16_(value) << RTC_MODE1_INTENSET_PER6_Pos)) /* Assignment of value for PER6 in the RTC_MODE1_INTENSET register */ 757 #define RTC_MODE1_INTENSET_PER7_Pos _UINT16_(7) /* (RTC_MODE1_INTENSET) Periodic Interval 7 Interrupt Enable Position */ 758 #define RTC_MODE1_INTENSET_PER7_Msk (_UINT16_(0x1) << RTC_MODE1_INTENSET_PER7_Pos) /* (RTC_MODE1_INTENSET) Periodic Interval 7 Interrupt Enable Mask */ 759 #define RTC_MODE1_INTENSET_PER7(value) (RTC_MODE1_INTENSET_PER7_Msk & (_UINT16_(value) << RTC_MODE1_INTENSET_PER7_Pos)) /* Assignment of value for PER7 in the RTC_MODE1_INTENSET register */ 760 #define RTC_MODE1_INTENSET_CMP0_Pos _UINT16_(8) /* (RTC_MODE1_INTENSET) Compare 0 Interrupt Enable Position */ 761 #define RTC_MODE1_INTENSET_CMP0_Msk (_UINT16_(0x1) << RTC_MODE1_INTENSET_CMP0_Pos) /* (RTC_MODE1_INTENSET) Compare 0 Interrupt Enable Mask */ 762 #define RTC_MODE1_INTENSET_CMP0(value) (RTC_MODE1_INTENSET_CMP0_Msk & (_UINT16_(value) << RTC_MODE1_INTENSET_CMP0_Pos)) /* Assignment of value for CMP0 in the RTC_MODE1_INTENSET register */ 763 #define RTC_MODE1_INTENSET_CMP1_Pos _UINT16_(9) /* (RTC_MODE1_INTENSET) Compare 1 Interrupt Enable Position */ 764 #define RTC_MODE1_INTENSET_CMP1_Msk (_UINT16_(0x1) << RTC_MODE1_INTENSET_CMP1_Pos) /* (RTC_MODE1_INTENSET) Compare 1 Interrupt Enable Mask */ 765 #define RTC_MODE1_INTENSET_CMP1(value) (RTC_MODE1_INTENSET_CMP1_Msk & (_UINT16_(value) << RTC_MODE1_INTENSET_CMP1_Pos)) /* Assignment of value for CMP1 in the RTC_MODE1_INTENSET register */ 766 #define RTC_MODE1_INTENSET_CMP2_Pos _UINT16_(10) /* (RTC_MODE1_INTENSET) Compare 2 Interrupt Enable Position */ 767 #define RTC_MODE1_INTENSET_CMP2_Msk (_UINT16_(0x1) << RTC_MODE1_INTENSET_CMP2_Pos) /* (RTC_MODE1_INTENSET) Compare 2 Interrupt Enable Mask */ 768 #define RTC_MODE1_INTENSET_CMP2(value) (RTC_MODE1_INTENSET_CMP2_Msk & (_UINT16_(value) << RTC_MODE1_INTENSET_CMP2_Pos)) /* Assignment of value for CMP2 in the RTC_MODE1_INTENSET register */ 769 #define RTC_MODE1_INTENSET_CMP3_Pos _UINT16_(11) /* (RTC_MODE1_INTENSET) Compare 3 Interrupt Enable Position */ 770 #define RTC_MODE1_INTENSET_CMP3_Msk (_UINT16_(0x1) << RTC_MODE1_INTENSET_CMP3_Pos) /* (RTC_MODE1_INTENSET) Compare 3 Interrupt Enable Mask */ 771 #define RTC_MODE1_INTENSET_CMP3(value) (RTC_MODE1_INTENSET_CMP3_Msk & (_UINT16_(value) << RTC_MODE1_INTENSET_CMP3_Pos)) /* Assignment of value for CMP3 in the RTC_MODE1_INTENSET register */ 772 #define RTC_MODE1_INTENSET_TAMPER_Pos _UINT16_(14) /* (RTC_MODE1_INTENSET) Tamper Enable Position */ 773 #define RTC_MODE1_INTENSET_TAMPER_Msk (_UINT16_(0x1) << RTC_MODE1_INTENSET_TAMPER_Pos) /* (RTC_MODE1_INTENSET) Tamper Enable Mask */ 774 #define RTC_MODE1_INTENSET_TAMPER(value) (RTC_MODE1_INTENSET_TAMPER_Msk & (_UINT16_(value) << RTC_MODE1_INTENSET_TAMPER_Pos)) /* Assignment of value for TAMPER in the RTC_MODE1_INTENSET register */ 775 #define RTC_MODE1_INTENSET_OVF_Pos _UINT16_(15) /* (RTC_MODE1_INTENSET) Overflow Interrupt Enable Position */ 776 #define RTC_MODE1_INTENSET_OVF_Msk (_UINT16_(0x1) << RTC_MODE1_INTENSET_OVF_Pos) /* (RTC_MODE1_INTENSET) Overflow Interrupt Enable Mask */ 777 #define RTC_MODE1_INTENSET_OVF(value) (RTC_MODE1_INTENSET_OVF_Msk & (_UINT16_(value) << RTC_MODE1_INTENSET_OVF_Pos)) /* Assignment of value for OVF in the RTC_MODE1_INTENSET register */ 778 #define RTC_MODE1_INTENSET_Msk _UINT16_(0xCFFF) /* (RTC_MODE1_INTENSET) Register Mask */ 779 780 #define RTC_MODE1_INTENSET_PER_Pos _UINT16_(0) /* (RTC_MODE1_INTENSET Position) Periodic Interval x Interrupt Enable */ 781 #define RTC_MODE1_INTENSET_PER_Msk (_UINT16_(0xFF) << RTC_MODE1_INTENSET_PER_Pos) /* (RTC_MODE1_INTENSET Mask) PER */ 782 #define RTC_MODE1_INTENSET_PER(value) (RTC_MODE1_INTENSET_PER_Msk & (_UINT16_(value) << RTC_MODE1_INTENSET_PER_Pos)) 783 #define RTC_MODE1_INTENSET_CMP_Pos _UINT16_(8) /* (RTC_MODE1_INTENSET Position) Compare x Interrupt Enable */ 784 #define RTC_MODE1_INTENSET_CMP_Msk (_UINT16_(0xF) << RTC_MODE1_INTENSET_CMP_Pos) /* (RTC_MODE1_INTENSET Mask) CMP */ 785 #define RTC_MODE1_INTENSET_CMP(value) (RTC_MODE1_INTENSET_CMP_Msk & (_UINT16_(value) << RTC_MODE1_INTENSET_CMP_Pos)) 786 787 /* -------- RTC_MODE2_INTENSET : (RTC Offset: 0x0A) (R/W 16) MODE2 Interrupt Enable Set -------- */ 788 #define RTC_MODE2_INTENSET_RESETVALUE _UINT16_(0x00) /* (RTC_MODE2_INTENSET) MODE2 Interrupt Enable Set Reset Value */ 789 790 #define RTC_MODE2_INTENSET_PER0_Pos _UINT16_(0) /* (RTC_MODE2_INTENSET) Periodic Interval 0 Enable Position */ 791 #define RTC_MODE2_INTENSET_PER0_Msk (_UINT16_(0x1) << RTC_MODE2_INTENSET_PER0_Pos) /* (RTC_MODE2_INTENSET) Periodic Interval 0 Enable Mask */ 792 #define RTC_MODE2_INTENSET_PER0(value) (RTC_MODE2_INTENSET_PER0_Msk & (_UINT16_(value) << RTC_MODE2_INTENSET_PER0_Pos)) /* Assignment of value for PER0 in the RTC_MODE2_INTENSET register */ 793 #define RTC_MODE2_INTENSET_PER1_Pos _UINT16_(1) /* (RTC_MODE2_INTENSET) Periodic Interval 1 Enable Position */ 794 #define RTC_MODE2_INTENSET_PER1_Msk (_UINT16_(0x1) << RTC_MODE2_INTENSET_PER1_Pos) /* (RTC_MODE2_INTENSET) Periodic Interval 1 Enable Mask */ 795 #define RTC_MODE2_INTENSET_PER1(value) (RTC_MODE2_INTENSET_PER1_Msk & (_UINT16_(value) << RTC_MODE2_INTENSET_PER1_Pos)) /* Assignment of value for PER1 in the RTC_MODE2_INTENSET register */ 796 #define RTC_MODE2_INTENSET_PER2_Pos _UINT16_(2) /* (RTC_MODE2_INTENSET) Periodic Interval 2 Enable Position */ 797 #define RTC_MODE2_INTENSET_PER2_Msk (_UINT16_(0x1) << RTC_MODE2_INTENSET_PER2_Pos) /* (RTC_MODE2_INTENSET) Periodic Interval 2 Enable Mask */ 798 #define RTC_MODE2_INTENSET_PER2(value) (RTC_MODE2_INTENSET_PER2_Msk & (_UINT16_(value) << RTC_MODE2_INTENSET_PER2_Pos)) /* Assignment of value for PER2 in the RTC_MODE2_INTENSET register */ 799 #define RTC_MODE2_INTENSET_PER3_Pos _UINT16_(3) /* (RTC_MODE2_INTENSET) Periodic Interval 3 Enable Position */ 800 #define RTC_MODE2_INTENSET_PER3_Msk (_UINT16_(0x1) << RTC_MODE2_INTENSET_PER3_Pos) /* (RTC_MODE2_INTENSET) Periodic Interval 3 Enable Mask */ 801 #define RTC_MODE2_INTENSET_PER3(value) (RTC_MODE2_INTENSET_PER3_Msk & (_UINT16_(value) << RTC_MODE2_INTENSET_PER3_Pos)) /* Assignment of value for PER3 in the RTC_MODE2_INTENSET register */ 802 #define RTC_MODE2_INTENSET_PER4_Pos _UINT16_(4) /* (RTC_MODE2_INTENSET) Periodic Interval 4 Enable Position */ 803 #define RTC_MODE2_INTENSET_PER4_Msk (_UINT16_(0x1) << RTC_MODE2_INTENSET_PER4_Pos) /* (RTC_MODE2_INTENSET) Periodic Interval 4 Enable Mask */ 804 #define RTC_MODE2_INTENSET_PER4(value) (RTC_MODE2_INTENSET_PER4_Msk & (_UINT16_(value) << RTC_MODE2_INTENSET_PER4_Pos)) /* Assignment of value for PER4 in the RTC_MODE2_INTENSET register */ 805 #define RTC_MODE2_INTENSET_PER5_Pos _UINT16_(5) /* (RTC_MODE2_INTENSET) Periodic Interval 5 Enable Position */ 806 #define RTC_MODE2_INTENSET_PER5_Msk (_UINT16_(0x1) << RTC_MODE2_INTENSET_PER5_Pos) /* (RTC_MODE2_INTENSET) Periodic Interval 5 Enable Mask */ 807 #define RTC_MODE2_INTENSET_PER5(value) (RTC_MODE2_INTENSET_PER5_Msk & (_UINT16_(value) << RTC_MODE2_INTENSET_PER5_Pos)) /* Assignment of value for PER5 in the RTC_MODE2_INTENSET register */ 808 #define RTC_MODE2_INTENSET_PER6_Pos _UINT16_(6) /* (RTC_MODE2_INTENSET) Periodic Interval 6 Enable Position */ 809 #define RTC_MODE2_INTENSET_PER6_Msk (_UINT16_(0x1) << RTC_MODE2_INTENSET_PER6_Pos) /* (RTC_MODE2_INTENSET) Periodic Interval 6 Enable Mask */ 810 #define RTC_MODE2_INTENSET_PER6(value) (RTC_MODE2_INTENSET_PER6_Msk & (_UINT16_(value) << RTC_MODE2_INTENSET_PER6_Pos)) /* Assignment of value for PER6 in the RTC_MODE2_INTENSET register */ 811 #define RTC_MODE2_INTENSET_PER7_Pos _UINT16_(7) /* (RTC_MODE2_INTENSET) Periodic Interval 7 Enable Position */ 812 #define RTC_MODE2_INTENSET_PER7_Msk (_UINT16_(0x1) << RTC_MODE2_INTENSET_PER7_Pos) /* (RTC_MODE2_INTENSET) Periodic Interval 7 Enable Mask */ 813 #define RTC_MODE2_INTENSET_PER7(value) (RTC_MODE2_INTENSET_PER7_Msk & (_UINT16_(value) << RTC_MODE2_INTENSET_PER7_Pos)) /* Assignment of value for PER7 in the RTC_MODE2_INTENSET register */ 814 #define RTC_MODE2_INTENSET_ALARM0_Pos _UINT16_(8) /* (RTC_MODE2_INTENSET) Alarm 0 Interrupt Enable Position */ 815 #define RTC_MODE2_INTENSET_ALARM0_Msk (_UINT16_(0x1) << RTC_MODE2_INTENSET_ALARM0_Pos) /* (RTC_MODE2_INTENSET) Alarm 0 Interrupt Enable Mask */ 816 #define RTC_MODE2_INTENSET_ALARM0(value) (RTC_MODE2_INTENSET_ALARM0_Msk & (_UINT16_(value) << RTC_MODE2_INTENSET_ALARM0_Pos)) /* Assignment of value for ALARM0 in the RTC_MODE2_INTENSET register */ 817 #define RTC_MODE2_INTENSET_ALARM1_Pos _UINT16_(9) /* (RTC_MODE2_INTENSET) Alarm 1 Interrupt Enable Position */ 818 #define RTC_MODE2_INTENSET_ALARM1_Msk (_UINT16_(0x1) << RTC_MODE2_INTENSET_ALARM1_Pos) /* (RTC_MODE2_INTENSET) Alarm 1 Interrupt Enable Mask */ 819 #define RTC_MODE2_INTENSET_ALARM1(value) (RTC_MODE2_INTENSET_ALARM1_Msk & (_UINT16_(value) << RTC_MODE2_INTENSET_ALARM1_Pos)) /* Assignment of value for ALARM1 in the RTC_MODE2_INTENSET register */ 820 #define RTC_MODE2_INTENSET_TAMPER_Pos _UINT16_(14) /* (RTC_MODE2_INTENSET) Tamper Enable Position */ 821 #define RTC_MODE2_INTENSET_TAMPER_Msk (_UINT16_(0x1) << RTC_MODE2_INTENSET_TAMPER_Pos) /* (RTC_MODE2_INTENSET) Tamper Enable Mask */ 822 #define RTC_MODE2_INTENSET_TAMPER(value) (RTC_MODE2_INTENSET_TAMPER_Msk & (_UINT16_(value) << RTC_MODE2_INTENSET_TAMPER_Pos)) /* Assignment of value for TAMPER in the RTC_MODE2_INTENSET register */ 823 #define RTC_MODE2_INTENSET_OVF_Pos _UINT16_(15) /* (RTC_MODE2_INTENSET) Overflow Interrupt Enable Position */ 824 #define RTC_MODE2_INTENSET_OVF_Msk (_UINT16_(0x1) << RTC_MODE2_INTENSET_OVF_Pos) /* (RTC_MODE2_INTENSET) Overflow Interrupt Enable Mask */ 825 #define RTC_MODE2_INTENSET_OVF(value) (RTC_MODE2_INTENSET_OVF_Msk & (_UINT16_(value) << RTC_MODE2_INTENSET_OVF_Pos)) /* Assignment of value for OVF in the RTC_MODE2_INTENSET register */ 826 #define RTC_MODE2_INTENSET_Msk _UINT16_(0xC3FF) /* (RTC_MODE2_INTENSET) Register Mask */ 827 828 #define RTC_MODE2_INTENSET_PER_Pos _UINT16_(0) /* (RTC_MODE2_INTENSET Position) Periodic Interval x Enable */ 829 #define RTC_MODE2_INTENSET_PER_Msk (_UINT16_(0xFF) << RTC_MODE2_INTENSET_PER_Pos) /* (RTC_MODE2_INTENSET Mask) PER */ 830 #define RTC_MODE2_INTENSET_PER(value) (RTC_MODE2_INTENSET_PER_Msk & (_UINT16_(value) << RTC_MODE2_INTENSET_PER_Pos)) 831 #define RTC_MODE2_INTENSET_ALARM_Pos _UINT16_(8) /* (RTC_MODE2_INTENSET Position) Alarm x Interrupt Enable */ 832 #define RTC_MODE2_INTENSET_ALARM_Msk (_UINT16_(0x3) << RTC_MODE2_INTENSET_ALARM_Pos) /* (RTC_MODE2_INTENSET Mask) ALARM */ 833 #define RTC_MODE2_INTENSET_ALARM(value) (RTC_MODE2_INTENSET_ALARM_Msk & (_UINT16_(value) << RTC_MODE2_INTENSET_ALARM_Pos)) 834 835 /* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x0C) (R/W 16) MODE0 Interrupt Flag Status and Clear -------- */ 836 #define RTC_MODE0_INTFLAG_RESETVALUE _UINT16_(0x00) /* (RTC_MODE0_INTFLAG) MODE0 Interrupt Flag Status and Clear Reset Value */ 837 838 #define RTC_MODE0_INTFLAG_PER0_Pos _UINT16_(0) /* (RTC_MODE0_INTFLAG) Periodic Interval 0 Position */ 839 #define RTC_MODE0_INTFLAG_PER0_Msk (_UINT16_(0x1) << RTC_MODE0_INTFLAG_PER0_Pos) /* (RTC_MODE0_INTFLAG) Periodic Interval 0 Mask */ 840 #define RTC_MODE0_INTFLAG_PER0(value) (RTC_MODE0_INTFLAG_PER0_Msk & (_UINT16_(value) << RTC_MODE0_INTFLAG_PER0_Pos)) /* Assignment of value for PER0 in the RTC_MODE0_INTFLAG register */ 841 #define RTC_MODE0_INTFLAG_PER1_Pos _UINT16_(1) /* (RTC_MODE0_INTFLAG) Periodic Interval 1 Position */ 842 #define RTC_MODE0_INTFLAG_PER1_Msk (_UINT16_(0x1) << RTC_MODE0_INTFLAG_PER1_Pos) /* (RTC_MODE0_INTFLAG) Periodic Interval 1 Mask */ 843 #define RTC_MODE0_INTFLAG_PER1(value) (RTC_MODE0_INTFLAG_PER1_Msk & (_UINT16_(value) << RTC_MODE0_INTFLAG_PER1_Pos)) /* Assignment of value for PER1 in the RTC_MODE0_INTFLAG register */ 844 #define RTC_MODE0_INTFLAG_PER2_Pos _UINT16_(2) /* (RTC_MODE0_INTFLAG) Periodic Interval 2 Position */ 845 #define RTC_MODE0_INTFLAG_PER2_Msk (_UINT16_(0x1) << RTC_MODE0_INTFLAG_PER2_Pos) /* (RTC_MODE0_INTFLAG) Periodic Interval 2 Mask */ 846 #define RTC_MODE0_INTFLAG_PER2(value) (RTC_MODE0_INTFLAG_PER2_Msk & (_UINT16_(value) << RTC_MODE0_INTFLAG_PER2_Pos)) /* Assignment of value for PER2 in the RTC_MODE0_INTFLAG register */ 847 #define RTC_MODE0_INTFLAG_PER3_Pos _UINT16_(3) /* (RTC_MODE0_INTFLAG) Periodic Interval 3 Position */ 848 #define RTC_MODE0_INTFLAG_PER3_Msk (_UINT16_(0x1) << RTC_MODE0_INTFLAG_PER3_Pos) /* (RTC_MODE0_INTFLAG) Periodic Interval 3 Mask */ 849 #define RTC_MODE0_INTFLAG_PER3(value) (RTC_MODE0_INTFLAG_PER3_Msk & (_UINT16_(value) << RTC_MODE0_INTFLAG_PER3_Pos)) /* Assignment of value for PER3 in the RTC_MODE0_INTFLAG register */ 850 #define RTC_MODE0_INTFLAG_PER4_Pos _UINT16_(4) /* (RTC_MODE0_INTFLAG) Periodic Interval 4 Position */ 851 #define RTC_MODE0_INTFLAG_PER4_Msk (_UINT16_(0x1) << RTC_MODE0_INTFLAG_PER4_Pos) /* (RTC_MODE0_INTFLAG) Periodic Interval 4 Mask */ 852 #define RTC_MODE0_INTFLAG_PER4(value) (RTC_MODE0_INTFLAG_PER4_Msk & (_UINT16_(value) << RTC_MODE0_INTFLAG_PER4_Pos)) /* Assignment of value for PER4 in the RTC_MODE0_INTFLAG register */ 853 #define RTC_MODE0_INTFLAG_PER5_Pos _UINT16_(5) /* (RTC_MODE0_INTFLAG) Periodic Interval 5 Position */ 854 #define RTC_MODE0_INTFLAG_PER5_Msk (_UINT16_(0x1) << RTC_MODE0_INTFLAG_PER5_Pos) /* (RTC_MODE0_INTFLAG) Periodic Interval 5 Mask */ 855 #define RTC_MODE0_INTFLAG_PER5(value) (RTC_MODE0_INTFLAG_PER5_Msk & (_UINT16_(value) << RTC_MODE0_INTFLAG_PER5_Pos)) /* Assignment of value for PER5 in the RTC_MODE0_INTFLAG register */ 856 #define RTC_MODE0_INTFLAG_PER6_Pos _UINT16_(6) /* (RTC_MODE0_INTFLAG) Periodic Interval 6 Position */ 857 #define RTC_MODE0_INTFLAG_PER6_Msk (_UINT16_(0x1) << RTC_MODE0_INTFLAG_PER6_Pos) /* (RTC_MODE0_INTFLAG) Periodic Interval 6 Mask */ 858 #define RTC_MODE0_INTFLAG_PER6(value) (RTC_MODE0_INTFLAG_PER6_Msk & (_UINT16_(value) << RTC_MODE0_INTFLAG_PER6_Pos)) /* Assignment of value for PER6 in the RTC_MODE0_INTFLAG register */ 859 #define RTC_MODE0_INTFLAG_PER7_Pos _UINT16_(7) /* (RTC_MODE0_INTFLAG) Periodic Interval 7 Position */ 860 #define RTC_MODE0_INTFLAG_PER7_Msk (_UINT16_(0x1) << RTC_MODE0_INTFLAG_PER7_Pos) /* (RTC_MODE0_INTFLAG) Periodic Interval 7 Mask */ 861 #define RTC_MODE0_INTFLAG_PER7(value) (RTC_MODE0_INTFLAG_PER7_Msk & (_UINT16_(value) << RTC_MODE0_INTFLAG_PER7_Pos)) /* Assignment of value for PER7 in the RTC_MODE0_INTFLAG register */ 862 #define RTC_MODE0_INTFLAG_CMP0_Pos _UINT16_(8) /* (RTC_MODE0_INTFLAG) Compare 0 Position */ 863 #define RTC_MODE0_INTFLAG_CMP0_Msk (_UINT16_(0x1) << RTC_MODE0_INTFLAG_CMP0_Pos) /* (RTC_MODE0_INTFLAG) Compare 0 Mask */ 864 #define RTC_MODE0_INTFLAG_CMP0(value) (RTC_MODE0_INTFLAG_CMP0_Msk & (_UINT16_(value) << RTC_MODE0_INTFLAG_CMP0_Pos)) /* Assignment of value for CMP0 in the RTC_MODE0_INTFLAG register */ 865 #define RTC_MODE0_INTFLAG_CMP1_Pos _UINT16_(9) /* (RTC_MODE0_INTFLAG) Compare 1 Position */ 866 #define RTC_MODE0_INTFLAG_CMP1_Msk (_UINT16_(0x1) << RTC_MODE0_INTFLAG_CMP1_Pos) /* (RTC_MODE0_INTFLAG) Compare 1 Mask */ 867 #define RTC_MODE0_INTFLAG_CMP1(value) (RTC_MODE0_INTFLAG_CMP1_Msk & (_UINT16_(value) << RTC_MODE0_INTFLAG_CMP1_Pos)) /* Assignment of value for CMP1 in the RTC_MODE0_INTFLAG register */ 868 #define RTC_MODE0_INTFLAG_TAMPER_Pos _UINT16_(14) /* (RTC_MODE0_INTFLAG) Tamper Position */ 869 #define RTC_MODE0_INTFLAG_TAMPER_Msk (_UINT16_(0x1) << RTC_MODE0_INTFLAG_TAMPER_Pos) /* (RTC_MODE0_INTFLAG) Tamper Mask */ 870 #define RTC_MODE0_INTFLAG_TAMPER(value) (RTC_MODE0_INTFLAG_TAMPER_Msk & (_UINT16_(value) << RTC_MODE0_INTFLAG_TAMPER_Pos)) /* Assignment of value for TAMPER in the RTC_MODE0_INTFLAG register */ 871 #define RTC_MODE0_INTFLAG_OVF_Pos _UINT16_(15) /* (RTC_MODE0_INTFLAG) Overflow Position */ 872 #define RTC_MODE0_INTFLAG_OVF_Msk (_UINT16_(0x1) << RTC_MODE0_INTFLAG_OVF_Pos) /* (RTC_MODE0_INTFLAG) Overflow Mask */ 873 #define RTC_MODE0_INTFLAG_OVF(value) (RTC_MODE0_INTFLAG_OVF_Msk & (_UINT16_(value) << RTC_MODE0_INTFLAG_OVF_Pos)) /* Assignment of value for OVF in the RTC_MODE0_INTFLAG register */ 874 #define RTC_MODE0_INTFLAG_Msk _UINT16_(0xC3FF) /* (RTC_MODE0_INTFLAG) Register Mask */ 875 876 #define RTC_MODE0_INTFLAG_PER_Pos _UINT16_(0) /* (RTC_MODE0_INTFLAG Position) Periodic Interval x */ 877 #define RTC_MODE0_INTFLAG_PER_Msk (_UINT16_(0xFF) << RTC_MODE0_INTFLAG_PER_Pos) /* (RTC_MODE0_INTFLAG Mask) PER */ 878 #define RTC_MODE0_INTFLAG_PER(value) (RTC_MODE0_INTFLAG_PER_Msk & (_UINT16_(value) << RTC_MODE0_INTFLAG_PER_Pos)) 879 #define RTC_MODE0_INTFLAG_CMP_Pos _UINT16_(8) /* (RTC_MODE0_INTFLAG Position) Compare x */ 880 #define RTC_MODE0_INTFLAG_CMP_Msk (_UINT16_(0x3) << RTC_MODE0_INTFLAG_CMP_Pos) /* (RTC_MODE0_INTFLAG Mask) CMP */ 881 #define RTC_MODE0_INTFLAG_CMP(value) (RTC_MODE0_INTFLAG_CMP_Msk & (_UINT16_(value) << RTC_MODE0_INTFLAG_CMP_Pos)) 882 883 /* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x0C) (R/W 16) MODE1 Interrupt Flag Status and Clear -------- */ 884 #define RTC_MODE1_INTFLAG_RESETVALUE _UINT16_(0x00) /* (RTC_MODE1_INTFLAG) MODE1 Interrupt Flag Status and Clear Reset Value */ 885 886 #define RTC_MODE1_INTFLAG_PER0_Pos _UINT16_(0) /* (RTC_MODE1_INTFLAG) Periodic Interval 0 Position */ 887 #define RTC_MODE1_INTFLAG_PER0_Msk (_UINT16_(0x1) << RTC_MODE1_INTFLAG_PER0_Pos) /* (RTC_MODE1_INTFLAG) Periodic Interval 0 Mask */ 888 #define RTC_MODE1_INTFLAG_PER0(value) (RTC_MODE1_INTFLAG_PER0_Msk & (_UINT16_(value) << RTC_MODE1_INTFLAG_PER0_Pos)) /* Assignment of value for PER0 in the RTC_MODE1_INTFLAG register */ 889 #define RTC_MODE1_INTFLAG_PER1_Pos _UINT16_(1) /* (RTC_MODE1_INTFLAG) Periodic Interval 1 Position */ 890 #define RTC_MODE1_INTFLAG_PER1_Msk (_UINT16_(0x1) << RTC_MODE1_INTFLAG_PER1_Pos) /* (RTC_MODE1_INTFLAG) Periodic Interval 1 Mask */ 891 #define RTC_MODE1_INTFLAG_PER1(value) (RTC_MODE1_INTFLAG_PER1_Msk & (_UINT16_(value) << RTC_MODE1_INTFLAG_PER1_Pos)) /* Assignment of value for PER1 in the RTC_MODE1_INTFLAG register */ 892 #define RTC_MODE1_INTFLAG_PER2_Pos _UINT16_(2) /* (RTC_MODE1_INTFLAG) Periodic Interval 2 Position */ 893 #define RTC_MODE1_INTFLAG_PER2_Msk (_UINT16_(0x1) << RTC_MODE1_INTFLAG_PER2_Pos) /* (RTC_MODE1_INTFLAG) Periodic Interval 2 Mask */ 894 #define RTC_MODE1_INTFLAG_PER2(value) (RTC_MODE1_INTFLAG_PER2_Msk & (_UINT16_(value) << RTC_MODE1_INTFLAG_PER2_Pos)) /* Assignment of value for PER2 in the RTC_MODE1_INTFLAG register */ 895 #define RTC_MODE1_INTFLAG_PER3_Pos _UINT16_(3) /* (RTC_MODE1_INTFLAG) Periodic Interval 3 Position */ 896 #define RTC_MODE1_INTFLAG_PER3_Msk (_UINT16_(0x1) << RTC_MODE1_INTFLAG_PER3_Pos) /* (RTC_MODE1_INTFLAG) Periodic Interval 3 Mask */ 897 #define RTC_MODE1_INTFLAG_PER3(value) (RTC_MODE1_INTFLAG_PER3_Msk & (_UINT16_(value) << RTC_MODE1_INTFLAG_PER3_Pos)) /* Assignment of value for PER3 in the RTC_MODE1_INTFLAG register */ 898 #define RTC_MODE1_INTFLAG_PER4_Pos _UINT16_(4) /* (RTC_MODE1_INTFLAG) Periodic Interval 4 Position */ 899 #define RTC_MODE1_INTFLAG_PER4_Msk (_UINT16_(0x1) << RTC_MODE1_INTFLAG_PER4_Pos) /* (RTC_MODE1_INTFLAG) Periodic Interval 4 Mask */ 900 #define RTC_MODE1_INTFLAG_PER4(value) (RTC_MODE1_INTFLAG_PER4_Msk & (_UINT16_(value) << RTC_MODE1_INTFLAG_PER4_Pos)) /* Assignment of value for PER4 in the RTC_MODE1_INTFLAG register */ 901 #define RTC_MODE1_INTFLAG_PER5_Pos _UINT16_(5) /* (RTC_MODE1_INTFLAG) Periodic Interval 5 Position */ 902 #define RTC_MODE1_INTFLAG_PER5_Msk (_UINT16_(0x1) << RTC_MODE1_INTFLAG_PER5_Pos) /* (RTC_MODE1_INTFLAG) Periodic Interval 5 Mask */ 903 #define RTC_MODE1_INTFLAG_PER5(value) (RTC_MODE1_INTFLAG_PER5_Msk & (_UINT16_(value) << RTC_MODE1_INTFLAG_PER5_Pos)) /* Assignment of value for PER5 in the RTC_MODE1_INTFLAG register */ 904 #define RTC_MODE1_INTFLAG_PER6_Pos _UINT16_(6) /* (RTC_MODE1_INTFLAG) Periodic Interval 6 Position */ 905 #define RTC_MODE1_INTFLAG_PER6_Msk (_UINT16_(0x1) << RTC_MODE1_INTFLAG_PER6_Pos) /* (RTC_MODE1_INTFLAG) Periodic Interval 6 Mask */ 906 #define RTC_MODE1_INTFLAG_PER6(value) (RTC_MODE1_INTFLAG_PER6_Msk & (_UINT16_(value) << RTC_MODE1_INTFLAG_PER6_Pos)) /* Assignment of value for PER6 in the RTC_MODE1_INTFLAG register */ 907 #define RTC_MODE1_INTFLAG_PER7_Pos _UINT16_(7) /* (RTC_MODE1_INTFLAG) Periodic Interval 7 Position */ 908 #define RTC_MODE1_INTFLAG_PER7_Msk (_UINT16_(0x1) << RTC_MODE1_INTFLAG_PER7_Pos) /* (RTC_MODE1_INTFLAG) Periodic Interval 7 Mask */ 909 #define RTC_MODE1_INTFLAG_PER7(value) (RTC_MODE1_INTFLAG_PER7_Msk & (_UINT16_(value) << RTC_MODE1_INTFLAG_PER7_Pos)) /* Assignment of value for PER7 in the RTC_MODE1_INTFLAG register */ 910 #define RTC_MODE1_INTFLAG_CMP0_Pos _UINT16_(8) /* (RTC_MODE1_INTFLAG) Compare 0 Position */ 911 #define RTC_MODE1_INTFLAG_CMP0_Msk (_UINT16_(0x1) << RTC_MODE1_INTFLAG_CMP0_Pos) /* (RTC_MODE1_INTFLAG) Compare 0 Mask */ 912 #define RTC_MODE1_INTFLAG_CMP0(value) (RTC_MODE1_INTFLAG_CMP0_Msk & (_UINT16_(value) << RTC_MODE1_INTFLAG_CMP0_Pos)) /* Assignment of value for CMP0 in the RTC_MODE1_INTFLAG register */ 913 #define RTC_MODE1_INTFLAG_CMP1_Pos _UINT16_(9) /* (RTC_MODE1_INTFLAG) Compare 1 Position */ 914 #define RTC_MODE1_INTFLAG_CMP1_Msk (_UINT16_(0x1) << RTC_MODE1_INTFLAG_CMP1_Pos) /* (RTC_MODE1_INTFLAG) Compare 1 Mask */ 915 #define RTC_MODE1_INTFLAG_CMP1(value) (RTC_MODE1_INTFLAG_CMP1_Msk & (_UINT16_(value) << RTC_MODE1_INTFLAG_CMP1_Pos)) /* Assignment of value for CMP1 in the RTC_MODE1_INTFLAG register */ 916 #define RTC_MODE1_INTFLAG_CMP2_Pos _UINT16_(10) /* (RTC_MODE1_INTFLAG) Compare 2 Position */ 917 #define RTC_MODE1_INTFLAG_CMP2_Msk (_UINT16_(0x1) << RTC_MODE1_INTFLAG_CMP2_Pos) /* (RTC_MODE1_INTFLAG) Compare 2 Mask */ 918 #define RTC_MODE1_INTFLAG_CMP2(value) (RTC_MODE1_INTFLAG_CMP2_Msk & (_UINT16_(value) << RTC_MODE1_INTFLAG_CMP2_Pos)) /* Assignment of value for CMP2 in the RTC_MODE1_INTFLAG register */ 919 #define RTC_MODE1_INTFLAG_CMP3_Pos _UINT16_(11) /* (RTC_MODE1_INTFLAG) Compare 3 Position */ 920 #define RTC_MODE1_INTFLAG_CMP3_Msk (_UINT16_(0x1) << RTC_MODE1_INTFLAG_CMP3_Pos) /* (RTC_MODE1_INTFLAG) Compare 3 Mask */ 921 #define RTC_MODE1_INTFLAG_CMP3(value) (RTC_MODE1_INTFLAG_CMP3_Msk & (_UINT16_(value) << RTC_MODE1_INTFLAG_CMP3_Pos)) /* Assignment of value for CMP3 in the RTC_MODE1_INTFLAG register */ 922 #define RTC_MODE1_INTFLAG_TAMPER_Pos _UINT16_(14) /* (RTC_MODE1_INTFLAG) Tamper Position */ 923 #define RTC_MODE1_INTFLAG_TAMPER_Msk (_UINT16_(0x1) << RTC_MODE1_INTFLAG_TAMPER_Pos) /* (RTC_MODE1_INTFLAG) Tamper Mask */ 924 #define RTC_MODE1_INTFLAG_TAMPER(value) (RTC_MODE1_INTFLAG_TAMPER_Msk & (_UINT16_(value) << RTC_MODE1_INTFLAG_TAMPER_Pos)) /* Assignment of value for TAMPER in the RTC_MODE1_INTFLAG register */ 925 #define RTC_MODE1_INTFLAG_OVF_Pos _UINT16_(15) /* (RTC_MODE1_INTFLAG) Overflow Position */ 926 #define RTC_MODE1_INTFLAG_OVF_Msk (_UINT16_(0x1) << RTC_MODE1_INTFLAG_OVF_Pos) /* (RTC_MODE1_INTFLAG) Overflow Mask */ 927 #define RTC_MODE1_INTFLAG_OVF(value) (RTC_MODE1_INTFLAG_OVF_Msk & (_UINT16_(value) << RTC_MODE1_INTFLAG_OVF_Pos)) /* Assignment of value for OVF in the RTC_MODE1_INTFLAG register */ 928 #define RTC_MODE1_INTFLAG_Msk _UINT16_(0xCFFF) /* (RTC_MODE1_INTFLAG) Register Mask */ 929 930 #define RTC_MODE1_INTFLAG_PER_Pos _UINT16_(0) /* (RTC_MODE1_INTFLAG Position) Periodic Interval x */ 931 #define RTC_MODE1_INTFLAG_PER_Msk (_UINT16_(0xFF) << RTC_MODE1_INTFLAG_PER_Pos) /* (RTC_MODE1_INTFLAG Mask) PER */ 932 #define RTC_MODE1_INTFLAG_PER(value) (RTC_MODE1_INTFLAG_PER_Msk & (_UINT16_(value) << RTC_MODE1_INTFLAG_PER_Pos)) 933 #define RTC_MODE1_INTFLAG_CMP_Pos _UINT16_(8) /* (RTC_MODE1_INTFLAG Position) Compare x */ 934 #define RTC_MODE1_INTFLAG_CMP_Msk (_UINT16_(0xF) << RTC_MODE1_INTFLAG_CMP_Pos) /* (RTC_MODE1_INTFLAG Mask) CMP */ 935 #define RTC_MODE1_INTFLAG_CMP(value) (RTC_MODE1_INTFLAG_CMP_Msk & (_UINT16_(value) << RTC_MODE1_INTFLAG_CMP_Pos)) 936 937 /* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x0C) (R/W 16) MODE2 Interrupt Flag Status and Clear -------- */ 938 #define RTC_MODE2_INTFLAG_RESETVALUE _UINT16_(0x00) /* (RTC_MODE2_INTFLAG) MODE2 Interrupt Flag Status and Clear Reset Value */ 939 940 #define RTC_MODE2_INTFLAG_PER0_Pos _UINT16_(0) /* (RTC_MODE2_INTFLAG) Periodic Interval 0 Position */ 941 #define RTC_MODE2_INTFLAG_PER0_Msk (_UINT16_(0x1) << RTC_MODE2_INTFLAG_PER0_Pos) /* (RTC_MODE2_INTFLAG) Periodic Interval 0 Mask */ 942 #define RTC_MODE2_INTFLAG_PER0(value) (RTC_MODE2_INTFLAG_PER0_Msk & (_UINT16_(value) << RTC_MODE2_INTFLAG_PER0_Pos)) /* Assignment of value for PER0 in the RTC_MODE2_INTFLAG register */ 943 #define RTC_MODE2_INTFLAG_PER1_Pos _UINT16_(1) /* (RTC_MODE2_INTFLAG) Periodic Interval 1 Position */ 944 #define RTC_MODE2_INTFLAG_PER1_Msk (_UINT16_(0x1) << RTC_MODE2_INTFLAG_PER1_Pos) /* (RTC_MODE2_INTFLAG) Periodic Interval 1 Mask */ 945 #define RTC_MODE2_INTFLAG_PER1(value) (RTC_MODE2_INTFLAG_PER1_Msk & (_UINT16_(value) << RTC_MODE2_INTFLAG_PER1_Pos)) /* Assignment of value for PER1 in the RTC_MODE2_INTFLAG register */ 946 #define RTC_MODE2_INTFLAG_PER2_Pos _UINT16_(2) /* (RTC_MODE2_INTFLAG) Periodic Interval 2 Position */ 947 #define RTC_MODE2_INTFLAG_PER2_Msk (_UINT16_(0x1) << RTC_MODE2_INTFLAG_PER2_Pos) /* (RTC_MODE2_INTFLAG) Periodic Interval 2 Mask */ 948 #define RTC_MODE2_INTFLAG_PER2(value) (RTC_MODE2_INTFLAG_PER2_Msk & (_UINT16_(value) << RTC_MODE2_INTFLAG_PER2_Pos)) /* Assignment of value for PER2 in the RTC_MODE2_INTFLAG register */ 949 #define RTC_MODE2_INTFLAG_PER3_Pos _UINT16_(3) /* (RTC_MODE2_INTFLAG) Periodic Interval 3 Position */ 950 #define RTC_MODE2_INTFLAG_PER3_Msk (_UINT16_(0x1) << RTC_MODE2_INTFLAG_PER3_Pos) /* (RTC_MODE2_INTFLAG) Periodic Interval 3 Mask */ 951 #define RTC_MODE2_INTFLAG_PER3(value) (RTC_MODE2_INTFLAG_PER3_Msk & (_UINT16_(value) << RTC_MODE2_INTFLAG_PER3_Pos)) /* Assignment of value for PER3 in the RTC_MODE2_INTFLAG register */ 952 #define RTC_MODE2_INTFLAG_PER4_Pos _UINT16_(4) /* (RTC_MODE2_INTFLAG) Periodic Interval 4 Position */ 953 #define RTC_MODE2_INTFLAG_PER4_Msk (_UINT16_(0x1) << RTC_MODE2_INTFLAG_PER4_Pos) /* (RTC_MODE2_INTFLAG) Periodic Interval 4 Mask */ 954 #define RTC_MODE2_INTFLAG_PER4(value) (RTC_MODE2_INTFLAG_PER4_Msk & (_UINT16_(value) << RTC_MODE2_INTFLAG_PER4_Pos)) /* Assignment of value for PER4 in the RTC_MODE2_INTFLAG register */ 955 #define RTC_MODE2_INTFLAG_PER5_Pos _UINT16_(5) /* (RTC_MODE2_INTFLAG) Periodic Interval 5 Position */ 956 #define RTC_MODE2_INTFLAG_PER5_Msk (_UINT16_(0x1) << RTC_MODE2_INTFLAG_PER5_Pos) /* (RTC_MODE2_INTFLAG) Periodic Interval 5 Mask */ 957 #define RTC_MODE2_INTFLAG_PER5(value) (RTC_MODE2_INTFLAG_PER5_Msk & (_UINT16_(value) << RTC_MODE2_INTFLAG_PER5_Pos)) /* Assignment of value for PER5 in the RTC_MODE2_INTFLAG register */ 958 #define RTC_MODE2_INTFLAG_PER6_Pos _UINT16_(6) /* (RTC_MODE2_INTFLAG) Periodic Interval 6 Position */ 959 #define RTC_MODE2_INTFLAG_PER6_Msk (_UINT16_(0x1) << RTC_MODE2_INTFLAG_PER6_Pos) /* (RTC_MODE2_INTFLAG) Periodic Interval 6 Mask */ 960 #define RTC_MODE2_INTFLAG_PER6(value) (RTC_MODE2_INTFLAG_PER6_Msk & (_UINT16_(value) << RTC_MODE2_INTFLAG_PER6_Pos)) /* Assignment of value for PER6 in the RTC_MODE2_INTFLAG register */ 961 #define RTC_MODE2_INTFLAG_PER7_Pos _UINT16_(7) /* (RTC_MODE2_INTFLAG) Periodic Interval 7 Position */ 962 #define RTC_MODE2_INTFLAG_PER7_Msk (_UINT16_(0x1) << RTC_MODE2_INTFLAG_PER7_Pos) /* (RTC_MODE2_INTFLAG) Periodic Interval 7 Mask */ 963 #define RTC_MODE2_INTFLAG_PER7(value) (RTC_MODE2_INTFLAG_PER7_Msk & (_UINT16_(value) << RTC_MODE2_INTFLAG_PER7_Pos)) /* Assignment of value for PER7 in the RTC_MODE2_INTFLAG register */ 964 #define RTC_MODE2_INTFLAG_ALARM0_Pos _UINT16_(8) /* (RTC_MODE2_INTFLAG) Alarm 0 Position */ 965 #define RTC_MODE2_INTFLAG_ALARM0_Msk (_UINT16_(0x1) << RTC_MODE2_INTFLAG_ALARM0_Pos) /* (RTC_MODE2_INTFLAG) Alarm 0 Mask */ 966 #define RTC_MODE2_INTFLAG_ALARM0(value) (RTC_MODE2_INTFLAG_ALARM0_Msk & (_UINT16_(value) << RTC_MODE2_INTFLAG_ALARM0_Pos)) /* Assignment of value for ALARM0 in the RTC_MODE2_INTFLAG register */ 967 #define RTC_MODE2_INTFLAG_ALARM1_Pos _UINT16_(9) /* (RTC_MODE2_INTFLAG) Alarm 1 Position */ 968 #define RTC_MODE2_INTFLAG_ALARM1_Msk (_UINT16_(0x1) << RTC_MODE2_INTFLAG_ALARM1_Pos) /* (RTC_MODE2_INTFLAG) Alarm 1 Mask */ 969 #define RTC_MODE2_INTFLAG_ALARM1(value) (RTC_MODE2_INTFLAG_ALARM1_Msk & (_UINT16_(value) << RTC_MODE2_INTFLAG_ALARM1_Pos)) /* Assignment of value for ALARM1 in the RTC_MODE2_INTFLAG register */ 970 #define RTC_MODE2_INTFLAG_TAMPER_Pos _UINT16_(14) /* (RTC_MODE2_INTFLAG) Tamper Position */ 971 #define RTC_MODE2_INTFLAG_TAMPER_Msk (_UINT16_(0x1) << RTC_MODE2_INTFLAG_TAMPER_Pos) /* (RTC_MODE2_INTFLAG) Tamper Mask */ 972 #define RTC_MODE2_INTFLAG_TAMPER(value) (RTC_MODE2_INTFLAG_TAMPER_Msk & (_UINT16_(value) << RTC_MODE2_INTFLAG_TAMPER_Pos)) /* Assignment of value for TAMPER in the RTC_MODE2_INTFLAG register */ 973 #define RTC_MODE2_INTFLAG_OVF_Pos _UINT16_(15) /* (RTC_MODE2_INTFLAG) Overflow Position */ 974 #define RTC_MODE2_INTFLAG_OVF_Msk (_UINT16_(0x1) << RTC_MODE2_INTFLAG_OVF_Pos) /* (RTC_MODE2_INTFLAG) Overflow Mask */ 975 #define RTC_MODE2_INTFLAG_OVF(value) (RTC_MODE2_INTFLAG_OVF_Msk & (_UINT16_(value) << RTC_MODE2_INTFLAG_OVF_Pos)) /* Assignment of value for OVF in the RTC_MODE2_INTFLAG register */ 976 #define RTC_MODE2_INTFLAG_Msk _UINT16_(0xC3FF) /* (RTC_MODE2_INTFLAG) Register Mask */ 977 978 #define RTC_MODE2_INTFLAG_PER_Pos _UINT16_(0) /* (RTC_MODE2_INTFLAG Position) Periodic Interval x */ 979 #define RTC_MODE2_INTFLAG_PER_Msk (_UINT16_(0xFF) << RTC_MODE2_INTFLAG_PER_Pos) /* (RTC_MODE2_INTFLAG Mask) PER */ 980 #define RTC_MODE2_INTFLAG_PER(value) (RTC_MODE2_INTFLAG_PER_Msk & (_UINT16_(value) << RTC_MODE2_INTFLAG_PER_Pos)) 981 #define RTC_MODE2_INTFLAG_ALARM_Pos _UINT16_(8) /* (RTC_MODE2_INTFLAG Position) Alarm x */ 982 #define RTC_MODE2_INTFLAG_ALARM_Msk (_UINT16_(0x3) << RTC_MODE2_INTFLAG_ALARM_Pos) /* (RTC_MODE2_INTFLAG Mask) ALARM */ 983 #define RTC_MODE2_INTFLAG_ALARM(value) (RTC_MODE2_INTFLAG_ALARM_Msk & (_UINT16_(value) << RTC_MODE2_INTFLAG_ALARM_Pos)) 984 985 /* -------- RTC_DBGCTRL : (RTC Offset: 0x0E) (R/W 8) Debug Control -------- */ 986 #define RTC_DBGCTRL_RESETVALUE _UINT8_(0x00) /* (RTC_DBGCTRL) Debug Control Reset Value */ 987 988 #define RTC_DBGCTRL_DBGRUN_Pos _UINT8_(0) /* (RTC_DBGCTRL) Run During Debug Position */ 989 #define RTC_DBGCTRL_DBGRUN_Msk (_UINT8_(0x1) << RTC_DBGCTRL_DBGRUN_Pos) /* (RTC_DBGCTRL) Run During Debug Mask */ 990 #define RTC_DBGCTRL_DBGRUN(value) (RTC_DBGCTRL_DBGRUN_Msk & (_UINT8_(value) << RTC_DBGCTRL_DBGRUN_Pos)) /* Assignment of value for DBGRUN in the RTC_DBGCTRL register */ 991 #define RTC_DBGCTRL_Msk _UINT8_(0x01) /* (RTC_DBGCTRL) Register Mask */ 992 993 994 /* -------- RTC_MODE0_SYNCBUSY : (RTC Offset: 0x10) ( R/ 32) MODE0 Synchronization Busy Status -------- */ 995 #define RTC_MODE0_SYNCBUSY_RESETVALUE _UINT32_(0x00) /* (RTC_MODE0_SYNCBUSY) MODE0 Synchronization Busy Status Reset Value */ 996 997 #define RTC_MODE0_SYNCBUSY_SWRST_Pos _UINT32_(0) /* (RTC_MODE0_SYNCBUSY) Software Reset Busy Position */ 998 #define RTC_MODE0_SYNCBUSY_SWRST_Msk (_UINT32_(0x1) << RTC_MODE0_SYNCBUSY_SWRST_Pos) /* (RTC_MODE0_SYNCBUSY) Software Reset Busy Mask */ 999 #define RTC_MODE0_SYNCBUSY_SWRST(value) (RTC_MODE0_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << RTC_MODE0_SYNCBUSY_SWRST_Pos)) /* Assignment of value for SWRST in the RTC_MODE0_SYNCBUSY register */ 1000 #define RTC_MODE0_SYNCBUSY_ENABLE_Pos _UINT32_(1) /* (RTC_MODE0_SYNCBUSY) Enable Bit Busy Position */ 1001 #define RTC_MODE0_SYNCBUSY_ENABLE_Msk (_UINT32_(0x1) << RTC_MODE0_SYNCBUSY_ENABLE_Pos) /* (RTC_MODE0_SYNCBUSY) Enable Bit Busy Mask */ 1002 #define RTC_MODE0_SYNCBUSY_ENABLE(value) (RTC_MODE0_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << RTC_MODE0_SYNCBUSY_ENABLE_Pos)) /* Assignment of value for ENABLE in the RTC_MODE0_SYNCBUSY register */ 1003 #define RTC_MODE0_SYNCBUSY_FREQCORR_Pos _UINT32_(2) /* (RTC_MODE0_SYNCBUSY) FREQCORR Register Busy Position */ 1004 #define RTC_MODE0_SYNCBUSY_FREQCORR_Msk (_UINT32_(0x1) << RTC_MODE0_SYNCBUSY_FREQCORR_Pos) /* (RTC_MODE0_SYNCBUSY) FREQCORR Register Busy Mask */ 1005 #define RTC_MODE0_SYNCBUSY_FREQCORR(value) (RTC_MODE0_SYNCBUSY_FREQCORR_Msk & (_UINT32_(value) << RTC_MODE0_SYNCBUSY_FREQCORR_Pos)) /* Assignment of value for FREQCORR in the RTC_MODE0_SYNCBUSY register */ 1006 #define RTC_MODE0_SYNCBUSY_COUNT_Pos _UINT32_(3) /* (RTC_MODE0_SYNCBUSY) COUNT Register Busy Position */ 1007 #define RTC_MODE0_SYNCBUSY_COUNT_Msk (_UINT32_(0x1) << RTC_MODE0_SYNCBUSY_COUNT_Pos) /* (RTC_MODE0_SYNCBUSY) COUNT Register Busy Mask */ 1008 #define RTC_MODE0_SYNCBUSY_COUNT(value) (RTC_MODE0_SYNCBUSY_COUNT_Msk & (_UINT32_(value) << RTC_MODE0_SYNCBUSY_COUNT_Pos)) /* Assignment of value for COUNT in the RTC_MODE0_SYNCBUSY register */ 1009 #define RTC_MODE0_SYNCBUSY_COMP0_Pos _UINT32_(5) /* (RTC_MODE0_SYNCBUSY) COMP 0 Register Busy Position */ 1010 #define RTC_MODE0_SYNCBUSY_COMP0_Msk (_UINT32_(0x1) << RTC_MODE0_SYNCBUSY_COMP0_Pos) /* (RTC_MODE0_SYNCBUSY) COMP 0 Register Busy Mask */ 1011 #define RTC_MODE0_SYNCBUSY_COMP0(value) (RTC_MODE0_SYNCBUSY_COMP0_Msk & (_UINT32_(value) << RTC_MODE0_SYNCBUSY_COMP0_Pos)) /* Assignment of value for COMP0 in the RTC_MODE0_SYNCBUSY register */ 1012 #define RTC_MODE0_SYNCBUSY_COMP1_Pos _UINT32_(6) /* (RTC_MODE0_SYNCBUSY) COMP 1 Register Busy Position */ 1013 #define RTC_MODE0_SYNCBUSY_COMP1_Msk (_UINT32_(0x1) << RTC_MODE0_SYNCBUSY_COMP1_Pos) /* (RTC_MODE0_SYNCBUSY) COMP 1 Register Busy Mask */ 1014 #define RTC_MODE0_SYNCBUSY_COMP1(value) (RTC_MODE0_SYNCBUSY_COMP1_Msk & (_UINT32_(value) << RTC_MODE0_SYNCBUSY_COMP1_Pos)) /* Assignment of value for COMP1 in the RTC_MODE0_SYNCBUSY register */ 1015 #define RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos _UINT32_(15) /* (RTC_MODE0_SYNCBUSY) Count Synchronization Enable Bit Busy Position */ 1016 #define RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk (_UINT32_(0x1) << RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos) /* (RTC_MODE0_SYNCBUSY) Count Synchronization Enable Bit Busy Mask */ 1017 #define RTC_MODE0_SYNCBUSY_COUNTSYNC(value) (RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk & (_UINT32_(value) << RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos)) /* Assignment of value for COUNTSYNC in the RTC_MODE0_SYNCBUSY register */ 1018 #define RTC_MODE0_SYNCBUSY_GP0_Pos _UINT32_(16) /* (RTC_MODE0_SYNCBUSY) General Purpose 0 Register Busy Position */ 1019 #define RTC_MODE0_SYNCBUSY_GP0_Msk (_UINT32_(0x1) << RTC_MODE0_SYNCBUSY_GP0_Pos) /* (RTC_MODE0_SYNCBUSY) General Purpose 0 Register Busy Mask */ 1020 #define RTC_MODE0_SYNCBUSY_GP0(value) (RTC_MODE0_SYNCBUSY_GP0_Msk & (_UINT32_(value) << RTC_MODE0_SYNCBUSY_GP0_Pos)) /* Assignment of value for GP0 in the RTC_MODE0_SYNCBUSY register */ 1021 #define RTC_MODE0_SYNCBUSY_GP1_Pos _UINT32_(17) /* (RTC_MODE0_SYNCBUSY) General Purpose 1 Register Busy Position */ 1022 #define RTC_MODE0_SYNCBUSY_GP1_Msk (_UINT32_(0x1) << RTC_MODE0_SYNCBUSY_GP1_Pos) /* (RTC_MODE0_SYNCBUSY) General Purpose 1 Register Busy Mask */ 1023 #define RTC_MODE0_SYNCBUSY_GP1(value) (RTC_MODE0_SYNCBUSY_GP1_Msk & (_UINT32_(value) << RTC_MODE0_SYNCBUSY_GP1_Pos)) /* Assignment of value for GP1 in the RTC_MODE0_SYNCBUSY register */ 1024 #define RTC_MODE0_SYNCBUSY_GP2_Pos _UINT32_(18) /* (RTC_MODE0_SYNCBUSY) General Purpose 2 Register Busy Position */ 1025 #define RTC_MODE0_SYNCBUSY_GP2_Msk (_UINT32_(0x1) << RTC_MODE0_SYNCBUSY_GP2_Pos) /* (RTC_MODE0_SYNCBUSY) General Purpose 2 Register Busy Mask */ 1026 #define RTC_MODE0_SYNCBUSY_GP2(value) (RTC_MODE0_SYNCBUSY_GP2_Msk & (_UINT32_(value) << RTC_MODE0_SYNCBUSY_GP2_Pos)) /* Assignment of value for GP2 in the RTC_MODE0_SYNCBUSY register */ 1027 #define RTC_MODE0_SYNCBUSY_GP3_Pos _UINT32_(19) /* (RTC_MODE0_SYNCBUSY) General Purpose 3 Register Busy Position */ 1028 #define RTC_MODE0_SYNCBUSY_GP3_Msk (_UINT32_(0x1) << RTC_MODE0_SYNCBUSY_GP3_Pos) /* (RTC_MODE0_SYNCBUSY) General Purpose 3 Register Busy Mask */ 1029 #define RTC_MODE0_SYNCBUSY_GP3(value) (RTC_MODE0_SYNCBUSY_GP3_Msk & (_UINT32_(value) << RTC_MODE0_SYNCBUSY_GP3_Pos)) /* Assignment of value for GP3 in the RTC_MODE0_SYNCBUSY register */ 1030 #define RTC_MODE0_SYNCBUSY_Msk _UINT32_(0x000F806F) /* (RTC_MODE0_SYNCBUSY) Register Mask */ 1031 1032 #define RTC_MODE0_SYNCBUSY_COMP_Pos _UINT32_(5) /* (RTC_MODE0_SYNCBUSY Position) COMP x Register Busy */ 1033 #define RTC_MODE0_SYNCBUSY_COMP_Msk (_UINT32_(0x3) << RTC_MODE0_SYNCBUSY_COMP_Pos) /* (RTC_MODE0_SYNCBUSY Mask) COMP */ 1034 #define RTC_MODE0_SYNCBUSY_COMP(value) (RTC_MODE0_SYNCBUSY_COMP_Msk & (_UINT32_(value) << RTC_MODE0_SYNCBUSY_COMP_Pos)) 1035 #define RTC_MODE0_SYNCBUSY_GP_Pos _UINT32_(16) /* (RTC_MODE0_SYNCBUSY Position) General Purpose 3 Register Busy */ 1036 #define RTC_MODE0_SYNCBUSY_GP_Msk (_UINT32_(0xF) << RTC_MODE0_SYNCBUSY_GP_Pos) /* (RTC_MODE0_SYNCBUSY Mask) GP */ 1037 #define RTC_MODE0_SYNCBUSY_GP(value) (RTC_MODE0_SYNCBUSY_GP_Msk & (_UINT32_(value) << RTC_MODE0_SYNCBUSY_GP_Pos)) 1038 1039 /* -------- RTC_MODE1_SYNCBUSY : (RTC Offset: 0x10) ( R/ 32) MODE1 Synchronization Busy Status -------- */ 1040 #define RTC_MODE1_SYNCBUSY_RESETVALUE _UINT32_(0x00) /* (RTC_MODE1_SYNCBUSY) MODE1 Synchronization Busy Status Reset Value */ 1041 1042 #define RTC_MODE1_SYNCBUSY_SWRST_Pos _UINT32_(0) /* (RTC_MODE1_SYNCBUSY) Software Reset Bit Busy Position */ 1043 #define RTC_MODE1_SYNCBUSY_SWRST_Msk (_UINT32_(0x1) << RTC_MODE1_SYNCBUSY_SWRST_Pos) /* (RTC_MODE1_SYNCBUSY) Software Reset Bit Busy Mask */ 1044 #define RTC_MODE1_SYNCBUSY_SWRST(value) (RTC_MODE1_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << RTC_MODE1_SYNCBUSY_SWRST_Pos)) /* Assignment of value for SWRST in the RTC_MODE1_SYNCBUSY register */ 1045 #define RTC_MODE1_SYNCBUSY_ENABLE_Pos _UINT32_(1) /* (RTC_MODE1_SYNCBUSY) Enable Bit Busy Position */ 1046 #define RTC_MODE1_SYNCBUSY_ENABLE_Msk (_UINT32_(0x1) << RTC_MODE1_SYNCBUSY_ENABLE_Pos) /* (RTC_MODE1_SYNCBUSY) Enable Bit Busy Mask */ 1047 #define RTC_MODE1_SYNCBUSY_ENABLE(value) (RTC_MODE1_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << RTC_MODE1_SYNCBUSY_ENABLE_Pos)) /* Assignment of value for ENABLE in the RTC_MODE1_SYNCBUSY register */ 1048 #define RTC_MODE1_SYNCBUSY_FREQCORR_Pos _UINT32_(2) /* (RTC_MODE1_SYNCBUSY) FREQCORR Register Busy Position */ 1049 #define RTC_MODE1_SYNCBUSY_FREQCORR_Msk (_UINT32_(0x1) << RTC_MODE1_SYNCBUSY_FREQCORR_Pos) /* (RTC_MODE1_SYNCBUSY) FREQCORR Register Busy Mask */ 1050 #define RTC_MODE1_SYNCBUSY_FREQCORR(value) (RTC_MODE1_SYNCBUSY_FREQCORR_Msk & (_UINT32_(value) << RTC_MODE1_SYNCBUSY_FREQCORR_Pos)) /* Assignment of value for FREQCORR in the RTC_MODE1_SYNCBUSY register */ 1051 #define RTC_MODE1_SYNCBUSY_COUNT_Pos _UINT32_(3) /* (RTC_MODE1_SYNCBUSY) COUNT Register Busy Position */ 1052 #define RTC_MODE1_SYNCBUSY_COUNT_Msk (_UINT32_(0x1) << RTC_MODE1_SYNCBUSY_COUNT_Pos) /* (RTC_MODE1_SYNCBUSY) COUNT Register Busy Mask */ 1053 #define RTC_MODE1_SYNCBUSY_COUNT(value) (RTC_MODE1_SYNCBUSY_COUNT_Msk & (_UINT32_(value) << RTC_MODE1_SYNCBUSY_COUNT_Pos)) /* Assignment of value for COUNT in the RTC_MODE1_SYNCBUSY register */ 1054 #define RTC_MODE1_SYNCBUSY_PER_Pos _UINT32_(4) /* (RTC_MODE1_SYNCBUSY) PER Register Busy Position */ 1055 #define RTC_MODE1_SYNCBUSY_PER_Msk (_UINT32_(0x1) << RTC_MODE1_SYNCBUSY_PER_Pos) /* (RTC_MODE1_SYNCBUSY) PER Register Busy Mask */ 1056 #define RTC_MODE1_SYNCBUSY_PER(value) (RTC_MODE1_SYNCBUSY_PER_Msk & (_UINT32_(value) << RTC_MODE1_SYNCBUSY_PER_Pos)) /* Assignment of value for PER in the RTC_MODE1_SYNCBUSY register */ 1057 #define RTC_MODE1_SYNCBUSY_COMP0_Pos _UINT32_(5) /* (RTC_MODE1_SYNCBUSY) COMP 0 Register Busy Position */ 1058 #define RTC_MODE1_SYNCBUSY_COMP0_Msk (_UINT32_(0x1) << RTC_MODE1_SYNCBUSY_COMP0_Pos) /* (RTC_MODE1_SYNCBUSY) COMP 0 Register Busy Mask */ 1059 #define RTC_MODE1_SYNCBUSY_COMP0(value) (RTC_MODE1_SYNCBUSY_COMP0_Msk & (_UINT32_(value) << RTC_MODE1_SYNCBUSY_COMP0_Pos)) /* Assignment of value for COMP0 in the RTC_MODE1_SYNCBUSY register */ 1060 #define RTC_MODE1_SYNCBUSY_COMP1_Pos _UINT32_(6) /* (RTC_MODE1_SYNCBUSY) COMP 1 Register Busy Position */ 1061 #define RTC_MODE1_SYNCBUSY_COMP1_Msk (_UINT32_(0x1) << RTC_MODE1_SYNCBUSY_COMP1_Pos) /* (RTC_MODE1_SYNCBUSY) COMP 1 Register Busy Mask */ 1062 #define RTC_MODE1_SYNCBUSY_COMP1(value) (RTC_MODE1_SYNCBUSY_COMP1_Msk & (_UINT32_(value) << RTC_MODE1_SYNCBUSY_COMP1_Pos)) /* Assignment of value for COMP1 in the RTC_MODE1_SYNCBUSY register */ 1063 #define RTC_MODE1_SYNCBUSY_COMP2_Pos _UINT32_(7) /* (RTC_MODE1_SYNCBUSY) COMP 2 Register Busy Position */ 1064 #define RTC_MODE1_SYNCBUSY_COMP2_Msk (_UINT32_(0x1) << RTC_MODE1_SYNCBUSY_COMP2_Pos) /* (RTC_MODE1_SYNCBUSY) COMP 2 Register Busy Mask */ 1065 #define RTC_MODE1_SYNCBUSY_COMP2(value) (RTC_MODE1_SYNCBUSY_COMP2_Msk & (_UINT32_(value) << RTC_MODE1_SYNCBUSY_COMP2_Pos)) /* Assignment of value for COMP2 in the RTC_MODE1_SYNCBUSY register */ 1066 #define RTC_MODE1_SYNCBUSY_COMP3_Pos _UINT32_(8) /* (RTC_MODE1_SYNCBUSY) COMP 3 Register Busy Position */ 1067 #define RTC_MODE1_SYNCBUSY_COMP3_Msk (_UINT32_(0x1) << RTC_MODE1_SYNCBUSY_COMP3_Pos) /* (RTC_MODE1_SYNCBUSY) COMP 3 Register Busy Mask */ 1068 #define RTC_MODE1_SYNCBUSY_COMP3(value) (RTC_MODE1_SYNCBUSY_COMP3_Msk & (_UINT32_(value) << RTC_MODE1_SYNCBUSY_COMP3_Pos)) /* Assignment of value for COMP3 in the RTC_MODE1_SYNCBUSY register */ 1069 #define RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos _UINT32_(15) /* (RTC_MODE1_SYNCBUSY) Count Synchronization Enable Bit Busy Position */ 1070 #define RTC_MODE1_SYNCBUSY_COUNTSYNC_Msk (_UINT32_(0x1) << RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos) /* (RTC_MODE1_SYNCBUSY) Count Synchronization Enable Bit Busy Mask */ 1071 #define RTC_MODE1_SYNCBUSY_COUNTSYNC(value) (RTC_MODE1_SYNCBUSY_COUNTSYNC_Msk & (_UINT32_(value) << RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos)) /* Assignment of value for COUNTSYNC in the RTC_MODE1_SYNCBUSY register */ 1072 #define RTC_MODE1_SYNCBUSY_GP0_Pos _UINT32_(16) /* (RTC_MODE1_SYNCBUSY) General Purpose 0 Register Busy Position */ 1073 #define RTC_MODE1_SYNCBUSY_GP0_Msk (_UINT32_(0x1) << RTC_MODE1_SYNCBUSY_GP0_Pos) /* (RTC_MODE1_SYNCBUSY) General Purpose 0 Register Busy Mask */ 1074 #define RTC_MODE1_SYNCBUSY_GP0(value) (RTC_MODE1_SYNCBUSY_GP0_Msk & (_UINT32_(value) << RTC_MODE1_SYNCBUSY_GP0_Pos)) /* Assignment of value for GP0 in the RTC_MODE1_SYNCBUSY register */ 1075 #define RTC_MODE1_SYNCBUSY_GP1_Pos _UINT32_(17) /* (RTC_MODE1_SYNCBUSY) General Purpose 1 Register Busy Position */ 1076 #define RTC_MODE1_SYNCBUSY_GP1_Msk (_UINT32_(0x1) << RTC_MODE1_SYNCBUSY_GP1_Pos) /* (RTC_MODE1_SYNCBUSY) General Purpose 1 Register Busy Mask */ 1077 #define RTC_MODE1_SYNCBUSY_GP1(value) (RTC_MODE1_SYNCBUSY_GP1_Msk & (_UINT32_(value) << RTC_MODE1_SYNCBUSY_GP1_Pos)) /* Assignment of value for GP1 in the RTC_MODE1_SYNCBUSY register */ 1078 #define RTC_MODE1_SYNCBUSY_GP2_Pos _UINT32_(18) /* (RTC_MODE1_SYNCBUSY) General Purpose 2 Register Busy Position */ 1079 #define RTC_MODE1_SYNCBUSY_GP2_Msk (_UINT32_(0x1) << RTC_MODE1_SYNCBUSY_GP2_Pos) /* (RTC_MODE1_SYNCBUSY) General Purpose 2 Register Busy Mask */ 1080 #define RTC_MODE1_SYNCBUSY_GP2(value) (RTC_MODE1_SYNCBUSY_GP2_Msk & (_UINT32_(value) << RTC_MODE1_SYNCBUSY_GP2_Pos)) /* Assignment of value for GP2 in the RTC_MODE1_SYNCBUSY register */ 1081 #define RTC_MODE1_SYNCBUSY_GP3_Pos _UINT32_(19) /* (RTC_MODE1_SYNCBUSY) General Purpose 3 Register Busy Position */ 1082 #define RTC_MODE1_SYNCBUSY_GP3_Msk (_UINT32_(0x1) << RTC_MODE1_SYNCBUSY_GP3_Pos) /* (RTC_MODE1_SYNCBUSY) General Purpose 3 Register Busy Mask */ 1083 #define RTC_MODE1_SYNCBUSY_GP3(value) (RTC_MODE1_SYNCBUSY_GP3_Msk & (_UINT32_(value) << RTC_MODE1_SYNCBUSY_GP3_Pos)) /* Assignment of value for GP3 in the RTC_MODE1_SYNCBUSY register */ 1084 #define RTC_MODE1_SYNCBUSY_Msk _UINT32_(0x000F81FF) /* (RTC_MODE1_SYNCBUSY) Register Mask */ 1085 1086 #define RTC_MODE1_SYNCBUSY_COMP_Pos _UINT32_(5) /* (RTC_MODE1_SYNCBUSY Position) COMP x Register Busy */ 1087 #define RTC_MODE1_SYNCBUSY_COMP_Msk (_UINT32_(0xF) << RTC_MODE1_SYNCBUSY_COMP_Pos) /* (RTC_MODE1_SYNCBUSY Mask) COMP */ 1088 #define RTC_MODE1_SYNCBUSY_COMP(value) (RTC_MODE1_SYNCBUSY_COMP_Msk & (_UINT32_(value) << RTC_MODE1_SYNCBUSY_COMP_Pos)) 1089 #define RTC_MODE1_SYNCBUSY_GP_Pos _UINT32_(16) /* (RTC_MODE1_SYNCBUSY Position) General Purpose 3 Register Busy */ 1090 #define RTC_MODE1_SYNCBUSY_GP_Msk (_UINT32_(0xF) << RTC_MODE1_SYNCBUSY_GP_Pos) /* (RTC_MODE1_SYNCBUSY Mask) GP */ 1091 #define RTC_MODE1_SYNCBUSY_GP(value) (RTC_MODE1_SYNCBUSY_GP_Msk & (_UINT32_(value) << RTC_MODE1_SYNCBUSY_GP_Pos)) 1092 1093 /* -------- RTC_MODE2_SYNCBUSY : (RTC Offset: 0x10) ( R/ 32) MODE2 Synchronization Busy Status -------- */ 1094 #define RTC_MODE2_SYNCBUSY_RESETVALUE _UINT32_(0x00) /* (RTC_MODE2_SYNCBUSY) MODE2 Synchronization Busy Status Reset Value */ 1095 1096 #define RTC_MODE2_SYNCBUSY_SWRST_Pos _UINT32_(0) /* (RTC_MODE2_SYNCBUSY) Software Reset Bit Busy Position */ 1097 #define RTC_MODE2_SYNCBUSY_SWRST_Msk (_UINT32_(0x1) << RTC_MODE2_SYNCBUSY_SWRST_Pos) /* (RTC_MODE2_SYNCBUSY) Software Reset Bit Busy Mask */ 1098 #define RTC_MODE2_SYNCBUSY_SWRST(value) (RTC_MODE2_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << RTC_MODE2_SYNCBUSY_SWRST_Pos)) /* Assignment of value for SWRST in the RTC_MODE2_SYNCBUSY register */ 1099 #define RTC_MODE2_SYNCBUSY_ENABLE_Pos _UINT32_(1) /* (RTC_MODE2_SYNCBUSY) Enable Bit Busy Position */ 1100 #define RTC_MODE2_SYNCBUSY_ENABLE_Msk (_UINT32_(0x1) << RTC_MODE2_SYNCBUSY_ENABLE_Pos) /* (RTC_MODE2_SYNCBUSY) Enable Bit Busy Mask */ 1101 #define RTC_MODE2_SYNCBUSY_ENABLE(value) (RTC_MODE2_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << RTC_MODE2_SYNCBUSY_ENABLE_Pos)) /* Assignment of value for ENABLE in the RTC_MODE2_SYNCBUSY register */ 1102 #define RTC_MODE2_SYNCBUSY_FREQCORR_Pos _UINT32_(2) /* (RTC_MODE2_SYNCBUSY) FREQCORR Register Busy Position */ 1103 #define RTC_MODE2_SYNCBUSY_FREQCORR_Msk (_UINT32_(0x1) << RTC_MODE2_SYNCBUSY_FREQCORR_Pos) /* (RTC_MODE2_SYNCBUSY) FREQCORR Register Busy Mask */ 1104 #define RTC_MODE2_SYNCBUSY_FREQCORR(value) (RTC_MODE2_SYNCBUSY_FREQCORR_Msk & (_UINT32_(value) << RTC_MODE2_SYNCBUSY_FREQCORR_Pos)) /* Assignment of value for FREQCORR in the RTC_MODE2_SYNCBUSY register */ 1105 #define RTC_MODE2_SYNCBUSY_CLOCK_Pos _UINT32_(3) /* (RTC_MODE2_SYNCBUSY) CLOCK Register Busy Position */ 1106 #define RTC_MODE2_SYNCBUSY_CLOCK_Msk (_UINT32_(0x1) << RTC_MODE2_SYNCBUSY_CLOCK_Pos) /* (RTC_MODE2_SYNCBUSY) CLOCK Register Busy Mask */ 1107 #define RTC_MODE2_SYNCBUSY_CLOCK(value) (RTC_MODE2_SYNCBUSY_CLOCK_Msk & (_UINT32_(value) << RTC_MODE2_SYNCBUSY_CLOCK_Pos)) /* Assignment of value for CLOCK in the RTC_MODE2_SYNCBUSY register */ 1108 #define RTC_MODE2_SYNCBUSY_ALARM0_Pos _UINT32_(5) /* (RTC_MODE2_SYNCBUSY) ALARM 0 Register Busy Position */ 1109 #define RTC_MODE2_SYNCBUSY_ALARM0_Msk (_UINT32_(0x1) << RTC_MODE2_SYNCBUSY_ALARM0_Pos) /* (RTC_MODE2_SYNCBUSY) ALARM 0 Register Busy Mask */ 1110 #define RTC_MODE2_SYNCBUSY_ALARM0(value) (RTC_MODE2_SYNCBUSY_ALARM0_Msk & (_UINT32_(value) << RTC_MODE2_SYNCBUSY_ALARM0_Pos)) /* Assignment of value for ALARM0 in the RTC_MODE2_SYNCBUSY register */ 1111 #define RTC_MODE2_SYNCBUSY_ALARM1_Pos _UINT32_(6) /* (RTC_MODE2_SYNCBUSY) ALARM 1 Register Busy Position */ 1112 #define RTC_MODE2_SYNCBUSY_ALARM1_Msk (_UINT32_(0x1) << RTC_MODE2_SYNCBUSY_ALARM1_Pos) /* (RTC_MODE2_SYNCBUSY) ALARM 1 Register Busy Mask */ 1113 #define RTC_MODE2_SYNCBUSY_ALARM1(value) (RTC_MODE2_SYNCBUSY_ALARM1_Msk & (_UINT32_(value) << RTC_MODE2_SYNCBUSY_ALARM1_Pos)) /* Assignment of value for ALARM1 in the RTC_MODE2_SYNCBUSY register */ 1114 #define RTC_MODE2_SYNCBUSY_MASK0_Pos _UINT32_(11) /* (RTC_MODE2_SYNCBUSY) MASK 0 Register Busy Position */ 1115 #define RTC_MODE2_SYNCBUSY_MASK0_Msk (_UINT32_(0x1) << RTC_MODE2_SYNCBUSY_MASK0_Pos) /* (RTC_MODE2_SYNCBUSY) MASK 0 Register Busy Mask */ 1116 #define RTC_MODE2_SYNCBUSY_MASK0(value) (RTC_MODE2_SYNCBUSY_MASK0_Msk & (_UINT32_(value) << RTC_MODE2_SYNCBUSY_MASK0_Pos)) /* Assignment of value for MASK0 in the RTC_MODE2_SYNCBUSY register */ 1117 #define RTC_MODE2_SYNCBUSY_MASK1_Pos _UINT32_(12) /* (RTC_MODE2_SYNCBUSY) MASK 1 Register Busy Position */ 1118 #define RTC_MODE2_SYNCBUSY_MASK1_Msk (_UINT32_(0x1) << RTC_MODE2_SYNCBUSY_MASK1_Pos) /* (RTC_MODE2_SYNCBUSY) MASK 1 Register Busy Mask */ 1119 #define RTC_MODE2_SYNCBUSY_MASK1(value) (RTC_MODE2_SYNCBUSY_MASK1_Msk & (_UINT32_(value) << RTC_MODE2_SYNCBUSY_MASK1_Pos)) /* Assignment of value for MASK1 in the RTC_MODE2_SYNCBUSY register */ 1120 #define RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos _UINT32_(15) /* (RTC_MODE2_SYNCBUSY) Clock Synchronization Enable Bit Busy Position */ 1121 #define RTC_MODE2_SYNCBUSY_CLOCKSYNC_Msk (_UINT32_(0x1) << RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos) /* (RTC_MODE2_SYNCBUSY) Clock Synchronization Enable Bit Busy Mask */ 1122 #define RTC_MODE2_SYNCBUSY_CLOCKSYNC(value) (RTC_MODE2_SYNCBUSY_CLOCKSYNC_Msk & (_UINT32_(value) << RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos)) /* Assignment of value for CLOCKSYNC in the RTC_MODE2_SYNCBUSY register */ 1123 #define RTC_MODE2_SYNCBUSY_GP0_Pos _UINT32_(16) /* (RTC_MODE2_SYNCBUSY) General Purpose 0 Register Busy Position */ 1124 #define RTC_MODE2_SYNCBUSY_GP0_Msk (_UINT32_(0x1) << RTC_MODE2_SYNCBUSY_GP0_Pos) /* (RTC_MODE2_SYNCBUSY) General Purpose 0 Register Busy Mask */ 1125 #define RTC_MODE2_SYNCBUSY_GP0(value) (RTC_MODE2_SYNCBUSY_GP0_Msk & (_UINT32_(value) << RTC_MODE2_SYNCBUSY_GP0_Pos)) /* Assignment of value for GP0 in the RTC_MODE2_SYNCBUSY register */ 1126 #define RTC_MODE2_SYNCBUSY_GP1_Pos _UINT32_(17) /* (RTC_MODE2_SYNCBUSY) General Purpose 1 Register Busy Position */ 1127 #define RTC_MODE2_SYNCBUSY_GP1_Msk (_UINT32_(0x1) << RTC_MODE2_SYNCBUSY_GP1_Pos) /* (RTC_MODE2_SYNCBUSY) General Purpose 1 Register Busy Mask */ 1128 #define RTC_MODE2_SYNCBUSY_GP1(value) (RTC_MODE2_SYNCBUSY_GP1_Msk & (_UINT32_(value) << RTC_MODE2_SYNCBUSY_GP1_Pos)) /* Assignment of value for GP1 in the RTC_MODE2_SYNCBUSY register */ 1129 #define RTC_MODE2_SYNCBUSY_GP2_Pos _UINT32_(18) /* (RTC_MODE2_SYNCBUSY) General Purpose 2 Register Busy Position */ 1130 #define RTC_MODE2_SYNCBUSY_GP2_Msk (_UINT32_(0x1) << RTC_MODE2_SYNCBUSY_GP2_Pos) /* (RTC_MODE2_SYNCBUSY) General Purpose 2 Register Busy Mask */ 1131 #define RTC_MODE2_SYNCBUSY_GP2(value) (RTC_MODE2_SYNCBUSY_GP2_Msk & (_UINT32_(value) << RTC_MODE2_SYNCBUSY_GP2_Pos)) /* Assignment of value for GP2 in the RTC_MODE2_SYNCBUSY register */ 1132 #define RTC_MODE2_SYNCBUSY_GP3_Pos _UINT32_(19) /* (RTC_MODE2_SYNCBUSY) General Purpose 3 Register Busy Position */ 1133 #define RTC_MODE2_SYNCBUSY_GP3_Msk (_UINT32_(0x1) << RTC_MODE2_SYNCBUSY_GP3_Pos) /* (RTC_MODE2_SYNCBUSY) General Purpose 3 Register Busy Mask */ 1134 #define RTC_MODE2_SYNCBUSY_GP3(value) (RTC_MODE2_SYNCBUSY_GP3_Msk & (_UINT32_(value) << RTC_MODE2_SYNCBUSY_GP3_Pos)) /* Assignment of value for GP3 in the RTC_MODE2_SYNCBUSY register */ 1135 #define RTC_MODE2_SYNCBUSY_Msk _UINT32_(0x000F986F) /* (RTC_MODE2_SYNCBUSY) Register Mask */ 1136 1137 #define RTC_MODE2_SYNCBUSY_ALARM_Pos _UINT32_(5) /* (RTC_MODE2_SYNCBUSY Position) ALARM x Register Busy */ 1138 #define RTC_MODE2_SYNCBUSY_ALARM_Msk (_UINT32_(0x3) << RTC_MODE2_SYNCBUSY_ALARM_Pos) /* (RTC_MODE2_SYNCBUSY Mask) ALARM */ 1139 #define RTC_MODE2_SYNCBUSY_ALARM(value) (RTC_MODE2_SYNCBUSY_ALARM_Msk & (_UINT32_(value) << RTC_MODE2_SYNCBUSY_ALARM_Pos)) 1140 #define RTC_MODE2_SYNCBUSY_MASK_Pos _UINT32_(11) /* (RTC_MODE2_SYNCBUSY Position) MASK x Register Busy */ 1141 #define RTC_MODE2_SYNCBUSY_MASK_Msk (_UINT32_(0x3) << RTC_MODE2_SYNCBUSY_MASK_Pos) /* (RTC_MODE2_SYNCBUSY Mask) MASK */ 1142 #define RTC_MODE2_SYNCBUSY_MASK(value) (RTC_MODE2_SYNCBUSY_MASK_Msk & (_UINT32_(value) << RTC_MODE2_SYNCBUSY_MASK_Pos)) 1143 #define RTC_MODE2_SYNCBUSY_GP_Pos _UINT32_(16) /* (RTC_MODE2_SYNCBUSY Position) General Purpose 3 Register Busy */ 1144 #define RTC_MODE2_SYNCBUSY_GP_Msk (_UINT32_(0xF) << RTC_MODE2_SYNCBUSY_GP_Pos) /* (RTC_MODE2_SYNCBUSY Mask) GP */ 1145 #define RTC_MODE2_SYNCBUSY_GP(value) (RTC_MODE2_SYNCBUSY_GP_Msk & (_UINT32_(value) << RTC_MODE2_SYNCBUSY_GP_Pos)) 1146 1147 /* -------- RTC_FREQCORR : (RTC Offset: 0x14) (R/W 8) Frequency Correction -------- */ 1148 #define RTC_FREQCORR_RESETVALUE _UINT8_(0x00) /* (RTC_FREQCORR) Frequency Correction Reset Value */ 1149 1150 #define RTC_FREQCORR_VALUE_Pos _UINT8_(0) /* (RTC_FREQCORR) Correction Value Position */ 1151 #define RTC_FREQCORR_VALUE_Msk (_UINT8_(0x7F) << RTC_FREQCORR_VALUE_Pos) /* (RTC_FREQCORR) Correction Value Mask */ 1152 #define RTC_FREQCORR_VALUE(value) (RTC_FREQCORR_VALUE_Msk & (_UINT8_(value) << RTC_FREQCORR_VALUE_Pos)) /* Assignment of value for VALUE in the RTC_FREQCORR register */ 1153 #define RTC_FREQCORR_SIGN_Pos _UINT8_(7) /* (RTC_FREQCORR) Correction Sign Position */ 1154 #define RTC_FREQCORR_SIGN_Msk (_UINT8_(0x1) << RTC_FREQCORR_SIGN_Pos) /* (RTC_FREQCORR) Correction Sign Mask */ 1155 #define RTC_FREQCORR_SIGN(value) (RTC_FREQCORR_SIGN_Msk & (_UINT8_(value) << RTC_FREQCORR_SIGN_Pos)) /* Assignment of value for SIGN in the RTC_FREQCORR register */ 1156 #define RTC_FREQCORR_Msk _UINT8_(0xFF) /* (RTC_FREQCORR) Register Mask */ 1157 1158 1159 /* -------- RTC_MODE0_COUNT : (RTC Offset: 0x18) (R/W 32) MODE0 Counter Value -------- */ 1160 #define RTC_MODE0_COUNT_RESETVALUE _UINT32_(0x00) /* (RTC_MODE0_COUNT) MODE0 Counter Value Reset Value */ 1161 1162 #define RTC_MODE0_COUNT_COUNT_Pos _UINT32_(0) /* (RTC_MODE0_COUNT) Counter Value Position */ 1163 #define RTC_MODE0_COUNT_COUNT_Msk (_UINT32_(0xFFFFFFFF) << RTC_MODE0_COUNT_COUNT_Pos) /* (RTC_MODE0_COUNT) Counter Value Mask */ 1164 #define RTC_MODE0_COUNT_COUNT(value) (RTC_MODE0_COUNT_COUNT_Msk & (_UINT32_(value) << RTC_MODE0_COUNT_COUNT_Pos)) /* Assignment of value for COUNT in the RTC_MODE0_COUNT register */ 1165 #define RTC_MODE0_COUNT_Msk _UINT32_(0xFFFFFFFF) /* (RTC_MODE0_COUNT) Register Mask */ 1166 1167 1168 /* -------- RTC_MODE1_COUNT : (RTC Offset: 0x18) (R/W 16) MODE1 Counter Value -------- */ 1169 #define RTC_MODE1_COUNT_RESETVALUE _UINT16_(0x00) /* (RTC_MODE1_COUNT) MODE1 Counter Value Reset Value */ 1170 1171 #define RTC_MODE1_COUNT_COUNT_Pos _UINT16_(0) /* (RTC_MODE1_COUNT) Counter Value Position */ 1172 #define RTC_MODE1_COUNT_COUNT_Msk (_UINT16_(0xFFFF) << RTC_MODE1_COUNT_COUNT_Pos) /* (RTC_MODE1_COUNT) Counter Value Mask */ 1173 #define RTC_MODE1_COUNT_COUNT(value) (RTC_MODE1_COUNT_COUNT_Msk & (_UINT16_(value) << RTC_MODE1_COUNT_COUNT_Pos)) /* Assignment of value for COUNT in the RTC_MODE1_COUNT register */ 1174 #define RTC_MODE1_COUNT_Msk _UINT16_(0xFFFF) /* (RTC_MODE1_COUNT) Register Mask */ 1175 1176 1177 /* -------- RTC_MODE2_CLOCK : (RTC Offset: 0x18) (R/W 32) MODE2 Clock Value -------- */ 1178 #define RTC_MODE2_CLOCK_RESETVALUE _UINT32_(0x00) /* (RTC_MODE2_CLOCK) MODE2 Clock Value Reset Value */ 1179 1180 #define RTC_MODE2_CLOCK_SECOND_Pos _UINT32_(0) /* (RTC_MODE2_CLOCK) Second Position */ 1181 #define RTC_MODE2_CLOCK_SECOND_Msk (_UINT32_(0x3F) << RTC_MODE2_CLOCK_SECOND_Pos) /* (RTC_MODE2_CLOCK) Second Mask */ 1182 #define RTC_MODE2_CLOCK_SECOND(value) (RTC_MODE2_CLOCK_SECOND_Msk & (_UINT32_(value) << RTC_MODE2_CLOCK_SECOND_Pos)) /* Assignment of value for SECOND in the RTC_MODE2_CLOCK register */ 1183 #define RTC_MODE2_CLOCK_MINUTE_Pos _UINT32_(6) /* (RTC_MODE2_CLOCK) Minute Position */ 1184 #define RTC_MODE2_CLOCK_MINUTE_Msk (_UINT32_(0x3F) << RTC_MODE2_CLOCK_MINUTE_Pos) /* (RTC_MODE2_CLOCK) Minute Mask */ 1185 #define RTC_MODE2_CLOCK_MINUTE(value) (RTC_MODE2_CLOCK_MINUTE_Msk & (_UINT32_(value) << RTC_MODE2_CLOCK_MINUTE_Pos)) /* Assignment of value for MINUTE in the RTC_MODE2_CLOCK register */ 1186 #define RTC_MODE2_CLOCK_HOUR_Pos _UINT32_(12) /* (RTC_MODE2_CLOCK) Hour Position */ 1187 #define RTC_MODE2_CLOCK_HOUR_Msk (_UINT32_(0x1F) << RTC_MODE2_CLOCK_HOUR_Pos) /* (RTC_MODE2_CLOCK) Hour Mask */ 1188 #define RTC_MODE2_CLOCK_HOUR(value) (RTC_MODE2_CLOCK_HOUR_Msk & (_UINT32_(value) << RTC_MODE2_CLOCK_HOUR_Pos)) /* Assignment of value for HOUR in the RTC_MODE2_CLOCK register */ 1189 #define RTC_MODE2_CLOCK_HOUR_AM_Val _UINT32_(0x0) /* (RTC_MODE2_CLOCK) AM when CLKREP in 12-hour */ 1190 #define RTC_MODE2_CLOCK_HOUR_PM_Val _UINT32_(0x10) /* (RTC_MODE2_CLOCK) PM when CLKREP in 12-hour */ 1191 #define RTC_MODE2_CLOCK_HOUR_AM (RTC_MODE2_CLOCK_HOUR_AM_Val << RTC_MODE2_CLOCK_HOUR_Pos) /* (RTC_MODE2_CLOCK) AM when CLKREP in 12-hour Position */ 1192 #define RTC_MODE2_CLOCK_HOUR_PM (RTC_MODE2_CLOCK_HOUR_PM_Val << RTC_MODE2_CLOCK_HOUR_Pos) /* (RTC_MODE2_CLOCK) PM when CLKREP in 12-hour Position */ 1193 #define RTC_MODE2_CLOCK_DAY_Pos _UINT32_(17) /* (RTC_MODE2_CLOCK) Day Position */ 1194 #define RTC_MODE2_CLOCK_DAY_Msk (_UINT32_(0x1F) << RTC_MODE2_CLOCK_DAY_Pos) /* (RTC_MODE2_CLOCK) Day Mask */ 1195 #define RTC_MODE2_CLOCK_DAY(value) (RTC_MODE2_CLOCK_DAY_Msk & (_UINT32_(value) << RTC_MODE2_CLOCK_DAY_Pos)) /* Assignment of value for DAY in the RTC_MODE2_CLOCK register */ 1196 #define RTC_MODE2_CLOCK_MONTH_Pos _UINT32_(22) /* (RTC_MODE2_CLOCK) Month Position */ 1197 #define RTC_MODE2_CLOCK_MONTH_Msk (_UINT32_(0xF) << RTC_MODE2_CLOCK_MONTH_Pos) /* (RTC_MODE2_CLOCK) Month Mask */ 1198 #define RTC_MODE2_CLOCK_MONTH(value) (RTC_MODE2_CLOCK_MONTH_Msk & (_UINT32_(value) << RTC_MODE2_CLOCK_MONTH_Pos)) /* Assignment of value for MONTH in the RTC_MODE2_CLOCK register */ 1199 #define RTC_MODE2_CLOCK_YEAR_Pos _UINT32_(26) /* (RTC_MODE2_CLOCK) Year Position */ 1200 #define RTC_MODE2_CLOCK_YEAR_Msk (_UINT32_(0x3F) << RTC_MODE2_CLOCK_YEAR_Pos) /* (RTC_MODE2_CLOCK) Year Mask */ 1201 #define RTC_MODE2_CLOCK_YEAR(value) (RTC_MODE2_CLOCK_YEAR_Msk & (_UINT32_(value) << RTC_MODE2_CLOCK_YEAR_Pos)) /* Assignment of value for YEAR in the RTC_MODE2_CLOCK register */ 1202 #define RTC_MODE2_CLOCK_Msk _UINT32_(0xFFFFFFFF) /* (RTC_MODE2_CLOCK) Register Mask */ 1203 1204 1205 /* -------- RTC_MODE1_PER : (RTC Offset: 0x1C) (R/W 16) MODE1 Counter Period -------- */ 1206 #define RTC_MODE1_PER_RESETVALUE _UINT16_(0x00) /* (RTC_MODE1_PER) MODE1 Counter Period Reset Value */ 1207 1208 #define RTC_MODE1_PER_PER_Pos _UINT16_(0) /* (RTC_MODE1_PER) Counter Period Position */ 1209 #define RTC_MODE1_PER_PER_Msk (_UINT16_(0xFFFF) << RTC_MODE1_PER_PER_Pos) /* (RTC_MODE1_PER) Counter Period Mask */ 1210 #define RTC_MODE1_PER_PER(value) (RTC_MODE1_PER_PER_Msk & (_UINT16_(value) << RTC_MODE1_PER_PER_Pos)) /* Assignment of value for PER in the RTC_MODE1_PER register */ 1211 #define RTC_MODE1_PER_Msk _UINT16_(0xFFFF) /* (RTC_MODE1_PER) Register Mask */ 1212 1213 1214 /* -------- RTC_MODE0_COMP : (RTC Offset: 0x20) (R/W 32) MODE0 Compare n Value -------- */ 1215 #define RTC_MODE0_COMP_RESETVALUE _UINT32_(0x00) /* (RTC_MODE0_COMP) MODE0 Compare n Value Reset Value */ 1216 1217 #define RTC_MODE0_COMP_COMP_Pos _UINT32_(0) /* (RTC_MODE0_COMP) Compare Value Position */ 1218 #define RTC_MODE0_COMP_COMP_Msk (_UINT32_(0xFFFFFFFF) << RTC_MODE0_COMP_COMP_Pos) /* (RTC_MODE0_COMP) Compare Value Mask */ 1219 #define RTC_MODE0_COMP_COMP(value) (RTC_MODE0_COMP_COMP_Msk & (_UINT32_(value) << RTC_MODE0_COMP_COMP_Pos)) /* Assignment of value for COMP in the RTC_MODE0_COMP register */ 1220 #define RTC_MODE0_COMP_Msk _UINT32_(0xFFFFFFFF) /* (RTC_MODE0_COMP) Register Mask */ 1221 1222 1223 /* -------- RTC_MODE1_COMP : (RTC Offset: 0x20) (R/W 16) MODE1 Compare n Value -------- */ 1224 #define RTC_MODE1_COMP_RESETVALUE _UINT16_(0x00) /* (RTC_MODE1_COMP) MODE1 Compare n Value Reset Value */ 1225 1226 #define RTC_MODE1_COMP_COMP_Pos _UINT16_(0) /* (RTC_MODE1_COMP) Compare Value Position */ 1227 #define RTC_MODE1_COMP_COMP_Msk (_UINT16_(0xFFFF) << RTC_MODE1_COMP_COMP_Pos) /* (RTC_MODE1_COMP) Compare Value Mask */ 1228 #define RTC_MODE1_COMP_COMP(value) (RTC_MODE1_COMP_COMP_Msk & (_UINT16_(value) << RTC_MODE1_COMP_COMP_Pos)) /* Assignment of value for COMP in the RTC_MODE1_COMP register */ 1229 #define RTC_MODE1_COMP_Msk _UINT16_(0xFFFF) /* (RTC_MODE1_COMP) Register Mask */ 1230 1231 1232 /* -------- RTC_MODE2_ALARM0 : (RTC Offset: 0x20) (R/W 32) MODE2_ALARM Alarm n Value -------- */ 1233 #define RTC_MODE2_ALARM0_RESETVALUE _UINT32_(0x00) /* (RTC_MODE2_ALARM0) MODE2_ALARM Alarm n Value Reset Value */ 1234 1235 #define RTC_MODE2_ALARM0_SECOND_Pos _UINT32_(0) /* (RTC_MODE2_ALARM0) Second Position */ 1236 #define RTC_MODE2_ALARM0_SECOND_Msk (_UINT32_(0x3F) << RTC_MODE2_ALARM0_SECOND_Pos) /* (RTC_MODE2_ALARM0) Second Mask */ 1237 #define RTC_MODE2_ALARM0_SECOND(value) (RTC_MODE2_ALARM0_SECOND_Msk & (_UINT32_(value) << RTC_MODE2_ALARM0_SECOND_Pos)) /* Assignment of value for SECOND in the RTC_MODE2_ALARM0 register */ 1238 #define RTC_MODE2_ALARM0_MINUTE_Pos _UINT32_(6) /* (RTC_MODE2_ALARM0) Minute Position */ 1239 #define RTC_MODE2_ALARM0_MINUTE_Msk (_UINT32_(0x3F) << RTC_MODE2_ALARM0_MINUTE_Pos) /* (RTC_MODE2_ALARM0) Minute Mask */ 1240 #define RTC_MODE2_ALARM0_MINUTE(value) (RTC_MODE2_ALARM0_MINUTE_Msk & (_UINT32_(value) << RTC_MODE2_ALARM0_MINUTE_Pos)) /* Assignment of value for MINUTE in the RTC_MODE2_ALARM0 register */ 1241 #define RTC_MODE2_ALARM0_HOUR_Pos _UINT32_(12) /* (RTC_MODE2_ALARM0) Hour Position */ 1242 #define RTC_MODE2_ALARM0_HOUR_Msk (_UINT32_(0x1F) << RTC_MODE2_ALARM0_HOUR_Pos) /* (RTC_MODE2_ALARM0) Hour Mask */ 1243 #define RTC_MODE2_ALARM0_HOUR(value) (RTC_MODE2_ALARM0_HOUR_Msk & (_UINT32_(value) << RTC_MODE2_ALARM0_HOUR_Pos)) /* Assignment of value for HOUR in the RTC_MODE2_ALARM0 register */ 1244 #define RTC_MODE2_ALARM0_HOUR_AM_Val _UINT32_(0x0) /* (RTC_MODE2_ALARM0) Morning hour */ 1245 #define RTC_MODE2_ALARM0_HOUR_PM_Val _UINT32_(0x10) /* (RTC_MODE2_ALARM0) Afternoon hour */ 1246 #define RTC_MODE2_ALARM0_HOUR_AM (RTC_MODE2_ALARM0_HOUR_AM_Val << RTC_MODE2_ALARM0_HOUR_Pos) /* (RTC_MODE2_ALARM0) Morning hour Position */ 1247 #define RTC_MODE2_ALARM0_HOUR_PM (RTC_MODE2_ALARM0_HOUR_PM_Val << RTC_MODE2_ALARM0_HOUR_Pos) /* (RTC_MODE2_ALARM0) Afternoon hour Position */ 1248 #define RTC_MODE2_ALARM0_DAY_Pos _UINT32_(17) /* (RTC_MODE2_ALARM0) Day Position */ 1249 #define RTC_MODE2_ALARM0_DAY_Msk (_UINT32_(0x1F) << RTC_MODE2_ALARM0_DAY_Pos) /* (RTC_MODE2_ALARM0) Day Mask */ 1250 #define RTC_MODE2_ALARM0_DAY(value) (RTC_MODE2_ALARM0_DAY_Msk & (_UINT32_(value) << RTC_MODE2_ALARM0_DAY_Pos)) /* Assignment of value for DAY in the RTC_MODE2_ALARM0 register */ 1251 #define RTC_MODE2_ALARM0_MONTH_Pos _UINT32_(22) /* (RTC_MODE2_ALARM0) Month Position */ 1252 #define RTC_MODE2_ALARM0_MONTH_Msk (_UINT32_(0xF) << RTC_MODE2_ALARM0_MONTH_Pos) /* (RTC_MODE2_ALARM0) Month Mask */ 1253 #define RTC_MODE2_ALARM0_MONTH(value) (RTC_MODE2_ALARM0_MONTH_Msk & (_UINT32_(value) << RTC_MODE2_ALARM0_MONTH_Pos)) /* Assignment of value for MONTH in the RTC_MODE2_ALARM0 register */ 1254 #define RTC_MODE2_ALARM0_YEAR_Pos _UINT32_(26) /* (RTC_MODE2_ALARM0) Year Position */ 1255 #define RTC_MODE2_ALARM0_YEAR_Msk (_UINT32_(0x3F) << RTC_MODE2_ALARM0_YEAR_Pos) /* (RTC_MODE2_ALARM0) Year Mask */ 1256 #define RTC_MODE2_ALARM0_YEAR(value) (RTC_MODE2_ALARM0_YEAR_Msk & (_UINT32_(value) << RTC_MODE2_ALARM0_YEAR_Pos)) /* Assignment of value for YEAR in the RTC_MODE2_ALARM0 register */ 1257 #define RTC_MODE2_ALARM0_Msk _UINT32_(0xFFFFFFFF) /* (RTC_MODE2_ALARM0) Register Mask */ 1258 1259 1260 /* -------- RTC_MODE2_MASK0 : (RTC Offset: 0x24) (R/W 8) MODE2_ALARM Alarm n Mask -------- */ 1261 #define RTC_MODE2_MASK0_RESETVALUE _UINT8_(0x00) /* (RTC_MODE2_MASK0) MODE2_ALARM Alarm n Mask Reset Value */ 1262 1263 #define RTC_MODE2_MASK0_SEL_Pos _UINT8_(0) /* (RTC_MODE2_MASK0) Alarm Mask Selection Position */ 1264 #define RTC_MODE2_MASK0_SEL_Msk (_UINT8_(0x7) << RTC_MODE2_MASK0_SEL_Pos) /* (RTC_MODE2_MASK0) Alarm Mask Selection Mask */ 1265 #define RTC_MODE2_MASK0_SEL(value) (RTC_MODE2_MASK0_SEL_Msk & (_UINT8_(value) << RTC_MODE2_MASK0_SEL_Pos)) /* Assignment of value for SEL in the RTC_MODE2_MASK0 register */ 1266 #define RTC_MODE2_MASK0_SEL_OFF_Val _UINT8_(0x0) /* (RTC_MODE2_MASK0) Alarm Disabled */ 1267 #define RTC_MODE2_MASK0_SEL_SS_Val _UINT8_(0x1) /* (RTC_MODE2_MASK0) Match seconds only */ 1268 #define RTC_MODE2_MASK0_SEL_MMSS_Val _UINT8_(0x2) /* (RTC_MODE2_MASK0) Match seconds and minutes only */ 1269 #define RTC_MODE2_MASK0_SEL_HHMMSS_Val _UINT8_(0x3) /* (RTC_MODE2_MASK0) Match seconds, minutes, and hours only */ 1270 #define RTC_MODE2_MASK0_SEL_DDHHMMSS_Val _UINT8_(0x4) /* (RTC_MODE2_MASK0) Match seconds, minutes, hours, and days only */ 1271 #define RTC_MODE2_MASK0_SEL_MMDDHHMMSS_Val _UINT8_(0x5) /* (RTC_MODE2_MASK0) Match seconds, minutes, hours, days, and months only */ 1272 #define RTC_MODE2_MASK0_SEL_YYMMDDHHMMSS_Val _UINT8_(0x6) /* (RTC_MODE2_MASK0) Match seconds, minutes, hours, days, months, and years */ 1273 #define RTC_MODE2_MASK0_SEL_OFF (RTC_MODE2_MASK0_SEL_OFF_Val << RTC_MODE2_MASK0_SEL_Pos) /* (RTC_MODE2_MASK0) Alarm Disabled Position */ 1274 #define RTC_MODE2_MASK0_SEL_SS (RTC_MODE2_MASK0_SEL_SS_Val << RTC_MODE2_MASK0_SEL_Pos) /* (RTC_MODE2_MASK0) Match seconds only Position */ 1275 #define RTC_MODE2_MASK0_SEL_MMSS (RTC_MODE2_MASK0_SEL_MMSS_Val << RTC_MODE2_MASK0_SEL_Pos) /* (RTC_MODE2_MASK0) Match seconds and minutes only Position */ 1276 #define RTC_MODE2_MASK0_SEL_HHMMSS (RTC_MODE2_MASK0_SEL_HHMMSS_Val << RTC_MODE2_MASK0_SEL_Pos) /* (RTC_MODE2_MASK0) Match seconds, minutes, and hours only Position */ 1277 #define RTC_MODE2_MASK0_SEL_DDHHMMSS (RTC_MODE2_MASK0_SEL_DDHHMMSS_Val << RTC_MODE2_MASK0_SEL_Pos) /* (RTC_MODE2_MASK0) Match seconds, minutes, hours, and days only Position */ 1278 #define RTC_MODE2_MASK0_SEL_MMDDHHMMSS (RTC_MODE2_MASK0_SEL_MMDDHHMMSS_Val << RTC_MODE2_MASK0_SEL_Pos) /* (RTC_MODE2_MASK0) Match seconds, minutes, hours, days, and months only Position */ 1279 #define RTC_MODE2_MASK0_SEL_YYMMDDHHMMSS (RTC_MODE2_MASK0_SEL_YYMMDDHHMMSS_Val << RTC_MODE2_MASK0_SEL_Pos) /* (RTC_MODE2_MASK0) Match seconds, minutes, hours, days, months, and years Position */ 1280 #define RTC_MODE2_MASK0_Msk _UINT8_(0x07) /* (RTC_MODE2_MASK0) Register Mask */ 1281 1282 1283 /* -------- RTC_MODE2_ALARM1 : (RTC Offset: 0x28) (R/W 32) MODE2_ALARM Alarm n Value -------- */ 1284 #define RTC_MODE2_ALARM1_RESETVALUE _UINT32_(0x00) /* (RTC_MODE2_ALARM1) MODE2_ALARM Alarm n Value Reset Value */ 1285 1286 #define RTC_MODE2_ALARM1_SECOND_Pos _UINT32_(0) /* (RTC_MODE2_ALARM1) Second Position */ 1287 #define RTC_MODE2_ALARM1_SECOND_Msk (_UINT32_(0x3F) << RTC_MODE2_ALARM1_SECOND_Pos) /* (RTC_MODE2_ALARM1) Second Mask */ 1288 #define RTC_MODE2_ALARM1_SECOND(value) (RTC_MODE2_ALARM1_SECOND_Msk & (_UINT32_(value) << RTC_MODE2_ALARM1_SECOND_Pos)) /* Assignment of value for SECOND in the RTC_MODE2_ALARM1 register */ 1289 #define RTC_MODE2_ALARM1_MINUTE_Pos _UINT32_(6) /* (RTC_MODE2_ALARM1) Minute Position */ 1290 #define RTC_MODE2_ALARM1_MINUTE_Msk (_UINT32_(0x3F) << RTC_MODE2_ALARM1_MINUTE_Pos) /* (RTC_MODE2_ALARM1) Minute Mask */ 1291 #define RTC_MODE2_ALARM1_MINUTE(value) (RTC_MODE2_ALARM1_MINUTE_Msk & (_UINT32_(value) << RTC_MODE2_ALARM1_MINUTE_Pos)) /* Assignment of value for MINUTE in the RTC_MODE2_ALARM1 register */ 1292 #define RTC_MODE2_ALARM1_HOUR_Pos _UINT32_(12) /* (RTC_MODE2_ALARM1) Hour Position */ 1293 #define RTC_MODE2_ALARM1_HOUR_Msk (_UINT32_(0x1F) << RTC_MODE2_ALARM1_HOUR_Pos) /* (RTC_MODE2_ALARM1) Hour Mask */ 1294 #define RTC_MODE2_ALARM1_HOUR(value) (RTC_MODE2_ALARM1_HOUR_Msk & (_UINT32_(value) << RTC_MODE2_ALARM1_HOUR_Pos)) /* Assignment of value for HOUR in the RTC_MODE2_ALARM1 register */ 1295 #define RTC_MODE2_ALARM1_HOUR_AM_Val _UINT32_(0x0) /* (RTC_MODE2_ALARM1) Morning hour */ 1296 #define RTC_MODE2_ALARM1_HOUR_PM_Val _UINT32_(0x10) /* (RTC_MODE2_ALARM1) Afternoon hour */ 1297 #define RTC_MODE2_ALARM1_HOUR_AM (RTC_MODE2_ALARM1_HOUR_AM_Val << RTC_MODE2_ALARM1_HOUR_Pos) /* (RTC_MODE2_ALARM1) Morning hour Position */ 1298 #define RTC_MODE2_ALARM1_HOUR_PM (RTC_MODE2_ALARM1_HOUR_PM_Val << RTC_MODE2_ALARM1_HOUR_Pos) /* (RTC_MODE2_ALARM1) Afternoon hour Position */ 1299 #define RTC_MODE2_ALARM1_DAY_Pos _UINT32_(17) /* (RTC_MODE2_ALARM1) Day Position */ 1300 #define RTC_MODE2_ALARM1_DAY_Msk (_UINT32_(0x1F) << RTC_MODE2_ALARM1_DAY_Pos) /* (RTC_MODE2_ALARM1) Day Mask */ 1301 #define RTC_MODE2_ALARM1_DAY(value) (RTC_MODE2_ALARM1_DAY_Msk & (_UINT32_(value) << RTC_MODE2_ALARM1_DAY_Pos)) /* Assignment of value for DAY in the RTC_MODE2_ALARM1 register */ 1302 #define RTC_MODE2_ALARM1_MONTH_Pos _UINT32_(22) /* (RTC_MODE2_ALARM1) Month Position */ 1303 #define RTC_MODE2_ALARM1_MONTH_Msk (_UINT32_(0xF) << RTC_MODE2_ALARM1_MONTH_Pos) /* (RTC_MODE2_ALARM1) Month Mask */ 1304 #define RTC_MODE2_ALARM1_MONTH(value) (RTC_MODE2_ALARM1_MONTH_Msk & (_UINT32_(value) << RTC_MODE2_ALARM1_MONTH_Pos)) /* Assignment of value for MONTH in the RTC_MODE2_ALARM1 register */ 1305 #define RTC_MODE2_ALARM1_YEAR_Pos _UINT32_(26) /* (RTC_MODE2_ALARM1) Year Position */ 1306 #define RTC_MODE2_ALARM1_YEAR_Msk (_UINT32_(0x3F) << RTC_MODE2_ALARM1_YEAR_Pos) /* (RTC_MODE2_ALARM1) Year Mask */ 1307 #define RTC_MODE2_ALARM1_YEAR(value) (RTC_MODE2_ALARM1_YEAR_Msk & (_UINT32_(value) << RTC_MODE2_ALARM1_YEAR_Pos)) /* Assignment of value for YEAR in the RTC_MODE2_ALARM1 register */ 1308 #define RTC_MODE2_ALARM1_Msk _UINT32_(0xFFFFFFFF) /* (RTC_MODE2_ALARM1) Register Mask */ 1309 1310 1311 /* -------- RTC_MODE2_MASK1 : (RTC Offset: 0x2C) (R/W 8) MODE2_ALARM Alarm n Mask -------- */ 1312 #define RTC_MODE2_MASK1_RESETVALUE _UINT8_(0x00) /* (RTC_MODE2_MASK1) MODE2_ALARM Alarm n Mask Reset Value */ 1313 1314 #define RTC_MODE2_MASK1_SEL_Pos _UINT8_(0) /* (RTC_MODE2_MASK1) Alarm Mask Selection Position */ 1315 #define RTC_MODE2_MASK1_SEL_Msk (_UINT8_(0x7) << RTC_MODE2_MASK1_SEL_Pos) /* (RTC_MODE2_MASK1) Alarm Mask Selection Mask */ 1316 #define RTC_MODE2_MASK1_SEL(value) (RTC_MODE2_MASK1_SEL_Msk & (_UINT8_(value) << RTC_MODE2_MASK1_SEL_Pos)) /* Assignment of value for SEL in the RTC_MODE2_MASK1 register */ 1317 #define RTC_MODE2_MASK1_SEL_OFF_Val _UINT8_(0x0) /* (RTC_MODE2_MASK1) Alarm Disabled */ 1318 #define RTC_MODE2_MASK1_SEL_SS_Val _UINT8_(0x1) /* (RTC_MODE2_MASK1) Match seconds only */ 1319 #define RTC_MODE2_MASK1_SEL_MMSS_Val _UINT8_(0x2) /* (RTC_MODE2_MASK1) Match seconds and minutes only */ 1320 #define RTC_MODE2_MASK1_SEL_HHMMSS_Val _UINT8_(0x3) /* (RTC_MODE2_MASK1) Match seconds, minutes, and hours only */ 1321 #define RTC_MODE2_MASK1_SEL_DDHHMMSS_Val _UINT8_(0x4) /* (RTC_MODE2_MASK1) Match seconds, minutes, hours, and days only */ 1322 #define RTC_MODE2_MASK1_SEL_MMDDHHMMSS_Val _UINT8_(0x5) /* (RTC_MODE2_MASK1) Match seconds, minutes, hours, days, and months only */ 1323 #define RTC_MODE2_MASK1_SEL_YYMMDDHHMMSS_Val _UINT8_(0x6) /* (RTC_MODE2_MASK1) Match seconds, minutes, hours, days, months, and years */ 1324 #define RTC_MODE2_MASK1_SEL_OFF (RTC_MODE2_MASK1_SEL_OFF_Val << RTC_MODE2_MASK1_SEL_Pos) /* (RTC_MODE2_MASK1) Alarm Disabled Position */ 1325 #define RTC_MODE2_MASK1_SEL_SS (RTC_MODE2_MASK1_SEL_SS_Val << RTC_MODE2_MASK1_SEL_Pos) /* (RTC_MODE2_MASK1) Match seconds only Position */ 1326 #define RTC_MODE2_MASK1_SEL_MMSS (RTC_MODE2_MASK1_SEL_MMSS_Val << RTC_MODE2_MASK1_SEL_Pos) /* (RTC_MODE2_MASK1) Match seconds and minutes only Position */ 1327 #define RTC_MODE2_MASK1_SEL_HHMMSS (RTC_MODE2_MASK1_SEL_HHMMSS_Val << RTC_MODE2_MASK1_SEL_Pos) /* (RTC_MODE2_MASK1) Match seconds, minutes, and hours only Position */ 1328 #define RTC_MODE2_MASK1_SEL_DDHHMMSS (RTC_MODE2_MASK1_SEL_DDHHMMSS_Val << RTC_MODE2_MASK1_SEL_Pos) /* (RTC_MODE2_MASK1) Match seconds, minutes, hours, and days only Position */ 1329 #define RTC_MODE2_MASK1_SEL_MMDDHHMMSS (RTC_MODE2_MASK1_SEL_MMDDHHMMSS_Val << RTC_MODE2_MASK1_SEL_Pos) /* (RTC_MODE2_MASK1) Match seconds, minutes, hours, days, and months only Position */ 1330 #define RTC_MODE2_MASK1_SEL_YYMMDDHHMMSS (RTC_MODE2_MASK1_SEL_YYMMDDHHMMSS_Val << RTC_MODE2_MASK1_SEL_Pos) /* (RTC_MODE2_MASK1) Match seconds, minutes, hours, days, months, and years Position */ 1331 #define RTC_MODE2_MASK1_Msk _UINT8_(0x07) /* (RTC_MODE2_MASK1) Register Mask */ 1332 1333 1334 /* -------- RTC_GP : (RTC Offset: 0x40) (R/W 32) General Purpose -------- */ 1335 #define RTC_GP_RESETVALUE _UINT32_(0x00) /* (RTC_GP) General Purpose Reset Value */ 1336 1337 #define RTC_GP_GP_Pos _UINT32_(0) /* (RTC_GP) General Purpose Position */ 1338 #define RTC_GP_GP_Msk (_UINT32_(0xFFFFFFFF) << RTC_GP_GP_Pos) /* (RTC_GP) General Purpose Mask */ 1339 #define RTC_GP_GP(value) (RTC_GP_GP_Msk & (_UINT32_(value) << RTC_GP_GP_Pos)) /* Assignment of value for GP in the RTC_GP register */ 1340 #define RTC_GP_Msk _UINT32_(0xFFFFFFFF) /* (RTC_GP) Register Mask */ 1341 1342 1343 /* -------- RTC_TAMPCTRL : (RTC Offset: 0x60) (R/W 32) Tamper Control -------- */ 1344 #define RTC_TAMPCTRL_RESETVALUE _UINT32_(0x00) /* (RTC_TAMPCTRL) Tamper Control Reset Value */ 1345 1346 #define RTC_TAMPCTRL_IN0ACT_Pos _UINT32_(0) /* (RTC_TAMPCTRL) Tamper Input 0 Action Position */ 1347 #define RTC_TAMPCTRL_IN0ACT_Msk (_UINT32_(0x3) << RTC_TAMPCTRL_IN0ACT_Pos) /* (RTC_TAMPCTRL) Tamper Input 0 Action Mask */ 1348 #define RTC_TAMPCTRL_IN0ACT(value) (RTC_TAMPCTRL_IN0ACT_Msk & (_UINT32_(value) << RTC_TAMPCTRL_IN0ACT_Pos)) /* Assignment of value for IN0ACT in the RTC_TAMPCTRL register */ 1349 #define RTC_TAMPCTRL_IN0ACT_OFF_Val _UINT32_(0x0) /* (RTC_TAMPCTRL) Off (Disabled) */ 1350 #define RTC_TAMPCTRL_IN0ACT_WAKE_Val _UINT32_(0x1) /* (RTC_TAMPCTRL) Wake without timestamp */ 1351 #define RTC_TAMPCTRL_IN0ACT_CAPTURE_Val _UINT32_(0x2) /* (RTC_TAMPCTRL) Capture timestamp */ 1352 #define RTC_TAMPCTRL_IN0ACT_ACTL_Val _UINT32_(0x3) /* (RTC_TAMPCTRL) Compare IN0 to OUT */ 1353 #define RTC_TAMPCTRL_IN0ACT_OFF (RTC_TAMPCTRL_IN0ACT_OFF_Val << RTC_TAMPCTRL_IN0ACT_Pos) /* (RTC_TAMPCTRL) Off (Disabled) Position */ 1354 #define RTC_TAMPCTRL_IN0ACT_WAKE (RTC_TAMPCTRL_IN0ACT_WAKE_Val << RTC_TAMPCTRL_IN0ACT_Pos) /* (RTC_TAMPCTRL) Wake without timestamp Position */ 1355 #define RTC_TAMPCTRL_IN0ACT_CAPTURE (RTC_TAMPCTRL_IN0ACT_CAPTURE_Val << RTC_TAMPCTRL_IN0ACT_Pos) /* (RTC_TAMPCTRL) Capture timestamp Position */ 1356 #define RTC_TAMPCTRL_IN0ACT_ACTL (RTC_TAMPCTRL_IN0ACT_ACTL_Val << RTC_TAMPCTRL_IN0ACT_Pos) /* (RTC_TAMPCTRL) Compare IN0 to OUT Position */ 1357 #define RTC_TAMPCTRL_IN1ACT_Pos _UINT32_(2) /* (RTC_TAMPCTRL) Tamper Input 1 Action Position */ 1358 #define RTC_TAMPCTRL_IN1ACT_Msk (_UINT32_(0x3) << RTC_TAMPCTRL_IN1ACT_Pos) /* (RTC_TAMPCTRL) Tamper Input 1 Action Mask */ 1359 #define RTC_TAMPCTRL_IN1ACT(value) (RTC_TAMPCTRL_IN1ACT_Msk & (_UINT32_(value) << RTC_TAMPCTRL_IN1ACT_Pos)) /* Assignment of value for IN1ACT in the RTC_TAMPCTRL register */ 1360 #define RTC_TAMPCTRL_IN1ACT_OFF_Val _UINT32_(0x0) /* (RTC_TAMPCTRL) Off (Disabled) */ 1361 #define RTC_TAMPCTRL_IN1ACT_WAKE_Val _UINT32_(0x1) /* (RTC_TAMPCTRL) Wake without timestamp */ 1362 #define RTC_TAMPCTRL_IN1ACT_CAPTURE_Val _UINT32_(0x2) /* (RTC_TAMPCTRL) Capture timestamp */ 1363 #define RTC_TAMPCTRL_IN1ACT_ACTL_Val _UINT32_(0x3) /* (RTC_TAMPCTRL) Compare IN1 to OUT */ 1364 #define RTC_TAMPCTRL_IN1ACT_OFF (RTC_TAMPCTRL_IN1ACT_OFF_Val << RTC_TAMPCTRL_IN1ACT_Pos) /* (RTC_TAMPCTRL) Off (Disabled) Position */ 1365 #define RTC_TAMPCTRL_IN1ACT_WAKE (RTC_TAMPCTRL_IN1ACT_WAKE_Val << RTC_TAMPCTRL_IN1ACT_Pos) /* (RTC_TAMPCTRL) Wake without timestamp Position */ 1366 #define RTC_TAMPCTRL_IN1ACT_CAPTURE (RTC_TAMPCTRL_IN1ACT_CAPTURE_Val << RTC_TAMPCTRL_IN1ACT_Pos) /* (RTC_TAMPCTRL) Capture timestamp Position */ 1367 #define RTC_TAMPCTRL_IN1ACT_ACTL (RTC_TAMPCTRL_IN1ACT_ACTL_Val << RTC_TAMPCTRL_IN1ACT_Pos) /* (RTC_TAMPCTRL) Compare IN1 to OUT Position */ 1368 #define RTC_TAMPCTRL_IN2ACT_Pos _UINT32_(4) /* (RTC_TAMPCTRL) Tamper Input 2 Action Position */ 1369 #define RTC_TAMPCTRL_IN2ACT_Msk (_UINT32_(0x3) << RTC_TAMPCTRL_IN2ACT_Pos) /* (RTC_TAMPCTRL) Tamper Input 2 Action Mask */ 1370 #define RTC_TAMPCTRL_IN2ACT(value) (RTC_TAMPCTRL_IN2ACT_Msk & (_UINT32_(value) << RTC_TAMPCTRL_IN2ACT_Pos)) /* Assignment of value for IN2ACT in the RTC_TAMPCTRL register */ 1371 #define RTC_TAMPCTRL_IN2ACT_OFF_Val _UINT32_(0x0) /* (RTC_TAMPCTRL) Off (Disabled) */ 1372 #define RTC_TAMPCTRL_IN2ACT_WAKE_Val _UINT32_(0x1) /* (RTC_TAMPCTRL) Wake without timestamp */ 1373 #define RTC_TAMPCTRL_IN2ACT_CAPTURE_Val _UINT32_(0x2) /* (RTC_TAMPCTRL) Capture timestamp */ 1374 #define RTC_TAMPCTRL_IN2ACT_ACTL_Val _UINT32_(0x3) /* (RTC_TAMPCTRL) Compare IN2 to OUT */ 1375 #define RTC_TAMPCTRL_IN2ACT_OFF (RTC_TAMPCTRL_IN2ACT_OFF_Val << RTC_TAMPCTRL_IN2ACT_Pos) /* (RTC_TAMPCTRL) Off (Disabled) Position */ 1376 #define RTC_TAMPCTRL_IN2ACT_WAKE (RTC_TAMPCTRL_IN2ACT_WAKE_Val << RTC_TAMPCTRL_IN2ACT_Pos) /* (RTC_TAMPCTRL) Wake without timestamp Position */ 1377 #define RTC_TAMPCTRL_IN2ACT_CAPTURE (RTC_TAMPCTRL_IN2ACT_CAPTURE_Val << RTC_TAMPCTRL_IN2ACT_Pos) /* (RTC_TAMPCTRL) Capture timestamp Position */ 1378 #define RTC_TAMPCTRL_IN2ACT_ACTL (RTC_TAMPCTRL_IN2ACT_ACTL_Val << RTC_TAMPCTRL_IN2ACT_Pos) /* (RTC_TAMPCTRL) Compare IN2 to OUT Position */ 1379 #define RTC_TAMPCTRL_IN3ACT_Pos _UINT32_(6) /* (RTC_TAMPCTRL) Tamper Input 3 Action Position */ 1380 #define RTC_TAMPCTRL_IN3ACT_Msk (_UINT32_(0x3) << RTC_TAMPCTRL_IN3ACT_Pos) /* (RTC_TAMPCTRL) Tamper Input 3 Action Mask */ 1381 #define RTC_TAMPCTRL_IN3ACT(value) (RTC_TAMPCTRL_IN3ACT_Msk & (_UINT32_(value) << RTC_TAMPCTRL_IN3ACT_Pos)) /* Assignment of value for IN3ACT in the RTC_TAMPCTRL register */ 1382 #define RTC_TAMPCTRL_IN3ACT_OFF_Val _UINT32_(0x0) /* (RTC_TAMPCTRL) Off (Disabled) */ 1383 #define RTC_TAMPCTRL_IN3ACT_WAKE_Val _UINT32_(0x1) /* (RTC_TAMPCTRL) Wake without timestamp */ 1384 #define RTC_TAMPCTRL_IN3ACT_CAPTURE_Val _UINT32_(0x2) /* (RTC_TAMPCTRL) Capture timestamp */ 1385 #define RTC_TAMPCTRL_IN3ACT_ACTL_Val _UINT32_(0x3) /* (RTC_TAMPCTRL) Compare IN3 to OUT */ 1386 #define RTC_TAMPCTRL_IN3ACT_OFF (RTC_TAMPCTRL_IN3ACT_OFF_Val << RTC_TAMPCTRL_IN3ACT_Pos) /* (RTC_TAMPCTRL) Off (Disabled) Position */ 1387 #define RTC_TAMPCTRL_IN3ACT_WAKE (RTC_TAMPCTRL_IN3ACT_WAKE_Val << RTC_TAMPCTRL_IN3ACT_Pos) /* (RTC_TAMPCTRL) Wake without timestamp Position */ 1388 #define RTC_TAMPCTRL_IN3ACT_CAPTURE (RTC_TAMPCTRL_IN3ACT_CAPTURE_Val << RTC_TAMPCTRL_IN3ACT_Pos) /* (RTC_TAMPCTRL) Capture timestamp Position */ 1389 #define RTC_TAMPCTRL_IN3ACT_ACTL (RTC_TAMPCTRL_IN3ACT_ACTL_Val << RTC_TAMPCTRL_IN3ACT_Pos) /* (RTC_TAMPCTRL) Compare IN3 to OUT Position */ 1390 #define RTC_TAMPCTRL_IN4ACT_Pos _UINT32_(8) /* (RTC_TAMPCTRL) Tamper Input 4 Action Position */ 1391 #define RTC_TAMPCTRL_IN4ACT_Msk (_UINT32_(0x3) << RTC_TAMPCTRL_IN4ACT_Pos) /* (RTC_TAMPCTRL) Tamper Input 4 Action Mask */ 1392 #define RTC_TAMPCTRL_IN4ACT(value) (RTC_TAMPCTRL_IN4ACT_Msk & (_UINT32_(value) << RTC_TAMPCTRL_IN4ACT_Pos)) /* Assignment of value for IN4ACT in the RTC_TAMPCTRL register */ 1393 #define RTC_TAMPCTRL_IN4ACT_OFF_Val _UINT32_(0x0) /* (RTC_TAMPCTRL) Off (Disabled) */ 1394 #define RTC_TAMPCTRL_IN4ACT_WAKE_Val _UINT32_(0x1) /* (RTC_TAMPCTRL) Wake without timestamp */ 1395 #define RTC_TAMPCTRL_IN4ACT_CAPTURE_Val _UINT32_(0x2) /* (RTC_TAMPCTRL) Capture timestamp */ 1396 #define RTC_TAMPCTRL_IN4ACT_ACTL_Val _UINT32_(0x3) /* (RTC_TAMPCTRL) Compare IN4 to OUT */ 1397 #define RTC_TAMPCTRL_IN4ACT_OFF (RTC_TAMPCTRL_IN4ACT_OFF_Val << RTC_TAMPCTRL_IN4ACT_Pos) /* (RTC_TAMPCTRL) Off (Disabled) Position */ 1398 #define RTC_TAMPCTRL_IN4ACT_WAKE (RTC_TAMPCTRL_IN4ACT_WAKE_Val << RTC_TAMPCTRL_IN4ACT_Pos) /* (RTC_TAMPCTRL) Wake without timestamp Position */ 1399 #define RTC_TAMPCTRL_IN4ACT_CAPTURE (RTC_TAMPCTRL_IN4ACT_CAPTURE_Val << RTC_TAMPCTRL_IN4ACT_Pos) /* (RTC_TAMPCTRL) Capture timestamp Position */ 1400 #define RTC_TAMPCTRL_IN4ACT_ACTL (RTC_TAMPCTRL_IN4ACT_ACTL_Val << RTC_TAMPCTRL_IN4ACT_Pos) /* (RTC_TAMPCTRL) Compare IN4 to OUT Position */ 1401 #define RTC_TAMPCTRL_TAMLVL0_Pos _UINT32_(16) /* (RTC_TAMPCTRL) Tamper Level Select 0 Position */ 1402 #define RTC_TAMPCTRL_TAMLVL0_Msk (_UINT32_(0x1) << RTC_TAMPCTRL_TAMLVL0_Pos) /* (RTC_TAMPCTRL) Tamper Level Select 0 Mask */ 1403 #define RTC_TAMPCTRL_TAMLVL0(value) (RTC_TAMPCTRL_TAMLVL0_Msk & (_UINT32_(value) << RTC_TAMPCTRL_TAMLVL0_Pos)) /* Assignment of value for TAMLVL0 in the RTC_TAMPCTRL register */ 1404 #define RTC_TAMPCTRL_TAMLVL1_Pos _UINT32_(17) /* (RTC_TAMPCTRL) Tamper Level Select 1 Position */ 1405 #define RTC_TAMPCTRL_TAMLVL1_Msk (_UINT32_(0x1) << RTC_TAMPCTRL_TAMLVL1_Pos) /* (RTC_TAMPCTRL) Tamper Level Select 1 Mask */ 1406 #define RTC_TAMPCTRL_TAMLVL1(value) (RTC_TAMPCTRL_TAMLVL1_Msk & (_UINT32_(value) << RTC_TAMPCTRL_TAMLVL1_Pos)) /* Assignment of value for TAMLVL1 in the RTC_TAMPCTRL register */ 1407 #define RTC_TAMPCTRL_TAMLVL2_Pos _UINT32_(18) /* (RTC_TAMPCTRL) Tamper Level Select 2 Position */ 1408 #define RTC_TAMPCTRL_TAMLVL2_Msk (_UINT32_(0x1) << RTC_TAMPCTRL_TAMLVL2_Pos) /* (RTC_TAMPCTRL) Tamper Level Select 2 Mask */ 1409 #define RTC_TAMPCTRL_TAMLVL2(value) (RTC_TAMPCTRL_TAMLVL2_Msk & (_UINT32_(value) << RTC_TAMPCTRL_TAMLVL2_Pos)) /* Assignment of value for TAMLVL2 in the RTC_TAMPCTRL register */ 1410 #define RTC_TAMPCTRL_TAMLVL3_Pos _UINT32_(19) /* (RTC_TAMPCTRL) Tamper Level Select 3 Position */ 1411 #define RTC_TAMPCTRL_TAMLVL3_Msk (_UINT32_(0x1) << RTC_TAMPCTRL_TAMLVL3_Pos) /* (RTC_TAMPCTRL) Tamper Level Select 3 Mask */ 1412 #define RTC_TAMPCTRL_TAMLVL3(value) (RTC_TAMPCTRL_TAMLVL3_Msk & (_UINT32_(value) << RTC_TAMPCTRL_TAMLVL3_Pos)) /* Assignment of value for TAMLVL3 in the RTC_TAMPCTRL register */ 1413 #define RTC_TAMPCTRL_TAMLVL4_Pos _UINT32_(20) /* (RTC_TAMPCTRL) Tamper Level Select 4 Position */ 1414 #define RTC_TAMPCTRL_TAMLVL4_Msk (_UINT32_(0x1) << RTC_TAMPCTRL_TAMLVL4_Pos) /* (RTC_TAMPCTRL) Tamper Level Select 4 Mask */ 1415 #define RTC_TAMPCTRL_TAMLVL4(value) (RTC_TAMPCTRL_TAMLVL4_Msk & (_UINT32_(value) << RTC_TAMPCTRL_TAMLVL4_Pos)) /* Assignment of value for TAMLVL4 in the RTC_TAMPCTRL register */ 1416 #define RTC_TAMPCTRL_DEBNC0_Pos _UINT32_(24) /* (RTC_TAMPCTRL) Debouncer Enable 0 Position */ 1417 #define RTC_TAMPCTRL_DEBNC0_Msk (_UINT32_(0x1) << RTC_TAMPCTRL_DEBNC0_Pos) /* (RTC_TAMPCTRL) Debouncer Enable 0 Mask */ 1418 #define RTC_TAMPCTRL_DEBNC0(value) (RTC_TAMPCTRL_DEBNC0_Msk & (_UINT32_(value) << RTC_TAMPCTRL_DEBNC0_Pos)) /* Assignment of value for DEBNC0 in the RTC_TAMPCTRL register */ 1419 #define RTC_TAMPCTRL_DEBNC1_Pos _UINT32_(25) /* (RTC_TAMPCTRL) Debouncer Enable 1 Position */ 1420 #define RTC_TAMPCTRL_DEBNC1_Msk (_UINT32_(0x1) << RTC_TAMPCTRL_DEBNC1_Pos) /* (RTC_TAMPCTRL) Debouncer Enable 1 Mask */ 1421 #define RTC_TAMPCTRL_DEBNC1(value) (RTC_TAMPCTRL_DEBNC1_Msk & (_UINT32_(value) << RTC_TAMPCTRL_DEBNC1_Pos)) /* Assignment of value for DEBNC1 in the RTC_TAMPCTRL register */ 1422 #define RTC_TAMPCTRL_DEBNC2_Pos _UINT32_(26) /* (RTC_TAMPCTRL) Debouncer Enable 2 Position */ 1423 #define RTC_TAMPCTRL_DEBNC2_Msk (_UINT32_(0x1) << RTC_TAMPCTRL_DEBNC2_Pos) /* (RTC_TAMPCTRL) Debouncer Enable 2 Mask */ 1424 #define RTC_TAMPCTRL_DEBNC2(value) (RTC_TAMPCTRL_DEBNC2_Msk & (_UINT32_(value) << RTC_TAMPCTRL_DEBNC2_Pos)) /* Assignment of value for DEBNC2 in the RTC_TAMPCTRL register */ 1425 #define RTC_TAMPCTRL_DEBNC3_Pos _UINT32_(27) /* (RTC_TAMPCTRL) Debouncer Enable 3 Position */ 1426 #define RTC_TAMPCTRL_DEBNC3_Msk (_UINT32_(0x1) << RTC_TAMPCTRL_DEBNC3_Pos) /* (RTC_TAMPCTRL) Debouncer Enable 3 Mask */ 1427 #define RTC_TAMPCTRL_DEBNC3(value) (RTC_TAMPCTRL_DEBNC3_Msk & (_UINT32_(value) << RTC_TAMPCTRL_DEBNC3_Pos)) /* Assignment of value for DEBNC3 in the RTC_TAMPCTRL register */ 1428 #define RTC_TAMPCTRL_DEBNC4_Pos _UINT32_(28) /* (RTC_TAMPCTRL) Debouncer Enable 4 Position */ 1429 #define RTC_TAMPCTRL_DEBNC4_Msk (_UINT32_(0x1) << RTC_TAMPCTRL_DEBNC4_Pos) /* (RTC_TAMPCTRL) Debouncer Enable 4 Mask */ 1430 #define RTC_TAMPCTRL_DEBNC4(value) (RTC_TAMPCTRL_DEBNC4_Msk & (_UINT32_(value) << RTC_TAMPCTRL_DEBNC4_Pos)) /* Assignment of value for DEBNC4 in the RTC_TAMPCTRL register */ 1431 #define RTC_TAMPCTRL_Msk _UINT32_(0x1F1F03FF) /* (RTC_TAMPCTRL) Register Mask */ 1432 1433 #define RTC_TAMPCTRL_TAMLVL_Pos _UINT32_(16) /* (RTC_TAMPCTRL Position) Tamper Level Select x */ 1434 #define RTC_TAMPCTRL_TAMLVL_Msk (_UINT32_(0x1F) << RTC_TAMPCTRL_TAMLVL_Pos) /* (RTC_TAMPCTRL Mask) TAMLVL */ 1435 #define RTC_TAMPCTRL_TAMLVL(value) (RTC_TAMPCTRL_TAMLVL_Msk & (_UINT32_(value) << RTC_TAMPCTRL_TAMLVL_Pos)) 1436 #define RTC_TAMPCTRL_DEBNC_Pos _UINT32_(24) /* (RTC_TAMPCTRL Position) Debouncer Enable 4 */ 1437 #define RTC_TAMPCTRL_DEBNC_Msk (_UINT32_(0x1F) << RTC_TAMPCTRL_DEBNC_Pos) /* (RTC_TAMPCTRL Mask) DEBNC */ 1438 #define RTC_TAMPCTRL_DEBNC(value) (RTC_TAMPCTRL_DEBNC_Msk & (_UINT32_(value) << RTC_TAMPCTRL_DEBNC_Pos)) 1439 1440 /* -------- RTC_MODE0_TIMESTAMP : (RTC Offset: 0x64) ( R/ 32) MODE0 Timestamp -------- */ 1441 #define RTC_MODE0_TIMESTAMP_RESETVALUE _UINT32_(0x00) /* (RTC_MODE0_TIMESTAMP) MODE0 Timestamp Reset Value */ 1442 1443 #define RTC_MODE0_TIMESTAMP_COUNT_Pos _UINT32_(0) /* (RTC_MODE0_TIMESTAMP) Count Timestamp Value Position */ 1444 #define RTC_MODE0_TIMESTAMP_COUNT_Msk (_UINT32_(0xFFFFFFFF) << RTC_MODE0_TIMESTAMP_COUNT_Pos) /* (RTC_MODE0_TIMESTAMP) Count Timestamp Value Mask */ 1445 #define RTC_MODE0_TIMESTAMP_COUNT(value) (RTC_MODE0_TIMESTAMP_COUNT_Msk & (_UINT32_(value) << RTC_MODE0_TIMESTAMP_COUNT_Pos)) /* Assignment of value for COUNT in the RTC_MODE0_TIMESTAMP register */ 1446 #define RTC_MODE0_TIMESTAMP_Msk _UINT32_(0xFFFFFFFF) /* (RTC_MODE0_TIMESTAMP) Register Mask */ 1447 1448 1449 /* -------- RTC_MODE1_TIMESTAMP : (RTC Offset: 0x64) ( R/ 32) MODE1 Timestamp -------- */ 1450 #define RTC_MODE1_TIMESTAMP_RESETVALUE _UINT32_(0x00) /* (RTC_MODE1_TIMESTAMP) MODE1 Timestamp Reset Value */ 1451 1452 #define RTC_MODE1_TIMESTAMP_COUNT_Pos _UINT32_(0) /* (RTC_MODE1_TIMESTAMP) Count Timestamp Value Position */ 1453 #define RTC_MODE1_TIMESTAMP_COUNT_Msk (_UINT32_(0xFFFF) << RTC_MODE1_TIMESTAMP_COUNT_Pos) /* (RTC_MODE1_TIMESTAMP) Count Timestamp Value Mask */ 1454 #define RTC_MODE1_TIMESTAMP_COUNT(value) (RTC_MODE1_TIMESTAMP_COUNT_Msk & (_UINT32_(value) << RTC_MODE1_TIMESTAMP_COUNT_Pos)) /* Assignment of value for COUNT in the RTC_MODE1_TIMESTAMP register */ 1455 #define RTC_MODE1_TIMESTAMP_Msk _UINT32_(0x0000FFFF) /* (RTC_MODE1_TIMESTAMP) Register Mask */ 1456 1457 1458 /* -------- RTC_MODE2_TIMESTAMP : (RTC Offset: 0x64) ( R/ 32) MODE2 Timestamp -------- */ 1459 #define RTC_MODE2_TIMESTAMP_RESETVALUE _UINT32_(0x00) /* (RTC_MODE2_TIMESTAMP) MODE2 Timestamp Reset Value */ 1460 1461 #define RTC_MODE2_TIMESTAMP_SECOND_Pos _UINT32_(0) /* (RTC_MODE2_TIMESTAMP) Second Timestamp Value Position */ 1462 #define RTC_MODE2_TIMESTAMP_SECOND_Msk (_UINT32_(0x3F) << RTC_MODE2_TIMESTAMP_SECOND_Pos) /* (RTC_MODE2_TIMESTAMP) Second Timestamp Value Mask */ 1463 #define RTC_MODE2_TIMESTAMP_SECOND(value) (RTC_MODE2_TIMESTAMP_SECOND_Msk & (_UINT32_(value) << RTC_MODE2_TIMESTAMP_SECOND_Pos)) /* Assignment of value for SECOND in the RTC_MODE2_TIMESTAMP register */ 1464 #define RTC_MODE2_TIMESTAMP_MINUTE_Pos _UINT32_(6) /* (RTC_MODE2_TIMESTAMP) Minute Timestamp Value Position */ 1465 #define RTC_MODE2_TIMESTAMP_MINUTE_Msk (_UINT32_(0x3F) << RTC_MODE2_TIMESTAMP_MINUTE_Pos) /* (RTC_MODE2_TIMESTAMP) Minute Timestamp Value Mask */ 1466 #define RTC_MODE2_TIMESTAMP_MINUTE(value) (RTC_MODE2_TIMESTAMP_MINUTE_Msk & (_UINT32_(value) << RTC_MODE2_TIMESTAMP_MINUTE_Pos)) /* Assignment of value for MINUTE in the RTC_MODE2_TIMESTAMP register */ 1467 #define RTC_MODE2_TIMESTAMP_HOUR_Pos _UINT32_(12) /* (RTC_MODE2_TIMESTAMP) Hour Timestamp Value Position */ 1468 #define RTC_MODE2_TIMESTAMP_HOUR_Msk (_UINT32_(0x1F) << RTC_MODE2_TIMESTAMP_HOUR_Pos) /* (RTC_MODE2_TIMESTAMP) Hour Timestamp Value Mask */ 1469 #define RTC_MODE2_TIMESTAMP_HOUR(value) (RTC_MODE2_TIMESTAMP_HOUR_Msk & (_UINT32_(value) << RTC_MODE2_TIMESTAMP_HOUR_Pos)) /* Assignment of value for HOUR in the RTC_MODE2_TIMESTAMP register */ 1470 #define RTC_MODE2_TIMESTAMP_HOUR_AM_Val _UINT32_(0x0) /* (RTC_MODE2_TIMESTAMP) AM when CLKREP in 12-hour */ 1471 #define RTC_MODE2_TIMESTAMP_HOUR_PM_Val _UINT32_(0x10) /* (RTC_MODE2_TIMESTAMP) PM when CLKREP in 12-hour */ 1472 #define RTC_MODE2_TIMESTAMP_HOUR_AM (RTC_MODE2_TIMESTAMP_HOUR_AM_Val << RTC_MODE2_TIMESTAMP_HOUR_Pos) /* (RTC_MODE2_TIMESTAMP) AM when CLKREP in 12-hour Position */ 1473 #define RTC_MODE2_TIMESTAMP_HOUR_PM (RTC_MODE2_TIMESTAMP_HOUR_PM_Val << RTC_MODE2_TIMESTAMP_HOUR_Pos) /* (RTC_MODE2_TIMESTAMP) PM when CLKREP in 12-hour Position */ 1474 #define RTC_MODE2_TIMESTAMP_DAY_Pos _UINT32_(17) /* (RTC_MODE2_TIMESTAMP) Day Timestamp Value Position */ 1475 #define RTC_MODE2_TIMESTAMP_DAY_Msk (_UINT32_(0x1F) << RTC_MODE2_TIMESTAMP_DAY_Pos) /* (RTC_MODE2_TIMESTAMP) Day Timestamp Value Mask */ 1476 #define RTC_MODE2_TIMESTAMP_DAY(value) (RTC_MODE2_TIMESTAMP_DAY_Msk & (_UINT32_(value) << RTC_MODE2_TIMESTAMP_DAY_Pos)) /* Assignment of value for DAY in the RTC_MODE2_TIMESTAMP register */ 1477 #define RTC_MODE2_TIMESTAMP_MONTH_Pos _UINT32_(22) /* (RTC_MODE2_TIMESTAMP) Month Timestamp Value Position */ 1478 #define RTC_MODE2_TIMESTAMP_MONTH_Msk (_UINT32_(0xF) << RTC_MODE2_TIMESTAMP_MONTH_Pos) /* (RTC_MODE2_TIMESTAMP) Month Timestamp Value Mask */ 1479 #define RTC_MODE2_TIMESTAMP_MONTH(value) (RTC_MODE2_TIMESTAMP_MONTH_Msk & (_UINT32_(value) << RTC_MODE2_TIMESTAMP_MONTH_Pos)) /* Assignment of value for MONTH in the RTC_MODE2_TIMESTAMP register */ 1480 #define RTC_MODE2_TIMESTAMP_YEAR_Pos _UINT32_(26) /* (RTC_MODE2_TIMESTAMP) Year Timestamp Value Position */ 1481 #define RTC_MODE2_TIMESTAMP_YEAR_Msk (_UINT32_(0x3F) << RTC_MODE2_TIMESTAMP_YEAR_Pos) /* (RTC_MODE2_TIMESTAMP) Year Timestamp Value Mask */ 1482 #define RTC_MODE2_TIMESTAMP_YEAR(value) (RTC_MODE2_TIMESTAMP_YEAR_Msk & (_UINT32_(value) << RTC_MODE2_TIMESTAMP_YEAR_Pos)) /* Assignment of value for YEAR in the RTC_MODE2_TIMESTAMP register */ 1483 #define RTC_MODE2_TIMESTAMP_Msk _UINT32_(0xFFFFFFFF) /* (RTC_MODE2_TIMESTAMP) Register Mask */ 1484 1485 1486 /* -------- RTC_TAMPID : (RTC Offset: 0x68) (R/W 32) Tamper ID -------- */ 1487 #define RTC_TAMPID_RESETVALUE _UINT32_(0x00) /* (RTC_TAMPID) Tamper ID Reset Value */ 1488 1489 #define RTC_TAMPID_TAMPID0_Pos _UINT32_(0) /* (RTC_TAMPID) Tamper Input 0 Detected Position */ 1490 #define RTC_TAMPID_TAMPID0_Msk (_UINT32_(0x1) << RTC_TAMPID_TAMPID0_Pos) /* (RTC_TAMPID) Tamper Input 0 Detected Mask */ 1491 #define RTC_TAMPID_TAMPID0(value) (RTC_TAMPID_TAMPID0_Msk & (_UINT32_(value) << RTC_TAMPID_TAMPID0_Pos)) /* Assignment of value for TAMPID0 in the RTC_TAMPID register */ 1492 #define RTC_TAMPID_TAMPID1_Pos _UINT32_(1) /* (RTC_TAMPID) Tamper Input 1 Detected Position */ 1493 #define RTC_TAMPID_TAMPID1_Msk (_UINT32_(0x1) << RTC_TAMPID_TAMPID1_Pos) /* (RTC_TAMPID) Tamper Input 1 Detected Mask */ 1494 #define RTC_TAMPID_TAMPID1(value) (RTC_TAMPID_TAMPID1_Msk & (_UINT32_(value) << RTC_TAMPID_TAMPID1_Pos)) /* Assignment of value for TAMPID1 in the RTC_TAMPID register */ 1495 #define RTC_TAMPID_TAMPID2_Pos _UINT32_(2) /* (RTC_TAMPID) Tamper Input 2 Detected Position */ 1496 #define RTC_TAMPID_TAMPID2_Msk (_UINT32_(0x1) << RTC_TAMPID_TAMPID2_Pos) /* (RTC_TAMPID) Tamper Input 2 Detected Mask */ 1497 #define RTC_TAMPID_TAMPID2(value) (RTC_TAMPID_TAMPID2_Msk & (_UINT32_(value) << RTC_TAMPID_TAMPID2_Pos)) /* Assignment of value for TAMPID2 in the RTC_TAMPID register */ 1498 #define RTC_TAMPID_TAMPID3_Pos _UINT32_(3) /* (RTC_TAMPID) Tamper Input 3 Detected Position */ 1499 #define RTC_TAMPID_TAMPID3_Msk (_UINT32_(0x1) << RTC_TAMPID_TAMPID3_Pos) /* (RTC_TAMPID) Tamper Input 3 Detected Mask */ 1500 #define RTC_TAMPID_TAMPID3(value) (RTC_TAMPID_TAMPID3_Msk & (_UINT32_(value) << RTC_TAMPID_TAMPID3_Pos)) /* Assignment of value for TAMPID3 in the RTC_TAMPID register */ 1501 #define RTC_TAMPID_TAMPID4_Pos _UINT32_(4) /* (RTC_TAMPID) Tamper Input 4 Detected Position */ 1502 #define RTC_TAMPID_TAMPID4_Msk (_UINT32_(0x1) << RTC_TAMPID_TAMPID4_Pos) /* (RTC_TAMPID) Tamper Input 4 Detected Mask */ 1503 #define RTC_TAMPID_TAMPID4(value) (RTC_TAMPID_TAMPID4_Msk & (_UINT32_(value) << RTC_TAMPID_TAMPID4_Pos)) /* Assignment of value for TAMPID4 in the RTC_TAMPID register */ 1504 #define RTC_TAMPID_TAMPEVT_Pos _UINT32_(31) /* (RTC_TAMPID) Tamper Event Detected Position */ 1505 #define RTC_TAMPID_TAMPEVT_Msk (_UINT32_(0x1) << RTC_TAMPID_TAMPEVT_Pos) /* (RTC_TAMPID) Tamper Event Detected Mask */ 1506 #define RTC_TAMPID_TAMPEVT(value) (RTC_TAMPID_TAMPEVT_Msk & (_UINT32_(value) << RTC_TAMPID_TAMPEVT_Pos)) /* Assignment of value for TAMPEVT in the RTC_TAMPID register */ 1507 #define RTC_TAMPID_Msk _UINT32_(0x8000001F) /* (RTC_TAMPID) Register Mask */ 1508 1509 #define RTC_TAMPID_TAMPID_Pos _UINT32_(0) /* (RTC_TAMPID Position) Tamper Input x Detected */ 1510 #define RTC_TAMPID_TAMPID_Msk (_UINT32_(0x1F) << RTC_TAMPID_TAMPID_Pos) /* (RTC_TAMPID Mask) TAMPID */ 1511 #define RTC_TAMPID_TAMPID(value) (RTC_TAMPID_TAMPID_Msk & (_UINT32_(value) << RTC_TAMPID_TAMPID_Pos)) 1512 1513 /* -------- RTC_BKUP : (RTC Offset: 0x80) (R/W 32) Backup -------- */ 1514 #define RTC_BKUP_RESETVALUE _UINT32_(0x00) /* (RTC_BKUP) Backup Reset Value */ 1515 1516 #define RTC_BKUP_BKUP_Pos _UINT32_(0) /* (RTC_BKUP) Backup Position */ 1517 #define RTC_BKUP_BKUP_Msk (_UINT32_(0xFFFFFFFF) << RTC_BKUP_BKUP_Pos) /* (RTC_BKUP) Backup Mask */ 1518 #define RTC_BKUP_BKUP(value) (RTC_BKUP_BKUP_Msk & (_UINT32_(value) << RTC_BKUP_BKUP_Pos)) /* Assignment of value for BKUP in the RTC_BKUP register */ 1519 #define RTC_BKUP_Msk _UINT32_(0xFFFFFFFF) /* (RTC_BKUP) Register Mask */ 1520 1521 1522 /* RTC register offsets definitions */ 1523 #define RTC_MODE0_CTRLA_REG_OFST _UINT32_(0x00) /* (RTC_MODE0_CTRLA) MODE0 Control A Offset */ 1524 #define RTC_MODE1_CTRLA_REG_OFST _UINT32_(0x00) /* (RTC_MODE1_CTRLA) MODE1 Control A Offset */ 1525 #define RTC_MODE2_CTRLA_REG_OFST _UINT32_(0x00) /* (RTC_MODE2_CTRLA) MODE2 Control A Offset */ 1526 #define RTC_MODE0_CTRLB_REG_OFST _UINT32_(0x02) /* (RTC_MODE0_CTRLB) MODE0 Control B Offset */ 1527 #define RTC_MODE1_CTRLB_REG_OFST _UINT32_(0x02) /* (RTC_MODE1_CTRLB) MODE1 Control B Offset */ 1528 #define RTC_MODE2_CTRLB_REG_OFST _UINT32_(0x02) /* (RTC_MODE2_CTRLB) MODE2 Control B Offset */ 1529 #define RTC_MODE0_EVCTRL_REG_OFST _UINT32_(0x04) /* (RTC_MODE0_EVCTRL) MODE0 Event Control Offset */ 1530 #define RTC_MODE1_EVCTRL_REG_OFST _UINT32_(0x04) /* (RTC_MODE1_EVCTRL) MODE1 Event Control Offset */ 1531 #define RTC_MODE2_EVCTRL_REG_OFST _UINT32_(0x04) /* (RTC_MODE2_EVCTRL) MODE2 Event Control Offset */ 1532 #define RTC_MODE0_INTENCLR_REG_OFST _UINT32_(0x08) /* (RTC_MODE0_INTENCLR) MODE0 Interrupt Enable Clear Offset */ 1533 #define RTC_MODE1_INTENCLR_REG_OFST _UINT32_(0x08) /* (RTC_MODE1_INTENCLR) MODE1 Interrupt Enable Clear Offset */ 1534 #define RTC_MODE2_INTENCLR_REG_OFST _UINT32_(0x08) /* (RTC_MODE2_INTENCLR) MODE2 Interrupt Enable Clear Offset */ 1535 #define RTC_MODE0_INTENSET_REG_OFST _UINT32_(0x0A) /* (RTC_MODE0_INTENSET) MODE0 Interrupt Enable Set Offset */ 1536 #define RTC_MODE1_INTENSET_REG_OFST _UINT32_(0x0A) /* (RTC_MODE1_INTENSET) MODE1 Interrupt Enable Set Offset */ 1537 #define RTC_MODE2_INTENSET_REG_OFST _UINT32_(0x0A) /* (RTC_MODE2_INTENSET) MODE2 Interrupt Enable Set Offset */ 1538 #define RTC_MODE0_INTFLAG_REG_OFST _UINT32_(0x0C) /* (RTC_MODE0_INTFLAG) MODE0 Interrupt Flag Status and Clear Offset */ 1539 #define RTC_MODE1_INTFLAG_REG_OFST _UINT32_(0x0C) /* (RTC_MODE1_INTFLAG) MODE1 Interrupt Flag Status and Clear Offset */ 1540 #define RTC_MODE2_INTFLAG_REG_OFST _UINT32_(0x0C) /* (RTC_MODE2_INTFLAG) MODE2 Interrupt Flag Status and Clear Offset */ 1541 #define RTC_DBGCTRL_REG_OFST _UINT32_(0x0E) /* (RTC_DBGCTRL) Debug Control Offset */ 1542 #define RTC_MODE0_SYNCBUSY_REG_OFST _UINT32_(0x10) /* (RTC_MODE0_SYNCBUSY) MODE0 Synchronization Busy Status Offset */ 1543 #define RTC_MODE1_SYNCBUSY_REG_OFST _UINT32_(0x10) /* (RTC_MODE1_SYNCBUSY) MODE1 Synchronization Busy Status Offset */ 1544 #define RTC_MODE2_SYNCBUSY_REG_OFST _UINT32_(0x10) /* (RTC_MODE2_SYNCBUSY) MODE2 Synchronization Busy Status Offset */ 1545 #define RTC_FREQCORR_REG_OFST _UINT32_(0x14) /* (RTC_FREQCORR) Frequency Correction Offset */ 1546 #define RTC_MODE0_COUNT_REG_OFST _UINT32_(0x18) /* (RTC_MODE0_COUNT) MODE0 Counter Value Offset */ 1547 #define RTC_MODE1_COUNT_REG_OFST _UINT32_(0x18) /* (RTC_MODE1_COUNT) MODE1 Counter Value Offset */ 1548 #define RTC_MODE2_CLOCK_REG_OFST _UINT32_(0x18) /* (RTC_MODE2_CLOCK) MODE2 Clock Value Offset */ 1549 #define RTC_MODE1_PER_REG_OFST _UINT32_(0x1C) /* (RTC_MODE1_PER) MODE1 Counter Period Offset */ 1550 #define RTC_MODE0_COMP_REG_OFST _UINT32_(0x20) /* (RTC_MODE0_COMP) MODE0 Compare n Value Offset */ 1551 #define RTC_MODE0_COMP0_REG_OFST _UINT32_(0x20) /* (RTC_MODE0_COMP0) MODE0 Compare n Value Offset */ 1552 #define RTC_MODE0_COMP1_REG_OFST _UINT32_(0x24) /* (RTC_MODE0_COMP1) MODE0 Compare n Value Offset */ 1553 #define RTC_MODE1_COMP_REG_OFST _UINT32_(0x20) /* (RTC_MODE1_COMP) MODE1 Compare n Value Offset */ 1554 #define RTC_MODE1_COMP0_REG_OFST _UINT32_(0x20) /* (RTC_MODE1_COMP0) MODE1 Compare n Value Offset */ 1555 #define RTC_MODE1_COMP1_REG_OFST _UINT32_(0x22) /* (RTC_MODE1_COMP1) MODE1 Compare n Value Offset */ 1556 #define RTC_MODE1_COMP2_REG_OFST _UINT32_(0x24) /* (RTC_MODE1_COMP2) MODE1 Compare n Value Offset */ 1557 #define RTC_MODE1_COMP3_REG_OFST _UINT32_(0x26) /* (RTC_MODE1_COMP3) MODE1 Compare n Value Offset */ 1558 #define RTC_MODE2_ALARM0_REG_OFST _UINT32_(0x20) /* (RTC_MODE2_ALARM0) MODE2_ALARM Alarm n Value Offset */ 1559 #define RTC_MODE2_MASK0_REG_OFST _UINT32_(0x24) /* (RTC_MODE2_MASK0) MODE2_ALARM Alarm n Mask Offset */ 1560 #define RTC_MODE2_ALARM1_REG_OFST _UINT32_(0x28) /* (RTC_MODE2_ALARM1) MODE2_ALARM Alarm n Value Offset */ 1561 #define RTC_MODE2_MASK1_REG_OFST _UINT32_(0x2C) /* (RTC_MODE2_MASK1) MODE2_ALARM Alarm n Mask Offset */ 1562 #define RTC_GP_REG_OFST _UINT32_(0x40) /* (RTC_GP) General Purpose Offset */ 1563 #define RTC_GP0_REG_OFST _UINT32_(0x40) /* (RTC_GP0) General Purpose Offset */ 1564 #define RTC_GP1_REG_OFST _UINT32_(0x44) /* (RTC_GP1) General Purpose Offset */ 1565 #define RTC_GP2_REG_OFST _UINT32_(0x48) /* (RTC_GP2) General Purpose Offset */ 1566 #define RTC_GP3_REG_OFST _UINT32_(0x4C) /* (RTC_GP3) General Purpose Offset */ 1567 #define RTC_TAMPCTRL_REG_OFST _UINT32_(0x60) /* (RTC_TAMPCTRL) Tamper Control Offset */ 1568 #define RTC_MODE0_TIMESTAMP_REG_OFST _UINT32_(0x64) /* (RTC_MODE0_TIMESTAMP) MODE0 Timestamp Offset */ 1569 #define RTC_MODE1_TIMESTAMP_REG_OFST _UINT32_(0x64) /* (RTC_MODE1_TIMESTAMP) MODE1 Timestamp Offset */ 1570 #define RTC_MODE2_TIMESTAMP_REG_OFST _UINT32_(0x64) /* (RTC_MODE2_TIMESTAMP) MODE2 Timestamp Offset */ 1571 #define RTC_TAMPID_REG_OFST _UINT32_(0x68) /* (RTC_TAMPID) Tamper ID Offset */ 1572 #define RTC_BKUP_REG_OFST _UINT32_(0x80) /* (RTC_BKUP) Backup Offset */ 1573 #define RTC_BKUP0_REG_OFST _UINT32_(0x80) /* (RTC_BKUP0) Backup Offset */ 1574 #define RTC_BKUP1_REG_OFST _UINT32_(0x84) /* (RTC_BKUP1) Backup Offset */ 1575 #define RTC_BKUP2_REG_OFST _UINT32_(0x88) /* (RTC_BKUP2) Backup Offset */ 1576 #define RTC_BKUP3_REG_OFST _UINT32_(0x8C) /* (RTC_BKUP3) Backup Offset */ 1577 #define RTC_BKUP4_REG_OFST _UINT32_(0x90) /* (RTC_BKUP4) Backup Offset */ 1578 #define RTC_BKUP5_REG_OFST _UINT32_(0x94) /* (RTC_BKUP5) Backup Offset */ 1579 #define RTC_BKUP6_REG_OFST _UINT32_(0x98) /* (RTC_BKUP6) Backup Offset */ 1580 #define RTC_BKUP7_REG_OFST _UINT32_(0x9C) /* (RTC_BKUP7) Backup Offset */ 1581 1582 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1583 /* RTC register API structure */ 1584 typedef struct 1585 { /* Real-Time Counter */ 1586 __IO uint16_t RTC_CTRLA; /* Offset: 0x00 (R/W 16) MODE0 Control A */ 1587 __IO uint16_t RTC_CTRLB; /* Offset: 0x02 (R/W 16) MODE0 Control B */ 1588 __IO uint32_t RTC_EVCTRL; /* Offset: 0x04 (R/W 32) MODE0 Event Control */ 1589 __IO uint16_t RTC_INTENCLR; /* Offset: 0x08 (R/W 16) MODE0 Interrupt Enable Clear */ 1590 __IO uint16_t RTC_INTENSET; /* Offset: 0x0A (R/W 16) MODE0 Interrupt Enable Set */ 1591 __IO uint16_t RTC_INTFLAG; /* Offset: 0x0C (R/W 16) MODE0 Interrupt Flag Status and Clear */ 1592 __IO uint8_t RTC_DBGCTRL; /* Offset: 0x0E (R/W 8) Debug Control */ 1593 __I uint8_t Reserved1[0x01]; 1594 __I uint32_t RTC_SYNCBUSY; /* Offset: 0x10 (R/ 32) MODE0 Synchronization Busy Status */ 1595 __IO uint8_t RTC_FREQCORR; /* Offset: 0x14 (R/W 8) Frequency Correction */ 1596 __I uint8_t Reserved2[0x03]; 1597 __IO uint32_t RTC_COUNT; /* Offset: 0x18 (R/W 32) MODE0 Counter Value */ 1598 __I uint8_t Reserved3[0x04]; 1599 __IO uint32_t RTC_COMP[2]; /* Offset: 0x20 (R/W 32) MODE0 Compare n Value */ 1600 __I uint8_t Reserved4[0x18]; 1601 __IO uint32_t RTC_GP[4]; /* Offset: 0x40 (R/W 32) General Purpose */ 1602 __I uint8_t Reserved5[0x10]; 1603 __IO uint32_t RTC_TAMPCTRL; /* Offset: 0x60 (R/W 32) Tamper Control */ 1604 __I uint32_t RTC_TIMESTAMP; /* Offset: 0x64 (R/ 32) MODE0 Timestamp */ 1605 __IO uint32_t RTC_TAMPID; /* Offset: 0x68 (R/W 32) Tamper ID */ 1606 __I uint8_t Reserved6[0x14]; 1607 __IO uint32_t RTC_BKUP[8]; /* Offset: 0x80 (R/W 32) Backup */ 1608 } rtc_mode0_registers_t; 1609 1610 /* RTC register API structure */ 1611 typedef struct 1612 { /* Real-Time Counter */ 1613 __IO uint16_t RTC_CTRLA; /* Offset: 0x00 (R/W 16) MODE1 Control A */ 1614 __IO uint16_t RTC_CTRLB; /* Offset: 0x02 (R/W 16) MODE1 Control B */ 1615 __IO uint32_t RTC_EVCTRL; /* Offset: 0x04 (R/W 32) MODE1 Event Control */ 1616 __IO uint16_t RTC_INTENCLR; /* Offset: 0x08 (R/W 16) MODE1 Interrupt Enable Clear */ 1617 __IO uint16_t RTC_INTENSET; /* Offset: 0x0A (R/W 16) MODE1 Interrupt Enable Set */ 1618 __IO uint16_t RTC_INTFLAG; /* Offset: 0x0C (R/W 16) MODE1 Interrupt Flag Status and Clear */ 1619 __IO uint8_t RTC_DBGCTRL; /* Offset: 0x0E (R/W 8) Debug Control */ 1620 __I uint8_t Reserved1[0x01]; 1621 __I uint32_t RTC_SYNCBUSY; /* Offset: 0x10 (R/ 32) MODE1 Synchronization Busy Status */ 1622 __IO uint8_t RTC_FREQCORR; /* Offset: 0x14 (R/W 8) Frequency Correction */ 1623 __I uint8_t Reserved2[0x03]; 1624 __IO uint16_t RTC_COUNT; /* Offset: 0x18 (R/W 16) MODE1 Counter Value */ 1625 __I uint8_t Reserved3[0x02]; 1626 __IO uint16_t RTC_PER; /* Offset: 0x1C (R/W 16) MODE1 Counter Period */ 1627 __I uint8_t Reserved4[0x02]; 1628 __IO uint16_t RTC_COMP[4]; /* Offset: 0x20 (R/W 16) MODE1 Compare n Value */ 1629 __I uint8_t Reserved5[0x18]; 1630 __IO uint32_t RTC_GP[4]; /* Offset: 0x40 (R/W 32) General Purpose */ 1631 __I uint8_t Reserved6[0x10]; 1632 __IO uint32_t RTC_TAMPCTRL; /* Offset: 0x60 (R/W 32) Tamper Control */ 1633 __I uint32_t RTC_TIMESTAMP; /* Offset: 0x64 (R/ 32) MODE1 Timestamp */ 1634 __IO uint32_t RTC_TAMPID; /* Offset: 0x68 (R/W 32) Tamper ID */ 1635 __I uint8_t Reserved7[0x14]; 1636 __IO uint32_t RTC_BKUP[8]; /* Offset: 0x80 (R/W 32) Backup */ 1637 } rtc_mode1_registers_t; 1638 1639 /* RTC register API structure */ 1640 typedef struct 1641 { /* Real-Time Counter */ 1642 __IO uint16_t RTC_CTRLA; /* Offset: 0x00 (R/W 16) MODE2 Control A */ 1643 __IO uint16_t RTC_CTRLB; /* Offset: 0x02 (R/W 16) MODE2 Control B */ 1644 __IO uint32_t RTC_EVCTRL; /* Offset: 0x04 (R/W 32) MODE2 Event Control */ 1645 __IO uint16_t RTC_INTENCLR; /* Offset: 0x08 (R/W 16) MODE2 Interrupt Enable Clear */ 1646 __IO uint16_t RTC_INTENSET; /* Offset: 0x0A (R/W 16) MODE2 Interrupt Enable Set */ 1647 __IO uint16_t RTC_INTFLAG; /* Offset: 0x0C (R/W 16) MODE2 Interrupt Flag Status and Clear */ 1648 __IO uint8_t RTC_DBGCTRL; /* Offset: 0x0E (R/W 8) Debug Control */ 1649 __I uint8_t Reserved1[0x01]; 1650 __I uint32_t RTC_SYNCBUSY; /* Offset: 0x10 (R/ 32) MODE2 Synchronization Busy Status */ 1651 __IO uint8_t RTC_FREQCORR; /* Offset: 0x14 (R/W 8) Frequency Correction */ 1652 __I uint8_t Reserved2[0x03]; 1653 __IO uint32_t RTC_CLOCK; /* Offset: 0x18 (R/W 32) MODE2 Clock Value */ 1654 __I uint8_t Reserved3[0x04]; 1655 __IO uint32_t RTC_ALARM0; /* Offset: 0x20 (R/W 32) MODE2_ALARM Alarm n Value */ 1656 __IO uint8_t RTC_MASK0; /* Offset: 0x24 (R/W 8) MODE2_ALARM Alarm n Mask */ 1657 __I uint8_t Reserved4[0x03]; 1658 __IO uint32_t RTC_ALARM1; /* Offset: 0x28 (R/W 32) MODE2_ALARM Alarm n Value */ 1659 __IO uint8_t RTC_MASK1; /* Offset: 0x2C (R/W 8) MODE2_ALARM Alarm n Mask */ 1660 __I uint8_t Reserved5[0x13]; 1661 __IO uint32_t RTC_GP[4]; /* Offset: 0x40 (R/W 32) General Purpose */ 1662 __I uint8_t Reserved6[0x10]; 1663 __IO uint32_t RTC_TAMPCTRL; /* Offset: 0x60 (R/W 32) Tamper Control */ 1664 __I uint32_t RTC_TIMESTAMP; /* Offset: 0x64 (R/ 32) MODE2 Timestamp */ 1665 __IO uint32_t RTC_TAMPID; /* Offset: 0x68 (R/W 32) Tamper ID */ 1666 __I uint8_t Reserved7[0x14]; 1667 __IO uint32_t RTC_BKUP[8]; /* Offset: 0x80 (R/W 32) Backup */ 1668 } rtc_mode2_registers_t; 1669 1670 /* RTC hardware registers */ 1671 typedef union 1672 { /* Real-Time Counter */ 1673 rtc_mode0_registers_t MODE0; /* 32-bit Counter with Single 32-bit Compare */ 1674 rtc_mode1_registers_t MODE1; /* 16-bit Counter with Two 16-bit Compares */ 1675 rtc_mode2_registers_t MODE2; /* Clock/Calendar with Alarm */ 1676 } rtc_registers_t; 1677 1678 1679 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1680 #endif /* _PIC32CXSG41_RTC_COMPONENT_H_ */ 1681
