1 /* 2 * Component description for PORT 3 * 4 * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 */ 19 20 /* file generated from device description file (ATDF) version 2023-03-17T09:48:34Z */ 21 #ifndef _PIC32CXSG41_PORT_COMPONENT_H_ 22 #define _PIC32CXSG41_PORT_COMPONENT_H_ 23 24 /* ************************************************************************** */ 25 /* SOFTWARE API DEFINITION FOR PORT */ 26 /* ************************************************************************** */ 27 28 /* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) Data Direction -------- */ 29 #define PORT_DIR_RESETVALUE _UINT32_(0x00) /* (PORT_DIR) Data Direction Reset Value */ 30 31 #define PORT_DIR_DIR_Pos _UINT32_(0) /* (PORT_DIR) Port Data Direction Position */ 32 #define PORT_DIR_DIR_Msk (_UINT32_(0xFFFFFFFF) << PORT_DIR_DIR_Pos) /* (PORT_DIR) Port Data Direction Mask */ 33 #define PORT_DIR_DIR(value) (PORT_DIR_DIR_Msk & (_UINT32_(value) << PORT_DIR_DIR_Pos)) /* Assignment of value for DIR in the PORT_DIR register */ 34 #define PORT_DIR_Msk _UINT32_(0xFFFFFFFF) /* (PORT_DIR) Register Mask */ 35 36 37 /* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) Data Direction Clear -------- */ 38 #define PORT_DIRCLR_RESETVALUE _UINT32_(0x00) /* (PORT_DIRCLR) Data Direction Clear Reset Value */ 39 40 #define PORT_DIRCLR_DIRCLR_Pos _UINT32_(0) /* (PORT_DIRCLR) Port Data Direction Clear Position */ 41 #define PORT_DIRCLR_DIRCLR_Msk (_UINT32_(0xFFFFFFFF) << PORT_DIRCLR_DIRCLR_Pos) /* (PORT_DIRCLR) Port Data Direction Clear Mask */ 42 #define PORT_DIRCLR_DIRCLR(value) (PORT_DIRCLR_DIRCLR_Msk & (_UINT32_(value) << PORT_DIRCLR_DIRCLR_Pos)) /* Assignment of value for DIRCLR in the PORT_DIRCLR register */ 43 #define PORT_DIRCLR_Msk _UINT32_(0xFFFFFFFF) /* (PORT_DIRCLR) Register Mask */ 44 45 46 /* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) Data Direction Set -------- */ 47 #define PORT_DIRSET_RESETVALUE _UINT32_(0x00) /* (PORT_DIRSET) Data Direction Set Reset Value */ 48 49 #define PORT_DIRSET_DIRSET_Pos _UINT32_(0) /* (PORT_DIRSET) Port Data Direction Set Position */ 50 #define PORT_DIRSET_DIRSET_Msk (_UINT32_(0xFFFFFFFF) << PORT_DIRSET_DIRSET_Pos) /* (PORT_DIRSET) Port Data Direction Set Mask */ 51 #define PORT_DIRSET_DIRSET(value) (PORT_DIRSET_DIRSET_Msk & (_UINT32_(value) << PORT_DIRSET_DIRSET_Pos)) /* Assignment of value for DIRSET in the PORT_DIRSET register */ 52 #define PORT_DIRSET_Msk _UINT32_(0xFFFFFFFF) /* (PORT_DIRSET) Register Mask */ 53 54 55 /* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) Data Direction Toggle -------- */ 56 #define PORT_DIRTGL_RESETVALUE _UINT32_(0x00) /* (PORT_DIRTGL) Data Direction Toggle Reset Value */ 57 58 #define PORT_DIRTGL_DIRTGL_Pos _UINT32_(0) /* (PORT_DIRTGL) Port Data Direction Toggle Position */ 59 #define PORT_DIRTGL_DIRTGL_Msk (_UINT32_(0xFFFFFFFF) << PORT_DIRTGL_DIRTGL_Pos) /* (PORT_DIRTGL) Port Data Direction Toggle Mask */ 60 #define PORT_DIRTGL_DIRTGL(value) (PORT_DIRTGL_DIRTGL_Msk & (_UINT32_(value) << PORT_DIRTGL_DIRTGL_Pos)) /* Assignment of value for DIRTGL in the PORT_DIRTGL register */ 61 #define PORT_DIRTGL_Msk _UINT32_(0xFFFFFFFF) /* (PORT_DIRTGL) Register Mask */ 62 63 64 /* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) Data Output Value -------- */ 65 #define PORT_OUT_RESETVALUE _UINT32_(0x00) /* (PORT_OUT) Data Output Value Reset Value */ 66 67 #define PORT_OUT_OUT_Pos _UINT32_(0) /* (PORT_OUT) PORT Data Output Value Position */ 68 #define PORT_OUT_OUT_Msk (_UINT32_(0xFFFFFFFF) << PORT_OUT_OUT_Pos) /* (PORT_OUT) PORT Data Output Value Mask */ 69 #define PORT_OUT_OUT(value) (PORT_OUT_OUT_Msk & (_UINT32_(value) << PORT_OUT_OUT_Pos)) /* Assignment of value for OUT in the PORT_OUT register */ 70 #define PORT_OUT_Msk _UINT32_(0xFFFFFFFF) /* (PORT_OUT) Register Mask */ 71 72 73 /* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) Data Output Value Clear -------- */ 74 #define PORT_OUTCLR_RESETVALUE _UINT32_(0x00) /* (PORT_OUTCLR) Data Output Value Clear Reset Value */ 75 76 #define PORT_OUTCLR_OUTCLR_Pos _UINT32_(0) /* (PORT_OUTCLR) PORT Data Output Value Clear Position */ 77 #define PORT_OUTCLR_OUTCLR_Msk (_UINT32_(0xFFFFFFFF) << PORT_OUTCLR_OUTCLR_Pos) /* (PORT_OUTCLR) PORT Data Output Value Clear Mask */ 78 #define PORT_OUTCLR_OUTCLR(value) (PORT_OUTCLR_OUTCLR_Msk & (_UINT32_(value) << PORT_OUTCLR_OUTCLR_Pos)) /* Assignment of value for OUTCLR in the PORT_OUTCLR register */ 79 #define PORT_OUTCLR_Msk _UINT32_(0xFFFFFFFF) /* (PORT_OUTCLR) Register Mask */ 80 81 82 /* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) Data Output Value Set -------- */ 83 #define PORT_OUTSET_RESETVALUE _UINT32_(0x00) /* (PORT_OUTSET) Data Output Value Set Reset Value */ 84 85 #define PORT_OUTSET_OUTSET_Pos _UINT32_(0) /* (PORT_OUTSET) PORT Data Output Value Set Position */ 86 #define PORT_OUTSET_OUTSET_Msk (_UINT32_(0xFFFFFFFF) << PORT_OUTSET_OUTSET_Pos) /* (PORT_OUTSET) PORT Data Output Value Set Mask */ 87 #define PORT_OUTSET_OUTSET(value) (PORT_OUTSET_OUTSET_Msk & (_UINT32_(value) << PORT_OUTSET_OUTSET_Pos)) /* Assignment of value for OUTSET in the PORT_OUTSET register */ 88 #define PORT_OUTSET_Msk _UINT32_(0xFFFFFFFF) /* (PORT_OUTSET) Register Mask */ 89 90 91 /* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) Data Output Value Toggle -------- */ 92 #define PORT_OUTTGL_RESETVALUE _UINT32_(0x00) /* (PORT_OUTTGL) Data Output Value Toggle Reset Value */ 93 94 #define PORT_OUTTGL_OUTTGL_Pos _UINT32_(0) /* (PORT_OUTTGL) PORT Data Output Value Toggle Position */ 95 #define PORT_OUTTGL_OUTTGL_Msk (_UINT32_(0xFFFFFFFF) << PORT_OUTTGL_OUTTGL_Pos) /* (PORT_OUTTGL) PORT Data Output Value Toggle Mask */ 96 #define PORT_OUTTGL_OUTTGL(value) (PORT_OUTTGL_OUTTGL_Msk & (_UINT32_(value) << PORT_OUTTGL_OUTTGL_Pos)) /* Assignment of value for OUTTGL in the PORT_OUTTGL register */ 97 #define PORT_OUTTGL_Msk _UINT32_(0xFFFFFFFF) /* (PORT_OUTTGL) Register Mask */ 98 99 100 /* -------- PORT_IN : (PORT Offset: 0x20) ( R/ 32) Data Input Value -------- */ 101 #define PORT_IN_RESETVALUE _UINT32_(0x00) /* (PORT_IN) Data Input Value Reset Value */ 102 103 #define PORT_IN_IN_Pos _UINT32_(0) /* (PORT_IN) PORT Data Input Value Position */ 104 #define PORT_IN_IN_Msk (_UINT32_(0xFFFFFFFF) << PORT_IN_IN_Pos) /* (PORT_IN) PORT Data Input Value Mask */ 105 #define PORT_IN_IN(value) (PORT_IN_IN_Msk & (_UINT32_(value) << PORT_IN_IN_Pos)) /* Assignment of value for IN in the PORT_IN register */ 106 #define PORT_IN_Msk _UINT32_(0xFFFFFFFF) /* (PORT_IN) Register Mask */ 107 108 109 /* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) Control -------- */ 110 #define PORT_CTRL_RESETVALUE _UINT32_(0x00) /* (PORT_CTRL) Control Reset Value */ 111 112 #define PORT_CTRL_SAMPLING_Pos _UINT32_(0) /* (PORT_CTRL) Input Sampling Mode Position */ 113 #define PORT_CTRL_SAMPLING_Msk (_UINT32_(0xFFFFFFFF) << PORT_CTRL_SAMPLING_Pos) /* (PORT_CTRL) Input Sampling Mode Mask */ 114 #define PORT_CTRL_SAMPLING(value) (PORT_CTRL_SAMPLING_Msk & (_UINT32_(value) << PORT_CTRL_SAMPLING_Pos)) /* Assignment of value for SAMPLING in the PORT_CTRL register */ 115 #define PORT_CTRL_Msk _UINT32_(0xFFFFFFFF) /* (PORT_CTRL) Register Mask */ 116 117 118 /* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) Write Configuration -------- */ 119 #define PORT_WRCONFIG_RESETVALUE _UINT32_(0x00) /* (PORT_WRCONFIG) Write Configuration Reset Value */ 120 121 #define PORT_WRCONFIG_PINMASK_Pos _UINT32_(0) /* (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration Position */ 122 #define PORT_WRCONFIG_PINMASK_Msk (_UINT32_(0xFFFF) << PORT_WRCONFIG_PINMASK_Pos) /* (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration Mask */ 123 #define PORT_WRCONFIG_PINMASK(value) (PORT_WRCONFIG_PINMASK_Msk & (_UINT32_(value) << PORT_WRCONFIG_PINMASK_Pos)) /* Assignment of value for PINMASK in the PORT_WRCONFIG register */ 124 #define PORT_WRCONFIG_PMUXEN_Pos _UINT32_(16) /* (PORT_WRCONFIG) Peripheral Multiplexer Enable Position */ 125 #define PORT_WRCONFIG_PMUXEN_Msk (_UINT32_(0x1) << PORT_WRCONFIG_PMUXEN_Pos) /* (PORT_WRCONFIG) Peripheral Multiplexer Enable Mask */ 126 #define PORT_WRCONFIG_PMUXEN(value) (PORT_WRCONFIG_PMUXEN_Msk & (_UINT32_(value) << PORT_WRCONFIG_PMUXEN_Pos)) /* Assignment of value for PMUXEN in the PORT_WRCONFIG register */ 127 #define PORT_WRCONFIG_INEN_Pos _UINT32_(17) /* (PORT_WRCONFIG) Input Enable Position */ 128 #define PORT_WRCONFIG_INEN_Msk (_UINT32_(0x1) << PORT_WRCONFIG_INEN_Pos) /* (PORT_WRCONFIG) Input Enable Mask */ 129 #define PORT_WRCONFIG_INEN(value) (PORT_WRCONFIG_INEN_Msk & (_UINT32_(value) << PORT_WRCONFIG_INEN_Pos)) /* Assignment of value for INEN in the PORT_WRCONFIG register */ 130 #define PORT_WRCONFIG_PULLEN_Pos _UINT32_(18) /* (PORT_WRCONFIG) Pull Enable Position */ 131 #define PORT_WRCONFIG_PULLEN_Msk (_UINT32_(0x1) << PORT_WRCONFIG_PULLEN_Pos) /* (PORT_WRCONFIG) Pull Enable Mask */ 132 #define PORT_WRCONFIG_PULLEN(value) (PORT_WRCONFIG_PULLEN_Msk & (_UINT32_(value) << PORT_WRCONFIG_PULLEN_Pos)) /* Assignment of value for PULLEN in the PORT_WRCONFIG register */ 133 #define PORT_WRCONFIG_DRVSTR_Pos _UINT32_(22) /* (PORT_WRCONFIG) Output Driver Strength Selection Position */ 134 #define PORT_WRCONFIG_DRVSTR_Msk (_UINT32_(0x1) << PORT_WRCONFIG_DRVSTR_Pos) /* (PORT_WRCONFIG) Output Driver Strength Selection Mask */ 135 #define PORT_WRCONFIG_DRVSTR(value) (PORT_WRCONFIG_DRVSTR_Msk & (_UINT32_(value) << PORT_WRCONFIG_DRVSTR_Pos)) /* Assignment of value for DRVSTR in the PORT_WRCONFIG register */ 136 #define PORT_WRCONFIG_PMUX_Pos _UINT32_(24) /* (PORT_WRCONFIG) Peripheral Multiplexing Position */ 137 #define PORT_WRCONFIG_PMUX_Msk (_UINT32_(0xF) << PORT_WRCONFIG_PMUX_Pos) /* (PORT_WRCONFIG) Peripheral Multiplexing Mask */ 138 #define PORT_WRCONFIG_PMUX(value) (PORT_WRCONFIG_PMUX_Msk & (_UINT32_(value) << PORT_WRCONFIG_PMUX_Pos)) /* Assignment of value for PMUX in the PORT_WRCONFIG register */ 139 #define PORT_WRCONFIG_WRPMUX_Pos _UINT32_(28) /* (PORT_WRCONFIG) Write PMUX Position */ 140 #define PORT_WRCONFIG_WRPMUX_Msk (_UINT32_(0x1) << PORT_WRCONFIG_WRPMUX_Pos) /* (PORT_WRCONFIG) Write PMUX Mask */ 141 #define PORT_WRCONFIG_WRPMUX(value) (PORT_WRCONFIG_WRPMUX_Msk & (_UINT32_(value) << PORT_WRCONFIG_WRPMUX_Pos)) /* Assignment of value for WRPMUX in the PORT_WRCONFIG register */ 142 #define PORT_WRCONFIG_WRPINCFG_Pos _UINT32_(30) /* (PORT_WRCONFIG) Write PINCFG Position */ 143 #define PORT_WRCONFIG_WRPINCFG_Msk (_UINT32_(0x1) << PORT_WRCONFIG_WRPINCFG_Pos) /* (PORT_WRCONFIG) Write PINCFG Mask */ 144 #define PORT_WRCONFIG_WRPINCFG(value) (PORT_WRCONFIG_WRPINCFG_Msk & (_UINT32_(value) << PORT_WRCONFIG_WRPINCFG_Pos)) /* Assignment of value for WRPINCFG in the PORT_WRCONFIG register */ 145 #define PORT_WRCONFIG_HWSEL_Pos _UINT32_(31) /* (PORT_WRCONFIG) Half-Word Select Position */ 146 #define PORT_WRCONFIG_HWSEL_Msk (_UINT32_(0x1) << PORT_WRCONFIG_HWSEL_Pos) /* (PORT_WRCONFIG) Half-Word Select Mask */ 147 #define PORT_WRCONFIG_HWSEL(value) (PORT_WRCONFIG_HWSEL_Msk & (_UINT32_(value) << PORT_WRCONFIG_HWSEL_Pos)) /* Assignment of value for HWSEL in the PORT_WRCONFIG register */ 148 #define PORT_WRCONFIG_Msk _UINT32_(0xDF47FFFF) /* (PORT_WRCONFIG) Register Mask */ 149 150 151 /* -------- PORT_EVCTRL : (PORT Offset: 0x2C) (R/W 32) Event Input Control -------- */ 152 #define PORT_EVCTRL_RESETVALUE _UINT32_(0x00) /* (PORT_EVCTRL) Event Input Control Reset Value */ 153 154 #define PORT_EVCTRL_PID0_Pos _UINT32_(0) /* (PORT_EVCTRL) PORT Event Pin Identifier 0 Position */ 155 #define PORT_EVCTRL_PID0_Msk (_UINT32_(0x1F) << PORT_EVCTRL_PID0_Pos) /* (PORT_EVCTRL) PORT Event Pin Identifier 0 Mask */ 156 #define PORT_EVCTRL_PID0(value) (PORT_EVCTRL_PID0_Msk & (_UINT32_(value) << PORT_EVCTRL_PID0_Pos)) /* Assignment of value for PID0 in the PORT_EVCTRL register */ 157 #define PORT_EVCTRL_EVACT0_Pos _UINT32_(5) /* (PORT_EVCTRL) PORT Event Action 0 Position */ 158 #define PORT_EVCTRL_EVACT0_Msk (_UINT32_(0x3) << PORT_EVCTRL_EVACT0_Pos) /* (PORT_EVCTRL) PORT Event Action 0 Mask */ 159 #define PORT_EVCTRL_EVACT0(value) (PORT_EVCTRL_EVACT0_Msk & (_UINT32_(value) << PORT_EVCTRL_EVACT0_Pos)) /* Assignment of value for EVACT0 in the PORT_EVCTRL register */ 160 #define PORT_EVCTRL_EVACT0_OUT_Val _UINT32_(0x0) /* (PORT_EVCTRL) Event output to pin */ 161 #define PORT_EVCTRL_EVACT0_SET_Val _UINT32_(0x1) /* (PORT_EVCTRL) Set output register of pin on event */ 162 #define PORT_EVCTRL_EVACT0_CLR_Val _UINT32_(0x2) /* (PORT_EVCTRL) Clear output register of pin on event */ 163 #define PORT_EVCTRL_EVACT0_TGL_Val _UINT32_(0x3) /* (PORT_EVCTRL) Toggle output register of pin on event */ 164 #define PORT_EVCTRL_EVACT0_OUT (PORT_EVCTRL_EVACT0_OUT_Val << PORT_EVCTRL_EVACT0_Pos) /* (PORT_EVCTRL) Event output to pin Position */ 165 #define PORT_EVCTRL_EVACT0_SET (PORT_EVCTRL_EVACT0_SET_Val << PORT_EVCTRL_EVACT0_Pos) /* (PORT_EVCTRL) Set output register of pin on event Position */ 166 #define PORT_EVCTRL_EVACT0_CLR (PORT_EVCTRL_EVACT0_CLR_Val << PORT_EVCTRL_EVACT0_Pos) /* (PORT_EVCTRL) Clear output register of pin on event Position */ 167 #define PORT_EVCTRL_EVACT0_TGL (PORT_EVCTRL_EVACT0_TGL_Val << PORT_EVCTRL_EVACT0_Pos) /* (PORT_EVCTRL) Toggle output register of pin on event Position */ 168 #define PORT_EVCTRL_PORTEI0_Pos _UINT32_(7) /* (PORT_EVCTRL) PORT Event Input Enable 0 Position */ 169 #define PORT_EVCTRL_PORTEI0_Msk (_UINT32_(0x1) << PORT_EVCTRL_PORTEI0_Pos) /* (PORT_EVCTRL) PORT Event Input Enable 0 Mask */ 170 #define PORT_EVCTRL_PORTEI0(value) (PORT_EVCTRL_PORTEI0_Msk & (_UINT32_(value) << PORT_EVCTRL_PORTEI0_Pos)) /* Assignment of value for PORTEI0 in the PORT_EVCTRL register */ 171 #define PORT_EVCTRL_PID1_Pos _UINT32_(8) /* (PORT_EVCTRL) PORT Event Pin Identifier 1 Position */ 172 #define PORT_EVCTRL_PID1_Msk (_UINT32_(0x1F) << PORT_EVCTRL_PID1_Pos) /* (PORT_EVCTRL) PORT Event Pin Identifier 1 Mask */ 173 #define PORT_EVCTRL_PID1(value) (PORT_EVCTRL_PID1_Msk & (_UINT32_(value) << PORT_EVCTRL_PID1_Pos)) /* Assignment of value for PID1 in the PORT_EVCTRL register */ 174 #define PORT_EVCTRL_EVACT1_Pos _UINT32_(13) /* (PORT_EVCTRL) PORT Event Action 1 Position */ 175 #define PORT_EVCTRL_EVACT1_Msk (_UINT32_(0x3) << PORT_EVCTRL_EVACT1_Pos) /* (PORT_EVCTRL) PORT Event Action 1 Mask */ 176 #define PORT_EVCTRL_EVACT1(value) (PORT_EVCTRL_EVACT1_Msk & (_UINT32_(value) << PORT_EVCTRL_EVACT1_Pos)) /* Assignment of value for EVACT1 in the PORT_EVCTRL register */ 177 #define PORT_EVCTRL_PORTEI1_Pos _UINT32_(15) /* (PORT_EVCTRL) PORT Event Input Enable 1 Position */ 178 #define PORT_EVCTRL_PORTEI1_Msk (_UINT32_(0x1) << PORT_EVCTRL_PORTEI1_Pos) /* (PORT_EVCTRL) PORT Event Input Enable 1 Mask */ 179 #define PORT_EVCTRL_PORTEI1(value) (PORT_EVCTRL_PORTEI1_Msk & (_UINT32_(value) << PORT_EVCTRL_PORTEI1_Pos)) /* Assignment of value for PORTEI1 in the PORT_EVCTRL register */ 180 #define PORT_EVCTRL_PID2_Pos _UINT32_(16) /* (PORT_EVCTRL) PORT Event Pin Identifier 2 Position */ 181 #define PORT_EVCTRL_PID2_Msk (_UINT32_(0x1F) << PORT_EVCTRL_PID2_Pos) /* (PORT_EVCTRL) PORT Event Pin Identifier 2 Mask */ 182 #define PORT_EVCTRL_PID2(value) (PORT_EVCTRL_PID2_Msk & (_UINT32_(value) << PORT_EVCTRL_PID2_Pos)) /* Assignment of value for PID2 in the PORT_EVCTRL register */ 183 #define PORT_EVCTRL_EVACT2_Pos _UINT32_(21) /* (PORT_EVCTRL) PORT Event Action 2 Position */ 184 #define PORT_EVCTRL_EVACT2_Msk (_UINT32_(0x3) << PORT_EVCTRL_EVACT2_Pos) /* (PORT_EVCTRL) PORT Event Action 2 Mask */ 185 #define PORT_EVCTRL_EVACT2(value) (PORT_EVCTRL_EVACT2_Msk & (_UINT32_(value) << PORT_EVCTRL_EVACT2_Pos)) /* Assignment of value for EVACT2 in the PORT_EVCTRL register */ 186 #define PORT_EVCTRL_PORTEI2_Pos _UINT32_(23) /* (PORT_EVCTRL) PORT Event Input Enable 2 Position */ 187 #define PORT_EVCTRL_PORTEI2_Msk (_UINT32_(0x1) << PORT_EVCTRL_PORTEI2_Pos) /* (PORT_EVCTRL) PORT Event Input Enable 2 Mask */ 188 #define PORT_EVCTRL_PORTEI2(value) (PORT_EVCTRL_PORTEI2_Msk & (_UINT32_(value) << PORT_EVCTRL_PORTEI2_Pos)) /* Assignment of value for PORTEI2 in the PORT_EVCTRL register */ 189 #define PORT_EVCTRL_PID3_Pos _UINT32_(24) /* (PORT_EVCTRL) PORT Event Pin Identifier 3 Position */ 190 #define PORT_EVCTRL_PID3_Msk (_UINT32_(0x1F) << PORT_EVCTRL_PID3_Pos) /* (PORT_EVCTRL) PORT Event Pin Identifier 3 Mask */ 191 #define PORT_EVCTRL_PID3(value) (PORT_EVCTRL_PID3_Msk & (_UINT32_(value) << PORT_EVCTRL_PID3_Pos)) /* Assignment of value for PID3 in the PORT_EVCTRL register */ 192 #define PORT_EVCTRL_EVACT3_Pos _UINT32_(29) /* (PORT_EVCTRL) PORT Event Action 3 Position */ 193 #define PORT_EVCTRL_EVACT3_Msk (_UINT32_(0x3) << PORT_EVCTRL_EVACT3_Pos) /* (PORT_EVCTRL) PORT Event Action 3 Mask */ 194 #define PORT_EVCTRL_EVACT3(value) (PORT_EVCTRL_EVACT3_Msk & (_UINT32_(value) << PORT_EVCTRL_EVACT3_Pos)) /* Assignment of value for EVACT3 in the PORT_EVCTRL register */ 195 #define PORT_EVCTRL_PORTEI3_Pos _UINT32_(31) /* (PORT_EVCTRL) PORT Event Input Enable 3 Position */ 196 #define PORT_EVCTRL_PORTEI3_Msk (_UINT32_(0x1) << PORT_EVCTRL_PORTEI3_Pos) /* (PORT_EVCTRL) PORT Event Input Enable 3 Mask */ 197 #define PORT_EVCTRL_PORTEI3(value) (PORT_EVCTRL_PORTEI3_Msk & (_UINT32_(value) << PORT_EVCTRL_PORTEI3_Pos)) /* Assignment of value for PORTEI3 in the PORT_EVCTRL register */ 198 #define PORT_EVCTRL_Msk _UINT32_(0xFFFFFFFF) /* (PORT_EVCTRL) Register Mask */ 199 200 201 /* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W 8) Peripheral Multiplexing -------- */ 202 #define PORT_PMUX_RESETVALUE _UINT8_(0x00) /* (PORT_PMUX) Peripheral Multiplexing Reset Value */ 203 204 #define PORT_PMUX_PMUXE_Pos _UINT8_(0) /* (PORT_PMUX) Peripheral Multiplexing for Even-Numbered Pin Position */ 205 #define PORT_PMUX_PMUXE_Msk (_UINT8_(0xF) << PORT_PMUX_PMUXE_Pos) /* (PORT_PMUX) Peripheral Multiplexing for Even-Numbered Pin Mask */ 206 #define PORT_PMUX_PMUXE(value) (PORT_PMUX_PMUXE_Msk & (_UINT8_(value) << PORT_PMUX_PMUXE_Pos)) /* Assignment of value for PMUXE in the PORT_PMUX register */ 207 #define PORT_PMUX_PMUXE_A_Val _UINT8_(0x0) /* (PORT_PMUX) Peripheral function A selected */ 208 #define PORT_PMUX_PMUXE_B_Val _UINT8_(0x1) /* (PORT_PMUX) Peripheral function B selected */ 209 #define PORT_PMUX_PMUXE_C_Val _UINT8_(0x2) /* (PORT_PMUX) Peripheral function C selected */ 210 #define PORT_PMUX_PMUXE_D_Val _UINT8_(0x3) /* (PORT_PMUX) Peripheral function D selected */ 211 #define PORT_PMUX_PMUXE_E_Val _UINT8_(0x4) /* (PORT_PMUX) Peripheral function E selected */ 212 #define PORT_PMUX_PMUXE_F_Val _UINT8_(0x5) /* (PORT_PMUX) Peripheral function F selected */ 213 #define PORT_PMUX_PMUXE_G_Val _UINT8_(0x6) /* (PORT_PMUX) Peripheral function G selected */ 214 #define PORT_PMUX_PMUXE_H_Val _UINT8_(0x7) /* (PORT_PMUX) Peripheral function H selected */ 215 #define PORT_PMUX_PMUXE_I_Val _UINT8_(0x8) /* (PORT_PMUX) Peripheral function I selected */ 216 #define PORT_PMUX_PMUXE_J_Val _UINT8_(0x9) /* (PORT_PMUX) Peripheral function J selected */ 217 #define PORT_PMUX_PMUXE_K_Val _UINT8_(0xA) /* (PORT_PMUX) Peripheral function K selected */ 218 #define PORT_PMUX_PMUXE_L_Val _UINT8_(0xB) /* (PORT_PMUX) Peripheral function L selected */ 219 #define PORT_PMUX_PMUXE_M_Val _UINT8_(0xC) /* (PORT_PMUX) Peripheral function M selected */ 220 #define PORT_PMUX_PMUXE_N_Val _UINT8_(0xD) /* (PORT_PMUX) Peripheral function N selected */ 221 #define PORT_PMUX_PMUXE_A (PORT_PMUX_PMUXE_A_Val << PORT_PMUX_PMUXE_Pos) /* (PORT_PMUX) Peripheral function A selected Position */ 222 #define PORT_PMUX_PMUXE_B (PORT_PMUX_PMUXE_B_Val << PORT_PMUX_PMUXE_Pos) /* (PORT_PMUX) Peripheral function B selected Position */ 223 #define PORT_PMUX_PMUXE_C (PORT_PMUX_PMUXE_C_Val << PORT_PMUX_PMUXE_Pos) /* (PORT_PMUX) Peripheral function C selected Position */ 224 #define PORT_PMUX_PMUXE_D (PORT_PMUX_PMUXE_D_Val << PORT_PMUX_PMUXE_Pos) /* (PORT_PMUX) Peripheral function D selected Position */ 225 #define PORT_PMUX_PMUXE_E (PORT_PMUX_PMUXE_E_Val << PORT_PMUX_PMUXE_Pos) /* (PORT_PMUX) Peripheral function E selected Position */ 226 #define PORT_PMUX_PMUXE_F (PORT_PMUX_PMUXE_F_Val << PORT_PMUX_PMUXE_Pos) /* (PORT_PMUX) Peripheral function F selected Position */ 227 #define PORT_PMUX_PMUXE_G (PORT_PMUX_PMUXE_G_Val << PORT_PMUX_PMUXE_Pos) /* (PORT_PMUX) Peripheral function G selected Position */ 228 #define PORT_PMUX_PMUXE_H (PORT_PMUX_PMUXE_H_Val << PORT_PMUX_PMUXE_Pos) /* (PORT_PMUX) Peripheral function H selected Position */ 229 #define PORT_PMUX_PMUXE_I (PORT_PMUX_PMUXE_I_Val << PORT_PMUX_PMUXE_Pos) /* (PORT_PMUX) Peripheral function I selected Position */ 230 #define PORT_PMUX_PMUXE_J (PORT_PMUX_PMUXE_J_Val << PORT_PMUX_PMUXE_Pos) /* (PORT_PMUX) Peripheral function J selected Position */ 231 #define PORT_PMUX_PMUXE_K (PORT_PMUX_PMUXE_K_Val << PORT_PMUX_PMUXE_Pos) /* (PORT_PMUX) Peripheral function K selected Position */ 232 #define PORT_PMUX_PMUXE_L (PORT_PMUX_PMUXE_L_Val << PORT_PMUX_PMUXE_Pos) /* (PORT_PMUX) Peripheral function L selected Position */ 233 #define PORT_PMUX_PMUXE_M (PORT_PMUX_PMUXE_M_Val << PORT_PMUX_PMUXE_Pos) /* (PORT_PMUX) Peripheral function M selected Position */ 234 #define PORT_PMUX_PMUXE_N (PORT_PMUX_PMUXE_N_Val << PORT_PMUX_PMUXE_Pos) /* (PORT_PMUX) Peripheral function N selected Position */ 235 #define PORT_PMUX_PMUXO_Pos _UINT8_(4) /* (PORT_PMUX) Peripheral Multiplexing for Odd-Numbered Pin Position */ 236 #define PORT_PMUX_PMUXO_Msk (_UINT8_(0xF) << PORT_PMUX_PMUXO_Pos) /* (PORT_PMUX) Peripheral Multiplexing for Odd-Numbered Pin Mask */ 237 #define PORT_PMUX_PMUXO(value) (PORT_PMUX_PMUXO_Msk & (_UINT8_(value) << PORT_PMUX_PMUXO_Pos)) /* Assignment of value for PMUXO in the PORT_PMUX register */ 238 #define PORT_PMUX_PMUXO_A_Val _UINT8_(0x0) /* (PORT_PMUX) Peripheral function A selected */ 239 #define PORT_PMUX_PMUXO_B_Val _UINT8_(0x1) /* (PORT_PMUX) Peripheral function B selected */ 240 #define PORT_PMUX_PMUXO_C_Val _UINT8_(0x2) /* (PORT_PMUX) Peripheral function C selected */ 241 #define PORT_PMUX_PMUXO_D_Val _UINT8_(0x3) /* (PORT_PMUX) Peripheral function D selected */ 242 #define PORT_PMUX_PMUXO_E_Val _UINT8_(0x4) /* (PORT_PMUX) Peripheral function E selected */ 243 #define PORT_PMUX_PMUXO_F_Val _UINT8_(0x5) /* (PORT_PMUX) Peripheral function F selected */ 244 #define PORT_PMUX_PMUXO_G_Val _UINT8_(0x6) /* (PORT_PMUX) Peripheral function G selected */ 245 #define PORT_PMUX_PMUXO_H_Val _UINT8_(0x7) /* (PORT_PMUX) Peripheral function H selected */ 246 #define PORT_PMUX_PMUXO_I_Val _UINT8_(0x8) /* (PORT_PMUX) Peripheral function I selected */ 247 #define PORT_PMUX_PMUXO_J_Val _UINT8_(0x9) /* (PORT_PMUX) Peripheral function J selected */ 248 #define PORT_PMUX_PMUXO_K_Val _UINT8_(0xA) /* (PORT_PMUX) Peripheral function K selected */ 249 #define PORT_PMUX_PMUXO_L_Val _UINT8_(0xB) /* (PORT_PMUX) Peripheral function L selected */ 250 #define PORT_PMUX_PMUXO_M_Val _UINT8_(0xC) /* (PORT_PMUX) Peripheral function M selected */ 251 #define PORT_PMUX_PMUXO_N_Val _UINT8_(0xD) /* (PORT_PMUX) Peripheral function N selected */ 252 #define PORT_PMUX_PMUXO_A (PORT_PMUX_PMUXO_A_Val << PORT_PMUX_PMUXO_Pos) /* (PORT_PMUX) Peripheral function A selected Position */ 253 #define PORT_PMUX_PMUXO_B (PORT_PMUX_PMUXO_B_Val << PORT_PMUX_PMUXO_Pos) /* (PORT_PMUX) Peripheral function B selected Position */ 254 #define PORT_PMUX_PMUXO_C (PORT_PMUX_PMUXO_C_Val << PORT_PMUX_PMUXO_Pos) /* (PORT_PMUX) Peripheral function C selected Position */ 255 #define PORT_PMUX_PMUXO_D (PORT_PMUX_PMUXO_D_Val << PORT_PMUX_PMUXO_Pos) /* (PORT_PMUX) Peripheral function D selected Position */ 256 #define PORT_PMUX_PMUXO_E (PORT_PMUX_PMUXO_E_Val << PORT_PMUX_PMUXO_Pos) /* (PORT_PMUX) Peripheral function E selected Position */ 257 #define PORT_PMUX_PMUXO_F (PORT_PMUX_PMUXO_F_Val << PORT_PMUX_PMUXO_Pos) /* (PORT_PMUX) Peripheral function F selected Position */ 258 #define PORT_PMUX_PMUXO_G (PORT_PMUX_PMUXO_G_Val << PORT_PMUX_PMUXO_Pos) /* (PORT_PMUX) Peripheral function G selected Position */ 259 #define PORT_PMUX_PMUXO_H (PORT_PMUX_PMUXO_H_Val << PORT_PMUX_PMUXO_Pos) /* (PORT_PMUX) Peripheral function H selected Position */ 260 #define PORT_PMUX_PMUXO_I (PORT_PMUX_PMUXO_I_Val << PORT_PMUX_PMUXO_Pos) /* (PORT_PMUX) Peripheral function I selected Position */ 261 #define PORT_PMUX_PMUXO_J (PORT_PMUX_PMUXO_J_Val << PORT_PMUX_PMUXO_Pos) /* (PORT_PMUX) Peripheral function J selected Position */ 262 #define PORT_PMUX_PMUXO_K (PORT_PMUX_PMUXO_K_Val << PORT_PMUX_PMUXO_Pos) /* (PORT_PMUX) Peripheral function K selected Position */ 263 #define PORT_PMUX_PMUXO_L (PORT_PMUX_PMUXO_L_Val << PORT_PMUX_PMUXO_Pos) /* (PORT_PMUX) Peripheral function L selected Position */ 264 #define PORT_PMUX_PMUXO_M (PORT_PMUX_PMUXO_M_Val << PORT_PMUX_PMUXO_Pos) /* (PORT_PMUX) Peripheral function M selected Position */ 265 #define PORT_PMUX_PMUXO_N (PORT_PMUX_PMUXO_N_Val << PORT_PMUX_PMUXO_Pos) /* (PORT_PMUX) Peripheral function N selected Position */ 266 #define PORT_PMUX_Msk _UINT8_(0xFF) /* (PORT_PMUX) Register Mask */ 267 268 269 /* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W 8) Pin Configuration -------- */ 270 #define PORT_PINCFG_RESETVALUE _UINT8_(0x00) /* (PORT_PINCFG) Pin Configuration Reset Value */ 271 272 #define PORT_PINCFG_PMUXEN_Pos _UINT8_(0) /* (PORT_PINCFG) Peripheral Multiplexer Enable Position */ 273 #define PORT_PINCFG_PMUXEN_Msk (_UINT8_(0x1) << PORT_PINCFG_PMUXEN_Pos) /* (PORT_PINCFG) Peripheral Multiplexer Enable Mask */ 274 #define PORT_PINCFG_PMUXEN(value) (PORT_PINCFG_PMUXEN_Msk & (_UINT8_(value) << PORT_PINCFG_PMUXEN_Pos)) /* Assignment of value for PMUXEN in the PORT_PINCFG register */ 275 #define PORT_PINCFG_INEN_Pos _UINT8_(1) /* (PORT_PINCFG) Input Enable Position */ 276 #define PORT_PINCFG_INEN_Msk (_UINT8_(0x1) << PORT_PINCFG_INEN_Pos) /* (PORT_PINCFG) Input Enable Mask */ 277 #define PORT_PINCFG_INEN(value) (PORT_PINCFG_INEN_Msk & (_UINT8_(value) << PORT_PINCFG_INEN_Pos)) /* Assignment of value for INEN in the PORT_PINCFG register */ 278 #define PORT_PINCFG_PULLEN_Pos _UINT8_(2) /* (PORT_PINCFG) Pull Enable Position */ 279 #define PORT_PINCFG_PULLEN_Msk (_UINT8_(0x1) << PORT_PINCFG_PULLEN_Pos) /* (PORT_PINCFG) Pull Enable Mask */ 280 #define PORT_PINCFG_PULLEN(value) (PORT_PINCFG_PULLEN_Msk & (_UINT8_(value) << PORT_PINCFG_PULLEN_Pos)) /* Assignment of value for PULLEN in the PORT_PINCFG register */ 281 #define PORT_PINCFG_DRVSTR_Pos _UINT8_(6) /* (PORT_PINCFG) Output Driver Strength Selection Position */ 282 #define PORT_PINCFG_DRVSTR_Msk (_UINT8_(0x1) << PORT_PINCFG_DRVSTR_Pos) /* (PORT_PINCFG) Output Driver Strength Selection Mask */ 283 #define PORT_PINCFG_DRVSTR(value) (PORT_PINCFG_DRVSTR_Msk & (_UINT8_(value) << PORT_PINCFG_DRVSTR_Pos)) /* Assignment of value for DRVSTR in the PORT_PINCFG register */ 284 #define PORT_PINCFG_Msk _UINT8_(0x47) /* (PORT_PINCFG) Register Mask */ 285 286 287 /* PORT register offsets definitions */ 288 #define PORT_DIR_REG_OFST _UINT32_(0x00) /* (PORT_DIR) Data Direction Offset */ 289 #define PORT_DIRCLR_REG_OFST _UINT32_(0x04) /* (PORT_DIRCLR) Data Direction Clear Offset */ 290 #define PORT_DIRSET_REG_OFST _UINT32_(0x08) /* (PORT_DIRSET) Data Direction Set Offset */ 291 #define PORT_DIRTGL_REG_OFST _UINT32_(0x0C) /* (PORT_DIRTGL) Data Direction Toggle Offset */ 292 #define PORT_OUT_REG_OFST _UINT32_(0x10) /* (PORT_OUT) Data Output Value Offset */ 293 #define PORT_OUTCLR_REG_OFST _UINT32_(0x14) /* (PORT_OUTCLR) Data Output Value Clear Offset */ 294 #define PORT_OUTSET_REG_OFST _UINT32_(0x18) /* (PORT_OUTSET) Data Output Value Set Offset */ 295 #define PORT_OUTTGL_REG_OFST _UINT32_(0x1C) /* (PORT_OUTTGL) Data Output Value Toggle Offset */ 296 #define PORT_IN_REG_OFST _UINT32_(0x20) /* (PORT_IN) Data Input Value Offset */ 297 #define PORT_CTRL_REG_OFST _UINT32_(0x24) /* (PORT_CTRL) Control Offset */ 298 #define PORT_WRCONFIG_REG_OFST _UINT32_(0x28) /* (PORT_WRCONFIG) Write Configuration Offset */ 299 #define PORT_EVCTRL_REG_OFST _UINT32_(0x2C) /* (PORT_EVCTRL) Event Input Control Offset */ 300 #define PORT_PMUX_REG_OFST _UINT32_(0x30) /* (PORT_PMUX) Peripheral Multiplexing Offset */ 301 #define PORT_PMUX0_REG_OFST _UINT32_(0x30) /* (PORT_PMUX0) Peripheral Multiplexing Offset */ 302 #define PORT_PMUX1_REG_OFST _UINT32_(0x31) /* (PORT_PMUX1) Peripheral Multiplexing Offset */ 303 #define PORT_PMUX2_REG_OFST _UINT32_(0x32) /* (PORT_PMUX2) Peripheral Multiplexing Offset */ 304 #define PORT_PMUX3_REG_OFST _UINT32_(0x33) /* (PORT_PMUX3) Peripheral Multiplexing Offset */ 305 #define PORT_PMUX4_REG_OFST _UINT32_(0x34) /* (PORT_PMUX4) Peripheral Multiplexing Offset */ 306 #define PORT_PMUX5_REG_OFST _UINT32_(0x35) /* (PORT_PMUX5) Peripheral Multiplexing Offset */ 307 #define PORT_PMUX6_REG_OFST _UINT32_(0x36) /* (PORT_PMUX6) Peripheral Multiplexing Offset */ 308 #define PORT_PMUX7_REG_OFST _UINT32_(0x37) /* (PORT_PMUX7) Peripheral Multiplexing Offset */ 309 #define PORT_PMUX8_REG_OFST _UINT32_(0x38) /* (PORT_PMUX8) Peripheral Multiplexing Offset */ 310 #define PORT_PMUX9_REG_OFST _UINT32_(0x39) /* (PORT_PMUX9) Peripheral Multiplexing Offset */ 311 #define PORT_PMUX10_REG_OFST _UINT32_(0x3A) /* (PORT_PMUX10) Peripheral Multiplexing Offset */ 312 #define PORT_PMUX11_REG_OFST _UINT32_(0x3B) /* (PORT_PMUX11) Peripheral Multiplexing Offset */ 313 #define PORT_PMUX12_REG_OFST _UINT32_(0x3C) /* (PORT_PMUX12) Peripheral Multiplexing Offset */ 314 #define PORT_PMUX13_REG_OFST _UINT32_(0x3D) /* (PORT_PMUX13) Peripheral Multiplexing Offset */ 315 #define PORT_PMUX14_REG_OFST _UINT32_(0x3E) /* (PORT_PMUX14) Peripheral Multiplexing Offset */ 316 #define PORT_PMUX15_REG_OFST _UINT32_(0x3F) /* (PORT_PMUX15) Peripheral Multiplexing Offset */ 317 #define PORT_PINCFG_REG_OFST _UINT32_(0x40) /* (PORT_PINCFG) Pin Configuration Offset */ 318 #define PORT_PINCFG0_REG_OFST _UINT32_(0x40) /* (PORT_PINCFG0) Pin Configuration Offset */ 319 #define PORT_PINCFG1_REG_OFST _UINT32_(0x41) /* (PORT_PINCFG1) Pin Configuration Offset */ 320 #define PORT_PINCFG2_REG_OFST _UINT32_(0x42) /* (PORT_PINCFG2) Pin Configuration Offset */ 321 #define PORT_PINCFG3_REG_OFST _UINT32_(0x43) /* (PORT_PINCFG3) Pin Configuration Offset */ 322 #define PORT_PINCFG4_REG_OFST _UINT32_(0x44) /* (PORT_PINCFG4) Pin Configuration Offset */ 323 #define PORT_PINCFG5_REG_OFST _UINT32_(0x45) /* (PORT_PINCFG5) Pin Configuration Offset */ 324 #define PORT_PINCFG6_REG_OFST _UINT32_(0x46) /* (PORT_PINCFG6) Pin Configuration Offset */ 325 #define PORT_PINCFG7_REG_OFST _UINT32_(0x47) /* (PORT_PINCFG7) Pin Configuration Offset */ 326 #define PORT_PINCFG8_REG_OFST _UINT32_(0x48) /* (PORT_PINCFG8) Pin Configuration Offset */ 327 #define PORT_PINCFG9_REG_OFST _UINT32_(0x49) /* (PORT_PINCFG9) Pin Configuration Offset */ 328 #define PORT_PINCFG10_REG_OFST _UINT32_(0x4A) /* (PORT_PINCFG10) Pin Configuration Offset */ 329 #define PORT_PINCFG11_REG_OFST _UINT32_(0x4B) /* (PORT_PINCFG11) Pin Configuration Offset */ 330 #define PORT_PINCFG12_REG_OFST _UINT32_(0x4C) /* (PORT_PINCFG12) Pin Configuration Offset */ 331 #define PORT_PINCFG13_REG_OFST _UINT32_(0x4D) /* (PORT_PINCFG13) Pin Configuration Offset */ 332 #define PORT_PINCFG14_REG_OFST _UINT32_(0x4E) /* (PORT_PINCFG14) Pin Configuration Offset */ 333 #define PORT_PINCFG15_REG_OFST _UINT32_(0x4F) /* (PORT_PINCFG15) Pin Configuration Offset */ 334 #define PORT_PINCFG16_REG_OFST _UINT32_(0x50) /* (PORT_PINCFG16) Pin Configuration Offset */ 335 #define PORT_PINCFG17_REG_OFST _UINT32_(0x51) /* (PORT_PINCFG17) Pin Configuration Offset */ 336 #define PORT_PINCFG18_REG_OFST _UINT32_(0x52) /* (PORT_PINCFG18) Pin Configuration Offset */ 337 #define PORT_PINCFG19_REG_OFST _UINT32_(0x53) /* (PORT_PINCFG19) Pin Configuration Offset */ 338 #define PORT_PINCFG20_REG_OFST _UINT32_(0x54) /* (PORT_PINCFG20) Pin Configuration Offset */ 339 #define PORT_PINCFG21_REG_OFST _UINT32_(0x55) /* (PORT_PINCFG21) Pin Configuration Offset */ 340 #define PORT_PINCFG22_REG_OFST _UINT32_(0x56) /* (PORT_PINCFG22) Pin Configuration Offset */ 341 #define PORT_PINCFG23_REG_OFST _UINT32_(0x57) /* (PORT_PINCFG23) Pin Configuration Offset */ 342 #define PORT_PINCFG24_REG_OFST _UINT32_(0x58) /* (PORT_PINCFG24) Pin Configuration Offset */ 343 #define PORT_PINCFG25_REG_OFST _UINT32_(0x59) /* (PORT_PINCFG25) Pin Configuration Offset */ 344 #define PORT_PINCFG26_REG_OFST _UINT32_(0x5A) /* (PORT_PINCFG26) Pin Configuration Offset */ 345 #define PORT_PINCFG27_REG_OFST _UINT32_(0x5B) /* (PORT_PINCFG27) Pin Configuration Offset */ 346 #define PORT_PINCFG28_REG_OFST _UINT32_(0x5C) /* (PORT_PINCFG28) Pin Configuration Offset */ 347 #define PORT_PINCFG29_REG_OFST _UINT32_(0x5D) /* (PORT_PINCFG29) Pin Configuration Offset */ 348 #define PORT_PINCFG30_REG_OFST _UINT32_(0x5E) /* (PORT_PINCFG30) Pin Configuration Offset */ 349 #define PORT_PINCFG31_REG_OFST _UINT32_(0x5F) /* (PORT_PINCFG31) Pin Configuration Offset */ 350 351 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 352 /* GROUP register API structure */ 353 typedef struct 354 { 355 __IO uint32_t PORT_DIR; /* Offset: 0x00 (R/W 32) Data Direction */ 356 __IO uint32_t PORT_DIRCLR; /* Offset: 0x04 (R/W 32) Data Direction Clear */ 357 __IO uint32_t PORT_DIRSET; /* Offset: 0x08 (R/W 32) Data Direction Set */ 358 __IO uint32_t PORT_DIRTGL; /* Offset: 0x0C (R/W 32) Data Direction Toggle */ 359 __IO uint32_t PORT_OUT; /* Offset: 0x10 (R/W 32) Data Output Value */ 360 __IO uint32_t PORT_OUTCLR; /* Offset: 0x14 (R/W 32) Data Output Value Clear */ 361 __IO uint32_t PORT_OUTSET; /* Offset: 0x18 (R/W 32) Data Output Value Set */ 362 __IO uint32_t PORT_OUTTGL; /* Offset: 0x1C (R/W 32) Data Output Value Toggle */ 363 __I uint32_t PORT_IN; /* Offset: 0x20 (R/ 32) Data Input Value */ 364 __IO uint32_t PORT_CTRL; /* Offset: 0x24 (R/W 32) Control */ 365 __O uint32_t PORT_WRCONFIG; /* Offset: 0x28 ( /W 32) Write Configuration */ 366 __IO uint32_t PORT_EVCTRL; /* Offset: 0x2C (R/W 32) Event Input Control */ 367 __IO uint8_t PORT_PMUX[16]; /* Offset: 0x30 (R/W 8) Peripheral Multiplexing */ 368 __IO uint8_t PORT_PINCFG[32]; /* Offset: 0x40 (R/W 8) Pin Configuration */ 369 __I uint8_t Reserved1[0x20]; 370 } port_group_registers_t; 371 372 #define PORT_GROUP_NUMBER 4 373 374 /* PORT register API structure */ 375 typedef struct 376 { /* Port Module */ 377 port_group_registers_t GROUP[PORT_GROUP_NUMBER]; /* Offset: 0x00 */ 378 } port_registers_t; 379 380 381 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 382 #endif /* _PIC32CXSG41_PORT_COMPONENT_H_ */ 383
