1 /* 2 * Component description for PM 3 * 4 * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 */ 19 20 /* file generated from device description file (ATDF) version 2023-03-17T09:48:34Z */ 21 #ifndef _PIC32CXSG41_PM_COMPONENT_H_ 22 #define _PIC32CXSG41_PM_COMPONENT_H_ 23 24 /* ************************************************************************** */ 25 /* SOFTWARE API DEFINITION FOR PM */ 26 /* ************************************************************************** */ 27 28 /* -------- PM_CTRLA : (PM Offset: 0x00) (R/W 8) Control A -------- */ 29 #define PM_CTRLA_RESETVALUE _UINT8_(0x00) /* (PM_CTRLA) Control A Reset Value */ 30 31 #define PM_CTRLA_IORET_Pos _UINT8_(2) /* (PM_CTRLA) I/O Retention Position */ 32 #define PM_CTRLA_IORET_Msk (_UINT8_(0x1) << PM_CTRLA_IORET_Pos) /* (PM_CTRLA) I/O Retention Mask */ 33 #define PM_CTRLA_IORET(value) (PM_CTRLA_IORET_Msk & (_UINT8_(value) << PM_CTRLA_IORET_Pos)) /* Assignment of value for IORET in the PM_CTRLA register */ 34 #define PM_CTRLA_Msk _UINT8_(0x04) /* (PM_CTRLA) Register Mask */ 35 36 37 /* -------- PM_SLEEPCFG : (PM Offset: 0x01) (R/W 8) Sleep Configuration -------- */ 38 #define PM_SLEEPCFG_RESETVALUE _UINT8_(0x02) /* (PM_SLEEPCFG) Sleep Configuration Reset Value */ 39 40 #define PM_SLEEPCFG_SLEEPMODE_Pos _UINT8_(0) /* (PM_SLEEPCFG) Sleep Mode Position */ 41 #define PM_SLEEPCFG_SLEEPMODE_Msk (_UINT8_(0x7) << PM_SLEEPCFG_SLEEPMODE_Pos) /* (PM_SLEEPCFG) Sleep Mode Mask */ 42 #define PM_SLEEPCFG_SLEEPMODE(value) (PM_SLEEPCFG_SLEEPMODE_Msk & (_UINT8_(value) << PM_SLEEPCFG_SLEEPMODE_Pos)) /* Assignment of value for SLEEPMODE in the PM_SLEEPCFG register */ 43 #define PM_SLEEPCFG_SLEEPMODE_IDLE_Val _UINT8_(0x2) /* (PM_SLEEPCFG) CPU, AHBx, and APBx clocks are OFF */ 44 #define PM_SLEEPCFG_SLEEPMODE_STANDBY_Val _UINT8_(0x4) /* (PM_SLEEPCFG) All Clocks are OFF */ 45 #define PM_SLEEPCFG_SLEEPMODE_HIBERNATE_Val _UINT8_(0x5) /* (PM_SLEEPCFG) Backup domain is ON as well as some PDRAMs */ 46 #define PM_SLEEPCFG_SLEEPMODE_BACKUP_Val _UINT8_(0x6) /* (PM_SLEEPCFG) Only Backup domain is powered ON */ 47 #define PM_SLEEPCFG_SLEEPMODE_OFF_Val _UINT8_(0x7) /* (PM_SLEEPCFG) All power domains are powered OFF */ 48 #define PM_SLEEPCFG_SLEEPMODE_IDLE (PM_SLEEPCFG_SLEEPMODE_IDLE_Val << PM_SLEEPCFG_SLEEPMODE_Pos) /* (PM_SLEEPCFG) CPU, AHBx, and APBx clocks are OFF Position */ 49 #define PM_SLEEPCFG_SLEEPMODE_STANDBY (PM_SLEEPCFG_SLEEPMODE_STANDBY_Val << PM_SLEEPCFG_SLEEPMODE_Pos) /* (PM_SLEEPCFG) All Clocks are OFF Position */ 50 #define PM_SLEEPCFG_SLEEPMODE_HIBERNATE (PM_SLEEPCFG_SLEEPMODE_HIBERNATE_Val << PM_SLEEPCFG_SLEEPMODE_Pos) /* (PM_SLEEPCFG) Backup domain is ON as well as some PDRAMs Position */ 51 #define PM_SLEEPCFG_SLEEPMODE_BACKUP (PM_SLEEPCFG_SLEEPMODE_BACKUP_Val << PM_SLEEPCFG_SLEEPMODE_Pos) /* (PM_SLEEPCFG) Only Backup domain is powered ON Position */ 52 #define PM_SLEEPCFG_SLEEPMODE_OFF (PM_SLEEPCFG_SLEEPMODE_OFF_Val << PM_SLEEPCFG_SLEEPMODE_Pos) /* (PM_SLEEPCFG) All power domains are powered OFF Position */ 53 #define PM_SLEEPCFG_Msk _UINT8_(0x07) /* (PM_SLEEPCFG) Register Mask */ 54 55 56 /* -------- PM_INTENCLR : (PM Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ 57 #define PM_INTENCLR_RESETVALUE _UINT8_(0x00) /* (PM_INTENCLR) Interrupt Enable Clear Reset Value */ 58 59 #define PM_INTENCLR_SLEEPRDY_Pos _UINT8_(0) /* (PM_INTENCLR) Sleep Mode Entry Ready Enable Position */ 60 #define PM_INTENCLR_SLEEPRDY_Msk (_UINT8_(0x1) << PM_INTENCLR_SLEEPRDY_Pos) /* (PM_INTENCLR) Sleep Mode Entry Ready Enable Mask */ 61 #define PM_INTENCLR_SLEEPRDY(value) (PM_INTENCLR_SLEEPRDY_Msk & (_UINT8_(value) << PM_INTENCLR_SLEEPRDY_Pos)) /* Assignment of value for SLEEPRDY in the PM_INTENCLR register */ 62 #define PM_INTENCLR_Msk _UINT8_(0x01) /* (PM_INTENCLR) Register Mask */ 63 64 65 /* -------- PM_INTENSET : (PM Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ 66 #define PM_INTENSET_RESETVALUE _UINT8_(0x00) /* (PM_INTENSET) Interrupt Enable Set Reset Value */ 67 68 #define PM_INTENSET_SLEEPRDY_Pos _UINT8_(0) /* (PM_INTENSET) Sleep Mode Entry Ready Enable Position */ 69 #define PM_INTENSET_SLEEPRDY_Msk (_UINT8_(0x1) << PM_INTENSET_SLEEPRDY_Pos) /* (PM_INTENSET) Sleep Mode Entry Ready Enable Mask */ 70 #define PM_INTENSET_SLEEPRDY(value) (PM_INTENSET_SLEEPRDY_Msk & (_UINT8_(value) << PM_INTENSET_SLEEPRDY_Pos)) /* Assignment of value for SLEEPRDY in the PM_INTENSET register */ 71 #define PM_INTENSET_Msk _UINT8_(0x01) /* (PM_INTENSET) Register Mask */ 72 73 74 /* -------- PM_INTFLAG : (PM Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ 75 #define PM_INTFLAG_RESETVALUE _UINT8_(0x00) /* (PM_INTFLAG) Interrupt Flag Status and Clear Reset Value */ 76 77 #define PM_INTFLAG_SLEEPRDY_Pos _UINT8_(0) /* (PM_INTFLAG) Sleep Mode Entry Ready Position */ 78 #define PM_INTFLAG_SLEEPRDY_Msk (_UINT8_(0x1) << PM_INTFLAG_SLEEPRDY_Pos) /* (PM_INTFLAG) Sleep Mode Entry Ready Mask */ 79 #define PM_INTFLAG_SLEEPRDY(value) (PM_INTFLAG_SLEEPRDY_Msk & (_UINT8_(value) << PM_INTFLAG_SLEEPRDY_Pos)) /* Assignment of value for SLEEPRDY in the PM_INTFLAG register */ 80 #define PM_INTFLAG_Msk _UINT8_(0x01) /* (PM_INTFLAG) Register Mask */ 81 82 83 /* -------- PM_STDBYCFG : (PM Offset: 0x08) (R/W 8) Standby Configuration -------- */ 84 #define PM_STDBYCFG_RESETVALUE _UINT8_(0x00) /* (PM_STDBYCFG) Standby Configuration Reset Value */ 85 86 #define PM_STDBYCFG_RAMCFG_Pos _UINT8_(0) /* (PM_STDBYCFG) Ram Configuration Position */ 87 #define PM_STDBYCFG_RAMCFG_Msk (_UINT8_(0x3) << PM_STDBYCFG_RAMCFG_Pos) /* (PM_STDBYCFG) Ram Configuration Mask */ 88 #define PM_STDBYCFG_RAMCFG(value) (PM_STDBYCFG_RAMCFG_Msk & (_UINT8_(value) << PM_STDBYCFG_RAMCFG_Pos)) /* Assignment of value for RAMCFG in the PM_STDBYCFG register */ 89 #define PM_STDBYCFG_RAMCFG_RET_Val _UINT8_(0x0) /* (PM_STDBYCFG) All the system RAM is retained */ 90 #define PM_STDBYCFG_RAMCFG_PARTIAL_Val _UINT8_(0x1) /* (PM_STDBYCFG) Only the first 32Kbytes of the system RAM is retained */ 91 #define PM_STDBYCFG_RAMCFG_OFF_Val _UINT8_(0x2) /* (PM_STDBYCFG) All the system RAM is turned OFF */ 92 #define PM_STDBYCFG_RAMCFG_RET (PM_STDBYCFG_RAMCFG_RET_Val << PM_STDBYCFG_RAMCFG_Pos) /* (PM_STDBYCFG) All the system RAM is retained Position */ 93 #define PM_STDBYCFG_RAMCFG_PARTIAL (PM_STDBYCFG_RAMCFG_PARTIAL_Val << PM_STDBYCFG_RAMCFG_Pos) /* (PM_STDBYCFG) Only the first 32Kbytes of the system RAM is retained Position */ 94 #define PM_STDBYCFG_RAMCFG_OFF (PM_STDBYCFG_RAMCFG_OFF_Val << PM_STDBYCFG_RAMCFG_Pos) /* (PM_STDBYCFG) All the system RAM is turned OFF Position */ 95 #define PM_STDBYCFG_FASTWKUP_Pos _UINT8_(4) /* (PM_STDBYCFG) Fast Wakeup Position */ 96 #define PM_STDBYCFG_FASTWKUP_Msk (_UINT8_(0x3) << PM_STDBYCFG_FASTWKUP_Pos) /* (PM_STDBYCFG) Fast Wakeup Mask */ 97 #define PM_STDBYCFG_FASTWKUP(value) (PM_STDBYCFG_FASTWKUP_Msk & (_UINT8_(value) << PM_STDBYCFG_FASTWKUP_Pos)) /* Assignment of value for FASTWKUP in the PM_STDBYCFG register */ 98 #define PM_STDBYCFG_FASTWKUP_NO_Val _UINT8_(0x0) /* (PM_STDBYCFG) Fast Wakeup is disabled */ 99 #define PM_STDBYCFG_FASTWKUP_NVM_Val _UINT8_(0x1) /* (PM_STDBYCFG) Fast Wakeup is enabled on NVM */ 100 #define PM_STDBYCFG_FASTWKUP_MAINVREG_Val _UINT8_(0x2) /* (PM_STDBYCFG) Fast Wakeup is enabled on the main voltage regulator (MAINVREG) */ 101 #define PM_STDBYCFG_FASTWKUP_BOTH_Val _UINT8_(0x3) /* (PM_STDBYCFG) Fast Wakeup is enabled on both NVM and MAINVREG */ 102 #define PM_STDBYCFG_FASTWKUP_NO (PM_STDBYCFG_FASTWKUP_NO_Val << PM_STDBYCFG_FASTWKUP_Pos) /* (PM_STDBYCFG) Fast Wakeup is disabled Position */ 103 #define PM_STDBYCFG_FASTWKUP_NVM (PM_STDBYCFG_FASTWKUP_NVM_Val << PM_STDBYCFG_FASTWKUP_Pos) /* (PM_STDBYCFG) Fast Wakeup is enabled on NVM Position */ 104 #define PM_STDBYCFG_FASTWKUP_MAINVREG (PM_STDBYCFG_FASTWKUP_MAINVREG_Val << PM_STDBYCFG_FASTWKUP_Pos) /* (PM_STDBYCFG) Fast Wakeup is enabled on the main voltage regulator (MAINVREG) Position */ 105 #define PM_STDBYCFG_FASTWKUP_BOTH (PM_STDBYCFG_FASTWKUP_BOTH_Val << PM_STDBYCFG_FASTWKUP_Pos) /* (PM_STDBYCFG) Fast Wakeup is enabled on both NVM and MAINVREG Position */ 106 #define PM_STDBYCFG_Msk _UINT8_(0x33) /* (PM_STDBYCFG) Register Mask */ 107 108 109 /* -------- PM_HIBCFG : (PM Offset: 0x09) (R/W 8) Hibernate Configuration -------- */ 110 #define PM_HIBCFG_RESETVALUE _UINT8_(0x00) /* (PM_HIBCFG) Hibernate Configuration Reset Value */ 111 112 #define PM_HIBCFG_RAMCFG_Pos _UINT8_(0) /* (PM_HIBCFG) Ram Configuration Position */ 113 #define PM_HIBCFG_RAMCFG_Msk (_UINT8_(0x3) << PM_HIBCFG_RAMCFG_Pos) /* (PM_HIBCFG) Ram Configuration Mask */ 114 #define PM_HIBCFG_RAMCFG(value) (PM_HIBCFG_RAMCFG_Msk & (_UINT8_(value) << PM_HIBCFG_RAMCFG_Pos)) /* Assignment of value for RAMCFG in the PM_HIBCFG register */ 115 #define PM_HIBCFG_RAMCFG_RET_Val _UINT8_(0x0) /* (PM_HIBCFG) All the system RAM is retained */ 116 #define PM_HIBCFG_RAMCFG_PARTIAL_Val _UINT8_(0x1) /* (PM_HIBCFG) Only the first 32Kbytes of the system RAM is retained */ 117 #define PM_HIBCFG_RAMCFG_OFF_Val _UINT8_(0x2) /* (PM_HIBCFG) All the system RAM is turned OFF */ 118 #define PM_HIBCFG_RAMCFG_RET (PM_HIBCFG_RAMCFG_RET_Val << PM_HIBCFG_RAMCFG_Pos) /* (PM_HIBCFG) All the system RAM is retained Position */ 119 #define PM_HIBCFG_RAMCFG_PARTIAL (PM_HIBCFG_RAMCFG_PARTIAL_Val << PM_HIBCFG_RAMCFG_Pos) /* (PM_HIBCFG) Only the first 32Kbytes of the system RAM is retained Position */ 120 #define PM_HIBCFG_RAMCFG_OFF (PM_HIBCFG_RAMCFG_OFF_Val << PM_HIBCFG_RAMCFG_Pos) /* (PM_HIBCFG) All the system RAM is turned OFF Position */ 121 #define PM_HIBCFG_BRAMCFG_Pos _UINT8_(2) /* (PM_HIBCFG) Backup Ram Configuration Position */ 122 #define PM_HIBCFG_BRAMCFG_Msk (_UINT8_(0x3) << PM_HIBCFG_BRAMCFG_Pos) /* (PM_HIBCFG) Backup Ram Configuration Mask */ 123 #define PM_HIBCFG_BRAMCFG(value) (PM_HIBCFG_BRAMCFG_Msk & (_UINT8_(value) << PM_HIBCFG_BRAMCFG_Pos)) /* Assignment of value for BRAMCFG in the PM_HIBCFG register */ 124 #define PM_HIBCFG_BRAMCFG_RET_Val _UINT8_(0x0) /* (PM_HIBCFG) All the backup RAM is retained */ 125 #define PM_HIBCFG_BRAMCFG_PARTIAL_Val _UINT8_(0x1) /* (PM_HIBCFG) Only the first 4Kbytes of the backup RAM is retained */ 126 #define PM_HIBCFG_BRAMCFG_OFF_Val _UINT8_(0x2) /* (PM_HIBCFG) All the backup RAM is turned OFF */ 127 #define PM_HIBCFG_BRAMCFG_RET (PM_HIBCFG_BRAMCFG_RET_Val << PM_HIBCFG_BRAMCFG_Pos) /* (PM_HIBCFG) All the backup RAM is retained Position */ 128 #define PM_HIBCFG_BRAMCFG_PARTIAL (PM_HIBCFG_BRAMCFG_PARTIAL_Val << PM_HIBCFG_BRAMCFG_Pos) /* (PM_HIBCFG) Only the first 4Kbytes of the backup RAM is retained Position */ 129 #define PM_HIBCFG_BRAMCFG_OFF (PM_HIBCFG_BRAMCFG_OFF_Val << PM_HIBCFG_BRAMCFG_Pos) /* (PM_HIBCFG) All the backup RAM is turned OFF Position */ 130 #define PM_HIBCFG_Msk _UINT8_(0x0F) /* (PM_HIBCFG) Register Mask */ 131 132 133 /* -------- PM_BKUPCFG : (PM Offset: 0x0A) (R/W 8) Backup Configuration -------- */ 134 #define PM_BKUPCFG_RESETVALUE _UINT8_(0x00) /* (PM_BKUPCFG) Backup Configuration Reset Value */ 135 136 #define PM_BKUPCFG_BRAMCFG_Pos _UINT8_(0) /* (PM_BKUPCFG) Ram Configuration Position */ 137 #define PM_BKUPCFG_BRAMCFG_Msk (_UINT8_(0x3) << PM_BKUPCFG_BRAMCFG_Pos) /* (PM_BKUPCFG) Ram Configuration Mask */ 138 #define PM_BKUPCFG_BRAMCFG(value) (PM_BKUPCFG_BRAMCFG_Msk & (_UINT8_(value) << PM_BKUPCFG_BRAMCFG_Pos)) /* Assignment of value for BRAMCFG in the PM_BKUPCFG register */ 139 #define PM_BKUPCFG_BRAMCFG_RET_Val _UINT8_(0x0) /* (PM_BKUPCFG) All the backup RAM is retained */ 140 #define PM_BKUPCFG_BRAMCFG_PARTIAL_Val _UINT8_(0x1) /* (PM_BKUPCFG) Only the first 4Kbytes of the backup RAM is retained */ 141 #define PM_BKUPCFG_BRAMCFG_OFF_Val _UINT8_(0x2) /* (PM_BKUPCFG) All the backup RAM is turned OFF */ 142 #define PM_BKUPCFG_BRAMCFG_RET (PM_BKUPCFG_BRAMCFG_RET_Val << PM_BKUPCFG_BRAMCFG_Pos) /* (PM_BKUPCFG) All the backup RAM is retained Position */ 143 #define PM_BKUPCFG_BRAMCFG_PARTIAL (PM_BKUPCFG_BRAMCFG_PARTIAL_Val << PM_BKUPCFG_BRAMCFG_Pos) /* (PM_BKUPCFG) Only the first 4Kbytes of the backup RAM is retained Position */ 144 #define PM_BKUPCFG_BRAMCFG_OFF (PM_BKUPCFG_BRAMCFG_OFF_Val << PM_BKUPCFG_BRAMCFG_Pos) /* (PM_BKUPCFG) All the backup RAM is turned OFF Position */ 145 #define PM_BKUPCFG_Msk _UINT8_(0x03) /* (PM_BKUPCFG) Register Mask */ 146 147 148 /* -------- PM_PWSAKDLY : (PM Offset: 0x12) (R/W 8) Power Switch Acknowledge Delay -------- */ 149 #define PM_PWSAKDLY_RESETVALUE _UINT8_(0x00) /* (PM_PWSAKDLY) Power Switch Acknowledge Delay Reset Value */ 150 151 #define PM_PWSAKDLY_DLYVAL_Pos _UINT8_(0) /* (PM_PWSAKDLY) Delay Value Position */ 152 #define PM_PWSAKDLY_DLYVAL_Msk (_UINT8_(0x7F) << PM_PWSAKDLY_DLYVAL_Pos) /* (PM_PWSAKDLY) Delay Value Mask */ 153 #define PM_PWSAKDLY_DLYVAL(value) (PM_PWSAKDLY_DLYVAL_Msk & (_UINT8_(value) << PM_PWSAKDLY_DLYVAL_Pos)) /* Assignment of value for DLYVAL in the PM_PWSAKDLY register */ 154 #define PM_PWSAKDLY_IGNACK_Pos _UINT8_(7) /* (PM_PWSAKDLY) Ignore Acknowledge Position */ 155 #define PM_PWSAKDLY_IGNACK_Msk (_UINT8_(0x1) << PM_PWSAKDLY_IGNACK_Pos) /* (PM_PWSAKDLY) Ignore Acknowledge Mask */ 156 #define PM_PWSAKDLY_IGNACK(value) (PM_PWSAKDLY_IGNACK_Msk & (_UINT8_(value) << PM_PWSAKDLY_IGNACK_Pos)) /* Assignment of value for IGNACK in the PM_PWSAKDLY register */ 157 #define PM_PWSAKDLY_Msk _UINT8_(0xFF) /* (PM_PWSAKDLY) Register Mask */ 158 159 160 /* PM register offsets definitions */ 161 #define PM_CTRLA_REG_OFST _UINT32_(0x00) /* (PM_CTRLA) Control A Offset */ 162 #define PM_SLEEPCFG_REG_OFST _UINT32_(0x01) /* (PM_SLEEPCFG) Sleep Configuration Offset */ 163 #define PM_INTENCLR_REG_OFST _UINT32_(0x04) /* (PM_INTENCLR) Interrupt Enable Clear Offset */ 164 #define PM_INTENSET_REG_OFST _UINT32_(0x05) /* (PM_INTENSET) Interrupt Enable Set Offset */ 165 #define PM_INTFLAG_REG_OFST _UINT32_(0x06) /* (PM_INTFLAG) Interrupt Flag Status and Clear Offset */ 166 #define PM_STDBYCFG_REG_OFST _UINT32_(0x08) /* (PM_STDBYCFG) Standby Configuration Offset */ 167 #define PM_HIBCFG_REG_OFST _UINT32_(0x09) /* (PM_HIBCFG) Hibernate Configuration Offset */ 168 #define PM_BKUPCFG_REG_OFST _UINT32_(0x0A) /* (PM_BKUPCFG) Backup Configuration Offset */ 169 #define PM_PWSAKDLY_REG_OFST _UINT32_(0x12) /* (PM_PWSAKDLY) Power Switch Acknowledge Delay Offset */ 170 171 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 172 /* PM register API structure */ 173 typedef struct 174 { /* Power Manager */ 175 __IO uint8_t PM_CTRLA; /* Offset: 0x00 (R/W 8) Control A */ 176 __IO uint8_t PM_SLEEPCFG; /* Offset: 0x01 (R/W 8) Sleep Configuration */ 177 __I uint8_t Reserved1[0x02]; 178 __IO uint8_t PM_INTENCLR; /* Offset: 0x04 (R/W 8) Interrupt Enable Clear */ 179 __IO uint8_t PM_INTENSET; /* Offset: 0x05 (R/W 8) Interrupt Enable Set */ 180 __IO uint8_t PM_INTFLAG; /* Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ 181 __I uint8_t Reserved2[0x01]; 182 __IO uint8_t PM_STDBYCFG; /* Offset: 0x08 (R/W 8) Standby Configuration */ 183 __IO uint8_t PM_HIBCFG; /* Offset: 0x09 (R/W 8) Hibernate Configuration */ 184 __IO uint8_t PM_BKUPCFG; /* Offset: 0x0A (R/W 8) Backup Configuration */ 185 __I uint8_t Reserved3[0x07]; 186 __IO uint8_t PM_PWSAKDLY; /* Offset: 0x12 (R/W 8) Power Switch Acknowledge Delay */ 187 } pm_registers_t; 188 189 190 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 191 #endif /* _PIC32CXSG41_PM_COMPONENT_H_ */ 192
