1 /* 2 * Component description for OSCCTRL 3 * 4 * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 */ 19 20 /* file generated from device description file (ATDF) version 2023-03-17T09:48:34Z */ 21 #ifndef _PIC32CXSG41_OSCCTRL_COMPONENT_H_ 22 #define _PIC32CXSG41_OSCCTRL_COMPONENT_H_ 23 24 /* ************************************************************************** */ 25 /* SOFTWARE API DEFINITION FOR OSCCTRL */ 26 /* ************************************************************************** */ 27 28 /* -------- OSCCTRL_DPLLCTRLA : (OSCCTRL Offset: 0x00) (R/W 8) DPLL Control A -------- */ 29 #define OSCCTRL_DPLLCTRLA_RESETVALUE _UINT8_(0x80) /* (OSCCTRL_DPLLCTRLA) DPLL Control A Reset Value */ 30 31 #define OSCCTRL_DPLLCTRLA_ENABLE_Pos _UINT8_(1) /* (OSCCTRL_DPLLCTRLA) DPLL Enable Position */ 32 #define OSCCTRL_DPLLCTRLA_ENABLE_Msk (_UINT8_(0x1) << OSCCTRL_DPLLCTRLA_ENABLE_Pos) /* (OSCCTRL_DPLLCTRLA) DPLL Enable Mask */ 33 #define OSCCTRL_DPLLCTRLA_ENABLE(value) (OSCCTRL_DPLLCTRLA_ENABLE_Msk & (_UINT8_(value) << OSCCTRL_DPLLCTRLA_ENABLE_Pos)) /* Assignment of value for ENABLE in the OSCCTRL_DPLLCTRLA register */ 34 #define OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos _UINT8_(6) /* (OSCCTRL_DPLLCTRLA) Run in Standby Position */ 35 #define OSCCTRL_DPLLCTRLA_RUNSTDBY_Msk (_UINT8_(0x1) << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos) /* (OSCCTRL_DPLLCTRLA) Run in Standby Mask */ 36 #define OSCCTRL_DPLLCTRLA_RUNSTDBY(value) (OSCCTRL_DPLLCTRLA_RUNSTDBY_Msk & (_UINT8_(value) << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos)) /* Assignment of value for RUNSTDBY in the OSCCTRL_DPLLCTRLA register */ 37 #define OSCCTRL_DPLLCTRLA_ONDEMAND_Pos _UINT8_(7) /* (OSCCTRL_DPLLCTRLA) On Demand Control Position */ 38 #define OSCCTRL_DPLLCTRLA_ONDEMAND_Msk (_UINT8_(0x1) << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos) /* (OSCCTRL_DPLLCTRLA) On Demand Control Mask */ 39 #define OSCCTRL_DPLLCTRLA_ONDEMAND(value) (OSCCTRL_DPLLCTRLA_ONDEMAND_Msk & (_UINT8_(value) << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos)) /* Assignment of value for ONDEMAND in the OSCCTRL_DPLLCTRLA register */ 40 #define OSCCTRL_DPLLCTRLA_Msk _UINT8_(0xC2) /* (OSCCTRL_DPLLCTRLA) Register Mask */ 41 42 43 /* -------- OSCCTRL_DPLLRATIO : (OSCCTRL Offset: 0x04) (R/W 32) DPLL Ratio Control -------- */ 44 #define OSCCTRL_DPLLRATIO_RESETVALUE _UINT32_(0x00) /* (OSCCTRL_DPLLRATIO) DPLL Ratio Control Reset Value */ 45 46 #define OSCCTRL_DPLLRATIO_LDR_Pos _UINT32_(0) /* (OSCCTRL_DPLLRATIO) Loop Divider Ratio Position */ 47 #define OSCCTRL_DPLLRATIO_LDR_Msk (_UINT32_(0x1FFF) << OSCCTRL_DPLLRATIO_LDR_Pos) /* (OSCCTRL_DPLLRATIO) Loop Divider Ratio Mask */ 48 #define OSCCTRL_DPLLRATIO_LDR(value) (OSCCTRL_DPLLRATIO_LDR_Msk & (_UINT32_(value) << OSCCTRL_DPLLRATIO_LDR_Pos)) /* Assignment of value for LDR in the OSCCTRL_DPLLRATIO register */ 49 #define OSCCTRL_DPLLRATIO_LDRFRAC_Pos _UINT32_(16) /* (OSCCTRL_DPLLRATIO) Loop Divider Ratio Fractional Part Position */ 50 #define OSCCTRL_DPLLRATIO_LDRFRAC_Msk (_UINT32_(0x1F) << OSCCTRL_DPLLRATIO_LDRFRAC_Pos) /* (OSCCTRL_DPLLRATIO) Loop Divider Ratio Fractional Part Mask */ 51 #define OSCCTRL_DPLLRATIO_LDRFRAC(value) (OSCCTRL_DPLLRATIO_LDRFRAC_Msk & (_UINT32_(value) << OSCCTRL_DPLLRATIO_LDRFRAC_Pos)) /* Assignment of value for LDRFRAC in the OSCCTRL_DPLLRATIO register */ 52 #define OSCCTRL_DPLLRATIO_Msk _UINT32_(0x001F1FFF) /* (OSCCTRL_DPLLRATIO) Register Mask */ 53 54 55 /* -------- OSCCTRL_DPLLCTRLB : (OSCCTRL Offset: 0x08) (R/W 32) DPLL Control B -------- */ 56 #define OSCCTRL_DPLLCTRLB_RESETVALUE _UINT32_(0x20) /* (OSCCTRL_DPLLCTRLB) DPLL Control B Reset Value */ 57 58 #define OSCCTRL_DPLLCTRLB_FILTER_Pos _UINT32_(0) /* (OSCCTRL_DPLLCTRLB) Proportional Integral Filter Selection Position */ 59 #define OSCCTRL_DPLLCTRLB_FILTER_Msk (_UINT32_(0xF) << OSCCTRL_DPLLCTRLB_FILTER_Pos) /* (OSCCTRL_DPLLCTRLB) Proportional Integral Filter Selection Mask */ 60 #define OSCCTRL_DPLLCTRLB_FILTER(value) (OSCCTRL_DPLLCTRLB_FILTER_Msk & (_UINT32_(value) << OSCCTRL_DPLLCTRLB_FILTER_Pos)) /* Assignment of value for FILTER in the OSCCTRL_DPLLCTRLB register */ 61 #define OSCCTRL_DPLLCTRLB_FILTER_FILTER1_Val _UINT32_(0x0) /* (OSCCTRL_DPLLCTRLB) Bandwidth = 92.7Khz and Damping Factor = 0.76 */ 62 #define OSCCTRL_DPLLCTRLB_FILTER_FILTER2_Val _UINT32_(0x1) /* (OSCCTRL_DPLLCTRLB) Bandwidth = 131Khz and Damping Factor = 1.08 */ 63 #define OSCCTRL_DPLLCTRLB_FILTER_FILTER3_Val _UINT32_(0x2) /* (OSCCTRL_DPLLCTRLB) Bandwidth = 46.4Khz and Damping Factor = 0.38 */ 64 #define OSCCTRL_DPLLCTRLB_FILTER_FILTER4_Val _UINT32_(0x3) /* (OSCCTRL_DPLLCTRLB) Bandwidth = 65.6Khz and Damping Factor = 0.54 */ 65 #define OSCCTRL_DPLLCTRLB_FILTER_FILTER5_Val _UINT32_(0x4) /* (OSCCTRL_DPLLCTRLB) Bandwidth = 131Khz and Damping Factor = 0.56 */ 66 #define OSCCTRL_DPLLCTRLB_FILTER_FILTER6_Val _UINT32_(0x5) /* (OSCCTRL_DPLLCTRLB) Bandwidth = 185Khz and Damping Factor = 0.79 */ 67 #define OSCCTRL_DPLLCTRLB_FILTER_FILTER7_Val _UINT32_(0x6) /* (OSCCTRL_DPLLCTRLB) Bandwidth = 65.6Khz and Damping Factor = 0.28 */ 68 #define OSCCTRL_DPLLCTRLB_FILTER_FILTER8_Val _UINT32_(0x7) /* (OSCCTRL_DPLLCTRLB) Bandwidth = 92.7Khz and Damping Factor = 0.39 */ 69 #define OSCCTRL_DPLLCTRLB_FILTER_FILTER9_Val _UINT32_(0x8) /* (OSCCTRL_DPLLCTRLB) Bandwidth = 46.4Khz and Damping Factor = 1.49 */ 70 #define OSCCTRL_DPLLCTRLB_FILTER_FILTER10_Val _UINT32_(0x9) /* (OSCCTRL_DPLLCTRLB) Bandwidth = 65.6Khz and Damping Factor = 2.11 */ 71 #define OSCCTRL_DPLLCTRLB_FILTER_FILTER11_Val _UINT32_(0xA) /* (OSCCTRL_DPLLCTRLB) Bandwidth = 23.2Khz and Damping Factor = 0.75 */ 72 #define OSCCTRL_DPLLCTRLB_FILTER_FILTER12_Val _UINT32_(0xB) /* (OSCCTRL_DPLLCTRLB) Bandwidth = 32.8Khz and Damping Factor = 1.06 */ 73 #define OSCCTRL_DPLLCTRLB_FILTER_FILTER13_Val _UINT32_(0xC) /* (OSCCTRL_DPLLCTRLB) Bandwidth = 65.6Khz and Damping Factor = 1.07 */ 74 #define OSCCTRL_DPLLCTRLB_FILTER_FILTER14_Val _UINT32_(0xD) /* (OSCCTRL_DPLLCTRLB) Bandwidth = 92.7Khz and Damping Factor = 1.51 */ 75 #define OSCCTRL_DPLLCTRLB_FILTER_FILTER15_Val _UINT32_(0xE) /* (OSCCTRL_DPLLCTRLB) Bandwidth = 32.8Khz and Damping Factor = 0.53 */ 76 #define OSCCTRL_DPLLCTRLB_FILTER_FILTER16_Val _UINT32_(0xF) /* (OSCCTRL_DPLLCTRLB) Bandwidth = 46.4Khz and Damping Factor = 0.75 */ 77 #define OSCCTRL_DPLLCTRLB_FILTER_FILTER1 (OSCCTRL_DPLLCTRLB_FILTER_FILTER1_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /* (OSCCTRL_DPLLCTRLB) Bandwidth = 92.7Khz and Damping Factor = 0.76 Position */ 78 #define OSCCTRL_DPLLCTRLB_FILTER_FILTER2 (OSCCTRL_DPLLCTRLB_FILTER_FILTER2_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /* (OSCCTRL_DPLLCTRLB) Bandwidth = 131Khz and Damping Factor = 1.08 Position */ 79 #define OSCCTRL_DPLLCTRLB_FILTER_FILTER3 (OSCCTRL_DPLLCTRLB_FILTER_FILTER3_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /* (OSCCTRL_DPLLCTRLB) Bandwidth = 46.4Khz and Damping Factor = 0.38 Position */ 80 #define OSCCTRL_DPLLCTRLB_FILTER_FILTER4 (OSCCTRL_DPLLCTRLB_FILTER_FILTER4_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /* (OSCCTRL_DPLLCTRLB) Bandwidth = 65.6Khz and Damping Factor = 0.54 Position */ 81 #define OSCCTRL_DPLLCTRLB_FILTER_FILTER5 (OSCCTRL_DPLLCTRLB_FILTER_FILTER5_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /* (OSCCTRL_DPLLCTRLB) Bandwidth = 131Khz and Damping Factor = 0.56 Position */ 82 #define OSCCTRL_DPLLCTRLB_FILTER_FILTER6 (OSCCTRL_DPLLCTRLB_FILTER_FILTER6_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /* (OSCCTRL_DPLLCTRLB) Bandwidth = 185Khz and Damping Factor = 0.79 Position */ 83 #define OSCCTRL_DPLLCTRLB_FILTER_FILTER7 (OSCCTRL_DPLLCTRLB_FILTER_FILTER7_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /* (OSCCTRL_DPLLCTRLB) Bandwidth = 65.6Khz and Damping Factor = 0.28 Position */ 84 #define OSCCTRL_DPLLCTRLB_FILTER_FILTER8 (OSCCTRL_DPLLCTRLB_FILTER_FILTER8_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /* (OSCCTRL_DPLLCTRLB) Bandwidth = 92.7Khz and Damping Factor = 0.39 Position */ 85 #define OSCCTRL_DPLLCTRLB_FILTER_FILTER9 (OSCCTRL_DPLLCTRLB_FILTER_FILTER9_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /* (OSCCTRL_DPLLCTRLB) Bandwidth = 46.4Khz and Damping Factor = 1.49 Position */ 86 #define OSCCTRL_DPLLCTRLB_FILTER_FILTER10 (OSCCTRL_DPLLCTRLB_FILTER_FILTER10_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /* (OSCCTRL_DPLLCTRLB) Bandwidth = 65.6Khz and Damping Factor = 2.11 Position */ 87 #define OSCCTRL_DPLLCTRLB_FILTER_FILTER11 (OSCCTRL_DPLLCTRLB_FILTER_FILTER11_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /* (OSCCTRL_DPLLCTRLB) Bandwidth = 23.2Khz and Damping Factor = 0.75 Position */ 88 #define OSCCTRL_DPLLCTRLB_FILTER_FILTER12 (OSCCTRL_DPLLCTRLB_FILTER_FILTER12_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /* (OSCCTRL_DPLLCTRLB) Bandwidth = 32.8Khz and Damping Factor = 1.06 Position */ 89 #define OSCCTRL_DPLLCTRLB_FILTER_FILTER13 (OSCCTRL_DPLLCTRLB_FILTER_FILTER13_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /* (OSCCTRL_DPLLCTRLB) Bandwidth = 65.6Khz and Damping Factor = 1.07 Position */ 90 #define OSCCTRL_DPLLCTRLB_FILTER_FILTER14 (OSCCTRL_DPLLCTRLB_FILTER_FILTER14_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /* (OSCCTRL_DPLLCTRLB) Bandwidth = 92.7Khz and Damping Factor = 1.51 Position */ 91 #define OSCCTRL_DPLLCTRLB_FILTER_FILTER15 (OSCCTRL_DPLLCTRLB_FILTER_FILTER15_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /* (OSCCTRL_DPLLCTRLB) Bandwidth = 32.8Khz and Damping Factor = 0.53 Position */ 92 #define OSCCTRL_DPLLCTRLB_FILTER_FILTER16 (OSCCTRL_DPLLCTRLB_FILTER_FILTER16_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /* (OSCCTRL_DPLLCTRLB) Bandwidth = 46.4Khz and Damping Factor = 0.75 Position */ 93 #define OSCCTRL_DPLLCTRLB_WUF_Pos _UINT32_(4) /* (OSCCTRL_DPLLCTRLB) Wake Up Fast Position */ 94 #define OSCCTRL_DPLLCTRLB_WUF_Msk (_UINT32_(0x1) << OSCCTRL_DPLLCTRLB_WUF_Pos) /* (OSCCTRL_DPLLCTRLB) Wake Up Fast Mask */ 95 #define OSCCTRL_DPLLCTRLB_WUF(value) (OSCCTRL_DPLLCTRLB_WUF_Msk & (_UINT32_(value) << OSCCTRL_DPLLCTRLB_WUF_Pos)) /* Assignment of value for WUF in the OSCCTRL_DPLLCTRLB register */ 96 #define OSCCTRL_DPLLCTRLB_REFCLK_Pos _UINT32_(5) /* (OSCCTRL_DPLLCTRLB) Reference Clock Selection Position */ 97 #define OSCCTRL_DPLLCTRLB_REFCLK_Msk (_UINT32_(0x7) << OSCCTRL_DPLLCTRLB_REFCLK_Pos) /* (OSCCTRL_DPLLCTRLB) Reference Clock Selection Mask */ 98 #define OSCCTRL_DPLLCTRLB_REFCLK(value) (OSCCTRL_DPLLCTRLB_REFCLK_Msk & (_UINT32_(value) << OSCCTRL_DPLLCTRLB_REFCLK_Pos)) /* Assignment of value for REFCLK in the OSCCTRL_DPLLCTRLB register */ 99 #define OSCCTRL_DPLLCTRLB_REFCLK_GCLK_Val _UINT32_(0x0) /* (OSCCTRL_DPLLCTRLB) Dedicated GCLK clock reference */ 100 #define OSCCTRL_DPLLCTRLB_REFCLK_XOSC32_Val _UINT32_(0x1) /* (OSCCTRL_DPLLCTRLB) XOSC32K clock reference */ 101 #define OSCCTRL_DPLLCTRLB_REFCLK_XOSC0_Val _UINT32_(0x2) /* (OSCCTRL_DPLLCTRLB) XOSC0 clock reference */ 102 #define OSCCTRL_DPLLCTRLB_REFCLK_XOSC1_Val _UINT32_(0x3) /* (OSCCTRL_DPLLCTRLB) XOSC1 clock reference */ 103 #define OSCCTRL_DPLLCTRLB_REFCLK_GCLK (OSCCTRL_DPLLCTRLB_REFCLK_GCLK_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos) /* (OSCCTRL_DPLLCTRLB) Dedicated GCLK clock reference Position */ 104 #define OSCCTRL_DPLLCTRLB_REFCLK_XOSC32 (OSCCTRL_DPLLCTRLB_REFCLK_XOSC32_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos) /* (OSCCTRL_DPLLCTRLB) XOSC32K clock reference Position */ 105 #define OSCCTRL_DPLLCTRLB_REFCLK_XOSC0 (OSCCTRL_DPLLCTRLB_REFCLK_XOSC0_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos) /* (OSCCTRL_DPLLCTRLB) XOSC0 clock reference Position */ 106 #define OSCCTRL_DPLLCTRLB_REFCLK_XOSC1 (OSCCTRL_DPLLCTRLB_REFCLK_XOSC1_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos) /* (OSCCTRL_DPLLCTRLB) XOSC1 clock reference Position */ 107 #define OSCCTRL_DPLLCTRLB_LTIME_Pos _UINT32_(8) /* (OSCCTRL_DPLLCTRLB) Lock Time Position */ 108 #define OSCCTRL_DPLLCTRLB_LTIME_Msk (_UINT32_(0x7) << OSCCTRL_DPLLCTRLB_LTIME_Pos) /* (OSCCTRL_DPLLCTRLB) Lock Time Mask */ 109 #define OSCCTRL_DPLLCTRLB_LTIME(value) (OSCCTRL_DPLLCTRLB_LTIME_Msk & (_UINT32_(value) << OSCCTRL_DPLLCTRLB_LTIME_Pos)) /* Assignment of value for LTIME in the OSCCTRL_DPLLCTRLB register */ 110 #define OSCCTRL_DPLLCTRLB_LTIME_DEFAULT_Val _UINT32_(0x0) /* (OSCCTRL_DPLLCTRLB) No time-out. Automatic lock */ 111 #define OSCCTRL_DPLLCTRLB_LTIME_800US_Val _UINT32_(0x4) /* (OSCCTRL_DPLLCTRLB) Time-out if no lock within 800us */ 112 #define OSCCTRL_DPLLCTRLB_LTIME_900US_Val _UINT32_(0x5) /* (OSCCTRL_DPLLCTRLB) Time-out if no lock within 900us */ 113 #define OSCCTRL_DPLLCTRLB_LTIME_1MS_Val _UINT32_(0x6) /* (OSCCTRL_DPLLCTRLB) Time-out if no lock within 1ms */ 114 #define OSCCTRL_DPLLCTRLB_LTIME_1P1MS_Val _UINT32_(0x7) /* (OSCCTRL_DPLLCTRLB) Time-out if no lock within 1.1ms */ 115 #define OSCCTRL_DPLLCTRLB_LTIME_DEFAULT (OSCCTRL_DPLLCTRLB_LTIME_DEFAULT_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos) /* (OSCCTRL_DPLLCTRLB) No time-out. Automatic lock Position */ 116 #define OSCCTRL_DPLLCTRLB_LTIME_800US (OSCCTRL_DPLLCTRLB_LTIME_800US_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos) /* (OSCCTRL_DPLLCTRLB) Time-out if no lock within 800us Position */ 117 #define OSCCTRL_DPLLCTRLB_LTIME_900US (OSCCTRL_DPLLCTRLB_LTIME_900US_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos) /* (OSCCTRL_DPLLCTRLB) Time-out if no lock within 900us Position */ 118 #define OSCCTRL_DPLLCTRLB_LTIME_1MS (OSCCTRL_DPLLCTRLB_LTIME_1MS_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos) /* (OSCCTRL_DPLLCTRLB) Time-out if no lock within 1ms Position */ 119 #define OSCCTRL_DPLLCTRLB_LTIME_1P1MS (OSCCTRL_DPLLCTRLB_LTIME_1P1MS_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos) /* (OSCCTRL_DPLLCTRLB) Time-out if no lock within 1.1ms Position */ 120 #define OSCCTRL_DPLLCTRLB_LBYPASS_Pos _UINT32_(11) /* (OSCCTRL_DPLLCTRLB) Lock Bypass Position */ 121 #define OSCCTRL_DPLLCTRLB_LBYPASS_Msk (_UINT32_(0x1) << OSCCTRL_DPLLCTRLB_LBYPASS_Pos) /* (OSCCTRL_DPLLCTRLB) Lock Bypass Mask */ 122 #define OSCCTRL_DPLLCTRLB_LBYPASS(value) (OSCCTRL_DPLLCTRLB_LBYPASS_Msk & (_UINT32_(value) << OSCCTRL_DPLLCTRLB_LBYPASS_Pos)) /* Assignment of value for LBYPASS in the OSCCTRL_DPLLCTRLB register */ 123 #define OSCCTRL_DPLLCTRLB_DCOFILTER_Pos _UINT32_(12) /* (OSCCTRL_DPLLCTRLB) Sigma-Delta DCO Filter Selection Position */ 124 #define OSCCTRL_DPLLCTRLB_DCOFILTER_Msk (_UINT32_(0x7) << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos) /* (OSCCTRL_DPLLCTRLB) Sigma-Delta DCO Filter Selection Mask */ 125 #define OSCCTRL_DPLLCTRLB_DCOFILTER(value) (OSCCTRL_DPLLCTRLB_DCOFILTER_Msk & (_UINT32_(value) << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos)) /* Assignment of value for DCOFILTER in the OSCCTRL_DPLLCTRLB register */ 126 #define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER1_Val _UINT32_(0x0) /* (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 0.5 and Bandwidth Fn (MHz) = 3.21 */ 127 #define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER2_Val _UINT32_(0x1) /* (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 1 and Bandwidth Fn (MHz) = 1.6 */ 128 #define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER3_Val _UINT32_(0x2) /* (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 1.5 and Bandwidth Fn (MHz) = 1.1 */ 129 #define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER4_Val _UINT32_(0x3) /* (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 2 and Bandwidth Fn (MHz) = 0.8 */ 130 #define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER5_Val _UINT32_(0x4) /* (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 2.5 and Bandwidth Fn (MHz) = 0.64 */ 131 #define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER6_Val _UINT32_(0x5) /* (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 3 and Bandwidth Fn (MHz) = 0.55 */ 132 #define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER7_Val _UINT32_(0x6) /* (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 3.5 and Bandwidth Fn (MHz) = 0.45 */ 133 #define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER8_Val _UINT32_(0x7) /* (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 4 and Bandwidth Fn (MHz) = 0.4 */ 134 #define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER1 (OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER1_Val << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos) /* (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 0.5 and Bandwidth Fn (MHz) = 3.21 Position */ 135 #define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER2 (OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER2_Val << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos) /* (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 1 and Bandwidth Fn (MHz) = 1.6 Position */ 136 #define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER3 (OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER3_Val << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos) /* (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 1.5 and Bandwidth Fn (MHz) = 1.1 Position */ 137 #define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER4 (OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER4_Val << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos) /* (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 2 and Bandwidth Fn (MHz) = 0.8 Position */ 138 #define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER5 (OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER5_Val << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos) /* (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 2.5 and Bandwidth Fn (MHz) = 0.64 Position */ 139 #define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER6 (OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER6_Val << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos) /* (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 3 and Bandwidth Fn (MHz) = 0.55 Position */ 140 #define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER7 (OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER7_Val << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos) /* (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 3.5 and Bandwidth Fn (MHz) = 0.45 Position */ 141 #define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER8 (OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER8_Val << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos) /* (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 4 and Bandwidth Fn (MHz) = 0.4 Position */ 142 #define OSCCTRL_DPLLCTRLB_DCOEN_Pos _UINT32_(15) /* (OSCCTRL_DPLLCTRLB) DCO Filter Enable Position */ 143 #define OSCCTRL_DPLLCTRLB_DCOEN_Msk (_UINT32_(0x1) << OSCCTRL_DPLLCTRLB_DCOEN_Pos) /* (OSCCTRL_DPLLCTRLB) DCO Filter Enable Mask */ 144 #define OSCCTRL_DPLLCTRLB_DCOEN(value) (OSCCTRL_DPLLCTRLB_DCOEN_Msk & (_UINT32_(value) << OSCCTRL_DPLLCTRLB_DCOEN_Pos)) /* Assignment of value for DCOEN in the OSCCTRL_DPLLCTRLB register */ 145 #define OSCCTRL_DPLLCTRLB_DIV_Pos _UINT32_(16) /* (OSCCTRL_DPLLCTRLB) Clock Divider Position */ 146 #define OSCCTRL_DPLLCTRLB_DIV_Msk (_UINT32_(0x7FF) << OSCCTRL_DPLLCTRLB_DIV_Pos) /* (OSCCTRL_DPLLCTRLB) Clock Divider Mask */ 147 #define OSCCTRL_DPLLCTRLB_DIV(value) (OSCCTRL_DPLLCTRLB_DIV_Msk & (_UINT32_(value) << OSCCTRL_DPLLCTRLB_DIV_Pos)) /* Assignment of value for DIV in the OSCCTRL_DPLLCTRLB register */ 148 #define OSCCTRL_DPLLCTRLB_Msk _UINT32_(0x07FFFFFF) /* (OSCCTRL_DPLLCTRLB) Register Mask */ 149 150 151 /* -------- OSCCTRL_DPLLSYNCBUSY : (OSCCTRL Offset: 0x0C) ( R/ 32) DPLL Synchronization Busy -------- */ 152 #define OSCCTRL_DPLLSYNCBUSY_RESETVALUE _UINT32_(0x00) /* (OSCCTRL_DPLLSYNCBUSY) DPLL Synchronization Busy Reset Value */ 153 154 #define OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos _UINT32_(1) /* (OSCCTRL_DPLLSYNCBUSY) DPLL Enable Synchronization Status Position */ 155 #define OSCCTRL_DPLLSYNCBUSY_ENABLE_Msk (_UINT32_(0x1) << OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos) /* (OSCCTRL_DPLLSYNCBUSY) DPLL Enable Synchronization Status Mask */ 156 #define OSCCTRL_DPLLSYNCBUSY_ENABLE(value) (OSCCTRL_DPLLSYNCBUSY_ENABLE_Msk & (_UINT32_(value) << OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos)) /* Assignment of value for ENABLE in the OSCCTRL_DPLLSYNCBUSY register */ 157 #define OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos _UINT32_(2) /* (OSCCTRL_DPLLSYNCBUSY) DPLL Loop Divider Ratio Synchronization Status Position */ 158 #define OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Msk (_UINT32_(0x1) << OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos) /* (OSCCTRL_DPLLSYNCBUSY) DPLL Loop Divider Ratio Synchronization Status Mask */ 159 #define OSCCTRL_DPLLSYNCBUSY_DPLLRATIO(value) (OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Msk & (_UINT32_(value) << OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos)) /* Assignment of value for DPLLRATIO in the OSCCTRL_DPLLSYNCBUSY register */ 160 #define OSCCTRL_DPLLSYNCBUSY_Msk _UINT32_(0x00000006) /* (OSCCTRL_DPLLSYNCBUSY) Register Mask */ 161 162 163 /* -------- OSCCTRL_DPLLSTATUS : (OSCCTRL Offset: 0x10) ( R/ 32) DPLL Status -------- */ 164 #define OSCCTRL_DPLLSTATUS_RESETVALUE _UINT32_(0x00) /* (OSCCTRL_DPLLSTATUS) DPLL Status Reset Value */ 165 166 #define OSCCTRL_DPLLSTATUS_LOCK_Pos _UINT32_(0) /* (OSCCTRL_DPLLSTATUS) DPLL Lock Status Position */ 167 #define OSCCTRL_DPLLSTATUS_LOCK_Msk (_UINT32_(0x1) << OSCCTRL_DPLLSTATUS_LOCK_Pos) /* (OSCCTRL_DPLLSTATUS) DPLL Lock Status Mask */ 168 #define OSCCTRL_DPLLSTATUS_LOCK(value) (OSCCTRL_DPLLSTATUS_LOCK_Msk & (_UINT32_(value) << OSCCTRL_DPLLSTATUS_LOCK_Pos)) /* Assignment of value for LOCK in the OSCCTRL_DPLLSTATUS register */ 169 #define OSCCTRL_DPLLSTATUS_CLKRDY_Pos _UINT32_(1) /* (OSCCTRL_DPLLSTATUS) DPLL Clock Ready Position */ 170 #define OSCCTRL_DPLLSTATUS_CLKRDY_Msk (_UINT32_(0x1) << OSCCTRL_DPLLSTATUS_CLKRDY_Pos) /* (OSCCTRL_DPLLSTATUS) DPLL Clock Ready Mask */ 171 #define OSCCTRL_DPLLSTATUS_CLKRDY(value) (OSCCTRL_DPLLSTATUS_CLKRDY_Msk & (_UINT32_(value) << OSCCTRL_DPLLSTATUS_CLKRDY_Pos)) /* Assignment of value for CLKRDY in the OSCCTRL_DPLLSTATUS register */ 172 #define OSCCTRL_DPLLSTATUS_Msk _UINT32_(0x00000003) /* (OSCCTRL_DPLLSTATUS) Register Mask */ 173 174 175 /* -------- OSCCTRL_EVCTRL : (OSCCTRL Offset: 0x00) (R/W 8) Event Control -------- */ 176 #define OSCCTRL_EVCTRL_RESETVALUE _UINT8_(0x00) /* (OSCCTRL_EVCTRL) Event Control Reset Value */ 177 178 #define OSCCTRL_EVCTRL_CFDEO0_Pos _UINT8_(0) /* (OSCCTRL_EVCTRL) Clock 0 Failure Detector Event Output Enable Position */ 179 #define OSCCTRL_EVCTRL_CFDEO0_Msk (_UINT8_(0x1) << OSCCTRL_EVCTRL_CFDEO0_Pos) /* (OSCCTRL_EVCTRL) Clock 0 Failure Detector Event Output Enable Mask */ 180 #define OSCCTRL_EVCTRL_CFDEO0(value) (OSCCTRL_EVCTRL_CFDEO0_Msk & (_UINT8_(value) << OSCCTRL_EVCTRL_CFDEO0_Pos)) /* Assignment of value for CFDEO0 in the OSCCTRL_EVCTRL register */ 181 #define OSCCTRL_EVCTRL_CFDEO1_Pos _UINT8_(1) /* (OSCCTRL_EVCTRL) Clock 1 Failure Detector Event Output Enable Position */ 182 #define OSCCTRL_EVCTRL_CFDEO1_Msk (_UINT8_(0x1) << OSCCTRL_EVCTRL_CFDEO1_Pos) /* (OSCCTRL_EVCTRL) Clock 1 Failure Detector Event Output Enable Mask */ 183 #define OSCCTRL_EVCTRL_CFDEO1(value) (OSCCTRL_EVCTRL_CFDEO1_Msk & (_UINT8_(value) << OSCCTRL_EVCTRL_CFDEO1_Pos)) /* Assignment of value for CFDEO1 in the OSCCTRL_EVCTRL register */ 184 #define OSCCTRL_EVCTRL_Msk _UINT8_(0x03) /* (OSCCTRL_EVCTRL) Register Mask */ 185 186 #define OSCCTRL_EVCTRL_CFDEO_Pos _UINT8_(0) /* (OSCCTRL_EVCTRL Position) Clock x Failure Detector Event Output Enable */ 187 #define OSCCTRL_EVCTRL_CFDEO_Msk (_UINT8_(0x3) << OSCCTRL_EVCTRL_CFDEO_Pos) /* (OSCCTRL_EVCTRL Mask) CFDEO */ 188 #define OSCCTRL_EVCTRL_CFDEO(value) (OSCCTRL_EVCTRL_CFDEO_Msk & (_UINT8_(value) << OSCCTRL_EVCTRL_CFDEO_Pos)) 189 190 /* -------- OSCCTRL_INTENCLR : (OSCCTRL Offset: 0x04) (R/W 32) Interrupt Enable Clear -------- */ 191 #define OSCCTRL_INTENCLR_RESETVALUE _UINT32_(0x00) /* (OSCCTRL_INTENCLR) Interrupt Enable Clear Reset Value */ 192 193 #define OSCCTRL_INTENCLR_XOSCRDY0_Pos _UINT32_(0) /* (OSCCTRL_INTENCLR) XOSC 0 Ready Interrupt Enable Position */ 194 #define OSCCTRL_INTENCLR_XOSCRDY0_Msk (_UINT32_(0x1) << OSCCTRL_INTENCLR_XOSCRDY0_Pos) /* (OSCCTRL_INTENCLR) XOSC 0 Ready Interrupt Enable Mask */ 195 #define OSCCTRL_INTENCLR_XOSCRDY0(value) (OSCCTRL_INTENCLR_XOSCRDY0_Msk & (_UINT32_(value) << OSCCTRL_INTENCLR_XOSCRDY0_Pos)) /* Assignment of value for XOSCRDY0 in the OSCCTRL_INTENCLR register */ 196 #define OSCCTRL_INTENCLR_XOSCRDY1_Pos _UINT32_(1) /* (OSCCTRL_INTENCLR) XOSC 1 Ready Interrupt Enable Position */ 197 #define OSCCTRL_INTENCLR_XOSCRDY1_Msk (_UINT32_(0x1) << OSCCTRL_INTENCLR_XOSCRDY1_Pos) /* (OSCCTRL_INTENCLR) XOSC 1 Ready Interrupt Enable Mask */ 198 #define OSCCTRL_INTENCLR_XOSCRDY1(value) (OSCCTRL_INTENCLR_XOSCRDY1_Msk & (_UINT32_(value) << OSCCTRL_INTENCLR_XOSCRDY1_Pos)) /* Assignment of value for XOSCRDY1 in the OSCCTRL_INTENCLR register */ 199 #define OSCCTRL_INTENCLR_XOSCFAIL0_Pos _UINT32_(2) /* (OSCCTRL_INTENCLR) XOSC 0 Clock Failure Detector Interrupt Enable Position */ 200 #define OSCCTRL_INTENCLR_XOSCFAIL0_Msk (_UINT32_(0x1) << OSCCTRL_INTENCLR_XOSCFAIL0_Pos) /* (OSCCTRL_INTENCLR) XOSC 0 Clock Failure Detector Interrupt Enable Mask */ 201 #define OSCCTRL_INTENCLR_XOSCFAIL0(value) (OSCCTRL_INTENCLR_XOSCFAIL0_Msk & (_UINT32_(value) << OSCCTRL_INTENCLR_XOSCFAIL0_Pos)) /* Assignment of value for XOSCFAIL0 in the OSCCTRL_INTENCLR register */ 202 #define OSCCTRL_INTENCLR_XOSCFAIL1_Pos _UINT32_(3) /* (OSCCTRL_INTENCLR) XOSC 1 Clock Failure Detector Interrupt Enable Position */ 203 #define OSCCTRL_INTENCLR_XOSCFAIL1_Msk (_UINT32_(0x1) << OSCCTRL_INTENCLR_XOSCFAIL1_Pos) /* (OSCCTRL_INTENCLR) XOSC 1 Clock Failure Detector Interrupt Enable Mask */ 204 #define OSCCTRL_INTENCLR_XOSCFAIL1(value) (OSCCTRL_INTENCLR_XOSCFAIL1_Msk & (_UINT32_(value) << OSCCTRL_INTENCLR_XOSCFAIL1_Pos)) /* Assignment of value for XOSCFAIL1 in the OSCCTRL_INTENCLR register */ 205 #define OSCCTRL_INTENCLR_DFLLRDY_Pos _UINT32_(8) /* (OSCCTRL_INTENCLR) DFLL Ready Interrupt Enable Position */ 206 #define OSCCTRL_INTENCLR_DFLLRDY_Msk (_UINT32_(0x1) << OSCCTRL_INTENCLR_DFLLRDY_Pos) /* (OSCCTRL_INTENCLR) DFLL Ready Interrupt Enable Mask */ 207 #define OSCCTRL_INTENCLR_DFLLRDY(value) (OSCCTRL_INTENCLR_DFLLRDY_Msk & (_UINT32_(value) << OSCCTRL_INTENCLR_DFLLRDY_Pos)) /* Assignment of value for DFLLRDY in the OSCCTRL_INTENCLR register */ 208 #define OSCCTRL_INTENCLR_DFLLOOB_Pos _UINT32_(9) /* (OSCCTRL_INTENCLR) DFLL Out Of Bounds Interrupt Enable Position */ 209 #define OSCCTRL_INTENCLR_DFLLOOB_Msk (_UINT32_(0x1) << OSCCTRL_INTENCLR_DFLLOOB_Pos) /* (OSCCTRL_INTENCLR) DFLL Out Of Bounds Interrupt Enable Mask */ 210 #define OSCCTRL_INTENCLR_DFLLOOB(value) (OSCCTRL_INTENCLR_DFLLOOB_Msk & (_UINT32_(value) << OSCCTRL_INTENCLR_DFLLOOB_Pos)) /* Assignment of value for DFLLOOB in the OSCCTRL_INTENCLR register */ 211 #define OSCCTRL_INTENCLR_DFLLLCKF_Pos _UINT32_(10) /* (OSCCTRL_INTENCLR) DFLL Lock Fine Interrupt Enable Position */ 212 #define OSCCTRL_INTENCLR_DFLLLCKF_Msk (_UINT32_(0x1) << OSCCTRL_INTENCLR_DFLLLCKF_Pos) /* (OSCCTRL_INTENCLR) DFLL Lock Fine Interrupt Enable Mask */ 213 #define OSCCTRL_INTENCLR_DFLLLCKF(value) (OSCCTRL_INTENCLR_DFLLLCKF_Msk & (_UINT32_(value) << OSCCTRL_INTENCLR_DFLLLCKF_Pos)) /* Assignment of value for DFLLLCKF in the OSCCTRL_INTENCLR register */ 214 #define OSCCTRL_INTENCLR_DFLLLCKC_Pos _UINT32_(11) /* (OSCCTRL_INTENCLR) DFLL Lock Coarse Interrupt Enable Position */ 215 #define OSCCTRL_INTENCLR_DFLLLCKC_Msk (_UINT32_(0x1) << OSCCTRL_INTENCLR_DFLLLCKC_Pos) /* (OSCCTRL_INTENCLR) DFLL Lock Coarse Interrupt Enable Mask */ 216 #define OSCCTRL_INTENCLR_DFLLLCKC(value) (OSCCTRL_INTENCLR_DFLLLCKC_Msk & (_UINT32_(value) << OSCCTRL_INTENCLR_DFLLLCKC_Pos)) /* Assignment of value for DFLLLCKC in the OSCCTRL_INTENCLR register */ 217 #define OSCCTRL_INTENCLR_DFLLRCS_Pos _UINT32_(12) /* (OSCCTRL_INTENCLR) DFLL Reference Clock Stopped Interrupt Enable Position */ 218 #define OSCCTRL_INTENCLR_DFLLRCS_Msk (_UINT32_(0x1) << OSCCTRL_INTENCLR_DFLLRCS_Pos) /* (OSCCTRL_INTENCLR) DFLL Reference Clock Stopped Interrupt Enable Mask */ 219 #define OSCCTRL_INTENCLR_DFLLRCS(value) (OSCCTRL_INTENCLR_DFLLRCS_Msk & (_UINT32_(value) << OSCCTRL_INTENCLR_DFLLRCS_Pos)) /* Assignment of value for DFLLRCS in the OSCCTRL_INTENCLR register */ 220 #define OSCCTRL_INTENCLR_DPLL0LCKR_Pos _UINT32_(16) /* (OSCCTRL_INTENCLR) DPLL0 Lock Rise Interrupt Enable Position */ 221 #define OSCCTRL_INTENCLR_DPLL0LCKR_Msk (_UINT32_(0x1) << OSCCTRL_INTENCLR_DPLL0LCKR_Pos) /* (OSCCTRL_INTENCLR) DPLL0 Lock Rise Interrupt Enable Mask */ 222 #define OSCCTRL_INTENCLR_DPLL0LCKR(value) (OSCCTRL_INTENCLR_DPLL0LCKR_Msk & (_UINT32_(value) << OSCCTRL_INTENCLR_DPLL0LCKR_Pos)) /* Assignment of value for DPLL0LCKR in the OSCCTRL_INTENCLR register */ 223 #define OSCCTRL_INTENCLR_DPLL0LCKF_Pos _UINT32_(17) /* (OSCCTRL_INTENCLR) DPLL0 Lock Fall Interrupt Enable Position */ 224 #define OSCCTRL_INTENCLR_DPLL0LCKF_Msk (_UINT32_(0x1) << OSCCTRL_INTENCLR_DPLL0LCKF_Pos) /* (OSCCTRL_INTENCLR) DPLL0 Lock Fall Interrupt Enable Mask */ 225 #define OSCCTRL_INTENCLR_DPLL0LCKF(value) (OSCCTRL_INTENCLR_DPLL0LCKF_Msk & (_UINT32_(value) << OSCCTRL_INTENCLR_DPLL0LCKF_Pos)) /* Assignment of value for DPLL0LCKF in the OSCCTRL_INTENCLR register */ 226 #define OSCCTRL_INTENCLR_DPLL0LTO_Pos _UINT32_(18) /* (OSCCTRL_INTENCLR) DPLL0 Lock Timeout Interrupt Enable Position */ 227 #define OSCCTRL_INTENCLR_DPLL0LTO_Msk (_UINT32_(0x1) << OSCCTRL_INTENCLR_DPLL0LTO_Pos) /* (OSCCTRL_INTENCLR) DPLL0 Lock Timeout Interrupt Enable Mask */ 228 #define OSCCTRL_INTENCLR_DPLL0LTO(value) (OSCCTRL_INTENCLR_DPLL0LTO_Msk & (_UINT32_(value) << OSCCTRL_INTENCLR_DPLL0LTO_Pos)) /* Assignment of value for DPLL0LTO in the OSCCTRL_INTENCLR register */ 229 #define OSCCTRL_INTENCLR_DPLL0LDRTO_Pos _UINT32_(19) /* (OSCCTRL_INTENCLR) DPLL0 Loop Divider Ratio Update Complete Interrupt Enable Position */ 230 #define OSCCTRL_INTENCLR_DPLL0LDRTO_Msk (_UINT32_(0x1) << OSCCTRL_INTENCLR_DPLL0LDRTO_Pos) /* (OSCCTRL_INTENCLR) DPLL0 Loop Divider Ratio Update Complete Interrupt Enable Mask */ 231 #define OSCCTRL_INTENCLR_DPLL0LDRTO(value) (OSCCTRL_INTENCLR_DPLL0LDRTO_Msk & (_UINT32_(value) << OSCCTRL_INTENCLR_DPLL0LDRTO_Pos)) /* Assignment of value for DPLL0LDRTO in the OSCCTRL_INTENCLR register */ 232 #define OSCCTRL_INTENCLR_DPLL1LCKR_Pos _UINT32_(24) /* (OSCCTRL_INTENCLR) DPLL1 Lock Rise Interrupt Enable Position */ 233 #define OSCCTRL_INTENCLR_DPLL1LCKR_Msk (_UINT32_(0x1) << OSCCTRL_INTENCLR_DPLL1LCKR_Pos) /* (OSCCTRL_INTENCLR) DPLL1 Lock Rise Interrupt Enable Mask */ 234 #define OSCCTRL_INTENCLR_DPLL1LCKR(value) (OSCCTRL_INTENCLR_DPLL1LCKR_Msk & (_UINT32_(value) << OSCCTRL_INTENCLR_DPLL1LCKR_Pos)) /* Assignment of value for DPLL1LCKR in the OSCCTRL_INTENCLR register */ 235 #define OSCCTRL_INTENCLR_DPLL1LCKF_Pos _UINT32_(25) /* (OSCCTRL_INTENCLR) DPLL1 Lock Fall Interrupt Enable Position */ 236 #define OSCCTRL_INTENCLR_DPLL1LCKF_Msk (_UINT32_(0x1) << OSCCTRL_INTENCLR_DPLL1LCKF_Pos) /* (OSCCTRL_INTENCLR) DPLL1 Lock Fall Interrupt Enable Mask */ 237 #define OSCCTRL_INTENCLR_DPLL1LCKF(value) (OSCCTRL_INTENCLR_DPLL1LCKF_Msk & (_UINT32_(value) << OSCCTRL_INTENCLR_DPLL1LCKF_Pos)) /* Assignment of value for DPLL1LCKF in the OSCCTRL_INTENCLR register */ 238 #define OSCCTRL_INTENCLR_DPLL1LTO_Pos _UINT32_(26) /* (OSCCTRL_INTENCLR) DPLL1 Lock Timeout Interrupt Enable Position */ 239 #define OSCCTRL_INTENCLR_DPLL1LTO_Msk (_UINT32_(0x1) << OSCCTRL_INTENCLR_DPLL1LTO_Pos) /* (OSCCTRL_INTENCLR) DPLL1 Lock Timeout Interrupt Enable Mask */ 240 #define OSCCTRL_INTENCLR_DPLL1LTO(value) (OSCCTRL_INTENCLR_DPLL1LTO_Msk & (_UINT32_(value) << OSCCTRL_INTENCLR_DPLL1LTO_Pos)) /* Assignment of value for DPLL1LTO in the OSCCTRL_INTENCLR register */ 241 #define OSCCTRL_INTENCLR_DPLL1LDRTO_Pos _UINT32_(27) /* (OSCCTRL_INTENCLR) DPLL1 Loop Divider Ratio Update Complete Interrupt Enable Position */ 242 #define OSCCTRL_INTENCLR_DPLL1LDRTO_Msk (_UINT32_(0x1) << OSCCTRL_INTENCLR_DPLL1LDRTO_Pos) /* (OSCCTRL_INTENCLR) DPLL1 Loop Divider Ratio Update Complete Interrupt Enable Mask */ 243 #define OSCCTRL_INTENCLR_DPLL1LDRTO(value) (OSCCTRL_INTENCLR_DPLL1LDRTO_Msk & (_UINT32_(value) << OSCCTRL_INTENCLR_DPLL1LDRTO_Pos)) /* Assignment of value for DPLL1LDRTO in the OSCCTRL_INTENCLR register */ 244 #define OSCCTRL_INTENCLR_Msk _UINT32_(0x0F0F1F0F) /* (OSCCTRL_INTENCLR) Register Mask */ 245 246 #define OSCCTRL_INTENCLR_XOSCRDY_Pos _UINT32_(0) /* (OSCCTRL_INTENCLR Position) XOSC x Ready Interrupt Enable */ 247 #define OSCCTRL_INTENCLR_XOSCRDY_Msk (_UINT32_(0x3) << OSCCTRL_INTENCLR_XOSCRDY_Pos) /* (OSCCTRL_INTENCLR Mask) XOSCRDY */ 248 #define OSCCTRL_INTENCLR_XOSCRDY(value) (OSCCTRL_INTENCLR_XOSCRDY_Msk & (_UINT32_(value) << OSCCTRL_INTENCLR_XOSCRDY_Pos)) 249 #define OSCCTRL_INTENCLR_XOSCFAIL_Pos _UINT32_(2) /* (OSCCTRL_INTENCLR Position) XOSC x Clock Failure Detector Interrupt Enable */ 250 #define OSCCTRL_INTENCLR_XOSCFAIL_Msk (_UINT32_(0x3) << OSCCTRL_INTENCLR_XOSCFAIL_Pos) /* (OSCCTRL_INTENCLR Mask) XOSCFAIL */ 251 #define OSCCTRL_INTENCLR_XOSCFAIL(value) (OSCCTRL_INTENCLR_XOSCFAIL_Msk & (_UINT32_(value) << OSCCTRL_INTENCLR_XOSCFAIL_Pos)) 252 253 /* -------- OSCCTRL_INTENSET : (OSCCTRL Offset: 0x08) (R/W 32) Interrupt Enable Set -------- */ 254 #define OSCCTRL_INTENSET_RESETVALUE _UINT32_(0x00) /* (OSCCTRL_INTENSET) Interrupt Enable Set Reset Value */ 255 256 #define OSCCTRL_INTENSET_XOSCRDY0_Pos _UINT32_(0) /* (OSCCTRL_INTENSET) XOSC 0 Ready Interrupt Enable Position */ 257 #define OSCCTRL_INTENSET_XOSCRDY0_Msk (_UINT32_(0x1) << OSCCTRL_INTENSET_XOSCRDY0_Pos) /* (OSCCTRL_INTENSET) XOSC 0 Ready Interrupt Enable Mask */ 258 #define OSCCTRL_INTENSET_XOSCRDY0(value) (OSCCTRL_INTENSET_XOSCRDY0_Msk & (_UINT32_(value) << OSCCTRL_INTENSET_XOSCRDY0_Pos)) /* Assignment of value for XOSCRDY0 in the OSCCTRL_INTENSET register */ 259 #define OSCCTRL_INTENSET_XOSCRDY1_Pos _UINT32_(1) /* (OSCCTRL_INTENSET) XOSC 1 Ready Interrupt Enable Position */ 260 #define OSCCTRL_INTENSET_XOSCRDY1_Msk (_UINT32_(0x1) << OSCCTRL_INTENSET_XOSCRDY1_Pos) /* (OSCCTRL_INTENSET) XOSC 1 Ready Interrupt Enable Mask */ 261 #define OSCCTRL_INTENSET_XOSCRDY1(value) (OSCCTRL_INTENSET_XOSCRDY1_Msk & (_UINT32_(value) << OSCCTRL_INTENSET_XOSCRDY1_Pos)) /* Assignment of value for XOSCRDY1 in the OSCCTRL_INTENSET register */ 262 #define OSCCTRL_INTENSET_XOSCFAIL0_Pos _UINT32_(2) /* (OSCCTRL_INTENSET) XOSC 0 Clock Failure Detector Interrupt Enable Position */ 263 #define OSCCTRL_INTENSET_XOSCFAIL0_Msk (_UINT32_(0x1) << OSCCTRL_INTENSET_XOSCFAIL0_Pos) /* (OSCCTRL_INTENSET) XOSC 0 Clock Failure Detector Interrupt Enable Mask */ 264 #define OSCCTRL_INTENSET_XOSCFAIL0(value) (OSCCTRL_INTENSET_XOSCFAIL0_Msk & (_UINT32_(value) << OSCCTRL_INTENSET_XOSCFAIL0_Pos)) /* Assignment of value for XOSCFAIL0 in the OSCCTRL_INTENSET register */ 265 #define OSCCTRL_INTENSET_XOSCFAIL1_Pos _UINT32_(3) /* (OSCCTRL_INTENSET) XOSC 1 Clock Failure Detector Interrupt Enable Position */ 266 #define OSCCTRL_INTENSET_XOSCFAIL1_Msk (_UINT32_(0x1) << OSCCTRL_INTENSET_XOSCFAIL1_Pos) /* (OSCCTRL_INTENSET) XOSC 1 Clock Failure Detector Interrupt Enable Mask */ 267 #define OSCCTRL_INTENSET_XOSCFAIL1(value) (OSCCTRL_INTENSET_XOSCFAIL1_Msk & (_UINT32_(value) << OSCCTRL_INTENSET_XOSCFAIL1_Pos)) /* Assignment of value for XOSCFAIL1 in the OSCCTRL_INTENSET register */ 268 #define OSCCTRL_INTENSET_DFLLRDY_Pos _UINT32_(8) /* (OSCCTRL_INTENSET) DFLL Ready Interrupt Enable Position */ 269 #define OSCCTRL_INTENSET_DFLLRDY_Msk (_UINT32_(0x1) << OSCCTRL_INTENSET_DFLLRDY_Pos) /* (OSCCTRL_INTENSET) DFLL Ready Interrupt Enable Mask */ 270 #define OSCCTRL_INTENSET_DFLLRDY(value) (OSCCTRL_INTENSET_DFLLRDY_Msk & (_UINT32_(value) << OSCCTRL_INTENSET_DFLLRDY_Pos)) /* Assignment of value for DFLLRDY in the OSCCTRL_INTENSET register */ 271 #define OSCCTRL_INTENSET_DFLLOOB_Pos _UINT32_(9) /* (OSCCTRL_INTENSET) DFLL Out Of Bounds Interrupt Enable Position */ 272 #define OSCCTRL_INTENSET_DFLLOOB_Msk (_UINT32_(0x1) << OSCCTRL_INTENSET_DFLLOOB_Pos) /* (OSCCTRL_INTENSET) DFLL Out Of Bounds Interrupt Enable Mask */ 273 #define OSCCTRL_INTENSET_DFLLOOB(value) (OSCCTRL_INTENSET_DFLLOOB_Msk & (_UINT32_(value) << OSCCTRL_INTENSET_DFLLOOB_Pos)) /* Assignment of value for DFLLOOB in the OSCCTRL_INTENSET register */ 274 #define OSCCTRL_INTENSET_DFLLLCKF_Pos _UINT32_(10) /* (OSCCTRL_INTENSET) DFLL Lock Fine Interrupt Enable Position */ 275 #define OSCCTRL_INTENSET_DFLLLCKF_Msk (_UINT32_(0x1) << OSCCTRL_INTENSET_DFLLLCKF_Pos) /* (OSCCTRL_INTENSET) DFLL Lock Fine Interrupt Enable Mask */ 276 #define OSCCTRL_INTENSET_DFLLLCKF(value) (OSCCTRL_INTENSET_DFLLLCKF_Msk & (_UINT32_(value) << OSCCTRL_INTENSET_DFLLLCKF_Pos)) /* Assignment of value for DFLLLCKF in the OSCCTRL_INTENSET register */ 277 #define OSCCTRL_INTENSET_DFLLLCKC_Pos _UINT32_(11) /* (OSCCTRL_INTENSET) DFLL Lock Coarse Interrupt Enable Position */ 278 #define OSCCTRL_INTENSET_DFLLLCKC_Msk (_UINT32_(0x1) << OSCCTRL_INTENSET_DFLLLCKC_Pos) /* (OSCCTRL_INTENSET) DFLL Lock Coarse Interrupt Enable Mask */ 279 #define OSCCTRL_INTENSET_DFLLLCKC(value) (OSCCTRL_INTENSET_DFLLLCKC_Msk & (_UINT32_(value) << OSCCTRL_INTENSET_DFLLLCKC_Pos)) /* Assignment of value for DFLLLCKC in the OSCCTRL_INTENSET register */ 280 #define OSCCTRL_INTENSET_DFLLRCS_Pos _UINT32_(12) /* (OSCCTRL_INTENSET) DFLL Reference Clock Stopped Interrupt Enable Position */ 281 #define OSCCTRL_INTENSET_DFLLRCS_Msk (_UINT32_(0x1) << OSCCTRL_INTENSET_DFLLRCS_Pos) /* (OSCCTRL_INTENSET) DFLL Reference Clock Stopped Interrupt Enable Mask */ 282 #define OSCCTRL_INTENSET_DFLLRCS(value) (OSCCTRL_INTENSET_DFLLRCS_Msk & (_UINT32_(value) << OSCCTRL_INTENSET_DFLLRCS_Pos)) /* Assignment of value for DFLLRCS in the OSCCTRL_INTENSET register */ 283 #define OSCCTRL_INTENSET_DPLL0LCKR_Pos _UINT32_(16) /* (OSCCTRL_INTENSET) DPLL0 Lock Rise Interrupt Enable Position */ 284 #define OSCCTRL_INTENSET_DPLL0LCKR_Msk (_UINT32_(0x1) << OSCCTRL_INTENSET_DPLL0LCKR_Pos) /* (OSCCTRL_INTENSET) DPLL0 Lock Rise Interrupt Enable Mask */ 285 #define OSCCTRL_INTENSET_DPLL0LCKR(value) (OSCCTRL_INTENSET_DPLL0LCKR_Msk & (_UINT32_(value) << OSCCTRL_INTENSET_DPLL0LCKR_Pos)) /* Assignment of value for DPLL0LCKR in the OSCCTRL_INTENSET register */ 286 #define OSCCTRL_INTENSET_DPLL0LCKF_Pos _UINT32_(17) /* (OSCCTRL_INTENSET) DPLL0 Lock Fall Interrupt Enable Position */ 287 #define OSCCTRL_INTENSET_DPLL0LCKF_Msk (_UINT32_(0x1) << OSCCTRL_INTENSET_DPLL0LCKF_Pos) /* (OSCCTRL_INTENSET) DPLL0 Lock Fall Interrupt Enable Mask */ 288 #define OSCCTRL_INTENSET_DPLL0LCKF(value) (OSCCTRL_INTENSET_DPLL0LCKF_Msk & (_UINT32_(value) << OSCCTRL_INTENSET_DPLL0LCKF_Pos)) /* Assignment of value for DPLL0LCKF in the OSCCTRL_INTENSET register */ 289 #define OSCCTRL_INTENSET_DPLL0LTO_Pos _UINT32_(18) /* (OSCCTRL_INTENSET) DPLL0 Lock Timeout Interrupt Enable Position */ 290 #define OSCCTRL_INTENSET_DPLL0LTO_Msk (_UINT32_(0x1) << OSCCTRL_INTENSET_DPLL0LTO_Pos) /* (OSCCTRL_INTENSET) DPLL0 Lock Timeout Interrupt Enable Mask */ 291 #define OSCCTRL_INTENSET_DPLL0LTO(value) (OSCCTRL_INTENSET_DPLL0LTO_Msk & (_UINT32_(value) << OSCCTRL_INTENSET_DPLL0LTO_Pos)) /* Assignment of value for DPLL0LTO in the OSCCTRL_INTENSET register */ 292 #define OSCCTRL_INTENSET_DPLL0LDRTO_Pos _UINT32_(19) /* (OSCCTRL_INTENSET) DPLL0 Loop Divider Ratio Update Complete Interrupt Enable Position */ 293 #define OSCCTRL_INTENSET_DPLL0LDRTO_Msk (_UINT32_(0x1) << OSCCTRL_INTENSET_DPLL0LDRTO_Pos) /* (OSCCTRL_INTENSET) DPLL0 Loop Divider Ratio Update Complete Interrupt Enable Mask */ 294 #define OSCCTRL_INTENSET_DPLL0LDRTO(value) (OSCCTRL_INTENSET_DPLL0LDRTO_Msk & (_UINT32_(value) << OSCCTRL_INTENSET_DPLL0LDRTO_Pos)) /* Assignment of value for DPLL0LDRTO in the OSCCTRL_INTENSET register */ 295 #define OSCCTRL_INTENSET_DPLL1LCKR_Pos _UINT32_(24) /* (OSCCTRL_INTENSET) DPLL1 Lock Rise Interrupt Enable Position */ 296 #define OSCCTRL_INTENSET_DPLL1LCKR_Msk (_UINT32_(0x1) << OSCCTRL_INTENSET_DPLL1LCKR_Pos) /* (OSCCTRL_INTENSET) DPLL1 Lock Rise Interrupt Enable Mask */ 297 #define OSCCTRL_INTENSET_DPLL1LCKR(value) (OSCCTRL_INTENSET_DPLL1LCKR_Msk & (_UINT32_(value) << OSCCTRL_INTENSET_DPLL1LCKR_Pos)) /* Assignment of value for DPLL1LCKR in the OSCCTRL_INTENSET register */ 298 #define OSCCTRL_INTENSET_DPLL1LCKF_Pos _UINT32_(25) /* (OSCCTRL_INTENSET) DPLL1 Lock Fall Interrupt Enable Position */ 299 #define OSCCTRL_INTENSET_DPLL1LCKF_Msk (_UINT32_(0x1) << OSCCTRL_INTENSET_DPLL1LCKF_Pos) /* (OSCCTRL_INTENSET) DPLL1 Lock Fall Interrupt Enable Mask */ 300 #define OSCCTRL_INTENSET_DPLL1LCKF(value) (OSCCTRL_INTENSET_DPLL1LCKF_Msk & (_UINT32_(value) << OSCCTRL_INTENSET_DPLL1LCKF_Pos)) /* Assignment of value for DPLL1LCKF in the OSCCTRL_INTENSET register */ 301 #define OSCCTRL_INTENSET_DPLL1LTO_Pos _UINT32_(26) /* (OSCCTRL_INTENSET) DPLL1 Lock Timeout Interrupt Enable Position */ 302 #define OSCCTRL_INTENSET_DPLL1LTO_Msk (_UINT32_(0x1) << OSCCTRL_INTENSET_DPLL1LTO_Pos) /* (OSCCTRL_INTENSET) DPLL1 Lock Timeout Interrupt Enable Mask */ 303 #define OSCCTRL_INTENSET_DPLL1LTO(value) (OSCCTRL_INTENSET_DPLL1LTO_Msk & (_UINT32_(value) << OSCCTRL_INTENSET_DPLL1LTO_Pos)) /* Assignment of value for DPLL1LTO in the OSCCTRL_INTENSET register */ 304 #define OSCCTRL_INTENSET_DPLL1LDRTO_Pos _UINT32_(27) /* (OSCCTRL_INTENSET) DPLL1 Loop Divider Ratio Update Complete Interrupt Enable Position */ 305 #define OSCCTRL_INTENSET_DPLL1LDRTO_Msk (_UINT32_(0x1) << OSCCTRL_INTENSET_DPLL1LDRTO_Pos) /* (OSCCTRL_INTENSET) DPLL1 Loop Divider Ratio Update Complete Interrupt Enable Mask */ 306 #define OSCCTRL_INTENSET_DPLL1LDRTO(value) (OSCCTRL_INTENSET_DPLL1LDRTO_Msk & (_UINT32_(value) << OSCCTRL_INTENSET_DPLL1LDRTO_Pos)) /* Assignment of value for DPLL1LDRTO in the OSCCTRL_INTENSET register */ 307 #define OSCCTRL_INTENSET_Msk _UINT32_(0x0F0F1F0F) /* (OSCCTRL_INTENSET) Register Mask */ 308 309 #define OSCCTRL_INTENSET_XOSCRDY_Pos _UINT32_(0) /* (OSCCTRL_INTENSET Position) XOSC x Ready Interrupt Enable */ 310 #define OSCCTRL_INTENSET_XOSCRDY_Msk (_UINT32_(0x3) << OSCCTRL_INTENSET_XOSCRDY_Pos) /* (OSCCTRL_INTENSET Mask) XOSCRDY */ 311 #define OSCCTRL_INTENSET_XOSCRDY(value) (OSCCTRL_INTENSET_XOSCRDY_Msk & (_UINT32_(value) << OSCCTRL_INTENSET_XOSCRDY_Pos)) 312 #define OSCCTRL_INTENSET_XOSCFAIL_Pos _UINT32_(2) /* (OSCCTRL_INTENSET Position) XOSC x Clock Failure Detector Interrupt Enable */ 313 #define OSCCTRL_INTENSET_XOSCFAIL_Msk (_UINT32_(0x3) << OSCCTRL_INTENSET_XOSCFAIL_Pos) /* (OSCCTRL_INTENSET Mask) XOSCFAIL */ 314 #define OSCCTRL_INTENSET_XOSCFAIL(value) (OSCCTRL_INTENSET_XOSCFAIL_Msk & (_UINT32_(value) << OSCCTRL_INTENSET_XOSCFAIL_Pos)) 315 316 /* -------- OSCCTRL_INTFLAG : (OSCCTRL Offset: 0x0C) (R/W 32) Interrupt Flag Status and Clear -------- */ 317 #define OSCCTRL_INTFLAG_RESETVALUE _UINT32_(0x00) /* (OSCCTRL_INTFLAG) Interrupt Flag Status and Clear Reset Value */ 318 319 #define OSCCTRL_INTFLAG_XOSCRDY0_Pos _UINT32_(0) /* (OSCCTRL_INTFLAG) XOSC 0 Ready Position */ 320 #define OSCCTRL_INTFLAG_XOSCRDY0_Msk (_UINT32_(0x1) << OSCCTRL_INTFLAG_XOSCRDY0_Pos) /* (OSCCTRL_INTFLAG) XOSC 0 Ready Mask */ 321 #define OSCCTRL_INTFLAG_XOSCRDY0(value) (OSCCTRL_INTFLAG_XOSCRDY0_Msk & (_UINT32_(value) << OSCCTRL_INTFLAG_XOSCRDY0_Pos)) /* Assignment of value for XOSCRDY0 in the OSCCTRL_INTFLAG register */ 322 #define OSCCTRL_INTFLAG_XOSCRDY1_Pos _UINT32_(1) /* (OSCCTRL_INTFLAG) XOSC 1 Ready Position */ 323 #define OSCCTRL_INTFLAG_XOSCRDY1_Msk (_UINT32_(0x1) << OSCCTRL_INTFLAG_XOSCRDY1_Pos) /* (OSCCTRL_INTFLAG) XOSC 1 Ready Mask */ 324 #define OSCCTRL_INTFLAG_XOSCRDY1(value) (OSCCTRL_INTFLAG_XOSCRDY1_Msk & (_UINT32_(value) << OSCCTRL_INTFLAG_XOSCRDY1_Pos)) /* Assignment of value for XOSCRDY1 in the OSCCTRL_INTFLAG register */ 325 #define OSCCTRL_INTFLAG_XOSCFAIL0_Pos _UINT32_(2) /* (OSCCTRL_INTFLAG) XOSC 0 Clock Failure Detector Position */ 326 #define OSCCTRL_INTFLAG_XOSCFAIL0_Msk (_UINT32_(0x1) << OSCCTRL_INTFLAG_XOSCFAIL0_Pos) /* (OSCCTRL_INTFLAG) XOSC 0 Clock Failure Detector Mask */ 327 #define OSCCTRL_INTFLAG_XOSCFAIL0(value) (OSCCTRL_INTFLAG_XOSCFAIL0_Msk & (_UINT32_(value) << OSCCTRL_INTFLAG_XOSCFAIL0_Pos)) /* Assignment of value for XOSCFAIL0 in the OSCCTRL_INTFLAG register */ 328 #define OSCCTRL_INTFLAG_XOSCFAIL1_Pos _UINT32_(3) /* (OSCCTRL_INTFLAG) XOSC 1 Clock Failure Detector Position */ 329 #define OSCCTRL_INTFLAG_XOSCFAIL1_Msk (_UINT32_(0x1) << OSCCTRL_INTFLAG_XOSCFAIL1_Pos) /* (OSCCTRL_INTFLAG) XOSC 1 Clock Failure Detector Mask */ 330 #define OSCCTRL_INTFLAG_XOSCFAIL1(value) (OSCCTRL_INTFLAG_XOSCFAIL1_Msk & (_UINT32_(value) << OSCCTRL_INTFLAG_XOSCFAIL1_Pos)) /* Assignment of value for XOSCFAIL1 in the OSCCTRL_INTFLAG register */ 331 #define OSCCTRL_INTFLAG_DFLLRDY_Pos _UINT32_(8) /* (OSCCTRL_INTFLAG) DFLL Ready Position */ 332 #define OSCCTRL_INTFLAG_DFLLRDY_Msk (_UINT32_(0x1) << OSCCTRL_INTFLAG_DFLLRDY_Pos) /* (OSCCTRL_INTFLAG) DFLL Ready Mask */ 333 #define OSCCTRL_INTFLAG_DFLLRDY(value) (OSCCTRL_INTFLAG_DFLLRDY_Msk & (_UINT32_(value) << OSCCTRL_INTFLAG_DFLLRDY_Pos)) /* Assignment of value for DFLLRDY in the OSCCTRL_INTFLAG register */ 334 #define OSCCTRL_INTFLAG_DFLLOOB_Pos _UINT32_(9) /* (OSCCTRL_INTFLAG) DFLL Out Of Bounds Position */ 335 #define OSCCTRL_INTFLAG_DFLLOOB_Msk (_UINT32_(0x1) << OSCCTRL_INTFLAG_DFLLOOB_Pos) /* (OSCCTRL_INTFLAG) DFLL Out Of Bounds Mask */ 336 #define OSCCTRL_INTFLAG_DFLLOOB(value) (OSCCTRL_INTFLAG_DFLLOOB_Msk & (_UINT32_(value) << OSCCTRL_INTFLAG_DFLLOOB_Pos)) /* Assignment of value for DFLLOOB in the OSCCTRL_INTFLAG register */ 337 #define OSCCTRL_INTFLAG_DFLLLCKF_Pos _UINT32_(10) /* (OSCCTRL_INTFLAG) DFLL Lock Fine Position */ 338 #define OSCCTRL_INTFLAG_DFLLLCKF_Msk (_UINT32_(0x1) << OSCCTRL_INTFLAG_DFLLLCKF_Pos) /* (OSCCTRL_INTFLAG) DFLL Lock Fine Mask */ 339 #define OSCCTRL_INTFLAG_DFLLLCKF(value) (OSCCTRL_INTFLAG_DFLLLCKF_Msk & (_UINT32_(value) << OSCCTRL_INTFLAG_DFLLLCKF_Pos)) /* Assignment of value for DFLLLCKF in the OSCCTRL_INTFLAG register */ 340 #define OSCCTRL_INTFLAG_DFLLLCKC_Pos _UINT32_(11) /* (OSCCTRL_INTFLAG) DFLL Lock Coarse Position */ 341 #define OSCCTRL_INTFLAG_DFLLLCKC_Msk (_UINT32_(0x1) << OSCCTRL_INTFLAG_DFLLLCKC_Pos) /* (OSCCTRL_INTFLAG) DFLL Lock Coarse Mask */ 342 #define OSCCTRL_INTFLAG_DFLLLCKC(value) (OSCCTRL_INTFLAG_DFLLLCKC_Msk & (_UINT32_(value) << OSCCTRL_INTFLAG_DFLLLCKC_Pos)) /* Assignment of value for DFLLLCKC in the OSCCTRL_INTFLAG register */ 343 #define OSCCTRL_INTFLAG_DFLLRCS_Pos _UINT32_(12) /* (OSCCTRL_INTFLAG) DFLL Reference Clock Stopped Position */ 344 #define OSCCTRL_INTFLAG_DFLLRCS_Msk (_UINT32_(0x1) << OSCCTRL_INTFLAG_DFLLRCS_Pos) /* (OSCCTRL_INTFLAG) DFLL Reference Clock Stopped Mask */ 345 #define OSCCTRL_INTFLAG_DFLLRCS(value) (OSCCTRL_INTFLAG_DFLLRCS_Msk & (_UINT32_(value) << OSCCTRL_INTFLAG_DFLLRCS_Pos)) /* Assignment of value for DFLLRCS in the OSCCTRL_INTFLAG register */ 346 #define OSCCTRL_INTFLAG_DPLL0LCKR_Pos _UINT32_(16) /* (OSCCTRL_INTFLAG) DPLL0 Lock Rise Position */ 347 #define OSCCTRL_INTFLAG_DPLL0LCKR_Msk (_UINT32_(0x1) << OSCCTRL_INTFLAG_DPLL0LCKR_Pos) /* (OSCCTRL_INTFLAG) DPLL0 Lock Rise Mask */ 348 #define OSCCTRL_INTFLAG_DPLL0LCKR(value) (OSCCTRL_INTFLAG_DPLL0LCKR_Msk & (_UINT32_(value) << OSCCTRL_INTFLAG_DPLL0LCKR_Pos)) /* Assignment of value for DPLL0LCKR in the OSCCTRL_INTFLAG register */ 349 #define OSCCTRL_INTFLAG_DPLL0LCKF_Pos _UINT32_(17) /* (OSCCTRL_INTFLAG) DPLL0 Lock Fall Position */ 350 #define OSCCTRL_INTFLAG_DPLL0LCKF_Msk (_UINT32_(0x1) << OSCCTRL_INTFLAG_DPLL0LCKF_Pos) /* (OSCCTRL_INTFLAG) DPLL0 Lock Fall Mask */ 351 #define OSCCTRL_INTFLAG_DPLL0LCKF(value) (OSCCTRL_INTFLAG_DPLL0LCKF_Msk & (_UINT32_(value) << OSCCTRL_INTFLAG_DPLL0LCKF_Pos)) /* Assignment of value for DPLL0LCKF in the OSCCTRL_INTFLAG register */ 352 #define OSCCTRL_INTFLAG_DPLL0LTO_Pos _UINT32_(18) /* (OSCCTRL_INTFLAG) DPLL0 Lock Timeout Position */ 353 #define OSCCTRL_INTFLAG_DPLL0LTO_Msk (_UINT32_(0x1) << OSCCTRL_INTFLAG_DPLL0LTO_Pos) /* (OSCCTRL_INTFLAG) DPLL0 Lock Timeout Mask */ 354 #define OSCCTRL_INTFLAG_DPLL0LTO(value) (OSCCTRL_INTFLAG_DPLL0LTO_Msk & (_UINT32_(value) << OSCCTRL_INTFLAG_DPLL0LTO_Pos)) /* Assignment of value for DPLL0LTO in the OSCCTRL_INTFLAG register */ 355 #define OSCCTRL_INTFLAG_DPLL0LDRTO_Pos _UINT32_(19) /* (OSCCTRL_INTFLAG) DPLL0 Loop Divider Ratio Update Complete Position */ 356 #define OSCCTRL_INTFLAG_DPLL0LDRTO_Msk (_UINT32_(0x1) << OSCCTRL_INTFLAG_DPLL0LDRTO_Pos) /* (OSCCTRL_INTFLAG) DPLL0 Loop Divider Ratio Update Complete Mask */ 357 #define OSCCTRL_INTFLAG_DPLL0LDRTO(value) (OSCCTRL_INTFLAG_DPLL0LDRTO_Msk & (_UINT32_(value) << OSCCTRL_INTFLAG_DPLL0LDRTO_Pos)) /* Assignment of value for DPLL0LDRTO in the OSCCTRL_INTFLAG register */ 358 #define OSCCTRL_INTFLAG_DPLL1LCKR_Pos _UINT32_(24) /* (OSCCTRL_INTFLAG) DPLL1 Lock Rise Position */ 359 #define OSCCTRL_INTFLAG_DPLL1LCKR_Msk (_UINT32_(0x1) << OSCCTRL_INTFLAG_DPLL1LCKR_Pos) /* (OSCCTRL_INTFLAG) DPLL1 Lock Rise Mask */ 360 #define OSCCTRL_INTFLAG_DPLL1LCKR(value) (OSCCTRL_INTFLAG_DPLL1LCKR_Msk & (_UINT32_(value) << OSCCTRL_INTFLAG_DPLL1LCKR_Pos)) /* Assignment of value for DPLL1LCKR in the OSCCTRL_INTFLAG register */ 361 #define OSCCTRL_INTFLAG_DPLL1LCKF_Pos _UINT32_(25) /* (OSCCTRL_INTFLAG) DPLL1 Lock Fall Position */ 362 #define OSCCTRL_INTFLAG_DPLL1LCKF_Msk (_UINT32_(0x1) << OSCCTRL_INTFLAG_DPLL1LCKF_Pos) /* (OSCCTRL_INTFLAG) DPLL1 Lock Fall Mask */ 363 #define OSCCTRL_INTFLAG_DPLL1LCKF(value) (OSCCTRL_INTFLAG_DPLL1LCKF_Msk & (_UINT32_(value) << OSCCTRL_INTFLAG_DPLL1LCKF_Pos)) /* Assignment of value for DPLL1LCKF in the OSCCTRL_INTFLAG register */ 364 #define OSCCTRL_INTFLAG_DPLL1LTO_Pos _UINT32_(26) /* (OSCCTRL_INTFLAG) DPLL1 Lock Timeout Position */ 365 #define OSCCTRL_INTFLAG_DPLL1LTO_Msk (_UINT32_(0x1) << OSCCTRL_INTFLAG_DPLL1LTO_Pos) /* (OSCCTRL_INTFLAG) DPLL1 Lock Timeout Mask */ 366 #define OSCCTRL_INTFLAG_DPLL1LTO(value) (OSCCTRL_INTFLAG_DPLL1LTO_Msk & (_UINT32_(value) << OSCCTRL_INTFLAG_DPLL1LTO_Pos)) /* Assignment of value for DPLL1LTO in the OSCCTRL_INTFLAG register */ 367 #define OSCCTRL_INTFLAG_DPLL1LDRTO_Pos _UINT32_(27) /* (OSCCTRL_INTFLAG) DPLL1 Loop Divider Ratio Update Complete Position */ 368 #define OSCCTRL_INTFLAG_DPLL1LDRTO_Msk (_UINT32_(0x1) << OSCCTRL_INTFLAG_DPLL1LDRTO_Pos) /* (OSCCTRL_INTFLAG) DPLL1 Loop Divider Ratio Update Complete Mask */ 369 #define OSCCTRL_INTFLAG_DPLL1LDRTO(value) (OSCCTRL_INTFLAG_DPLL1LDRTO_Msk & (_UINT32_(value) << OSCCTRL_INTFLAG_DPLL1LDRTO_Pos)) /* Assignment of value for DPLL1LDRTO in the OSCCTRL_INTFLAG register */ 370 #define OSCCTRL_INTFLAG_Msk _UINT32_(0x0F0F1F0F) /* (OSCCTRL_INTFLAG) Register Mask */ 371 372 #define OSCCTRL_INTFLAG_XOSCRDY_Pos _UINT32_(0) /* (OSCCTRL_INTFLAG Position) XOSC x Ready */ 373 #define OSCCTRL_INTFLAG_XOSCRDY_Msk (_UINT32_(0x3) << OSCCTRL_INTFLAG_XOSCRDY_Pos) /* (OSCCTRL_INTFLAG Mask) XOSCRDY */ 374 #define OSCCTRL_INTFLAG_XOSCRDY(value) (OSCCTRL_INTFLAG_XOSCRDY_Msk & (_UINT32_(value) << OSCCTRL_INTFLAG_XOSCRDY_Pos)) 375 #define OSCCTRL_INTFLAG_XOSCFAIL_Pos _UINT32_(2) /* (OSCCTRL_INTFLAG Position) XOSC x Clock Failure Detector */ 376 #define OSCCTRL_INTFLAG_XOSCFAIL_Msk (_UINT32_(0x3) << OSCCTRL_INTFLAG_XOSCFAIL_Pos) /* (OSCCTRL_INTFLAG Mask) XOSCFAIL */ 377 #define OSCCTRL_INTFLAG_XOSCFAIL(value) (OSCCTRL_INTFLAG_XOSCFAIL_Msk & (_UINT32_(value) << OSCCTRL_INTFLAG_XOSCFAIL_Pos)) 378 379 /* -------- OSCCTRL_STATUS : (OSCCTRL Offset: 0x10) ( R/ 32) Status -------- */ 380 #define OSCCTRL_STATUS_RESETVALUE _UINT32_(0x00) /* (OSCCTRL_STATUS) Status Reset Value */ 381 382 #define OSCCTRL_STATUS_XOSCRDY0_Pos _UINT32_(0) /* (OSCCTRL_STATUS) XOSC 0 Ready Position */ 383 #define OSCCTRL_STATUS_XOSCRDY0_Msk (_UINT32_(0x1) << OSCCTRL_STATUS_XOSCRDY0_Pos) /* (OSCCTRL_STATUS) XOSC 0 Ready Mask */ 384 #define OSCCTRL_STATUS_XOSCRDY0(value) (OSCCTRL_STATUS_XOSCRDY0_Msk & (_UINT32_(value) << OSCCTRL_STATUS_XOSCRDY0_Pos)) /* Assignment of value for XOSCRDY0 in the OSCCTRL_STATUS register */ 385 #define OSCCTRL_STATUS_XOSCRDY1_Pos _UINT32_(1) /* (OSCCTRL_STATUS) XOSC 1 Ready Position */ 386 #define OSCCTRL_STATUS_XOSCRDY1_Msk (_UINT32_(0x1) << OSCCTRL_STATUS_XOSCRDY1_Pos) /* (OSCCTRL_STATUS) XOSC 1 Ready Mask */ 387 #define OSCCTRL_STATUS_XOSCRDY1(value) (OSCCTRL_STATUS_XOSCRDY1_Msk & (_UINT32_(value) << OSCCTRL_STATUS_XOSCRDY1_Pos)) /* Assignment of value for XOSCRDY1 in the OSCCTRL_STATUS register */ 388 #define OSCCTRL_STATUS_XOSCFAIL0_Pos _UINT32_(2) /* (OSCCTRL_STATUS) XOSC 0 Clock Failure Detector Position */ 389 #define OSCCTRL_STATUS_XOSCFAIL0_Msk (_UINT32_(0x1) << OSCCTRL_STATUS_XOSCFAIL0_Pos) /* (OSCCTRL_STATUS) XOSC 0 Clock Failure Detector Mask */ 390 #define OSCCTRL_STATUS_XOSCFAIL0(value) (OSCCTRL_STATUS_XOSCFAIL0_Msk & (_UINT32_(value) << OSCCTRL_STATUS_XOSCFAIL0_Pos)) /* Assignment of value for XOSCFAIL0 in the OSCCTRL_STATUS register */ 391 #define OSCCTRL_STATUS_XOSCFAIL1_Pos _UINT32_(3) /* (OSCCTRL_STATUS) XOSC 1 Clock Failure Detector Position */ 392 #define OSCCTRL_STATUS_XOSCFAIL1_Msk (_UINT32_(0x1) << OSCCTRL_STATUS_XOSCFAIL1_Pos) /* (OSCCTRL_STATUS) XOSC 1 Clock Failure Detector Mask */ 393 #define OSCCTRL_STATUS_XOSCFAIL1(value) (OSCCTRL_STATUS_XOSCFAIL1_Msk & (_UINT32_(value) << OSCCTRL_STATUS_XOSCFAIL1_Pos)) /* Assignment of value for XOSCFAIL1 in the OSCCTRL_STATUS register */ 394 #define OSCCTRL_STATUS_XOSCCKSW0_Pos _UINT32_(4) /* (OSCCTRL_STATUS) XOSC 0 Clock Switch Position */ 395 #define OSCCTRL_STATUS_XOSCCKSW0_Msk (_UINT32_(0x1) << OSCCTRL_STATUS_XOSCCKSW0_Pos) /* (OSCCTRL_STATUS) XOSC 0 Clock Switch Mask */ 396 #define OSCCTRL_STATUS_XOSCCKSW0(value) (OSCCTRL_STATUS_XOSCCKSW0_Msk & (_UINT32_(value) << OSCCTRL_STATUS_XOSCCKSW0_Pos)) /* Assignment of value for XOSCCKSW0 in the OSCCTRL_STATUS register */ 397 #define OSCCTRL_STATUS_XOSCCKSW1_Pos _UINT32_(5) /* (OSCCTRL_STATUS) XOSC 1 Clock Switch Position */ 398 #define OSCCTRL_STATUS_XOSCCKSW1_Msk (_UINT32_(0x1) << OSCCTRL_STATUS_XOSCCKSW1_Pos) /* (OSCCTRL_STATUS) XOSC 1 Clock Switch Mask */ 399 #define OSCCTRL_STATUS_XOSCCKSW1(value) (OSCCTRL_STATUS_XOSCCKSW1_Msk & (_UINT32_(value) << OSCCTRL_STATUS_XOSCCKSW1_Pos)) /* Assignment of value for XOSCCKSW1 in the OSCCTRL_STATUS register */ 400 #define OSCCTRL_STATUS_DFLLRDY_Pos _UINT32_(8) /* (OSCCTRL_STATUS) DFLL Ready Position */ 401 #define OSCCTRL_STATUS_DFLLRDY_Msk (_UINT32_(0x1) << OSCCTRL_STATUS_DFLLRDY_Pos) /* (OSCCTRL_STATUS) DFLL Ready Mask */ 402 #define OSCCTRL_STATUS_DFLLRDY(value) (OSCCTRL_STATUS_DFLLRDY_Msk & (_UINT32_(value) << OSCCTRL_STATUS_DFLLRDY_Pos)) /* Assignment of value for DFLLRDY in the OSCCTRL_STATUS register */ 403 #define OSCCTRL_STATUS_DFLLOOB_Pos _UINT32_(9) /* (OSCCTRL_STATUS) DFLL Out Of Bounds Position */ 404 #define OSCCTRL_STATUS_DFLLOOB_Msk (_UINT32_(0x1) << OSCCTRL_STATUS_DFLLOOB_Pos) /* (OSCCTRL_STATUS) DFLL Out Of Bounds Mask */ 405 #define OSCCTRL_STATUS_DFLLOOB(value) (OSCCTRL_STATUS_DFLLOOB_Msk & (_UINT32_(value) << OSCCTRL_STATUS_DFLLOOB_Pos)) /* Assignment of value for DFLLOOB in the OSCCTRL_STATUS register */ 406 #define OSCCTRL_STATUS_DFLLLCKF_Pos _UINT32_(10) /* (OSCCTRL_STATUS) DFLL Lock Fine Position */ 407 #define OSCCTRL_STATUS_DFLLLCKF_Msk (_UINT32_(0x1) << OSCCTRL_STATUS_DFLLLCKF_Pos) /* (OSCCTRL_STATUS) DFLL Lock Fine Mask */ 408 #define OSCCTRL_STATUS_DFLLLCKF(value) (OSCCTRL_STATUS_DFLLLCKF_Msk & (_UINT32_(value) << OSCCTRL_STATUS_DFLLLCKF_Pos)) /* Assignment of value for DFLLLCKF in the OSCCTRL_STATUS register */ 409 #define OSCCTRL_STATUS_DFLLLCKC_Pos _UINT32_(11) /* (OSCCTRL_STATUS) DFLL Lock Coarse Position */ 410 #define OSCCTRL_STATUS_DFLLLCKC_Msk (_UINT32_(0x1) << OSCCTRL_STATUS_DFLLLCKC_Pos) /* (OSCCTRL_STATUS) DFLL Lock Coarse Mask */ 411 #define OSCCTRL_STATUS_DFLLLCKC(value) (OSCCTRL_STATUS_DFLLLCKC_Msk & (_UINT32_(value) << OSCCTRL_STATUS_DFLLLCKC_Pos)) /* Assignment of value for DFLLLCKC in the OSCCTRL_STATUS register */ 412 #define OSCCTRL_STATUS_DFLLRCS_Pos _UINT32_(12) /* (OSCCTRL_STATUS) DFLL Reference Clock Stopped Position */ 413 #define OSCCTRL_STATUS_DFLLRCS_Msk (_UINT32_(0x1) << OSCCTRL_STATUS_DFLLRCS_Pos) /* (OSCCTRL_STATUS) DFLL Reference Clock Stopped Mask */ 414 #define OSCCTRL_STATUS_DFLLRCS(value) (OSCCTRL_STATUS_DFLLRCS_Msk & (_UINT32_(value) << OSCCTRL_STATUS_DFLLRCS_Pos)) /* Assignment of value for DFLLRCS in the OSCCTRL_STATUS register */ 415 #define OSCCTRL_STATUS_DPLL0LCKR_Pos _UINT32_(16) /* (OSCCTRL_STATUS) DPLL0 Lock Rise Position */ 416 #define OSCCTRL_STATUS_DPLL0LCKR_Msk (_UINT32_(0x1) << OSCCTRL_STATUS_DPLL0LCKR_Pos) /* (OSCCTRL_STATUS) DPLL0 Lock Rise Mask */ 417 #define OSCCTRL_STATUS_DPLL0LCKR(value) (OSCCTRL_STATUS_DPLL0LCKR_Msk & (_UINT32_(value) << OSCCTRL_STATUS_DPLL0LCKR_Pos)) /* Assignment of value for DPLL0LCKR in the OSCCTRL_STATUS register */ 418 #define OSCCTRL_STATUS_DPLL0LCKF_Pos _UINT32_(17) /* (OSCCTRL_STATUS) DPLL0 Lock Fall Position */ 419 #define OSCCTRL_STATUS_DPLL0LCKF_Msk (_UINT32_(0x1) << OSCCTRL_STATUS_DPLL0LCKF_Pos) /* (OSCCTRL_STATUS) DPLL0 Lock Fall Mask */ 420 #define OSCCTRL_STATUS_DPLL0LCKF(value) (OSCCTRL_STATUS_DPLL0LCKF_Msk & (_UINT32_(value) << OSCCTRL_STATUS_DPLL0LCKF_Pos)) /* Assignment of value for DPLL0LCKF in the OSCCTRL_STATUS register */ 421 #define OSCCTRL_STATUS_DPLL0TO_Pos _UINT32_(18) /* (OSCCTRL_STATUS) DPLL0 Timeout Position */ 422 #define OSCCTRL_STATUS_DPLL0TO_Msk (_UINT32_(0x1) << OSCCTRL_STATUS_DPLL0TO_Pos) /* (OSCCTRL_STATUS) DPLL0 Timeout Mask */ 423 #define OSCCTRL_STATUS_DPLL0TO(value) (OSCCTRL_STATUS_DPLL0TO_Msk & (_UINT32_(value) << OSCCTRL_STATUS_DPLL0TO_Pos)) /* Assignment of value for DPLL0TO in the OSCCTRL_STATUS register */ 424 #define OSCCTRL_STATUS_DPLL1LCKR_Pos _UINT32_(24) /* (OSCCTRL_STATUS) DPLL1 Lock Rise Position */ 425 #define OSCCTRL_STATUS_DPLL1LCKR_Msk (_UINT32_(0x1) << OSCCTRL_STATUS_DPLL1LCKR_Pos) /* (OSCCTRL_STATUS) DPLL1 Lock Rise Mask */ 426 #define OSCCTRL_STATUS_DPLL1LCKR(value) (OSCCTRL_STATUS_DPLL1LCKR_Msk & (_UINT32_(value) << OSCCTRL_STATUS_DPLL1LCKR_Pos)) /* Assignment of value for DPLL1LCKR in the OSCCTRL_STATUS register */ 427 #define OSCCTRL_STATUS_DPLL1LCKF_Pos _UINT32_(25) /* (OSCCTRL_STATUS) DPLL1 Lock Fall Position */ 428 #define OSCCTRL_STATUS_DPLL1LCKF_Msk (_UINT32_(0x1) << OSCCTRL_STATUS_DPLL1LCKF_Pos) /* (OSCCTRL_STATUS) DPLL1 Lock Fall Mask */ 429 #define OSCCTRL_STATUS_DPLL1LCKF(value) (OSCCTRL_STATUS_DPLL1LCKF_Msk & (_UINT32_(value) << OSCCTRL_STATUS_DPLL1LCKF_Pos)) /* Assignment of value for DPLL1LCKF in the OSCCTRL_STATUS register */ 430 #define OSCCTRL_STATUS_DPLL1TO_Pos _UINT32_(26) /* (OSCCTRL_STATUS) DPLL1 Timeout Position */ 431 #define OSCCTRL_STATUS_DPLL1TO_Msk (_UINT32_(0x1) << OSCCTRL_STATUS_DPLL1TO_Pos) /* (OSCCTRL_STATUS) DPLL1 Timeout Mask */ 432 #define OSCCTRL_STATUS_DPLL1TO(value) (OSCCTRL_STATUS_DPLL1TO_Msk & (_UINT32_(value) << OSCCTRL_STATUS_DPLL1TO_Pos)) /* Assignment of value for DPLL1TO in the OSCCTRL_STATUS register */ 433 #define OSCCTRL_STATUS_Msk _UINT32_(0x07071F3F) /* (OSCCTRL_STATUS) Register Mask */ 434 435 #define OSCCTRL_STATUS_XOSCRDY_Pos _UINT32_(0) /* (OSCCTRL_STATUS Position) XOSC x Ready */ 436 #define OSCCTRL_STATUS_XOSCRDY_Msk (_UINT32_(0x3) << OSCCTRL_STATUS_XOSCRDY_Pos) /* (OSCCTRL_STATUS Mask) XOSCRDY */ 437 #define OSCCTRL_STATUS_XOSCRDY(value) (OSCCTRL_STATUS_XOSCRDY_Msk & (_UINT32_(value) << OSCCTRL_STATUS_XOSCRDY_Pos)) 438 #define OSCCTRL_STATUS_XOSCFAIL_Pos _UINT32_(2) /* (OSCCTRL_STATUS Position) XOSC x Clock Failure Detector */ 439 #define OSCCTRL_STATUS_XOSCFAIL_Msk (_UINT32_(0x3) << OSCCTRL_STATUS_XOSCFAIL_Pos) /* (OSCCTRL_STATUS Mask) XOSCFAIL */ 440 #define OSCCTRL_STATUS_XOSCFAIL(value) (OSCCTRL_STATUS_XOSCFAIL_Msk & (_UINT32_(value) << OSCCTRL_STATUS_XOSCFAIL_Pos)) 441 #define OSCCTRL_STATUS_XOSCCKSW_Pos _UINT32_(4) /* (OSCCTRL_STATUS Position) XOSC x Clock Switch */ 442 #define OSCCTRL_STATUS_XOSCCKSW_Msk (_UINT32_(0x3) << OSCCTRL_STATUS_XOSCCKSW_Pos) /* (OSCCTRL_STATUS Mask) XOSCCKSW */ 443 #define OSCCTRL_STATUS_XOSCCKSW(value) (OSCCTRL_STATUS_XOSCCKSW_Msk & (_UINT32_(value) << OSCCTRL_STATUS_XOSCCKSW_Pos)) 444 445 /* -------- OSCCTRL_XOSCCTRL : (OSCCTRL Offset: 0x14) (R/W 32) External Multipurpose Crystal Oscillator Control -------- */ 446 #define OSCCTRL_XOSCCTRL_RESETVALUE _UINT32_(0x80) /* (OSCCTRL_XOSCCTRL) External Multipurpose Crystal Oscillator Control Reset Value */ 447 448 #define OSCCTRL_XOSCCTRL_ENABLE_Pos _UINT32_(1) /* (OSCCTRL_XOSCCTRL) Oscillator Enable Position */ 449 #define OSCCTRL_XOSCCTRL_ENABLE_Msk (_UINT32_(0x1) << OSCCTRL_XOSCCTRL_ENABLE_Pos) /* (OSCCTRL_XOSCCTRL) Oscillator Enable Mask */ 450 #define OSCCTRL_XOSCCTRL_ENABLE(value) (OSCCTRL_XOSCCTRL_ENABLE_Msk & (_UINT32_(value) << OSCCTRL_XOSCCTRL_ENABLE_Pos)) /* Assignment of value for ENABLE in the OSCCTRL_XOSCCTRL register */ 451 #define OSCCTRL_XOSCCTRL_XTALEN_Pos _UINT32_(2) /* (OSCCTRL_XOSCCTRL) Crystal Oscillator Enable Position */ 452 #define OSCCTRL_XOSCCTRL_XTALEN_Msk (_UINT32_(0x1) << OSCCTRL_XOSCCTRL_XTALEN_Pos) /* (OSCCTRL_XOSCCTRL) Crystal Oscillator Enable Mask */ 453 #define OSCCTRL_XOSCCTRL_XTALEN(value) (OSCCTRL_XOSCCTRL_XTALEN_Msk & (_UINT32_(value) << OSCCTRL_XOSCCTRL_XTALEN_Pos)) /* Assignment of value for XTALEN in the OSCCTRL_XOSCCTRL register */ 454 #define OSCCTRL_XOSCCTRL_RUNSTDBY_Pos _UINT32_(6) /* (OSCCTRL_XOSCCTRL) Run in Standby Position */ 455 #define OSCCTRL_XOSCCTRL_RUNSTDBY_Msk (_UINT32_(0x1) << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos) /* (OSCCTRL_XOSCCTRL) Run in Standby Mask */ 456 #define OSCCTRL_XOSCCTRL_RUNSTDBY(value) (OSCCTRL_XOSCCTRL_RUNSTDBY_Msk & (_UINT32_(value) << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos)) /* Assignment of value for RUNSTDBY in the OSCCTRL_XOSCCTRL register */ 457 #define OSCCTRL_XOSCCTRL_ONDEMAND_Pos _UINT32_(7) /* (OSCCTRL_XOSCCTRL) On Demand Control Position */ 458 #define OSCCTRL_XOSCCTRL_ONDEMAND_Msk (_UINT32_(0x1) << OSCCTRL_XOSCCTRL_ONDEMAND_Pos) /* (OSCCTRL_XOSCCTRL) On Demand Control Mask */ 459 #define OSCCTRL_XOSCCTRL_ONDEMAND(value) (OSCCTRL_XOSCCTRL_ONDEMAND_Msk & (_UINT32_(value) << OSCCTRL_XOSCCTRL_ONDEMAND_Pos)) /* Assignment of value for ONDEMAND in the OSCCTRL_XOSCCTRL register */ 460 #define OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos _UINT32_(8) /* (OSCCTRL_XOSCCTRL) Low Buffer Gain Enable Position */ 461 #define OSCCTRL_XOSCCTRL_LOWBUFGAIN_Msk (_UINT32_(0x1) << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos) /* (OSCCTRL_XOSCCTRL) Low Buffer Gain Enable Mask */ 462 #define OSCCTRL_XOSCCTRL_LOWBUFGAIN(value) (OSCCTRL_XOSCCTRL_LOWBUFGAIN_Msk & (_UINT32_(value) << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos)) /* Assignment of value for LOWBUFGAIN in the OSCCTRL_XOSCCTRL register */ 463 #define OSCCTRL_XOSCCTRL_IPTAT_Pos _UINT32_(9) /* (OSCCTRL_XOSCCTRL) Oscillator Current Reference Position */ 464 #define OSCCTRL_XOSCCTRL_IPTAT_Msk (_UINT32_(0x3) << OSCCTRL_XOSCCTRL_IPTAT_Pos) /* (OSCCTRL_XOSCCTRL) Oscillator Current Reference Mask */ 465 #define OSCCTRL_XOSCCTRL_IPTAT(value) (OSCCTRL_XOSCCTRL_IPTAT_Msk & (_UINT32_(value) << OSCCTRL_XOSCCTRL_IPTAT_Pos)) /* Assignment of value for IPTAT in the OSCCTRL_XOSCCTRL register */ 466 #define OSCCTRL_XOSCCTRL_IMULT_Pos _UINT32_(11) /* (OSCCTRL_XOSCCTRL) Oscillator Current Multiplier Position */ 467 #define OSCCTRL_XOSCCTRL_IMULT_Msk (_UINT32_(0xF) << OSCCTRL_XOSCCTRL_IMULT_Pos) /* (OSCCTRL_XOSCCTRL) Oscillator Current Multiplier Mask */ 468 #define OSCCTRL_XOSCCTRL_IMULT(value) (OSCCTRL_XOSCCTRL_IMULT_Msk & (_UINT32_(value) << OSCCTRL_XOSCCTRL_IMULT_Pos)) /* Assignment of value for IMULT in the OSCCTRL_XOSCCTRL register */ 469 #define OSCCTRL_XOSCCTRL_ENALC_Pos _UINT32_(15) /* (OSCCTRL_XOSCCTRL) Automatic Loop Control Enable Position */ 470 #define OSCCTRL_XOSCCTRL_ENALC_Msk (_UINT32_(0x1) << OSCCTRL_XOSCCTRL_ENALC_Pos) /* (OSCCTRL_XOSCCTRL) Automatic Loop Control Enable Mask */ 471 #define OSCCTRL_XOSCCTRL_ENALC(value) (OSCCTRL_XOSCCTRL_ENALC_Msk & (_UINT32_(value) << OSCCTRL_XOSCCTRL_ENALC_Pos)) /* Assignment of value for ENALC in the OSCCTRL_XOSCCTRL register */ 472 #define OSCCTRL_XOSCCTRL_CFDEN_Pos _UINT32_(16) /* (OSCCTRL_XOSCCTRL) Clock Failure Detector Enable Position */ 473 #define OSCCTRL_XOSCCTRL_CFDEN_Msk (_UINT32_(0x1) << OSCCTRL_XOSCCTRL_CFDEN_Pos) /* (OSCCTRL_XOSCCTRL) Clock Failure Detector Enable Mask */ 474 #define OSCCTRL_XOSCCTRL_CFDEN(value) (OSCCTRL_XOSCCTRL_CFDEN_Msk & (_UINT32_(value) << OSCCTRL_XOSCCTRL_CFDEN_Pos)) /* Assignment of value for CFDEN in the OSCCTRL_XOSCCTRL register */ 475 #define OSCCTRL_XOSCCTRL_SWBEN_Pos _UINT32_(17) /* (OSCCTRL_XOSCCTRL) Xosc Clock Switch Enable Position */ 476 #define OSCCTRL_XOSCCTRL_SWBEN_Msk (_UINT32_(0x1) << OSCCTRL_XOSCCTRL_SWBEN_Pos) /* (OSCCTRL_XOSCCTRL) Xosc Clock Switch Enable Mask */ 477 #define OSCCTRL_XOSCCTRL_SWBEN(value) (OSCCTRL_XOSCCTRL_SWBEN_Msk & (_UINT32_(value) << OSCCTRL_XOSCCTRL_SWBEN_Pos)) /* Assignment of value for SWBEN in the OSCCTRL_XOSCCTRL register */ 478 #define OSCCTRL_XOSCCTRL_STARTUP_Pos _UINT32_(20) /* (OSCCTRL_XOSCCTRL) Start-Up Time Position */ 479 #define OSCCTRL_XOSCCTRL_STARTUP_Msk (_UINT32_(0xF) << OSCCTRL_XOSCCTRL_STARTUP_Pos) /* (OSCCTRL_XOSCCTRL) Start-Up Time Mask */ 480 #define OSCCTRL_XOSCCTRL_STARTUP(value) (OSCCTRL_XOSCCTRL_STARTUP_Msk & (_UINT32_(value) << OSCCTRL_XOSCCTRL_STARTUP_Pos)) /* Assignment of value for STARTUP in the OSCCTRL_XOSCCTRL register */ 481 #define OSCCTRL_XOSCCTRL_STARTUP_CYCLE1_Val _UINT32_(0x0) /* (OSCCTRL_XOSCCTRL) 31 us */ 482 #define OSCCTRL_XOSCCTRL_STARTUP_CYCLE2_Val _UINT32_(0x1) /* (OSCCTRL_XOSCCTRL) 61 us */ 483 #define OSCCTRL_XOSCCTRL_STARTUP_CYCLE4_Val _UINT32_(0x2) /* (OSCCTRL_XOSCCTRL) 122 us */ 484 #define OSCCTRL_XOSCCTRL_STARTUP_CYCLE8_Val _UINT32_(0x3) /* (OSCCTRL_XOSCCTRL) 244 us */ 485 #define OSCCTRL_XOSCCTRL_STARTUP_CYCLE16_Val _UINT32_(0x4) /* (OSCCTRL_XOSCCTRL) 488 us */ 486 #define OSCCTRL_XOSCCTRL_STARTUP_CYCLE32_Val _UINT32_(0x5) /* (OSCCTRL_XOSCCTRL) 977 us */ 487 #define OSCCTRL_XOSCCTRL_STARTUP_CYCLE64_Val _UINT32_(0x6) /* (OSCCTRL_XOSCCTRL) 1953 us */ 488 #define OSCCTRL_XOSCCTRL_STARTUP_CYCLE128_Val _UINT32_(0x7) /* (OSCCTRL_XOSCCTRL) 3906 us */ 489 #define OSCCTRL_XOSCCTRL_STARTUP_CYCLE256_Val _UINT32_(0x8) /* (OSCCTRL_XOSCCTRL) 7813 us */ 490 #define OSCCTRL_XOSCCTRL_STARTUP_CYCLE512_Val _UINT32_(0x9) /* (OSCCTRL_XOSCCTRL) 15625 us */ 491 #define OSCCTRL_XOSCCTRL_STARTUP_CYCLE1024_Val _UINT32_(0xA) /* (OSCCTRL_XOSCCTRL) 31250 us */ 492 #define OSCCTRL_XOSCCTRL_STARTUP_CYCLE2048_Val _UINT32_(0xB) /* (OSCCTRL_XOSCCTRL) 62500 us */ 493 #define OSCCTRL_XOSCCTRL_STARTUP_CYCLE4096_Val _UINT32_(0xC) /* (OSCCTRL_XOSCCTRL) 125000 us */ 494 #define OSCCTRL_XOSCCTRL_STARTUP_CYCLE8192_Val _UINT32_(0xD) /* (OSCCTRL_XOSCCTRL) 250000 us */ 495 #define OSCCTRL_XOSCCTRL_STARTUP_CYCLE16384_Val _UINT32_(0xE) /* (OSCCTRL_XOSCCTRL) 500000 us */ 496 #define OSCCTRL_XOSCCTRL_STARTUP_CYCLE32768_Val _UINT32_(0xF) /* (OSCCTRL_XOSCCTRL) 1000000 us */ 497 #define OSCCTRL_XOSCCTRL_STARTUP_CYCLE1 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE1_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /* (OSCCTRL_XOSCCTRL) 31 us Position */ 498 #define OSCCTRL_XOSCCTRL_STARTUP_CYCLE2 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE2_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /* (OSCCTRL_XOSCCTRL) 61 us Position */ 499 #define OSCCTRL_XOSCCTRL_STARTUP_CYCLE4 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE4_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /* (OSCCTRL_XOSCCTRL) 122 us Position */ 500 #define OSCCTRL_XOSCCTRL_STARTUP_CYCLE8 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE8_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /* (OSCCTRL_XOSCCTRL) 244 us Position */ 501 #define OSCCTRL_XOSCCTRL_STARTUP_CYCLE16 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE16_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /* (OSCCTRL_XOSCCTRL) 488 us Position */ 502 #define OSCCTRL_XOSCCTRL_STARTUP_CYCLE32 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE32_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /* (OSCCTRL_XOSCCTRL) 977 us Position */ 503 #define OSCCTRL_XOSCCTRL_STARTUP_CYCLE64 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE64_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /* (OSCCTRL_XOSCCTRL) 1953 us Position */ 504 #define OSCCTRL_XOSCCTRL_STARTUP_CYCLE128 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE128_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /* (OSCCTRL_XOSCCTRL) 3906 us Position */ 505 #define OSCCTRL_XOSCCTRL_STARTUP_CYCLE256 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE256_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /* (OSCCTRL_XOSCCTRL) 7813 us Position */ 506 #define OSCCTRL_XOSCCTRL_STARTUP_CYCLE512 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE512_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /* (OSCCTRL_XOSCCTRL) 15625 us Position */ 507 #define OSCCTRL_XOSCCTRL_STARTUP_CYCLE1024 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE1024_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /* (OSCCTRL_XOSCCTRL) 31250 us Position */ 508 #define OSCCTRL_XOSCCTRL_STARTUP_CYCLE2048 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE2048_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /* (OSCCTRL_XOSCCTRL) 62500 us Position */ 509 #define OSCCTRL_XOSCCTRL_STARTUP_CYCLE4096 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE4096_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /* (OSCCTRL_XOSCCTRL) 125000 us Position */ 510 #define OSCCTRL_XOSCCTRL_STARTUP_CYCLE8192 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE8192_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /* (OSCCTRL_XOSCCTRL) 250000 us Position */ 511 #define OSCCTRL_XOSCCTRL_STARTUP_CYCLE16384 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE16384_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /* (OSCCTRL_XOSCCTRL) 500000 us Position */ 512 #define OSCCTRL_XOSCCTRL_STARTUP_CYCLE32768 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE32768_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /* (OSCCTRL_XOSCCTRL) 1000000 us Position */ 513 #define OSCCTRL_XOSCCTRL_CFDPRESC_Pos _UINT32_(24) /* (OSCCTRL_XOSCCTRL) Clock Failure Detector Prescaler Position */ 514 #define OSCCTRL_XOSCCTRL_CFDPRESC_Msk (_UINT32_(0xF) << OSCCTRL_XOSCCTRL_CFDPRESC_Pos) /* (OSCCTRL_XOSCCTRL) Clock Failure Detector Prescaler Mask */ 515 #define OSCCTRL_XOSCCTRL_CFDPRESC(value) (OSCCTRL_XOSCCTRL_CFDPRESC_Msk & (_UINT32_(value) << OSCCTRL_XOSCCTRL_CFDPRESC_Pos)) /* Assignment of value for CFDPRESC in the OSCCTRL_XOSCCTRL register */ 516 #define OSCCTRL_XOSCCTRL_CFDPRESC_DIV1_Val _UINT32_(0x0) /* (OSCCTRL_XOSCCTRL) 48 MHz */ 517 #define OSCCTRL_XOSCCTRL_CFDPRESC_DIV2_Val _UINT32_(0x1) /* (OSCCTRL_XOSCCTRL) 24 MHz */ 518 #define OSCCTRL_XOSCCTRL_CFDPRESC_DIV4_Val _UINT32_(0x2) /* (OSCCTRL_XOSCCTRL) 12 MHz */ 519 #define OSCCTRL_XOSCCTRL_CFDPRESC_DIV8_Val _UINT32_(0x3) /* (OSCCTRL_XOSCCTRL) 6 MHz */ 520 #define OSCCTRL_XOSCCTRL_CFDPRESC_DIV16_Val _UINT32_(0x4) /* (OSCCTRL_XOSCCTRL) 3 MHz */ 521 #define OSCCTRL_XOSCCTRL_CFDPRESC_DIV32_Val _UINT32_(0x5) /* (OSCCTRL_XOSCCTRL) 1.5 MHz */ 522 #define OSCCTRL_XOSCCTRL_CFDPRESC_DIV64_Val _UINT32_(0x6) /* (OSCCTRL_XOSCCTRL) 0.75 MHz */ 523 #define OSCCTRL_XOSCCTRL_CFDPRESC_DIV128_Val _UINT32_(0x7) /* (OSCCTRL_XOSCCTRL) 0.3125 MHz */ 524 #define OSCCTRL_XOSCCTRL_CFDPRESC_DIV1 (OSCCTRL_XOSCCTRL_CFDPRESC_DIV1_Val << OSCCTRL_XOSCCTRL_CFDPRESC_Pos) /* (OSCCTRL_XOSCCTRL) 48 MHz Position */ 525 #define OSCCTRL_XOSCCTRL_CFDPRESC_DIV2 (OSCCTRL_XOSCCTRL_CFDPRESC_DIV2_Val << OSCCTRL_XOSCCTRL_CFDPRESC_Pos) /* (OSCCTRL_XOSCCTRL) 24 MHz Position */ 526 #define OSCCTRL_XOSCCTRL_CFDPRESC_DIV4 (OSCCTRL_XOSCCTRL_CFDPRESC_DIV4_Val << OSCCTRL_XOSCCTRL_CFDPRESC_Pos) /* (OSCCTRL_XOSCCTRL) 12 MHz Position */ 527 #define OSCCTRL_XOSCCTRL_CFDPRESC_DIV8 (OSCCTRL_XOSCCTRL_CFDPRESC_DIV8_Val << OSCCTRL_XOSCCTRL_CFDPRESC_Pos) /* (OSCCTRL_XOSCCTRL) 6 MHz Position */ 528 #define OSCCTRL_XOSCCTRL_CFDPRESC_DIV16 (OSCCTRL_XOSCCTRL_CFDPRESC_DIV16_Val << OSCCTRL_XOSCCTRL_CFDPRESC_Pos) /* (OSCCTRL_XOSCCTRL) 3 MHz Position */ 529 #define OSCCTRL_XOSCCTRL_CFDPRESC_DIV32 (OSCCTRL_XOSCCTRL_CFDPRESC_DIV32_Val << OSCCTRL_XOSCCTRL_CFDPRESC_Pos) /* (OSCCTRL_XOSCCTRL) 1.5 MHz Position */ 530 #define OSCCTRL_XOSCCTRL_CFDPRESC_DIV64 (OSCCTRL_XOSCCTRL_CFDPRESC_DIV64_Val << OSCCTRL_XOSCCTRL_CFDPRESC_Pos) /* (OSCCTRL_XOSCCTRL) 0.75 MHz Position */ 531 #define OSCCTRL_XOSCCTRL_CFDPRESC_DIV128 (OSCCTRL_XOSCCTRL_CFDPRESC_DIV128_Val << OSCCTRL_XOSCCTRL_CFDPRESC_Pos) /* (OSCCTRL_XOSCCTRL) 0.3125 MHz Position */ 532 #define OSCCTRL_XOSCCTRL_Msk _UINT32_(0x0FF3FFC6) /* (OSCCTRL_XOSCCTRL) Register Mask */ 533 534 535 /* -------- OSCCTRL_DFLLCTRLA : (OSCCTRL Offset: 0x1C) (R/W 8) DFLL48M Control A -------- */ 536 #define OSCCTRL_DFLLCTRLA_RESETVALUE _UINT8_(0x82) /* (OSCCTRL_DFLLCTRLA) DFLL48M Control A Reset Value */ 537 538 #define OSCCTRL_DFLLCTRLA_ENABLE_Pos _UINT8_(1) /* (OSCCTRL_DFLLCTRLA) DFLL Enable Position */ 539 #define OSCCTRL_DFLLCTRLA_ENABLE_Msk (_UINT8_(0x1) << OSCCTRL_DFLLCTRLA_ENABLE_Pos) /* (OSCCTRL_DFLLCTRLA) DFLL Enable Mask */ 540 #define OSCCTRL_DFLLCTRLA_ENABLE(value) (OSCCTRL_DFLLCTRLA_ENABLE_Msk & (_UINT8_(value) << OSCCTRL_DFLLCTRLA_ENABLE_Pos)) /* Assignment of value for ENABLE in the OSCCTRL_DFLLCTRLA register */ 541 #define OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos _UINT8_(6) /* (OSCCTRL_DFLLCTRLA) Run in Standby Position */ 542 #define OSCCTRL_DFLLCTRLA_RUNSTDBY_Msk (_UINT8_(0x1) << OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos) /* (OSCCTRL_DFLLCTRLA) Run in Standby Mask */ 543 #define OSCCTRL_DFLLCTRLA_RUNSTDBY(value) (OSCCTRL_DFLLCTRLA_RUNSTDBY_Msk & (_UINT8_(value) << OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos)) /* Assignment of value for RUNSTDBY in the OSCCTRL_DFLLCTRLA register */ 544 #define OSCCTRL_DFLLCTRLA_ONDEMAND_Pos _UINT8_(7) /* (OSCCTRL_DFLLCTRLA) On Demand Control Position */ 545 #define OSCCTRL_DFLLCTRLA_ONDEMAND_Msk (_UINT8_(0x1) << OSCCTRL_DFLLCTRLA_ONDEMAND_Pos) /* (OSCCTRL_DFLLCTRLA) On Demand Control Mask */ 546 #define OSCCTRL_DFLLCTRLA_ONDEMAND(value) (OSCCTRL_DFLLCTRLA_ONDEMAND_Msk & (_UINT8_(value) << OSCCTRL_DFLLCTRLA_ONDEMAND_Pos)) /* Assignment of value for ONDEMAND in the OSCCTRL_DFLLCTRLA register */ 547 #define OSCCTRL_DFLLCTRLA_Msk _UINT8_(0xC2) /* (OSCCTRL_DFLLCTRLA) Register Mask */ 548 549 550 /* -------- OSCCTRL_DFLLCTRLB : (OSCCTRL Offset: 0x20) (R/W 8) DFLL48M Control B -------- */ 551 #define OSCCTRL_DFLLCTRLB_RESETVALUE _UINT8_(0x00) /* (OSCCTRL_DFLLCTRLB) DFLL48M Control B Reset Value */ 552 553 #define OSCCTRL_DFLLCTRLB_MODE_Pos _UINT8_(0) /* (OSCCTRL_DFLLCTRLB) Operating Mode Selection Position */ 554 #define OSCCTRL_DFLLCTRLB_MODE_Msk (_UINT8_(0x1) << OSCCTRL_DFLLCTRLB_MODE_Pos) /* (OSCCTRL_DFLLCTRLB) Operating Mode Selection Mask */ 555 #define OSCCTRL_DFLLCTRLB_MODE(value) (OSCCTRL_DFLLCTRLB_MODE_Msk & (_UINT8_(value) << OSCCTRL_DFLLCTRLB_MODE_Pos)) /* Assignment of value for MODE in the OSCCTRL_DFLLCTRLB register */ 556 #define OSCCTRL_DFLLCTRLB_STABLE_Pos _UINT8_(1) /* (OSCCTRL_DFLLCTRLB) Stable DFLL Frequency Position */ 557 #define OSCCTRL_DFLLCTRLB_STABLE_Msk (_UINT8_(0x1) << OSCCTRL_DFLLCTRLB_STABLE_Pos) /* (OSCCTRL_DFLLCTRLB) Stable DFLL Frequency Mask */ 558 #define OSCCTRL_DFLLCTRLB_STABLE(value) (OSCCTRL_DFLLCTRLB_STABLE_Msk & (_UINT8_(value) << OSCCTRL_DFLLCTRLB_STABLE_Pos)) /* Assignment of value for STABLE in the OSCCTRL_DFLLCTRLB register */ 559 #define OSCCTRL_DFLLCTRLB_LLAW_Pos _UINT8_(2) /* (OSCCTRL_DFLLCTRLB) Lose Lock After Wake Position */ 560 #define OSCCTRL_DFLLCTRLB_LLAW_Msk (_UINT8_(0x1) << OSCCTRL_DFLLCTRLB_LLAW_Pos) /* (OSCCTRL_DFLLCTRLB) Lose Lock After Wake Mask */ 561 #define OSCCTRL_DFLLCTRLB_LLAW(value) (OSCCTRL_DFLLCTRLB_LLAW_Msk & (_UINT8_(value) << OSCCTRL_DFLLCTRLB_LLAW_Pos)) /* Assignment of value for LLAW in the OSCCTRL_DFLLCTRLB register */ 562 #define OSCCTRL_DFLLCTRLB_USBCRM_Pos _UINT8_(3) /* (OSCCTRL_DFLLCTRLB) USB Clock Recovery Mode Position */ 563 #define OSCCTRL_DFLLCTRLB_USBCRM_Msk (_UINT8_(0x1) << OSCCTRL_DFLLCTRLB_USBCRM_Pos) /* (OSCCTRL_DFLLCTRLB) USB Clock Recovery Mode Mask */ 564 #define OSCCTRL_DFLLCTRLB_USBCRM(value) (OSCCTRL_DFLLCTRLB_USBCRM_Msk & (_UINT8_(value) << OSCCTRL_DFLLCTRLB_USBCRM_Pos)) /* Assignment of value for USBCRM in the OSCCTRL_DFLLCTRLB register */ 565 #define OSCCTRL_DFLLCTRLB_CCDIS_Pos _UINT8_(4) /* (OSCCTRL_DFLLCTRLB) Chill Cycle Disable Position */ 566 #define OSCCTRL_DFLLCTRLB_CCDIS_Msk (_UINT8_(0x1) << OSCCTRL_DFLLCTRLB_CCDIS_Pos) /* (OSCCTRL_DFLLCTRLB) Chill Cycle Disable Mask */ 567 #define OSCCTRL_DFLLCTRLB_CCDIS(value) (OSCCTRL_DFLLCTRLB_CCDIS_Msk & (_UINT8_(value) << OSCCTRL_DFLLCTRLB_CCDIS_Pos)) /* Assignment of value for CCDIS in the OSCCTRL_DFLLCTRLB register */ 568 #define OSCCTRL_DFLLCTRLB_QLDIS_Pos _UINT8_(5) /* (OSCCTRL_DFLLCTRLB) Quick Lock Disable Position */ 569 #define OSCCTRL_DFLLCTRLB_QLDIS_Msk (_UINT8_(0x1) << OSCCTRL_DFLLCTRLB_QLDIS_Pos) /* (OSCCTRL_DFLLCTRLB) Quick Lock Disable Mask */ 570 #define OSCCTRL_DFLLCTRLB_QLDIS(value) (OSCCTRL_DFLLCTRLB_QLDIS_Msk & (_UINT8_(value) << OSCCTRL_DFLLCTRLB_QLDIS_Pos)) /* Assignment of value for QLDIS in the OSCCTRL_DFLLCTRLB register */ 571 #define OSCCTRL_DFLLCTRLB_BPLCKC_Pos _UINT8_(6) /* (OSCCTRL_DFLLCTRLB) Bypass Coarse Lock Position */ 572 #define OSCCTRL_DFLLCTRLB_BPLCKC_Msk (_UINT8_(0x1) << OSCCTRL_DFLLCTRLB_BPLCKC_Pos) /* (OSCCTRL_DFLLCTRLB) Bypass Coarse Lock Mask */ 573 #define OSCCTRL_DFLLCTRLB_BPLCKC(value) (OSCCTRL_DFLLCTRLB_BPLCKC_Msk & (_UINT8_(value) << OSCCTRL_DFLLCTRLB_BPLCKC_Pos)) /* Assignment of value for BPLCKC in the OSCCTRL_DFLLCTRLB register */ 574 #define OSCCTRL_DFLLCTRLB_WAITLOCK_Pos _UINT8_(7) /* (OSCCTRL_DFLLCTRLB) Wait Lock Position */ 575 #define OSCCTRL_DFLLCTRLB_WAITLOCK_Msk (_UINT8_(0x1) << OSCCTRL_DFLLCTRLB_WAITLOCK_Pos) /* (OSCCTRL_DFLLCTRLB) Wait Lock Mask */ 576 #define OSCCTRL_DFLLCTRLB_WAITLOCK(value) (OSCCTRL_DFLLCTRLB_WAITLOCK_Msk & (_UINT8_(value) << OSCCTRL_DFLLCTRLB_WAITLOCK_Pos)) /* Assignment of value for WAITLOCK in the OSCCTRL_DFLLCTRLB register */ 577 #define OSCCTRL_DFLLCTRLB_Msk _UINT8_(0xFF) /* (OSCCTRL_DFLLCTRLB) Register Mask */ 578 579 580 /* -------- OSCCTRL_DFLLVAL : (OSCCTRL Offset: 0x24) (R/W 32) DFLL48M Value -------- */ 581 #define OSCCTRL_DFLLVAL_RESETVALUE _UINT32_(0x00) /* (OSCCTRL_DFLLVAL) DFLL48M Value Reset Value */ 582 583 #define OSCCTRL_DFLLVAL_FINE_Pos _UINT32_(0) /* (OSCCTRL_DFLLVAL) Fine Value Position */ 584 #define OSCCTRL_DFLLVAL_FINE_Msk (_UINT32_(0xFF) << OSCCTRL_DFLLVAL_FINE_Pos) /* (OSCCTRL_DFLLVAL) Fine Value Mask */ 585 #define OSCCTRL_DFLLVAL_FINE(value) (OSCCTRL_DFLLVAL_FINE_Msk & (_UINT32_(value) << OSCCTRL_DFLLVAL_FINE_Pos)) /* Assignment of value for FINE in the OSCCTRL_DFLLVAL register */ 586 #define OSCCTRL_DFLLVAL_COARSE_Pos _UINT32_(10) /* (OSCCTRL_DFLLVAL) Coarse Value Position */ 587 #define OSCCTRL_DFLLVAL_COARSE_Msk (_UINT32_(0x3F) << OSCCTRL_DFLLVAL_COARSE_Pos) /* (OSCCTRL_DFLLVAL) Coarse Value Mask */ 588 #define OSCCTRL_DFLLVAL_COARSE(value) (OSCCTRL_DFLLVAL_COARSE_Msk & (_UINT32_(value) << OSCCTRL_DFLLVAL_COARSE_Pos)) /* Assignment of value for COARSE in the OSCCTRL_DFLLVAL register */ 589 #define OSCCTRL_DFLLVAL_DIFF_Pos _UINT32_(16) /* (OSCCTRL_DFLLVAL) Multiplication Ratio Difference Position */ 590 #define OSCCTRL_DFLLVAL_DIFF_Msk (_UINT32_(0xFFFF) << OSCCTRL_DFLLVAL_DIFF_Pos) /* (OSCCTRL_DFLLVAL) Multiplication Ratio Difference Mask */ 591 #define OSCCTRL_DFLLVAL_DIFF(value) (OSCCTRL_DFLLVAL_DIFF_Msk & (_UINT32_(value) << OSCCTRL_DFLLVAL_DIFF_Pos)) /* Assignment of value for DIFF in the OSCCTRL_DFLLVAL register */ 592 #define OSCCTRL_DFLLVAL_Msk _UINT32_(0xFFFFFCFF) /* (OSCCTRL_DFLLVAL) Register Mask */ 593 594 595 /* -------- OSCCTRL_DFLLMUL : (OSCCTRL Offset: 0x28) (R/W 32) DFLL48M Multiplier -------- */ 596 #define OSCCTRL_DFLLMUL_RESETVALUE _UINT32_(0x00) /* (OSCCTRL_DFLLMUL) DFLL48M Multiplier Reset Value */ 597 598 #define OSCCTRL_DFLLMUL_MUL_Pos _UINT32_(0) /* (OSCCTRL_DFLLMUL) DFLL Multiply Factor Position */ 599 #define OSCCTRL_DFLLMUL_MUL_Msk (_UINT32_(0xFFFF) << OSCCTRL_DFLLMUL_MUL_Pos) /* (OSCCTRL_DFLLMUL) DFLL Multiply Factor Mask */ 600 #define OSCCTRL_DFLLMUL_MUL(value) (OSCCTRL_DFLLMUL_MUL_Msk & (_UINT32_(value) << OSCCTRL_DFLLMUL_MUL_Pos)) /* Assignment of value for MUL in the OSCCTRL_DFLLMUL register */ 601 #define OSCCTRL_DFLLMUL_FSTEP_Pos _UINT32_(16) /* (OSCCTRL_DFLLMUL) Fine Maximum Step Position */ 602 #define OSCCTRL_DFLLMUL_FSTEP_Msk (_UINT32_(0xFF) << OSCCTRL_DFLLMUL_FSTEP_Pos) /* (OSCCTRL_DFLLMUL) Fine Maximum Step Mask */ 603 #define OSCCTRL_DFLLMUL_FSTEP(value) (OSCCTRL_DFLLMUL_FSTEP_Msk & (_UINT32_(value) << OSCCTRL_DFLLMUL_FSTEP_Pos)) /* Assignment of value for FSTEP in the OSCCTRL_DFLLMUL register */ 604 #define OSCCTRL_DFLLMUL_CSTEP_Pos _UINT32_(26) /* (OSCCTRL_DFLLMUL) Coarse Maximum Step Position */ 605 #define OSCCTRL_DFLLMUL_CSTEP_Msk (_UINT32_(0x3F) << OSCCTRL_DFLLMUL_CSTEP_Pos) /* (OSCCTRL_DFLLMUL) Coarse Maximum Step Mask */ 606 #define OSCCTRL_DFLLMUL_CSTEP(value) (OSCCTRL_DFLLMUL_CSTEP_Msk & (_UINT32_(value) << OSCCTRL_DFLLMUL_CSTEP_Pos)) /* Assignment of value for CSTEP in the OSCCTRL_DFLLMUL register */ 607 #define OSCCTRL_DFLLMUL_Msk _UINT32_(0xFCFFFFFF) /* (OSCCTRL_DFLLMUL) Register Mask */ 608 609 610 /* -------- OSCCTRL_DFLLSYNC : (OSCCTRL Offset: 0x2C) (R/W 8) DFLL48M Synchronization -------- */ 611 #define OSCCTRL_DFLLSYNC_RESETVALUE _UINT8_(0x00) /* (OSCCTRL_DFLLSYNC) DFLL48M Synchronization Reset Value */ 612 613 #define OSCCTRL_DFLLSYNC_ENABLE_Pos _UINT8_(1) /* (OSCCTRL_DFLLSYNC) ENABLE Synchronization Busy Position */ 614 #define OSCCTRL_DFLLSYNC_ENABLE_Msk (_UINT8_(0x1) << OSCCTRL_DFLLSYNC_ENABLE_Pos) /* (OSCCTRL_DFLLSYNC) ENABLE Synchronization Busy Mask */ 615 #define OSCCTRL_DFLLSYNC_ENABLE(value) (OSCCTRL_DFLLSYNC_ENABLE_Msk & (_UINT8_(value) << OSCCTRL_DFLLSYNC_ENABLE_Pos)) /* Assignment of value for ENABLE in the OSCCTRL_DFLLSYNC register */ 616 #define OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos _UINT8_(2) /* (OSCCTRL_DFLLSYNC) DFLLCTRLB Synchronization Busy Position */ 617 #define OSCCTRL_DFLLSYNC_DFLLCTRLB_Msk (_UINT8_(0x1) << OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos) /* (OSCCTRL_DFLLSYNC) DFLLCTRLB Synchronization Busy Mask */ 618 #define OSCCTRL_DFLLSYNC_DFLLCTRLB(value) (OSCCTRL_DFLLSYNC_DFLLCTRLB_Msk & (_UINT8_(value) << OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos)) /* Assignment of value for DFLLCTRLB in the OSCCTRL_DFLLSYNC register */ 619 #define OSCCTRL_DFLLSYNC_DFLLVAL_Pos _UINT8_(3) /* (OSCCTRL_DFLLSYNC) DFLLVAL Synchronization Busy Position */ 620 #define OSCCTRL_DFLLSYNC_DFLLVAL_Msk (_UINT8_(0x1) << OSCCTRL_DFLLSYNC_DFLLVAL_Pos) /* (OSCCTRL_DFLLSYNC) DFLLVAL Synchronization Busy Mask */ 621 #define OSCCTRL_DFLLSYNC_DFLLVAL(value) (OSCCTRL_DFLLSYNC_DFLLVAL_Msk & (_UINT8_(value) << OSCCTRL_DFLLSYNC_DFLLVAL_Pos)) /* Assignment of value for DFLLVAL in the OSCCTRL_DFLLSYNC register */ 622 #define OSCCTRL_DFLLSYNC_DFLLMUL_Pos _UINT8_(4) /* (OSCCTRL_DFLLSYNC) DFLLMUL Synchronization Busy Position */ 623 #define OSCCTRL_DFLLSYNC_DFLLMUL_Msk (_UINT8_(0x1) << OSCCTRL_DFLLSYNC_DFLLMUL_Pos) /* (OSCCTRL_DFLLSYNC) DFLLMUL Synchronization Busy Mask */ 624 #define OSCCTRL_DFLLSYNC_DFLLMUL(value) (OSCCTRL_DFLLSYNC_DFLLMUL_Msk & (_UINT8_(value) << OSCCTRL_DFLLSYNC_DFLLMUL_Pos)) /* Assignment of value for DFLLMUL in the OSCCTRL_DFLLSYNC register */ 625 #define OSCCTRL_DFLLSYNC_Msk _UINT8_(0x1E) /* (OSCCTRL_DFLLSYNC) Register Mask */ 626 627 628 /* OSCCTRL register offsets definitions */ 629 #define OSCCTRL_DPLLCTRLA_REG_OFST _UINT32_(0x00) /* (OSCCTRL_DPLLCTRLA) DPLL Control A Offset */ 630 #define OSCCTRL_DPLLRATIO_REG_OFST _UINT32_(0x04) /* (OSCCTRL_DPLLRATIO) DPLL Ratio Control Offset */ 631 #define OSCCTRL_DPLLCTRLB_REG_OFST _UINT32_(0x08) /* (OSCCTRL_DPLLCTRLB) DPLL Control B Offset */ 632 #define OSCCTRL_DPLLSYNCBUSY_REG_OFST _UINT32_(0x0C) /* (OSCCTRL_DPLLSYNCBUSY) DPLL Synchronization Busy Offset */ 633 #define OSCCTRL_DPLLSTATUS_REG_OFST _UINT32_(0x10) /* (OSCCTRL_DPLLSTATUS) DPLL Status Offset */ 634 #define OSCCTRL_EVCTRL_REG_OFST _UINT32_(0x00) /* (OSCCTRL_EVCTRL) Event Control Offset */ 635 #define OSCCTRL_INTENCLR_REG_OFST _UINT32_(0x04) /* (OSCCTRL_INTENCLR) Interrupt Enable Clear Offset */ 636 #define OSCCTRL_INTENSET_REG_OFST _UINT32_(0x08) /* (OSCCTRL_INTENSET) Interrupt Enable Set Offset */ 637 #define OSCCTRL_INTFLAG_REG_OFST _UINT32_(0x0C) /* (OSCCTRL_INTFLAG) Interrupt Flag Status and Clear Offset */ 638 #define OSCCTRL_STATUS_REG_OFST _UINT32_(0x10) /* (OSCCTRL_STATUS) Status Offset */ 639 #define OSCCTRL_XOSCCTRL_REG_OFST _UINT32_(0x14) /* (OSCCTRL_XOSCCTRL) External Multipurpose Crystal Oscillator Control Offset */ 640 #define OSCCTRL_XOSCCTRL0_REG_OFST _UINT32_(0x14) /* (OSCCTRL_XOSCCTRL0) External Multipurpose Crystal Oscillator Control Offset */ 641 #define OSCCTRL_XOSCCTRL1_REG_OFST _UINT32_(0x18) /* (OSCCTRL_XOSCCTRL1) External Multipurpose Crystal Oscillator Control Offset */ 642 #define OSCCTRL_DFLLCTRLA_REG_OFST _UINT32_(0x1C) /* (OSCCTRL_DFLLCTRLA) DFLL48M Control A Offset */ 643 #define OSCCTRL_DFLLCTRLB_REG_OFST _UINT32_(0x20) /* (OSCCTRL_DFLLCTRLB) DFLL48M Control B Offset */ 644 #define OSCCTRL_DFLLVAL_REG_OFST _UINT32_(0x24) /* (OSCCTRL_DFLLVAL) DFLL48M Value Offset */ 645 #define OSCCTRL_DFLLMUL_REG_OFST _UINT32_(0x28) /* (OSCCTRL_DFLLMUL) DFLL48M Multiplier Offset */ 646 #define OSCCTRL_DFLLSYNC_REG_OFST _UINT32_(0x2C) /* (OSCCTRL_DFLLSYNC) DFLL48M Synchronization Offset */ 647 648 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 649 /* DPLL register API structure */ 650 typedef struct 651 { 652 __IO uint8_t OSCCTRL_DPLLCTRLA; /* Offset: 0x00 (R/W 8) DPLL Control A */ 653 __I uint8_t Reserved1[0x03]; 654 __IO uint32_t OSCCTRL_DPLLRATIO; /* Offset: 0x04 (R/W 32) DPLL Ratio Control */ 655 __IO uint32_t OSCCTRL_DPLLCTRLB; /* Offset: 0x08 (R/W 32) DPLL Control B */ 656 __I uint32_t OSCCTRL_DPLLSYNCBUSY; /* Offset: 0x0C (R/ 32) DPLL Synchronization Busy */ 657 __I uint32_t OSCCTRL_DPLLSTATUS; /* Offset: 0x10 (R/ 32) DPLL Status */ 658 } oscctrl_dpll_registers_t; 659 660 #define OSCCTRL_DPLL_NUMBER 2 661 662 /* OSCCTRL register API structure */ 663 typedef struct 664 { /* Oscillators Control */ 665 __IO uint8_t OSCCTRL_EVCTRL; /* Offset: 0x00 (R/W 8) Event Control */ 666 __I uint8_t Reserved1[0x03]; 667 __IO uint32_t OSCCTRL_INTENCLR; /* Offset: 0x04 (R/W 32) Interrupt Enable Clear */ 668 __IO uint32_t OSCCTRL_INTENSET; /* Offset: 0x08 (R/W 32) Interrupt Enable Set */ 669 __IO uint32_t OSCCTRL_INTFLAG; /* Offset: 0x0C (R/W 32) Interrupt Flag Status and Clear */ 670 __I uint32_t OSCCTRL_STATUS; /* Offset: 0x10 (R/ 32) Status */ 671 __IO uint32_t OSCCTRL_XOSCCTRL[2]; /* Offset: 0x14 (R/W 32) External Multipurpose Crystal Oscillator Control */ 672 __IO uint8_t OSCCTRL_DFLLCTRLA; /* Offset: 0x1C (R/W 8) DFLL48M Control A */ 673 __I uint8_t Reserved2[0x03]; 674 __IO uint8_t OSCCTRL_DFLLCTRLB; /* Offset: 0x20 (R/W 8) DFLL48M Control B */ 675 __I uint8_t Reserved3[0x03]; 676 __IO uint32_t OSCCTRL_DFLLVAL; /* Offset: 0x24 (R/W 32) DFLL48M Value */ 677 __IO uint32_t OSCCTRL_DFLLMUL; /* Offset: 0x28 (R/W 32) DFLL48M Multiplier */ 678 __IO uint8_t OSCCTRL_DFLLSYNC; /* Offset: 0x2C (R/W 8) DFLL48M Synchronization */ 679 __I uint8_t Reserved4[0x03]; 680 oscctrl_dpll_registers_t DPLL[OSCCTRL_DPLL_NUMBER]; /* Offset: 0x30 */ 681 } oscctrl_registers_t; 682 683 684 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 685 #endif /* _PIC32CXSG41_OSCCTRL_COMPONENT_H_ */ 686
